From 07a332c856b3ee9fe26a9cd47ea6005f9d579810 Mon Sep 17 00:00:00 2001 From: Thomas Bauereiss Date: Tue, 18 Dec 2018 14:59:59 +0000 Subject: Check more carefully for recursive functions when generating Lem Annotating non-recursive functions as recursive in Lem output is allowed, but will make Lem use "fun"/"function" commands when generating Isabelle output, which is much slower to process than "definiton". --- src/pretty_print_lem.ml | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/src/pretty_print_lem.ml b/src/pretty_print_lem.ml index 9d169108..5c67f93a 100644 --- a/src/pretty_print_lem.ml +++ b/src/pretty_print_lem.ml @@ -1267,10 +1267,6 @@ let rec untuple_args_pat (P_aux (paux, ((l, _) as annot)) as pat) arg_typs = | _, _ -> [pat], identity -let doc_rec_lem force_rec (Rec_aux(r,_)) = match r with - | Rec_nonrec when not force_rec -> space - | _ -> space ^^ string "rec" ^^ space - let doc_tannot_opt_lem (Typ_annot_opt_aux(t,_)) = match t with | Typ_annot_opt_some(tq,typ) -> (*doc_typquant_lem tq*) (doc_typ_lem typ) | Typ_annot_opt_none -> empty @@ -1324,9 +1320,19 @@ let doc_mutrec_lem = function let rec doc_fundef_lem (FD_aux(FD_function(r, typa, efa, fcls),fannot) as fd) = match fcls with | [] -> failwith "FD_function with empty function list" - | FCL_aux (FCL_Funcl(id,_),annot) :: _ - when not (Env.is_extern id (env_of_annot annot) "lem") -> - string "let" ^^ (doc_rec_lem (List.length fcls > 1) r) ^^ (doc_fundef_rhs_lem fd) + | FCL_aux (FCL_Funcl(id, pexp),annot) :: _ + when not (Env.is_extern id (env_of_annot annot) "lem") -> + (* Output "rec" modifier if function calls itself. Mutually recursive + functions are handled separately by doc_mutrec_lem. *) + let is_funcl_rec = + fold_pexp + { (pure_exp_alg false (||)) with + e_app = (fun (id', args) -> List.fold_left (||) (Id.compare id id' = 0) args); + e_app_infix = (fun (l, id', r) -> l || (Id.compare id id' = 0) || r) } + pexp + in + let doc_rec = if is_funcl_rec then [string "rec"] else [] in + separate space ([string "let"] @ doc_rec @ [doc_fundef_rhs_lem fd]) | _ -> empty -- cgit v1.2.3 From 66b55de7e24ab546aff3eba17d21b86d47306a6d Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Tue, 18 Dec 2018 10:30:27 +0000 Subject: Coq: handle existentials in hypotheses during solving, add max_nat, better casts --- lib/coq/Sail2_values.v | 9 +++++++++ src/pretty_print_coq.ml | 6 +++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/lib/coq/Sail2_values.v b/lib/coq/Sail2_values.v index 37e75961..b7e9bbc9 100644 --- a/lib/coq/Sail2_values.v +++ b/lib/coq/Sail2_values.v @@ -1125,6 +1125,10 @@ repeat end. *) +(* The linear solver doesn't like existentials. *) +Ltac destruct_exists := + repeat match goal with H:@ex Z _ |- _ => destruct H end. + Ltac prepare_for_solver := (*dump_context;*) clear_irrelevant_defns; @@ -1134,6 +1138,7 @@ Ltac prepare_for_solver := extract_properties; repeat match goal with w:mword ?n |- _ => apply ArithFact_mword in w end; unwrap_ArithFacts; + destruct_exists; unbool_comparisons; unfold_In; (* after unbool_comparisons to deal with && and || *) reduce_list_lengths; @@ -1798,3 +1803,7 @@ Definition sub_nat (x : Z) `{ArithFact (x >= 0)} (y : Z) `{ArithFact (y >= 0)} : Definition min_nat (x : Z) `{ArithFact (x >= 0)} (y : Z) `{ArithFact (y >= 0)} : {z : Z & ArithFact (z >= 0)} := build_ex (Z.min x y). + +Definition max_nat (x : Z) `{ArithFact (x >= 0)} (y : Z) `{ArithFact (y >= 0)} : + {z : Z & ArithFact (z >= 0)} := + build_ex (Z.max x y). diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml index 18e288dd..4f6a0dfc 100644 --- a/src/pretty_print_coq.ml +++ b/src/pretty_print_coq.ml @@ -1383,7 +1383,11 @@ let doc_exp, doc_let = if effects then if inner_ex then if cast_ex - then string "derive_m" ^^ space ^^ epp + (* If the types are the same use the cast as a hint to Coq, + otherwise derive the new type from the old one. *) + then if alpha_equivalent env inner_typ cast_typ + then epp + else string "derive_m" ^^ space ^^ epp else string "projT1_m" ^^ space ^^ epp else if cast_ex then string "build_ex_m" ^^ space ^^ epp -- cgit v1.2.3 From 502e0010ae4dfe24dde9dba0174d62540f9fc993 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Wed, 19 Dec 2018 11:17:15 +0000 Subject: Coq: add zeros library function (used by MIPS) --- lib/coq/Sail2_operators_mwords.v | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/lib/coq/Sail2_operators_mwords.v b/lib/coq/Sail2_operators_mwords.v index e37e9d26..809f9d89 100644 --- a/lib/coq/Sail2_operators_mwords.v +++ b/lib/coq/Sail2_operators_mwords.v @@ -172,6 +172,13 @@ Definition zero_extend {a} (v : mword a) (n : Z) `{ArithFact (n >= a)} : mword n Definition sign_extend {a} (v : mword a) (n : Z) `{ArithFact (n >= a)} : mword n := exts_vec n v. +Definition zeros (n : Z) `{ArithFact (n >= 0)} : mword n. +refine (cast_to_mword (Word.wzero (Z.to_nat n)) _). +unwrap_ArithFacts. +apply Z2Nat.id. +auto with zarith. +Defined. + Lemma truncate_eq {m n} : m >= 0 -> m <= n -> (Z.to_nat n = Z.to_nat m + (Z.to_nat n - Z.to_nat m))%nat. intros. assert ((Z.to_nat m <= Z.to_nat n)%nat). -- cgit v1.2.3 From 7524c25b16a4e393a17acde8b20f6a42d30d0f94 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Wed, 19 Dec 2018 17:54:23 +0000 Subject: Coq: handle pairs of ranges (and other existential types) properly (Needed for current CHERI.) --- src/pretty_print_coq.ml | 20 +++++++++++++++++--- test/coq/pass/rangepair.sail | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 3 deletions(-) create mode 100644 test/coq/pass/rangepair.sail diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml index 4f6a0dfc..9bbe056b 100644 --- a/src/pretty_print_coq.ml +++ b/src/pretty_print_coq.ml @@ -65,6 +65,20 @@ let opt_debug_on : string list ref = ref [] * PPrint-based sail-to-coq pprinter ****************************************************************************) +(* Data representation: + * + * In pure computations we keep values with top level existential types + * (including ranges and nats) separate from the proofs of the accompanying + * constraints, which keeps the terms shorter and more manageable. + * Existentials embedded in types (e.g., in tuples or datatypes) are dependent + * pairs. + * + * Monadic values always includes the proof in a dependent pair because the + * constraint solving tactic won't see the term that defined the value, and + * must rely entirely on the type (like the Sail type checker). + *) + + type context = { early_ret : bool; kid_renames : kid KBindings.t; (* Plain tyvar -> tyvar renames *) @@ -761,9 +775,9 @@ let rec doc_pat ctxt apat_needed exists_as_pairs (P_aux (p,(l,annot)) as pat, ty | _ -> raise (Reporting.err_unreachable l __POS__ "tuple pattern doesn't have tuple type") in (match pats, typs with - | [p], [typ'] -> doc_pat ctxt apat_needed exists_as_pairs (p, typ') + | [p], [typ'] -> doc_pat ctxt apat_needed true (p, typ') | [_], _ -> raise (Reporting.err_unreachable l __POS__ "tuple pattern length does not match tuple type length") - | _ -> parens (separate_map comma_sp (doc_pat ctxt false exists_as_pairs) (List.combine pats typs))) + | _ -> parens (separate_map comma_sp (doc_pat ctxt false true) (List.combine pats typs))) | P_list pats -> let el_typ = match typ with | Typ_aux (Typ_app (f, [A_aux (A_typ el_typ,_)]),_) @@ -1413,7 +1427,7 @@ let doc_exp, doc_let = in if aexp_needed then parens epp else epp | E_tuple exps -> - parens (align (group (separate_map (comma ^^ break 1) expN exps))) + construct_dep_pairs (env_of_annot (l,annot)) true full_exp (general_typ_of full_exp) | E_record fexps -> let recordtyp = match destruct_tannot annot with | Some (env, Typ_aux (Typ_id tid,_), _) diff --git a/test/coq/pass/rangepair.sail b/test/coq/pass/rangepair.sail new file mode 100644 index 00000000..ce08ee4a --- /dev/null +++ b/test/coq/pass/rangepair.sail @@ -0,0 +1,33 @@ +/* Check that tuples of values that should be accompanied by a Coq proof are + handled properly. */ + +$include + +/* Monadic version */ + +val getpair_eff : unit -> (range(1,2),range(3,4)) effect {escape} + +function getpair_eff () = { + assert(true); + return (2,3) +} + +val test_eff : unit -> range (4,6) effect {escape} + +function test_eff () = + let (x,y) = getpair_eff() in + x + y + +/* Pure version */ + +val getpair : unit -> (range(1,2),range(3,4)) + +function getpair () = { + return (2,3) +} + +val test : unit -> range (4,6) + +function test () = + let (x,y) = getpair() in + x + y -- cgit v1.2.3 From d99dd3833e8ebf89c586cc5316582a3c62ad7997 Mon Sep 17 00:00:00 2001 From: Robert Norton Date: Thu, 20 Dec 2018 13:49:39 +0000 Subject: RISVC model is now at https://github.com/rems-project/sail-riscv . Remove it and tests. --- .gitignore | 19 - Makefile | 2 - README.md | 6 - riscv/.gitignore | 5 - riscv/Holmakefile | 11 - riscv/Makefile | 160 - riscv/README | 3 - riscv/ROOT | 9 - riscv/_tags | 3 - riscv/_tags.bisect | 3 - riscv/coq.patch | 335 -- riscv/gen/ast.hgen | 21 - riscv/gen/fold.hgen | 20 - riscv/gen/herdtools_ast_to_shallow_ast.hgen | 88 - riscv/gen/herdtools_types_to_shallow_types.hgen | 90 - riscv/gen/lexer.hgen | 63 - riscv/gen/lexer_regexps.hgen | 131 - riscv/gen/map.hgen | 20 - riscv/gen/parser.hgen | 76 - riscv/gen/pretty.hgen | 38 - riscv/gen/pretty_xml.hgen | 138 - riscv/gen/sail_trans_out.hgen | 25 - riscv/gen/shallow_ast_to_herdtools_ast.hgen | 25 - riscv/gen/shallow_types_to_herdtools_types.hgen | 91 - riscv/gen/token_types.hgen | 24 - riscv/gen/tokens.hgen | 20 - riscv/gen/trans_sail.hgen | 156 - riscv/gen/types.hgen | 177 - riscv/gen/types_sail_trans_out.hgen | 103 - riscv/gen/types_trans_sail.hgen | 59 - riscv/main.sail | 26 - riscv/main_rvfi.sail | 108 - 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/power/power_embed_types.lem /power/power_toFromInterp.lem -/riscv/Riscv.thy -/riscv/RiscvAuxiliary.thy -/riscv/Riscv_extras.thy -/riscv/Riscv_lemmas.thy -/riscv/Riscv_types.thy -/riscv/riscv.lem -/riscv/riscv_types.lem -/riscv/riscv_sequential.lem -/riscv/riscv_sequential_types.lem -/riscv/Riscv_sequential_lemmas.thy -/riscv/riscv -/riscv/platform -/riscv/riscv.c -/riscv/riscv_model.c -/riscv/riscv_rvfi_model.c -/riscv/riscv_c -/riscv/riscv_sim -/riscv/riscv_rvfi - /x86/x86.lem /x86/x86.ml /x86/x86_embed.lem diff --git a/Makefile b/Makefile index 40040a11..12684d91 100644 --- a/Makefile +++ b/Makefile @@ -56,8 +56,6 @@ apply_header: anon_dist: headache -c etc/headache_config -h etc/anon_header `ls mips/*.sail` headache -c etc/headache_config -h etc/anon_header `ls cheri/*.sail` - headache -c etc/headache_config -h etc/anon_header `ls riscv/*.sail` - headache -c etc/headache_config -h etc/anon_header `ls riscv/*.ml` headache -c etc/headache_config -h etc/anon_header `ls lib/*.ml` headache -c etc/headache_config -h etc/anon_header `ls lib/coq/*.v` headache -c etc/headache_config -h etc/anon_header `ls src/Makefile*` diff --git a/README.md b/README.md index d1a5bc32..f1d9aeed 100644 --- a/README.md +++ b/README.md @@ -76,14 +76,8 @@ copyright ARM Ltd. See https://github.com/meriac/archex, and the The hand-written ARMv8 model, in arm/, is distributed under the 2-clause BSD licence in the headers of those files. -The MIPS and CHERI models, in mips/ and cheri/, are distributed under -the 2-clause BSD licence in the headers of those files. - The x86 model in x86/ is distributed under the 2-clause BSD licence in the headers of those files. The POWER model in power/ is distributed under the 2-clause BSD licence in the headers of those files. - -The RISC-V model in riscv/ model is also distributed under the -2-clause BSD licence. diff --git a/riscv/.gitignore b/riscv/.gitignore deleted file mode 100644 index 52f3767a..00000000 --- a/riscv/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -riscv.lem -riscv_types.lem -riscvScript.sml -riscv_extrasScript.sml -riscv_typesScript.sml diff --git a/riscv/Holmakefile b/riscv/Holmakefile deleted file mode 100644 index 8269bc36..00000000 --- a/riscv/Holmakefile +++ /dev/null @@ -1,11 +0,0 @@ -LEMDIR=../../lem/hol-lib - -INCLUDES = $(LEMDIR) ../lib/hol - -all: riscvTheory.uo -.PHONY: all - -ifdef POLY -BASE_HEAP = ../lib/hol/sail-heap - -endif diff --git a/riscv/Makefile b/riscv/Makefile deleted file mode 100644 index 52883c21..00000000 --- a/riscv/Makefile +++ /dev/null @@ -1,160 +0,0 @@ -SAIL_SEQ_INST = riscv.sail riscv_jalr_seq.sail -SAIL_RMEM_INST = riscv.sail riscv_jalr_rmem.sail - -SAIL_SEQ_INST_SRCS = riscv_insts_begin.sail $(SAIL_SEQ_INST) riscv_insts_end.sail -SAIL_RMEM_INST_SRCS = riscv_insts_begin.sail $(SAIL_RMEM_INST) riscv_insts_end.sail - -# non-instruction sources -SAIL_OTHER_SRCS = prelude.sail riscv_types.sail riscv_sys.sail riscv_platform.sail riscv_mem.sail riscv_vmem.sail -SAIL_OTHER_RVFI_SRCS = prelude.sail rvfi_dii.sail riscv_types.sail riscv_sys.sail riscv_platform.sail riscv_mem.sail riscv_vmem.sail - -SAIL_SRCS = $(SAIL_OTHER_SRCS) $(SAIL_SEQ_INST_SRCS) riscv_step.sail riscv_analysis.sail -SAIL_RMEM_SRCS = $(SAIL_OTHER_SRCS) $(SAIL_RMEM_INST_SRCS) riscv_step.sail riscv_analysis.sail -SAIL_RVFI_SRCS = $(SAIL_OTHER_RVFI_SRCS) $(SAIL_SEQ_INST_SRCS) riscv_step.sail riscv_analysis.sail - -PLATFORM_OCAML_SRCS = platform.ml platform_impl.ml platform_main.ml -SAIL_DIR ?= $(realpath ..) -SAIL ?= $(SAIL_DIR)/sail -C_WARNINGS ?= -#-Wall -Wextra -Wno-unused-label -Wno-unused-parameter -Wno-unused-but-set-variable -Wno-unused-function -C_INCS = riscv_prelude.h riscv_platform_impl.h riscv_platform.h -C_SRCS = riscv_prelude.c riscv_platform_impl.c riscv_platform.c - -C_FLAGS = -I ../lib -C_LIBS = -lgmp -lz - -# The C simulator can be built to be linked against Spike for tandem-verification. -# This needs the C bindings to Spike from https://github.com/SRI-CSL/l3riscv -# TV_SPIKE_DIR in the environment should point to the top-level dir of the L3 -# RISC-V, containing the built C bindings to Spike. -# RISCV should be defined if TV_SPIKE_DIR is. -ifneq (,$(TV_SPIKE_DIR)) -C_FLAGS += -I $(TV_SPIKE_DIR)/src/cpp -DENABLE_SPIKE -C_LIBS += -L $(TV_SPIKE_DIR) -ltv_spike -Wl,-rpath=$(TV_SPIKE_DIR) -C_LIBS += -L $(RISCV)/lib -lfesvr -lriscv -Wl,-rpath=$(RISCV)/lib -endif - -export SAIL_DIR - -all: platform Riscv.thy - -check: $(SAIL_SRCS) main.sail Makefile - $(SAIL) $(SAIL_FLAGS) $(SAIL_SRCS) main.sail - -interpret: $(SAIL_SRCS) - $(SAIL) -i $(SAIL_FLAGS) $(SAIL_SRCS) main.sail - -cgen: $(SAIL_SRCS) - $(SAIL) -cgen $(SAIL_FLAGS) $(SAIL_SRCS) main.sail - -_sbuild/riscv.ml: $(SAIL_SRCS) Makefile main.sail - $(SAIL) $(SAIL_FLAGS) -ocaml -ocaml-nobuild -o riscv $(SAIL_SRCS) - -_sbuild/platform_main.native: _sbuild/riscv.ml _tags $(PLATFORM_OCAML_SRCS) Makefile - cp _tags $(PLATFORM_OCAML_SRCS) _sbuild - cd _sbuild && ocamlbuild -use-ocamlfind platform_main.native - -_sbuild/coverage.native: _sbuild/riscv.ml _tags.bisect $(PLATFORM_OCAML_SRCS) Makefile - cp $(PLATFORM_OCAML_SRCS) _sbuild - cp _tags.bisect _sbuild/_tags - cd _sbuild && ocamlbuild -use-ocamlfind platform_main.native && cp -L platform_main.native coverage.native - -platform: _sbuild/platform_main.native - rm -f $@ && ln -s $^ $@ - -coverage: _sbuild/coverage.native - rm -f platform && ln -s $^ platform # since the test scripts runs this file - rm -rf bisect*.out bisect coverage - ../test/riscv/run_tests.sh # this will generate bisect*.out files in this directory - mkdir bisect && mv bisect*.out bisect/ - mkdir coverage && bisect-ppx-report -html coverage/ -I _sbuild/ bisect/bisect*.out - -riscv.c: $(SAIL_SRCS) main.sail Makefile - $(SAIL) $(SAIL_FLAGS) -O -memo_z3 -c -c_include riscv_prelude.h -c_include riscv_platform.h $(SAIL_SRCS) main.sail 1> $@ - -riscv_c: riscv.c $(C_INCS) $(C_SRCS) Makefile - gcc $(C_WARNINGS) -O2 riscv.c $(C_SRCS) ../lib/*.c -lgmp -lz -I ../lib -o riscv_c - -riscv_model.c: $(SAIL_SRCS) main.sail Makefile - $(SAIL) $(SAIL_FLAGS) -O -memo_z3 -c -c_include riscv_prelude.h -c_include riscv_platform.h -c_no_main $(SAIL_SRCS) main.sail 1> $@ - -riscv_sim: riscv_model.c riscv_sim.c $(C_INCS) $(C_SRCS) $(CPP_SRCS) Makefile - gcc -g $(C_WARNINGS) $(C_FLAGS) -O2 riscv_model.c riscv_sim.c $(C_SRCS) ../lib/*.c $(C_LIBS) -o $@ - -riscv_rvfi_model.c: $(SAIL_RVFI_SRCS) main_rvfi.sail Makefile - $(SAIL) -O -memo_z3 -c -c_include riscv_prelude.h -c_include riscv_platform.h -c_no_main $(SAIL_RVFI_SRCS) main_rvfi.sail 1> $@ - -riscv_rvfi: riscv_rvfi_model.c riscv_sim.c $(C_INCS) $(C_SRCS) $(CPP_SRCS) Makefile - gcc -g $(C_WARNINGS) $(C_FLAGS) -O2 riscv_rvfi_model.c -DRVFI_DII riscv_sim.c $(C_SRCS) ../lib/*.c $(C_LIBS) -o $@ - -latex: $(SAIL_SRCS) Makefile - $(SAIL) -latex -latex_prefix sail -o sail_ltx $(SAIL_SRCS) - -tracecmp: tracecmp.ml - ocamlfind ocamlopt -annot -linkpkg -package unix $^ -o $@ - -riscv_duopod_ocaml: prelude.sail riscv_duopod.sail - $(SAIL) $(SAIL_FLAGS) -ocaml -o $@ $^ - -riscv_duopod.lem: prelude.sail riscv_duopod.sail - $(SAIL) $(SAIL_FLAGS) -lem -lem_mwords -lem_lib Riscv_extras -o riscv_duopod $^ -Riscv_duopod.thy: riscv_duopod.lem riscv_extras.lem - lem -isa -outdir . -lib Sail=../src/lem_interp -lib Sail=../src/gen_lib \ - riscv_extras.lem \ - riscv_duopod_types.lem \ - riscv_duopod.lem - -riscv_duopod: riscv_duopod_ocaml Riscv_duopod.thy - -Riscv.thy: riscv.lem riscv_extras.lem - lem -isa -outdir . -lib Sail=../src/lem_interp -lib Sail=../src/gen_lib \ - riscv_extras.lem \ - riscv_types.lem \ - riscv.lem - sed -i 's/datatype ast/datatype (plugins only: size) ast/' Riscv_types.thy - -riscv.lem: $(SAIL_SRCS) Makefile - $(SAIL) $(SAIL_FLAGS) -lem -o riscv -lem_mwords -lem_lib Riscv_extras $(SAIL_SRCS) - -riscv_sequential.lem: $(SAIL_SRCS) Makefile - $(SAIL_DIR)/sail -lem -lem_sequential -o riscv_sequential -lem_mwords -lem_lib Riscv_extras_sequential $(SAIL_SRCS) - -riscvScript.sml : riscv.lem riscv_extras.lem - lem -hol -outdir . -lib ../lib/hol -i ../lib/hol/sail2_prompt_monad.lem -i ../lib/hol/sail2_prompt.lem \ - -lib ../src/lem_interp -lib ../src/gen_lib \ - riscv_extras.lem \ - riscv_types.lem \ - riscv.lem - -riscvTheory.uo riscvTheory.ui: riscvScript.sml - Holmake riscvTheory.uo - -COQ_LIBS = -R ../../bbv/theories bbv -R ../lib/coq Sail - -riscv.v riscv_types.v: $(SAIL_SRCS) - $(SAIL) $(SAIL_FLAGS) -dcoq_undef_axioms -coq -o riscv -coq_lib riscv_extras $(SAIL_SRCS) -riscv_duopod.v riscv_duopod_types.v: prelude.sail riscv_duopod.sail - $(SAIL) $(SAIL_FLAGS) -dcoq_undef_axioms -coq -o riscv_duopod -coq_lib riscv_extras $^ -%.vo: %.v - coqc $(COQ_LIBS) $< -riscv.vo: riscv_types.vo riscv_extras.vo -riscv_duopod.vo: riscv_duopod_types.vo riscv_extras.vo - -# we exclude prelude.sail here, most code there should move to sail lib -LOC_FILES:=$(SAIL_SRCS) main.sail -include ../etc/loc.mk - -clean: - -rm -rf riscv _sbuild - -rm -f riscv.lem riscv_types.lem - -rm -f Riscv.thy Riscv_types.thy \ - Riscv_extras.thy - -rm -f Riscv_duopod.thy Riscv_duopod_types.thy riscv_duopod.lem riscv_duopod_types.lem - -rm -f riscvScript.sml riscv_typesScript.sml riscv_extrasScript.sml - -rm -f platform_main.native platform coverage.native - -rm -f riscv.vo riscv_types.vo riscv_extras.vo riscv.v riscv_types.v - -rm -f riscv_duopod.vo riscv_duopod_types.vo riscv_duopod.v riscv_duopod_types.v - -rm -f riscv.c riscv_model.c riscv_sim - -rm -f riscv_rvfi_model.c riscv_rvfi - -Holmake cleanAll - ocamlbuild -clean diff --git a/riscv/README b/riscv/README deleted file mode 100644 index 2748c897..00000000 --- a/riscv/README +++ /dev/null @@ -1,3 +0,0 @@ - -Please use the repository at -https://github.com/rems-project/sail-riscv diff --git a/riscv/ROOT b/riscv/ROOT deleted file mode 100644 index ea74bca1..00000000 --- a/riscv/ROOT +++ /dev/null @@ -1,9 +0,0 @@ -session "Sail-RISC-V" = "Sail" + - options [document = false] - theories - Riscv_lemmas - -session "Sail-RISC-V-Duopod" = "Sail" + - options [document = false] - theories - Riscv_duopod_lemmas diff --git a/riscv/_tags b/riscv/_tags deleted file mode 100644 index eab7e89a..00000000 --- a/riscv/_tags +++ /dev/null @@ -1,3 +0,0 @@ -<**/*.ml>: bin_annot, annot -<*.m{l,li}>: package(lem), package(linksem), package(zarith) -: package(lem), package(linksem), package(zarith) diff --git a/riscv/_tags.bisect b/riscv/_tags.bisect deleted file mode 100644 index d3b996f2..00000000 --- a/riscv/_tags.bisect +++ /dev/null @@ -1,3 +0,0 @@ -<**/*.ml>: bin_annot, annot -<*.m{l,li}>: package(lem), package(linksem), package(zarith), package(bisect_ppx) -: package(lem), package(linksem), package(zarith), package(bisect_ppx) diff --git a/riscv/coq.patch b/riscv/coq.patch deleted file mode 100644 index 829466e8..00000000 --- a/riscv/coq.patch +++ /dev/null @@ -1,335 +0,0 @@ ---- riscv.v.plain 2018-11-20 14:53:45.400922942 +0000 -+++ riscv.v 2018-11-20 15:08:45.661714873 +0000 -@@ -1260,6 +1260,9 @@ - let v64 : bits 64 := EXTS 64 v in - subrange_vec_dec (shift_bits_right v64 shift) 31 0. - -+Definition n_leading_spaces s : {n : Z & ArithFact (n >= 0)} := -+ build_ex (Z.of_nat (n_leading_spaces s)). -+(* - Fixpoint n_leading_spaces (s : string) - : {n : Z & ArithFact (n >= 0)} := - build_ex(let p0_ := s in -@@ -1273,7 +1276,7 @@ - (string_drop s - (build_ex 1))))))) - : {n : Z & ArithFact (n >= 0)})))) -- else 0). -+ else 0).*) - - Definition spc_forwards '(tt : unit) : string := " ". - -@@ -1284,7 +1287,7 @@ - let 'n := projT1 (n_leading_spaces s) in - let p0_ := n in - if sumbool_of_bool ((Z.eqb p0_ 0)) then None -- else Some ((tt, n)). -+ else Some ((tt, build_ex n)). - - Definition opt_spc_forwards '(tt : unit) : string := "". - -@@ -10451,14 +10454,13 @@ - returnm ((EXTZ 56 (shiftl (_get_Satp64_PPN satp64) PAGESIZE_BITS)) - : mword 56). - --Fixpoint walk39 (vaddr : mword 39) (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) (ptb : mword 56) '(existT _ level _ : {n : Z & ArithFact (n >= -- 0)}) (global : bool) -+Fixpoint walk39 (vaddr : mword 39) (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) (ptb : mword 56) (level : nat) (global : bool) - : M (PTW_Result) := - let va := Mk_SV39_Vaddr vaddr in - let pt_ofs : paddr39 := - shiftl - (EXTZ 56 -- (subrange_vec_dec (shiftr (_get_SV39_Vaddr_VPNi va) (Z.mul level SV39_LEVEL_BITS)) -+ (subrange_vec_dec (shiftr (_get_SV39_Vaddr_VPNi va) (Z.mul (Z.of_nat level) SV39_LEVEL_BITS)) - (projT1 (sub_range (build_ex SV39_LEVEL_BITS) (build_ex 1))) 0)) PTE39_LOG_SIZE in - let pte_addr := add_vec ptb pt_ofs in - (phys_mem_read Data (EXTZ 64 pte_addr) 8 false false false) >>= fun w__0 : MemoryOpResult (mword (8 * 8)) => -@@ -10471,27 +10473,27 @@ - let is_global := orb global (eq_vec (_get_PTE_Bits_G pattr) ((bool_to_bits true) : mword 1)) in - (if ((isInvalidPTE pbits)) then returnm ((PTW_Failure (PTW_Invalid_PTE)) : PTW_Result ) - else if ((isPTEPtr pbits)) then -- (if sumbool_of_bool ((Z.eqb level 0)) then -+ (match level with O => - returnm ((PTW_Failure - (PTW_Invalid_PTE)) - : PTW_Result ) -- else -+ | S level' => - (walk39 vaddr ac priv mxr do_sum - (EXTZ 56 (shiftl (_get_SV39_PTE_PPNi pte) PAGESIZE_BITS)) -- (build_ex (projT1 (sub_range (build_ex level) (build_ex 1)))) is_global) -- : M (PTW_Result)) -+ level' is_global) -+ : M (PTW_Result) end) - : M (PTW_Result) - else - (checkPTEPermission ac priv mxr do_sum pattr) >>= fun w__3 : bool => - returnm ((if ((negb w__3)) then PTW_Failure (PTW_No_Permission) -- else if sumbool_of_bool ((Z.gtb level 0)) then -+ else if sumbool_of_bool (Nat.ltb O level) then - let mask := - sub_vec_int - (shiftl - (xor_vec (_get_SV39_PTE_PPNi pte) - (xor_vec (_get_SV39_PTE_PPNi pte) - (EXTZ 44 (vec_of_bits [B1] : mword 1)))) -- (Z.mul level SV39_LEVEL_BITS)) 1 in -+ (Z.mul (Z.of_nat level) SV39_LEVEL_BITS)) 1 in - if ((neq_vec (and_vec (_get_SV39_PTE_PPNi pte) mask) - (EXTZ 44 (vec_of_bits [B0] : mword 1)))) then - PTW_Failure -@@ -10501,10 +10503,10 @@ - or_vec (_get_SV39_PTE_PPNi pte) - (and_vec (EXTZ 44 (_get_SV39_Vaddr_VPNi va)) mask) in - PTW_Success -- ((concat_vec ppn (_get_SV39_Vaddr_PgOfs va), pte, pte_addr, build_ex level, is_global)) -+ ((concat_vec ppn (_get_SV39_Vaddr_PgOfs va), pte, pte_addr, build_ex (Z.of_nat level), is_global)) - else - PTW_Success -- ((concat_vec (_get_SV39_PTE_PPNi pte) (_get_SV39_Vaddr_PgOfs va), pte, pte_addr, build_ex level, is_global))) -+ ((concat_vec (_get_SV39_PTE_PPNi pte) (_get_SV39_Vaddr_PgOfs va), pte, pte_addr, build_ex (Z.of_nat level), is_global))) - : PTW_Result)) - : M (PTW_Result) - end) -@@ -10630,7 +10632,7 @@ - : M (TR39_Result) - | None => - (curPTB39 tt) >>= fun w__6 : mword 56 => -- (walk39 vAddr ac priv mxr do_sum w__6 (build_ex level) false) >>= fun w__7 : PTW_Result => -+ (walk39 vAddr ac priv mxr do_sum w__6 (Z.to_nat level) false) >>= fun w__7 : PTW_Result => - (match w__7 with - | PTW_Failure (f) => returnm ((TR39_Failure (f)) : TR39_Result ) - | PTW_Success (pAddr,pte,pteAddr,(existT _ level _),global) => -@@ -14670,138 +14672,144 @@ - returnm (true - : bool). - --Fixpoint execute (merge_var : ast) --: M (bool) := -- match merge_var with -+Definition expand_ast (i : ast) : ast := -+match i with - | C_ADDI4SPN (rdc,nzimm) => - let imm : bits 12 := - concat_vec (vec_of_bits [B0;B0] : mword 2) - (concat_vec nzimm (vec_of_bits [B0;B0] : mword 2)) in - let rd := creg2reg_bits rdc in -- (execute (ITYPE ((imm, sp, rd, RISCV_ADDI)))) -- : M (bool) -+ ((ITYPE ((imm, sp, rd, RISCV_ADDI)))) -+ - | C_LW (uimm,rsc,rdc) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in - let rd := creg2reg_bits rdc in - let rs := creg2reg_bits rsc in -- (execute (LOAD ((imm, rs, rd, false, WORD, false, false)))) -- : M (bool) -+ ((LOAD ((imm, rs, rd, false, WORD, false, false)))) -+ - | C_LD (uimm,rsc,rdc) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in - let rd := creg2reg_bits rdc in - let rs := creg2reg_bits rsc in -- (execute (LOAD ((imm, rs, rd, false, DOUBLE, false, false)))) -- : M (bool) -+ ((LOAD ((imm, rs, rd, false, DOUBLE, false, false)))) -+ - | C_SW (uimm,rsc1,rsc2) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in - let rs1 := creg2reg_bits rsc1 in - let rs2 := creg2reg_bits rsc2 in -- (execute (STORE ((imm, rs2, rs1, WORD, false, false)))) -- : M (bool) -+ ((STORE ((imm, rs2, rs1, WORD, false, false)))) -+ - | C_SD (uimm,rsc1,rsc2) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in - let rs1 := creg2reg_bits rsc1 in - let rs2 := creg2reg_bits rsc2 in -- (execute (STORE ((imm, rs2, rs1, DOUBLE, false, false)))) -- : M (bool) -+ ((STORE ((imm, rs2, rs1, DOUBLE, false, false)))) -+ - | C_ADDI (nzi,rsd) => - let imm : bits 12 := EXTS 12 nzi in -- (execute (ITYPE ((imm, rsd, rsd, RISCV_ADDI)))) -- : M (bool) -+ ((ITYPE ((imm, rsd, rsd, RISCV_ADDI)))) -+ - | C_JAL (imm) => -- (execute (RISCV_JAL ((EXTS 21 (concat_vec imm (vec_of_bits [B0] : mword 1)), ra)))) -- : M (bool) -+ ((RISCV_JAL ((EXTS 21 (concat_vec imm (vec_of_bits [B0] : mword 1)), ra)))) -+ - | C_LI (imm,rd) => - let imm : bits 12 := EXTS 12 imm in -- (execute (ITYPE ((imm, zreg, rd, RISCV_ADDI)))) -- : M (bool) -+ ((ITYPE ((imm, zreg, rd, RISCV_ADDI)))) -+ - | C_ADDI16SP (imm) => - let imm : bits 12 := EXTS 12 (concat_vec imm (vec_of_bits [B0;B0;B0;B0] : mword 4)) in -- (execute (ITYPE ((imm, sp, sp, RISCV_ADDI)))) -- : M (bool) -+ ((ITYPE ((imm, sp, sp, RISCV_ADDI)))) -+ - | C_LUI (imm,rd) => - let res : bits 20 := EXTS 20 imm in -- (execute (UTYPE ((res, rd, RISCV_LUI)))) -- : M (bool) -+ ((UTYPE ((res, rd, RISCV_LUI)))) -+ - | C_SRLI (shamt,rsd) => - let rsd := creg2reg_bits rsd in -- (execute (SHIFTIOP ((shamt, rsd, rsd, RISCV_SRLI)))) -- : M (bool) -+ ((SHIFTIOP ((shamt, rsd, rsd, RISCV_SRLI)))) -+ - | C_SRAI (shamt,rsd) => - let rsd := creg2reg_bits rsd in -- (execute (SHIFTIOP ((shamt, rsd, rsd, RISCV_SRAI)))) -- : M (bool) -+ ((SHIFTIOP ((shamt, rsd, rsd, RISCV_SRAI)))) -+ - | C_ANDI (imm,rsd) => - let rsd := creg2reg_bits rsd in -- (execute (ITYPE ((EXTS 12 imm, rsd, rsd, RISCV_ANDI)))) -- : M (bool) -+ ((ITYPE ((EXTS 12 imm, rsd, rsd, RISCV_ANDI)))) -+ - | C_SUB (rsd,rs2) => - let rsd := creg2reg_bits rsd in - let rs2 := creg2reg_bits rs2 in -- (execute (RTYPE ((rs2, rsd, rsd, RISCV_SUB)))) -- : M (bool) -+ ((RTYPE ((rs2, rsd, rsd, RISCV_SUB)))) -+ - | C_XOR (rsd,rs2) => - let rsd := creg2reg_bits rsd in - let rs2 := creg2reg_bits rs2 in -- (execute (RTYPE ((rs2, rsd, rsd, RISCV_XOR)))) -- : M (bool) -+ ((RTYPE ((rs2, rsd, rsd, RISCV_XOR)))) -+ - | C_OR (rsd,rs2) => - let rsd := creg2reg_bits rsd in - let rs2 := creg2reg_bits rs2 in -- (execute (RTYPE ((rs2, rsd, rsd, RISCV_OR)))) -- : M (bool) -+ ((RTYPE ((rs2, rsd, rsd, RISCV_OR)))) -+ - | C_AND (rsd,rs2) => - let rsd := creg2reg_bits rsd in - let rs2 := creg2reg_bits rs2 in -- (execute (RTYPE ((rs2, rsd, rsd, RISCV_AND)))) -- : M (bool) -+ ((RTYPE ((rs2, rsd, rsd, RISCV_AND)))) -+ - | C_SUBW (rsd,rs2) => - let rsd := creg2reg_bits rsd in - let rs2 := creg2reg_bits rs2 in -- (execute (RTYPEW ((rs2, rsd, rsd, RISCV_SUBW)))) -- : M (bool) -+ ((RTYPEW ((rs2, rsd, rsd, RISCV_SUBW)))) -+ - | C_ADDW (rsd,rs2) => - let rsd := creg2reg_bits rsd in - let rs2 := creg2reg_bits rs2 in -- (execute (RTYPEW ((rs2, rsd, rsd, RISCV_ADDW)))) -- : M (bool) -+ ((RTYPEW ((rs2, rsd, rsd, RISCV_ADDW)))) -+ - | C_J (imm) => -- (execute (RISCV_JAL ((EXTS 21 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg)))) -- : M (bool) -+ ((RISCV_JAL ((EXTS 21 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg)))) -+ - | C_BEQZ (imm,rs) => -- (execute -+ ( - (BTYPE - ((EXTS 13 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg, creg2reg_bits rs, RISCV_BEQ)))) -- : M (bool) -+ - | C_BNEZ (imm,rs) => -- (execute -+ ( - (BTYPE - ((EXTS 13 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg, creg2reg_bits rs, RISCV_BNE)))) -- : M (bool) -- | C_SLLI (shamt,rsd) => (execute (SHIFTIOP ((shamt, rsd, rsd, RISCV_SLLI)))) : M (bool) -+ -+ | C_SLLI (shamt,rsd) => ((SHIFTIOP ((shamt, rsd, rsd, RISCV_SLLI)))) - | C_LWSP (uimm,rd) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in -- (execute (LOAD ((imm, sp, rd, false, WORD, false, false)))) -- : M (bool) -+ ((LOAD ((imm, sp, rd, false, WORD, false, false)))) -+ - | C_LDSP (uimm,rd) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in -- (execute (LOAD ((imm, sp, rd, false, DOUBLE, false, false)))) -- : M (bool) -+ ((LOAD ((imm, sp, rd, false, DOUBLE, false, false)))) -+ - | C_SWSP (uimm,rs2) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in -- (execute (STORE ((imm, rs2, sp, WORD, false, false)))) -- : M (bool) -+ ((STORE ((imm, rs2, sp, WORD, false, false)))) -+ - | C_SDSP (uimm,rs2) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in -- (execute (STORE ((imm, rs2, sp, DOUBLE, false, false)))) -- : M (bool) -+ ((STORE ((imm, rs2, sp, DOUBLE, false, false)))) -+ - | C_JR (rs1) => -- (execute (RISCV_JALR ((EXTZ 12 (vec_of_bits [B0] : mword 1), rs1, zreg)))) : M (bool) -+ ((RISCV_JALR ((EXTZ 12 (vec_of_bits [B0] : mword 1), rs1, zreg)))) - | C_JALR (rs1) => -- (execute (RISCV_JALR ((EXTZ 12 (vec_of_bits [B0] : mword 1), rs1, ra)))) : M (bool) -- | C_MV (rd,rs2) => (execute (RTYPE ((rs2, zreg, rd, RISCV_ADD)))) : M (bool) -- | C_EBREAK (tt) => (execute (EBREAK (tt))) : M (bool) -- | C_ADD (rsd,rs2) => (execute (RTYPE ((rs2, rsd, rsd, RISCV_ADD)))) : M (bool) -+ ((RISCV_JALR ((EXTZ 12 (vec_of_bits [B0] : mword 1), rs1, ra)))) -+ | C_MV (rd,rs2) => ((RTYPE ((rs2, zreg, rd, RISCV_ADD)))) -+ | C_EBREAK (tt) => ((EBREAK (tt))) -+ | C_ADD (rsd,rs2) => ((RTYPE ((rs2, rsd, rsd, RISCV_ADD)))) -+| i => i -+end. -+ -+Fixpoint execute (merge_var : ast) -+: M (bool) := -+let merge_var := expand_ast merge_var in -+ match merge_var with - | UTYPE (imm,rd,op) => (execute_UTYPE imm rd op) : M (bool) - | RISCV_JAL (imm,rd) => (execute_RISCV_JAL imm rd) : M (bool) - | BTYPE (imm,rs2,rs1,op) => (execute_BTYPE imm rs2 rs1 op) : M (bool) -@@ -14841,6 +14849,7 @@ - | ILLEGAL (s) => (execute_ILLEGAL s) : M (bool) - | C_ILLEGAL (s) => (execute_C_ILLEGAL s) : M (bool) - | RISCV_JALR (imm,rs1,rd) => (execute_RISCV_JALR imm rs1 rd) : M (bool) -+| _ => Fail "Unexpanded instruction" - end. - - Definition assembly_forwards (arg_ : ast) -@@ -35883,7 +35892,7 @@ - returnm (stepped - : bool). - --Definition loop '(tt : unit) -+(*Definition loop '(tt : unit) - : M (unit) := - let insns_per_tick := plat_insns_per_tick tt in - let i : Z := 0 in -@@ -35923,7 +35932,7 @@ - : M (Z)) >>= fun i : Z => - returnm (i, step_no))) >>= fun '(i, step_no) => - returnm (tt -- : unit). -+ : unit).*) - - Definition read_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 11)} - : read_kind := diff --git a/riscv/gen/ast.hgen b/riscv/gen/ast.hgen deleted file mode 100644 index 4bad813d..00000000 --- a/riscv/gen/ast.hgen +++ /dev/null @@ -1,21 +0,0 @@ -| `RISCVStopFetching (* this is a special instruction used by rmem to - indicate the end of a litmus thread *) -| `RISCVThreadStart (* this instruction indicates a thread creation in ELF files *) - -| `RISCVUTYPE of bit20 * reg * riscvUop -| `RISCVJAL of bit20 * reg -| `RISCVJALR of bit12 * reg * reg -| `RISCVBType of bit12 * reg * reg * riscvBop -| `RISCVIType of bit12 * reg * reg * riscvIop -| `RISCVShiftIop of bit6 * reg * reg * riscvSop -| `RISCVRType of reg * reg * reg * riscvRop -| `RISCVLoad of bit12 * reg * reg * bool * wordWidth * bool * bool -| `RISCVStore of bit12 * reg * reg * wordWidth * bool * bool -| `RISCVADDIW of bit12 * reg * reg -| `RISCVSHIFTW of bit5 * reg * reg * riscvSop -| `RISCVRTYPEW of reg * reg * reg * riscvRopw -| `RISCVFENCE of riscv_fence_mode * bit4 * bit4 -| `RISCVFENCEI -| `RISCVLoadRes of bool * bool * reg * wordWidth * reg -| `RISCVStoreCon of bool * bool * reg * reg * wordWidth * reg -| `RISCVAMO of riscvAmoop * bool * bool * reg * reg * wordWidth * reg diff --git a/riscv/gen/fold.hgen b/riscv/gen/fold.hgen deleted file mode 100644 index a47aa246..00000000 --- a/riscv/gen/fold.hgen +++ /dev/null @@ -1,20 +0,0 @@ -| `RISCVThreadStart -> (y_reg, y_sreg) -| `RISCVStopFetching -> (y_reg, y_sreg) - -| `RISCVUTYPE (_, r0, _) -> fold_reg r0 (y_reg, y_sreg) -| `RISCVJAL (_, r0) -> fold_reg r0 (y_reg, y_sreg) -| `RISCVJALR (_, r0, r1) -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg)) -| `RISCVBType (_, r0, r1, _) -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg)) -| `RISCVIType (_, r0, r1, _) -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg)) -| `RISCVShiftIop (_, r0, r1, _) -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg)) -| `RISCVRType (r0, r1, r2, _) -> fold_reg r0 (fold_reg r1 (fold_reg r2 (y_reg, y_sreg))) -| `RISCVLoad (_, r0, r1, _, _, _, _) -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg)) -| `RISCVStore (_, r0, r1, _, _, _) -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg)) -| `RISCVADDIW (_, r0, r1) -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg)) -| `RISCVSHIFTW (_, r0, r1, _) -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg)) -| `RISCVRTYPEW (r0, r1, r2, _) -> fold_reg r0 (fold_reg r1 (fold_reg r2 (y_reg, y_sreg))) -| `RISCVFENCE (_, _, _) -> (y_reg, y_sreg) -| `RISCVFENCEI -> (y_reg, y_sreg) -| `RISCVLoadRes (_, _, rs1, _, rd) -> fold_reg rs1 (fold_reg rd (y_reg, y_sreg)) -| `RISCVStoreCon (_, _, rs2, rs1, _, rd) -> fold_reg rs2 (fold_reg rs1 (fold_reg rd (y_reg, y_sreg))) -| `RISCVAMO (_, _, _, rs2, rs1, _, rd) -> fold_reg rs2 (fold_reg rs1 (fold_reg rd (y_reg, y_sreg))) diff --git a/riscv/gen/herdtools_ast_to_shallow_ast.hgen b/riscv/gen/herdtools_ast_to_shallow_ast.hgen deleted file mode 100644 index f36949f7..00000000 --- a/riscv/gen/herdtools_ast_to_shallow_ast.hgen +++ /dev/null @@ -1,88 +0,0 @@ -| `RISCVThreadStart -> THREAD_START() -| `RISCVStopFetching -> STOP_FETCHING() - -| `RISCVUTYPE(imm, rd, op) -> UTYPE( - translate_imm20 "imm" imm, - translate_reg "rd" rd, - translate_uop op) -| `RISCVJAL(imm, rd) -> RISCV_JAL( - translate_imm21 "imm" imm, - translate_reg "rd" rd) -| `RISCVJALR(imm, rs, rd) -> RISCV_JALR( - translate_imm12 "imm" imm, - translate_reg "rs" rd, - translate_reg "rd" rd) -| `RISCVBType(imm, rs2, rs1, op) -> BTYPE( - translate_imm13 "imm" imm, - translate_reg "rs2" rs2, - translate_reg "rs1" rs1, - translate_bop op) -| `RISCVIType(imm, rs1, rd, op) -> ITYPE( - translate_imm12 "imm" imm, - translate_reg "rs1" rs1, - translate_reg "rd" rd, - translate_iop op) -| `RISCVShiftIop(imm, rs, rd, op) -> SHIFTIOP( - translate_imm6 "imm" imm, - translate_reg "rs" rs, - translate_reg "rd" rd, - translate_sop op) -| `RISCVRType (rs2, rs1, rd, op) -> RTYPE ( - translate_reg "rs2" rs2, - translate_reg "rs1" rs1, - translate_reg "rd" rd, - translate_rop op) -| `RISCVLoad(imm, rs, rd, unsigned, width, aq, rl) -> LOAD( - translate_imm12 "imm" imm, - translate_reg "rs" rs, - translate_reg "rd" rd, - translate_bool "unsigned" unsigned, - translate_wordWidth width, - translate_bool "aq" aq, - translate_bool "rl" rl) -| `RISCVStore(imm, rs, rd, width, aq, rl) -> STORE ( - translate_imm12 "imm" imm, - translate_reg "rs" rs, - translate_reg "rd" rd, - translate_wordWidth width, - translate_bool "aq" aq, - translate_bool "rl" rl) -| `RISCVADDIW(imm, rs, rd) -> ADDIW( - translate_imm12 "imm" imm, - translate_reg "rs" rs, - translate_reg "rd" rd) -| `RISCVSHIFTW(imm, rs, rd, op) -> SHIFTW( - translate_imm5 "imm" imm, - translate_reg "rs" rs, - translate_reg "rd" rd, - translate_sop op) -| `RISCVRTYPEW(rs2, rs1, rd, op) -> RTYPEW( - translate_reg "rs2" rs2, - translate_reg "rs1" rs1, - translate_reg "rd" rd, - translate_ropw op) -| `RISCVFENCE(mode, pred, succ) -> FENCE( - translate_imm4 "pred" pred, - translate_imm4 "succ" succ) -| `RISCVFENCEI -> FENCEI () -| `RISCVLoadRes(aq, rl, rs1, width, rd) -> LOADRES( - translate_bool "aq" aq, - translate_bool "rl" rl, - translate_reg "rs1" rs1, - translate_wordWidth width, - translate_reg "rd" rd) -| `RISCVStoreCon(aq, rl, rs2, rs1, width, rd) -> STORECON( - translate_bool "aq" aq, - translate_bool "rl" rl, - translate_reg "rs2" rs2, - translate_reg "rs1" rs1, - translate_wordWidth width, - translate_reg "rd" rd) -| `RISCVAMO (op, aq, rl, rs2, rs1, width, rd) -> AMO( - translate_amoop op, - translate_bool "aq" aq, - translate_bool "rl" rl, - translate_reg "rs2" rs2, - translate_reg "rs1" rs1, - translate_wordWidth width, - translate_reg "rd" rd) diff --git a/riscv/gen/herdtools_types_to_shallow_types.hgen b/riscv/gen/herdtools_types_to_shallow_types.hgen deleted file mode 100644 index 8bd311b2..00000000 --- a/riscv/gen/herdtools_types_to_shallow_types.hgen +++ /dev/null @@ -1,90 +0,0 @@ -let is_inc = false - -let translate_reg name value = - Lem_machine_word.wordFromInteger Lem_machine_word.instance_Machine_word_Size_Machine_word_ty5_dict (Nat_big_num.of_int (reg_to_int value)) - -let translate_uop op = match op with - | RISCVLUI -> RISCV_LUI - | RISCVAUIPC -> RISCV_AUIPC - -let translate_bop op = match op with - | RISCVBEQ -> RISCV_BEQ - | RISCVBNE -> RISCV_BNE - | RISCVBLT -> RISCV_BLT - | RISCVBGE -> RISCV_BGE - | RISCVBLTU -> RISCV_BLTU - | RISCVBGEU -> RISCV_BGEU - -let translate_iop op = match op with - | RISCVADDI -> RISCV_ADDI - | RISCVSLTI -> RISCV_SLTI - | RISCVSLTIU -> RISCV_SLTIU - | RISCVXORI -> RISCV_XORI - | RISCVORI -> RISCV_ORI - | RISCVANDI -> RISCV_ANDI - -let translate_sop op = match op with - | RISCVSLLI -> RISCV_SLLI - | RISCVSRLI -> RISCV_SRLI - | RISCVSRAI -> RISCV_SRAI - -let translate_rop op = match op with - | RISCVADD -> RISCV_ADD - | RISCVSUB -> RISCV_SUB - | RISCVSLL -> RISCV_SLL - | RISCVSLT -> RISCV_SLT - | RISCVSLTU -> RISCV_SLTU - | RISCVXOR -> RISCV_XOR - | RISCVSRL -> RISCV_SRL - | RISCVSRA -> RISCV_SRA - | RISCVOR -> RISCV_OR - | RISCVAND -> RISCV_AND - -let translate_ropw op = match op with - | RISCVADDW -> RISCV_ADDW - | RISCVSUBW -> RISCV_SUBW - | RISCVSLLW -> RISCV_SLLW - | RISCVSRLW -> RISCV_SRLW - | RISCVSRAW -> RISCV_SRAW - -let translate_amoop op = match op with - | RISCVAMOSWAP -> AMOSWAP - | RISCVAMOADD -> AMOADD - | RISCVAMOXOR -> AMOXOR - | RISCVAMOAND -> AMOAND - | RISCVAMOOR -> AMOOR - | RISCVAMOMIN -> AMOMIN - | RISCVAMOMAX -> AMOMAX - | RISCVAMOMINU -> AMOMINU - | RISCVAMOMAXU -> AMOMAXU - -let translate_wordWidth op = match op with - | RISCVBYTE -> BYTE - | RISCVHALF -> HALF - | RISCVWORD -> WORD - | RISCVDOUBLE -> DOUBLE - -let translate_bool name b = b (* function - * | true -> trueSail2_values.B10 - * | false -> false Sail2_values.B00 *) - -let translate_imm21 name value = - Lem_machine_word.wordFromInteger Lem_machine_word.instance_Machine_word_Size_Machine_word_ty21_dict (Nat_big_num.of_int value) - -let translate_imm20 name value = - Lem_machine_word.wordFromInteger Lem_machine_word.instance_Machine_word_Size_Machine_word_ty20_dict (Nat_big_num.of_int value) - -let translate_imm13 name value = - Lem_machine_word.wordFromInteger Lem_machine_word.instance_Machine_word_Size_Machine_word_ty13_dict (Nat_big_num.of_int value) - -let translate_imm12 name value = - Lem_machine_word.wordFromInteger Lem_machine_word.instance_Machine_word_Size_Machine_word_ty12_dict (Nat_big_num.of_int value) - -let translate_imm6 name value = - Lem_machine_word.wordFromInteger Lem_machine_word.instance_Machine_word_Size_Machine_word_ty6_dict (Nat_big_num.of_int value) - -let translate_imm5 name value = - Lem_machine_word.wordFromInteger Lem_machine_word.instance_Machine_word_Size_Machine_word_ty5_dict (Nat_big_num.of_int value) - -let translate_imm4 name value = - Lem_machine_word.wordFromInteger Lem_machine_word.instance_Machine_word_Size_Machine_word_ty4_dict (Nat_big_num.of_int value) diff --git a/riscv/gen/lexer.hgen b/riscv/gen/lexer.hgen deleted file mode 100644 index 9009f333..00000000 --- a/riscv/gen/lexer.hgen +++ /dev/null @@ -1,63 +0,0 @@ -(** RV32I (and RV64I) ***********************************************) -"lui" , UTYPE { op=RISCVLUI }; -"auipc" , UTYPE { op=RISCVAUIPC }; - -"jal", JAL (); -"jalr", JALR (); - -"beq", BTYPE {op=RISCVBEQ}; -"bne", BTYPE {op=RISCVBNE}; -"blt", BTYPE {op=RISCVBLT}; -"bge", BTYPE {op=RISCVBGE}; -"bltu", BTYPE {op=RISCVBLTU}; -"bgeu", BTYPE {op=RISCVBGEU}; - -"addi", ITYPE {op=RISCVADDI}; -"stli", ITYPE {op=RISCVSLTI}; -"sltiu", ITYPE {op=RISCVSLTIU}; -"xori", ITYPE {op=RISCVXORI}; -"ori", ITYPE {op=RISCVORI}; -"andi", ITYPE {op=RISCVANDI}; - -"add", RTYPE {op=RISCVADD}; -"sub", RTYPE {op=RISCVSUB}; -"sll", RTYPE {op=RISCVSLL}; -"slt", RTYPE {op=RISCVSLT}; -"sltu", RTYPE {op=RISCVSLT}; -"xor", RTYPE {op=RISCVXOR}; -"srl", RTYPE {op=RISCVSRL}; -"sra", RTYPE {op=RISCVSRA}; -"or", RTYPE {op=RISCVOR}; -"and", RTYPE {op=RISCVAND}; - -"fence", FENCE (); -"fence.tso", FENCETSO (); -"fence.i", FENCEI (); - -(** RV64I (in addition to RV32I) ************************************) - -"addiw", ADDIW (); - -"addw", RTYPEW {op=RISCVADDW}; -"subw", RTYPEW {op=RISCVSUBW}; -"sllw", RTYPEW {op=RISCVSLLW}; -"srlw", RTYPEW {op=RISCVSRLW}; -"sraw", RTYPEW {op=RISCVSRAW}; - -"slli", SHIFTIOP {op=RISCVSLLI}; -"srli", SHIFTIOP {op=RISCVSRLI}; -"srai", SHIFTIOP {op=RISCVSRAI}; - -"slliw", SHIFTW {op=RISCVSLLI}; -"srliw", SHIFTW {op=RISCVSRLI}; -"sraiw", SHIFTW {op=RISCVSRAI}; - -(** RV32A (and RV64A) ***********************************************) - -"r", FENCEOPTION Fence_R; -"w", FENCEOPTION Fence_W; -"rw", FENCEOPTION Fence_RW; - -(** pseudo instructions *********************************************) - -"li", LI () diff --git a/riscv/gen/lexer_regexps.hgen b/riscv/gen/lexer_regexps.hgen deleted file mode 100644 index b8f3ca67..00000000 --- a/riscv/gen/lexer_regexps.hgen +++ /dev/null @@ -1,131 +0,0 @@ -(** RV32I (and RV64I) ***********************************************) - -| 'l' (('b'|'h') as width) ("u"? as u) (".aq"? as aq) (".rl"? as rl) as load - { if (rl = ".rl") && not (aq = ".aq") then failwith ("'" ^ load ^ "' is not a valid instruction") else - LOAD { width = (match width with 'b' -> RISCVBYTE | 'h' -> RISCVHALF | _ -> failwith "bad width"); - unsigned = (u = "u"); - aq = (aq = ".aq"); - rl = (rl = ".rl"); - } - } - -| "lw" (".aq"? as aq) (".rl"? as rl) as load - { if (rl = ".rl") && not (aq = ".aq") then failwith ("'" ^ load ^ "' is not a valid instruction") else - LOAD { width = RISCVWORD; - unsigned = false; - aq = (aq = ".aq"); - rl = (rl = ".rl"); - } - } - -| 's' (('b'|'h'|'w') as width) (".aq"? as aq) (".rl"? as rl) as store - { if (aq = ".aq") && not (rl = ".rl") then failwith ("'" ^ store ^ "' is not a valid instruction") else - STORE { width = (match width with 'b' -> RISCVBYTE | 'h' -> RISCVHALF | 'w' -> RISCVWORD | _ -> failwith "bad width"); - aq = (aq = ".aq"); - rl = (rl = ".rl"); - } - } - -(** RV64I (in addition to RV32I) ************************************) - -| "lwu" (".aq"? as aq) (".rl"? as rl) as load - { if (rl = ".rl") && not (aq = ".aq") then failwith ("'" ^ load ^ "' is not a valid instruction") else - LOAD { width = RISCVWORD; - unsigned = true; - aq = (aq = ".aq"); - rl = (rl = ".rl"); - } - } - -| "ld" (".aq"? as aq) (".rl"? as rl) as load - { if (rl = ".rl") && not (aq = ".aq") then failwith ("'" ^ load ^ "' is not a valid instruction") else - LOAD { width = RISCVDOUBLE; - unsigned = false; - aq = (aq = ".aq"); - rl = (rl = ".rl"); - } - } - -| "sd" (".aq"? as aq) (".rl"? as rl) as store - { if (aq = ".aq") && not (rl = ".rl") then failwith ("'" ^ store ^ "' is not a valid instruction") else - STORE { width = RISCVDOUBLE; - aq = (aq = ".aq"); - rl = (rl = ".rl"); - } - } - -(** RV32A (and RV64A) ***********************************************) - -| "lr.w" (".aq"? as aq) (".rl"? as rl) as lr - { if (rl = ".rl") && not (aq = ".aq") then failwith ("'" ^ lr ^ "' is not a valid instruction") else - LOADRES { width = RISCVWORD; - aq = (aq = ".aq"); - rl = (rl = ".rl"); - } - } - -| "sc.w" (".aq"? as aq) (".rl"? as rl) as sc - { if (aq = ".aq") && not (rl = ".rl") then failwith ("'" ^ sc ^ "' is not a valid instruction") else - STORECON { width = RISCVWORD; - aq = (aq = ".aq"); - rl = (rl = ".rl"); - } - } - -| "amo" (("swap"|"add"|"and"|"or"|"xor"|"max"|"min"|"maxu"|"minu") as op) ".w" (".aq"? as aq) (".rl"? as rl) - { AMO { op = - begin match op with - | "swap" -> RISCVAMOSWAP; - | "add" -> RISCVAMOADD; - | "and" -> RISCVAMOAND; - | "or" -> RISCVAMOOR; - | "xor" -> RISCVAMOXOR; - | "max" -> RISCVAMOMAX; - | "min" -> RISCVAMOMIN; - | "maxu" -> RISCVAMOMAXU; - | "minu" -> RISCVAMOMINU; - | _ -> failwith "bad amo" - end; - width = RISCVWORD; - aq = (aq = ".aq"); - rl = (rl = ".rl"); - } - } - -(** RV64A (in addition to RV32A) ************************************) - -| "lr.d" (".aq"? as aq) (".rl"? as rl) as lr - { if (rl = ".rl") && not (aq = ".aq") then failwith ("'" ^ lr ^ "' is not a valid instruction") else - LOADRES { width = RISCVDOUBLE; - aq = (aq = ".aq"); - rl = (rl = ".rl"); - } - } - -| "sc.d" (".aq"? as aq) (".rl"? as rl) as sc - { if (aq = ".aq") && not (rl = ".rl") then failwith ("'" ^ sc ^ "' is not a valid instruction") else - STORECON { width = RISCVDOUBLE; - aq = (aq = ".aq"); - rl = (rl = ".rl"); - } - } - -| "amo" (("swap"|"add"|"and"|"or"|"xor"|"max"|"min"|"maxu"|"minu") as op) ".d" (".aq"? as aq) (".rl"? as rl) - { AMO { op = - begin match op with - | "swap" -> RISCVAMOSWAP; - | "add" -> RISCVAMOADD; - | "and" -> RISCVAMOAND; - | "or" -> RISCVAMOOR; - | "xor" -> RISCVAMOXOR; - | "max" -> RISCVAMOMAX; - | "min" -> RISCVAMOMIN; - | "maxu" -> RISCVAMOMAXU; - | "minu" -> RISCVAMOMINU; - | _ -> failwith "bad amo" - end; - width = RISCVDOUBLE; - aq = (aq = ".aq"); - rl = (rl = ".rl"); - } - } diff --git a/riscv/gen/map.hgen b/riscv/gen/map.hgen deleted file mode 100644 index 28e36e08..00000000 --- a/riscv/gen/map.hgen +++ /dev/null @@ -1,20 +0,0 @@ -| `RISCVThreadStart -> `RISCVThreadStart -| `RISCVStopFetching -> `RISCVStopFetching - -| `RISCVUTYPE (x, r0, y) -> `RISCVUTYPE (x, map_reg r0, y) -| `RISCVJAL (x, r0) -> `RISCVJAL (x, map_reg r0) -| `RISCVJALR (x, r0, r1) -> `RISCVJALR (x, map_reg r0, map_reg r1) -| `RISCVBType (x, r0, r1, y) -> `RISCVBType (x, map_reg r0, map_reg r1, y) -| `RISCVIType (x, r0, r1, y) -> `RISCVIType (x, map_reg r0, map_reg r1, y) -| `RISCVShiftIop (x, r0, r1, y) -> `RISCVShiftIop (x, map_reg r0, map_reg r1, y) -| `RISCVRType (r0, r1, r2, y) -> `RISCVRType (r0, map_reg r1, map_reg r2, y) -| `RISCVLoad (x, r0, r1, y, z, a, b) -> `RISCVLoad (x, map_reg r0, map_reg r1, y, z, a, b) -| `RISCVStore (x, r0, r1, y, z, a) -> `RISCVStore (x, map_reg r0, map_reg r1, y, z, a) -| `RISCVADDIW (x, r0, r1) -> `RISCVADDIW (x, map_reg r0, map_reg r1) -| `RISCVSHIFTW (x, r0, r1, y) -> `RISCVSHIFTW (x, map_reg r0, map_reg r1, y) -| `RISCVRTYPEW (r0, r1, r2, x) -> `RISCVRTYPEW (r0, map_reg r1, map_reg r2, x) -| `RISCVFENCE (m, p, s) -> `RISCVFENCE (m, p, s) -| `RISCVFENCEI -> `RISCVFENCEI -| `RISCVLoadRes (aq, rl, rs1, w, rd) -> `RISCVLoadRes (aq, rl, map_reg rs1, w, map_reg rd) -| `RISCVStoreCon (aq, rl, rs2, rs1, w, rd) -> `RISCVStoreCon (aq, rl, map_reg rs2, map_reg rs1, w, map_reg rd) -| `RISCVAMO (op, aq, rl, rs2, rs1, w, rd) -> `RISCVAMO (op, aq, rl, map_reg rs2, map_reg rs1, w, map_reg rd) diff --git a/riscv/gen/parser.hgen b/riscv/gen/parser.hgen deleted file mode 100644 index b0ed4b31..00000000 --- a/riscv/gen/parser.hgen +++ /dev/null @@ -1,76 +0,0 @@ -| UTYPE reg COMMA NUM - { (* it's not clear if NUM here should be before or after filling the - lowest 12 bits with zeros, or if it should be signed or unsigned; - currently assuming: NUM does not include the 12 zeros, and is unsigned *) - if not (iskbituimm 20 $4) then failwith "immediate is not 20bit" - else `RISCVUTYPE ($4, $2, $1.op) } -| JAL reg COMMA NUM - { if not ($4 mod 2 = 0) then failwith "odd offset" - else if not (iskbitsimm 21 $4) then failwith "offset is not 21bit" - else `RISCVJAL ($4, $2) } -| JALR reg COMMA reg COMMA NUM - { if not (iskbitsimm 12 $6) then failwith "offset is not 12bit" - else `RISCVJALR ($6, $4, $2) } -| BTYPE reg COMMA reg COMMA NUM - { if not ($6 mod 2 = 0) then failwith "odd offset" - else if not (iskbitsimm 13 $6) then failwith "offset is not 13bit" - else `RISCVBType ($6, $4, $2, $1.op) } -| ITYPE reg COMMA reg COMMA NUM - { if $1.op <> RISCVSLTIU && not (iskbitsimm 12 $6) then failwith "immediate is not 12bit" - else if $1.op = RISCVSLTIU && not (iskbituimm 12 $6) then failwith "unsigned immediate is not 12bit" - else `RISCVIType ($6, $4, $2, $1.op) } -| ADDIW reg COMMA reg COMMA NUM - { if not (iskbitsimm 12 $6) then failwith "immediate is not 12bit" - else `RISCVADDIW ($6, $4, $2) } -| SHIFTIOP reg COMMA reg COMMA NUM - { if not (iskbituimm 6 $6) then failwith "unsigned immediate is not 6bit" - else `RISCVShiftIop ($6, $4, $2, $1.op) } -| SHIFTW reg COMMA reg COMMA NUM - { if not (iskbituimm 5 $6) then failwith "unsigned immediate is not 5bit" - else `RISCVSHIFTW ($6, $4, $2, $1.op) } -| RTYPE reg COMMA reg COMMA reg - { `RISCVRType ($6, $4, $2, $1.op) } -| LOAD reg COMMA NUM LPAR reg RPAR - { if not (iskbitsimm 12 $4) then failwith "offset is not 12bit" - else `RISCVLoad ($4, $6, $2, $1.unsigned, $1.width, $1.aq, $1.rl) } -| STORE reg COMMA NUM LPAR reg RPAR - { if not (iskbitsimm 12 $4) then failwith "offset is not 12bit" - else `RISCVStore ($4, $2, $6, $1.width, $1.aq, $1.rl) } -| RTYPEW reg COMMA reg COMMA reg - { `RISCVRTYPEW ($6, $4, $2, $1.op) } -| FENCE FENCEOPTION COMMA FENCEOPTION - { match ($2, $4) with - | (Fence_RW, Fence_RW) -> `RISCVFENCE (RISCV_FM_NORMAL, 0b0011, 0b0011) - | (Fence_R, Fence_RW) -> `RISCVFENCE (RISCV_FM_NORMAL, 0b0010, 0b0011) - | (Fence_W, Fence_RW) -> `RISCVFENCE (RISCV_FM_NORMAL, 0b0001, 0b0011) - | (Fence_RW, Fence_R) -> `RISCVFENCE (RISCV_FM_NORMAL, 0b0011, 0b0010) - | (Fence_R, Fence_R) -> `RISCVFENCE (RISCV_FM_NORMAL, 0b0010, 0b0010) - | (Fence_W, Fence_R) -> `RISCVFENCE (RISCV_FM_NORMAL, 0b0001, 0b0010) - | (Fence_RW, Fence_W) -> `RISCVFENCE (RISCV_FM_NORMAL, 0b0011, 0b0001) - | (Fence_R, Fence_W) -> `RISCVFENCE (RISCV_FM_NORMAL, 0b0010, 0b0001) - | (Fence_W, Fence_W) -> `RISCVFENCE (RISCV_FM_NORMAL, 0b0001, 0b0001) - } -| FENCETSO - { `RISCVFENCE (RISCV_FM_TSO, 0b0011, 0b0011) } -| FENCEI - { `RISCVFENCEI } -| LOADRES reg COMMA LPAR reg RPAR - { `RISCVLoadRes ($1.aq, $1.rl, $5, $1.width, $2) } -| LOADRES reg COMMA NUM LPAR reg RPAR - { if $4 <> 0 then failwith "'lr' offset must be 0" else - `RISCVLoadRes ($1.aq, $1.rl, $6, $1.width, $2) } -| STORECON reg COMMA reg COMMA LPAR reg RPAR - { `RISCVStoreCon ($1.aq, $1.rl, $4, $7, $1.width, $2) } -| STORECON reg COMMA reg COMMA NUM LPAR reg RPAR - { if $6 <> 0 then failwith "'sc' offset must be 0" else - `RISCVStoreCon ($1.aq, $1.rl, $4, $8, $1.width, $2) } -| AMO reg COMMA reg COMMA LPAR reg RPAR - { `RISCVAMO ($1.op, $1.aq, $1.rl, $4, $7, $1.width, $2) } -| AMO reg COMMA reg COMMA NUM LPAR reg RPAR - { if $6 <> 0 then failwith "'amo' offset must be 0" else - `RISCVAMO ($1.op, $1.aq, $1.rl, $4, $8, $1.width, $2) } - -/* pseudo-ops */ -| LI reg COMMA NUM - { if not (iskbitsimm 12 $4) then failwith "immediate is not 12bit (li is currently implemented only with small immediate)" - else `RISCVIType ($4, IReg R0, $2, RISCVORI) } diff --git a/riscv/gen/pretty.hgen b/riscv/gen/pretty.hgen deleted file mode 100644 index a283b7e4..00000000 --- a/riscv/gen/pretty.hgen +++ /dev/null @@ -1,38 +0,0 @@ -| `RISCVThreadStart -> "start" -| `RISCVStopFetching -> "stop" - -| `RISCVUTYPE(imm, rd, op) -> sprintf "%s %s, %d" (pp_riscv_uop op) (pp_reg rd) imm -| `RISCVJAL(imm, rd) -> sprintf "jal %s, %d" (pp_reg rd) imm -| `RISCVJALR(imm, rs, rd) -> sprintf "jalr %s, %s, %d" (pp_reg rd) (pp_reg rs) imm -| `RISCVBType(imm, rs2, rs1, op) -> sprintf "%s %s, %s, %d" (pp_riscv_bop op) (pp_reg rs1) (pp_reg rs2) imm -| `RISCVIType(imm, rs2, rs1, op) -> sprintf "%s %s, %s, %d" (pp_riscv_iop op) (pp_reg rs1) (pp_reg rs2) imm -| `RISCVShiftIop(imm, rs, rd, op) -> sprintf "%s %s, %s, %d" (pp_riscv_sop op) (pp_reg rd) (pp_reg rs) imm -| `RISCVRType (rs2, rs1, rd, op) -> sprintf "%s %s, %s, %s" (pp_riscv_rop op) (pp_reg rd) (pp_reg rs1) (pp_reg rs2) - -| `RISCVLoad(imm, rs, rd, unsigned, width, aq, rl) -> - sprintf "%s %s, %d(%s)" (pp_riscv_load_op (unsigned, width, aq, rl)) (pp_reg rd) imm (pp_reg rs) - -| `RISCVStore(imm, rs2, rs1, width, aq, rl) -> - sprintf "%s %s, %d(%s)" (pp_riscv_store_op (width, aq, rl)) (pp_reg rs2) imm (pp_reg rs1) - -| `RISCVADDIW(imm, rs, rd) -> sprintf "addiw %s, %s, %d" (pp_reg rd) (pp_reg rs) imm -| `RISCVSHIFTW(imm, rs, rd, op) -> sprintf "%s %s, %s, %d" (pp_riscv_sop op) (pp_reg rd) (pp_reg rs) imm -| `RISCVRTYPEW(rs2, rs1, rd, op) -> sprintf "%s %s, %s, %s" (pp_riscv_ropw op) (pp_reg rd) (pp_reg rs1) (pp_reg rs2) - -| `RISCVFENCE(RISCV_FM_NORMAL, pred, succ) - -> sprintf "fence %s,%s" (pp_riscv_fence_option pred) (pp_riscv_fence_option succ) - -| `RISCVFENCE(RISCV_FM_TSO, 0b0011, 0b0011) - -> sprintf "fence.tso" -| `RISCVFENCE(RISCV_FM_TSO, _, _) -> failwith "bad fence.tso" - -| `RISCVFENCEI -> sprintf "fence.i" - -| `RISCVLoadRes(aq, rl, rs1, width, rd) -> - sprintf "%s %s, (%s)" (pp_riscv_load_reserved_op (aq, rl, width)) (pp_reg rd) (pp_reg rs1) - -| `RISCVStoreCon(aq, rl, rs2, rs1, width, rd) -> - sprintf "%s %s, %s, (%s)" (pp_riscv_store_conditional_op (aq, rl, width)) (pp_reg rd) (pp_reg rs2) (pp_reg rs1) - -| `RISCVAMO(op, aq, rl, rs2, rs1, width, rd) -> - sprintf "%s %s, %s, (%s)" (pp_riscv_amo_op (op, aq, rl, width)) (pp_reg rd) (pp_reg rs2) (pp_reg rs1) diff --git a/riscv/gen/pretty_xml.hgen b/riscv/gen/pretty_xml.hgen deleted file mode 100644 index c2c350a3..00000000 --- a/riscv/gen/pretty_xml.hgen +++ /dev/null @@ -1,138 +0,0 @@ -| `RISCVThreadStart -> ("op_thread_start", []) - -| `RISCVStopFetching -> ("op_stop_fetching", []) - -| `RISCVUTYPE(imm, rd, op) -> - ("op_U_type", - [ ("op", pp_riscv_uop op); - ("uimm", sprintf "%d" imm); - ("dest", pp_reg rd); - ]) - -| `RISCVJAL(imm, rd) -> - ("op_jal", - [ ("offset", sprintf "%d" imm); - ("dest", pp_reg rd); - ]) - -| `RISCVJALR(imm, rs1, rd) -> - ("op_jalr", - [ ("offset", sprintf "%d" imm); - ("base", pp_reg rs1); - ("dest", pp_reg rd); - ]) - -| `RISCVBType(imm, rs2, rs1, op) -> - ("op_branch", - [ ("op", pp_riscv_bop op); - ("offset", sprintf "%d" imm); - ("src2", pp_reg rs2); - ("src1", pp_reg rs1); - ]) - -| `RISCVIType(imm, rs1, rd, op) -> - ("op_I_type", - [ ("op", pp_riscv_iop op); - ("iimm", sprintf "%d" imm); - ("src", pp_reg rs1); - ("dest", pp_reg rd); - ]) - -| `RISCVShiftIop(imm, rs1, rd, op) -> - ("op_IS_type", - [ ("op", pp_riscv_sop op); - ("shamt", sprintf "%d" imm); - ("src", pp_reg rs1); - ("dest", pp_reg rd); - ]) - -| `RISCVSHIFTW(imm, rs1, rd, op) -> - ("op_ISW_type", - [ ("op", pp_riscv_sop op); - ("shamt", sprintf "%d" imm); - ("src", pp_reg rs1); - ("dest", pp_reg rd); - ]) - -| `RISCVRType (rs2, rs1, rd, op) -> - ("op_R_type", - [ ("op", pp_riscv_rop op); - ("src2", pp_reg rs2); - ("src1", pp_reg rs1); - ("dest", pp_reg rd); - ]) - -| `RISCVLoad(imm, rs1, rd, unsigned, width, aq, rl) -> - ("op_load", - [ ("aq", if aq then "true" else "false"); - ("rl", if rl then "true" else "false"); - ("width", pp_word_width width); - ("unsigned", if unsigned then "true" else "false"); - ("base", pp_reg rs1); - ("offset", sprintf "%d" imm); - ("dest", pp_reg rd); - ]) - -| `RISCVStore(imm, rs2, rs1, width, aq, rl) -> - ("op_store", - [ ("aq", if aq then "true" else "false"); - ("rl", if rl then "true" else "false"); - ("width", pp_word_width width); - ("src", pp_reg rs2); - ("base", pp_reg rs1); - ("offset", sprintf "%d" imm); - ]) - -| `RISCVADDIW(imm, rs1, rd) -> - ("op_addiw", - [ ("iimm", sprintf "%d" imm); - ("src", pp_reg rs1); - ("dest", pp_reg rd); - ]) - -| `RISCVRTYPEW(rs2, rs1, rd, op) -> - ("op_RW_type", - [ ("op", pp_riscv_ropw op); - ("src2", pp_reg rs2); - ("src1", pp_reg rs1); - ("dest", pp_reg rd); - ]) - -| `RISCVFENCE(mode, pred, succ) -> - ("op_fence", - [ ("mode", match mode with RISCV_FM_NORMAL -> "normal" | RISCV_FM_TSO -> "tso"); - ("pred", pp_riscv_fence_option pred); - ("succ", pp_riscv_fence_option succ); - ]) - -| `RISCVFENCEI -> ("op_fence_i", []) - -| `RISCVLoadRes(aq, rl, rs1, width, rd) -> - ("op_lr", - [ ("aq", if aq then "true" else "false"); - ("rl", if rl then "true" else "false"); - ("width", pp_word_width width); - ("addr", pp_reg rs1); - ("dest", pp_reg rd); - ]) - -| `RISCVStoreCon(aq, rl, rs2, rs1, width, rd) -> - ("op_sc", - [ ("aq", if aq then "true" else "false"); - ("rl", if rl then "true" else "false"); - ("width", pp_word_width width); - ("addr", pp_reg rs1); - ("src", pp_reg rs2); - ("dest", pp_reg rd); - ]) - -| `RISCVAMO(op, aq, rl, rs2, rs1, width, rd) -> - ("op_amo", - [ ("op", pp_riscv_amo_op_part op); - ("aq", if aq then "true" else "false"); - ("rl", if rl then "true" else "false"); - ("width", pp_word_width width); - ("src", pp_reg rs2); - ("addr", pp_reg rs1); - ("dest", pp_reg rd); - ]) diff --git a/riscv/gen/sail_trans_out.hgen b/riscv/gen/sail_trans_out.hgen deleted file mode 100644 index 3c252502..00000000 --- a/riscv/gen/sail_trans_out.hgen +++ /dev/null @@ -1,25 +0,0 @@ -| ("StopFetching", []) -> `RISCVStopFetching -| ("ThreadStart", []) -> `RISCVThreadStart - -| ("UTYPE", [imm; rd; op]) -> `RISCVUTYPE(translate_out_simm20 imm, translate_out_ireg rd, translate_out_uop op) -| ("JAL", [imm; rd]) -> `RISCVJAL(translate_out_simm21 imm, translate_out_ireg rd) -| ("JALR", [imm; rs; rd]) -> `RISCVJALR(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd) -| ("BTYPE", [imm; rs2; rs1; op]) -> `RISCVBType(translate_out_simm13 imm, translate_out_ireg rs2, translate_out_ireg rs1, translate_out_bop op) -| ("ITYPE", [imm; rs1; rd; op]) -> `RISCVIType(translate_out_simm12 imm, translate_out_ireg rs1, translate_out_ireg rd, translate_out_iop op) -| ("SHIFTIOP", [imm; rs; rd; op]) -> `RISCVShiftIop(translate_out_imm6 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_sop op) -| ("RTYPE", [rs2; rs1; rd; op]) -> `RISCVRType (translate_out_ireg rs2, translate_out_ireg rs1, translate_out_ireg rd, translate_out_rop op) -| ("LOAD", [imm; rs; rd; unsigned; width; aq; rl]) - -> `RISCVLoad(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_bool unsigned, translate_out_wordWidth width, translate_out_bool aq, translate_out_bool rl) -| ("STORE", [imm; rs; rd; width; aq; rl]) - -> `RISCVStore(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_wordWidth width, translate_out_bool aq, translate_out_bool rl) -| ("ADDIW", [imm; rs; rd]) -> `RISCVADDIW(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd) -| ("SHIFTW", [imm; rs; rd; op]) -> `RISCVSHIFTW(translate_out_imm5 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_sop op) -| ("RTYPEW", [rs2; rs1; rd; op]) -> `RISCVRTYPEW(translate_out_ireg rs2, translate_out_ireg rs1, translate_out_ireg rd, translate_out_ropw op) -| ("FENCE", [mode; pred; succ]) -> `RISCVFENCE(translate_out_fm_mode mode, translate_out_imm4 pred, translate_out_imm4 succ) -| ("FENCEI", []) -> `RISCVFENCEI -| ("LOADRES", [aq; rl; rs1; width; rd]) - -> `RISCVLoadRes(translate_out_bool aq, translate_out_bool rl, translate_out_ireg rs1, translate_out_wordWidth width, translate_out_ireg rd) -| ("STORECON", [aq; rl; rs2; rs1; width; rd]) - -> `RISCVStoreCon(translate_out_bool aq, translate_out_bool rl, translate_out_ireg rs2, translate_out_ireg rs1, translate_out_wordWidth width, translate_out_ireg rd) -| ("AMO", [op; aq; rl; rs2; rs1; width; rd]) - -> `RISCVAMO(translate_out_amoop op, translate_out_bool aq, translate_out_bool rl, translate_out_ireg rs2, translate_out_ireg rs1, translate_out_wordWidth width, translate_out_ireg rd) diff --git a/riscv/gen/shallow_ast_to_herdtools_ast.hgen b/riscv/gen/shallow_ast_to_herdtools_ast.hgen deleted file mode 100644 index e612f8c3..00000000 --- a/riscv/gen/shallow_ast_to_herdtools_ast.hgen +++ /dev/null @@ -1,25 +0,0 @@ -| STOP_FETCHING () -> `RISCVStopFetching -| THREAD_START () -> `RISCVThreadStart - -| UTYPE( imm, rd, op) -> `RISCVUTYPE(translate_out_simm20 imm, translate_out_ireg rd, translate_out_uop op) -| RISCV_JAL( imm, rd) -> `RISCVJAL(translate_out_simm21 imm, translate_out_ireg rd) -| RISCV_JALR( imm, rs, rd) -> `RISCVJALR(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd) -| BTYPE( imm, rs2, rs1, op) -> `RISCVBType(translate_out_simm13 imm, translate_out_ireg rs2, translate_out_ireg rs1, translate_out_bop op) -| ITYPE( imm, rs1, rd, op) -> `RISCVIType(translate_out_simm12 imm, translate_out_ireg rs1, translate_out_ireg rd, translate_out_iop op) -| SHIFTIOP( imm, rs, rd, op) -> `RISCVShiftIop(translate_out_imm6 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_sop op) -| RTYPE( rs2, rs1, rd, op) -> `RISCVRType (translate_out_ireg rs2, translate_out_ireg rs1, translate_out_ireg rd, translate_out_rop op) -| LOAD( imm, rs, rd, unsigned, width, aq, rl) - -> `RISCVLoad(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_bool unsigned, translate_out_wordWidth width, translate_out_bool aq, translate_out_bool rl) -| STORE( imm, rs, rd, width, aq, rl) - -> `RISCVStore(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_wordWidth width, translate_out_bool aq, translate_out_bool rl) -| ADDIW( imm, rs, rd) -> `RISCVADDIW(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd) -| SHIFTW( imm, rs, rd, op) -> `RISCVSHIFTW(translate_out_imm5 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_sop op) -| RTYPEW( rs2, rs1, rd, op) -> `RISCVRTYPEW(translate_out_ireg rs2, translate_out_ireg rs1, translate_out_ireg rd, translate_out_ropw op) -| FENCE( pred, succ) -> `RISCVFENCE(RISCV_FM_NORMAL, translate_out_imm4 pred, translate_out_imm4 succ) -| FENCEI () -> `RISCVFENCEI -| LOADRES( aq, rl, rs1, width, rd) - -> `RISCVLoadRes(translate_out_bool aq, translate_out_bool rl, translate_out_ireg rs1, translate_out_wordWidth width, translate_out_ireg rd) -| STORECON( aq, rl, rs2, rs1, width, rd) - -> `RISCVStoreCon(translate_out_bool aq, translate_out_bool rl, translate_out_ireg rs2, translate_out_ireg rs1, translate_out_wordWidth width, translate_out_ireg rd) -| AMO( op, aq, rl, rs2, rs1, width, rd) - -> `RISCVAMO(translate_out_amoop op, translate_out_bool aq, translate_out_bool rl, translate_out_ireg rs2, translate_out_ireg rs1, translate_out_wordWidth width, translate_out_ireg rd) diff --git a/riscv/gen/shallow_types_to_herdtools_types.hgen b/riscv/gen/shallow_types_to_herdtools_types.hgen deleted file mode 100644 index 5a659cd4..00000000 --- a/riscv/gen/shallow_types_to_herdtools_types.hgen +++ /dev/null @@ -1,91 +0,0 @@ -(* let translate_out_big_bit = Sail_values.unsigned - * - * let translate_out_int inst = (Nat_big_num.to_int (translate_out_big_bit inst)) - * let translate_out_signed_int inst bits = - * let i = (Nat_big_num.to_int (translate_out_big_bit inst)) in - * if (i >= (1 lsl (bits - 1))) then - * (i - (1 lsl bits)) else - * i *) - -let translate_out_int i = Nat_big_num.to_int (Lem.naturalFromWord i) -let translate_out_signed_int i = Nat_big_num.to_int (Lem.signedIntegerFromWord i) - -let translate_out_ireg ireg = IReg (int_to_ireg (translate_out_int ireg)) - -let translate_out_uop op = match op with - | RISCV_LUI -> RISCVLUI - | RISCV_AUIPC -> RISCVAUIPC - -let translate_out_bop op = match op with - | RISCV_BEQ -> RISCVBEQ - | RISCV_BNE -> RISCVBNE - | RISCV_BLT -> RISCVBLT - | RISCV_BGE -> RISCVBGE - | RISCV_BLTU -> RISCVBLTU - | RISCV_BGEU -> RISCVBGEU - -let translate_out_iop op = match op with - | RISCV_ADDI -> RISCVADDI - | RISCV_SLTI -> RISCVSLTI - | RISCV_SLTIU -> RISCVSLTIU - | RISCV_XORI -> RISCVXORI - | RISCV_ORI -> RISCVORI - | RISCV_ANDI -> RISCVANDI - -let translate_out_sop op = match op with - | RISCV_SLLI -> RISCVSLLI - | RISCV_SRLI -> RISCVSRLI - | RISCV_SRAI -> RISCVSRAI - -let translate_out_rop op = match op with - | RISCV_ADD -> RISCVADD - | RISCV_SUB -> RISCVSUB - | RISCV_SLL -> RISCVSLL - | RISCV_SLT -> RISCVSLT - | RISCV_SLTU -> RISCVSLTU - | RISCV_XOR -> RISCVXOR - | RISCV_SRL -> RISCVSRL - | RISCV_SRA -> RISCVSRA - | RISCV_OR -> RISCVOR - | RISCV_AND -> RISCVAND - -let translate_out_ropw op = match op with - | RISCV_ADDW -> RISCVADDW - | RISCV_SUBW -> RISCVSUBW - | RISCV_SLLW -> RISCVSLLW - | RISCV_SRLW -> RISCVSRLW - | RISCV_SRAW -> RISCVSRAW - -let translate_out_amoop op = match op with - | AMOSWAP -> RISCVAMOSWAP - | AMOADD -> RISCVAMOADD - | AMOXOR -> RISCVAMOXOR - | AMOAND -> RISCVAMOAND - | AMOOR -> RISCVAMOOR - | AMOMIN -> RISCVAMOMIN - | AMOMAX -> RISCVAMOMAX - | AMOMINU -> RISCVAMOMINU - | AMOMAXU -> RISCVAMOMAXU - -let translate_out_wordWidth op = match op with - | BYTE -> RISCVBYTE - | HALF -> RISCVHALF - | WORD -> RISCVWORD - | DOUBLE -> RISCVDOUBLE - -(* let translate_out_fm_mode = function - * | FM_NORMAL -> RISCV_FM_NORMAL - * | FM_TSO -> RISCV_FM_TSO *) - -let translate_out_bool b = b (* function - * | Sail_values.B1 -> true - * | Sail_values.B0 -> false - * | _ -> failwith "translate_out_bool Undef" *) - -let translate_out_simm21 imm = translate_out_signed_int imm (* 21 *) -let translate_out_simm20 imm = translate_out_signed_int imm (* 20 *) -let translate_out_simm13 imm = translate_out_signed_int imm (* 13 *) -let translate_out_simm12 imm = translate_out_signed_int imm (* 12 *) -let translate_out_imm6 imm = translate_out_int imm -let translate_out_imm5 imm = translate_out_int imm -let translate_out_imm4 imm = translate_out_int imm diff --git a/riscv/gen/token_types.hgen b/riscv/gen/token_types.hgen deleted file mode 100644 index 1a2895af..00000000 --- a/riscv/gen/token_types.hgen +++ /dev/null @@ -1,24 +0,0 @@ -type token_UTYPE = {op : riscvUop } -type token_JAL = unit -type token_JALR = unit -type token_BType = {op : riscvBop } -type token_IType = {op : riscvIop } -type token_ShiftIop = {op : riscvSop } -type token_RTYPE = {op : riscvRop } -type token_Load = {unsigned: bool; width : wordWidth; aq: bool; rl: bool } -type token_Store = {width : wordWidth; aq: bool; rl: bool } -type token_ADDIW = unit -type token_SHIFTW = {op : riscvSop } -type token_RTYPEW = {op : riscvRopw } -type token_FENCE = unit -type token_FENCETSO = unit -type token_FENCEI = unit -type token_LoadRes = {width : wordWidth; aq: bool; rl: bool } -type token_StoreCon = {width : wordWidth; aq: bool; rl: bool } -type token_AMO = {width : wordWidth; aq: bool; rl: bool; op: riscvAmoop } - -type token_FENCEOPTION = Fence_R | Fence_W | Fence_RW - -(* pseudo-ops *) - -type token_LI = unit diff --git a/riscv/gen/tokens.hgen b/riscv/gen/tokens.hgen deleted file mode 100644 index 37c76a2e..00000000 --- a/riscv/gen/tokens.hgen +++ /dev/null @@ -1,20 +0,0 @@ -%token UTYPE -%token JAL -%token JALR -%token BTYPE -%token ITYPE -%token SHIFTIOP -%token RTYPE -%token LOAD -%token STORE -%token ADDIW -%token SHIFTW -%token RTYPEW -%token FENCE -%token FENCEOPTION -%token FENCETSO -%token FENCEI -%token LOADRES -%token STORECON -%token AMO -%token LI diff --git a/riscv/gen/trans_sail.hgen b/riscv/gen/trans_sail.hgen deleted file mode 100644 index bff31ce8..00000000 --- a/riscv/gen/trans_sail.hgen +++ /dev/null @@ -1,156 +0,0 @@ -| `RISCVStopFetching -> ("StopFetching", [], []) -| `RISCVThreadStart -> ("ThreadStart", [], []) - -| `RISCVUTYPE(imm, rd, op) -> - ("UTYPE", - [ - translate_imm20 "imm" imm; - translate_reg "rd" rd; - translate_uop "op" op; - ], - []) -| `RISCVJAL(imm, rd) -> - ("JAL", - [ - translate_imm21 "imm" imm; - translate_reg "rd" rd; - ], - []) -| `RISCVJALR(imm, rs, rd) -> - ("JALR", - [ - translate_imm12 "imm" imm; - translate_reg "rs" rd; - translate_reg "rd" rd; - ], - []) -| `RISCVBType(imm, rs2, rs1, op) -> - ("BTYPE", - [ - translate_imm13 "imm" imm; - translate_reg "rs2" rs2; - translate_reg "rs1" rs1; - translate_bop "op" op; - ], - []) -| `RISCVIType(imm, rs1, rd, op) -> - ("ITYPE", - [ - translate_imm12 "imm" imm; - translate_reg "rs1" rs1; - translate_reg "rd" rd; - translate_iop "op" op; - ], - []) -| `RISCVShiftIop(imm, rs, rd, op) -> - ("SHIFTIOP", - [ - translate_imm6 "imm" imm; - translate_reg "rs" rs; - translate_reg "rd" rd; - translate_sop "op" op; - ], - []) -| `RISCVRType (rs2, rs1, rd, op) -> - ("RTYPE", - [ - translate_reg "rs2" rs2; - translate_reg "rs1" rs1; - translate_reg "rd" rd; - translate_rop "op" op; - ], - []) -| `RISCVLoad(imm, rs, rd, unsigned, width, aq, rl) -> - ("LOAD", - [ - translate_imm12 "imm" imm; - translate_reg "rs" rs; - translate_reg "rd" rd; - translate_bool "unsigned" unsigned; - translate_width "width" width; - translate_bool "aq" aq; - translate_bool "rl" rl; - ], - []) -| `RISCVStore(imm, rs2, rs1, width, aq, rl) -> - ("STORE", - [ - translate_imm12 "imm" imm; - translate_reg "rs2" rs2; - translate_reg "rs1" rs1; - translate_width "width" width; - translate_bool "aq" aq; - translate_bool "rl" rl; - ], - []) -| `RISCVADDIW(imm, rs, rd) -> - ("ADDIW", - [ - translate_imm12 "imm" imm; - translate_reg "rs" rs; - translate_reg "rd" rd; - ], - []) -| `RISCVSHIFTW(imm, rs, rd, op) -> - ("SHIFTW", - [ - translate_imm5 "imm" imm; - translate_reg "rs" rs; - translate_reg "rd" rd; - translate_sop "op" op; - ], - []) -| `RISCVRTYPEW(rs2, rs1, rd, op) -> - ("RTYPEW", - [ - translate_reg "rs2" rs2; - translate_reg "rs1" rs1; - translate_reg "rd" rd; - translate_ropw "op" op; - ], - []) -| `RISCVFENCE(mode, pred, succ) -> - ("FENCE", - [ - translate_fm_mode "mode" mode; - translate_imm4 "pred" pred; - translate_imm4 "succ" succ; - ], - []) -| `RISCVFENCEI -> - ("FENCEI", - [], - []) -| `RISCVLoadRes(aq, rl, rs1, width, rd) -> - ("LOADRES", - [ - translate_bool "aq" aq; - translate_bool "rl" rl; - translate_reg "rs1" rs1; - translate_width "width" width; - translate_reg "rd" rd; - ], - []) -| `RISCVStoreCon(aq, rl, rs2, rs1, width, rd) -> - ("STORECON", - [ - translate_bool "aq" aq; - translate_bool "rl" rl; - translate_reg "rs2" rs2; - translate_reg "rs1" rs1; - translate_width "width" width; - translate_reg "rd" rd; - ], - []) -| `RISCVAMO(op, aq, rl, rs2, rs1, width, rd) -> - ("AMO", - [ - translate_amoop "op" op; - translate_bool "aq" aq; - translate_bool "rl" rl; - translate_reg "rs2" rs2; - translate_reg "rs1" rs1; - translate_width "width" width; - translate_reg "rd" rd; - ], - []) diff --git a/riscv/gen/types.hgen b/riscv/gen/types.hgen deleted file mode 100644 index 5ad0b733..00000000 --- a/riscv/gen/types.hgen +++ /dev/null @@ -1,177 +0,0 @@ -type bit20 = int -type bit12 = int -type bit6 = int -type bit5 = int -type bit4 = int - -type riscvUop = (* upper immediate ops *) -| RISCVLUI -| RISCVAUIPC - -let pp_riscv_uop = function -| RISCVLUI -> "lui" -| RISCVAUIPC -> "auipc" - - -type riscvBop = (* branch ops *) -| RISCVBEQ -| RISCVBNE -| RISCVBLT -| RISCVBGE -| RISCVBLTU -| RISCVBGEU - -let pp_riscv_bop = function -| RISCVBEQ -> "beq" -| RISCVBNE -> "bne" -| RISCVBLT -> "blt" -| RISCVBGE -> "bge" -| RISCVBLTU -> "bltu" -| RISCVBGEU -> "bgeu" - -type riscvIop = (* immediate ops *) -| RISCVADDI -| RISCVSLTI -| RISCVSLTIU -| RISCVXORI -| RISCVORI -| RISCVANDI - -let pp_riscv_iop = function -| RISCVADDI -> "addi" -| RISCVSLTI -> "slti" -| RISCVSLTIU -> "sltiu" -| RISCVXORI -> "xori" -| RISCVORI -> "ori" -| RISCVANDI -> "andi" - -type riscvSop = (* shift ops *) -| RISCVSLLI -| RISCVSRLI -| RISCVSRAI - -let pp_riscv_sop = function -| RISCVSLLI -> "slli" -| RISCVSRLI -> "srli" -| RISCVSRAI -> "srai" - -type riscvRop = (* reg-reg ops *) -| RISCVADD -| RISCVSUB -| RISCVSLL -| RISCVSLT -| RISCVSLTU -| RISCVXOR -| RISCVSRL -| RISCVSRA -| RISCVOR -| RISCVAND - -let pp_riscv_rop = function -| RISCVADD -> "add" -| RISCVSUB -> "sub" -| RISCVSLL -> "sll" -| RISCVSLT -> "slt" -| RISCVSLTU -> "sltu" -| RISCVXOR -> "xor" -| RISCVSRL -> "srl" -| RISCVSRA -> "sra" -| RISCVOR -> "or" -| RISCVAND -> "and" - -type riscvRopw = (* reg-reg 32-bit ops *) -| RISCVADDW -| RISCVSUBW -| RISCVSLLW -| RISCVSRLW -| RISCVSRAW - -let pp_riscv_ropw = function -| RISCVADDW -> "addw" -| RISCVSUBW -> "subw" -| RISCVSLLW -> "sllw" -| RISCVSRLW -> "srlw" -| RISCVSRAW -> "sraw" - -type wordWidth = - | RISCVBYTE - | RISCVHALF - | RISCVWORD - | RISCVDOUBLE - -let pp_word_width width : string = - begin match width with - | RISCVBYTE -> "b" - | RISCVHALF -> "h" - | RISCVWORD -> "w" - | RISCVDOUBLE -> "d" - end - -let pp_riscv_load_op (unsigned, width, aq, rl) = - "l" ^ - (pp_word_width width) ^ - (if unsigned then "u" else "") ^ - (if aq then ".aq" else "") ^ - (if rl then ".rl" else "") - -let pp_riscv_store_op (width, aq, rl) = - "s" ^ - (pp_word_width width) ^ - (if aq then ".aq" else "") ^ - (if rl then ".rl" else "") - -let pp_riscv_load_reserved_op (aq, rl, width) = - "lr." ^ - (pp_word_width width) ^ - (if aq then ".aq" else "") ^ - (if rl then ".rl" else "") - -let pp_riscv_store_conditional_op (aq, rl, width) = - "sc." ^ - (pp_word_width width) ^ - (if aq then ".aq" else "") ^ - (if rl then ".rl" else "") - -type riscvAmoop = - | RISCVAMOSWAP - | RISCVAMOADD - | RISCVAMOXOR - | RISCVAMOAND - | RISCVAMOOR - | RISCVAMOMIN - | RISCVAMOMAX - | RISCVAMOMINU - | RISCVAMOMAXU - -let pp_riscv_amo_op_part = function - | RISCVAMOSWAP -> "swap" - | RISCVAMOADD -> "add" - | RISCVAMOXOR -> "xor" - | RISCVAMOAND -> "and" - | RISCVAMOOR -> "or" - | RISCVAMOMIN -> "min" - | RISCVAMOMAX -> "max" - | RISCVAMOMINU -> "minu" - | RISCVAMOMAXU -> "maxu" - -let pp_riscv_amo_op (op, aq, rl, width) = - "amo" ^ - pp_riscv_amo_op_part op ^ - begin match width with - | RISCVWORD -> ".w" - | RISCVDOUBLE -> ".d" - | _ -> assert false - end ^ - (if aq then ".aq" else "") ^ - (if rl then ".rl" else "") - -let pp_riscv_fence_option = function - | 0b0011 -> "rw" - | 0b0010 -> "r" - | 0b0001 -> "w" - | _ -> failwith "unexpected fence option" - -type riscv_fence_mode = - | RISCV_FM_NORMAL - | RISCV_FM_TSO - diff --git a/riscv/gen/types_sail_trans_out.hgen b/riscv/gen/types_sail_trans_out.hgen deleted file mode 100644 index 66e8eec2..00000000 --- a/riscv/gen/types_sail_trans_out.hgen +++ /dev/null @@ -1,103 +0,0 @@ -let translate_out_big_bit = function - | (name, Bvector _, bits) -> IInt.integer_of_bit_list bits - | _ -> assert false - -let translate_out_int inst = (Nat_big_num.to_int (translate_out_big_bit inst)) -let translate_out_signed_int inst bits = - let i = (Nat_big_num.to_int (translate_out_big_bit inst)) in - if (i >= (1 lsl (bits - 1))) then - (i - (1 lsl bits)) else - i - -let translate_out_ireg ireg = IReg (int_to_ireg (translate_out_int ireg)) - -let translate_out_simm21 imm = translate_out_signed_int imm 21 -let translate_out_simm20 imm = translate_out_signed_int imm 20 -let translate_out_simm13 imm = translate_out_signed_int imm 13 -let translate_out_simm12 imm = translate_out_signed_int imm 12 -let translate_out_imm6 imm = translate_out_int imm -let translate_out_imm5 imm = translate_out_int imm -let translate_out_imm4 imm = translate_out_int imm - -let translate_out_bool = function - | (name, Bit, [Bitc_one]) -> true - | (name, Bit, [Bitc_zero]) -> false - | _ -> assert false - -let translate_out_enum (name,_,bits) = - Nat_big_num.to_int (IInt.integer_of_bit_list bits) - -let translate_out_wordWidth w = - match translate_out_enum w with - | 0 -> RISCVBYTE - | 1 -> RISCVHALF - | 2 -> RISCVWORD - | 3 -> RISCVDOUBLE - | _ -> failwith "Unknown wordWidth in sail translate out" - -let translate_out_uop op = match translate_out_enum op with - | 0 -> RISCVLUI - | 1 -> RISCVAUIPC - | _ -> failwith "Unknown uop in sail translate out" - -let translate_out_bop op = match translate_out_enum op with -| 0 -> RISCVBEQ -| 1 -> RISCVBNE -| 2 -> RISCVBLT -| 3 -> RISCVBGE -| 4 -> RISCVBLTU -| 5 -> RISCVBGEU -| _ -> failwith "Unknown bop in sail translate out" - -let translate_out_iop op = match translate_out_enum op with -| 0 -> RISCVADDI -| 1 -> RISCVSLTI -| 2 -> RISCVSLTIU -| 3 -> RISCVXORI -| 4 -> RISCVORI -| 5 -> RISCVANDI -| _ -> failwith "Unknown iop in sail translate out" - -let translate_out_sop op = match translate_out_enum op with -| 0 -> RISCVSLLI -| 1 -> RISCVSRLI -| 2 -> RISCVSRAI -| _ -> failwith "Unknown sop in sail translate out" - -let translate_out_rop op = match translate_out_enum op with -| 0 -> RISCVADD -| 1 -> RISCVSUB -| 2 -> RISCVSLL -| 3 -> RISCVSLT -| 4 -> RISCVSLTU -| 5 -> RISCVXOR -| 6 -> RISCVSRL -| 7 -> RISCVSRA -| 8 -> RISCVOR -| 9 -> RISCVAND -| _ -> failwith "Unknown rop in sail translate out" - -let translate_out_ropw op = match translate_out_enum op with -| 0 -> RISCVADDW -| 1 -> RISCVSUBW -| 2 -> RISCVSLLW -| 3 -> RISCVSRLW -| 4 -> RISCVSRAW -| _ -> failwith "Unknown ropw in sail translate out" - -let translate_out_amoop op = match translate_out_enum op with -| 0 -> RISCVAMOSWAP -| 1 -> RISCVAMOADD -| 2 -> RISCVAMOXOR -| 3 -> RISCVAMOAND -| 4 -> RISCVAMOOR -| 5 -> RISCVAMOMIN -| 6 -> RISCVAMOMAX -| 7 -> RISCVAMOMINU -| 8 -> RISCVAMOMAXU -| _ -> failwith "Unknown amoop in sail translate out" - -let translate_out_fm_mode mode = match translate_out_enum mode with -| 0 -> RISCV_FM_NORMAL -| 1 -> RISCV_FM_TSO -| _ -> failwith "Unknown fm_mode in sail translate out" diff --git a/riscv/gen/types_trans_sail.hgen b/riscv/gen/types_trans_sail.hgen deleted file mode 100644 index eb6aa458..00000000 --- a/riscv/gen/types_trans_sail.hgen +++ /dev/null @@ -1,59 +0,0 @@ -let translate_enum enum_values name value = - let rec bit_count n = - if n = 0 then 0 - else 1 + (bit_count (n lsr 1)) in - let rec find_index element = function - | h::tail -> if h = element then 0 else 1 + (find_index element tail) - | _ -> failwith "translate_enum could not find value" - in - let size = bit_count (List.length enum_values) in - let index = find_index value enum_values in - (name, Range0 (Some size), IInt.bit_list_of_integer size (Nat_big_num.of_int index)) - -let translate_uop = translate_enum [RISCVLUI; RISCVAUIPC] - -let translate_bop = translate_enum [RISCVBEQ; RISCVBNE; RISCVBLT; RISCVBGE; RISCVBLTU; RISCVBGEU] (* branch ops *) - -let translate_iop = translate_enum [RISCVADDI; RISCVSLTI; RISCVSLTIU; RISCVXORI; RISCVORI; RISCVANDI] (* immediate ops *) - -let translate_sop = translate_enum [RISCVSLLI; RISCVSRLI; RISCVSRAI] (* shift ops *) - -let translate_rop = translate_enum [RISCVADD; RISCVSUB; RISCVSLL; RISCVSLT; RISCVSLTU; RISCVXOR; RISCVSRL; RISCVSRA; RISCVOR; RISCVAND] (* reg-reg ops *) - -let translate_ropw = translate_enum [RISCVADDW; RISCVSUBW; RISCVSLLW; RISCVSRLW; RISCVSRAW] (* reg-reg 32-bit ops *) - -let translate_amoop = translate_enum [RISCVAMOSWAP; RISCVAMOADD; RISCVAMOXOR; RISCVAMOAND; RISCVAMOOR; RISCVAMOMIN; RISCVAMOMAX; RISCVAMOMINU; RISCVAMOMAXU] - -let translate_width = translate_enum [RISCVBYTE; RISCVHALF; RISCVWORD; RISCVDOUBLE] - -let translate_fm_mode = translate_enum [RISCV_FM_NORMAL; RISCV_FM_TSO] - -let translate_reg name value = - (name, Bvector (Some 5), bit_list_of_integer 5 (Nat_big_num.of_int (reg_to_int value))) - -let translate_imm21 name value = - (name, Bvector (Some 21), bit_list_of_integer 21 (Nat_big_num.of_int value)) - -let translate_imm20 name value = - (name, Bvector (Some 20), bit_list_of_integer 20 (Nat_big_num.of_int value)) - -let translate_imm16 name value = - (name, Bvector (Some 16), bit_list_of_integer 16 (Nat_big_num.of_int value)) - -let translate_imm13 name value = - (name, Bvector (Some 13), bit_list_of_integer 13 (Nat_big_num.of_int value)) - -let translate_imm12 name value = - (name, Bvector (Some 12), bit_list_of_integer 12 (Nat_big_num.of_int value)) - -let translate_imm6 name value = - (name, Bvector (Some 6), bit_list_of_integer 6 (Nat_big_num.of_int value)) - -let translate_imm5 name value = - (name, Bvector (Some 5), bit_list_of_integer 5 (Nat_big_num.of_int value)) - -let translate_imm4 name value = - (name, Bvector (Some 4), bit_list_of_integer 4 (Nat_big_num.of_int value)) - -let translate_bool name value = - (name, Bit, [if value then Bitc_one else Bitc_zero]) diff --git a/riscv/main.sail b/riscv/main.sail deleted file mode 100644 index dbf41f49..00000000 --- a/riscv/main.sail +++ /dev/null @@ -1,26 +0,0 @@ -val elf_tohost = { - ocaml: "Elf_loader.elf_tohost", - c: "elf_tohost" -} : unit -> int - -val elf_entry = { - ocaml: "Elf_loader.elf_entry", - c: "elf_entry" -} : unit -> int - -val main : unit -> unit effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg} - -function main () = { - - // PC = __GetSlice_int(64, elf_entry(), 0); - PC = zero_extend(0x1000, 64); - print_bits("PC = ", PC); - try { - init_platform(); - init_sys(); - loop() - } catch { - Error_not_implemented(s) => print_string("Error: Not implemented: ", s), - Error_internal_error() => print("Error: internal error") - } -} diff --git a/riscv/main_rvfi.sail b/riscv/main_rvfi.sail deleted file mode 100644 index 0ba4acfc..00000000 --- a/riscv/main_rvfi.sail +++ /dev/null @@ -1,108 +0,0 @@ -// Alternative fetch and step for RVFI DII mode. - -val rvfi_fetch : unit -> FetchResult effect {escape, rmem, rreg, wmv, wreg} - -function rvfi_fetch() = - /* check for legal PC */ - if (PC[0] != 0b0 | (PC[1] != 0b0 & (~ (haveRVC())))) - then F_Error(E_Fetch_Addr_Align, PC) - else { - let i = rvfi_instruction.rvfi_insn(); - rvfi_exec->rvfi_order() = minstret; - rvfi_exec->rvfi_pc_rdata() = PC; - rvfi_exec->rvfi_insn() = zero_extend(i,64); - /* TODO: should we write these even if they're not really registers? */ - rvfi_exec->rvfi_rs1_data() = X(i[19 .. 15]); - rvfi_exec->rvfi_rs2_data() = X(i[24 .. 20]); - rvfi_exec->rvfi_rs1_addr() = zero_extend(i[19 .. 15],8); - rvfi_exec->rvfi_rs2_addr() = zero_extend(i[24 .. 20],8); - if (i[1 .. 0] == 0b11) - then F_Base(i) - else F_RVC(i[15 .. 0]) - } - -// This should be kept in sync with the normal step - at the moment the only -// changes are to replace fetch by rvfi_fetch and record the next PC. - -/* returns whether to increment the step count in the trace */ -val rvfi_step : int -> bool effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg} -function rvfi_step(step_no) = { - minstret_written = false; /* see note for minstret */ - let (retired, stepped) : (bool, bool) = - match curInterrupt(cur_privilege, mip, mie, mideleg) { - Some(intr, priv) => { - print_bits("Handling interrupt: ", intr); - handle_interrupt(intr, priv); - (false, false) - }, - None() => { - match rvfi_fetch() { - F_Error(e, addr) => { - handle_mem_exception(addr, e); - (false, false) - }, - F_RVC(h) => { - match decodeCompressed(h) { - None() => { - print("[" ^ string_of_int(step_no) ^ "] [" ^ cur_privilege ^ "]: " ^ BitStr(PC) ^ " (" ^ BitStr(h) ^ ") "); - instbits = EXTZ(h); - handle_illegal(); - (false, true) - }, - Some(ast) => { - print("[" ^ string_of_int(step_no) ^ "] [" ^ cur_privilege ^ "]: " ^ BitStr(PC) ^ " (" ^ BitStr(h) ^ ") " ^ ast); - nextPC = PC + 2; - (execute(ast), true) - } - } - }, - F_Base(w) => { - match decode(w) { - None() => { - print("[" ^ string_of_int(step_no) ^ "] [" ^ cur_privilege ^ "]: " ^ BitStr(PC) ^ " (" ^ BitStr(w) ^ ") "); - instbits = EXTZ(w); - handle_illegal(); - (false, true) - }, - Some(ast) => { - print("[" ^ string_of_int(step_no) ^ "] [" ^ cur_privilege ^ "]: " ^ BitStr(PC) ^ " (" ^ BitStr(w) ^ ") " ^ ast); - nextPC = PC + 4; - (execute(ast), true) - } - } - } - } - } - }; - PC = nextPC; - rvfi_exec->rvfi_pc_wdata() = PC; -//print_rvfi_exec(); - if retired then retire_instruction(); - stepped -} - - -/* Dummy to make sure that sail doesn't throw functions away */ - -val main : unit -> unit effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg} - -function main () = { - - // PC = __GetSlice_int(64, elf_entry(), 0); - rvfi_set_instr_packet(0x0000000000000000); - print_bits("", rvfi_get_cmd()); - let _ = rvfi_step(0); - rvfi_zero_exec_packet(); - rvfi_halt_exec_packet(); - let _ = rvfi_get_exec_packet(); - PC = zero_extend(0x1000, 64); - print_bits("PC = ", PC); - try { - init_platform(); - init_sys(); - loop() - } catch { - Error_not_implemented(s) => print_string("Error: Not implemented: ", s), - Error_internal_error() => print("Error: internal error") - } -} diff --git a/riscv/platform.ml b/riscv/platform.ml deleted file mode 100644 index bdd5bd04..00000000 --- a/riscv/platform.ml +++ /dev/null @@ -1,172 +0,0 @@ -(**************************************************************************) -(* Sail *) -(* *) -(* Copyright (c) 2013-2017 *) -(* Kathyrn Gray *) -(* Shaked Flur *) -(* Stephen Kell *) -(* Gabriel Kerneis *) -(* Robert Norton-Wright *) -(* Christopher Pulte *) -(* Peter Sewell *) -(* Alasdair Armstrong *) -(* Brian Campbell *) -(* Thomas Bauereiss *) -(* Anthony Fox *) -(* Jon French *) -(* Dominic Mulligan *) -(* Stephen Kell *) -(* Mark Wassell *) -(* *) -(* All rights reserved. *) -(* *) -(* This software was developed by the University of Cambridge Computer *) -(* Laboratory as part of the Rigorous Engineering of Mainstream Systems *) -(* (REMS) project, funded by EPSRC grant EP/K008528/1. *) -(* *) -(* Redistribution and use in source and binary forms, with or without *) -(* modification, are permitted provided that the following conditions *) -(* are met: *) -(* 1. Redistributions of source code must retain the above copyright *) -(* notice, this list of conditions and the following disclaimer. *) -(* 2. Redistributions in binary form must reproduce the above copyright *) -(* notice, this list of conditions and the following disclaimer in *) -(* the documentation and/or other materials provided with the *) -(* distribution. *) -(* *) -(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *) -(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *) -(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *) -(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *) -(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *) -(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *) -(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *) -(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *) -(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *) -(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *) -(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *) -(* SUCH DAMAGE. *) -(**************************************************************************) - -open Sail_lib;; -module P = Platform_impl;; -module Elf = Elf_loader;; - -(* Platform configuration *) - -let config_enable_dirty_update = ref false -let config_enable_misaligned_access = ref false -let config_mtval_has_illegal_inst_bits = ref false - -(* logging *) - -let config_print_instr = ref true -let config_print_reg = ref true -let config_print_mem_access = ref true -let config_print_platform = ref true - -let print_instr s = - if !config_print_instr - then print_endline s - else () - -let print_reg s = - if !config_print_reg - then print_endline s - else () - -let print_mem_access s = - if !config_print_mem_access - then print_endline s - else () - -let print_platform s = - if !config_print_platform - then print_endline s - else () - -(* Mapping to Sail externs *) - -let bits_of_int i = - get_slice_int (Big_int.of_int 64, Big_int.of_int i, Big_int.zero) - -let bits_of_int64 i = - get_slice_int (Big_int.of_int 64, Big_int.of_int64 i, Big_int.zero) - -let rom_size_ref = ref 0 -let make_rom start_pc = - let reset_vec = List.concat (List.map P.uint32_to_bytes (P.reset_vec_int start_pc)) in - let dtb = P.make_dtb (P.make_dts ()) in - let rom = reset_vec @ dtb in - ( rom_size_ref := List.length rom; - (* - List.iteri (fun i c -> - print_mem_access "rom[0x%Lx] <- %x\n" - (Int64.add P.rom_base (Int64.of_int i)) - c - ) rom; - *) - rom ) - -let enable_dirty_update () = !config_enable_dirty_update -let enable_misaligned_access () = !config_enable_misaligned_access -let mtval_has_illegal_inst_bits () = !config_mtval_has_illegal_inst_bits - -let rom_base () = bits_of_int64 P.rom_base -let rom_size () = bits_of_int !rom_size_ref - -let dram_base () = bits_of_int64 P.dram_base -let dram_size () = bits_of_int64 !P.dram_size_ref - -let htif_tohost () = - bits_of_int64 (Big_int.to_int64 (Elf.elf_tohost ())) - -let clint_base () = bits_of_int64 P.clint_base -let clint_size () = bits_of_int64 P.clint_size - -let insns_per_tick () = Big_int.of_int P.insns_per_tick - -(* load reservation *) - -let reservation = ref "none" (* shouldn't match any valid address *) - -let load_reservation addr = - print_platform (Printf.sprintf "reservation <- %s\n" (string_of_bits addr)); - reservation := string_of_bits addr - -let match_reservation addr = - print_platform (Printf.sprintf "reservation: %s, key=%s\n" (!reservation) (string_of_bits addr)); - string_of_bits addr = !reservation - -let cancel_reservation () = - print_platform (Printf.sprintf "reservation <- none\n"); - reservation := "none" - -(* terminal I/O *) - -let term_write char_bits = - let big_char = Big_int.bitwise_and (uint char_bits) (Big_int.of_int 255) in - P.term_write (char_of_int (Big_int.to_int big_char)) - -let term_read () = - let c = P.term_read () in - bits_of_int (int_of_char c) - -(* returns starting value for PC, i.e. start of reset vector *) -let init elf_file = - Elf.load_elf elf_file; - - print_platform (Printf.sprintf "\nRegistered htif_tohost at 0x%Lx.\n" (Big_int.to_int64 (Elf.elf_tohost ()))); - print_platform (Printf.sprintf "Registered clint at 0x%Lx (size 0x%Lx).\n%!" P.clint_base P.clint_size); - - let start_pc = Elf.Big_int.to_int64 (Elf.elf_entry ()) in - let rom = make_rom start_pc in - let rom_base = Big_int.of_int64 P.rom_base in - let rec write_rom ofs = function - | [] -> () - | h :: tl -> let addr = Big_int.add rom_base (Big_int.of_int ofs) in - (wram addr h); - write_rom (ofs + 1) tl - in ( write_rom 0 rom; - get_slice_int (Big_int.of_int 64, rom_base, Big_int.zero) - ) diff --git a/riscv/platform_impl.ml b/riscv/platform_impl.ml deleted file mode 100644 index 3eb82179..00000000 --- a/riscv/platform_impl.ml +++ /dev/null @@ -1,189 +0,0 @@ -(* FIXME: copyright header *) - -(* int->byte converters in little-endian order *) - -let uint32_to_bytes u = let open Int32 in - List.map to_int - [ logand u 0xffl; - logand (shift_right u 8) 0xffl; - logand (shift_right u 16) 0xffl; - logand (shift_right u 24) 0xffl; - ] - -let uint64_to_bytes u = let open Int64 in - List.map to_int - [ logand u 0xffL; - logand (shift_right u 8) 0xffL; - logand (shift_right u 16) 0xffL; - logand (shift_right u 24) 0xffL; - logand (shift_right u 32) 0xffL; - logand (shift_right u 40) 0xffL; - logand (shift_right u 48) 0xffL; - logand (shift_right u 56) 0xffL; - ] - -(* reset vector for the rom *) - -let reset_vec_size = 8l;; - -let reset_vec_int start_pc = [ - 0x297l; (* auipc t0, 0x0 *) - (let open Int32 in - add 0x28593l (shift_left (mul reset_vec_size 4l) 20)); (* addi a1, t0, ofs(dtb) *) - 0xf1402573l; (* csrr a0, mhartid *) - 0x0182b283l; (* ld t0, 24(t0) *) - 0x28067l; (* jr t0 *) - 0x0l; - (let open Int64 in to_int32 (logand start_pc 0xffffffffL)); - (let open Int64 in to_int32 (shift_right_logical start_pc 32)); -] - -(* address map *) - -let dram_base = 0x80000000L;; (* Spike::DRAM_BASE *) -let clint_base = 0x02000000L;; (* Spike::CLINT_BASE *) -let clint_size = 0x000c0000L;; (* Spike::CLINT_SIZE *) -let rom_base = 0x00001000L;; (* Spike::DEFAULT_RSTVEC *) - -let dram_size_ref = ref (Int64.(shift_left 2048L 20)) - -type mem_region = { - addr : Int64.t; - size : Int64.t -} - -(* dts from spike *) -let spike_dts isa_spec cpu_hz insns_per_rtc_tick mems = - "/dts-v1/;\n" - ^ "\n" - ^ "/ {\n" - ^ " #address-cells = <2>;\n" - ^ " #size-cells = <2>;\n" - ^ " compatible = \"ucbbar,spike-bare-dev\";\n" - ^ " model = \"ucbbar,spike-bare\";\n" - ^ " cpus {\n" - ^ " #address-cells = <1>;\n" - ^ " #size-cells = <0>;\n" - ^ " timebase-frequency = <" ^ string_of_int (cpu_hz/insns_per_rtc_tick) ^ ">;\n" - ^ " CPU0: cpu@0 {\n" - ^ " device_type = \"cpu\";\n" - ^ " reg = <0>;\n" - ^ " status = \"okay\";\n" - ^ " compatible = \"riscv\";\n" - ^ " riscv,isa = \"" ^ isa_spec ^ "\";\n" - ^ " mmu-type = \"riscv,sv39\";\n" - ^ " clock-frequency = <" ^ string_of_int cpu_hz ^ ">;\n" - ^ " CPU0_intc: interrupt-controller {\n" - ^ " #interrupt-cells = <1>;\n" - ^ " interrupt-controller;\n" - ^ " compatible = \"riscv,cpu-intc\";\n" - ^ " };\n" - ^ " };\n" - ^ " };\n" - ^ (List.fold_left (^) "" - (List.map (fun m -> - " memory@" ^ Printf.sprintf "%Lx" m.addr ^ " {\n" - ^ " device_type = \"memory\";\n" - ^ " reg = <0x" ^ Printf.sprintf "%Lx" Int64.(shift_right_logical m.addr 32) ^ " 0x" ^ Printf.sprintf "%Lx" Int64.(logand m.addr 0xffffffffL) - ^ " 0x" ^ Printf.sprintf "%Lx" Int64.(shift_right_logical m.size 32) ^ " 0x" ^ Printf.sprintf "%Lx" Int64.(logand m.size 0xffffffffL) ^ ">;\n" - ^ " };\n") mems)) - ^ " soc {\n" - ^ " #address-cells = <2>;\n" - ^ " #size-cells = <2>;\n" - ^ " compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n" - ^ " ranges;\n" - ^ " clint@" ^ Printf.sprintf "%Lx" clint_base ^ " {\n" - ^ " compatible = \"riscv,clint0\";\n" - ^ " interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7 >;\n" - ^ " reg = <0x" ^ Printf.sprintf "%Lx" Int64.(shift_right_logical clint_base 32) ^ " 0x" ^ Printf.sprintf "%Lx" Int64.(logand clint_base 0xffffffffL) - ^ " 0x" ^ Printf.sprintf "%Lx" Int64.(shift_right_logical clint_size 32) ^ " 0x" ^ Printf.sprintf "%Lx" Int64.(logand clint_size 0xffffffffL) ^ ">;\n" - ^ " };\n" - ^ " };\n" - ^ " htif {\n" - ^ " compatible = \"ucb,htif0\";\n" - ^ " };\n" - ^ "};\n" - -let cpu_hz = 1000000000;; -let insns_per_tick = 100;; - -let make_mems () = [{ addr = dram_base; - size = !dram_size_ref }];; - -let make_dts () = spike_dts "rv64imac" cpu_hz insns_per_tick (make_mems ());; - -let bytes_to_string bytes = - String.init (List.length bytes) (fun i -> Char.chr (List.nth bytes i)) - -let dtc_path = ref "/usr/bin/dtc" - -let set_dtc path = - try let st = Unix.stat path in - if st.Unix.st_kind = Unix.S_REG && st.Unix.st_perm != 0 - then dtc_path := path - else ( Printf.eprintf "%s doesn't seem like a valid executable.\n%!" path; - exit 1) - with Unix.Unix_error (e, _, _) -> - ( Printf.eprintf "Error accessing %s: %s\n%!" path (Unix.error_message e); - exit 1) - -let set_dram_size mb = - dram_size_ref := Int64.(shift_left (Int64.of_int mb) 20) - -let make_dtb dts = (* Call the dtc compiler, assumed to be at /usr/bin/dtc *) - try - let cmd = Printf.sprintf "%s -I dts" !dtc_path in - let (cfrom, cto, cerr) = - Unix.open_process_full cmd [||] - in ( - output_string cto dts; - (* print_endline " sent dts to dtc ..."; *) - close_out cto; - (* simple and stupid for now *) - let rec accum_bytes cin acc = - match ( - try Some (input_byte cin) - with End_of_file -> None - ) with - | Some b -> accum_bytes cin (b :: acc) - | None -> List.rev acc - in - (* let _ = print_endline " accumulating dtb ..." in *) - let dtb = accum_bytes cfrom [] in - (* let _ = print_endline " accumulating emsg ..." in *) - let emsg = bytes_to_string (accum_bytes cerr []) in - match Unix.close_process_full (cfrom, cto, cerr) with - | Unix.WEXITED 0 -> dtb - | _ -> (Printf.printf "%s\n%!" ("Error executing dtc: " ^ emsg); - exit 1) - ) - with Unix.Unix_error (e, fn, _) -> - (Printf.printf "%s\n" ("Error executing dtc: " ^ fn ^ ": " ^ Unix.error_message e); - exit 1) - -(* Terminal I/O *) - -let term_write char = - ignore (Unix.write_substring Unix.stderr (String.make 1 char) 0 1) - -let rec term_read () = - let buf = Bytes.make 1 '\000' in - let nbytes = Unix.read Unix.stdin buf 0 1 in - (* todo: handle nbytes == 0 *) - Bytes.get buf 0 - -(* Platform diagnostics *) - -let show_bytes s = - output_string stdout s - -let dump_dts () = show_bytes (make_dts ()) -let dump_dtb () = show_bytes (bytes_to_string (make_dtb (make_dts ()))) - -(* -let save_string_to_file s fname = - let out = open_out fname in - output_string out s; - close_out out;; - - *) diff --git a/riscv/platform_main.ml b/riscv/platform_main.ml deleted file mode 100644 index 1c9ba209..00000000 --- a/riscv/platform_main.ml +++ /dev/null @@ -1,131 +0,0 @@ -(**************************************************************************) -(* Sail *) -(* *) -(* Copyright (c) 2013-2017 *) -(* Kathyrn Gray *) -(* Shaked Flur *) -(* Stephen Kell *) -(* Gabriel Kerneis *) -(* Robert Norton-Wright *) -(* Christopher Pulte *) -(* Peter Sewell *) -(* Alasdair Armstrong *) -(* Brian Campbell *) -(* Thomas Bauereiss *) -(* Anthony Fox *) -(* Jon French *) -(* Dominic Mulligan *) -(* Stephen Kell *) -(* Mark Wassell *) -(* *) -(* All rights reserved. *) -(* *) -(* This software was developed by the University of Cambridge Computer *) -(* Laboratory as part of the Rigorous Engineering of Mainstream Systems *) -(* (REMS) project, funded by EPSRC grant EP/K008528/1. *) -(* *) -(* Redistribution and use in source and binary forms, with or without *) -(* modification, are permitted provided that the following conditions *) -(* are met: *) -(* 1. Redistributions of source code must retain the above copyright *) -(* notice, this list of conditions and the following disclaimer. *) -(* 2. Redistributions in binary form must reproduce the above copyright *) -(* notice, this list of conditions and the following disclaimer in *) -(* the documentation and/or other materials provided with the *) -(* distribution. *) -(* *) -(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *) -(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *) -(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *) -(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *) -(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *) -(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *) -(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *) -(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *) -(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *) -(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *) -(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *) -(* SUCH DAMAGE. *) -(**************************************************************************) - -open Elf_loader -open Sail_lib -open Riscv -module PI = Platform_impl -module P = Platform - -(* OCaml driver for generated RISC-V model. *) - -let opt_file_arguments = ref ([] : string list) - -let opt_dump_dts = ref false -let opt_dump_dtb = ref false - -let options = Arg.align ([("-dump-dts", - Arg.Set opt_dump_dts, - " dump the platform device-tree source to stdout"); - ("-dump-dtb", - Arg.Set opt_dump_dtb, - " dump the *binary* platform device-tree blob to stdout"); - ("-enable-dirty-update", - Arg.Set P.config_enable_dirty_update, - " enable dirty-bit update during page-table walks"); - ("-enable-misaligned-access", - Arg.Set P.config_enable_misaligned_access, - " enable misaligned accesses without M-mode traps"); - ("-mtval-has-illegal-inst-bits", - Arg.Set P.config_mtval_has_illegal_inst_bits, - " mtval stores instruction bits on an illegal instruction exception"); - ("-ram-size", - Arg.Int PI.set_dram_size, - " size of physical ram memory to use (in MB)"); - ("-with-dtc", - Arg.String PI.set_dtc, - " full path to dtc to use") - ]) - -let usage_msg = "RISC-V platform options:" - -let elf_arg = - Arg.parse options (fun s -> opt_file_arguments := !opt_file_arguments @ [s]) - usage_msg; - if !opt_dump_dts then (PI.dump_dts (); exit 0); - if !opt_dump_dtb then (PI.dump_dtb (); exit 0); - ( match !opt_file_arguments with - | f :: _ -> prerr_endline ("Sail/RISC-V: running ELF file " ^ f); f - | _ -> (prerr_endline "Please provide an ELF file."; exit 0) - ) - -let run pc = - sail_call - (fun r -> - try ( zinit_platform (); (* devices *) - zinit_sys (); (* processor *) - zPC := pc; - zloop () - ) - with - | ZError_not_implemented (zs) -> - print_string ("Error: Not implemented: ", zs) - | ZError_internal_error (_) -> - prerr_endline "Error: internal error" - ) - -let show_times init_s init_e run_e insts = - let init_time = init_e.Unix.tms_utime -. init_s.Unix.tms_utime in - let exec_time = run_e.Unix.tms_utime -. init_e.Unix.tms_utime in - Printf.eprintf "\nInitialization: %g secs\n" init_time; - Printf.eprintf "Execution: %g secs\n" exec_time; - Printf.eprintf "Instructions retired: %Ld\n" insts; - Printf.eprintf "Perf: %g ips\n" ((Int64.to_float insts) /. exec_time) - -let () = - Random.self_init (); - - let init_start = Unix.times () in - let pc = Platform.init elf_arg in - let init_end = Unix.times () in - let _ = run pc in - let run_end = Unix.times () in - let insts = Big_int.to_int64 (uint (!Riscv.zminstret)) in - show_times init_start init_end run_end insts diff --git a/riscv/prelude.sail b/riscv/prelude.sail deleted file mode 100644 index 5779609d..00000000 --- a/riscv/prelude.sail +++ /dev/null @@ -1,1156 +0,0 @@ -default Order dec - -$include - -type bits ('n : Int) = vector('n, dec, bit) -union option ('a : Type) = {None : unit, Some : 'a} - -val spc : unit <-> string -val opt_spc : unit <-> string -val def_spc : unit <-> string - -val hex_bits : forall 'n . (atom('n), bits('n)) <-> string - -val string_startswith = "string_startswith" : (string, string) -> bool -val string_drop = "string_drop" : (string, nat) -> string -val string_take = "string_take" : (string, nat) -> string -val string_length = "string_length" : string -> nat -val string_append = {c: "concat_str", _: "string_append"} : (string, string) -> string -val maybe_int_of_prefix = "maybe_int_of_prefix" : string -> option((int, nat)) -val maybe_nat_of_prefix = "maybe_nat_of_prefix" : string -> option((nat, nat)) -val maybe_int_of_string = "maybe_int_of_string" : string -> option(int) - -/* Python: -f = """val hex_bits_{0} : bits({0}) <-> string -val hex_bits_{0}_forwards = "decimal_string_of_bits" : bits({0}) -> string -val hex_bits_{0}_forwards_matches : bits({0}) -> bool -function hex_bits_{0}_forwards_matches bv = true -val "hex_bits_{0}_matches_prefix" : string -> option((bits({0}), nat)) -val hex_bits_{0}_backwards_matches : string -> bool -function hex_bits_{0}_backwards_matches s = match s {{ - s if match hex_bits_{0}_matches_prefix(s) {{ - Some (_, n) if n == string_length(s) => true, - _ => false - }} => true, - _ => false -}} -val hex_bits_{0}_backwards : string -> bits({0}) -function hex_bits_{0}_backwards s = - match hex_bits_{0}_matches_prefix(s) {{ - Some (bv, n) if n == string_length(s) => bv - }} -""" - -for i in list(range(1, 34)) + [48, 64]: - print(f.format(i)) - -*/ -val hex_bits_1 : bits(1) <-> string -val hex_bits_1_forwards = "decimal_string_of_bits" : bits(1) -> string -val hex_bits_1_forwards_matches : bits(1) -> bool -function hex_bits_1_forwards_matches bv = true -val "hex_bits_1_matches_prefix" : string -> option((bits(1), nat)) -val hex_bits_1_backwards_matches : string -> bool -function hex_bits_1_backwards_matches s = match s { - s if match hex_bits_1_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_1_backwards : string -> bits(1) -function hex_bits_1_backwards s = - match hex_bits_1_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_2 : bits(2) <-> string -val hex_bits_2_forwards = "decimal_string_of_bits" : bits(2) -> string -val hex_bits_2_forwards_matches : bits(2) -> bool -function hex_bits_2_forwards_matches bv = true -val "hex_bits_2_matches_prefix" : string -> option((bits(2), nat)) -val hex_bits_2_backwards_matches : string -> bool -function hex_bits_2_backwards_matches s = match s { - s if match hex_bits_2_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_2_backwards : string -> bits(2) -function hex_bits_2_backwards s = - match hex_bits_2_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_3 : bits(3) <-> string -val hex_bits_3_forwards = "decimal_string_of_bits" : bits(3) -> string -val hex_bits_3_forwards_matches : bits(3) -> bool -function hex_bits_3_forwards_matches bv = true -val "hex_bits_3_matches_prefix" : string -> option((bits(3), nat)) -val hex_bits_3_backwards_matches : string -> bool -function hex_bits_3_backwards_matches s = match s { - s if match hex_bits_3_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_3_backwards : string -> bits(3) -function hex_bits_3_backwards s = - match hex_bits_3_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_4 : bits(4) <-> string -val hex_bits_4_forwards = "decimal_string_of_bits" : bits(4) -> string -val hex_bits_4_forwards_matches : bits(4) -> bool -function hex_bits_4_forwards_matches bv = true -val "hex_bits_4_matches_prefix" : string -> option((bits(4), nat)) -val hex_bits_4_backwards_matches : string -> bool -function hex_bits_4_backwards_matches s = match s { - s if match hex_bits_4_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_4_backwards : string -> bits(4) -function hex_bits_4_backwards s = - match hex_bits_4_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_5 : bits(5) <-> string -val hex_bits_5_forwards = "decimal_string_of_bits" : bits(5) -> string -val hex_bits_5_forwards_matches : bits(5) -> bool -function hex_bits_5_forwards_matches bv = true -val "hex_bits_5_matches_prefix" : string -> option((bits(5), nat)) -val hex_bits_5_backwards_matches : string -> bool -function hex_bits_5_backwards_matches s = match s { - s if match hex_bits_5_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_5_backwards : string -> bits(5) -function hex_bits_5_backwards s = - match hex_bits_5_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_6 : bits(6) <-> string -val hex_bits_6_forwards = "decimal_string_of_bits" : bits(6) -> string -val hex_bits_6_forwards_matches : bits(6) -> bool -function hex_bits_6_forwards_matches bv = true -val "hex_bits_6_matches_prefix" : string -> option((bits(6), nat)) -val hex_bits_6_backwards_matches : string -> bool -function hex_bits_6_backwards_matches s = match s { - s if match hex_bits_6_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_6_backwards : string -> bits(6) -function hex_bits_6_backwards s = - match hex_bits_6_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_7 : bits(7) <-> string -val hex_bits_7_forwards = "decimal_string_of_bits" : bits(7) -> string -val hex_bits_7_forwards_matches : bits(7) -> bool -function hex_bits_7_forwards_matches bv = true -val "hex_bits_7_matches_prefix" : string -> option((bits(7), nat)) -val hex_bits_7_backwards_matches : string -> bool -function hex_bits_7_backwards_matches s = match s { - s if match hex_bits_7_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_7_backwards : string -> bits(7) -function hex_bits_7_backwards s = - match hex_bits_7_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_8 : bits(8) <-> string -val hex_bits_8_forwards = "decimal_string_of_bits" : bits(8) -> string -val hex_bits_8_forwards_matches : bits(8) -> bool -function hex_bits_8_forwards_matches bv = true -val "hex_bits_8_matches_prefix" : string -> option((bits(8), nat)) -val hex_bits_8_backwards_matches : string -> bool -function hex_bits_8_backwards_matches s = match s { - s if match hex_bits_8_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_8_backwards : string -> bits(8) -function hex_bits_8_backwards s = - match hex_bits_8_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_9 : bits(9) <-> string -val hex_bits_9_forwards = "decimal_string_of_bits" : bits(9) -> string -val hex_bits_9_forwards_matches : bits(9) -> bool -function hex_bits_9_forwards_matches bv = true -val "hex_bits_9_matches_prefix" : string -> option((bits(9), nat)) -val hex_bits_9_backwards_matches : string -> bool -function hex_bits_9_backwards_matches s = match s { - s if match hex_bits_9_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_9_backwards : string -> bits(9) -function hex_bits_9_backwards s = - match hex_bits_9_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_10 : bits(10) <-> string -val hex_bits_10_forwards = "decimal_string_of_bits" : bits(10) -> string -val hex_bits_10_forwards_matches : bits(10) -> bool -function hex_bits_10_forwards_matches bv = true -val "hex_bits_10_matches_prefix" : string -> option((bits(10), nat)) -val hex_bits_10_backwards_matches : string -> bool -function hex_bits_10_backwards_matches s = match s { - s if match hex_bits_10_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_10_backwards : string -> bits(10) -function hex_bits_10_backwards s = - match hex_bits_10_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_11 : bits(11) <-> string -val hex_bits_11_forwards = "decimal_string_of_bits" : bits(11) -> string -val hex_bits_11_forwards_matches : bits(11) -> bool -function hex_bits_11_forwards_matches bv = true -val "hex_bits_11_matches_prefix" : string -> option((bits(11), nat)) -val hex_bits_11_backwards_matches : string -> bool -function hex_bits_11_backwards_matches s = match s { - s if match hex_bits_11_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_11_backwards : string -> bits(11) -function hex_bits_11_backwards s = - match hex_bits_11_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_12 : bits(12) <-> string -val hex_bits_12_forwards = "decimal_string_of_bits" : bits(12) -> string -val hex_bits_12_forwards_matches : bits(12) -> bool -function hex_bits_12_forwards_matches bv = true -val "hex_bits_12_matches_prefix" : string -> option((bits(12), nat)) -val hex_bits_12_backwards_matches : string -> bool -function hex_bits_12_backwards_matches s = match s { - s if match hex_bits_12_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_12_backwards : string -> bits(12) -function hex_bits_12_backwards s = - match hex_bits_12_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_13 : bits(13) <-> string -val hex_bits_13_forwards = "decimal_string_of_bits" : bits(13) -> string -val hex_bits_13_forwards_matches : bits(13) -> bool -function hex_bits_13_forwards_matches bv = true -val "hex_bits_13_matches_prefix" : string -> option((bits(13), nat)) -val hex_bits_13_backwards_matches : string -> bool -function hex_bits_13_backwards_matches s = match s { - s if match hex_bits_13_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_13_backwards : string -> bits(13) -function hex_bits_13_backwards s = - match hex_bits_13_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_14 : bits(14) <-> string -val hex_bits_14_forwards = "decimal_string_of_bits" : bits(14) -> string -val hex_bits_14_forwards_matches : bits(14) -> bool -function hex_bits_14_forwards_matches bv = true -val "hex_bits_14_matches_prefix" : string -> option((bits(14), nat)) -val hex_bits_14_backwards_matches : string -> bool -function hex_bits_14_backwards_matches s = match s { - s if match hex_bits_14_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_14_backwards : string -> bits(14) -function hex_bits_14_backwards s = - match hex_bits_14_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_15 : bits(15) <-> string -val hex_bits_15_forwards = "decimal_string_of_bits" : bits(15) -> string -val hex_bits_15_forwards_matches : bits(15) -> bool -function hex_bits_15_forwards_matches bv = true -val "hex_bits_15_matches_prefix" : string -> option((bits(15), nat)) -val hex_bits_15_backwards_matches : string -> bool -function hex_bits_15_backwards_matches s = match s { - s if match hex_bits_15_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_15_backwards : string -> bits(15) -function hex_bits_15_backwards s = - match hex_bits_15_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_16 : bits(16) <-> string -val hex_bits_16_forwards = "decimal_string_of_bits" : bits(16) -> string -val hex_bits_16_forwards_matches : bits(16) -> bool -function hex_bits_16_forwards_matches bv = true -val "hex_bits_16_matches_prefix" : string -> option((bits(16), nat)) -val hex_bits_16_backwards_matches : string -> bool -function hex_bits_16_backwards_matches s = match s { - s if match hex_bits_16_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_16_backwards : string -> bits(16) -function hex_bits_16_backwards s = - match hex_bits_16_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_17 : bits(17) <-> string -val hex_bits_17_forwards = "decimal_string_of_bits" : bits(17) -> string -val hex_bits_17_forwards_matches : bits(17) -> bool -function hex_bits_17_forwards_matches bv = true -val "hex_bits_17_matches_prefix" : string -> option((bits(17), nat)) -val hex_bits_17_backwards_matches : string -> bool -function hex_bits_17_backwards_matches s = match s { - s if match hex_bits_17_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_17_backwards : string -> bits(17) -function hex_bits_17_backwards s = - match hex_bits_17_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_18 : bits(18) <-> string -val hex_bits_18_forwards = "decimal_string_of_bits" : bits(18) -> string -val hex_bits_18_forwards_matches : bits(18) -> bool -function hex_bits_18_forwards_matches bv = true -val "hex_bits_18_matches_prefix" : string -> option((bits(18), nat)) -val hex_bits_18_backwards_matches : string -> bool -function hex_bits_18_backwards_matches s = match s { - s if match hex_bits_18_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_18_backwards : string -> bits(18) -function hex_bits_18_backwards s = - match hex_bits_18_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_19 : bits(19) <-> string -val hex_bits_19_forwards = "decimal_string_of_bits" : bits(19) -> string -val hex_bits_19_forwards_matches : bits(19) -> bool -function hex_bits_19_forwards_matches bv = true -val "hex_bits_19_matches_prefix" : string -> option((bits(19), nat)) -val hex_bits_19_backwards_matches : string -> bool -function hex_bits_19_backwards_matches s = match s { - s if match hex_bits_19_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_19_backwards : string -> bits(19) -function hex_bits_19_backwards s = - match hex_bits_19_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_20 : bits(20) <-> string -val hex_bits_20_forwards = "decimal_string_of_bits" : bits(20) -> string -val hex_bits_20_forwards_matches : bits(20) -> bool -function hex_bits_20_forwards_matches bv = true -val "hex_bits_20_matches_prefix" : string -> option((bits(20), nat)) -val hex_bits_20_backwards_matches : string -> bool -function hex_bits_20_backwards_matches s = match s { - s if match hex_bits_20_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_20_backwards : string -> bits(20) -function hex_bits_20_backwards s = - match hex_bits_20_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_21 : bits(21) <-> string -val hex_bits_21_forwards = "decimal_string_of_bits" : bits(21) -> string -val hex_bits_21_forwards_matches : bits(21) -> bool -function hex_bits_21_forwards_matches bv = true -val "hex_bits_21_matches_prefix" : string -> option((bits(21), nat)) -val hex_bits_21_backwards_matches : string -> bool -function hex_bits_21_backwards_matches s = match s { - s if match hex_bits_21_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_21_backwards : string -> bits(21) -function hex_bits_21_backwards s = - match hex_bits_21_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_22 : bits(22) <-> string -val hex_bits_22_forwards = "decimal_string_of_bits" : bits(22) -> string -val hex_bits_22_forwards_matches : bits(22) -> bool -function hex_bits_22_forwards_matches bv = true -val "hex_bits_22_matches_prefix" : string -> option((bits(22), nat)) -val hex_bits_22_backwards_matches : string -> bool -function hex_bits_22_backwards_matches s = match s { - s if match hex_bits_22_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_22_backwards : string -> bits(22) -function hex_bits_22_backwards s = - match hex_bits_22_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_23 : bits(23) <-> string -val hex_bits_23_forwards = "decimal_string_of_bits" : bits(23) -> string -val hex_bits_23_forwards_matches : bits(23) -> bool -function hex_bits_23_forwards_matches bv = true -val "hex_bits_23_matches_prefix" : string -> option((bits(23), nat)) -val hex_bits_23_backwards_matches : string -> bool -function hex_bits_23_backwards_matches s = match s { - s if match hex_bits_23_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_23_backwards : string -> bits(23) -function hex_bits_23_backwards s = - match hex_bits_23_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_24 : bits(24) <-> string -val hex_bits_24_forwards = "decimal_string_of_bits" : bits(24) -> string -val hex_bits_24_forwards_matches : bits(24) -> bool -function hex_bits_24_forwards_matches bv = true -val "hex_bits_24_matches_prefix" : string -> option((bits(24), nat)) -val hex_bits_24_backwards_matches : string -> bool -function hex_bits_24_backwards_matches s = match s { - s if match hex_bits_24_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_24_backwards : string -> bits(24) -function hex_bits_24_backwards s = - match hex_bits_24_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_25 : bits(25) <-> string -val hex_bits_25_forwards = "decimal_string_of_bits" : bits(25) -> string -val hex_bits_25_forwards_matches : bits(25) -> bool -function hex_bits_25_forwards_matches bv = true -val "hex_bits_25_matches_prefix" : string -> option((bits(25), nat)) -val hex_bits_25_backwards_matches : string -> bool -function hex_bits_25_backwards_matches s = match s { - s if match hex_bits_25_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_25_backwards : string -> bits(25) -function hex_bits_25_backwards s = - match hex_bits_25_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_26 : bits(26) <-> string -val hex_bits_26_forwards = "decimal_string_of_bits" : bits(26) -> string -val hex_bits_26_forwards_matches : bits(26) -> bool -function hex_bits_26_forwards_matches bv = true -val "hex_bits_26_matches_prefix" : string -> option((bits(26), nat)) -val hex_bits_26_backwards_matches : string -> bool -function hex_bits_26_backwards_matches s = match s { - s if match hex_bits_26_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_26_backwards : string -> bits(26) -function hex_bits_26_backwards s = - match hex_bits_26_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_27 : bits(27) <-> string -val hex_bits_27_forwards = "decimal_string_of_bits" : bits(27) -> string -val hex_bits_27_forwards_matches : bits(27) -> bool -function hex_bits_27_forwards_matches bv = true -val "hex_bits_27_matches_prefix" : string -> option((bits(27), nat)) -val hex_bits_27_backwards_matches : string -> bool -function hex_bits_27_backwards_matches s = match s { - s if match hex_bits_27_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_27_backwards : string -> bits(27) -function hex_bits_27_backwards s = - match hex_bits_27_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_28 : bits(28) <-> string -val hex_bits_28_forwards = "decimal_string_of_bits" : bits(28) -> string -val hex_bits_28_forwards_matches : bits(28) -> bool -function hex_bits_28_forwards_matches bv = true -val "hex_bits_28_matches_prefix" : string -> option((bits(28), nat)) -val hex_bits_28_backwards_matches : string -> bool -function hex_bits_28_backwards_matches s = match s { - s if match hex_bits_28_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_28_backwards : string -> bits(28) -function hex_bits_28_backwards s = - match hex_bits_28_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_29 : bits(29) <-> string -val hex_bits_29_forwards = "decimal_string_of_bits" : bits(29) -> string -val hex_bits_29_forwards_matches : bits(29) -> bool -function hex_bits_29_forwards_matches bv = true -val "hex_bits_29_matches_prefix" : string -> option((bits(29), nat)) -val hex_bits_29_backwards_matches : string -> bool -function hex_bits_29_backwards_matches s = match s { - s if match hex_bits_29_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_29_backwards : string -> bits(29) -function hex_bits_29_backwards s = - match hex_bits_29_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_30 : bits(30) <-> string -val hex_bits_30_forwards = "decimal_string_of_bits" : bits(30) -> string -val hex_bits_30_forwards_matches : bits(30) -> bool -function hex_bits_30_forwards_matches bv = true -val "hex_bits_30_matches_prefix" : string -> option((bits(30), nat)) -val hex_bits_30_backwards_matches : string -> bool -function hex_bits_30_backwards_matches s = match s { - s if match hex_bits_30_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_30_backwards : string -> bits(30) -function hex_bits_30_backwards s = - match hex_bits_30_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_31 : bits(31) <-> string -val hex_bits_31_forwards = "decimal_string_of_bits" : bits(31) -> string -val hex_bits_31_forwards_matches : bits(31) -> bool -function hex_bits_31_forwards_matches bv = true -val "hex_bits_31_matches_prefix" : string -> option((bits(31), nat)) -val hex_bits_31_backwards_matches : string -> bool -function hex_bits_31_backwards_matches s = match s { - s if match hex_bits_31_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_31_backwards : string -> bits(31) -function hex_bits_31_backwards s = - match hex_bits_31_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_32 : bits(32) <-> string -val hex_bits_32_forwards = "decimal_string_of_bits" : bits(32) -> string -val hex_bits_32_forwards_matches : bits(32) -> bool -function hex_bits_32_forwards_matches bv = true -val "hex_bits_32_matches_prefix" : string -> option((bits(32), nat)) -val hex_bits_32_backwards_matches : string -> bool -function hex_bits_32_backwards_matches s = match s { - s if match hex_bits_32_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_32_backwards : string -> bits(32) -function hex_bits_32_backwards s = - match hex_bits_32_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_33 : bits(33) <-> string -val hex_bits_33_forwards = "decimal_string_of_bits" : bits(33) -> string -val hex_bits_33_forwards_matches : bits(33) -> bool -function hex_bits_33_forwards_matches bv = true -val "hex_bits_33_matches_prefix" : string -> option((bits(33), nat)) -val hex_bits_33_backwards_matches : string -> bool -function hex_bits_33_backwards_matches s = match s { - s if match hex_bits_33_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_33_backwards : string -> bits(33) -function hex_bits_33_backwards s = - match hex_bits_33_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_48 : bits(48) <-> string -val hex_bits_48_forwards = "decimal_string_of_bits" : bits(48) -> string -val hex_bits_48_forwards_matches : bits(48) -> bool -function hex_bits_48_forwards_matches bv = true -val "hex_bits_48_matches_prefix" : string -> option((bits(48), nat)) -val hex_bits_48_backwards_matches : string -> bool -function hex_bits_48_backwards_matches s = match s { - s if match hex_bits_48_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_48_backwards : string -> bits(48) -function hex_bits_48_backwards s = - match hex_bits_48_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val hex_bits_64 : bits(64) <-> string -val hex_bits_64_forwards = "decimal_string_of_bits" : bits(64) -> string -val hex_bits_64_forwards_matches : bits(64) -> bool -function hex_bits_64_forwards_matches bv = true -val "hex_bits_64_matches_prefix" : string -> option((bits(64), nat)) -val hex_bits_64_backwards_matches : string -> bool -function hex_bits_64_backwards_matches s = match s { - s if match hex_bits_64_matches_prefix(s) { - Some (_, n) if n == string_length(s) => true, - _ => false - } => true, - _ => false -} -val hex_bits_64_backwards : string -> bits(64) -function hex_bits_64_backwards s = - match hex_bits_64_matches_prefix(s) { - Some (bv, n) if n == string_length(s) => bv - } - -val eq_vec = {ocaml: "eq_list", lem: "eq_vec", coq: "eq_vec", c: "eq_bits"} : forall 'n. (bits('n), bits('n)) -> bool - -val eq_string = {c: "eq_string", ocaml: "eq_string", lem: "eq", coq: "generic_eq"} : (string, string) -> bool - -val eq_real = {ocaml: "eq_real", lem: "eq"} : (real, real) -> bool - -val eq_anything = {ocaml: "(fun (x, y) -> x = y)", lem: "eq", coq: "generic_eq"} : forall ('a : Type). ('a, 'a) -> bool - -val bitvector_length = {ocaml: "length", lem: "length", coq: "length_mword"} : forall 'n. bits('n) -> atom('n) -val vector_length = {ocaml: "length", lem: "length_list", coq: "vec_length"} : forall 'n ('a : Type). vector('n, dec, 'a) -> atom('n) -val list_length = {ocaml: "length", lem: "length_list", coq: "length_list"} : forall ('a : Type). list('a) -> int - -overload length = {bitvector_length, vector_length, list_length} - -val "reg_deref" : forall ('a : Type). register('a) -> 'a effect {rreg} -/* sneaky deref with no effect necessary for bitfield writes */ -val _reg_deref = "reg_deref" : forall ('a : Type). register('a) -> 'a - -overload operator == = {eq_vec, eq_string, eq_real, eq_anything} - -val vector_subrange = { - ocaml: "subrange", - lem: "subrange_vec_dec", - c: "vector_subrange", - coq: "subrange_vec_dec" -} : forall ('n : Int) ('m : Int) ('o : Int), 0 <= 'o <= 'm < 'n. - (bits('n), atom('m), atom('o)) -> bits('m - 'o + 1) -/* -val vector_subrange = {ocaml: "subrange", lem: "subrange_vec_dec", coq: "subrange_vec_dec"} : forall ('n : Int) ('m : Int) ('o : Int), 'o <= 'm <= 'n. - (bits('n), atom('m), atom('o)) -> bits('m - ('o - 1)) -*/ - -val bitvector_access = {c: "bitvector_access", ocaml: "access", lem: "access_vec_dec", coq: "access_vec_dec"} : forall ('n : Int) ('m : Int), 0 <= 'm < 'n. - (bits('n), atom('m)) -> bit - -val any_vector_access = {ocaml: "access", lem: "access_list_dec", coq: "vec_access_dec"} : forall ('n : Int) ('m : Int) ('a : Type), 0 <= 'm < 'n. - (vector('n, dec, 'a), atom('m)) -> 'a - -overload vector_access = {bitvector_access, any_vector_access} - -val bitvector_update = {ocaml: "update", lem: "update_vec_dec", coq: "update_vec_dec"} : forall 'n. - (bits('n), int, bit) -> bits('n) - -val any_vector_update = {ocaml: "update", lem: "update_list_dec", coq: "vector_update"} : forall 'n ('a : Type). - (vector('n, dec, 'a), int, 'a) -> vector('n, dec, 'a) - -overload vector_update = {bitvector_update, any_vector_update} - -val update_subrange = {ocaml: "update_subrange", lem: "update_subrange_vec_dec", coq: "update_subrange_vec_dec"} : forall 'n 'm 'o. - (bits('n), atom('m), atom('o), bits('m - ('o - 1))) -> bits('n) - -val vcons = {lem: "cons_vec"} : forall ('n : Int) ('a : Type). - ('a, vector('n, dec, 'a)) -> vector('n + 1, dec, 'a) - -val bitvector_concat = {c: "append", ocaml: "append", lem: "concat_vec", coq: "concat_vec"} : forall ('n : Int) ('m : Int). - (bits('n), bits('m)) -> bits('n + 'm) - -val vector_concat = {ocaml: "append", lem: "append_list"} : forall ('n : Int) ('m : Int) ('a : Type). - (vector('n, dec, 'a), vector('m, dec, 'a)) -> vector('n + 'm, dec, 'a) - -overload append = {bitvector_concat, vector_concat} - -val not_bool = {coq: "negb", _: "not"} : bool -> bool - -val not_vec = {c: "not_bits", _: "not_vec"} : forall 'n. bits('n) -> bits('n) - -overload ~ = {not_bool, not_vec} - -val neq_vec = {lem: "neq"} : forall 'n. (bits('n), bits('n)) -> bool - -function neq_vec (x, y) = not_bool(eq_vec(x, y)) - -val neq_anything = {lem: "neq", coq: "generic_neq"} : forall ('a : Type). ('a, 'a) -> bool - -function neq_anything (x, y) = not_bool(x == y) - -overload operator != = {neq_vec, neq_anything} - -val and_vec = {lem: "and_vec", c: "and_bits", coq: "and_vec", ocaml: "and_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) - -overload operator & = {and_vec} - -val or_vec = {lem: "or_vec", c: "or_bits", coq: "or_vec", ocaml: "or_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) - -overload operator | = {or_vec} - -val unsigned = {ocaml: "uint", lem: "uint", coq: "uint", c: "sail_unsigned"} : forall 'n. bits('n) -> range(0, 2 ^ 'n - 1) - -val signed = {ocaml: "sint", lem: "sint", coq: "sint", c: "sail_signed"} : forall 'n. bits('n) -> range(- (2 ^ ('n - 1)), 2 ^ ('n - 1) - 1) - -val hex_slice = "hex_slice" : forall 'n 'm, 'n >= 'm. (string, atom('n), atom('m)) -> bits('n - 'm) - -val __SetSlice_bits = "set_slice" : forall 'n 'm. - (atom('n), atom('m), bits('n), int, bits('m)) -> bits('n) - -val __SetSlice_int = "set_slice_int" : forall 'w. (atom('w), int, int, bits('w)) -> int - -val __raw_SetSlice_int : forall 'w. (atom('w), int, int, bits('w)) -> int - -val __raw_GetSlice_int = "get_slice_int" : forall 'w, 'w >= 0. (atom('w), int, int) -> bits('w) - -val __GetSlice_int : forall 'n, 'n >= 0. (atom('n), int, int) -> bits('n) - -function __GetSlice_int (n, m, o) = __raw_GetSlice_int(n, m, o) - -val __raw_SetSlice_bits : forall 'n 'w. - (atom('n), atom('w), bits('n), int, bits('w)) -> bits('n) - -val __raw_GetSlice_bits : forall 'n 'w, 'w >= 0. - (atom('n), atom('w), bits('n), int) -> bits('w) - -val "shiftl" : forall 'm. (bits('m), int) -> bits('m) -val "shiftr" : forall 'm. (bits('m), int) -> bits('m) - -val __SignExtendSlice = {lem: "exts_slice"} : forall 'm. (bits('m), int, int) -> bits('m) - -val __ZeroExtendSlice = {lem: "extz_slice"} : forall 'm. (bits('m), int, int) -> bits('m) - -val cast cast_unit_vec : bit -> bits(1) - -function cast_unit_vec b = match b { - bitzero => 0b0, - bitone => 0b1 -} - -val putchar = "putchar" : forall ('a : Type). 'a -> unit - -val concat_str = {c: "concat_str", ocaml: "concat_str", lem: "stringAppend", coq: "String.append"} : (string, string) -> string - -val string_of_int = {c: "string_of_int", ocaml: "string_of_int", lem: "stringFromInteger", coq: "string_of_int"} : int -> string - -val DecStr : int -> string - -val HexStr : int -> string - -val BitStr = "string_of_bits" : forall 'n. bits('n) -> string -val "decimal_string_of_bits" : forall 'n. bits('n) -> string - -val xor_vec = {c: "xor_bits", _: "xor_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) - -val int_power = {ocaml: "int_power", lem: "pow", coq: "pow", c: "pow_int"} : (int, int) -> int - -val real_power = {ocaml: "real_power", lem: "realPowInteger"} : (real, int) -> real - -overload operator ^ = {xor_vec, int_power, real_power, concat_str} - -val add_atom = {ocaml: "add_int", lem: "integerAdd", c: "add_int", coq: "Z.add"} : forall 'n 'm. - (int('n), int('m)) -> int('n + 'm) - -val add_vec = {c: "add_bits", _: "add_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) - -val add_vec_int = {c: "add_bits_int", _: "add_vec_int"} : forall 'n. (bits('n), int) -> bits('n) - -val add_real = {ocaml: "add_real", lem: "realAdd"} : (real, real) -> real - -overload operator + = {add_atom, add_vec, add_vec_int, add_real} - -val sub_atom = {ocaml: "sub_int", c: "sub_int", lem: "integerMinus", coq: "sub_range"} : forall 'n 'm. - (int('n), int('m)) -> int('n - 'm) - -val sub_int = {ocaml: "sub_int", c: "sub_int", lem: "integerMinus", coq: "Z.sub"} : (int, int) -> int -val sub_nat = {ocaml: "(fun (x,y) -> let n = sub_int (x,y) in if Big_int.less_equal n Big_int.zero then Big_int.zero else n)", - lem: "integerMinus", coq: "sub_nat", c: "sub_nat"} - : (nat, nat) -> nat - -val sub_vec = {c: "sub_bits", _: "sub_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) - -val sub_vec_int = {c: "sub_bits_int", _: "sub_vec_int"} : forall 'n. (bits('n), int) -> bits('n) - -val sub_real = {ocaml: "sub_real", lem: "realMinus"} : (real, real) -> real - -val negate_atom = {ocaml: "negate", lem: "integerNegate", coq: "negate_range"} : forall 'n 'm. atom('n) -> atom(- 'n) - -val negate_int = {ocaml: "negate", lem: "integerNegate", coq: "Z.opp"} : int -> int - -val negate_real = {ocaml: "Num.minus_num", lem: "realNegate"} : real -> real - -overload operator - = {sub_atom, sub_int, sub_vec, sub_vec_int, sub_real} - -overload negate = {negate_range, negate_int, negate_real} - -val mult_atom = {ocaml: "mult", lem: "integerMult", c: "mult_int", coq: "Z.mul"} : forall 'n 'm. - (atom('n), atom('m)) -> atom('n * 'm) - -val mult_int = {ocaml: "mult", lem: "integerMult", coq: "Z.mul"} : (int, int) -> int - -val mult_real = {ocaml: "mult_real", lem: "realMult"} : (real, real) -> real - -overload operator * = {mult_atom, mult_int, mult_real} - -val Sqrt = {ocaml: "sqrt_real", lem: "realSqrt"} : real -> real - -val gteq_real = {ocaml: "gteq_real", lem: "gteq"} : (real, real) -> bool - -overload operator >= = {gteq_real} - -val lteq_real = {ocaml: "lteq_real", lem: "lteq"} : (real, real) -> bool - -overload operator <= = {lteq_real} - -val gt_real = {ocaml: "gt_real", lem: "gt"} : (real, real) -> bool - -overload operator > = {gt_real} - -val lt_real = {ocaml: "lt_real", lem: "lt"} : (real, real) -> bool - -overload operator < = {lt_real} - -val RoundDown = {ocaml: "round_down", lem: "realFloor"} : real -> int - -val RoundUp = {ocaml: "round_up", lem: "realCeiling"} : real -> int - -val abs_int = {ocaml: "abs_int", lem: "abs", coq: "Z.abs"} : int -> int - -val abs_real = {ocaml: "abs_real", lem: "abs"} : real -> real - -overload abs = {abs_int, abs_real} - -val quotient_nat = {ocaml: "quotient", lem: "integerDiv"} : (nat, nat) -> nat - -val quotient_real = {ocaml: "quotient_real", lem: "realDiv"} : (real, real) -> real - -val quotient = {ocaml: "quotient", lem: "integerDiv"} : (int, int) -> int - -overload operator / = {quotient_nat, quotient, quotient_real} - -val quot_round_zero = {ocaml: "quot_round_zero", lem: "hardware_quot", c: "tdiv_int"} : (int, int) -> int -val rem_round_zero = {ocaml: "rem_round_zero", lem: "hardware_mod", c: "tmod_int"} : (int, int) -> int - -val modulus = {ocaml: "modulus", lem: "hardware_mod", c: "tmod_int"} : (int, int) -> int - -overload operator % = {modulus} - -val Real = {ocaml: "Num.num_of_big_int", lem: "realFromInteger"} : int -> real - -val shl_int = "shl_int" : (int, int) -> int -val shr_int = "shr_int" : (int, int) -> int -val lor_int = "lor_int" : (int, int) -> int -val land_int = "land_int" : (int, int) -> int -val lxor_int = "lxor_int" : (int, int) -> int - -val min_nat = {ocaml: "min_int", lem: "min", c: "min_int"} : (nat, nat) -> nat - -val min_int = {ocaml: "min_int", lem: "min", coq: "Z.min", c: "min_int"} : (int, int) -> int - -val max_nat = {ocaml: "max_int", lem: "max", c: "max_int"} : (nat, nat) -> nat - -val max_int = {ocaml: "max_int", lem: "max", coq: "Z.max", c: "max_int"} : (int, int) -> int - -overload min = {min_nat, min_int} - -overload max = {max_nat, max_int} - -val __WriteRAM = "write_ram" : forall 'n 'm. - (atom('m), atom('n), bits('m), bits('m), bits(8 * 'n)) -> bool effect {wmv} - -val __RISCV_write : forall 'n. (bits(64), atom('n), bits(8 * 'n)) -> bool effect {wmv} -function __RISCV_write (addr, width, data) = { - __WriteRAM(64, width, 0x0000_0000_0000_0000, addr, data) -} - -val __TraceMemoryWrite : forall 'n 'm. - (atom('n), bits('m), bits(8 * 'n)) -> unit - -val __ReadRAM = { lem: "MEMr", _ : "read_ram" } : forall 'n 'm, 'n >= 0. - (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem} - -val __ReadRAM_acquire = { lem: "MEMr_acquire", _ : "read_ram" } : forall 'n 'm, 'n >= 0. - (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem} - -val __ReadRAM_strong_acquire = { lem: "MEMr_strong_acquire", _ : "read_ram" } : forall 'n 'm, 'n >= 0. - (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem} - -val __ReadRAM_reserved = { lem: "MEMr_reserved", _ : "read_ram" } : forall 'n 'm, 'n >= 0. - (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem} - -val __ReadRAM_reserved_acquire = { lem: "MEMr_reserved_acquire", _ : "read_ram" } : forall 'n 'm, 'n >= 0. - (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem} - -val __ReadRAM_reserved_strong_acquire = { lem: "MEMr_reserved_strong_acquire", _ : "read_ram" } : forall 'n 'm, 'n >= 0. - (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem} - -val __RISCV_read : forall 'n, 'n >= 0. (bits(64), atom('n), bool, bool, bool) -> option(bits(8 * 'n)) effect {rmem} -function __RISCV_read (addr, width, aq, rl, res) = - match (aq, rl, res) { - (false, false, false) => Some(__ReadRAM(64, width, 0x0000_0000_0000_0000, addr)), - (true, false, false) => Some(__ReadRAM_acquire(64, width, 0x0000_0000_0000_0000, addr)), - (true, true, false) => Some(__ReadRAM_strong_acquire(64, width, 0x0000_0000_0000_0000, addr)), - (false, false, true) => Some(__ReadRAM_reserved(64, width, 0x0000_0000_0000_0000, addr)), - (true, false, true) => Some(__ReadRAM_reserved_acquire(64, width, 0x0000_0000_0000_0000, addr)), - (true, true, true) => Some(__ReadRAM_reserved_strong_acquire(64, width, 0x0000_0000_0000_0000, addr)), - (false, true, false) => None(), - (false, true, true) => None() - } - -val __TraceMemoryRead : forall 'n 'm. (atom('n), bits('m), bits(8 * 'n)) -> unit - -val replicate_bits = "replicate_bits" : forall 'n 'm, 'm >= 0. (bits('n), atom('m)) -> bits('n * 'm) - -val cast ex_nat : nat -> {'n, 'n >= 0. atom('n)} - -function ex_nat 'n = n - -val cast ex_int : int -> {'n, true. atom('n)} - -function ex_int 'n = n - -/* -val cast ex_range : forall 'n 'm. range('n, 'm) -> {'o, 'n <= 'o <= 'm. atom('o)} - -function ex_range (n as 'N) = n -*/ - -val coerce_int_nat : int -> nat effect {escape} - -function coerce_int_nat 'x = { - assert(constraint('x >= 0)); - x -} - -val slice = "slice" : forall ('n : Int) ('m : Int), 'm >= 0 & 'n >= 0. - (bits('m), int, atom('n)) -> bits('n) - -val pow2 = "pow2" : forall 'n. atom('n) -> atom(2 ^ 'n) - -val print = "print_endline" : string -> unit -val print_int = "print_int" : (string, int) -> unit -val print_bits = "print_bits" : forall 'n. (string, bits('n)) -> unit -val print_string = "print_string" : (string, string) -> unit - -val print_instr = {ocaml: "Platform.print_instr", c: "print_instr", _: "print_endline"} : string -> unit -val print_reg = {ocaml: "Platform.print_reg", c: "print_reg", _: "print_endline"} : string -> unit -val print_mem = {ocaml: "Platform.print_mem_access", c: "print_mem_access", _: "print_endline"} : string -> unit -val print_platform = {ocaml: "Platform.print_platform", c: "print_platform", _: "print_endline"} : string -> unit - -val "sign_extend" : forall 'n 'm, 'm >= 'n. (bits('n), atom('m)) -> bits('m) -val "zero_extend" : forall 'n 'm, 'm >= 'n. (bits('n), atom('m)) -> bits('m) - -val EXTS : forall 'n 'm , 'm >= 'n . bits('n) -> bits('m) -val EXTZ : forall 'n 'm , 'm >= 'n . bits('n) -> bits('m) - -function EXTS v = sign_extend(v, sizeof('m)) -function EXTZ v = zero_extend(v, sizeof('m)) - -infix 4 <_s -infix 4 >=_s -infix 4 <_u -infix 4 >=_u -infix 4 <=_u - -val operator <_s : forall 'n, 'n > 0. (bits('n), bits('n)) -> bool -val operator >=_s : forall 'n, 'n > 0. (bits('n), bits('n)) -> bool -val operator <_u : forall 'n. (bits('n), bits('n)) -> bool -val operator >=_u : forall 'n. (bits('n), bits('n)) -> bool -val operator <=_u : forall 'n. (bits('n), bits('n)) -> bool - -function operator <_s (x, y) = signed(x) < signed(y) -function operator >=_s (x, y) = signed(x) >= signed(y) -function operator <_u (x, y) = unsigned(x) < unsigned(y) -function operator >=_u (x, y) = unsigned(x) >= unsigned(y) -function operator <=_u (x, y) = unsigned(x) <= unsigned(y) - -val cast bool_to_bits : bool -> bits(1) -function bool_to_bits x = if x then 0b1 else 0b0 - -val cast bit_to_bool : bit -> bool -function bit_to_bool b = match b { - bitone => true, - bitzero => false -} - -infix 7 >> -infix 7 << - -val operator >> = "shift_bits_right" : forall 'n 'm. (bits('n), bits('m)) -> bits('n) -val operator << = "shift_bits_left" : forall 'n 'm. (bits('n), bits('m)) -> bits('n) - -val vector64 : int -> bits(64) - -function vector64 n = __raw_GetSlice_int(64, n, 0) - -val to_bits : forall 'l, 'l >= 0.(atom('l), int) -> bits('l) -function to_bits (l, n) = __raw_GetSlice_int(l, n, 0) - -val vector_update_subrange_dec = {ocaml: "update_subrange", c: "vector_update_subrange", lem: "update_subrange_vec_dec", coq: "update_subrange_vec_dec"} : forall 'n 'm 'o. - (bits('n), atom('m), atom('o), bits('m - ('o - 1))) -> bits('n) - -val vector_update_subrange_inc = {ocaml: "update_subrange", lem: "update_subrange_vec_inc"} : forall 'n 'm 'o. - (vector('n, inc, bit), atom('m), atom('o), vector('o - ('m - 1), inc, bit)) -> vector('n, inc, bit) - -overload vector_update_subrange = {vector_update_subrange_dec, vector_update_subrange_inc} - -/* Ideally these would be sail builtin */ - -function shift_right_arith64 (v : bits(64), shift : bits(6)) -> bits(64) = - let v128 : bits(128) = EXTS(v) in - (v128 >> shift)[63..0] - -function shift_right_arith32 (v : bits(32), shift : bits(5)) -> bits(32) = - let v64 : bits(64) = EXTS(v) in - (v64 >> shift)[31..0] - -/* Special version of zero_extend that the Lem back-end knows will be at a - case split on 'm and uses a more generic type for. (Temporary hack, honest) */ -val zero_extend_type_hack = "zero_extend" : forall 'n 'm, 'm >= 'n. (bits('n), atom('m)) -> bits('m) - - -val n_leading_spaces : string -> {'n, 'n >= 0. int('n)} -function n_leading_spaces s = - match s { - "" => 0, - _ => match string_take(s, 1) { - " " => 1 + n_leading_spaces(string_drop(s, 1)), - _ => 0 - } - } - -val spc_forwards : unit -> string -function spc_forwards () = " " -val spc_backwards : string -> unit -function spc_backwards s = () -val spc_matches_prefix : string -> option((unit, nat)) -function spc_matches_prefix s = { - let n = n_leading_spaces(s); - match n { - 0 => None(), - _ => Some((), n) - } -} - -val opt_spc_forwards : unit -> string -function opt_spc_forwards () = "" -val opt_spc_backwards : string -> unit -function opt_spc_backwards s = () -val opt_spc_matches_prefix : string -> option((unit, nat)) -function opt_spc_matches_prefix s = - Some((), n_leading_spaces(s)) - -val def_spc_forwards : unit -> string -function def_spc_forwards () = " " -val def_spc_backwards : string -> unit -function def_spc_backwards s = () -val def_spc_matches_prefix : string -> option((unit, nat)) -function def_spc_matches_prefix s = opt_spc_matches_prefix(s) diff --git a/riscv/reset_vec.S b/riscv/reset_vec.S deleted file mode 100644 index 526bbc79..00000000 --- a/riscv/reset_vec.S +++ /dev/null @@ -1,12 +0,0 @@ -.global _start - -.text - -_start: - auipc t0, 0x0 - addi a1, t0, 32 - csrr a0, mhartid - ld t0, 24(t0) - jr t0 -.short 0x0000 -.word 0x00000000, 0x80000000 diff --git a/riscv/reset_vec.bin b/riscv/reset_vec.bin deleted file mode 100755 index d2d3563c..00000000 Binary files a/riscv/reset_vec.bin and /dev/null differ diff --git a/riscv/riscv.sail b/riscv/riscv.sail deleted file mode 100644 index 37553299..00000000 --- a/riscv/riscv.sail +++ /dev/null @@ -1,1569 +0,0 @@ -/* ****************************************************************** */ -union clause ast = UTYPE : (bits(20), regbits, uop) - -mapping encdec_uop : uop <-> bits(7) = { - RISCV_LUI <-> 0b0110111, - RISCV_AUIPC <-> 0b0010111 -} - -mapping clause encdec = UTYPE(imm, rd, op) <-> imm @ rd @ encdec_uop(op) - -function clause execute UTYPE(imm, rd, op) = { - let off : xlenbits = EXTS(imm @ 0x000); - let ret : xlenbits = match op { - RISCV_LUI => off, - RISCV_AUIPC => PC + off - }; - X(rd) = ret; - true -} - -mapping utype_mnemonic : uop <-> string = { - RISCV_LUI <-> "lui", - RISCV_AUIPC <-> "auipc" -} - -mapping clause assembly = UTYPE(imm, rd, op) - <-> utype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_20(imm) - -/* ****************************************************************** */ -union clause ast = RISCV_JAL : (bits(21), regbits) - -mapping clause encdec = RISCV_JAL(imm_19 @ imm_7_0 @ imm_8 @ imm_18_13 @ imm_12_9 @ 0b0, rd) - <-> imm_19 : bits(1) @ imm_18_13 : bits(6) @ imm_12_9 : bits(4) @ imm_8 : bits(1) @ imm_7_0 : bits(8) @ rd @ 0b1101111 - -/* -ideally we want some syntax like - -mapping clause encdec = RISCV_JAL(imm @ 0b0, rd) <-> imm[19] @ imm[9..0] @ imm[10] @ imm[18..11] @ rd @ 0b1101111 - -match bv { - imm[19] @ imm[9..0] @ imm[10] @ imm[18..11] -> imm @ 0b0 -} - -but this is difficult -*/ - -function clause execute (RISCV_JAL(imm, rd)) = { - let pc : xlenbits = PC; - let newPC : xlenbits = pc + EXTS(imm); - if newPC[1] & (~ (haveRVC())) then { - handle_mem_exception(newPC, E_Fetch_Addr_Align); - false - } else { - X(rd) = nextPC; /* compatible with JAL and C.JAL */ - nextPC = newPC; - true - } -} -/* TODO: handle 2-byte-alignment in mappings */ - -mapping clause assembly = RISCV_JAL(imm, rd) <-> "jal" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_21(imm) - -/* ****************************************************************** */ -union clause ast = RISCV_JALR : (bits(12), regbits, regbits) - -mapping clause encdec = RISCV_JALR(imm, rs1, rd) <-> imm @ rs1 @ 0b000 @ rd @ 0b1100111 - -mapping clause assembly = RISCV_JALR(imm, rs1, rd) - <-> "jalr" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm) - -/* see riscv_jalr_seq.sail or riscv_jalr_rmem.sail for the execute clause. */ - -/* ****************************************************************** */ -union clause ast = BTYPE : (bits(13), regbits, regbits, bop) - -mapping encdec_bop : bop <-> bits(3) = { - RISCV_BEQ <-> 0b000, - RISCV_BNE <-> 0b001, - RISCV_BLT <-> 0b100, - RISCV_BGE <-> 0b101, - RISCV_BLTU <-> 0b110, - RISCV_BGEU <-> 0b111 -} - -mapping clause encdec = BTYPE(imm7_6 @ imm5_0 @ imm7_5_0 @ imm5_4_1 @ 0b0, rs2, rs1, op) - <-> imm7_6 : bits(1) @ imm7_5_0 : bits(6) @ rs2 @ rs1 @ encdec_bop(op) @ imm5_4_1 : bits(4) @ imm5_0 : bits(1) @ 0b1100011 - -function clause execute (BTYPE(imm, rs2, rs1, op)) = { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let taken : bool = match op { - RISCV_BEQ => rs1_val == rs2_val, - RISCV_BNE => rs1_val != rs2_val, - RISCV_BLT => rs1_val <_s rs2_val, - RISCV_BGE => rs1_val >=_s rs2_val, - RISCV_BLTU => rs1_val <_u rs2_val, - RISCV_BGEU => rs1_val >=_u rs2_val - }; - let newPC = PC + EXTS(imm); - if taken then { - if newPC[1] & (~ (haveRVC())) then { - handle_mem_exception(newPC, E_Fetch_Addr_Align); - false; - } else { - nextPC = newPC; - true - } - } else true -} - -mapping btype_mnemonic : bop <-> string = { - RISCV_BEQ <-> "beq", - RISCV_BNE <-> "bne", - RISCV_BLT <-> "blt", - RISCV_BGE <-> "bge", - RISCV_BLTU <-> "bltu", - RISCV_BGEU <-> "bgeu" -} - -mapping clause assembly = BTYPE(imm, rs2, rs1, op) - <-> btype_mnemonic(op) ^ spc() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) ^ sep() ^ hex_bits_13(imm) - -/* ****************************************************************** */ -union clause ast = ITYPE : (bits(12), regbits, regbits, iop) - -mapping encdec_iop : iop <-> bits(3) = { - RISCV_ADDI <-> 0b000, - RISCV_SLTI <-> 0b010, - RISCV_SLTIU <-> 0b011, - RISCV_XORI <-> 0b100, - RISCV_ORI <-> 0b110, - RISCV_ANDI <-> 0b111 -} - -mapping clause encdec = ITYPE(imm, rs1, rd, op) <-> imm @ rs1 @ encdec_iop(op) @ rd @ 0b0010011 - -function clause execute (ITYPE (imm, rs1, rd, op)) = { - let rs1_val = X(rs1); - let immext : xlenbits = EXTS(imm); - let result : xlenbits = match op { - RISCV_ADDI => rs1_val + immext, - RISCV_SLTI => EXTZ(rs1_val <_s immext), - RISCV_SLTIU => EXTZ(rs1_val <_u immext), - RISCV_XORI => rs1_val ^ immext, - RISCV_ORI => rs1_val | immext, - RISCV_ANDI => rs1_val & immext - }; - X(rd) = result; - true -} - -mapping itype_mnemonic : iop <-> string = { - RISCV_ADDI <-> "addi", - RISCV_SLTI <-> "slti", - RISCV_SLTIU <-> "sltiu", - RISCV_XORI <-> "xori", - RISCV_ORI <-> "ori", - RISCV_ANDI <-> "andi" -} - -mapping clause assembly = ITYPE(imm, rs1, rd, op) - <-> itype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm) - -/* ****************************************************************** */ -union clause ast = SHIFTIOP : (bits(6), regbits, regbits, sop) - -mapping encdec_sop : sop <-> bits(3) = { - RISCV_SLLI <-> 0b001, - RISCV_SRLI <-> 0b101, - RISCV_SRAI <-> 0b101 -} - -mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SLLI) <-> 0b000000 @ shamt @ rs1 @ 0b001 @ rd @ 0b0010011 -mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SRLI) <-> 0b000000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0010011 -mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SRAI) <-> 0b010000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0010011 - -function clause execute (SHIFTIOP(shamt, rs1, rd, op)) = { - let rs1_val = X(rs1); - let result : xlenbits = match op { - RISCV_SLLI => rs1_val << shamt, - RISCV_SRLI => rs1_val >> shamt, - RISCV_SRAI => shift_right_arith64(rs1_val, shamt) - }; - X(rd) = result; - true -} - -mapping shiftiop_mnemonic : sop <-> string = { - RISCV_SLLI <-> "slli", - RISCV_SRLI <-> "srli", - RISCV_SRAI <-> "srai" -} - -mapping clause assembly = SHIFTIOP(shamt, rs1, rd, op) - <-> shiftiop_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ hex_bits_6(shamt) - -/* ****************************************************************** */ -union clause ast = RTYPE : (regbits, regbits, regbits, rop) - -mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_ADD) <-> 0b0000000 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011 -mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_SUB) <-> 0b0100000 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0110011 -mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_SLL) <-> 0b0000000 @ rs2 @ rs1 @ 0b001 @ rd @ 0b0110011 -mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_SLT) <-> 0b0000000 @ rs2 @ rs1 @ 0b010 @ rd @ 0b0110011 -mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_SLTU) <-> 0b0000000 @ rs2 @ rs1 @ 0b011 @ rd @ 0b0110011 -mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_XOR) <-> 0b0000000 @ rs2 @ rs1 @ 0b100 @ rd @ 0b0110011 -mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_SRL) <-> 0b0000000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0110011 -mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_SRA) <-> 0b0100000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0110011 -mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_OR) <-> 0b0000000 @ rs2 @ rs1 @ 0b110 @ rd @ 0b0110011 -mapping clause encdec = RTYPE(rs2, rs1, rd, RISCV_AND) <-> 0b0000000 @ rs2 @ rs1 @ 0b111 @ rd @ 0b0110011 - -function clause execute (RTYPE(rs2, rs1, rd, op)) = { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let result : xlenbits = match op { - RISCV_ADD => rs1_val + rs2_val, - RISCV_SUB => rs1_val - rs2_val, - RISCV_SLL => rs1_val << (rs2_val[5..0]), - RISCV_SLT => EXTZ(rs1_val <_s rs2_val), - RISCV_SLTU => EXTZ(rs1_val <_u rs2_val), - RISCV_XOR => rs1_val ^ rs2_val, - RISCV_SRL => rs1_val >> (rs2_val[5..0]), - RISCV_SRA => shift_right_arith64(rs1_val, rs2_val[5..0]), - RISCV_OR => rs1_val | rs2_val, - RISCV_AND => rs1_val & rs2_val - }; - X(rd) = result; - true -} - -mapping rtype_mnemonic : rop <-> string = { - RISCV_ADD <-> "add", - RISCV_SUB <-> "sub", - RISCV_SLL <-> "sll", - RISCV_SLT <-> "slt", - RISCV_SLTU <-> "sltu", - RISCV_XOR <-> "xor", - RISCV_SRL <-> "srl", - RISCV_SRA <-> "sra", - RISCV_OR <-> "or", - RISCV_AND <-> "and" -} - -mapping clause assembly = RTYPE(rs2, rs1, rd, op) - <-> rtype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) - -/* ****************************************************************** */ -union clause ast = LOAD : (bits(12), regbits, regbits, bool, word_width, bool, bool) - -/* Load unsigned double is only present in RV128I, not RV64I */ -/* TODO: aq/rl */ -mapping clause encdec = LOAD(imm, rs1, rd, is_unsigned, size, false, false) if size_bits(size) != 0b11 | not_bool(is_unsigned) - <-> imm @ rs1 @ bool_bits(is_unsigned) @ size_bits(size) @ rd @ 0b0000011 if size_bits(size) != 0b11 | not_bool(is_unsigned) - -val extend_value : forall 'n, 0 < 'n <= 8. (bool, MemoryOpResult(bits(8 * 'n))) -> MemoryOpResult(xlenbits) -function extend_value(is_unsigned, value) = match (value) { - MemValue(v) => MemValue(if is_unsigned then EXTZ(v) else EXTS(v) : xlenbits), - MemException(e) => MemException(e) -} - -val process_load : forall 'n, 0 < 'n <= 8. (regbits, xlenbits, MemoryOpResult(bits(8 * 'n)), bool) -> bool effect {escape, rreg, wreg} -function process_load(rd, addr, value, is_unsigned) = - match extend_value(is_unsigned, value) { - MemValue(result) => { X(rd) = result; true }, - MemException(e) => { handle_mem_exception(addr, e); false } - } - -function check_misaligned(vaddr : xlenbits, width : word_width) -> bool = - if plat_enable_misaligned_access() then false - else match width { - BYTE => false, - HALF => vaddr[0] == true, - WORD => vaddr[0] == true | vaddr[1] == true, - DOUBLE => vaddr[0] == true | vaddr[1] == true | vaddr[2] == true - } - -function clause execute(LOAD(imm, rs1, rd, is_unsigned, width, aq, rl)) = - let vaddr : xlenbits = X(rs1) + EXTS(imm) in - if check_misaligned(vaddr, width) - then { handle_mem_exception(vaddr, E_Load_Addr_Align); false } - else match translateAddr(vaddr, Read, Data) { - TR_Failure(e) => { handle_mem_exception(vaddr, e); false }, - TR_Address(addr) => - match width { - BYTE => process_load(rd, vaddr, mem_read(addr, 1, aq, rl, false), is_unsigned), - HALF => process_load(rd, vaddr, mem_read(addr, 2, aq, rl, false), is_unsigned), - WORD => process_load(rd, vaddr, mem_read(addr, 4, aq, rl, false), is_unsigned), - DOUBLE => process_load(rd, vaddr, mem_read(addr, 8, aq, rl, false), is_unsigned) - } - } - -/* TODO FIXME: is this the actual aq/rl syntax? */ -val maybe_aq : bool <-> string -mapping maybe_aq = { - true <-> ".aq", - false <-> "" -} - -val maybe_rl : bool <-> string -mapping maybe_rl = { - true <-> ".rl", - false <-> "" -} - -val maybe_u : bool <-> string -mapping maybe_u = { - true <-> "u", - false <-> "" -} - - -mapping clause assembly = LOAD(imm, rs1, rd, is_unsigned, size, aq, rl) - <-> "l" ^ size_mnemonic(size) ^ maybe_u(is_unsigned) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm) - -/* ****************************************************************** */ -union clause ast = STORE : (bits(12), regbits, regbits, word_width, bool, bool) - -/* TODO: aq/rl */ -mapping clause encdec = STORE(imm7 @ imm5, rs2, rs1, size, false, false) - <-> imm7 : bits(7) @ rs2 @ rs1 @ 0b0 @ size_bits(size) @ imm5 : bits(5) @ 0b0100011 - -/* NOTE: Currently, we only EA if address translation is successful. - This may need revisiting. */ -function clause execute (STORE(imm, rs2, rs1, width, aq, rl)) = - let vaddr : xlenbits = X(rs1) + EXTS(imm) in - if check_misaligned(vaddr, width) - then { handle_mem_exception(vaddr, E_SAMO_Addr_Align); false } - else match translateAddr(vaddr, Write, Data) { - TR_Failure(e) => { handle_mem_exception(vaddr, e); false }, - TR_Address(addr) => { - let eares : MemoryOpResult(unit) = match width { - BYTE => mem_write_ea(addr, 1, aq, rl, false), - HALF => mem_write_ea(addr, 2, aq, rl, false), - WORD => mem_write_ea(addr, 4, aq, rl, false), - DOUBLE => mem_write_ea(addr, 8, aq, rl, false) - }; - match (eares) { - MemException(e) => { handle_mem_exception(addr, e); false }, - MemValue(_) => { - let rs2_val = X(rs2); - let res : MemoryOpResult(bool) = match width { - BYTE => mem_write_value(addr, 1, rs2_val[7..0], aq, rl, false), - HALF => mem_write_value(addr, 2, rs2_val[15..0], aq, rl, false), - WORD => mem_write_value(addr, 4, rs2_val[31..0], aq, rl, false), - DOUBLE => mem_write_value(addr, 8, rs2_val, aq, rl, false) - }; - match (res) { - MemValue(true) => true, - MemValue(false) => internal_error("store got false from mem_write_value"), - MemException(e) => { handle_mem_exception(addr, e); false } - } - } - } - } - } - -mapping clause assembly = STORE(imm, rs1, rd, size, aq, rl) - <-> "s" ^ size_mnemonic(size) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm) - - -/* ****************************************************************** */ -union clause ast = ADDIW : (bits(12), regbits, regbits) - -mapping clause encdec = ADDIW(imm, rs1, rd) <-> imm @ rs1 @ 0b000 @ rd @ 0b0011011 - -function clause execute (ADDIW(imm, rs1, rd)) = { - let result : xlenbits = EXTS(imm) + X(rs1); - X(rd) = EXTS(result[31..0]); - true -} - - -mapping clause assembly = ADDIW(imm, rs1, rd) <-> "addiw" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm) - -/* ****************************************************************** */ -union clause ast = SHIFTW : (bits(5), regbits, regbits, sop) - -mapping clause encdec = SHIFTW(shamt, rs1, rd, RISCV_SLLI) <-> 0b0000000 @ shamt @ rs1 @ 0b001 @ rd @ 0b0011011 -mapping clause encdec = SHIFTW(shamt, rs1, rd, RISCV_SRLI) <-> 0b0000000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0011011 -mapping clause encdec = SHIFTW(shamt, rs1, rd, RISCV_SRAI) <-> 0b0100000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0011011 - -function clause execute (SHIFTW(shamt, rs1, rd, op)) = { - let rs1_val = (X(rs1))[31..0]; - let result : bits(32) = match op { - RISCV_SLLI => rs1_val << shamt, - RISCV_SRLI => rs1_val >> shamt, - RISCV_SRAI => shift_right_arith32(rs1_val, shamt) - }; - X(rd) = EXTS(result); - true -} - -mapping shiftw_mnemonic : sop <-> string = { - RISCV_SLLI <-> "slli", - RISCV_SRLI <-> "srli", - RISCV_SRAI <-> "srai" -} - -mapping clause assembly = SHIFTW(shamt, rs1, rd, op) - <-> shiftw_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_5(shamt) - -/* ****************************************************************** */ -union clause ast = RTYPEW : (regbits, regbits, regbits, ropw) - -mapping clause encdec = RTYPEW(rs2, rs1, rd, RISCV_ADDW) <-> 0b0000000 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0111011 -mapping clause encdec = RTYPEW(rs2, rs1, rd, RISCV_SUBW) <-> 0b0100000 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0111011 -mapping clause encdec = RTYPEW(rs2, rs1, rd, RISCV_SLLW) <-> 0b0000000 @ rs2 @ rs1 @ 0b001 @ rd @ 0b0111011 -mapping clause encdec = RTYPEW(rs2, rs1, rd, RISCV_SRLW) <-> 0b0000000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0111011 -mapping clause encdec = RTYPEW(rs2, rs1, rd, RISCV_SRAW) <-> 0b0100000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0111011 - -function clause execute (RTYPEW(rs2, rs1, rd, op)) = { - let rs1_val = (X(rs1))[31..0]; - let rs2_val = (X(rs2))[31..0]; - let result : bits(32) = match op { - RISCV_ADDW => rs1_val + rs2_val, - RISCV_SUBW => rs1_val - rs2_val, - RISCV_SLLW => rs1_val << (rs2_val[4..0]), - RISCV_SRLW => rs1_val >> (rs2_val[4..0]), - RISCV_SRAW => shift_right_arith32(rs1_val, rs2_val[4..0]) - }; - X(rd) = EXTS(result); - true -} - -mapping rtypew_mnemonic : ropw <-> string = { - RISCV_ADDW <-> "addw", - RISCV_SUBW <-> "subw", - RISCV_SLLW <-> "sllw", - RISCV_SRLW <-> "srlw", - RISCV_SRAW <-> "sraw" -} - -mapping clause assembly = RTYPEW(rs2, rs1, rd, op) - <-> rtypew_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) - -/* ****************************************************************** */ -union clause ast = SHIFTIWOP : (bits(5), regbits, regbits, sopw) - -mapping clause encdec = SHIFTIWOP(shamt, rs1, rd, RISCV_SLLIW) <-> 0b0000000 @ shamt @ rs1 @ 0b001 @ rd @ 0b0011011 -mapping clause encdec = SHIFTIWOP(shamt, rs1, rd, RISCV_SRLIW) <-> 0b0000000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0011011 -mapping clause encdec = SHIFTIWOP(shamt, rs1, rd, RISCV_SRAIW) <-> 0b0100000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0011011 - -function clause execute (SHIFTIWOP(shamt, rs1, rd, op)) = { - let rs1_val = X(rs1); - let result : xlenbits = match op { - RISCV_SLLIW => EXTS(rs1_val[31..0] << shamt), - RISCV_SRLIW => EXTS(rs1_val[31..0] >> shamt), - RISCV_SRAIW => EXTS(shift_right_arith32(rs1_val[31..0], shamt)) - }; - X(rd) = result; - true -} - -mapping shiftiwop_mnemonic : sopw <-> string = { - RISCV_SLLIW <-> "slliw", - RISCV_SRLIW <-> "srliw", - RISCV_SRAIW <-> "sraiw" -} - -mapping clause assembly = SHIFTIWOP(shamt, rs1, rd, op) - <-> shiftiwop_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ hex_bits_5(shamt) - -/* ****************************************************************** */ -/* FIXME: separate these out into separate ast variants */ -union clause ast = MUL : (regbits, regbits, regbits, bool, bool, bool) - -mapping encdec_mul_op : (bool, bool, bool) <-> bits(3) = { - (false, true, true) <-> 0b000, - (true, true, true) <-> 0b001, - (true, true, false) <-> 0b010, - (true, false, false) <-> 0b011 -} - -/* for some reason the : bits(3) here is still necessary - BUG */ -mapping clause encdec = MUL(rs2, rs1, rd, high, signed1, signed2) - <-> 0b0000001 @ rs2 @ rs1 @ encdec_mul_op(high, signed1, signed2) : bits(3) @ rd @ 0b0110011 - -function clause execute (MUL(rs2, rs1, rd, high, signed1, signed2)) = { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let rs1_int : int = if signed1 then signed(rs1_val) else unsigned(rs1_val); - let rs2_int : int = if signed2 then signed(rs2_val) else unsigned(rs2_val); - let result128 = to_bits(128, rs1_int * rs2_int); - let result = if high then result128[127..64] else result128[63..0]; - X(rd) = result; - true -} - -mapping mul_mnemonic : (bool, bool, bool) <-> string = { - (false, true, true) <-> "mul", - (true, true, true) <-> "mulh", - (true, true, false) <-> "mulhsu", - (true, false, false) <-> "mulhu" -} - -mapping clause assembly = MUL(rs2, rs1, rd, high, signed1, signed2) <-> mul_mnemonic(high, signed1, signed2) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) - -/* ****************************************************************** */ -union clause ast = DIV : (regbits, regbits, regbits, bool) - -mapping clause encdec = DIV(rs2, rs1, rd, s) <-> 0b0000001 @ rs2 @ rs1 @ 0b10 @ bool_not_bits(s) @ rd @ 0b0110011 - -function clause execute (DIV(rs2, rs1, rd, s)) = { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val); - let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); - let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int); - let q': int = if s & q > xlen_max_signed then xlen_min_signed else q; /* check for signed overflow */ - X(rd) = to_bits(xlen, q'); - true -} - -mapping maybe_not_u : bool <-> string = { - false <-> "u", - true <-> "" -} - -mapping clause assembly = DIV(rs2, rs1, rd, s) - <-> "div" ^ maybe_not_u(s) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) - -/* ****************************************************************** */ -union clause ast = REM : (regbits, regbits, regbits, bool) - -mapping clause encdec = REM(rs2, rs1, rd, s) <-> 0b0000001 @ rs2 @ rs1 @ 0b11 @ bool_not_bits(s) @ rd @ 0b0110011 - -function clause execute (REM(rs2, rs1, rd, s)) = { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val); - let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); - let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int); - /* signed overflow case returns zero naturally as required due to -1 divisor */ - X(rd) = to_bits(xlen, r); - true -} - -mapping clause assembly = REM(rs2, rs1, rd, s) <-> "rem" ^ maybe_not_u(s) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) - -/* ****************************************************************** */ -union clause ast = MULW : (regbits, regbits, regbits) - -mapping clause encdec = MULW(rs2, rs1, rd) <-> 0b0000001 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0111011 - -function clause execute (MULW(rs2, rs1, rd)) = { - let rs1_val = X(rs1)[31..0]; - let rs2_val = X(rs2)[31..0]; - let rs1_int : int = signed(rs1_val); - let rs2_int : int = signed(rs2_val); - let result32 = to_bits(64, rs1_int * rs2_int)[31..0]; /* XXX surprising behaviour of to_bits requires expansion to 64 bits followed by truncation... */ - let result : xlenbits = EXTS(result32); - X(rd) = result; - true -} - -mapping clause assembly = MULW(rs2, rs1, rd) - <-> "mulw" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) - -/* ****************************************************************** */ -union clause ast = DIVW : (regbits, regbits, regbits, bool) - -mapping clause encdec = DIVW(rs2, rs1, rd, s) <-> 0b0000001 @ rs2 @ rs1 @ 0b10 @ bool_not_bits(s) @ rd @ 0b0111011 - -function clause execute (DIVW(rs2, rs1, rd, s)) = { - let rs1_val = X(rs1)[31..0]; - let rs2_val = X(rs2)[31..0]; - let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val); - let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); - let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int); - let q': int = if s & q > (2 ^ 31 - 1) then (0 - 2^31) else q; /* check for signed overflow */ - X(rd) = EXTS(to_bits(32, q')); - true -} - -mapping clause assembly = DIVW(rs2, rs1, rd, s) - <-> "div" ^ maybe_not_u(s) ^ "w" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) - -/* ****************************************************************** */ -union clause ast = REMW : (regbits, regbits, regbits, bool) - -mapping clause encdec = REMW(rs2, rs1, rd, s) <-> 0b0000001 @ rs2 @ rs1 @ 0b11 @ bool_not_bits(s) @ rd @ 0b0111011 - -function clause execute (REMW(rs2, rs1, rd, s)) = { - let rs1_val = X(rs1)[31..0]; - let rs2_val = X(rs2)[31..0]; - let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val); - let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); - let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int); - /* signed overflow case returns zero naturally as required due to -1 divisor */ - X(rd) = EXTS(to_bits(32, r)); - true -} - -mapping clause assembly = REMW(rs2, rs1, rd, s) <-> "rem" ^ maybe_not_u(s) ^ "w" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) - -/* ****************************************************************** */ -union clause ast = FENCE : (bits(4), bits(4)) - -mapping clause encdec = FENCE(pred, succ) <-> 0b0000 @ pred @ succ @ 0b00000 @ 0b000 @ 0b00000 @ 0b0001111 - -function clause execute (FENCE(pred, succ)) = { - match (pred, succ) { - (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => MEM_fence_rw_rw(), - (_ : bits(2) @ 0b10, _ : bits(2) @ 0b11) => MEM_fence_r_rw(), - (_ : bits(2) @ 0b10, _ : bits(2) @ 0b10) => MEM_fence_r_r(), - (_ : bits(2) @ 0b11, _ : bits(2) @ 0b01) => MEM_fence_rw_w(), - (_ : bits(2) @ 0b01, _ : bits(2) @ 0b01) => MEM_fence_w_w(), - (_ : bits(2) @ 0b01, _ : bits(2) @ 0b11) => MEM_fence_w_rw(), - (_ : bits(2) @ 0b11, _ : bits(2) @ 0b10) => MEM_fence_rw_r(), - (_ : bits(2) @ 0b10, _ : bits(2) @ 0b01) => MEM_fence_r_w(), - (_ : bits(2) @ 0b01, _ : bits(2) @ 0b10) => MEM_fence_w_r(), - - (_ : bits(2) @ 0b00, _ : bits(2) @ 0b00) => (), - - _ => { print("FIXME: unsupported fence"); - () } - }; - true -} - -mapping bit_maybe_r : bits(1) <-> string = { - 0b1 <-> "r", - 0b0 <-> "" -} - -mapping bit_maybe_w : bits(1) <-> string = { - 0b1 <-> "w", - 0b0 <-> "" -} - -mapping bit_maybe_i : bits(1) <-> string = { - 0b1 <-> "i", - 0b0 <-> "" -} - -mapping bit_maybe_o : bits(1) <-> string = { - 0b1 <-> "o", - 0b0 <-> "" -} - -mapping fence_bits : bits(4) <-> string = { - i : bits(1) @ o : bits(1) @ r : bits(1) @ w : bits(1) <-> bit_maybe_i(i) ^ bit_maybe_o(o) ^ bit_maybe_r(r) ^ bit_maybe_w(w) -} - -mapping clause assembly = FENCE(pred, succ) <-> "fence" ^ spc() ^ fence_bits(pred) ^ sep() ^ fence_bits(succ) - -/* ****************************************************************** */ -union clause ast = FENCEI : unit - -mapping clause encdec = FENCEI() <-> 0b000000000000 @ 0b00000 @ 0b001 @ 0b00000 @ 0b0001111 - -/* fence.i is a nop for the memory model */ -function clause execute FENCEI() = { /* MEM_fence_i(); */ true } - - -mapping clause assembly = FENCEI() <-> "fence.i" - -/* ****************************************************************** */ -union clause ast = ECALL : unit - -mapping clause encdec = ECALL() <-> 0b000000000000 @ 0b00000 @ 0b000 @ 0b00000 @ 0b1110011 - -function clause execute ECALL() = { - let t : sync_exception = - struct { trap = match (cur_privilege) { - User => E_U_EnvCall, - Supervisor => E_S_EnvCall, - Machine => E_M_EnvCall - }, - excinfo = (None() : option(xlenbits)) }; - nextPC = handle_exception(cur_privilege, CTL_TRAP(t), PC); - false -} - -mapping clause assembly = ECALL() <-> "ecall" - -/* ****************************************************************** */ -union clause ast = MRET : unit - -mapping clause encdec = MRET() <-> 0b0011000 @ 0b00010 @ 0b00000 @ 0b000 @ 0b00000 @ 0b1110011 - -function clause execute MRET() = { - if cur_privilege == Machine - then nextPC = handle_exception(cur_privilege, CTL_MRET(), PC) - else handle_illegal(); - false -} - -mapping clause assembly = MRET() <-> "mret" - -/* ****************************************************************** */ -union clause ast = SRET : unit - -mapping clause encdec = SRET() <-> 0b0001000 @ 0b00010 @ 0b00000 @ 0b000 @ 0b00000 @ 0b1110011 - -function clause execute SRET() = { - match cur_privilege { - User => handle_illegal(), - Supervisor => if mstatus.TSR() == true - then handle_illegal() - else nextPC = handle_exception(cur_privilege, CTL_SRET(), PC), - Machine => nextPC = handle_exception(cur_privilege, CTL_SRET(), PC) - }; - false -} - -mapping clause assembly = SRET() <-> "sret" - -/* ****************************************************************** */ -union clause ast = EBREAK : unit - -mapping clause encdec = EBREAK() <-> 0b000000000001 @ 0b00000 @ 0b000 @ 0b00000 @ 0b1110011 - -function clause execute EBREAK() = { - handle_mem_exception(PC, E_Breakpoint); - false -} - -mapping clause assembly = EBREAK() <-> "ebreak" - -/* ****************************************************************** */ -union clause ast = WFI : unit - -mapping clause encdec = WFI() <-> 0b000100000101 @ 0b00000 @ 0b000 @ 0b00000 @ 0b1110011 - -function clause execute WFI() = - match cur_privilege { - Machine => { platform_wfi(); true }, - Supervisor => if mstatus.TW() == true - then { handle_illegal(); false } - else { platform_wfi(); true }, - User => { handle_illegal(); false } - } - -mapping clause assembly = WFI() <-> "wfi" - -/* ****************************************************************** */ -union clause ast = SFENCE_VMA : (regbits, regbits) - -mapping clause encdec = SFENCE_VMA(rs1, rs2) <-> 0b0001001 @ rs2 @ rs1 @ 0b000 @ 0b00000 @ 0b1110011 - -function clause execute SFENCE_VMA(rs1, rs2) = { - /* TODO: handle PMP/TLB synchronization when executed in M-mode. */ - if cur_privilege == User - then { handle_illegal(); false } - else match (architecture(mstatus.SXL()), mstatus.TVM()) { - (Some(RV64), true) => { handle_illegal(); false }, - (Some(RV64), false) => { - let addr : option(vaddr39) = if rs1 == 0 then None() else Some(X(rs1)[38 .. 0]); - let asid : option(asid64) = if rs2 == 0 then None() else Some(X(rs2)[15 .. 0]); - flushTLB(asid, addr); - true - }, - (_, _) => internal_error("unimplemented sfence architecture") - } -} - -mapping clause assembly = SFENCE_VMA(rs1, rs2) - <-> "sfence.vma" ^ spc() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) - -/* ****************************************************************** */ -// Some print utils for lr/sc. - -function aqrl_str(aq : bool, rl : bool) -> string = - match (aq, rl) { - (false, false) => "", - (false, true) => ".rl", - (true, false) => ".aq", - (true, true) => ".aqrl" - } - -function lrsc_width_str(width : word_width) -> string = - match (width) { - BYTE => ".b", - HALF => ".h", - WORD => ".w", - DOUBLE => ".d" - } - -/* ****************************************************************** */ -union clause ast = LOADRES : (bool, bool, regbits, word_width, regbits) - -mapping clause encdec = LOADRES(aq, rl, rs1, size, rd) <-> 0b00010 @ bool_bits(aq) @ bool_bits(rl) @ 0b00000 @ rs1 @ 0b0 @ size_bits(size) @ rd @ 0b0101111 - -/* We could set load-reservations on physical or virtual addresses. - * For now we set them on virtual addresses, since it makes the - * sequential model of SC a bit simpler, at the cost of an explicit - * call to load_reservation in LR and cancel_reservation in SC. - */ - -val process_loadres : forall 'n, 0 < 'n <= 8. (regbits, xlenbits, MemoryOpResult(bits(8 * 'n)), bool) -> bool effect {escape, rreg, wreg} -function process_loadres(rd, addr, value, is_unsigned) = - match extend_value(is_unsigned, value) { - MemValue(result) => { load_reservation(addr); X(rd) = result; true }, - MemException(e) => { handle_mem_exception(addr, e); false } - } - -function clause execute(LOADRES(aq, rl, rs1, width, rd)) = - let vaddr : xlenbits = X(rs1) in - let aligned : bool = - /* BYTE and HALF would only occur due to invalid decodes, but it doesn't hurt - * to treat them as valid here; otherwise we'd need to throw an internal_error. - * May need to revisit for latex output. - */ - match width { - BYTE => true, - HALF => vaddr[0] == 0b0, - WORD => vaddr[1..0] == 0b00, - DOUBLE => vaddr[2..0] == 0b000 - } in - /* "LR faults like a normal load, even though it's in the AMO major opcode space." - - Andrew Waterman, isa-dev, 10 Jul 2018. - */ - if (~ (aligned)) - then { handle_mem_exception(vaddr, E_Load_Addr_Align); false } - else match translateAddr(vaddr, Read, Data) { - TR_Failure(e) => { handle_mem_exception(vaddr, e); false }, - TR_Address(addr) => - match width { - WORD => process_loadres(rd, vaddr, mem_read(addr, 4, aq, rl, true), false), - DOUBLE => process_loadres(rd, vaddr, mem_read(addr, 8, aq, rl, true), false), - _ => internal_error("LOADRES expected WORD or DOUBLE") - } - } - -mapping clause assembly = LOADRES(aq, rl, rs1, size, rd) - <-> "lr." ^ size_mnemonic(size) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) - -/* ****************************************************************** */ -union clause ast = STORECON : (bool, bool, regbits, regbits, word_width, regbits) - -mapping clause encdec = STORECON(aq, rl, rs2, rs1, size, rd) - <-> 0b00011 @ bool_bits(aq) @ bool_bits(rl) @ rs2 @ rs1 @ 0b0 @ size_bits(size) @ rd @ 0b0101111 - -/* NOTE: Currently, we only EA if address translation is successful. - This may need revisiting. */ -function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = { - /* RMEM FIXME: This definition differs from the Sail1 version: - * rs1 is read *before* speculate_conditional_success - * (called via match_reservation), partly due to the current api of - * match_reservation. Reverting back to the weaker Sail1 version - * will require changes to the API for the ghost reservation state. - */ - vaddr : xlenbits = X(rs1); - let aligned : bool = - /* BYTE and HALF would only occur due to invalid decodes, but it doesn't hurt - * to treat them as valid here; otherwise we'd need to throw an internal_error. - * May need to revisit for latex output. - */ - match width { - BYTE => true, - HALF => vaddr[0] == 0b0, - WORD => vaddr[1..0] == 0b00, - DOUBLE => vaddr[2..0] == 0b000 - } in - if (~ (aligned)) - then { handle_mem_exception(vaddr, E_SAMO_Addr_Align); false } - else { - if match_reservation(vaddr) == false - then { X(rd) = EXTZ(0b1); true } - else { - match translateAddr(vaddr, Write, Data) { - TR_Failure(e) => { handle_mem_exception(vaddr, e); false }, - TR_Address(addr) => { - let eares : MemoryOpResult(unit) = match width { - WORD => mem_write_ea(addr, 4, aq, rl, true), - DOUBLE => mem_write_ea(addr, 8, aq, rl, true), - _ => internal_error("STORECON expected word or double") - }; - match (eares) { - MemException(e) => { handle_mem_exception(addr, e); false }, - MemValue(_) => { - rs2_val = X(rs2); - let res : MemoryOpResult(bool) = match width { - WORD => mem_write_value(addr, 4, rs2_val[31..0], aq, rl, true), - DOUBLE => mem_write_value(addr, 8, rs2_val, aq, rl, true), - _ => internal_error("STORECON expected word or double") - }; - match (res) { - MemValue(true) => { X(rd) = EXTZ(0b0); cancel_reservation(); true }, - MemValue(false) => { X(rd) = EXTZ(0b1); cancel_reservation(); true }, - MemException(e) => { handle_mem_exception(addr, e); false } - } - } - } - } - } - } - } -} - -mapping clause assembly = STORECON(aq, rl, rs2, rs1, size, rd) <-> "sc." ^ size_mnemonic(size) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) - -/* ****************************************************************** */ -union clause ast = AMO : (amoop, bool, bool, regbits, regbits, word_width, regbits) - -mapping encdec_amoop : amoop <-> bits(5) = { - AMOSWAP <-> 0b00001, - AMOADD <-> 0b00000, - AMOXOR <-> 0b00100, - AMOAND <-> 0b01100, - AMOOR <-> 0b01000, - AMOMIN <-> 0b10000, - AMOMAX <-> 0b10100, - AMOMINU <-> 0b11000, - AMOMAXU <-> 0b11100 -} - -mapping clause encdec = AMO(op, aq, rl, rs2, rs1, size, rd) <-> encdec_amoop(op) @ bool_bits(aq) @ bool_bits(rl) @ rs2 @ rs1 @ 0b0 @ size_bits(size) @ rd @ 0b0101111 - -/* NOTE: Currently, we only EA if address translation is successful. - This may need revisiting. */ -function clause execute (AMO(op, aq, rl, rs2, rs1, width, rd)) = { - vaddr : xlenbits = X(rs1); - match translateAddr(vaddr, ReadWrite, Data) { - TR_Failure(e) => { handle_mem_exception(vaddr, e); false }, - TR_Address(addr) => { - let eares : MemoryOpResult(unit) = match width { - WORD => mem_write_ea(addr, 4, aq & rl, rl, true), - DOUBLE => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error ("AMO expected WORD or DOUBLE") - }; - match (eares) { - MemException(e) => { handle_mem_exception(addr, e); false }, - MemValue(_) => { - let rval : MemoryOpResult(xlenbits) = match width { - WORD => extend_value(false, mem_read(addr, 4, aq, aq & rl, true)), - DOUBLE => extend_value(false, mem_read(addr, 8, aq, aq & rl, true)), - _ => internal_error ("AMO expected WORD or DOUBLE") - }; - match (rval) { - MemException(e) => { handle_mem_exception(addr, e); false }, - MemValue(loaded) => { - rs2_val : xlenbits = X(rs2); - result : xlenbits = - match op { - AMOSWAP => rs2_val, - AMOADD => rs2_val + loaded, - AMOXOR => rs2_val ^ loaded, - AMOAND => rs2_val & loaded, - AMOOR => rs2_val | loaded, - - /* Have to convert number to vector here. Check this */ - AMOMIN => vector64(min(signed(rs2_val), signed(loaded))), - AMOMAX => vector64(max(signed(rs2_val), signed(loaded))), - AMOMINU => vector64(min(unsigned(rs2_val), unsigned(loaded))), - AMOMAXU => vector64(max(unsigned(rs2_val), unsigned(loaded))) - }; - - let wval : MemoryOpResult(bool) = match width { - WORD => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), - DOUBLE => mem_write_value(addr, 8, result, aq & rl, rl, true), - _ => internal_error("AMO expected WORD or DOUBLE") - }; - match (wval) { - MemValue(true) => { X(rd) = loaded; true }, - MemValue(false) => { internal_error("AMO got false from mem_write_value") }, - MemException(e) => { handle_mem_exception(addr, e); false } - } - } - } - } - } - } - } -} - - -mapping amo_mnemonic : amoop <-> string = { - AMOSWAP <-> "amoswap", - AMOADD <-> "amoadd", - AMOXOR <-> "amoxor", - AMOAND <-> "amoand", - AMOOR <-> "amoor", - AMOMIN <-> "amomin", - AMOMAX <-> "amomax", - AMOMINU <-> "amominu", - AMOMAXU <-> "amomaxu" -} - -mapping clause assembly = AMO(op, aq, rl, rs2, rs1, width, rd) - <-> amo_mnemonic(op) ^ "." ^ size_mnemonic(width) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) - -/* ****************************************************************** */ -union clause ast = CSR : (bits(12), regbits, regbits, bool, csrop) - -mapping encdec_csrop : csrop <-> bits(2) = { - CSRRW <-> 0b01, - CSRRS <-> 0b10, - CSRRC <-> 0b11 -} - -mapping clause encdec = CSR(csr, rs1, rd, is_imm, op) <-> csr @ rs1 @ bool_bits(is_imm) @ encdec_csrop(op) @ rd @ 0b1110011 - -function readCSR csr : csreg -> xlenbits = - let res : xlenbits = - match csr { - /* machine mode */ - 0xF11 => mvendorid, - 0xF12 => marchid, - 0xF13 => mimpid, - 0xF14 => mhartid, - 0x300 => mstatus.bits(), - 0x301 => misa.bits(), - 0x302 => medeleg.bits(), - 0x303 => mideleg.bits(), - 0x304 => mie.bits(), - 0x305 => mtvec.bits(), - 0x306 => EXTZ(mcounteren.bits()), - 0x340 => mscratch, - 0x341 => mepc & pc_alignment_mask(), - 0x342 => mcause.bits(), - 0x343 => mtval, - 0x344 => mip.bits(), - - 0x3A0 => pmpcfg0, - 0x3B0 => pmpaddr0, - - /* supervisor mode */ - 0x100 => lower_mstatus(mstatus).bits(), - 0x102 => sedeleg.bits(), - 0x103 => sideleg.bits(), - 0x104 => lower_mie(mie, mideleg).bits(), - 0x105 => stvec.bits(), - 0x106 => EXTZ(scounteren.bits()), - 0x140 => sscratch, - 0x141 => sepc & pc_alignment_mask(), - 0x142 => scause.bits(), - 0x143 => stval, - 0x144 => lower_mip(mip, mideleg).bits(), - 0x180 => satp, - - /* others */ - 0xC00 => mcycle, - 0xC01 => mtime, - 0xC02 => minstret, - - /* trigger/debug */ - 0x7a0 => ~(tselect), /* this indicates we don't have any trigger support */ - - _ => { print_bits("unhandled read to CSR ", csr); - 0x0000_0000_0000_0000 } - } in { - print_reg("CSR " ^ csr ^ " -> " ^ BitStr(res)); - res - } - -function writeCSR (csr : csreg, value : xlenbits) -> unit = - let res : option(xlenbits) = - match csr { - /* machine mode */ - 0x300 => { mstatus = legalize_mstatus(mstatus, value); Some(mstatus.bits()) }, - 0x301 => { misa = legalize_misa(misa, value); Some(misa.bits()) }, - 0x302 => { medeleg = legalize_medeleg(medeleg, value); Some(medeleg.bits()) }, - 0x303 => { mideleg = legalize_mideleg(mideleg, value); Some(mideleg.bits()) }, - 0x304 => { mie = legalize_mie(mie, value); Some(mie.bits()) }, - 0x305 => { mtvec = legalize_tvec(mtvec, value); Some(mtvec.bits()) }, - 0x306 => { mcounteren = legalize_mcounteren(mcounteren, value); Some(EXTZ(mcounteren.bits())) }, - 0x340 => { mscratch = value; Some(mscratch) }, - 0x341 => { mepc = legalize_xepc(value); Some(mepc) }, - 0x342 => { mcause->bits() = value; Some(mcause.bits()) }, - 0x343 => { mtval = value; Some(mtval) }, - 0x344 => { mip = legalize_mip(mip, value); Some(mip.bits()) }, - - 0x3A0 => { pmpcfg0 = value; Some(pmpcfg0) }, /* FIXME: legalize */ - 0x3B0 => { pmpaddr0 = value; Some(pmpaddr0) }, /* FIXME: legalize */ - - /* supervisor mode */ - 0x100 => { mstatus = legalize_sstatus(mstatus, value); Some(mstatus.bits()) }, - 0x102 => { sedeleg = legalize_sedeleg(sedeleg, value); Some(sedeleg.bits()) }, - 0x103 => { sideleg->bits() = value; Some(sideleg.bits()) }, /* TODO: does this need legalization? */ - 0x104 => { mie = legalize_sie(mie, mideleg, value); Some(mie.bits()) }, - 0x105 => { stvec = legalize_tvec(stvec, value); Some(stvec.bits()) }, - 0x106 => { scounteren = legalize_scounteren(scounteren, value); Some(EXTZ(scounteren.bits())) }, - 0x140 => { sscratch = value; Some(sscratch) }, - 0x141 => { sepc = legalize_xepc(value); Some(sepc) }, - 0x142 => { scause->bits() = value; Some(scause.bits()) }, - 0x143 => { stval = value; Some(stval) }, - 0x144 => { mip = legalize_sip(mip, mideleg, value); Some(mip.bits()) }, - 0x180 => { satp = legalize_satp(cur_Architecture(), satp, value); Some(satp) }, - - /* trigger/debug */ - 0x7a0 => { tselect = value; Some(tselect) }, - - /* counters */ - 0xC00 => { mcycle = value; Some(mcycle) }, - /* FIXME: it is not clear whether writable mtime is platform-dependent. */ - 0xC02 => { minstret = value; minstret_written = true; Some(minstret) }, - - _ => None() - } in - match res { - Some(v) => print_reg("CSR " ^ csr ^ " <- " ^ BitStr(v) ^ " (input: " ^ BitStr(value) ^ ")"), - None() => print_bits("unhandled write to CSR ", csr) - } - -function clause execute CSR(csr, rs1, rd, is_imm, op) = - let rs1_val : xlenbits = if is_imm then EXTZ(rs1) else X(rs1) in - let isWrite : bool = match op { - CSRRW => true, - _ => if is_imm then unsigned(rs1_val) != 0 else unsigned(rs1) != 0 - } in - if ~ (check_CSR(csr, cur_privilege, isWrite)) - then { handle_illegal(); false } - else { - let csr_val = readCSR(csr); /* could have side-effects, so technically shouldn't perform for CSRW[I] with rd == 0 */ - if isWrite then { - let new_val : xlenbits = match op { - CSRRW => rs1_val, - CSRRS => csr_val | rs1_val, - CSRRC => csr_val & ~(rs1_val) - } in - writeCSR(csr, new_val) - }; - X(rd) = csr_val; - true - } - - -mapping maybe_i : bool <-> string = { - true <-> "i", - false <-> "" -} - -mapping csr_mnemonic : csrop <-> string = { - CSRRW <-> "csrrw", - CSRRS <-> "csrrs", - CSRRC <-> "csrrc" -} - -mapping clause assembly = CSR(csr, rs1, rd, true, op) <-> csr_mnemonic(op) ^ "i" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_5(rs1) ^ sep() ^ csr_name_map(csr) -mapping clause assembly = CSR(csr, rs1, rd, false, op) <-> csr_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ csr_name_map(csr) - -/* ****************************************************************** */ -union clause ast = C_NOP : unit - -mapping clause encdec_compressed = C_NOP() <-> 0b000 @ 0b0 @ 0b00000 @ 0b00000 @ 0b01 - -function clause execute C_NOP() = true - -mapping clause assembly = C_NOP() <-> "c.nop" - -/* ****************************************************************** */ - -union clause ast = C_ADDI4SPN : (cregbits, bits(8)) - -mapping clause encdec_compressed = C_ADDI4SPN(rd, nz96 @ nz54 @ nz3 @ nz2) - if nz96 @ nz54 @ nz3 @ nz2 != 0b00000000 <-> - 0b000 @ nz54 : bits(2) @ nz96 : bits(4) @ nz2 : bits(1) @ nz3 : bits(1) @ rd : cregbits @ 0b00 - if nz96 @ nz54 @ nz3 @ nz2 != 0b00000000 - -function clause execute (C_ADDI4SPN(rdc, nzimm)) = - let imm : bits(12) = (0b00 @ nzimm @ 0b00) in - let rd = creg2reg_bits(rdc) in - execute(ITYPE(imm, sp, rd, RISCV_ADDI)) - -mapping clause assembly = C_ADDI4SPN(rdc, nzimm) if nzimm != 0b00000000 <-> "c.addi4spn" ^ spc() ^ creg_name(rdc) ^ sep() ^ hex_bits_10(nzimm @ 0b00) if nzimm != 0b00000000 - -/* ****************************************************************** */ -union clause ast = C_LW : (bits(5), cregbits, cregbits) - -mapping clause encdec_compressed = C_LW(ui6 @ ui53 @ ui2, rs1, rd) <-> 0b010 @ ui53 : bits(3) @ rs1 : cregbits @ ui2 : bits(1) @ ui6 : bits(1) @ rd : cregbits @ 0b00 - -function clause execute (C_LW(uimm, rsc, rdc)) = - let imm : bits(12) = EXTZ(uimm @ 0b00) in - let rd = creg2reg_bits(rdc) in - let rs = creg2reg_bits(rsc) in - execute(LOAD(imm, rs, rd, false, WORD, false, false)) - -mapping clause assembly = C_LW(uimm, rsc, rdc) <-> "c.lw" ^ spc() ^ creg_name(rdc) ^ sep() ^ creg_name(rsc) ^ sep() ^ hex_bits_7(uimm @ 0b00) - -/* ****************************************************************** */ -union clause ast = C_LD : (bits(5), cregbits, cregbits) - -mapping clause encdec_compressed = C_LD(ui76 @ ui53, rs1, rd) <-> 0b011 @ ui53 : bits(3) @ rs1 : cregbits @ ui76 : bits(2) @ rd : cregbits @ 0b00 - -function clause execute (C_LD(uimm, rsc, rdc)) = - let imm : bits(12) = EXTZ(uimm @ 0b000) in - let rd = creg2reg_bits(rdc) in - let rs = creg2reg_bits(rsc) in - execute(LOAD(imm, rs, rd, false, DOUBLE, false, false)) - -mapping clause assembly = C_LD(uimm, rsc, rdc) <-> "c.ld" ^ spc() ^ creg_name(rdc) ^ sep() ^ creg_name(rsc) ^ sep() ^ hex_bits_8(uimm @ 0b000) - -/* ****************************************************************** */ -union clause ast = C_SW : (bits(5), cregbits, cregbits) - -mapping clause encdec_compressed = C_SW(ui6 @ ui53 @ ui2, rs1, rs2) <-> 0b110 @ ui53 : bits(3) @ rs1 : cregbits @ ui2 : bits(1) @ ui6 : bits(1) @ rs2 : cregbits @ 0b00 - -function clause execute (C_SW(uimm, rsc1, rsc2)) = - let imm : bits(12) = EXTZ(uimm @ 0b00) in - let rs1 = creg2reg_bits(rsc1) in - let rs2 = creg2reg_bits(rsc2) in - execute(STORE(imm, rs2, rs1, WORD, false, false)) - -mapping clause assembly = C_SW(uimm, rsc1, rsc2) <-> "c.sw" ^ spc() ^ creg_name(rsc1) ^ sep() ^ creg_name(rsc2) ^ sep() ^ hex_bits_7(uimm @ 0b00) - -/* ****************************************************************** */ -union clause ast = C_SD : (bits(5), cregbits, cregbits) - -mapping clause encdec_compressed = C_SD(ui76 @ ui53, rs1, rs2) <-> 0b111 @ ui53 : bits(3) @ rs1 : bits(3) @ ui76 : bits(2) @ rs2 : bits(3) @ 0b00 - -function clause execute (C_SD(uimm, rsc1, rsc2)) = - let imm : bits(12) = EXTZ(uimm @ 0b000) in - let rs1 = creg2reg_bits(rsc1) in - let rs2 = creg2reg_bits(rsc2) in - execute(STORE(imm, rs2, rs1, DOUBLE, false, false)) - -mapping clause assembly = C_SD(uimm, rsc1, rsc2) <-> "c.sd" ^ spc() ^ creg_name(rsc1) ^ sep() ^ creg_name(rsc2) ^ sep() ^ hex_bits_8(uimm @ 0b000) - -/* ****************************************************************** */ -union clause ast = C_ADDI : (bits(6), regbits) - -mapping clause encdec_compressed = C_ADDI(nzi5 @ nzi40, rsd) if nzi5 @ nzi40 != 0b000000 & rsd != zreg <-> 0b000 @ nzi5 : bits(1) @ rsd : regbits @ nzi40 : bits(5) @ 0b01 if nzi5 @ nzi40 != 0b000000 & rsd != zreg - -function clause execute (C_ADDI(nzi, rsd)) = - let imm : bits(12) = EXTS(nzi) in - execute(ITYPE(imm, rsd, rsd, RISCV_ADDI)) - -mapping clause assembly = C_ADDI(nzi, rsd) if nzi != 0b000000 & rsd != zreg <-> "c.addi" ^ spc() ^ reg_name(rsd) ^ sep() ^ hex_bits_6(nzi) if nzi != 0b000000 & rsd != zreg - -/* ****************************************************************** */ -union clause ast = C_JAL : (bits(11)) -union clause ast = C_ADDIW : (bits(6), regbits) - -/* FIXME: decoding differs for RVC32/RVC64. Below, we are assuming - * RV64, and C_JAL is RV32 only. */ - -mapping clause encdec_compressed = C_ADDIW(imm5 @ imm40, rsd) if rsd != zreg <-> 0b001 @ imm5 : bits(1) @ rsd : regbits @ imm40 : bits(5) @ 0b01 if rsd != zreg - -function clause execute (C_JAL(imm)) = - execute(RISCV_JAL(EXTS(imm @ 0b0), ra)) - -function clause execute (C_ADDIW(imm, rsd)) = { - let imm : bits(32) = EXTS(imm); - let rs_val = X(rsd); - let res : bits(32) = rs_val[31..0] + imm; - X(rsd) = EXTS(res); - true -} - -mapping clause assembly = C_JAL(imm) <-> "c.jal" ^ spc() ^ hex_bits_12(imm @ 0b0) - -mapping clause assembly = C_ADDIW(imm, rsd) <-> "c.addiw" ^ spc() ^ reg_name(rsd) ^ sep() ^ hex_bits_6(imm) - -/* ****************************************************************** */ -union clause ast = C_LI : (bits(6), regbits) - -mapping clause encdec_compressed = C_LI(imm5 @ imm40, rd) if rd != zreg <-> 0b010 @ imm5 : bits(1) @ rd : regbits @ imm40 : bits(5) @ 0b01 if rd != zreg - -function clause execute (C_LI(imm, rd)) = - let imm : bits(12) = EXTS(imm) in - execute(ITYPE(imm, zreg, rd, RISCV_ADDI)) - -mapping clause assembly = C_LI(imm, rd) if rd != zreg <-> "c.li" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_6(imm) if rd != zreg - -/* ****************************************************************** */ -union clause ast = C_ADDI16SP : (bits(6)) - -mapping clause encdec_compressed = C_ADDI16SP(nzi9 @ nzi87 @ nzi6 @ nzi5 @ nzi4) - if nzi9 @ nzi87 @ nzi6 @ nzi5 @ nzi4 != 0b000000 - <-> 0b011 @ nzi9 : bits(1) @ /* x2 */ 0b00010 @ nzi4 : bits(1) @ nzi6 : bits(1) @ nzi87 : bits(2) @ nzi5 : bits(1) @ 0b01 - if nzi9 @ nzi87 @ nzi6 @ nzi5 @ nzi4 != 0b000000 - -function clause execute (C_ADDI16SP(imm)) = - let imm : bits(12) = EXTS(imm @ 0x0) in - execute(ITYPE(imm, sp, sp, RISCV_ADDI)) - -mapping clause assembly = C_ADDI16SP(imm) if imm != 0b000000 <-> "c.addi16sp" ^ spc() ^ hex_bits_6(imm) if imm != 0b000000 - -/* ****************************************************************** */ -union clause ast = C_LUI : (bits(6), regbits) - -mapping clause encdec_compressed = C_LUI(imm17 @ imm1612, rd) if rd != zreg & rd != sp & imm17 @ imm1612 != 0b000000 <-> 0b011 @ imm17 : bits(1) @ rd : regbits @ imm1612 : bits(5) @ 0b01 if rd != zreg & rd != sp & imm17 @ imm1612 != 0b000000 - -function clause execute (C_LUI(imm, rd)) = - let res : bits(20) = EXTS(imm) in - execute(UTYPE(res, rd, RISCV_LUI)) - -mapping clause assembly = C_LUI(imm, rd) if rd != zreg & rd != sp & imm != 0b000000 <-> "c.lui" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_6(imm) if rd != zreg & rd != sp & imm != 0b000000 - -/* ****************************************************************** */ -union clause ast = C_SRLI : (bits(6), cregbits) - -mapping clause encdec_compressed = C_SRLI(nzui5 @ nzui40, rsd) if nzui5 @ nzui40 != 0b000000 <-> 0b100 @ nzui5 : bits(1) @ 0b00 @ rsd : cregbits @ nzui40 : bits(5) @ 0b01 if nzui5 @ nzui40 != 0b000000 - -function clause execute (C_SRLI(shamt, rsd)) = - let rsd = creg2reg_bits(rsd) in - execute(SHIFTIOP(shamt, rsd, rsd, RISCV_SRLI)) - -mapping clause assembly = C_SRLI(shamt, rsd) if shamt != 0b000000 <-> "c.srli" ^ spc() ^ creg_name(rsd) ^ sep() ^ hex_bits_6(shamt) if shamt != 0b000000 - -/* ****************************************************************** */ -union clause ast = C_SRAI : (bits(6), cregbits) - -mapping clause encdec_compressed = C_SRAI(nzui5 @ nzui40, rsd) if nzui5 @ nzui40 != 0b000000 <-> 0b100 @ nzui5 : bits(1) @ 0b01 @ rsd : cregbits @ nzui40 : bits(5) @ 0b01 if nzui5 @ nzui40 != 0b000000 - -function clause execute (C_SRAI(shamt, rsd)) = - let rsd = creg2reg_bits(rsd) in - execute(SHIFTIOP(shamt, rsd, rsd, RISCV_SRAI)) - -mapping clause assembly = C_SRAI(shamt, rsd) if shamt != 0b000000 <-> "c.srai" ^ spc() ^ creg_name(rsd) ^ sep() ^ hex_bits_6(shamt) if shamt != 0b000000 - -/* ****************************************************************** */ -union clause ast = C_ANDI : (bits(6), cregbits) - -mapping clause encdec_compressed = C_ANDI(i5 @ i40, rsd) <-> 0b100 @ i5 : bits(1) @ 0b10 @ rsd : cregbits @ i40 : bits(5) @ 0b01 - -function clause execute (C_ANDI(imm, rsd)) = - let rsd = creg2reg_bits(rsd) in - execute(ITYPE(EXTS(imm), rsd, rsd, RISCV_ANDI)) - -mapping clause assembly = C_ANDI(imm, rsd) <-> "c.andi" ^ spc() ^ creg_name(rsd) ^ sep() ^ hex_bits_6(imm) - -/* ****************************************************************** */ -union clause ast = C_SUB : (cregbits, cregbits) - -mapping clause encdec_compressed = C_SUB(rsd, rs2) <-> 0b100 @ 0b0 @ 0b11 @ rsd : cregbits @ 0b00 @ rs2 : cregbits @ 0b01 - -function clause execute (C_SUB(rsd, rs2)) = - let rsd = creg2reg_bits(rsd) in - let rs2 = creg2reg_bits(rs2) in - execute(RTYPE(rs2, rsd, rsd, RISCV_SUB)) - -mapping clause assembly = C_SUB(rsd, rs2) <-> "c.sub" ^ spc() ^ creg_name(rsd) ^ sep() ^ creg_name(rs2) - -/* ****************************************************************** */ -union clause ast = C_XOR : (cregbits, cregbits) - -mapping clause encdec_compressed = C_XOR(rsd, rs2) <-> 0b100 @ 0b0 @ 0b11 @ rsd : cregbits @ 0b01 @ rs2 : cregbits @ 0b01 - -function clause execute (C_XOR(rsd, rs2)) = - let rsd = creg2reg_bits(rsd) in - let rs2 = creg2reg_bits(rs2) in - execute(RTYPE(rs2, rsd, rsd, RISCV_XOR)) - -mapping clause assembly = C_XOR(rsd, rs2) <-> "c.xor" ^ spc() ^ creg_name(rsd) ^ sep() ^ creg_name(rs2) - -/* ****************************************************************** */ -union clause ast = C_OR : (cregbits, cregbits) - -mapping clause encdec_compressed = C_OR(rsd, rs2) <-> 0b100 @ 0b0 @ 0b11 @ rsd : cregbits @ 0b10 @ rs2 : cregbits @ 0b01 - -function clause execute (C_OR(rsd, rs2)) = - let rsd = creg2reg_bits(rsd) in - let rs2 = creg2reg_bits(rs2) in - execute(RTYPE(rs2, rsd, rsd, RISCV_OR)) - -mapping clause assembly = C_OR(rsd, rs2) <-> "c.or" ^ spc() ^ creg_name(rsd) ^ sep() ^ creg_name(rs2) - -/* ****************************************************************** */ -union clause ast = C_AND : (cregbits, cregbits) - -mapping clause encdec_compressed = C_AND(rsd, rs2) <-> 0b100 @ 0b0 @ 0b11 @ rsd : cregbits @ 0b11 @ rs2 : cregbits @ 0b01 - -function clause execute (C_AND(rsd, rs2)) = - let rsd = creg2reg_bits(rsd) in - let rs2 = creg2reg_bits(rs2) in - execute(RTYPE(rs2, rsd, rsd, RISCV_AND)) - -mapping clause assembly = C_AND(rsd, rs2) <-> "c.and" ^ spc() ^ creg_name(rsd) ^ sep() ^ creg_name(rs2) - -/* ****************************************************************** */ -union clause ast = C_SUBW : (cregbits, cregbits) - -/* TODO: invalid on RV32 */ -mapping clause encdec_compressed = C_SUBW(rsd, rs2) <-> 0b100 @ 0b1 @ 0b11 @ rsd : cregbits @ 0b00 @ rs2 : cregbits @ 0b01 - -function clause execute (C_SUBW(rsd, rs2)) = - let rsd = creg2reg_bits(rsd) in - let rs2 = creg2reg_bits(rs2) in - execute(RTYPEW(rs2, rsd, rsd, RISCV_SUBW)) - -mapping clause assembly = C_SUBW(rsd, rs2) <-> "c.subw" ^ spc() ^ creg_name(rsd) ^ sep() ^ creg_name(rs2) - -/* ****************************************************************** */ -union clause ast = C_ADDW : (cregbits, cregbits) - -/* TODO: invalid on RV32 */ -mapping clause encdec_compressed = C_ADDW(rsd, rs2) <-> 0b100 @ 0b1 @ 0b11 @ rsd : cregbits @ 0b01 @ rs2 : cregbits @ 0b01 - -function clause execute (C_ADDW(rsd, rs2)) = - let rsd = creg2reg_bits(rsd) in - let rs2 = creg2reg_bits(rs2) in - execute(RTYPEW(rs2, rsd, rsd, RISCV_ADDW)) - -mapping clause assembly = C_ADDW(rsd, rs2) <-> "c.addw" ^ spc() ^ creg_name(rsd) ^ sep() ^ creg_name(rs2) - -/* ****************************************************************** */ -union clause ast = C_J : (bits(11)) - -mapping clause encdec_compressed = C_J(i11 @ i10 @ i98 @ i7 @ i6 @ i5 @ i4 @ i31) <-> 0b101 @ i11 : bits(1) @ i4 : bits(1) @ i98 : bits(2) @ i10 : bits(1) @ i6 : bits(1) @ i7 : bits(1) @ i31 : bits(3) @ i5 : bits(1) @ 0b01 - -function clause execute (C_J(imm)) = - execute(RISCV_JAL(EXTS(imm @ 0b0), zreg)) - -mapping clause assembly = C_J(imm) <-> "c.j" ^ spc() ^ hex_bits_11(imm) - -/* ****************************************************************** */ -union clause ast = C_BEQZ : (bits(8), cregbits) - -mapping clause encdec_compressed = C_BEQZ(i8 @ i76 @ i5 @ i43 @ i21, rs) <-> 0b110 @ i8 : bits(1) @ i43 : bits(2) @ rs : cregbits @ i76 : bits(2) @ i21 : bits(2) @ i5 : bits(1) @ 0b01 - -function clause execute (C_BEQZ(imm, rs)) = - execute(BTYPE(EXTS(imm @ 0b0), zreg, creg2reg_bits(rs), RISCV_BEQ)) - -mapping clause assembly = C_BEQZ(imm, rs) <-> "c.beqz" ^ spc() ^ creg_name(rs) ^ sep() ^ hex_bits_8(imm) - -/* ****************************************************************** */ -union clause ast = C_BNEZ : (bits(8), cregbits) - -mapping clause encdec_compressed = C_BNEZ(i8 @ i76 @ i5 @ i43 @ i21, rs) <-> 0b111 @ i8 : bits(1) @ i43 : bits(2) @ rs : cregbits @ i76 : bits(2) @ i21 : bits(2) @ i5 : bits(1) @ 0b01 - -function clause execute (C_BNEZ(imm, rs)) = - execute(BTYPE(EXTS(imm @ 0b0), zreg, creg2reg_bits(rs), RISCV_BNE)) - -mapping clause assembly = C_BNEZ(imm, rs) <-> "c.bnez" ^ spc() ^ creg_name(rs) ^ sep() ^ hex_bits_8(imm) - -/* ****************************************************************** */ -union clause ast = C_SLLI : (bits(6), regbits) - -/* TODO: On RV32, also need shamt[5] == 0 */ -mapping clause encdec_compressed = C_SLLI(nzui5 @ nzui40, rsd) if nzui5 @ nzui40 != 0b000000 & rsd != zreg - <-> 0b000 @ nzui5 : bits(1) @ rsd : regbits @ nzui40 : bits(5) @ 0b10 if nzui5 @ nzui40 != 0b000000 & rsd != zreg - -function clause execute (C_SLLI(shamt, rsd)) = - execute(SHIFTIOP(shamt, rsd, rsd, RISCV_SLLI)) - -mapping clause assembly = C_SLLI(shamt, rsd) if shamt != 0b000000 & rsd != zreg - <-> "c.slli" ^ spc() ^ reg_name(rsd) ^ sep() ^ hex_bits_6(shamt) if shamt != 0b000000 & rsd != zreg - -/* ****************************************************************** */ -union clause ast = C_LWSP : (bits(6), regbits) - -mapping clause encdec_compressed = C_LWSP(ui76 @ ui5 @ ui42, rd) if rd != zreg - <-> 0b010 @ ui5 : bits(1) @ rd : regbits @ ui42 : bits(3) @ ui76 : bits(2) @ 0b10 if rd != zreg - -function clause execute (C_LWSP(uimm, rd)) = - let imm : bits(12) = EXTZ(uimm @ 0b00) in - execute(LOAD(imm, sp, rd, false, WORD, false, false)) - -mapping clause assembly = C_LWSP(uimm, rd) if rd != zreg <-> "c.lwsp" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_6(uimm) if rd != zreg - -/* ****************************************************************** */ -union clause ast = C_LDSP : (bits(6), regbits) - -mapping clause encdec_compressed = C_LDSP(ui86 @ ui5 @ ui43, rd) if rd != zreg <-> 0b011 @ ui5 : bits(1) @ rd : regbits @ ui43 : bits(2) @ ui86 : bits(3) @ 0b10 if rd != zreg - -function clause execute (C_LDSP(uimm, rd)) = - let imm : bits(12) = EXTZ(uimm @ 0b000) in - execute(LOAD(imm, sp, rd, false, DOUBLE, false, false)) - -mapping clause assembly = C_LDSP(uimm, rd) if rd != zreg <-> "c.ldsp" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_6(uimm) if rd != zreg - -/* ****************************************************************** */ -union clause ast = C_SWSP : (bits(6), regbits) - -mapping clause encdec_compressed = C_SWSP(ui76 @ ui52, rs2) <-> 0b110 @ ui52 : bits(4) @ ui76 : bits(2) @ rs2 : regbits @ 0b10 - -function clause execute (C_SWSP(uimm, rs2)) = - let imm : bits(12) = EXTZ(uimm @ 0b00) in - execute(STORE(imm, rs2, sp, WORD, false, false)) - -mapping clause assembly = C_SWSP(uimm, rd) <-> "c.swsp" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_6(uimm) - -/* ****************************************************************** */ -union clause ast = C_SDSP : (bits(6), regbits) - -mapping clause encdec_compressed = C_SDSP(ui86 @ ui53, rs2) <-> 0b111 @ ui53 : bits(3) @ ui86 : bits(3) @ rs2 : regbits @ 0b10 - -function clause execute (C_SDSP(uimm, rs2)) = - let imm : bits(12) = EXTZ(uimm @ 0b000) in - execute(STORE(imm, rs2, sp, DOUBLE, false, false)) - -mapping clause assembly = C_SDSP(uimm, rs2) <-> "c.sdsp" ^ spc() ^ reg_name(rs2) ^ sep() ^ hex_bits_6(uimm) - -/* ****************************************************************** */ -union clause ast = C_JR : (regbits) - -mapping clause encdec_compressed = C_JR(rs1) if rs1 != zreg <-> 0b100 @ 0b0 @ rs1 : regbits @ 0b00000 @ 0b10 if rs1 != zreg - -function clause execute (C_JR(rs1)) = - execute(RISCV_JALR(EXTZ(0b0), rs1, zreg)) - -mapping clause assembly = C_JR(rs1) if rs1 != zreg <-> "c.jr" ^ spc() ^ reg_name(rs1) if rs1 != zreg - -/* ****************************************************************** */ -union clause ast = C_JALR : (regbits) - -mapping clause encdec_compressed = C_JALR(rs1) if rs1 != zreg <-> 0b100 @ 0b1 @ rs1 : regbits @ 0b00000 @ 0b10 if rs1 != zreg - -function clause execute (C_JALR(rs1)) = - execute(RISCV_JALR(EXTZ(0b0), rs1, ra)) - -mapping clause assembly = C_JALR(rs1) if rs1 != zreg <-> "c.jalr" ^ spc() ^ reg_name(rs1) if rs1 != zreg - -/* ****************************************************************** */ -union clause ast = C_MV : (regbits, regbits) - -mapping clause encdec_compressed = C_MV(rd, rs2) if rd != zreg & rs2 != zreg <-> 0b100 @ 0b0 @ rd : regbits @ rs2 : regbits @ 0b10 if rd != zreg & rs2 != zreg - -function clause execute (C_MV(rd, rs2)) = - execute(RTYPE(rs2, zreg, rd, RISCV_ADD)) - -mapping clause assembly = C_MV(rd, rs2) if rd != zreg & rs2 != zreg <-> "c.mv" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs2) if rd != zreg & rs2 != zreg - -/* ****************************************************************** */ -union clause ast = C_EBREAK : unit - -mapping clause encdec_compressed = C_EBREAK() <-> 0b100 @ 0b1 @ 0b00000 @ 0b00000 @ 0b10 - -function clause execute C_EBREAK() = - execute(EBREAK()) - -mapping clause assembly = C_EBREAK() <-> "c.ebreak" - -/* ****************************************************************** */ -union clause ast = C_ADD : (regbits, regbits) - -mapping clause encdec_compressed = C_ADD(rsd, rs2) if rsd != zreg & rs2 != zreg <-> 0b100 @ 0b1 @ rsd : regbits @ rs2 : regbits @ 0b10 if rsd != zreg & rs2 != zreg - -function clause execute (C_ADD(rsd, rs2)) = - execute(RTYPE(rs2, rsd, rsd, RISCV_ADD)) - -mapping clause assembly = C_ADD(rsd, rs2) if rsd != zreg & rs2 != zreg <-> "c.add" ^ spc() ^ reg_name(rsd) ^ sep() ^ reg_name(rs2) if rsd != zreg & rs2 != zreg - -/* ****************************************************************** */ - -union clause ast = STOP_FETCHING : unit - -/* RMEM stop fetching sentinel, using RISCV encoding space custom-0 */ -mapping clause encdec = STOP_FETCHING() <-> 0xfade @ 0b00000000 @ 0b0 @ 0b00 @ 0b010 @ 0b11 - -function clause execute (STOP_FETCHING()) = true - -mapping clause assembly = STOP_FETCHING() <-> "stop_fetching" - -union clause ast = THREAD_START : unit - -/* RMEM thread start sentinel, using RISCV encoding space custom-0 */ -mapping clause encdec = THREAD_START() <-> 0xc0de @ 0b00000000 @ 0b0 @ 0b00 @ 0b010 @ 0b11 - -function clause execute (THREAD_START()) = true - -mapping clause assembly = THREAD_START() <-> "thread_start" - - -/* ****************************************************************** */ - -union clause ast = ILLEGAL : word - -mapping clause encdec = ILLEGAL(s) <-> s - -function clause execute (ILLEGAL(s)) = { handle_illegal(); false } - -mapping clause assembly = ILLEGAL(s) <-> "illegal" ^ spc() ^ hex_bits_32(s) - - - -/* ****************************************************************** */ - -union clause ast = C_ILLEGAL : half - -mapping clause encdec_compressed = C_ILLEGAL(s) <-> s - -function clause execute C_ILLEGAL(s) = { handle_illegal(); false } - -mapping clause assembly = C_ILLEGAL(s) <-> "c.illegal" ^ spc() ^ hex_bits_16(s) - -/* ****************************************************************** */ diff --git a/riscv/riscv_analysis.sail b/riscv/riscv_analysis.sail deleted file mode 100644 index e374933a..00000000 --- a/riscv/riscv_analysis.sail +++ /dev/null @@ -1,179 +0,0 @@ -$include - -/* in reverse order because inc vectors don't seem to work (bug) */ -let GPRstr : vector(32, dec, string) = [ "x31", "x30", "x29", "x28", "x27", "x26", "x25", "x24", "x23", "x22", "x21", - "x20", "x19", "x18", "x17", "x16", "x15", "x14", "x13", "x12", "x11", - "x10", "x9", "x8", "x7", "x6", "x5", "x4", "x3", "x2", "x1", "x0" - ] - - -let CIA_fp = RFull("CIA") -let NIA_fp = RFull("NIA") - -function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,instruction_kind) = { - iR = [| |] : regfps; - oR = [| |] : regfps; - aR = [| |] : regfps; - ik = IK_simple() : instruction_kind; - Nias = [| NIAFP_successor() |] : niafps; - Dia = DIAFP_none() : diafp; - - match instr { - EBREAK() => (), - UTYPE(imm, rd, op) => { - if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR; - }, - RISCV_JAL(imm, rd) => { - if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR; - let offset : bits(64) = EXTS(imm) in - Nias = [| NIAFP_concrete_address (PC + offset) |]; - ik = IK_branch(); - }, - RISCV_JALR(imm, rs, rd) => { - if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR; - if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR; - let offset : bits(64) = EXTS(imm) in - Nias = [| NIAFP_indirect_address() |]; - ik = IK_branch(); - }, - BTYPE(imm, rs2, rs1, op) => { - if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR; - if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR; - ik = IK_branch(); - let offset : bits(64) = EXTS(imm) in - Nias = [| NIAFP_concrete_address(PC + offset), NIAFP_successor() |]; - }, - ITYPE(imm, rs, rd, op) => { - if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR; - if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR; - }, - SHIFTIOP(imm, rs, rd, op) => { - if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR; - if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR; - }, - RTYPE(rs2, rs1, rd, op) => { - if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR; - if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR; - if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR; - }, - CSR(csr, rs1, rd, is_imm, op) => { - let isWrite : bool = match op { - CSRRW => true, - _ => if is_imm then unsigned(rs1) != 0 else unsigned(rs1) != 0 - }; - iR = RFull(csr_name(csr)) :: iR; - if ~(is_imm) then { - iR = RFull(GPRstr[rs1]) :: iR; - }; - if isWrite then { - oR = RFull(csr_name(csr)) :: oR; - }; - oR = RFull(GPRstr[rd]) :: oR; - }, - LOAD(imm, rs, rd, unsign, width, aq, rl) => { /* XXX "unsigned" causes name conflict in lem shallow embedding... */ - if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR; - if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR; - aR = iR; - ik = - match (aq, rl) { - (false, false) => IK_mem_read (Read_plain), - (true, false) => IK_mem_read (Read_RISCV_acquire), - (true, true) => IK_mem_read (Read_RISCV_strong_acquire), - - _ => internal_error("LOAD type not implemented in initial_analysis") - } - }, - STORE(imm, rs2, rs1, width, aq, rl) => { - if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR; - if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR; - if (rs1 == 0) then () else aR = RFull(GPRstr[rs1]) :: aR; - ik = - match (aq, rl) { - (false, false) => IK_mem_write (Write_plain), - (false, true) => IK_mem_write (Write_RISCV_release), - (true, true) => IK_mem_write (Write_RISCV_strong_release), - - _ => internal_error("STORE type not implemented in initial_analysis") - } - }, - ADDIW(imm, rs, rd) => { - if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR; - if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR; - }, - SHIFTW(imm, rs, rd, op) => { - if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR; - if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR; - }, - RTYPEW(rs2, rs1, rd, op) => { - if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR; - if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR; - if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR; - }, - FENCE(pred, succ) => { - ik = - match (pred, succ) { - (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_rw_rw), - (_ : bits(2) @ 0b10, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_r_rw), - (_ : bits(2) @ 0b10, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_r_r), - (_ : bits(2) @ 0b11, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_rw_w), - (_ : bits(2) @ 0b01, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_w_w), - (_ : bits(2) @ 0b01, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_w_rw), - (_ : bits(2) @ 0b11, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_rw_r), - (_ : bits(2) @ 0b10, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_r_w), - (_ : bits(2) @ 0b01, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_w_r), - - - (_ : bits(2) @ 0b00, _ : bits(2) @ 0b00) => IK_simple (), - - _ => internal_error("barrier type not implemented in initial_analysis") - // case (FM_NORMAL, _, _) -> exit "not implemented" - - // case (FM_TSO, 0b0011, 0b0011) -> IK_barrier (Barrier_RISCV_tso) - // case (FM_TSO, _, _) -> exit "not implemented" - }; - }, - FENCEI() => { - ik = IK_simple (); // for RMEM, should morally be Barrier_RISCV_i - }, - LOADRES(aq, rl, rs1, width, rd) => { - if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR; - if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR; - aR = iR; - ik = match (aq, rl) { - (false, false) => IK_mem_read (Read_RISCV_reserved), - (true, false) => IK_mem_read (Read_RISCV_reserved_acquire), - (true, true) => IK_mem_read (Read_RISCV_reserved_strong_acquire), - (false, true) => internal_error("LOADRES type not implemented in initial_analysis") - }; - }, - STORECON(aq, rl, rs2, rs1, width, rd) => { - if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR; - if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR; - if (rs1 == 0) then () else aR = RFull(GPRstr[rs1]) :: aR; - if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR; - ik = match (aq, rl) { - (false, false) => IK_mem_write (Write_RISCV_conditional), - (false, true) => IK_mem_write (Write_RISCV_conditional_release), - (true, true) => IK_mem_write (Write_RISCV_conditional_strong_release), - - (true, false) => internal_error("STORECON type not implemented in initial_analysis") - }; - }, - AMO(op, aq, rl, rs2, rs1, width, rd) => { - if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR; - if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR; - if (rs1 == 0) then () else aR = RFull(GPRstr[rs1]) :: aR; - if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR; - ik = match (aq, rl) { - (false, false) => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional), - (false, true) => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional_release), - (true, false) => IK_mem_rmw (Read_RISCV_reserved_acquire, - Write_RISCV_conditional), - (true, true) => IK_mem_rmw (Read_RISCV_reserved_acquire, - Write_RISCV_conditional_release) - }; - }, - _ => () - }; - (iR,oR,aR,Nias,Dia,ik) -} diff --git a/riscv/riscv_config.h b/riscv/riscv_config.h deleted file mode 100644 index f8f3eb30..00000000 --- a/riscv/riscv_config.h +++ /dev/null @@ -1,7 +0,0 @@ -#pragma once -#include - -extern bool config_print_instr; -extern bool config_print_reg; -extern bool config_print_mem_access; -extern bool config_print_platform; diff --git a/riscv/riscv_duopod.sail b/riscv/riscv_duopod.sail deleted file mode 100644 index 0a5a7f8c..00000000 --- a/riscv/riscv_duopod.sail +++ /dev/null @@ -1,86 +0,0 @@ - -type xlen = atom(64) -type xlen_t = bits(64) - -type regno ('n : Int), 0 <= 'n < 32 = atom('n) -type regbits = bits(5) - -val zeros : forall 'n, 'n >= 0. atom('n) -> bits('n) -function zeros n = replicate_bits(0b0, n) - -val cast regbits_to_regno : bits(5) -> {'n, 0 <= 'n < 32. regno('n)} -function regbits_to_regno b = let r as atom(_) = unsigned(b) in r - -/* Architectural state */ - -register PC : xlen_t -register nextPC : xlen_t - -register Xs : vector(32, dec, xlen_t) - -/* Getters and setters for X registers (special case for zeros register, x0) */ -val rX : forall 'n, 0 <= 'n < 32. regno('n) -> xlen_t effect {rreg} - -function rX 0 = 0x0000000000000000 -and rX (r if r > 0) = Xs[r] - -val wX : forall 'n, 0 <= 'n < 32. (regno('n), xlen_t) -> unit effect {wreg} - -function wX (r, v) = - if (r != 0) then { - Xs[r] = v; - } - -overload X = {rX, wX} - -/* Accessors for memory */ - -val MEMr : forall 'n, 'n >= 0. (xlen_t, atom('n)) -> bits(8 * 'n) effect {rmem} -function MEMr (addr, width) = - match __RISCV_read(addr, width, false, false, false) { Some(v) => v, None() => zeros(8 * width) } - -/* Instruction decode and execute */ -enum iop = {RISCV_ADDI, RISCV_SLTI, RISCV_SLTIU, RISCV_XORI, RISCV_ORI, RISCV_ANDI} /* immediate ops */ -scattered union ast - -val decode : bits(32) -> option(ast) effect pure -scattered function decode - -val execute : ast -> unit effect {rmem, rreg, wreg} -scattered function execute - -/* ****************************************************************** */ - -/* ADDI */ - -union clause ast = ITYPE : (bits(12), regbits, regbits, iop) - -function clause decode imm : bits(12) @ rs1 : regbits @ 0b000 @ rd : regbits @ 0b0010011 - = Some(ITYPE(imm, rs1, rd, RISCV_ADDI)) - -function clause execute (ITYPE (imm, rs1, rd, RISCV_ADDI)) = - let rs1_val = X(rs1) in - let imm_ext : xlen_t = EXTS(imm) in - let result = rs1_val + imm_ext in - X(rd) = result - -/* ****************************************************************** */ - -/* Load double */ -union clause ast = LOAD : (bits(12), regbits, regbits) - -function clause decode imm : bits(12) @ rs1 : regbits @ 0b011 @ rd : regbits @ 0b0000011 - = Some(LOAD(imm, rs1, rd)) - -function clause execute(LOAD(imm, rs1, rd)) = - let addr : xlen_t = X(rs1) + EXTS(imm) in - let result : xlen_t = MEMr(addr, 8) in - X(rd) = result - -/* ****************************************************************** */ - -function clause decode _ = None() - -end ast -end decode -end execute diff --git a/riscv/riscv_extras.lem b/riscv/riscv_extras.lem deleted file mode 100644 index 7028d5b8..00000000 --- a/riscv/riscv_extras.lem +++ /dev/null @@ -1,135 +0,0 @@ -open import Pervasives -open import Pervasives_extra -open import Sail2_instr_kinds -open import Sail2_values -open import Sail2_operators_mwords -open import Sail2_prompt_monad -open import Sail2_prompt - -type bitvector 'a = mword 'a - -let MEM_fence_rw_rw () = barrier Barrier_RISCV_rw_rw -let MEM_fence_r_rw () = barrier Barrier_RISCV_r_rw -let MEM_fence_r_r () = barrier Barrier_RISCV_r_r -let MEM_fence_rw_w () = barrier Barrier_RISCV_rw_w -let MEM_fence_w_w () = barrier Barrier_RISCV_w_w -let MEM_fence_w_rw () = barrier Barrier_RISCV_w_rw -let MEM_fence_rw_r () = barrier Barrier_RISCV_rw_r -let MEM_fence_r_w () = barrier Barrier_RISCV_r_w -let MEM_fence_w_r () = barrier Barrier_RISCV_w_r -let MEM_fence_i () = barrier Barrier_RISCV_i - -val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -val MEMea_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -val MEMea_conditional : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -val MEMea_conditional_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e - -let MEMea addr size = write_mem_ea Write_plain addr size -let MEMea_release addr size = write_mem_ea Write_RISCV_release addr size -let MEMea_strong_release addr size = write_mem_ea Write_RISCV_strong_release addr size -let MEMea_conditional addr size = write_mem_ea Write_RISCV_conditional addr size -let MEMea_conditional_release addr size = write_mem_ea Write_RISCV_conditional_release addr size -let MEMea_conditional_strong_release addr size - = write_mem_ea Write_RISCV_conditional_strong_release addr size - -val MEMr : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e -val MEMr_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e -val MEMr_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e -val MEMr_reserved : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e -val MEMr_reserved_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e -val MEMr_reserved_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e - -let MEMr addrsize size hexRAM addr = read_mem Read_plain addr size -let MEMr_acquire addrsize size hexRAM addr = read_mem Read_RISCV_acquire addr size -let MEMr_strong_acquire addrsize size hexRAM addr = read_mem Read_RISCV_strong_acquire addr size -let MEMr_reserved addrsize size hexRAM addr = read_mem Read_RISCV_reserved addr size -let MEMr_reserved_acquire addrsize size hexRAM addr = read_mem Read_RISCV_reserved_acquire addr size -let MEMr_reserved_strong_acquire addrsize size hexRAM addr = read_mem Read_RISCV_reserved_strong_acquire addr size - -val write_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b => - integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e -let write_ram addrsize size hexRAM address value = - write_mem_val value - -val read_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b => - integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e -let read_ram addrsize size hexRAM address = - read_mem Read_plain address size - -val load_reservation : forall 'a. Size 'a => bitvector 'a -> unit -let load_reservation addr = () - -let speculate_conditional_success _ = excl_result () - -let cancel_reservation () = () - -val plat_ram_base : forall 'a. Size 'a => unit -> bitvector 'a -let plat_ram_base () = wordFromInteger 0 -declare ocaml target_rep function plat_ram_base = `Platform.dram_base` - -val plat_ram_size : forall 'a. Size 'a => unit -> bitvector 'a -let plat_ram_size () = wordFromInteger 0 -declare ocaml target_rep function plat_ram_size = `Platform.dram_size` - -val plat_rom_base : forall 'a. Size 'a => unit -> bitvector 'a -let plat_rom_base () = wordFromInteger 0 -declare ocaml target_rep function plat_rom_base = `Platform.rom_base` - -val plat_rom_size : forall 'a. Size 'a => unit -> bitvector 'a -let plat_rom_size () = wordFromInteger 0 -declare ocaml target_rep function plat_rom_size = `Platform.rom_size` - -val plat_clint_base : forall 'a. Size 'a => unit -> bitvector 'a -let plat_clint_base () = wordFromInteger 0 -declare ocaml target_rep function plat_clint_base = `Platform.clint_base` - -val plat_clint_size : forall 'a. Size 'a => unit -> bitvector 'a -let plat_clint_size () = wordFromInteger 0 -declare ocaml target_rep function plat_clint_size = `Platform.clint_size` - -val plat_enable_dirty_update : unit -> bool -let plat_enable_dirty_update () = false -declare ocaml target_rep function plat_enable_dirty_update = `Platform.enable_dirty_update` - -val plat_enable_misaligned_access : unit -> bool -let plat_enable_misaligned_access () = false -declare ocaml target_rep function plat_enable_misaligned_access = `Platform.enable_misaligned_access` - -val plat_mtval_has_illegal_inst_bits : unit -> bool -let plat_mtval_has_illegal_inst_bits () = false -declare ocaml target_rep function plat_mtval_has_illegal_inst_bits = `Platform.mtval_has_illegal_inst_bits` - -val plat_insns_per_tick : unit -> integer -let plat_insns_per_tick () = 1 -declare ocaml target_rep function plat_insns_per_tick = `Platform.insns_per_tick` - -val plat_htif_tohost : forall 'a. Size 'a => unit -> bitvector 'a -let plat_htif_tohost () = wordFromInteger 0 -declare ocaml target_rep function plat_htif_tohost = `Platform.htif_tohost` - -val plat_term_write : forall 'a. Size 'a => bitvector 'a -> unit -let plat_term_write _ = () -declare ocaml target_rep function plat_term_write = `Platform.term_write` - -val plat_term_read : forall 'a. Size 'a => unit -> bitvector 'a -let plat_term_read () = wordFromInteger 0 -declare ocaml target_rep function plat_term_read = `Platform.term_read` - -val shift_bits_right : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a -let shift_bits_right v m = shiftr v (uint m) -val shift_bits_left : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a -let shift_bits_left v m = shiftl v (uint m) - -val print_string : string -> string -> unit -let print_string msg s = () (* print_endline (msg ^ s) *) - -val prerr_string : string -> string -> unit -let prerr_string msg s = prerr_endline (msg ^ s) - -val prerr_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit -let prerr_bits msg bs = prerr_endline (msg ^ (show_bitlist (bits_of bs))) - -val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit -let print_bits msg bs = () (* print_endline (msg ^ (show_bitlist (bits_of bs))) *) diff --git a/riscv/riscv_extras.v b/riscv/riscv_extras.v deleted file mode 100644 index 820e3f3a..00000000 --- a/riscv/riscv_extras.v +++ /dev/null @@ -1,134 +0,0 @@ -Require Import Sail2_instr_kinds. -Require Import Sail2_values. -Require Import Sail2_operators_mwords. -Require Import Sail2_prompt_monad. -Require Import Sail2_prompt. -Require Import String. -Require Import List. -Import List.ListNotations. - -Axiom real : Type. - -Definition MEM_fence_rw_rw {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_rw_rw. -Definition MEM_fence_r_rw {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_r_rw. -Definition MEM_fence_r_r {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_r_r. -Definition MEM_fence_rw_w {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_rw_w. -Definition MEM_fence_w_w {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_w_w. -Definition MEM_fence_w_rw {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_w_rw. -Definition MEM_fence_rw_r {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_rw_r. -Definition MEM_fence_r_w {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_r_w. -Definition MEM_fence_w_r {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_w_r. -Definition MEM_fence_i {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_i. -(* -val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -val MEMea_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -val MEMea_conditional : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -val MEMea_conditional_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -*) -Definition MEMea {rv a e} (addr : mword a) size : monad rv unit e := write_mem_ea Write_plain addr size. -Definition MEMea_release {rv a e} (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_release addr size. -Definition MEMea_strong_release {rv a e} (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_strong_release addr size. -Definition MEMea_conditional {rv a e} (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_conditional addr size. -Definition MEMea_conditional_release {rv a e} (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_conditional_release addr size. -Definition MEMea_conditional_strong_release {rv a e} (addr : mword a) size : monad rv unit e - := write_mem_ea Write_RISCV_conditional_strong_release addr size. - - -(* Some wrappers copied from aarch64_extras *) -(* TODO: Harmonise into a common library *) -(* -Definition get_slice_int_bl len n lo := - (* TODO: Is this the intended behaviour? *) - let hi := lo + len - 1 in - let bs := bools_of_int (hi + 1) n in - subrange_list false bs hi lo - -val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a -Definition get_slice_int len n lo := of_bools (get_slice_int_bl len n lo) -*) -Definition write_ram {rv e} m size (hexRAM : mword m) (addr : mword m) (data : mword (8 * size)) : monad rv bool e := - write_mem_val data. - -Definition read_ram {rv e} m size `{ArithFact (size >= 0)} (_ : mword m) (addr : mword m) : monad rv (mword (8 * size)) e := - read_mem Read_plain addr size. -(* -Definition string_of_bits bs := string_of_bv (bits_of bs). -Definition string_of_int := show - -Definition _sign_extend bits len := maybe_failwith (of_bits (exts_bv len bits)) -Definition _zero_extend bits len := maybe_failwith (of_bits (extz_bv len bits)) -*) -Definition shift_bits_left {a b} (v : mword a) (n : mword b) : mword a := - shiftl v (int_of_mword false n). - -Definition shift_bits_right {a b} (v : mword a) (n : mword b) : mword a := - shiftr v (int_of_mword false n). - -Definition shift_bits_right_arith {a b} (v : mword a) (n : mword b) : mword a := - arith_shiftr v (int_of_mword false n). - -(* Use constants for undefined values for now *) -Definition internal_pick {rv a e} (vs : list a) : monad rv a e := -match vs with -| (h::_) => returnm h -| _ => Fail "empty list in internal_pick" -end. -Definition undefined_string {rv e} (_:unit) : monad rv string e := returnm ""%string. -Definition undefined_unit {rv e} (_:unit) : monad rv unit e := returnm tt. -Definition undefined_int {rv e} (_:unit) : monad rv Z e := returnm (0:ii). -(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*) -Definition undefined_vector {rv a e} len (u : a) `{ArithFact (len >= 0)} : monad rv (vec a len) e := returnm (vec_init u len). -(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) -Definition undefined_bitvector {rv e} len `{ArithFact (len >= 0)} : monad rv (mword len) e := returnm (mword_of_int 0). -(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) -Definition undefined_bits {rv e} := @undefined_bitvector rv e. -Definition undefined_bit {rv e} (_:unit) : monad rv bitU e := returnm BU. -(*Definition undefined_real {rv e} (_:unit) : monad rv real e := returnm (realFromFrac 0 1).*) -Definition undefined_range {rv e} i j `{ArithFact (i <= j)} : monad rv {z : Z & ArithFact (i <= z /\ z <= j)} e := returnm (build_ex i). -Definition undefined_atom {rv e} i : monad rv Z e := returnm i. -Definition undefined_nat {rv e} (_:unit) : monad rv Z e := returnm (0:ii). - -Definition skip {rv e} (_:unit) : monad rv unit e := returnm tt. - -(*val elf_entry : unit -> integer*) -Definition elf_entry (_:unit) : Z := 0. -(*declare ocaml target_rep function elf_entry := `Elf_loader.elf_entry`*) - -Definition print_bits {n} msg (bs : mword n) := prerr_endline (msg ++ (string_of_bits bs)). - -(*val get_time_ns : unit -> integer*) -Definition get_time_ns (_:unit) : Z := 0. -(*declare ocaml target_rep function get_time_ns := `(fun () -> Big_int.of_int (int_of_float (1e9 *. Unix.gettimeofday ())))`*) - -Definition eq_bit (x : bitU) (y : bitU) : bool := - match x, y with - | B0, B0 => true - | B1, B1 => true - | BU, BU => true - | _,_ => false - end. - -Require Import Zeuclid. -Definition euclid_modulo (m n : Z) `{ArithFact (n > 0)} : {z : Z & ArithFact (0 <= z <= n-1)}. -apply existT with (x := ZEuclid.modulo m n). -constructor. -destruct H. -assert (Z.abs n = n). { rewrite Z.abs_eq; auto with zarith. } -rewrite <- H at 3. -lapply (ZEuclid.mod_always_pos m n); omega. -Qed. - -(* Override the more general version *) - -Definition mults_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mults_vec l r. -Definition mult_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mult_vec l r. - - -Definition print_endline (_:string) : unit := tt. -Definition prerr_endline (_:string) : unit := tt. -Definition prerr_string (_:string) : unit := tt. -Definition putchar {T} (_:T) : unit := tt. -Require DecimalString. -Definition string_of_int z := DecimalString.NilZero.string_of_int (Z.to_int z). diff --git a/riscv/riscv_extras_sequential.lem b/riscv/riscv_extras_sequential.lem deleted file mode 100644 index 7028d5b8..00000000 --- a/riscv/riscv_extras_sequential.lem +++ /dev/null @@ -1,135 +0,0 @@ -open import Pervasives -open import Pervasives_extra -open import Sail2_instr_kinds -open import Sail2_values -open import Sail2_operators_mwords -open import Sail2_prompt_monad -open import Sail2_prompt - -type bitvector 'a = mword 'a - -let MEM_fence_rw_rw () = barrier Barrier_RISCV_rw_rw -let MEM_fence_r_rw () = barrier Barrier_RISCV_r_rw -let MEM_fence_r_r () = barrier Barrier_RISCV_r_r -let MEM_fence_rw_w () = barrier Barrier_RISCV_rw_w -let MEM_fence_w_w () = barrier Barrier_RISCV_w_w -let MEM_fence_w_rw () = barrier Barrier_RISCV_w_rw -let MEM_fence_rw_r () = barrier Barrier_RISCV_rw_r -let MEM_fence_r_w () = barrier Barrier_RISCV_r_w -let MEM_fence_w_r () = barrier Barrier_RISCV_w_r -let MEM_fence_i () = barrier Barrier_RISCV_i - -val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -val MEMea_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -val MEMea_conditional : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -val MEMea_conditional_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e - -let MEMea addr size = write_mem_ea Write_plain addr size -let MEMea_release addr size = write_mem_ea Write_RISCV_release addr size -let MEMea_strong_release addr size = write_mem_ea Write_RISCV_strong_release addr size -let MEMea_conditional addr size = write_mem_ea Write_RISCV_conditional addr size -let MEMea_conditional_release addr size = write_mem_ea Write_RISCV_conditional_release addr size -let MEMea_conditional_strong_release addr size - = write_mem_ea Write_RISCV_conditional_strong_release addr size - -val MEMr : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e -val MEMr_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e -val MEMr_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e -val MEMr_reserved : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e -val MEMr_reserved_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e -val MEMr_reserved_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e - -let MEMr addrsize size hexRAM addr = read_mem Read_plain addr size -let MEMr_acquire addrsize size hexRAM addr = read_mem Read_RISCV_acquire addr size -let MEMr_strong_acquire addrsize size hexRAM addr = read_mem Read_RISCV_strong_acquire addr size -let MEMr_reserved addrsize size hexRAM addr = read_mem Read_RISCV_reserved addr size -let MEMr_reserved_acquire addrsize size hexRAM addr = read_mem Read_RISCV_reserved_acquire addr size -let MEMr_reserved_strong_acquire addrsize size hexRAM addr = read_mem Read_RISCV_reserved_strong_acquire addr size - -val write_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b => - integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e -let write_ram addrsize size hexRAM address value = - write_mem_val value - -val read_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b => - integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e -let read_ram addrsize size hexRAM address = - read_mem Read_plain address size - -val load_reservation : forall 'a. Size 'a => bitvector 'a -> unit -let load_reservation addr = () - -let speculate_conditional_success _ = excl_result () - -let cancel_reservation () = () - -val plat_ram_base : forall 'a. Size 'a => unit -> bitvector 'a -let plat_ram_base () = wordFromInteger 0 -declare ocaml target_rep function plat_ram_base = `Platform.dram_base` - -val plat_ram_size : forall 'a. Size 'a => unit -> bitvector 'a -let plat_ram_size () = wordFromInteger 0 -declare ocaml target_rep function plat_ram_size = `Platform.dram_size` - -val plat_rom_base : forall 'a. Size 'a => unit -> bitvector 'a -let plat_rom_base () = wordFromInteger 0 -declare ocaml target_rep function plat_rom_base = `Platform.rom_base` - -val plat_rom_size : forall 'a. Size 'a => unit -> bitvector 'a -let plat_rom_size () = wordFromInteger 0 -declare ocaml target_rep function plat_rom_size = `Platform.rom_size` - -val plat_clint_base : forall 'a. Size 'a => unit -> bitvector 'a -let plat_clint_base () = wordFromInteger 0 -declare ocaml target_rep function plat_clint_base = `Platform.clint_base` - -val plat_clint_size : forall 'a. Size 'a => unit -> bitvector 'a -let plat_clint_size () = wordFromInteger 0 -declare ocaml target_rep function plat_clint_size = `Platform.clint_size` - -val plat_enable_dirty_update : unit -> bool -let plat_enable_dirty_update () = false -declare ocaml target_rep function plat_enable_dirty_update = `Platform.enable_dirty_update` - -val plat_enable_misaligned_access : unit -> bool -let plat_enable_misaligned_access () = false -declare ocaml target_rep function plat_enable_misaligned_access = `Platform.enable_misaligned_access` - -val plat_mtval_has_illegal_inst_bits : unit -> bool -let plat_mtval_has_illegal_inst_bits () = false -declare ocaml target_rep function plat_mtval_has_illegal_inst_bits = `Platform.mtval_has_illegal_inst_bits` - -val plat_insns_per_tick : unit -> integer -let plat_insns_per_tick () = 1 -declare ocaml target_rep function plat_insns_per_tick = `Platform.insns_per_tick` - -val plat_htif_tohost : forall 'a. Size 'a => unit -> bitvector 'a -let plat_htif_tohost () = wordFromInteger 0 -declare ocaml target_rep function plat_htif_tohost = `Platform.htif_tohost` - -val plat_term_write : forall 'a. Size 'a => bitvector 'a -> unit -let plat_term_write _ = () -declare ocaml target_rep function plat_term_write = `Platform.term_write` - -val plat_term_read : forall 'a. Size 'a => unit -> bitvector 'a -let plat_term_read () = wordFromInteger 0 -declare ocaml target_rep function plat_term_read = `Platform.term_read` - -val shift_bits_right : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a -let shift_bits_right v m = shiftr v (uint m) -val shift_bits_left : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a -let shift_bits_left v m = shiftl v (uint m) - -val print_string : string -> string -> unit -let print_string msg s = () (* print_endline (msg ^ s) *) - -val prerr_string : string -> string -> unit -let prerr_string msg s = prerr_endline (msg ^ s) - -val prerr_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit -let prerr_bits msg bs = prerr_endline (msg ^ (show_bitlist (bits_of bs))) - -val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit -let print_bits msg bs = () (* print_endline (msg ^ (show_bitlist (bits_of bs))) *) diff --git a/riscv/riscv_insts_begin.sail b/riscv/riscv_insts_begin.sail deleted file mode 100644 index 56fd8b43..00000000 --- a/riscv/riscv_insts_begin.sail +++ /dev/null @@ -1,19 +0,0 @@ -/* Instruction definitions. - * - * This includes decoding, execution, and assembly parsing and printing. - */ - -scattered union ast - -/* returns whether an instruction was retired, used for computing minstret */ -val execute : ast -> bool effect {escape, wreg, rreg, wmv, eamem, rmem, barr, exmem} -scattered function execute - -val assembly : ast <-> string -scattered mapping assembly - -val encdec : ast <-> bits(32) -scattered mapping encdec - -val encdec_compressed : ast <-> bits(16) -scattered mapping encdec_compressed diff --git a/riscv/riscv_insts_end.sail b/riscv/riscv_insts_end.sail deleted file mode 100644 index 144f06e3..00000000 --- a/riscv/riscv_insts_end.sail +++ /dev/null @@ -1,15 +0,0 @@ -/* End definitions */ -end ast -end execute -end assembly -end encdec -end encdec_compressed - -val cast print_insn : ast -> string -function print_insn insn = assembly(insn) - -val decode : bits(32) -> option(ast) effect pure -function decode bv = Some(encdec(bv)) - -val decodeCompressed : bits(16) -> option(ast) effect pure -function decodeCompressed bv = Some(encdec_compressed(bv)) diff --git a/riscv/riscv_jalr_rmem.sail b/riscv/riscv_jalr_rmem.sail deleted file mode 100644 index daf4bb01..00000000 --- a/riscv/riscv_jalr_rmem.sail +++ /dev/null @@ -1,10 +0,0 @@ -/* The definition for the memory model. */ - -function clause execute (RISCV_JALR(imm, rs1, rd)) = { - /* FIXME: this does not check for a misaligned target address. See riscv_jalr_seq.sail. */ - /* write rd before anything else to prevent unintended strength */ - X(rd) = nextPC; /* compatible with JALR, C.JR and C.JALR */ - let newPC : xlenbits = X(rs1) + EXTS(imm); - nextPC = newPC[63..1] @ 0b0; - true -} diff --git a/riscv/riscv_jalr_seq.sail b/riscv/riscv_jalr_seq.sail deleted file mode 100644 index fcf9526e..00000000 --- a/riscv/riscv_jalr_seq.sail +++ /dev/null @@ -1,19 +0,0 @@ -/* The definition for the sequential model. */ - -function clause execute (RISCV_JALR(imm, rs1, rd)) = { -/* For the sequential model, the memory-model definition doesn't work directly - if rs1 = rd. We would effectively have to keep a regfile for reads and another for - writes, and swap on instruction completion. This could perhaps be optimized in - some manner, but for now, we just keep a reordered definition to improve simulator - performance. -*/ - let newPC : xlenbits = (X(rs1) + EXTS(imm))[63..1] @ 0b0; - if newPC[1] & (~ (haveRVC())) then { - handle_mem_exception(newPC, E_Fetch_Addr_Align); - false; - } else { - X(rd) = nextPC; - nextPC = newPC; - true - } -} diff --git a/riscv/riscv_mem.sail b/riscv/riscv_mem.sail deleted file mode 100644 index 3d380380..00000000 --- a/riscv/riscv_mem.sail +++ /dev/null @@ -1,190 +0,0 @@ -/* Physical memory model. - * - * This assumes that the platform memory map has been defined, so that accesses - * to MMIO regions can be dispatched. - */ - -function is_aligned_addr forall 'n. (addr : xlenbits, width : atom('n)) -> bool = - unsigned(addr) % width == 0 - -// only used for actual memory regions, to avoid MMIO effects -function phys_mem_read forall 'n, 'n >= 0. (t : ReadType, addr : xlenbits, width : atom('n), aq : bool, rl: bool, res : bool) -> MemoryOpResult(bits(8 * 'n)) = - match (t, __RISCV_read(addr, width, aq, rl, res)) { - (Instruction, None()) => MemException(E_Fetch_Access_Fault), - (Data, None()) => MemException(E_Load_Access_Fault), - (_, Some(v)) => { print_mem("mem[" ^ t ^ "," ^ BitStr(addr) ^ "] -> " ^ BitStr(v)); - MemValue(v) } - } - -function checked_mem_read forall 'n, 'n > 0. (t : ReadType, addr : xlenbits, width : atom('n), aq : bool, rl : bool, res: bool) -> MemoryOpResult(bits(8 * 'n)) = - /* treat MMIO regions as not executable for now. TODO: this should actually come from PMP/PMA. */ - if t == Data & within_mmio_readable(addr, width) - then mmio_read(addr, width) - else if within_phys_mem(addr, width) - then phys_mem_read(t, addr, width, aq, rl, res) - else MemException(E_Load_Access_Fault) - -/* Atomic accesses can be done to MMIO regions, e.g. in kernel access to device registers. */ - -val MEMr : forall 'n, 'n > 0. (xlenbits, atom('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rmem, rreg} -val MEMr_acquire : forall 'n, 'n > 0. (xlenbits, atom('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rmem, rreg} -val MEMr_strong_acquire : forall 'n, 'n > 0. (xlenbits, atom('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rmem, rreg} -val MEMr_reserved : forall 'n, 'n > 0. (xlenbits, atom('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rmem, rreg} -val MEMr_reserved_acquire : forall 'n, 'n > 0. (xlenbits, atom('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rmem, rreg} -val MEMr_reserved_strong_acquire : forall 'n, 'n > 0. (xlenbits, atom('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rmem, rreg} - -function MEMr (addr, width) = checked_mem_read(Data, addr, width, false, false, false) -function MEMr_acquire (addr, width) = checked_mem_read(Data, addr, width, true, false, false) -function MEMr_strong_acquire (addr, width) = checked_mem_read(Data, addr, width, true, true, false) -function MEMr_reserved (addr, width) = checked_mem_read(Data, addr, width, false, false, true) -function MEMr_reserved_acquire (addr, width) = checked_mem_read(Data, addr, width, true, false, true) -function MEMr_reserved_strong_acquire (addr, width) = checked_mem_read(Data, addr, width, true, true, true) - -$ifdef RVFI_DII -val rvfi_read : forall 'n, 'n > 0. (xlenbits, atom('n), MemoryOpResult(bits(8 * 'n))) -> unit effect {wreg} -function rvfi_read (addr, width, result) = { - rvfi_exec->rvfi_mem_addr() = addr; - match result { - MemValue(v) => - if width <= 8 - then { - rvfi_exec->rvfi_mem_wdata() = zero_extend(v,64); - rvfi_exec->rvfi_mem_wmask() = to_bits(8,width) - } else (), - MemException(_) => () - }; -} -$else -val rvfi_read : forall 'n, 'n > 0. (xlenbits, atom('n), MemoryOpResult(bits(8 * 'n))) -> unit -function rvfi_read (addr, width, value) = () -$endif - -/* NOTE: The rreg effect is due to MMIO. */ -$ifdef RVFI_DII -val mem_read : forall 'n, 'n > 0. (xlenbits, atom('n), bool, bool, bool) -> MemoryOpResult(bits(8 * 'n)) effect {wreg, rmem, rreg, escape} -$else -val mem_read : forall 'n, 'n > 0. (xlenbits, atom('n), bool, bool, bool) -> MemoryOpResult(bits(8 * 'n)) effect {rmem, rreg, escape} -$endif - -function mem_read (addr, width, aq, rl, res) = { - let result : MemoryOpResult(bits(8 * 'n)) = - if (aq | res) & (~ (is_aligned_addr(addr, width))) - then MemException(E_Load_Addr_Align) - else match (aq, rl, res) { - (false, false, false) => checked_mem_read(Data, addr, width, false, false, false), - (true, false, false) => MEMr_acquire(addr, width), - (false, false, true) => MEMr_reserved(addr, width), - (true, false, true) => MEMr_reserved_acquire(addr, width), - (false, true, false) => throw(Error_not_implemented("load.rl")), - (true, true, false) => MEMr_strong_acquire(addr, width), - (false, true, true) => throw(Error_not_implemented("lr.rl")), - (true, true, true) => MEMr_reserved_strong_acquire(addr, width) - }; - rvfi_read(addr, width, result); - result -} - -val MEMea = {lem: "MEMea", coq: "MEMea", _: "memea"} : forall 'n. - (xlenbits, atom('n)) -> unit effect {eamem} -val MEMea_release = {lem: "MEMea_release", coq: "MEMea_release", _: "memea"} : forall 'n. - (xlenbits, atom('n)) -> unit effect {eamem} -val MEMea_strong_release = {lem: "MEMea_strong_release", coq: "MEMea_strong_release", _: "memea"} : forall 'n. - (xlenbits, atom('n)) -> unit effect {eamem} -val MEMea_conditional = {lem: "MEMea_conditional", coq: "MEMea_conditional", _: "memea"} : forall 'n. - (xlenbits, atom('n)) -> unit effect {eamem} -val MEMea_conditional_release = {lem: "MEMea_conditional_release", coq: "MEMea_conditional_release", _: "memea"} : forall 'n. - (xlenbits, atom('n)) -> unit effect {eamem} -val MEMea_conditional_strong_release = {lem: "MEMea_conditional_strong_release", coq: "MEMea_conditional_strong_release", _: "memea"} : forall 'n. - (xlenbits, atom('n)) -> unit effect {eamem} - -val mem_write_ea : forall 'n. (xlenbits, atom('n), bool, bool, bool) -> MemoryOpResult(unit) effect {eamem, escape} - -function mem_write_ea (addr, width, aq, rl, con) = { - if (rl | con) & (~ (is_aligned_addr(addr, width))) - then MemException(E_SAMO_Addr_Align) - else match (aq, rl, con) { - (false, false, false) => MemValue(MEMea(addr, width)), - (false, true, false) => MemValue(MEMea_release(addr, width)), - (false, false, true) => MemValue(MEMea_conditional(addr, width)), - (false, true , true) => MemValue(MEMea_conditional_release(addr, width)), - (true, false, false) => throw(Error_not_implemented("store.aq")), - (true, true, false) => MemValue(MEMea_strong_release(addr, width)), - (true, false, true) => throw(Error_not_implemented("sc.aq")), - (true, true , true) => MemValue(MEMea_conditional_strong_release(addr, width)) - } -} - -// only used for actual memory regions, to avoid MMIO effects -function phys_mem_write forall 'n. (addr : xlenbits, width : atom('n), data: bits(8 * 'n)) -> MemoryOpResult(bool) = { - print_mem("mem[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data)); - MemValue(__RISCV_write(addr, width, data)) -} - -// dispatches to MMIO regions or physical memory regions depending on physical memory map -function checked_mem_write forall 'n, 'n > 0. (addr : xlenbits, width : atom('n), data: bits(8 * 'n)) -> MemoryOpResult(bool) = - if within_mmio_writable(addr, width) - then mmio_write(addr, width, data) - else if within_phys_mem(addr, width) - then phys_mem_write(addr, width, data) - else MemException(E_SAMO_Access_Fault) - -/* Atomic accesses can be done to MMIO regions, e.g. in kernel access to device registers. */ - -val MEMval : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(bool) effect {wmv, rreg, wreg} -val MEMval_release : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(bool) effect {wmv, rreg, wreg} -val MEMval_strong_release : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(bool) effect {wmv, rreg, wreg} -val MEMval_conditional : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(bool) effect {wmv, rreg, wreg} -val MEMval_conditional_release : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(bool) effect {wmv, rreg, wreg} -val MEMval_conditional_strong_release : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> MemoryOpResult(bool) effect {wmv, rreg, wreg} - -function MEMval (addr, width, data) = checked_mem_write(addr, width, data) -function MEMval_release (addr, width, data) = checked_mem_write(addr, width, data) -function MEMval_strong_release (addr, width, data) = checked_mem_write(addr, width, data) -function MEMval_conditional (addr, width, data) = checked_mem_write(addr, width, data) -function MEMval_conditional_release (addr, width, data) = checked_mem_write(addr, width, data) -function MEMval_conditional_strong_release (addr, width, data) = checked_mem_write(addr, width, data) - - -$ifdef RVFI_DII -val rvfi_write : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> unit effect {wreg} -function rvfi_write (addr, width, value) = { - rvfi_exec->rvfi_mem_addr() = addr; - if width <= 8 then { - rvfi_exec->rvfi_mem_wdata() = zero_extend(value,64); - rvfi_exec->rvfi_mem_wmask() = to_bits(8,width); - } -} -$else -val rvfi_write : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> unit -function rvfi_write (addr, width, value) = () -$endif - -/* NOTE: The wreg effect is due to MMIO, the rreg is due to checking mtime. */ -val mem_write_value : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n), bool, bool, bool) -> MemoryOpResult(bool) effect {wmv, rreg, wreg, escape} - -function mem_write_value (addr, width, value, aq, rl, con) = { - rvfi_write(addr, width, value); - if (rl | con) & (~ (is_aligned_addr(addr, width))) - then MemException(E_SAMO_Addr_Align) - else match (aq, rl, con) { - (false, false, false) => checked_mem_write(addr, width, value), - (false, true, false) => MEMval_release(addr, width, value), - (false, false, true) => MEMval_conditional(addr, width, value), - (false, true, true) => MEMval_conditional_release(addr, width, value), - (true, false, false) => throw(Error_not_implemented("store.aq")), - (true, true, false) => MEMval_strong_release(addr, width, value), - (true, false, true) => throw(Error_not_implemented("sc.aq")), - (true, true, true) => MEMval_conditional_strong_release(addr, width, value) - } -} - -val MEM_fence_rw_rw = {lem: "MEM_fence_rw_rw", coq: "MEM_fence_rw_rw", _: "skip"} : unit -> unit effect {barr} -val MEM_fence_r_rw = {lem: "MEM_fence_r_rw", coq: "MEM_fence_r_rw", _: "skip"} : unit -> unit effect {barr} -val MEM_fence_r_r = {lem: "MEM_fence_r_r", coq: "MEM_fence_r_r", _: "skip"} : unit -> unit effect {barr} -val MEM_fence_rw_w = {lem: "MEM_fence_rw_w", coq: "MEM_fence_rw_w", _: "skip"} : unit -> unit effect {barr} -val MEM_fence_w_w = {lem: "MEM_fence_w_w", coq: "MEM_fence_w_w", _: "skip"} : unit -> unit effect {barr} -val MEM_fence_w_rw = {lem: "MEM_fence_w_rw", coq: "MEM_fence_w_rw", _: "skip"} : unit -> unit effect {barr} -val MEM_fence_rw_r = {lem: "MEM_fence_rw_r", coq: "MEM_fence_rw_r", _: "skip"} : unit -> unit effect {barr} -val MEM_fence_r_w = {lem: "MEM_fence_r_w", coq: "MEM_fence_r_w", _: "skip"} : unit -> unit effect {barr} -val MEM_fence_w_r = {lem: "MEM_fence_w_r", coq: "MEM_fence_w_r", _: "skip"} : unit -> unit effect {barr} -val MEM_fence_i = {lem: "MEM_fence_i", coq: "MEM_fence_i", _: "skip"} : unit -> unit effect {barr} diff --git a/riscv/riscv_platform.c b/riscv/riscv_platform.c deleted file mode 100644 index f0aff76a..00000000 --- a/riscv/riscv_platform.c +++ /dev/null @@ -1,71 +0,0 @@ -#include "sail.h" -#include "rts.h" -#include "riscv_prelude.h" -#include "riscv_platform_impl.h" - -/* This file contains the definitions of the C externs of Sail model. */ - -static mach_bits reservation = 0; -static bool reservation_valid = false; - -bool plat_enable_dirty_update(unit u) -{ return rv_enable_dirty_update; } - -bool plat_enable_misaligned_access(unit u) -{ return rv_enable_misaligned; } - -bool plat_mtval_has_illegal_inst_bits(unit u) -{ return rv_mtval_has_illegal_inst_bits; } - -mach_bits plat_ram_base(unit u) -{ return rv_ram_base; } - -mach_bits plat_ram_size(unit u) -{ return rv_ram_size; } - -mach_bits plat_rom_base(unit u) -{ return rv_rom_base; } - -mach_bits plat_rom_size(unit u) -{ return rv_rom_size; } - -mach_bits plat_clint_base(unit u) -{ return rv_clint_base; } - -mach_bits plat_clint_size(unit u) -{ return rv_clint_size; } - -unit load_reservation(mach_bits addr) -{ - reservation = addr; - reservation_valid = true; - return UNIT; -} - -bool match_reservation(mach_bits addr) -{ return reservation_valid && reservation == addr; } - -unit cancel_reservation(unit u) -{ - reservation_valid = false; - return UNIT; -} - -unit plat_term_write(mach_bits s) -{ char c = s & 0xff; - plat_term_write_impl(c); - return UNIT; -} - -void plat_insns_per_tick(sail_int *rop, unit u) -{ } - -mach_bits plat_htif_tohost(unit u) -{ - return rv_htif_tohost; -} - -unit memea(mach_bits len, sail_int n) -{ - return UNIT; -} diff --git a/riscv/riscv_platform.h b/riscv/riscv_platform.h deleted file mode 100644 index 93782660..00000000 --- a/riscv/riscv_platform.h +++ /dev/null @@ -1,28 +0,0 @@ -#pragma once -#include "sail.h" - -bool plat_enable_dirty_update(unit); -bool plat_enable_misaligned_access(unit); -bool plat_mtval_has_illegal_inst_bits(unit); - -mach_bits plat_ram_base(unit); -mach_bits plat_ram_size(unit); -bool within_phys_mem(mach_bits, sail_int); - -mach_bits plat_rom_base(unit); -mach_bits plat_rom_size(unit); - -mach_bits plat_clint_base(unit); -mach_bits plat_clint_size(unit); - -unit load_reservation(mach_bits); -bool match_reservation(mach_bits); -unit cancel_reservation(unit); - -void plat_insns_per_tick(sail_int *rop, unit); - -unit plat_term_write(mach_bits); -mach_bits plat_htif_tohost(unit); - -unit memea(mach_bits, sail_int); - diff --git a/riscv/riscv_platform.sail b/riscv/riscv_platform.sail deleted file mode 100644 index aee72e47..00000000 --- a/riscv/riscv_platform.sail +++ /dev/null @@ -1,295 +0,0 @@ -/* Platform-specific definitions, and basic MMIO devices. */ - -/* Current constraints on this implementation are: - - it cannot access memory directly, but instead provides definitions for the physical memory model - - it can access system register state, needed to manipulate interrupt bits - - it relies on externs to get platform address information and doesn't hardcode them. -*/ - -/* Main memory */ -val plat_ram_base = {c: "plat_ram_base", ocaml: "Platform.dram_base", lem: "plat_ram_base"} : unit -> xlenbits -val plat_ram_size = {c: "plat_ram_size", ocaml: "Platform.dram_size", lem: "plat_ram_size"} : unit -> xlenbits - -/* whether the MMU should update dirty bits in PTEs */ -val plat_enable_dirty_update = {ocaml: "Platform.enable_dirty_update", - c: "plat_enable_dirty_update", - lem: "plat_enable_dirty_update"} : unit -> bool - -/* whether the platform supports misaligned accesses without trapping to M-mode. if false, - * misaligned loads/stores are trapped to Machine mode. - */ -val plat_enable_misaligned_access = {ocaml: "Platform.enable_misaligned_access", - c: "plat_enable_misaligned_access", - lem: "plat_enable_misaligned_access"} : unit -> bool - -/* whether mtval stores the bits of a faulting instruction on illegal instruction exceptions */ -val plat_mtval_has_illegal_inst_bits = {ocaml: "Platform.mtval_has_illegal_inst_bits", - c: "plat_mtval_has_illegal_inst_bits", - lem: "plat_mtval_has_illegal_inst_bits"} : unit -> bool - -/* ROM holding reset vector and device-tree DTB */ -val plat_rom_base = {ocaml: "Platform.rom_base", c: "plat_rom_base", lem: "plat_rom_base"} : unit -> xlenbits -val plat_rom_size = {ocaml: "Platform.rom_size", c: "plat_rom_size", lem: "plat_rom_size"} : unit -> xlenbits - -/* Location of clock-interface, which should match with the spec in the DTB */ -val plat_clint_base = {ocaml: "Platform.clint_base", c: "plat_clint_base", lem: "plat_clint_base"} : unit -> xlenbits -val plat_clint_size = {ocaml: "Platform.clint_size", c: "plat_clint_size", lem: "plat_clint_size"} : unit -> xlenbits - -/* Location of HTIF ports */ -val plat_htif_tohost = {ocaml: "Platform.htif_tohost", c: "plat_htif_tohost", lem: "plat_htif_tohost"} : unit -> xlenbits -// todo: fromhost - -val phys_mem_segments : unit -> list((xlenbits, xlenbits)) -function phys_mem_segments() = - (plat_rom_base (), plat_rom_size ()) :: - (plat_ram_base (), plat_ram_size ()) :: - [||] - -/* Physical memory map predicates */ - -function within_phys_mem forall 'n. (addr : xlenbits, width : atom('n)) -> bool = { - let ram_base = plat_ram_base (); - let rom_base = plat_rom_base (); - let ram_size = plat_ram_size (); - let rom_size = plat_rom_size (); - - /* todo: iterate over segment list */ - if ( ram_base <=_u addr - & (addr + sizeof('n)) <=_u (ram_base + ram_size)) - then true - else if ( rom_base <=_u addr - & (addr + sizeof('n)) <=_u (rom_base + rom_size)) - then true - else { - print_platform("within_phys_mem: " ^ BitStr(addr) ^ " not within phys-mem:"); - print_platform(" plat_rom_base: " ^ BitStr(rom_base)); - print_platform(" plat_rom_size: " ^ BitStr(rom_size)); - print_platform(" plat_ram_base: " ^ BitStr(ram_base)); - print_platform(" plat_ram_size: " ^ BitStr(ram_size)); - false - } -} - -function within_clint forall 'n. (addr : xlenbits, width : atom('n)) -> bool = - plat_clint_base() <=_u addr - & (addr + sizeof('n)) <=_u (plat_clint_base() + plat_clint_size()) - -function within_htif_writable forall 'n. (addr : xlenbits, width : atom('n)) -> bool = - plat_htif_tohost() == addr - -function within_htif_readable forall 'n. (addr : xlenbits, width : atom('n)) -> bool = - plat_htif_tohost() == addr - -/* CLINT (Core Local Interruptor), based on Spike. */ - -val plat_insns_per_tick = {ocaml: "Platform.insns_per_tick", c: "plat_insns_per_tick", lem: "plat_insns_per_tick"} : unit -> int - -// assumes a single hart, since this typically is a vector of per-hart registers. -register mtimecmp : xlenbits // memory-mapped internal clint register. - -/* CLINT memory-mapped IO */ - -/* relative address map: - * - * 0000 msip hart 0 -- memory-mapped software interrupt - * 0004 msip hart 1 - * 4000 mtimecmp hart 0 lo -- memory-mapped timer thresholds - * 4004 mtimecmp hart 0 hi - * 4008 mtimecmp hart 1 lo - * 400c mtimecmp hart 1 hi - * bff8 mtime lo -- memory-mapped clocktimer value - * bffc mtime hi - */ - -let MSIP_BASE : xlenbits = 0x0000000000000000 -let MTIMECMP_BASE : xlenbits = 0x0000000000004000 -let MTIME_BASE : xlenbits = 0x000000000000bff8 - -val clint_load : forall 'n, 'n > 0. (xlenbits, int('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rreg} -function clint_load(addr, width) = { - let addr = addr - plat_clint_base (); - /* FIXME: For now, only allow exact aligned access. */ - if addr == MSIP_BASE & ('n == 8 | 'n == 4) - then { - print_platform("clint[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mip.MSI())); - MemValue(zero_extend_type_hack(mip.MSI(), sizeof(8 * 'n))) - } - else if addr == MTIMECMP_BASE & ('n == 8) - then { - print_platform("clint[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mtimecmp)); - MemValue(zero_extend_type_hack(mtimecmp, 64)) /* FIXME: Redundant zero_extend currently required by Lem backend */ - } - else if addr == MTIME_BASE & ('n == 8) - then { - print_platform("clint[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mtime)); - MemValue(zero_extend_type_hack(mtime, 64)) - } - else { - print_platform("clint[" ^ BitStr(addr) ^ "] -> "); - MemException(E_Load_Access_Fault) - } -} - -function clint_dispatch() -> unit = { - print_platform("clint::tick mtime <- " ^ BitStr(mtime)); - mip->MTI() = false; - if mtimecmp <=_u mtime then { - print_platform(" clint timer pending at mtime " ^ BitStr(mtime)); - mip->MTI() = true - } -} - -/* The rreg effect is due to checking mtime. */ -val clint_store: forall 'n, 'n > 0. (xlenbits, int('n), bits(8 * 'n)) -> MemoryOpResult(bool) effect {rreg,wreg} -function clint_store(addr, width, data) = { - let addr = addr - plat_clint_base (); - if addr == MSIP_BASE & ('n == 8 | 'n == 4) then { - print_platform("clint[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data) ^ " (mip.MSI <- " ^ BitStr(data[0]) ^ ")"); - mip->MSI() = data[0] == 0b1; - clint_dispatch(); - MemValue(true) - } else if addr == MTIMECMP_BASE & 'n == 8 then { - print_platform("clint[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data) ^ " (mtimecmp)"); - mtimecmp = zero_extend(data, 64); /* FIXME: Redundant zero_extend currently required by Lem backend */ - clint_dispatch(); - MemValue(true) - } else { - print_platform("clint[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data) ^ " ()"); - MemException(E_SAMO_Access_Fault) - } -} - -val tick_clock : unit -> unit effect {rreg, wreg} -function tick_clock() = { - mcycle = mcycle + 1; - mtime = mtime + 1; - clint_dispatch() -} - -/* Basic terminal character I/O. */ - -val plat_term_write = {ocaml: "Platform.term_write", c: "plat_term_write", lem: "plat_term_write"} : bits(8) -> unit -val plat_term_read = {ocaml: "Platform.term_read", c: "plat_term_read", lem: "plat_term_read"} : unit -> bits(8) - -/* Spike's HTIF device interface, which multiplexes the above MMIO devices. */ - -bitfield htif_cmd : bits(64) = { - device : 63 .. 56, - cmd : 55 .. 48, - payload : 47 .. 0 -} - -register htif_tohost : xlenbits -register htif_done : bool -register htif_exit_code : xlenbits - - -/* Since the htif tohost port is only available at a single address, - * we'll assume here that physical memory model has correctly - * dispatched the address. - */ - -val htif_load : forall 'n, 'n > 0. (xlenbits, int('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rreg} -function htif_load(addr, width) = { - print_platform("htif[" ^ BitStr(addr) ^ "] -> " ^ BitStr(htif_tohost)); - /* FIXME: For now, only allow the expected access widths. */ - if width == 8 - then MemValue(zero_extend_type_hack(htif_tohost, 64)) /* FIXME: Redundant zero_extend currently required by Lem backend */ - else MemException(E_Load_Access_Fault) -} - -/* The wreg effect is an artifact of using 'register' to implement device state. */ -val htif_store: forall 'n, 0 < 'n <= 8. (xlenbits, int('n), bits(8 * 'n)) -> MemoryOpResult(bool) effect {wreg} -function htif_store(addr, width, data) = { - print_platform("htif[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data)); - /* Store the written value so that we can ack it later. */ - let cbits : xlenbits = EXTZ(data); - htif_tohost = cbits; - /* Process the cmd immediately; this is needed for terminal output. */ - let cmd = Mk_htif_cmd(cbits); - match cmd.device() { - 0x00 => { /* syscall-proxy */ - print_platform("htif-syscall-proxy cmd: " ^ BitStr(cmd.payload())); - if cmd.payload()[0] == 0b1 - then { - htif_done = true; - htif_exit_code = (zero_extend(cmd.payload(), xlen) >> 0b01) : xlenbits - } - else () - }, - 0x01 => { /* terminal */ - print_platform("htif-term cmd: " ^ BitStr(cmd.payload())); - match cmd.cmd() { - 0x00 => /* TODO: terminal input handling */ (), - 0x01 => plat_term_write(cmd.payload()[7..0]), - c => print("Unknown term cmd: " ^ BitStr(c)) - } - }, - d => print("htif-???? cmd: " ^ BitStr(data)) - }; - MemValue(true) -} - -val htif_tick : unit -> unit effect {rreg, wreg} -function htif_tick() = { - print_platform("htif::tick " ^ BitStr(htif_tohost)); - htif_tohost = EXTZ(0b0) /* htif ack */ -} - -/* Top-level MMIO dispatch */ - -function within_mmio_readable forall 'n. (addr : xlenbits, width : atom('n)) -> bool = - within_clint(addr, width) | (within_htif_readable(addr, width) & 1 <= 'n) - -function within_mmio_writable forall 'n. (addr : xlenbits, width : atom('n)) -> bool = - within_clint(addr, width) | (within_htif_writable(addr, width) & 'n <= 8) - -function mmio_read forall 'n, 'n > 0. (addr : xlenbits, width : atom('n)) -> MemoryOpResult(bits(8 * 'n)) = - if within_clint(addr, width) - then clint_load(addr, width) - else if within_htif_readable(addr, width) & (1 <= 'n) - then htif_load(addr, width) - else MemException(E_Load_Access_Fault) - -function mmio_write forall 'n, 'n > 0. (addr : xlenbits, width : atom('n), data: bits(8 * 'n)) -> MemoryOpResult(bool) = - if within_clint(addr, width) - then clint_store(addr, width, data) - else if within_htif_writable(addr, width) & 'n <= 8 - then htif_store(addr, width, data) - else MemException(E_SAMO_Access_Fault) - -/* Platform initialization and ticking. */ - -function init_platform() -> unit = { - htif_tohost = EXTZ(0b0); - htif_done = false; - htif_exit_code = EXTZ(0b0) -} - -function tick_platform() -> unit = { - cancel_reservation(); - htif_tick(); -} - -/* Platform-specific handling of instruction faults */ - -function handle_illegal() -> unit = { - let info = if plat_mtval_has_illegal_inst_bits () - then Some(instbits) - else None(); - let t : sync_exception = struct { trap = E_Illegal_Instr, - excinfo = info }; - nextPC = handle_exception(cur_privilege, CTL_TRAP(t), PC) -} - -/* Platform-specific wait-for-interrupt */ - -function platform_wfi() -> unit = { - /* speed execution by getting the timer to fire at the next instruction, - * since we currently don't have any other devices raising interrupts. - */ - if mtime <_u mtimecmp then { - mtime = mtimecmp; - mcycle = mtimecmp; - } -} \ No newline at end of file diff --git a/riscv/riscv_platform_impl.c b/riscv/riscv_platform_impl.c deleted file mode 100644 index 04a661c0..00000000 --- a/riscv/riscv_platform_impl.c +++ /dev/null @@ -1,29 +0,0 @@ -#include "riscv_platform_impl.h" -#include -#include - -/* Settings of the platform implementation, with common defaults. */ - -bool rv_enable_dirty_update = false; -bool rv_enable_misaligned = false; -bool rv_mtval_has_illegal_inst_bits = false; - -uint64_t rv_ram_base = UINT64_C(0x80000000); -uint64_t rv_ram_size = UINT64_C(0x80000000); - -uint64_t rv_rom_base = UINT64_C(0x1000); -uint64_t rv_rom_size = UINT64_C(0x100); - -uint64_t rv_clint_base = UINT64_C(0x2000000); -uint64_t rv_clint_size = UINT64_C(0xc0000); - -uint64_t rv_htif_tohost = UINT64_C(0x80001000); -uint64_t rv_insns_per_tick = UINT64_C(100); - -int term_fd = 1; // set during startup -void plat_term_write_impl(char c) -{ - if (write(term_fd, &c, sizeof(c)) < 0) { - fprintf(stderr, "Unable to write to terminal!\n"); - } -} diff --git a/riscv/riscv_platform_impl.h b/riscv/riscv_platform_impl.h deleted file mode 100644 index 85e25c95..00000000 --- a/riscv/riscv_platform_impl.h +++ /dev/null @@ -1,28 +0,0 @@ -#pragma once - -#include -#include - -/* Settings of the platform implementation. */ - -#define DEFAULT_RSTVEC 0x00001000 -#define SAIL_XLEN 64 - -extern bool rv_enable_dirty_update; -extern bool rv_enable_misaligned; -extern bool rv_mtval_has_illegal_inst_bits; - -extern uint64_t rv_ram_base; -extern uint64_t rv_ram_size; - -extern uint64_t rv_rom_base; -extern uint64_t rv_rom_size; - -extern uint64_t rv_clint_base; -extern uint64_t rv_clint_size; - -extern uint64_t rv_htif_tohost; -extern uint64_t rv_insns_per_tick; - -extern int term_fd; -void plat_term_write_impl(char c); diff --git a/riscv/riscv_prelude.c b/riscv/riscv_prelude.c deleted file mode 100644 index 16219137..00000000 --- a/riscv/riscv_prelude.c +++ /dev/null @@ -1,32 +0,0 @@ -#include "riscv_prelude.h" -#include "riscv_config.h" - -unit print_string(sail_string prefix, sail_string msg) -{ - printf("%s%s\n", prefix, msg); - return UNIT; -} - -unit print_instr(sail_string s) -{ - if (config_print_instr) printf("%s\n", s); - return UNIT; -} - -unit print_reg(sail_string s) -{ - if (config_print_reg) printf("%s\n", s); - return UNIT; -} - -unit print_mem_access(sail_string s) -{ - if (config_print_mem_access) printf("%s\n", s); - return UNIT; -} - -unit print_platform(sail_string s) -{ - if (config_print_platform) printf("%s\n", s); - return UNIT; -} diff --git a/riscv/riscv_prelude.h b/riscv/riscv_prelude.h deleted file mode 100644 index a296c7e9..00000000 --- a/riscv/riscv_prelude.h +++ /dev/null @@ -1,10 +0,0 @@ -#pragma once -#include "sail.h" -#include "rts.h" - -unit print_string(sail_string prefix, sail_string msg); - -unit print_instr(sail_string s); -unit print_reg(sail_string s); -unit print_mem_access(sail_string s); -unit print_platform(sail_string s); diff --git a/riscv/riscv_sail.h b/riscv/riscv_sail.h deleted file mode 100644 index 424b64b0..00000000 --- a/riscv/riscv_sail.h +++ /dev/null @@ -1,54 +0,0 @@ -/* Top-level interfaces to the Sail model. - Ideally, this would be autogenerated. - */ - -typedef int unit; -#define UNIT 0 -typedef uint64_t mach_bits; - -struct zMisa {mach_bits zMisa_chunk_0;}; -struct zMisa zmisa; - -void model_init(void); -void model_fini(void); - -unit zinit_platform(unit); -unit zinit_sys(unit); -bool zstep(sail_int); -unit ztick_clock(unit); -unit ztick_platform(unit); -unit z_set_Misa_C(struct zMisa*, mach_bits); - -#ifdef RVFI_DII -unit zrvfi_set_instr_packet(mach_bits); -mach_bits zrvfi_get_cmd(unit); -bool zrvfi_step(sail_int); -unit zrvfi_zzero_exec_packet(unit); -unit zrvfi_halt_exec_packet(unit); -void zrvfi_get_exec_packet(sail_bits *rop, unit); -#endif - -extern bool zhtif_done; -extern mach_bits zhtif_exit_code; -extern bool have_exception; - -/* machine state */ - -extern uint32_t zcur_privilege; - -extern mach_bits zPC; - -extern mach_bits - zx1, zx2, zx3, zx4, zx5, zx6, zx7, - zx8, zx9, zx10, zx11, zx12, zx13, zx14, zx15, - zx16, zx17, zx18, zx19, zx20, zx21, zx22, zx23, - zx24, zx25, zx26, zx27, zx28, zx29, zx30, zx31; - -extern mach_bits zmstatus; -extern mach_bits zmepc, zmtval; -extern mach_bits zsepc, zstval; - -struct zMcause {mach_bits zMcause_chunk_0;}; -struct zMcause zmcause, zscause; - -extern mach_bits zminstret; diff --git a/riscv/riscv_sim.c b/riscv/riscv_sim.c deleted file mode 100644 index d86a197d..00000000 --- a/riscv/riscv_sim.c +++ /dev/null @@ -1,680 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "elf.h" -#include "sail.h" -#include "rts.h" -#include "riscv_platform.h" -#include "riscv_platform_impl.h" -#include "riscv_sail.h" - -#ifdef ENABLE_SPIKE -#include "tv_spike_intf.h" -#else -struct tv_spike_t; -#endif - -/* Selected CSRs from riscv-isa-sim/riscv/encoding.h */ -#define CSR_STVEC 0x105 -#define CSR_SEPC 0x141 -#define CSR_SCAUSE 0x142 -#define CSR_STVAL 0x143 - -#define CSR_MSTATUS 0x300 -#define CSR_MISA 0x301 -#define CSR_MEDELEG 0x302 -#define CSR_MIDELEG 0x303 -#define CSR_MIE 0x304 -#define CSR_MTVEC 0x305 -#define CSR_MEPC 0x341 -#define CSR_MCAUSE 0x342 -#define CSR_MTVAL 0x343 -#define CSR_MIP 0x344 - -static bool do_dump_dts = false; -static bool disable_compressed = false; -struct tv_spike_t *s = NULL; -char *term_log = NULL; -char *dtb_file = NULL; -unsigned char *dtb = NULL; -size_t dtb_len = 0; -#ifdef RVFI_DII -static bool rvfi_dii = false; -static int rvfi_dii_port; -static int rvfi_dii_sock; -#endif - -unsigned char *spike_dtb = NULL; -size_t spike_dtb_len = 0; - -bool config_print_instr = true; -bool config_print_reg = true; -bool config_print_mem_access = true; -bool config_print_platform = true; - -static struct option options[] = { - {"enable-dirty", no_argument, 0, 'd'}, - {"enable-misaligned", no_argument, 0, 'm'}, - {"ram-size", required_argument, 0, 'z'}, - {"disable-compressed", no_argument, 0, 'C'}, - {"mtval-has-illegal-inst-bits", no_argument, 0, 'i'}, - {"dump-dts", no_argument, 0, 's'}, - {"device-tree-blob", required_argument, 0, 'b'}, - {"terminal-log", required_argument, 0, 't'}, -#ifdef RVFI_DII - {"rvfi-dii", required_argument, 0, 'r'}, -#endif - {"help", no_argument, 0, 'h'}, - {0, 0, 0, 0} -}; - -static void print_usage(const char *argv0, int ec) -{ -#ifdef RVFI_DII - fprintf(stdout, "Usage: %s [options] \n %s [options] -r \n", argv0, argv0); -#else - fprintf(stdout, "Usage: %s [options] \n", argv0); -#endif - struct option *opt = options; - while (opt->name) { - fprintf(stdout, "\t -%c\t %s\n", (char)opt->val, opt->name); - opt++; - } - exit(ec); -} - -static void dump_dts(void) -{ -#ifdef ENABLE_SPIKE - size_t dts_len = 0; - struct tv_spike_t *s = tv_init("RV64IMAC", rv_ram_size, 0); - tv_get_dts(s, NULL, &dts_len); - if (dts_len > 0) { - unsigned char *dts = (unsigned char *)malloc(dts_len + 1); - dts[dts_len] = '\0'; - tv_get_dts(s, dts, &dts_len); - fprintf(stdout, "%s\n", dts); - } -#else - fprintf(stdout, "Spike linkage is currently needed to generate DTS.\n"); -#endif - exit(0); -} - -static void read_dtb(const char *path) -{ - int fd = open(path, O_RDONLY); - if (fd < 0) { - fprintf(stderr, "Unable to read DTB file %s: %s\n", path, strerror(errno)); - exit(1); - } - struct stat st; - if (fstat(fd, &st) < 0) { - fprintf(stderr, "Unable to stat DTB file %s: %s\n", path, strerror(errno)); - exit(1); - } - char *m = (char *)mmap(NULL, st.st_size, PROT_READ, MAP_PRIVATE, fd, 0); - if (m == MAP_FAILED) { - fprintf(stderr, "Unable to map DTB file %s: %s\n", path, strerror(errno)); - exit(1); - } - dtb = (unsigned char *)malloc(st.st_size); - if (dtb == NULL) { - fprintf(stderr, "Cannot allocate DTB from file %s!\n", path); - exit(1); - } - memcpy(dtb, m, st.st_size); - dtb_len = st.st_size; - munmap(m, st.st_size); - close(fd); - - fprintf(stdout, "Read %ld bytes of DTB from %s.\n", dtb_len, path); -} - -char *process_args(int argc, char **argv) -{ - int c, idx = 1; - uint64_t ram_size = 0; - while(true) { - c = getopt_long(argc, argv, "dmCsz:b:t:v:hr:", options, &idx); - if (c == -1) break; - switch (c) { - case 'd': - fprintf(stderr, "enabling dirty update.\n"); - rv_enable_dirty_update = true; - break; - case 'm': - fprintf(stderr, "enabling misaligned access.\n"); - rv_enable_misaligned = true; - break; - case 'C': - disable_compressed = true; - break; - case 'i': - rv_mtval_has_illegal_inst_bits = true; - case 's': - do_dump_dts = true; - break; - case 'z': - ram_size = atol(optarg); - if (ram_size) { - fprintf(stderr, "setting ram-size to %ld MB\n", ram_size); - rv_ram_size = ram_size << 20; - } - break; - case 'b': - dtb_file = strdup(optarg); - break; - case 't': - term_log = strdup(optarg); - break; - case 'h': - print_usage(argv[0], 0); - break; -#ifdef RVFI_DII - case 'r': - rvfi_dii = true; - rvfi_dii_port = atoi(optarg); - break; -#endif - default: - fprintf(stderr, "Unrecognized optchar %c\n", c); - print_usage(argv[0], 1); - } - } - if (do_dump_dts) dump_dts(); -#ifdef RVFI_DII - if (idx > argc || (idx == argc && !rvfi_dii)) print_usage(argv[0], 0); -#else - if (idx >= argc) print_usage(argv[0], 0); -#endif - if (term_log == NULL) term_log = strdup("term.log"); - if (dtb_file) read_dtb(dtb_file); - -#ifdef RVFI_DII - if (!rvfi_dii) -#endif - fprintf(stdout, "Running file %s.\n", argv[optind]); - return argv[optind]; -} - -uint64_t load_sail(char *f) -{ - bool is32bit; - uint64_t entry; - load_elf(f, &is32bit, &entry); - if (is32bit) { - fprintf(stderr, "32-bit RISC-V not yet supported.\n"); - exit(1); - } - fprintf(stdout, "ELF Entry @ %lx\n", entry); - /* locate htif ports */ - if (lookup_sym(f, "tohost", &rv_htif_tohost) < 0) { - fprintf(stderr, "Unable to locate htif tohost port.\n"); - exit(1); - } - fprintf(stderr, "tohost located at %0" PRIx64 "\n", rv_htif_tohost); - return entry; -} - -void init_spike(const char *f, uint64_t entry, uint64_t ram_size) -{ -#ifdef ENABLE_SPIKE - bool mismatch = false; - s = tv_init("RV64IMAC", ram_size, 1); - if (tv_is_dirty_enabled(s) != rv_enable_dirty_update) { - mismatch = true; - fprintf(stderr, "inconsistent enable-dirty-update setting: spike %s, sail %s\n", - tv_is_dirty_enabled(s) ? "on" : "off", - rv_enable_dirty_update ? "on" : "off"); - } - if (tv_is_misaligned_enabled(s) != rv_enable_misaligned) { - mismatch = true; - fprintf(stderr, "inconsistent enable-misaligned-access setting: spike %s, sail %s\n", - tv_is_misaligned_enabled(s) ? "on" : "off", - rv_enable_misaligned ? "on" : "off"); - } - if (tv_ram_size(s) != rv_ram_size) { - mismatch = true; - fprintf(stderr, "inconsistent ram-size setting: spike %lx, sail %lx\n", - tv_ram_size(s), rv_ram_size); - } - if (mismatch) exit(1); - - /* The initialization order below matters. */ - tv_set_verbose(s, 1); - tv_set_dtb_in_rom(s, 1); - tv_load_elf(s, f); - tv_reset(s); - - /* sync the insns per tick */ - rv_insns_per_tick = tv_get_insns_per_tick(s); - - /* get DTB from spike */ - tv_get_dtb(s, NULL, &spike_dtb_len); - if (spike_dtb_len > 0) { - spike_dtb = (unsigned char *)malloc(spike_dtb_len + 1); - spike_dtb[spike_dtb_len] = '\0'; - if (!tv_get_dtb(s, spike_dtb, &spike_dtb_len)) { - fprintf(stderr, "Got %ld bytes of dtb at %p\n", spike_dtb_len, spike_dtb); - } else { - fprintf(stderr, "Error getting DTB from Spike.\n"); - exit(1); - } - } else { - fprintf(stderr, "No DTB available from Spike.\n"); - } -#else - s = NULL; -#endif -} - -void tick_spike() -{ -#ifdef ENABLE_SPIKE - tv_tick_clock(s); - tv_step_io(s); -#endif -} - -void init_sail_reset_vector(uint64_t entry) -{ -#define RST_VEC_SIZE 8 - uint32_t reset_vec[RST_VEC_SIZE] = { - 0x297, // auipc t0,0x0 - 0x28593 + (RST_VEC_SIZE * 4 << 20), // addi a1, t0, &dtb - 0xf1402573, // csrr a0, mhartid - SAIL_XLEN == 32 ? - 0x0182a283u : // lw t0,24(t0) - 0x0182b283u, // ld t0,24(t0) - 0x28067, // jr t0 - 0, - (uint32_t) (entry & 0xffffffff), - (uint32_t) (entry >> 32) - }; - - rv_rom_base = DEFAULT_RSTVEC; - uint64_t addr = rv_rom_base; - for (int i = 0; i < sizeof(reset_vec); i++) - write_mem(addr++, (uint64_t)((char *)reset_vec)[i]); - - if (dtb && dtb_len) { - for (size_t i = 0; i < dtb_len; i++) - write_mem(addr++, dtb[i]); - } - -#ifdef ENABLE_SPIKE - if (dtb && dtb_len) { - // Ensure that Spike's DTB matches the one provided. - bool matched = dtb_len == spike_dtb_len; - if (matched) { - for (size_t i = 0; i < dtb_len; i++) - matched = matched && (dtb[i] == spike_dtb[i]); - } - if (!matched) { - fprintf(stderr, "Provided DTB does not match Spike's!\n"); - exit(1); - } - } else { - if (spike_dtb_len > 0) { - // Use the DTB from Spike. - for (size_t i = 0; i < spike_dtb_len; i++) - write_mem(addr++, spike_dtb[i]); - } else { - fprintf(stderr, "Running without rom device tree.\n"); - } - } -#endif - - /* zero-fill to page boundary */ - const int align = 0x1000; - uint64_t rom_end = (addr + align -1)/align * align; - for (int i = addr; i < rom_end; i++) - write_mem(addr++, 0); - - /* set rom size */ - rv_rom_size = rom_end - rv_rom_base; - /* boot at reset vector */ - zPC = rv_rom_base; -} - -void init_sail(uint64_t elf_entry) -{ - model_init(); - zinit_platform(UNIT); - zinit_sys(UNIT); -#ifdef RVFI_DII - if (rvfi_dii) { - rv_ram_base = UINT64_C(0x80000000); - rv_ram_size = UINT64_C(0x10000); - rv_rom_base = UINT64_C(0); - rv_rom_size = UINT64_C(0); - zPC = elf_entry; - } else -#endif - init_sail_reset_vector(elf_entry); - if (disable_compressed) - z_set_Misa_C(&zmisa, 0); -} - -int init_check(struct tv_spike_t *s) -{ - int passed = 1; -#ifdef ENABLE_SPIKE - passed &= tv_check_csr(s, CSR_MISA, zmisa.zMisa_chunk_0); -#endif - return passed; -} - -void finish(int ec) -{ - model_fini(); -#ifdef ENABLE_SPIKE - tv_free(s); -#endif - exit(ec); -} - -int compare_states(struct tv_spike_t *s) -{ - int passed = 1; - -#ifdef ENABLE_SPIKE -#define TV_CHECK(reg, spike_reg, sail_reg) \ - passed &= tv_check_ ## reg(s, spike_reg, sail_reg); - - // fix default C enum map for cur_privilege - uint8_t priv = (zcur_privilege == 2) ? 3 : zcur_privilege; - passed &= tv_check_priv(s, priv); - - passed &= tv_check_pc(s, zPC); - - TV_CHECK(gpr, 1, zx1); - TV_CHECK(gpr, 2, zx2); - TV_CHECK(gpr, 3, zx3); - TV_CHECK(gpr, 4, zx4); - TV_CHECK(gpr, 5, zx5); - TV_CHECK(gpr, 6, zx6); - TV_CHECK(gpr, 7, zx7); - TV_CHECK(gpr, 8, zx8); - TV_CHECK(gpr, 9, zx9); - TV_CHECK(gpr, 10, zx10); - TV_CHECK(gpr, 11, zx11); - TV_CHECK(gpr, 12, zx12); - TV_CHECK(gpr, 13, zx13); - TV_CHECK(gpr, 14, zx14); - TV_CHECK(gpr, 15, zx15); - TV_CHECK(gpr, 15, zx15); - TV_CHECK(gpr, 16, zx16); - TV_CHECK(gpr, 17, zx17); - TV_CHECK(gpr, 18, zx18); - TV_CHECK(gpr, 19, zx19); - TV_CHECK(gpr, 20, zx20); - TV_CHECK(gpr, 21, zx21); - TV_CHECK(gpr, 22, zx22); - TV_CHECK(gpr, 23, zx23); - TV_CHECK(gpr, 24, zx24); - TV_CHECK(gpr, 25, zx25); - TV_CHECK(gpr, 25, zx25); - TV_CHECK(gpr, 26, zx26); - TV_CHECK(gpr, 27, zx27); - TV_CHECK(gpr, 28, zx28); - TV_CHECK(gpr, 29, zx29); - TV_CHECK(gpr, 30, zx30); - TV_CHECK(gpr, 31, zx31); - - /* some selected CSRs for now */ - - TV_CHECK(csr, CSR_MCAUSE, zmcause.zMcause_chunk_0); - TV_CHECK(csr, CSR_MEPC, zmepc); - TV_CHECK(csr, CSR_MTVAL, zmtval); - TV_CHECK(csr, CSR_MSTATUS, zmstatus); - - TV_CHECK(csr, CSR_SCAUSE, zscause.zMcause_chunk_0); - TV_CHECK(csr, CSR_SEPC, zsepc); - TV_CHECK(csr, CSR_STVAL, zstval); - -#undef TV_CHECK -#endif - - return passed; -} - -void flush_logs(void) -{ - fprintf(stderr, "\n"); - fflush(stderr); - fprintf(stdout, "\n"); - fflush(stdout); -} - -#ifdef RVFI_DII -void rvfi_send_trace(void) { - sail_bits packet; - CREATE(lbits)(&packet); - zrvfi_get_exec_packet(&packet, UNIT); - if (packet.len % 8 != 0) { - fprintf(stderr, "RVFI-DII trace packet not byte aligned: %d\n", (int)packet.len); - exit(1); - } - unsigned char bytes[packet.len / 8]; - /* mpz_export might not write all of the null bytes */ - memset(bytes, 0, sizeof(bytes)); - mpz_export(bytes, NULL, -1, 1, 0, 0, *(packet.bits)); - if (write(rvfi_dii_sock, bytes, packet.len / 8) == -1) { - fprintf(stderr, "Writing RVFI DII trace failed: %s", strerror(errno)); - exit(1); - } -} -#endif - -void run_sail(void) -{ - bool spike_done; - bool stepped; - bool diverged = false; - - /* initialize the step number */ - mach_int step_no = 0; - int insn_cnt = 0; -#ifdef RVFI_DII - bool need_instr = true; -#endif - - while (!zhtif_done) { -#ifdef RVFI_DII - if (rvfi_dii) { - if (need_instr) { - mach_bits instr_bits; - if (read(rvfi_dii_sock, &instr_bits, sizeof(instr_bits)) == -1) { - fprintf(stderr, "Reading RVFI DII command failed: %s", strerror(errno)); - exit(1); - } - zrvfi_set_instr_packet(instr_bits); - zrvfi_zzero_exec_packet(UNIT); - mach_bits cmd = zrvfi_get_cmd(UNIT); - switch (cmd) { - case 0: /* EndOfTrace */ - zrvfi_halt_exec_packet(UNIT); - rvfi_send_trace(); - return; - case 1: /* Instruction */ - break; - default: - fprintf(stderr, "Unknown RVFI-DII command: %d\n", (int)cmd); - exit(1); - } - } - sail_int sail_step; - CREATE(sail_int)(&sail_step); - CONVERT_OF(sail_int, mach_int)(&sail_step, step_no); - stepped = zrvfi_step(sail_step); - if (have_exception) goto step_exception; - flush_logs(); - if (stepped) { - need_instr = true; - rvfi_send_trace(); - } else - need_instr = false; - } else -#endif - { /* run a Sail step */ - sail_int sail_step; - CREATE(sail_int)(&sail_step); - CONVERT_OF(sail_int, mach_int)(&sail_step, step_no); - stepped = zstep(sail_step); - if (have_exception) goto step_exception; - flush_logs(); - KILL(sail_int)(&sail_step); - } - if (stepped) { - step_no++; - insn_cnt++; - } - -#ifdef ENABLE_SPIKE - { /* run a Spike step */ - tv_step(s); - spike_done = tv_is_done(s); - flush_logs(); - } - - if (zhtif_done) { - if (!spike_done) { - fprintf(stdout, "Sail done (exit-code %ld), but not Spike!\n", zhtif_exit_code); - exit(1); - } - } else { - if (spike_done) { - fprintf(stdout, "Spike done, but not Sail!\n"); - exit(1); - } - } - if (!compare_states(s)) { - diverged = true; - break; - } -#endif - if (zhtif_done) { - /* check exit code */ - if (zhtif_exit_code == 0) - fprintf(stdout, "SUCCESS\n"); - else - fprintf(stdout, "FAILURE: %ld\n", zhtif_exit_code); - } - - if (insn_cnt == rv_insns_per_tick) { - insn_cnt = 0; - ztick_clock(UNIT); - ztick_platform(UNIT); - - tick_spike(); - } - } - - dump_state: - if (diverged) { - /* TODO */ - } - finish(diverged); - - step_exception: - fprintf(stderr, "Sail exception!"); - goto dump_state; -} - -void init_logs() -{ -#ifdef ENABLE_SPIKE - // The Spike interface uses stdout for terminal output, and stderr for logs. - // Do the same here. - if (dup2(1, 2) < 0) { - fprintf(stderr, "Unable to dup 1 -> 2: %s\n", strerror(errno)); - exit(1); - } -#endif - - if ((term_fd = open(term_log, O_WRONLY|O_CREAT|O_TRUNC, S_IRUSR|S_IRGRP|S_IROTH|S_IWUSR)) < 0) { - fprintf(stderr, "Cannot create terminal log '%s': %s\n", term_log, strerror(errno)); - exit(1); - } -} - -int main(int argc, char **argv) -{ - char *file = process_args(argc, argv); - init_logs(); - -#ifdef RVFI_DII - uint64_t entry; - if (rvfi_dii) { - entry = 0x80000000; - int listen_sock = socket(AF_INET, SOCK_STREAM, 0); - if (listen_sock == -1) { - fprintf(stderr, "Unable to create socket: %s", strerror(errno)); - return 1; - } - int opt = 1; - if (setsockopt(listen_sock, SOL_SOCKET, SO_REUSEADDR, &opt, sizeof(opt)) == -1) { - fprintf(stderr, "Unable to set reuseaddr on socket: %s", strerror(errno)); - return 1; - } - struct sockaddr_in addr = { - .sin_family = AF_INET, - .sin_addr.s_addr = INADDR_ANY, - .sin_port = htons(rvfi_dii_port) - }; - if (bind(listen_sock, (struct sockaddr *)&addr, sizeof(addr)) == -1) { - fprintf(stderr, "Unable to set bind socket: %s", strerror(errno)); - return 1; - } - if (listen(listen_sock, 1) == -1) { - fprintf(stderr, "Unable to listen on socket: %s", strerror(errno)); - return 1; - } - printf("Waiting for connection\n"); - rvfi_dii_sock = accept(listen_sock, NULL, NULL); - if (rvfi_dii_sock == -1) { - fprintf(stderr, "Unable to accept connection on socket: %s", strerror(errno)); - return 1; - } - close(listen_sock); - printf("Connected\n"); - } else - entry = load_sail(file); -#else - uint64_t entry = load_sail(file); -#endif - - /* initialize spike before sail so that we can access the device-tree blob, - * until we roll our own. - */ - init_spike(file, entry, rv_ram_size); - init_sail(entry); - - if (!init_check(s)) finish(1); - - do { - run_sail(); -#ifndef RVFI_DII - } while (0); -#else - if (rvfi_dii) { - /* Reset for next test; currently we only quit when the connection breaks - and we crash due to SIGPIPE. */ - model_fini(); - init_sail(entry); - } - } while (rvfi_dii); -#endif - flush_logs(); -} diff --git a/riscv/riscv_step.sail b/riscv/riscv_step.sail deleted file mode 100644 index 755420d9..00000000 --- a/riscv/riscv_step.sail +++ /dev/null @@ -1,125 +0,0 @@ -/* The emulator fetch-execute-interrupt dispatch loop. */ - -union FetchResult = { - F_Base : word, /* Base ISA */ - F_RVC : half, /* Compressed ISA */ - F_Error : (ExceptionType, xlenbits) /* exception and PC */ -} - -function isRVC(h : half) -> bool = - ~ (h[1 .. 0] == 0b11) - -val fetch : unit -> FetchResult effect {escape, rmem, rreg, wmv, wreg} -function fetch() -> FetchResult = - /* check for legal PC */ - if (PC[0] != 0b0 | (PC[1] != 0b0 & (~ (haveRVC())))) - then F_Error(E_Fetch_Addr_Align, PC) - else match translateAddr(PC, Execute, Instruction) { - TR_Failure(e) => F_Error(e, PC), - TR_Address(ppclo) => { - /* split instruction fetch into 16-bit granules to handle RVC, as - * well as to generate precise fault addresses in any fetch - * exceptions. - */ - match checked_mem_read(Instruction, ppclo, 2, false, false, false) { - MemException(e) => F_Error(E_Fetch_Access_Fault, PC), - MemValue(ilo) => { - if isRVC(ilo) then F_RVC(ilo) - else { - PChi : xlenbits = PC + 2; - match translateAddr(PChi, Execute, Instruction) { - TR_Failure(e) => F_Error(e, PChi), - TR_Address(ppchi) => { - match checked_mem_read(Instruction, ppchi, 2, false, false, false) { - MemException(e) => F_Error(E_Fetch_Access_Fault, PChi), - MemValue(ihi) => F_Base(append(ihi, ilo)) - } - } - } - } - } - } - } - } - -/* returns whether to increment the step count in the trace */ -val step : int -> bool effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg} -function step(step_no) = { - minstret_written = false; /* see note for minstret */ - let (retired, stepped) : (bool, bool) = - match curInterrupt(cur_privilege, mip, mie, mideleg) { - Some(intr, priv) => { - print_bits("Handling interrupt: ", intr); - handle_interrupt(intr, priv); - (false, false) - }, - None() => { - match fetch() { - F_Error(e, addr) => { - handle_mem_exception(addr, e); - (false, false) - }, - F_RVC(h) => { - match decodeCompressed(h) { - None() => { - print_instr("[" ^ string_of_int(step_no) ^ "] [" ^ cur_privilege ^ "]: " ^ BitStr(PC) ^ " (" ^ BitStr(h) ^ ") "); - instbits = EXTZ(h); - handle_illegal(); - (false, true) - }, - Some(ast) => { - print_instr("[" ^ string_of_int(step_no) ^ "] [" ^ cur_privilege ^ "]: " ^ BitStr(PC) ^ " (" ^ BitStr(h) ^ ") " ^ ast); - nextPC = PC + 2; - (execute(ast), true) - } - } - }, - F_Base(w) => { - match decode(w) { - None() => { - print_instr("[" ^ string_of_int(step_no) ^ "] [" ^ cur_privilege ^ "]: " ^ BitStr(PC) ^ " (" ^ BitStr(w) ^ ") "); - instbits = EXTZ(w); - handle_illegal(); - (false, true) - }, - Some(ast) => { - print_instr("[" ^ string_of_int(step_no) ^ "] [" ^ cur_privilege ^ "]: " ^ BitStr(PC) ^ " (" ^ BitStr(w) ^ ") " ^ ast); - nextPC = PC + 4; - (execute(ast), true) - } - } - } - } - } - }; - PC = nextPC; - if retired then retire_instruction(); - stepped -} - -val loop : unit -> unit effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg} -function loop () = { - let insns_per_tick = plat_insns_per_tick(); - i : int = 0; - step_no : int = 0; - while (~ (htif_done)) do { - let stepped = step(step_no); - if stepped then step_no = step_no + 1; - - /* check htif exit */ - if htif_done then { - let exit_val = unsigned(htif_exit_code); - if exit_val == 0 then print("SUCCESS") - else print_int("FAILURE: ", exit_val); - } else { - /* update time */ - i = i + 1; - if i == insns_per_tick then { - tick_clock(); - /* for now, we drive the platform i/o at every clock tick. */ - tick_platform(); - i = 0; - } - } - } -} diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail deleted file mode 100644 index 58609949..00000000 --- a/riscv/riscv_sys.sail +++ /dev/null @@ -1,1044 +0,0 @@ -/* Machine-mode and supervisor-mode state definitions and operations. */ - -/* privilege level */ - -register cur_privilege : Privilege - -/* current instruction bits, used for illegal instruction exceptions */ - -register cur_inst : xlenbits - -/* State projections - * - * Some machine state is processed via projections from machine-mode views to - * views from lower privilege levels. So, for e.g. when mstatus is read from - * lower privilege levels, we use 'lowering_' projections: - * - * mstatus -> sstatus -> ustatus - * - * Similarly, when machine state is written from lower privileges, that state is - * lifted into the appropriate value for the machine-mode state. - * - * ustatus -> sstatus -> mstatus - * - * In addition, several fields in machine state registers are WARL or WLRL, - * requiring that values written to the registers be legalized. For each such - * register, there will be an associated 'legalize_' function. These functions - * will need to be supplied externally, and will depend on the legal values - * supported by a platform/implementation (or misa). The legalize_ functions - * generate a legal value from the current value and the written value. In more - * complex cases, they will also implicitly read the current values of misa, - * mstatus, etc. - * - * Each register definition below is followed by custom projections - * and choice of legalizations if needed. For now, we typically - * implement the simplest legalize_ alternatives. - */ - - -/* M-mode registers */ - -bitfield Misa : bits(64) = { - MXL : 63 .. 62, - - Z : 25, - Y : 24, - X : 23, - W : 22, - V : 21, - U : 20, - T : 19, - S : 18, - R : 17, - Q : 16, - P : 15, - O : 14, - N : 13, - M : 12, - L : 11, - K : 10, - J : 9, - I : 8, - H : 7, - G : 6, - F : 5, - E : 4, - D : 3, - C : 2, - B : 1, - A : 0 -} -register misa : Misa - -function legalize_misa(m : Misa, v : xlenbits) -> Misa = { - /* Allow modifications to C. */ - let v = Mk_Misa(v); - // Suppress changing C if nextPC would become misaligned. - if v.C() == false & nextPC[1] == true - then m - else update_C(m, v.C()) -} - -bitfield Mstatus : bits(64) = { - SD : 63, - - SXL : 35 .. 34, - UXL : 33 .. 32, - - TSR : 22, - TW : 21, - TVM : 20, - MXR : 19, - SUM : 18, - MPRV : 17, - - XS : 16 .. 15, - FS : 14 .. 13, - - MPP : 12 .. 11, - SPP : 8, - - MPIE : 7, - SPIE : 5, - UPIE : 4, - - MIE : 3, - SIE : 1, - UIE : 0 -} -register mstatus : Mstatus - -function legalize_mstatus(o : Mstatus, v : xlenbits) -> Mstatus = { - let m : Mstatus = Mk_Mstatus(v); - - /* We don't have any extension context yet. */ - let m = update_XS(m, extStatus_to_bits(Off)); - let m = update_FS(m, extStatus_to_bits(Off)); - - let m = update_SD(m, extStatus_of_bits(m.FS()) == Dirty - | extStatus_of_bits(m.XS()) == Dirty); - - /* For now, we don't allow SXL and UXL to be changed, for Spike compatibility. */ - let m = update_SXL(m, o.SXL()); - let m = update_UXL(m, o.UXL()); - - /* Hardwired to zero in the absence of 'N'. */ - let m = update_UPIE(m, false); - let m = update_UIE(m, false); - m -} - -/* architecture and extension checks */ - -function cur_Architecture() -> Architecture = { - let a : arch_xlen = - match (cur_privilege) { - Machine => misa.MXL(), - Supervisor => mstatus.SXL(), - User => mstatus.UXL() - }; - match architecture(a) { - Some(a) => a, - None() => internal_error("Invalid current architecture") - } -} - -function in32BitMode() -> bool = { - cur_Architecture() == RV32 -} - -function haveAtomics() -> bool = { misa.A() == true } -function haveRVC() -> bool = { misa.C() == true } -function haveMulDiv() -> bool = { misa.M() == true } -function haveFP() -> bool = { misa.F() == true | misa.D() == true } - -/* interrupt processing state */ - -bitfield Minterrupts : bits(64) = { - MEI : 11, /* external interrupts */ - SEI : 9, - UEI : 8, - - MTI : 7, /* timers interrupts */ - STI : 5, - UTI : 4, - - MSI : 3, /* software interrupts */ - SSI : 1, - USI : 0, -} -register mip : Minterrupts /* Pending */ -register mie : Minterrupts /* Enabled */ -register mideleg : Minterrupts /* Delegation to S-mode */ - -function legalize_mip(o : Minterrupts, v : xlenbits) -> Minterrupts = { - /* The only writable bits are the S-mode bits, and with the 'N' - * extension, the U-mode bits. */ - let v = Mk_Minterrupts(v); - let m = update_SEI(o, v.SEI()); - let m = update_STI(m, v.STI()); - let m = update_SSI(m, v.SSI()); - m -} - -function legalize_mie(o : Minterrupts, v : xlenbits) -> Minterrupts = { - let v = Mk_Minterrupts(v); - let m = update_MEI(o, v.MEI()); - let m = update_MTI(m, v.MTI()); - let m = update_MSI(m, v.MSI()); - let m = update_SEI(m, v.SEI()); - let m = update_STI(m, v.STI()); - let m = update_SSI(m, v.SSI()); - /* The U-mode bits will be modified if we have the 'N' extension. */ - m -} - -function legalize_mideleg(o : Minterrupts, v : xlenbits) -> Minterrupts = { - /* M-mode interrupt delegation bits "should" be hardwired to 0. */ - /* FIXME: needs verification against eventual spec language. */ - let m = Mk_Minterrupts(v); - let m = update_MEI(m, false); - let m = update_MTI(m, false); - let m = update_MSI(m, false); - m -} - -/* exception processing state */ - -bitfield Medeleg : bits(64) = { - SAMO_Page_Fault : 15, - Load_Page_Fault : 13, - Fetch_Page_Fault : 12, - MEnvCall : 10, - SEnvCall : 9, - UEnvCall : 8, - SAMO_Access_Fault : 7, - SAMO_Addr_Align : 6, - Load_Access_Fault : 5, - Load_Addr_Align : 4, - Breakpoint : 3, - Illegal_Instr : 2, - Fetch_Access_Fault: 1, - Fetch_Addr_Align : 0 -} -register medeleg : Medeleg /* Delegation to S-mode */ - -function legalize_medeleg(o : Medeleg, v : xlenbits) -> Medeleg = { - let m = Mk_Medeleg(v); - /* M-EnvCalls delegation is not supported */ - let m = update_MEnvCall(m, false); - m -} - -/* registers for trap handling */ - -bitfield Mtvec : bits(64) = { - Base : 63 .. 2, - Mode : 1 .. 0 -} -register mtvec : Mtvec /* Trap Vector */ - -function legalize_tvec(o : Mtvec, v : xlenbits) -> Mtvec = { - let v = Mk_Mtvec(v); - match (trapVectorMode_of_bits(v.Mode())) { - TV_Direct => v, - TV_Vector => v, - _ => update_Mode(v, o.Mode()) - } -} - -bitfield Mcause : bits(64) = { - IsInterrupt : 63, - Cause : 62 .. 0 -} -register mcause : Mcause - -/* Interpreting the trap-vector address */ -function tvec_addr(m : Mtvec, c : Mcause) -> option(xlenbits) = { - let base : xlenbits = m.Base() @ 0b00; - match (trapVectorMode_of_bits(m.Mode())) { - TV_Direct => Some(base), - TV_Vector => if c.IsInterrupt() == true - then Some(base + (EXTZ(c.Cause()) << 0b10)) - else Some(base), - TV_Reserved => None() - } -} - -/* Exception PC */ - -register mepc : xlenbits - -// legalizing writes to xepc -function legalize_xepc(v : xlenbits) -> xlenbits = { - v & EXTS(if haveRVC() then 0b110 else 0b100) -} - -// masking for reads to xepc -function pc_alignment_mask() -> xlenbits = - ~(EXTZ(if misa.C() == true then 0b00 else 0b10)) - -/* auxiliary exception registers */ - -register mtval : xlenbits -register mscratch : xlenbits - -/* counters */ - -bitfield Counteren : bits(32) = { - HPM : 31 .. 3, - IR : 2, - TM : 1, - CY : 0 -} - -register mcounteren : Counteren -register scounteren : Counteren - -function legalize_mcounteren(c : Counteren, v : xlenbits) -> Counteren = { - /* no HPM counters yet */ - let c = update_IR(c, v[2]); - let c = update_TM(c, v[1]); - let c = update_CY(c, v[0]); - c -} - -function legalize_scounteren(c : Counteren, v : xlenbits) -> Counteren = { - /* no HPM counters yet */ - let c = update_IR(c, v[2]); - let c = update_TM(c, v[1]); - let c = update_CY(c, v[0]); - c -} - -register mcycle : xlenbits -register mtime : xlenbits - -/* minstret - * - * minstret is an architectural register, and can be written to. The - * spec says that minstret increments on instruction retires need to - * occur before any explicit writes to instret. However, in our - * simulation loop, we need to execute an instruction to find out - * whether it retired, and hence can only increment instret after - * execution. To avoid doing this in the case minstret was explicitly - * written to, we track writes to it in a separate model-internal - * register. - */ -register minstret : xlenbits -register minstret_written : bool - -function retire_instruction() -> unit = { - if minstret_written == true - then minstret_written = false - else minstret = minstret + 1 -} - -/* informational registers */ -register mvendorid : xlenbits -register mimpid : xlenbits -register marchid : xlenbits -/* TODO: this should be readonly, and always 0 for now */ -register mhartid : xlenbits - -/* physical memory protection configuration */ -register pmpaddr0 : xlenbits -register pmpcfg0 : xlenbits - - -/* S-mode registers */ - -/* sstatus reveals a subset of mstatus */ -bitfield Sstatus : bits(64) = { - SD : 63, - UXL : 33 .. 32, - MXR : 19, - SUM : 18, - XS : 16 .. 15, - FS : 14 .. 13, - SPP : 8, - SPIE : 5, - UPIE : 4, - SIE : 1, - UIE : 0 -} -/* This is a view, so there is no register defined. */ -function lower_mstatus(m : Mstatus) -> Sstatus = { - let s = Mk_Sstatus(EXTZ(0b0)); - let s = update_SD(s, m.SD()); - let s = update_UXL(s, m.UXL()); - let s = update_MXR(s, m.MXR()); - let s = update_SUM(s, m.SUM()); - let s = update_XS(s, m.XS()); - let s = update_FS(s, m.FS()); - let s = update_SPP(s, m.SPP()); - let s = update_SPIE(s, m.SPIE()); - let s = update_UPIE(s, m.UPIE()); - let s = update_SIE(s, m.SIE()); - let s = update_UIE(s, m.UIE()); - s -} - -function lift_sstatus(m : Mstatus, s : Sstatus) -> Mstatus = { - // FIXME: This should be parameterized by a platform setting. For now, match spike. - // let m = update_UXL(m, s.UXL()); - let m = update_MXR(m, s.MXR()); - let m = update_SUM(m, s.SUM()); - - // FIXME: Should XS and FS check whether X and F|D are supported in misa? - let m = update_XS(m, s.XS()); - let m = update_FS(m, s.FS()); - let m = update_SD(m, extStatus_of_bits(m.FS()) == Dirty - | extStatus_of_bits(m.XS()) == Dirty); - - let m = update_SPP(m, s.SPP()); - let m = update_SPIE(m, s.SPIE()); - let m = update_UPIE(m, s.UPIE()); - let m = update_SIE(m, s.SIE()); - let m = update_UIE(m, s.UIE()); - m -} - -function legalize_sstatus(m : Mstatus, v : xlenbits) -> Mstatus = { - lift_sstatus(m, Mk_Sstatus(v)) -} - -bitfield Sedeleg : bits(64) = { - UEnvCall : 8, - SAMO_Access_Fault : 7, - SAMO_Addr_Align : 6, - Load_Access_Fault : 5, - Load_Addr_Align : 4, - Breakpoint : 3, - Illegal_Instr : 2, - Fetch_Access_Fault: 1, - Fetch_Addr_Align : 0 -} -register sedeleg : Sedeleg - -function legalize_sedeleg(s : Sedeleg, v : xlenbits) -> Sedeleg = { - Mk_Sedeleg(EXTZ(v[8..0])) -} - -bitfield Sinterrupts : bits(64) = { - SEI : 9, /* external interrupts */ - UEI : 8, - - STI : 5, /* timers interrupts */ - UTI : 4, - - SSI : 1, /* software interrupts */ - USI : 0 -} - -/* Provides the sip read view of mip as delegated by mideleg. */ -function lower_mip(m : Minterrupts, d : Minterrupts) -> Sinterrupts = { - let s : Sinterrupts = Mk_Sinterrupts(EXTZ(0b0)); - let s = update_SEI(s, m.SEI() & d.SEI()); - let s = update_STI(s, m.STI() & d.STI()); - let s = update_SSI(s, m.SSI() & d.SSI()); - - let s = update_UEI(s, m.UEI() & d.UEI()); - let s = update_UTI(s, m.UTI() & d.UTI()); - let s = update_USI(s, m.USI() & d.USI()); - s -} -/* Provides the sie read view of mie as delegated by mideleg. */ -function lower_mie(m : Minterrupts, d : Minterrupts) -> Sinterrupts = { - let s : Sinterrupts = Mk_Sinterrupts(EXTZ(0b0)); - let s = update_SEI(s, m.SEI() & d.SEI()); - let s = update_STI(s, m.STI() & d.STI()); - let s = update_SSI(s, m.SSI() & d.SSI()); - let s = update_UEI(s, m.UEI() & d.UEI()); - let s = update_UTI(s, m.UTI() & d.UTI()); - let s = update_USI(s, m.USI() & d.USI()); - s -} -/* Provides the sip write view of mip as delegated by mideleg. */ -function lift_sip(o : Minterrupts, d : Minterrupts, s : Sinterrupts) -> Minterrupts = { - let m : Minterrupts = o; - let m = update_SSI(m, s.SSI() & d.SSI()); - let m = update_UEI(m, m.UEI() & d.UEI()); - let m = update_USI(m, m.USI() & d.USI()); - m -} -function legalize_sip(m : Minterrupts, d : Minterrupts, v : xlenbits) -> Minterrupts = { - lift_sip(m, d, Mk_Sinterrupts(v)) -} -/* Provides the sie write view of mie as delegated by mideleg. */ -function lift_sie(o : Minterrupts, d : Minterrupts, s : Sinterrupts) -> Minterrupts = { - let m : Minterrupts = o; - let m = if d.SEI() == true then update_SEI(m, s.SEI()) else m; - let m = if d.STI() == true then update_STI(m, s.STI()) else m; - let m = if d.SSI() == true then update_SSI(m, s.SSI()) else m; - let m = if d.UEI() == true then update_UEI(m, s.UEI()) else m; - let m = if d.UTI() == true then update_UTI(m, s.UTI()) else m; - let m = if d.USI() == true then update_USI(m, s.USI()) else m; - m -} -function legalize_sie(m : Minterrupts, d : Minterrupts, v : xlenbits) -> Minterrupts = { - lift_sie(m, d, Mk_Sinterrupts(v)) -} - -register sideleg : Sinterrupts - -/* s-mode address translation and protection (satp) */ -bitfield Satp64 : bits(64) = { - Mode : 63 .. 60, - Asid : 59 .. 44, - PPN : 43 .. 0 -} -register satp : xlenbits - -function legalize_satp(a : Architecture, o : xlenbits, v : xlenbits) -> xlenbits = { - let s = Mk_Satp64(v); - match satpMode_of_bits(a, s.Mode()) { - None() => o, - Some(Sv32) => o, /* Sv32 is unsupported for now */ - Some(_) => s.bits() - } -} - -/* other supervisor state */ -register stvec : Mtvec -register sscratch : xlenbits -register sepc : xlenbits -register scause : Mcause -register stval : xlenbits - -/* disabled trigger/debug module */ -register tselect : xlenbits - -/* CSR names */ - -val cast csr_name : csreg -> string -function csr_name(csr) = { - match (csr) { - /* user trap setup */ - 0x000 => "ustatus", - 0x004 => "uie", - 0x005 => "utvec", - /* user floating-point context */ - 0x001 => "fflags", - 0x002 => "frm", - 0x003 => "fcsr", - /* counter/timers */ - 0xC00 => "cycle", - 0xC01 => "time", - 0xC02 => "instret", - 0xC80 => "cycleh", - 0xC81 => "timeh", - 0xC82 => "instreth", - /* TODO: other hpm counters */ - /* supervisor trap setup */ - 0x100 => "sstatus", - 0x102 => "sedeleg", - 0x103 => "sideleg", - 0x104 => "sie", - 0x105 => "stvec", - 0x106 => "scounteren", - /* supervisor trap handling */ - 0x140 => "sscratch", - 0x141 => "sepc", - 0x142 => "scause", - 0x143 => "stval", - 0x144 => "sip", - /* supervisor protection and translation */ - 0x180 => "satp", - /* machine information registers */ - 0xF11 => "mvendorid", - 0xF12 => "marchid", - 0xF13 => "mimpid", - 0xF14 => "mhartid", - /* machine trap setup */ - 0x300 => "mstatus", - 0x301 => "misa", - 0x302 => "medeleg", - 0x303 => "mideleg", - 0x304 => "mie", - 0x305 => "mtvec", - 0x306 => "mcounteren", - /* machine trap handling */ - 0x340 => "mscratch", - 0x341 => "mepc", - 0x342 => "mcause", - 0x343 => "mtval", - 0x344 => "mip", - - 0x3A0 => "pmpcfg0", - 0x3B0 => "pmpaddr0", - /* TODO: machine protection and translation */ - /* machine counters/timers */ - 0xB00 => "mcycle", - 0xB02 => "minstret", - 0xB80 => "mcycleh", - 0xB82 => "minstreth", - /* TODO: other hpm counters and events */ - /* trigger/debug */ - 0x7a0 => "tselect", - _ => "UNKNOWN" - } -} - -mapping csr_name_map : csreg <-> string = { - /* user trap setup */ - 0x000 <-> "ustatus", - 0x004 <-> "uie", - 0x005 <-> "utvec", - /* user trap handling */ - 0x040 <-> "uscratch", - 0x041 <-> "uepc", - 0x042 <-> "ucause", - 0x043 <-> "utval", - 0x044 <-> "uip", - /* user floating-point context */ - 0x001 <-> "fflags", - 0x002 <-> "frm", - 0x003 <-> "fcsr", - /* counter/timers */ - 0xC00 <-> "cycle", - 0xC01 <-> "time", - 0xC02 <-> "instret", - 0xC80 <-> "cycleh", - 0xC81 <-> "timeh", - 0xC82 <-> "instreth", - /* TODO: other hpm counters */ - /* supervisor trap setup */ - 0x100 <-> "sstatus", - 0x102 <-> "sedeleg", - 0x103 <-> "sideleg", - 0x104 <-> "sie", - 0x105 <-> "stvec", - 0x106 <-> "scounteren", - /* supervisor trap handling */ - 0x140 <-> "sscratch", - 0x141 <-> "sepc", - 0x142 <-> "scause", - 0x143 <-> "stval", - 0x144 <-> "sip", - /* supervisor protection and translation */ - 0x180 <-> "satp", - /* machine information registers */ - 0xF11 <-> "mvendorid", - 0xF12 <-> "marchid", - 0xF13 <-> "mimpid", - 0xF14 <-> "mhartid", - /* machine trap setup */ - 0x300 <-> "mstatus", - 0x301 <-> "misa", - 0x302 <-> "medeleg", - 0x303 <-> "mideleg", - 0x304 <-> "mie", - 0x305 <-> "mtvec", - 0x306 <-> "mcounteren", - /* machine trap handling */ - 0x340 <-> "mscratch", - 0x341 <-> "mepc", - 0x342 <-> "mcause", - 0x343 <-> "mtval", - 0x344 <-> "mip", - /* machine protection and translation */ - 0x3A0 <-> "pmpcfg0", - 0x3A1 <-> "pmpcfg1", - 0x3A2 <-> "pmpcfg2", - 0x3A3 <-> "pmpcfg3", - 0x3B0 <-> "pmpaddr0", - 0x3B1 <-> "pmpaddr1", - 0x3B2 <-> "pmpaddr2", - 0x3B3 <-> "pmpaddr3", - 0x3B4 <-> "pmpaddr4", - 0x3B5 <-> "pmpaddr5", - 0x3B6 <-> "pmpaddr6", - 0x3B7 <-> "pmpaddr7", - 0x3B8 <-> "pmpaddr8", - 0x3B9 <-> "pmpaddr9", - 0x3BA <-> "pmpaddr10", - 0x3BB <-> "pmpaddr11", - 0x3BC <-> "pmpaddr12", - 0x3BD <-> "pmpaddr13", - 0x3BE <-> "pmpaddr14", - 0x3BF <-> "pmpaddr15", - /* machine counters/timers */ - 0xB00 <-> "mcycle", - 0xB02 <-> "minstret", - 0xB80 <-> "mcycleh", - 0xB82 <-> "minstreth", - /* TODO: other hpm counters and events */ - /* trigger/debug */ - 0x7a0 <-> "tselect", - 0x7a1 <-> "tdata1", - 0x7a2 <-> "tdata2", - 0x7a3 <-> "tdata3" - - /* numeric fallback */ - /* reg <-> hex_bits_12(reg) */ - } - - -/* CSR access control */ - -function csrAccess(csr : csreg) -> csrRW = csr[11..10] -function csrPriv(csr : csreg) -> priv_level = csr[9..8] - -function is_CSR_defined (csr : bits(12), p : Privilege) -> bool = - match (csr) { - /* machine mode: informational */ - 0xf11 => p == Machine, // mvendorid - 0xf12 => p == Machine, // marchdid - 0xf13 => p == Machine, // mimpid - 0xf14 => p == Machine, // mhartid - /* machine mode: trap setup */ - 0x300 => p == Machine, // mstatus - 0x301 => p == Machine, // misa - 0x302 => p == Machine, // medeleg - 0x303 => p == Machine, // mideleg - 0x304 => p == Machine, // mie - 0x305 => p == Machine, // mtvec - 0x306 => p == Machine, // mcounteren - /* machine mode: trap handling */ - 0x340 => p == Machine, // mscratch - 0x341 => p == Machine, // mepc - 0x342 => p == Machine, // mcause - 0x343 => p == Machine, // mtval - 0x344 => p == Machine, // mip - - 0x3A0 => p == Machine, // pmpcfg0 - 0x3B0 => false, // (Disabled for Spike compatibility) -// 0x3B0 => p == Machine, // pmpaddr0 - - /* supervisor mode: trap setup */ - 0x100 => p == Machine | p == Supervisor, // sstatus - 0x102 => p == Machine | p == Supervisor, // sedeleg - 0x103 => p == Machine | p == Supervisor, // sideleg - 0x104 => p == Machine | p == Supervisor, // sie - 0x105 => p == Machine | p == Supervisor, // stvec - 0x106 => p == Machine | p == Supervisor, // scounteren - - /* supervisor mode: trap handling */ - 0x140 => p == Machine | p == Supervisor, // sscratch - 0x141 => p == Machine | p == Supervisor, // sepc - 0x142 => p == Machine | p == Supervisor, // scause - 0x143 => p == Machine | p == Supervisor, // stval - 0x144 => p == Machine | p == Supervisor, // sip - - /* supervisor mode: address translation */ - 0x180 => p == Machine | p == Supervisor, // satp - - /* disabled trigger/debug module */ - 0x7a0 => p == Machine, - - _ => false - } - -val check_CSR_access : (csrRW, priv_level, Privilege, bool) -> bool -function check_CSR_access(csrrw, csrpr, p, isWrite) = - (~ (isWrite == true & csrrw == 0b11)) /* read/write */ - & (privLevel_to_bits(p) >=_u csrpr) /* privilege */ - -function check_TVM_SATP(csr : csreg, p : Privilege) -> bool = - ~ (csr == 0x180 & p == Supervisor & mstatus.TVM() == true) - -function check_Counteren(csr : csreg, p : Privilege) -> bool = - match(csr, p) { - (0xC00, Supervisor) => mcounteren.CY() == true, - (0xC01, Supervisor) => mcounteren.TM() == true, - (0xC02, Supervisor) => mcounteren.IR() == true, - - (0xC00, User) => scounteren.CY() == true, - (0xC01, User) => scounteren.TM() == true, - (0xC02, User) => scounteren.IR() == true, - - (_, _) => /* no HPM counters for now */ - if 0xC03 <=_u csr & csr <=_u 0xC1F - then false - else true - } - -function check_CSR(csr : csreg, p : Privilege, isWrite : bool) -> bool = - is_CSR_defined(csr, p) - & check_CSR_access(csrAccess(csr), csrPriv(csr), p, isWrite) - & check_TVM_SATP(csr, p) - & check_Counteren(csr, p) - -/* Reservation handling for LR/SC. - * - * The reservation state is maintained external to the model since the - * reservation behavior is platform-specific anyway and maintaining - * this state outside the model simplifies the concurrency analysis. - * - * These are externs are defined here in the system module since - * we currently perform reservation cancellation on privilege level - * transition. Ideally, the platform should get more visibility into - * where cancellation can be performed. - */ - -val load_reservation = {ocaml: "Platform.load_reservation", c: "load_reservation", lem: "load_reservation"} : xlenbits -> unit - -val match_reservation = {ocaml: "Platform.match_reservation", lem: "speculate_conditional_success", c: "match_reservation"} : xlenbits -> bool effect {exmem} - -val cancel_reservation = {ocaml: "Platform.cancel_reservation", c: "cancel_reservation", lem: "cancel_reservation"} : unit -> unit - -/* Exception delegation: given an exception and the privilege at which - * it occured, returns the privilege at which it should be handled. - */ -function exception_delegatee(e : ExceptionType, p : Privilege) -> Privilege = { - let idx = num_of_ExceptionType(e); - let super = medeleg.bits()[idx]; - let user = sedeleg.bits()[idx]; - let deleg = /* if misa.N() == true & user then User - else */ - if misa.S() == true & super then Supervisor - else Machine; - /* Ensure there is no transition to a less-privileged mode. */ - if privLevel_to_bits(deleg) <_u privLevel_to_bits(p) - then p else deleg -} - -/* Interrupts are prioritized in privilege order, and for each - * privilege, in the order: external, software, timers. - */ -function findPendingInterrupt(ip : xlenbits) -> option(InterruptType) = { - let ip = Mk_Minterrupts(ip); - if ip.MEI() == true then Some(I_M_External) - else if ip.MSI() == true then Some(I_M_Software) - else if ip.MTI() == true then Some(I_M_Timer) - else if ip.SEI() == true then Some(I_S_External) - else if ip.SSI() == true then Some(I_S_Software) - else if ip.STI() == true then Some(I_S_Timer) - else if ip.UEI() == true then Some(I_U_External) - else if ip.USI() == true then Some(I_U_Software) - else if ip.UTI() == true then Some(I_U_Timer) - else None() -} - -/* Examines current M-mode interrupt state and returns an interrupt to be - * handled, and the privilege it should be handled at. Interrupts are - * dispatched in order of decreasing privilege, while ensuring that the - * resulting privilege level is not reduced; i.e. delegated interrupts to - * lower privileges are effectively masked until control returns to them. - * - * For now, it assumes 'S' and no 'N' extension, which is the common case. - */ -function curInterrupt(priv : Privilege, pend : Minterrupts, enbl : Minterrupts, delg : Minterrupts) - -> option((InterruptType, Privilege)) = { - let en_mip : xlenbits = pend.bits() & enbl.bits(); - if en_mip == EXTZ(0b0) then None() /* fast path */ - else { - /* check implicit enabling when in lower privileges */ - let eff_mie = priv != Machine | (priv == Machine & mstatus.MIE() == true); - let eff_sie = priv == User | (priv == Supervisor & mstatus.SIE() == true); - /* handle delegation */ - let eff_mip = en_mip & (~ (delg.bits())); /* retained at M-mode */ - let eff_sip = en_mip & delg.bits(); /* delegated to S-mode */ - - if eff_mie & eff_mip != EXTZ(0b0) - then match findPendingInterrupt(eff_mip) { - Some(i) => let r = (i, Machine) in Some(r), - None() => { internal_error("non-zero eff_mip=" ^ BitStr(eff_mip) ^ ", but nothing pending") } - } - else if eff_sie & eff_sip != EXTZ(0b0) - then match findPendingInterrupt(eff_sip) { - Some(i) => let r = (i, Supervisor) in Some(r), - None() => { internal_error("non-zero eff_sip=" ^ BitStr(eff_sip) ^ ", but nothing pending") } - } - else { - let p = if pend.MTI() == true then "1" else "0"; - let e = if enbl.MTI() == true then "1" else "0"; - let d = if delg.MTI() == true then "1" else "0"; - print_platform(" MTI: pend=" ^ p ^ " enbl=" ^ e ^ " delg=" ^ d); - let eff_mip = en_mip & (~ (delg.bits())); /* retained at M-mode */ - let eff_sip = en_mip & delg.bits(); /* delegated to S-mode */ - print_platform("mstatus=" ^ BitStr(mstatus.bits()) - ^ " mie,sie=" ^ BitStr(mstatus.MIE()) ^ "," ^ BitStr(mstatus.SIE()) - ^ " en_mip=" ^ BitStr(en_mip) - ^ " eff_mip=" ^ BitStr(eff_mip) - ^ " eff_sip=" ^ BitStr(eff_sip)); - None() - } - } -} - -/* privilege transitions due to exceptions and interrupts */ - -struct sync_exception = { - trap : ExceptionType, - excinfo : option(xlenbits) -} - -function tval(excinfo : option(xlenbits)) -> xlenbits = { - match (excinfo) { - Some(e) => e, - None() => EXTZ(0b0) - } -} - -union ctl_result = { - CTL_TRAP : sync_exception, - CTL_SRET : unit, - CTL_MRET : unit -/* TODO: CTL_URET */ -} - -$ifdef RVFI_DII -val rvfi_trap : unit -> unit effect {wreg} -function rvfi_trap () = - rvfi_exec->rvfi_trap() = 0x01 -$else -val rvfi_trap : unit -> unit -function rvfi_trap () = () -$endif - -/* handle exceptional ctl flow by updating nextPC and operating privilege */ - -function handle_trap(del_priv : Privilege, intr : bool, c : exc_code, pc : xlenbits, info : option(xlenbits)) - -> xlenbits = { - rvfi_trap(); - print_platform("handling " ^ (if intr then "int#" else "exc#") ^ BitStr(c) ^ " at priv " ^ del_priv ^ " with tval " ^ BitStr(tval(info))); - - match (del_priv) { - Machine => { - mcause->IsInterrupt() = intr; - mcause->Cause() = EXTZ(c); - - mstatus->MPIE() = mstatus.MIE(); - mstatus->MIE() = false; - mstatus->MPP() = privLevel_to_bits(cur_privilege); - mtval = tval(info); - mepc = pc; - - cur_privilege = del_priv; - - print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(mstatus.bits()) ^ ")"); // Spike compatible log - - cancel_reservation(); - - match tvec_addr(mtvec, mcause) { - Some(epc) => epc, - None() => internal_error("Invalid mtvec mode") - } - }, - Supervisor => { - scause->IsInterrupt() = intr; - scause->Cause() = EXTZ(c); - - mstatus->SPIE() = mstatus.SIE(); - mstatus->SIE() = false; - mstatus->SPP() = match (cur_privilege) { - User => false, - Supervisor => true, - Machine => internal_error("invalid privilege for s-mode trap") - }; - stval = tval(info); - sepc = pc; - - cur_privilege = del_priv; - - print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(mstatus.bits()) ^ ")"); // Spike compatible log - - cancel_reservation(); - - match tvec_addr(stvec, scause) { - Some(epc) => epc, - None() => internal_error("Invalid stvec mode") - } - - }, - User => internal_error("the N extension is currently unsupported") - }; -} - -function handle_exception(cur_priv : Privilege, ctl : ctl_result, - pc: xlenbits) -> xlenbits = { - match (cur_priv, ctl) { - (_, CTL_TRAP(e)) => { - let del_priv = exception_delegatee(e.trap, cur_priv); - print_platform("trapping from " ^ cur_priv ^ " to " ^ del_priv - ^ " to handle " ^ e.trap); - handle_trap(del_priv, false, e.trap, pc, e.excinfo) - }, - (_, CTL_MRET()) => { - let prev_priv = cur_privilege; - mstatus->MIE() = mstatus.MPIE(); - mstatus->MPIE() = true; - cur_privilege = privLevel_of_bits(mstatus.MPP()); - mstatus->MPP() = privLevel_to_bits(User); - - print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(mstatus.bits()) ^ ")"); // Spike compatible log - print_platform("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege); - - cancel_reservation(); - mepc & pc_alignment_mask() - }, - (_, CTL_SRET()) => { - let prev_priv = cur_privilege; - mstatus->SIE() = mstatus.SPIE(); - mstatus->SPIE() = true; - cur_privilege = if mstatus.SPP() == true then Supervisor else User; - mstatus->SPP() = false; - - print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(mstatus.bits()) ^ ")"); // Spike compatible log - print_platform("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege); - - cancel_reservation(); - sepc & pc_alignment_mask() - } - } -} - -function handle_mem_exception(addr : xlenbits, e : ExceptionType) -> unit = { - let t : sync_exception = struct { trap = e, - excinfo = Some(addr) } in - nextPC = handle_exception(cur_privilege, CTL_TRAP(t), PC) -} - -function handle_interrupt(i : InterruptType, del_priv : Privilege) -> unit = - nextPC = handle_trap(del_priv, true, i, PC, None()) - -/* state state initialization */ - -function init_sys() -> unit = { - cur_privilege = Machine; - - mhartid = EXTZ(0b0); - - misa->MXL() = arch_to_bits(RV64); - misa->A() = true; /* atomics */ - misa->C() = true; /* RVC */ - misa->I() = true; /* base integer ISA */ - misa->M() = true; /* integer multiply/divide */ - misa->U() = true; /* user-mode */ - misa->S() = true; /* supervisor-mode */ - - /* 64-bit only mode with no extensions */ - mstatus->SXL() = misa.MXL(); - mstatus->UXL() = misa.MXL(); - mstatus->SD() = false; - - mip->bits() = EXTZ(0b0); - mie->bits() = EXTZ(0b0); - mideleg->bits() = EXTZ(0b0); - medeleg->bits() = EXTZ(0b0); - mtvec->bits() = EXTZ(0b0); - mcause->bits() = EXTZ(0b0); - mepc = EXTZ(0b0); - mtval = EXTZ(0b0); - mscratch = EXTZ(0b0); - - mcycle = EXTZ(0b0); - mtime = EXTZ(0b0); - - mcounteren->bits() = EXTZ(0b0); - - minstret = EXTZ(0b0); - minstret_written = false; - - // log compatibility with spike - print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(EXTZ(0b0) : xlenbits) ^ ")") -} - -/* memory access exceptions, defined here for use by the platform model. */ - -union MemoryOpResult ('a : Type) = { - MemValue : 'a, - MemException : ExceptionType -} diff --git a/riscv/riscv_types.sail b/riscv/riscv_types.sail deleted file mode 100644 index 4d012e0c..00000000 --- a/riscv/riscv_types.sail +++ /dev/null @@ -1,550 +0,0 @@ -/* Basic type and function definitions used pervasively in the model. */ - -let xlen = 64 -type xlenbits = bits(64) - -let xlen_max_unsigned = 2 ^ xlen - 1 -let xlen_max_signed = 2 ^ (xlen - 1) - 1 -let xlen_min_signed = 0 - 2 ^ (xlen - 1) - -type half = bits(16) -type word = bits(32) - -/* register identifiers */ - -type regbits = bits(5) -type cregbits = bits(3) /* identifiers in RVC instructions */ -type csreg = bits(12) /* CSR addressing */ - -/* register file indexing */ - -type regno ('n : Int), 0 <= 'n < 32 = atom('n) - -val cast regbits_to_regno : bits(5) -> {'n, 0 <= 'n < 32. regno('n)} -function regbits_to_regno b = let 'r = unsigned(b) in r - -/* mapping RVC register indices into normal indices */ -val creg2reg_bits : cregbits -> regbits -function creg2reg_bits(creg) = 0b01 @ creg - -/* some architecture and ABI relevant register identifiers */ -let zreg : regbits = 0b00000 /* x0, zero register */ -let ra : regbits = 0b00001 /* x1, return address */ -let sp : regbits = 0b00010 /* x2, stack pointer */ - -/* program counter */ - -register PC : xlenbits -register nextPC : xlenbits - -/* internal state to hold instruction bits for faulting instructions */ -register instbits : xlenbits - -/* register file and accessors */ - -register Xs : vector(32, dec, xlenbits) - -register x1 : xlenbits -register x2 : xlenbits -register x3 : xlenbits -register x4 : xlenbits -register x5 : xlenbits -register x6 : xlenbits -register x7 : xlenbits -register x8 : xlenbits -register x9 : xlenbits -register x10 : xlenbits -register x11 : xlenbits -register x12 : xlenbits -register x13 : xlenbits -register x14 : xlenbits -register x15 : xlenbits -register x16 : xlenbits -register x17 : xlenbits -register x18 : xlenbits -register x19 : xlenbits -register x20 : xlenbits -register x21 : xlenbits -register x22 : xlenbits -register x23 : xlenbits -register x24 : xlenbits -register x25 : xlenbits -register x26 : xlenbits -register x27 : xlenbits -register x28 : xlenbits -register x29 : xlenbits -register x30 : xlenbits -register x31 : xlenbits - -val rX : forall 'n, 0 <= 'n < 32. regno('n) -> xlenbits effect {rreg} -/*function rX 0 = 0x0000000000000000 -and rX (r if r > 0) = Xs[r]*/ -function rX r = match r { - 0 => 0x0000000000000000, - 1 => x1, - 2 => x2, - 3 => x3, - 4 => x4, - 5 => x5, - 6 => x6, - 7 => x7, - 8 => x8, - 9 => x9, - 10 => x10, - 11 => x11, - 12 => x12, - 13 => x13, - 14 => x14, - 15 => x15, - 16 => x16, - 17 => x17, - 18 => x18, - 19 => x19, - 20 => x20, - 21 => x21, - 22 => x22, - 23 => x23, - 24 => x24, - 25 => x25, - 26 => x26, - 27 => x27, - 28 => x28, - 29 => x29, - 30 => x30, - 31 => x31 -} - -$ifdef RVFI_DII -val rvfi_wX : forall 'n, 0 <= 'n < 32. (regno('n), xlenbits) -> unit effect {wreg} -function rvfi_wX (r,v) = { - rvfi_exec->rvfi_rd_wdata() = v; - rvfi_exec->rvfi_rd_addr() = to_bits(8,r); -} -$else -val rvfi_wX : forall 'n, 0 <= 'n < 32. (regno('n), xlenbits) -> unit -function rvfi_wX (r,v) = () -$endif - -val wX : forall 'n, 0 <= 'n < 32. (regno('n), xlenbits) -> unit effect {wreg} -function wX (r, v) = { - match r { - 0 => (), - 1 => x1 = v, - 2 => x2 = v, - 3 => x3 = v, - 4 => x4 = v, - 5 => x5 = v, - 6 => x6 = v, - 7 => x7 = v, - 8 => x8 = v, - 9 => x9 = v, - 10 => x10 = v, - 11 => x11 = v, - 12 => x12 = v, - 13 => x13 = v, - 14 => x14 = v, - 15 => x15 = v, - 16 => x16 = v, - 17 => x17 = v, - 18 => x18 = v, - 19 => x19 = v, - 20 => x20 = v, - 21 => x21 = v, - 22 => x22 = v, - 23 => x23 = v, - 24 => x24 = v, - 25 => x25 = v, - 26 => x26 = v, - 27 => x27 = v, - 28 => x28 = v, - 29 => x29 = v, - 30 => x30 = v, - 31 => x31 = v - }; - if (r != 0) then { - rvfi_wX(r,v); - // Xs[r] = v; - print_reg("x" ^ string_of_int(r) ^ " <- " ^ BitStr(v)); - } -} - -overload X = {rX, wX} - -/* register names */ - -val cast reg_name_abi : regbits -> string - -function reg_name_abi(r) = { - match (r) { - 0b00000 => "zero", - 0b00001 => "ra", - 0b00010 => "sp", - 0b00011 => "gp", - 0b00100 => "tp", - 0b00101 => "t0", - 0b00110 => "t1", - 0b00111 => "t2", - 0b01000 => "fp", - 0b01001 => "s1", - 0b01010 => "a0", - 0b01011 => "a1", - 0b01100 => "a2", - 0b01101 => "a3", - 0b01110 => "a4", - 0b01111 => "a5", - 0b10000 => "a6", - 0b10001 => "a7", - 0b10010 => "s2", - 0b10011 => "s3", - 0b10100 => "s4", - 0b10101 => "s5", - 0b10110 => "s6", - 0b10111 => "s7", - 0b11000 => "s8", - 0b11001 => "s9", - 0b11010 => "s10", - 0b11011 => "s11", - 0b11100 => "t3", - 0b11101 => "t4", - 0b11110 => "t5", - 0b11111 => "t6" - } -} - -/* instruction fields */ - -type opcode = bits(7) -type imm12 = bits(12) -type imm20 = bits(20) -type amo = bits(1) /* amo opcode flags */ - -/* base architecture definitions */ - -enum Architecture = {RV32, RV64, RV128} -type arch_xlen = bits(2) -function architecture(a : arch_xlen) -> option(Architecture) = - match (a) { - 0b01 => Some(RV32), - 0b10 => Some(RV64), - 0b11 => Some(RV128), - _ => None() - } - -function arch_to_bits(a : Architecture) -> arch_xlen = - match (a) { - RV32 => 0b01, - RV64 => 0b10, - RV128 => 0b11 - } - -/* privilege levels */ - -type priv_level = bits(2) -enum Privilege = {User, Supervisor, Machine} - -val cast privLevel_to_bits : Privilege -> priv_level -function privLevel_to_bits (p) = - match (p) { - User => 0b00, - Supervisor => 0b01, - Machine => 0b11 - } - -val cast privLevel_of_bits : priv_level -> Privilege -function privLevel_of_bits (p) = - match (p) { - 0b00 => User, - 0b01 => Supervisor, - 0b11 => Machine - } - -val cast privLevel_to_str : Privilege -> string -function privLevel_to_str (p) = - match (p) { - User => "U", - Supervisor => "S", - Machine => "M" - } - -/* memory access types */ - -enum AccessType = {Read, Write, ReadWrite, Execute} - -val cast accessType_to_str : AccessType -> string -function accessType_to_str (a) = - match (a) { - Read => "R", - Write => "W", - ReadWrite => "RW", - Execute => "X" - } - -enum ReadType = {Instruction, Data} - -val cast readType_to_str : ReadType -> string -function readType_to_str (r) = - match (r) { - Instruction => "I", - Data => "D" - } - -enum word_width = {BYTE, HALF, WORD, DOUBLE} - -/* architectural interrupt definitions */ - -type exc_code = bits(4) - -enum InterruptType = { - I_U_Software, - I_S_Software, - I_M_Software, - I_U_Timer, - I_S_Timer, - I_M_Timer, - I_U_External, - I_S_External, - I_M_External -} - -val cast interruptType_to_bits : InterruptType -> exc_code -function interruptType_to_bits (i) = - match (i) { - I_U_Software => 0x0, - I_S_Software => 0x1, - I_M_Software => 0x3, - I_U_Timer => 0x4, - I_S_Timer => 0x5, - I_M_Timer => 0x7, - I_U_External => 0x8, - I_S_External => 0x9, - I_M_External => 0xb - } - -/* architectural exception definitions */ - -enum ExceptionType = { - E_Fetch_Addr_Align, - E_Fetch_Access_Fault, - E_Illegal_Instr, - E_Breakpoint, - E_Load_Addr_Align, - E_Load_Access_Fault, - E_SAMO_Addr_Align, - E_SAMO_Access_Fault, - E_U_EnvCall, - E_S_EnvCall, - E_Reserved_10, - E_M_EnvCall, - E_Fetch_Page_Fault, - E_Load_Page_Fault, - E_Reserved_14, - E_SAMO_Page_Fault -} - -val cast exceptionType_to_bits : ExceptionType -> exc_code -function exceptionType_to_bits(e) = - match (e) { - E_Fetch_Addr_Align => 0x0, - E_Fetch_Access_Fault => 0x1, - E_Illegal_Instr => 0x2, - E_Breakpoint => 0x3, - E_Load_Addr_Align => 0x4, - E_Load_Access_Fault => 0x5, - E_SAMO_Addr_Align => 0x6, - E_SAMO_Access_Fault => 0x7, - E_U_EnvCall => 0x8, - E_S_EnvCall => 0x9, - E_Reserved_10 => 0xa, - E_M_EnvCall => 0xb, - E_Fetch_Page_Fault => 0xc, - E_Load_Page_Fault => 0xd, - E_Reserved_14 => 0xe, - E_SAMO_Page_Fault => 0xf - } - -val cast exceptionType_to_str : ExceptionType -> string -function exceptionType_to_str(e) = - match (e) { - E_Fetch_Addr_Align => "misaligned-fetch", - E_Fetch_Access_Fault => "fetch-access-fault", - E_Illegal_Instr => "illegal-instruction", - E_Breakpoint => "breakpoint", - E_Load_Addr_Align => "misaligned-load", - E_Load_Access_Fault => "load-access-fault", - E_SAMO_Addr_Align => "misaliged-store/amo", - E_SAMO_Access_Fault => "store/amo-access-fault", - E_U_EnvCall => "u-call", - E_S_EnvCall => "s-call", - E_Reserved_10 => "reserved-0", - E_M_EnvCall => "m-call", - E_Fetch_Page_Fault => "fetch-page-fault", - E_Load_Page_Fault => "load-page-fault", - E_Reserved_14 => "reserved-1", - E_SAMO_Page_Fault => "store/amo-page-fault" - } - -/* model-internal exceptions */ - -union exception = { - Error_not_implemented : string, - Error_internal_error : unit -} - -val not_implemented : forall ('a : Type). string -> 'a effect {escape} -function not_implemented message = throw(Error_not_implemented(message)) - -val internal_error : forall ('a : Type). string -> 'a effect {escape} -function internal_error(s) = { - assert (false, s); - throw Error_internal_error() -} - -/* trap modes */ - -type tv_mode = bits(2) -enum TrapVectorMode = {TV_Direct, TV_Vector, TV_Reserved} - -val cast trapVectorMode_of_bits : tv_mode -> TrapVectorMode -function trapVectorMode_of_bits (m) = - match (m) { - 0b00 => TV_Direct, - 0b01 => TV_Vector, - _ => TV_Reserved - } - -/* extension context status */ - -type ext_status = bits(2) -enum ExtStatus = {Off, Initial, Clean, Dirty} - -val cast extStatus_to_bits : ExtStatus -> ext_status -function extStatus_to_bits(e) = - match (e) { - Off => 0b00, - Initial => 0b01, - Clean => 0b10, - Dirty => 0b11 - } - -val cast extStatus_of_bits : ext_status -> ExtStatus -function extStatus_of_bits(e) = - match (e) { - 0b00 => Off, - 0b01 => Initial, - 0b10 => Clean, - 0b11 => Dirty - } - -/* supervisor-level address translation modes */ - -type satp_mode = bits(4) -enum SATPMode = {Sbare, Sv32, Sv39} - -function satpMode_of_bits(a : Architecture, m : satp_mode) -> option(SATPMode) = - match (a, m) { - (_, 0x0) => Some(Sbare), - (RV32, 0x1) => Some(Sv32), - (RV64, 0x8) => Some(Sv39), - (_, _) => None() - } - -/* CSR access control bits (from CSR addresses) */ - -type csrRW = bits(2) /* read/write */ - -/* instruction opcode grouping */ -enum uop = {RISCV_LUI, RISCV_AUIPC} /* upper immediate ops */ -enum bop = {RISCV_BEQ, RISCV_BNE, RISCV_BLT, - RISCV_BGE, RISCV_BLTU, RISCV_BGEU} /* branch ops */ -enum iop = {RISCV_ADDI, RISCV_SLTI, RISCV_SLTIU, - RISCV_XORI, RISCV_ORI, RISCV_ANDI} /* immediate ops */ -enum sop = {RISCV_SLLI, RISCV_SRLI, RISCV_SRAI} /* shift ops */ -enum rop = {RISCV_ADD, RISCV_SUB, RISCV_SLL, RISCV_SLT, - RISCV_SLTU, RISCV_XOR, RISCV_SRL, RISCV_SRA, - RISCV_OR, RISCV_AND} /* reg-reg ops */ - -enum ropw = {RISCV_ADDW, RISCV_SUBW, RISCV_SLLW, - RISCV_SRLW, RISCV_SRAW} /* reg-reg 32-bit ops */ -enum sopw = {RISCV_SLLIW, RISCV_SRLIW, - RISCV_SRAIW} /* RV64-only shift ops */ -enum amoop = {AMOSWAP, AMOADD, AMOXOR, AMOAND, AMOOR, - AMOMIN, AMOMAX, AMOMINU, AMOMAXU} /* AMO ops */ -enum csrop = {CSRRW, CSRRS, CSRRC} /* CSR ops */ - -/* mappings for assembly */ - -val reg_name : bits(5) <-> string -mapping reg_name = { - 0b00000 <-> "zero", - 0b00001 <-> "ra", - 0b00010 <-> "sp", - 0b00011 <-> "gp", - 0b00100 <-> "tp", - 0b00101 <-> "t0", - 0b00110 <-> "t1", - 0b00111 <-> "t2", - 0b01000 <-> "fp", - 0b01001 <-> "s1", - 0b01010 <-> "a0", - 0b01011 <-> "a1", - 0b01100 <-> "a2", - 0b01101 <-> "a3", - 0b01110 <-> "a4", - 0b01111 <-> "a5", - 0b10000 <-> "a6", - 0b10001 <-> "a7", - 0b10010 <-> "s2", - 0b10011 <-> "s3", - 0b10100 <-> "s4", - 0b10101 <-> "s5", - 0b10110 <-> "s6", - 0b10111 <-> "s7", - 0b11000 <-> "s8", - 0b11001 <-> "s9", - 0b11010 <-> "s10", - 0b11011 <-> "s11", - 0b11100 <-> "t3", - 0b11101 <-> "t4", - 0b11110 <-> "t5", - 0b11111 <-> "t6" -} - -mapping creg_name : bits(3) <-> string = { - 0b000 <-> "s0", - 0b001 <-> "s1", - 0b010 <-> "a0", - 0b011 <-> "a1", - 0b100 <-> "a2", - 0b101 <-> "a3", - 0b110 <-> "a4", - 0b111 <-> "a5" -} - -val sep : unit <-> string -mapping sep : unit <-> string = { - () <-> opt_spc() ^ "," ^ def_spc() -} - -mapping bool_bits : bool <-> bits(1) = { - true <-> 0b1, - false <-> 0b0 -} - -mapping bool_not_bits : bool <-> bits(1) = { - true <-> 0b0, - false <-> 0b1 -} - -mapping size_bits : word_width <-> bits(2) = { - BYTE <-> 0b00, - HALF <-> 0b01, - WORD <-> 0b10, - DOUBLE <-> 0b11 -} - -mapping size_mnemonic : word_width <-> string = { - BYTE <-> "b", - HALF <-> "h", - WORD <-> "w", - DOUBLE <-> "d" -} diff --git a/riscv/riscv_vmem.sail b/riscv/riscv_vmem.sail deleted file mode 100644 index b617d297..00000000 --- a/riscv/riscv_vmem.sail +++ /dev/null @@ -1,406 +0,0 @@ -/* Supervisor-mode address translation and page-table walks. */ - -/* PageSize */ - -let PAGESIZE_BITS = 12 - -/* PTE attributes, permission checks and updates */ - -type pteAttribs = bits(8) - -bitfield PTE_Bits : pteAttribs = { - D : 7, - A : 6, - G : 5, - U : 4, - X : 3, - W : 2, - R : 1, - V : 0 -} - -function isPTEPtr(p : pteAttribs) -> bool = { - let a = Mk_PTE_Bits(p); - a.R() == false & a.W() == false & a.X() == false -} - -function isInvalidPTE(p : pteAttribs) -> bool = { - let a = Mk_PTE_Bits(p); - a.V() == false | (a.W() == true & a.R() == false) -} - -function checkPTEPermission(ac : AccessType, priv : Privilege, mxr : bool, do_sum : bool, p : PTE_Bits) -> bool = { - match (ac, priv) { - (Read, User) => p.U() == true & (p.R() == true | (p.X() == true & mxr)), - (Write, User) => p.U() == true & p.W() == true, - (ReadWrite, User) => p.U() == true & p.W() == true & (p.R() == true | (p.X() == true & mxr)), - (Execute, User) => p.U() == true & p.X() == true, - - (Read, Supervisor) => (p.U() == false | do_sum) & (p.R() == true | (p.X() == true & mxr)), - (Write, Supervisor) => (p.U() == false | do_sum) & p.W() == true, - (ReadWrite, Supervisor) => (p.U() == false | do_sum) & p.W() == true & (p.R() == true | (p.X() == true & mxr)), - (Execute, Supervisor) => p.U() == false & p.X() == true, - - (_, Machine) => internal_error("m-mode mem perm check") - } -} - -function update_PTE_Bits(p : PTE_Bits, a : AccessType) -> option(PTE_Bits) = { - let update_d = (a == Write | a == ReadWrite) & p.D() == false; // dirty-bit - let update_a = p.A() == false; // accessed-bit - if update_d | update_a then { - let np = update_A(p, true); - let np = if update_d then update_D(np, true) else np; - Some(np) - } else None() -} - -/* failure modes for address-translation/page-table-walks */ -enum PTW_Error = { - PTW_Access, /* physical memory access error for a PTE */ - PTW_Invalid_PTE, - PTW_No_Permission, - PTW_Misaligned, /* misaligned superpage */ - PTW_PTE_Update /* PTE update needed but not enabled */ -} -val cast ptw_error_to_str : PTW_Error -> string -function ptw_error_to_str(e) = - match (e) { - PTW_Access => "mem-access-error", - PTW_Invalid_PTE => "invalid-pte", - PTW_No_Permission => "no-permission", - PTW_Misaligned => "misaligned-superpage", - PTW_PTE_Update => "pte-update-needed" - } - -/* conversion of these translation/PTW failures into architectural exceptions */ -function translationException(a : AccessType, f : PTW_Error) -> ExceptionType = { - let e : ExceptionType = - match (a, f) { - (ReadWrite, PTW_Access) => E_SAMO_Access_Fault, - (ReadWrite, _) => E_SAMO_Page_Fault, - (Read, PTW_Access) => E_Load_Access_Fault, - (Read, _) => E_Load_Page_Fault, - (Write, PTW_Access) => E_SAMO_Access_Fault, - (Write, _) => E_SAMO_Page_Fault, - (Fetch, PTW_Access) => E_Fetch_Access_Fault, - (Fetch, _) => E_Fetch_Page_Fault - } in { -/* print("translationException(" ^ a ^ ", " ^ f ^ ") -> " ^ e); */ - e - } -} -/* address translation: Sv39 */ - -let SV39_LEVEL_BITS = 9 -let SV39_LEVELS = 3 -let PTE39_LOG_SIZE = 3 -let PTE39_SIZE = 8 - -type vaddr39 = bits(39) -type paddr39 = bits(56) -type pte39 = xlenbits - -bitfield SV39_Vaddr : vaddr39 = { - VPNi : 38 .. 12, - PgOfs : 11 .. 0 -} - -bitfield SV39_Paddr : paddr39 = { - PPNi : 55 .. 12, - PgOfs : 11 .. 0 -} - -bitfield SV39_PTE : pte39 = { - PPNi : 53 .. 10, - RSW : 9 .. 8, - BITS : 7 .. 0 -} - -/* ASID */ - -type asid64 = bits(16) - -function curAsid64() -> asid64 = { - let satp64 = Mk_Satp64(satp); - satp64.Asid() -} - -/* Current page table base from satp */ -function curPTB39() -> paddr39 = { - let satp64 = Mk_Satp64(satp); - EXTZ(shiftl(satp64.PPN(), PAGESIZE_BITS)) -} - -/* Page-table walk. */ - -union PTW_Result = { - PTW_Success: (paddr39, SV39_PTE, paddr39, nat, bool), - PTW_Failure: PTW_Error -} - -val walk39 : (vaddr39, AccessType, Privilege, bool, bool, paddr39, nat, bool) -> PTW_Result effect {rmem, escape} -function walk39(vaddr, ac, priv, mxr, do_sum, ptb, level, global) -> PTW_Result = { - let va = Mk_SV39_Vaddr(vaddr); - let pt_ofs : paddr39 = shiftl(EXTZ(shiftr(va.VPNi(), (level * SV39_LEVEL_BITS))[(SV39_LEVEL_BITS - 1) .. 0]), - PTE39_LOG_SIZE); - let pte_addr = ptb + pt_ofs; - /* FIXME: we assume here that walks only access physical-memory-backed addresses, and not MMIO regions. */ - match (phys_mem_read(Data, EXTZ(pte_addr), 8, false, false, false)) { - MemException(_) => { -/* print("walk39(vaddr=" ^ BitStr(vaddr) ^ " level=" ^ string_of_int(level) - ^ " pt_base=" ^ BitStr(ptb) - ^ " pt_ofs=" ^ BitStr(pt_ofs) - ^ " pte_addr=" ^ BitStr(pte_addr) - ^ ": invalid pte address"); */ - PTW_Failure(PTW_Access) - }, - MemValue(v) => { - let pte = Mk_SV39_PTE(v); - let pbits = pte.BITS(); - let pattr = Mk_PTE_Bits(pbits); - let is_global = global | (pattr.G() == true); -/* print("walk39(vaddr=" ^ BitStr(vaddr) ^ " level=" ^ string_of_int(level) - ^ " pt_base=" ^ BitStr(ptb) - ^ " pt_ofs=" ^ BitStr(pt_ofs) - ^ " pte_addr=" ^ BitStr(pte_addr) - ^ " pte=" ^ BitStr(v)); */ - if isInvalidPTE(pbits) then { -/* print("walk39: invalid pte"); */ - PTW_Failure(PTW_Invalid_PTE) - } else { - if isPTEPtr(pbits) then { - if level == 0 then { - /* last-level PTE contains a pointer instead of a leaf */ -/* print("walk39: last-level pte contains a ptr"); */ - PTW_Failure(PTW_Invalid_PTE) - } else { - /* walk down the pointer to the next level */ - walk39(vaddr, ac, priv, mxr, do_sum, EXTZ(shiftl(pte.PPNi(), PAGESIZE_BITS)), level - 1, is_global) - } - } else { /* leaf PTE */ - if ~ (checkPTEPermission(ac, priv, mxr, do_sum, pattr)) then { -/* print("walk39: pte permission check failure"); */ - PTW_Failure(PTW_No_Permission) - } else { - if level > 0 then { /* superpage */ - /* fixme hack: to get a mask of appropriate size */ - let mask = shiftl(pte.PPNi() ^ pte.PPNi() ^ EXTZ(0b1), level * SV39_LEVEL_BITS) - 1; - if (pte.PPNi() & mask) != EXTZ(0b0) then { - /* misaligned superpage mapping */ -/* print("walk39: misaligned superpage mapping"); */ - PTW_Failure(PTW_Misaligned) - } else { - /* add the appropriate bits of the VPN to the superpage PPN */ - let ppn = pte.PPNi() | (EXTZ(va.VPNi()) & mask); -/* let res = append(ppn, va.PgOfs()); - print("walk39: using superpage: pte.ppn=" ^ BitStr(pte.PPNi()) - ^ " ppn=" ^ BitStr(ppn) ^ " res=" ^ BitStr(res)); */ - PTW_Success(append(ppn, va.PgOfs()), pte, pte_addr, level, is_global) - } - } else { - /* normal leaf PTE */ -/* let res = append(pte.PPNi(), va.PgOfs()); - print("walk39: pte.ppn=" ^ BitStr(pte.PPNi()) ^ " ppn=" ^ BitStr(pte.PPNi()) ^ " res=" ^ BitStr(res)); */ - PTW_Success(append(pte.PPNi(), va.PgOfs()), pte, pte_addr, level, is_global) - } - } - } - } - } - } -} - -/* idealized TLB to model fence.vm and also speed up simulation. */ - -struct TLB39_Entry = { - asid : asid64, - global : bool, - vAddr : vaddr39, /* VPN */ - pAddr : paddr39, /* PPN */ - vMatchMask : vaddr39, /* matching mask for superpages */ - vAddrMask : vaddr39, /* selection mask for superpages */ - pte : SV39_PTE, /* permissions */ - pteAddr : paddr39, /* for dirty writeback */ - age : xlenbits -} - -/* the rreg effect is an artifact of using the cycle counter to provide the age */ -val make_TLB39_Entry : (asid64, bool, vaddr39, paddr39, SV39_PTE, nat, paddr39) -> TLB39_Entry effect {rreg} - -function make_TLB39_Entry(asid, global, vAddr, pAddr, pte, level, pteAddr) = { - let shift : nat = PAGESIZE_BITS + (level * SV39_LEVEL_BITS); - /* fixme hack: use a better idiom for masks */ - let vAddrMask : vaddr39 = shiftl(vAddr ^ vAddr ^ EXTZ(0b1), shift) - 1; - let vMatchMask : vaddr39 = ~ (vAddrMask); - struct { - asid = asid, - global = global, - pte = pte, - pteAddr = pteAddr, - vAddrMask = vAddrMask, - vMatchMask = vMatchMask, - vAddr = vAddr & vMatchMask, - pAddr = shiftl(shiftr(pAddr, shift), shift), - age = mcycle - } -} - -/* TODO: make this a vector or array of entries */ -register tlb39 : option(TLB39_Entry) - -val lookupTLB39 : (asid64, vaddr39) -> option((int, TLB39_Entry)) effect {rreg} -function lookupTLB39(asid, vaddr) = { - match tlb39 { - None() => None(), - Some(e) => if (e.global | (e.asid == asid)) - & (e.vAddr == (e.vMatchMask & vaddr)) - then Some((0, e)) - else None() - } -} - -val addToTLB39 : (asid64, vaddr39, paddr39, SV39_PTE, paddr39, nat, bool) -> unit effect {wreg, rreg} -function addToTLB39(asid, vAddr, pAddr, pte, pteAddr, level, global) = { - let ent = make_TLB39_Entry(asid, global, vAddr, pAddr, pte, level, pteAddr); - tlb39 = Some(ent) -} - -function writeTLB39(idx : int, ent : TLB39_Entry) -> unit = - tlb39 = Some(ent) - -val flushTLB : (option(asid64), option(vaddr39)) -> unit effect {rreg, wreg} -function flushTLB(asid, addr) = { - let ent : option(TLB39_Entry) = - match (tlb39, asid, addr) { - (None(), _, _) => None(), - (Some(e), None(), None()) => None(), - (Some(e), None(), Some(a)) => if e.vAddr == (e.vMatchMask & a) - then None() else Some(e), - (Some(e), Some(i), None()) => if (e.asid == i) & (~ (e.global)) - then None() else Some(e), - (Some(e), Some(i), Some(a)) => if (e.asid == i) & (e.vAddr == (a & e.vMatchMask)) - & (~ (e.global)) - then None() else Some(e) - }; - tlb39 = ent -} - -union TR39_Result = { - TR39_Address : paddr39, - TR39_Failure : PTW_Error -} - -val translate39 : (vaddr39, AccessType, Privilege, bool, bool, nat) -> TR39_Result effect {rreg, wreg, wmv, escape, rmem} -function translate39(vAddr, ac, priv, mxr, do_sum, level) = { - let asid = curAsid64(); - match lookupTLB39(asid, vAddr) { - Some(idx, ent) => { - let pteBits = Mk_PTE_Bits(ent.pte.BITS()); - if ~ (checkPTEPermission(ac, priv, mxr, do_sum, pteBits)) - then TR39_Failure(PTW_No_Permission) - else { - match update_PTE_Bits(pteBits, ac) { - None() => TR39_Address(ent.pAddr | EXTZ(vAddr & ent.vAddrMask)), - Some(pbits) => { - if ~ (plat_enable_dirty_update ()) - then { - /* pte needs dirty/accessed update but that is not enabled */ - TR39_Failure(PTW_PTE_Update) - } else { - /* update PTE entry and TLB */ - n_ent : TLB39_Entry = ent; - n_ent.pte = update_BITS(ent.pte, pbits.bits()); - writeTLB39(idx, n_ent); - /* update page table */ - match checked_mem_write(EXTZ(ent.pteAddr), 8, ent.pte.bits()) { - MemValue(_) => (), - MemException(e) => internal_error("invalid physical address in TLB") - }; - TR39_Address(ent.pAddr | EXTZ(vAddr & ent.vAddrMask)) - } - } - } - } - }, - None() => { - match walk39(vAddr, ac, priv, mxr, do_sum, curPTB39(), level, false) { - PTW_Failure(f) => TR39_Failure(f), - PTW_Success(pAddr, pte, pteAddr, level, global) => { - match update_PTE_Bits(Mk_PTE_Bits(pte.BITS()), ac) { - None() => { - addToTLB39(asid, vAddr, pAddr, pte, pteAddr, level, global); - TR39_Address(pAddr) - }, - Some(pbits) => - if ~ (plat_enable_dirty_update ()) - then { - /* pte needs dirty/accessed update but that is not enabled */ - TR39_Failure(PTW_PTE_Update) - } else { - w_pte : SV39_PTE = update_BITS(pte, pbits.bits()); - match checked_mem_write(EXTZ(pteAddr), 8, w_pte.bits()) { - MemValue(_) => { - addToTLB39(asid, vAddr, pAddr, w_pte, pteAddr, level, global); - TR39_Address(pAddr) - }, - MemException(e) => { - /* pte is not in valid memory */ - TR39_Failure(PTW_Access) - } - } - } - } - } - } - } - } -} - -/* Address translation mode */ - -val translationMode : (Privilege) -> SATPMode effect {rreg, escape} -function translationMode(priv) = { - if priv == Machine then Sbare - else { - let arch = architecture(mstatus.SXL()); - match arch { - Some(RV64) => { - let mbits : satp_mode = Mk_Satp64(satp).Mode(); - match satpMode_of_bits(RV64, mbits) { - Some(m) => m, - None() => internal_error("invalid RV64 translation mode in satp") - } - }, - _ => internal_error("unsupported address translation arch") - } - } -} - -union TR_Result = { - TR_Address : xlenbits, - TR_Failure : ExceptionType -} - -/* Top-level address translation dispatcher */ - -val translateAddr : (xlenbits, AccessType, ReadType) -> TR_Result effect {escape, rmem, rreg, wmv, wreg} -function translateAddr(vAddr, ac, rt) = { - let effPriv : Privilege = match rt { - Instruction => cur_privilege, - Data => if mstatus.MPRV() == true - then privLevel_of_bits(mstatus.MPP()) - else cur_privilege - }; - let mxr : bool = mstatus.MXR() == true; - let do_sum : bool = mstatus.SUM() == true; - let mode : SATPMode = translationMode(effPriv); - match mode { - Sbare => TR_Address(vAddr), - SV39 => match translate39(vAddr[38 .. 0], ac, effPriv, mxr, do_sum, SV39_LEVELS - 1) { - TR39_Address(pa) => TR_Address(EXTZ(pa)), - TR39_Failure(f) => TR_Failure(translationException(ac, f)) - }, - _ => internal_error("unsupported address translation scheme") - } -} diff --git a/riscv/rvfi_dii.sail b/riscv/rvfi_dii.sail deleted file mode 100644 index 9680ab49..00000000 --- a/riscv/rvfi_dii.sail +++ /dev/null @@ -1,98 +0,0 @@ -// "RISC-V Formal Interface - Direct Instruction Injection" support -// For use with https://github.com/CTSRD-CHERI/TestRIG - -$define RVFI_DII - -bitfield RVFI_DII_Instruction_Packet : bits(64) = { - padding : 63 .. 56, // [7] - rvfi_cmd : 55 .. 48, // [6] This token is a trace command. For example, reset device under test. - rvfi_time : 47 .. 32, // [5 - 4] Time to inject token. The difference between this and the previous - // instruction time gives a delay before injecting this instruction. - // This can be ignored for models but gives repeatability for implementations - // while shortening counterexamples. - rvfi_insn : 31 .. 0, // [0 - 3] Instruction word: 32-bit instruction or command. The lower 16-bits - // may decode to a 16-bit compressed instruction. -} - -register rvfi_instruction : RVFI_DII_Instruction_Packet - -val rvfi_set_instr_packet : bits(64) -> unit effect {wreg} - -function rvfi_set_instr_packet(p) = - rvfi_instruction = Mk_RVFI_DII_Instruction_Packet(p) - -val rvfi_get_cmd : unit -> bits(8) effect {rreg} - -function rvfi_get_cmd () = rvfi_instruction.rvfi_cmd() - -val print_instr_packet : bits(64) -> unit - -function print_instr_packet(bs) = { - let p = Mk_RVFI_DII_Instruction_Packet(bs); - print_bits("command", p.rvfi_cmd()); - print_bits("instruction", p.rvfi_insn()) -} - -bitfield RVFI_DII_Execution_Packet : bits(704) = { - rvfi_intr : 703 .. 696, // [87] Trap handler: Set for first instruction in trap handler. - rvfi_halt : 695 .. 688, // [86] Halt indicator: Marks the last instruction retired - // before halting execution. - rvfi_trap : 687 .. 680, // [85] Trap indicator: Invalid decode, misaligned access or - // jump command to misaligned address. - rvfi_rd_addr : 679 .. 672, // [84] Write register address: MUST be 0 if not used. - rvfi_rs2_addr : 671 .. 664, // [83] otherwise set as decoded. - rvfi_rs1_addr : 663 .. 656, // [82] Read register addresses: Can be arbitrary when not used, - rvfi_mem_wmask : 655 .. 648, // [81] Write mask: Indicates valid bytes written. 0 if unused. - rvfi_mem_rmask : 647 .. 640, // [80] Read mask: Indicates valid bytes read. 0 if unused. - rvfi_mem_wdata : 639 .. 576, // [72 - 79] Write data: Data written to memory by this command. - rvfi_mem_rdata : 575 .. 512, // [64 - 71] Read data: Data read from mem_addr (i.e. before write) - rvfi_mem_addr : 511 .. 448, // [56 - 63] Memory access addr: Points to byte address (aligned if define - // is set). *Should* be straightforward. - // 0 if unused. - rvfi_rd_wdata : 447 .. 384, // [48 - 55] Write register value: MUST be 0 if rd_ is 0. - rvfi_rs2_data : 383 .. 320, // [40 - 47] above. Must be 0 if register ID is 0. - rvfi_rs1_data : 319 .. 256, // [32 - 39] Read register values: Values as read from registers named - rvfi_insn : 255 .. 192, // [24 - 31] Instruction word: 32-bit command value. - rvfi_pc_wdata : 191 .. 128, // [16 - 23] PC after instr: Following PC - either PC + 4 or jump/trap target. - rvfi_pc_rdata : 127 .. 64, // [08 - 15] PC before instr: PC for current instruction - rvfi_order : 63 .. 0, // [00 - 07] Instruction number: INSTRET value after completion. -} - -register rvfi_exec : RVFI_DII_Execution_Packet - -val rvfi_zero_exec_packet : unit -> unit effect {wreg} - -function rvfi_zero_exec_packet () = - rvfi_exec = Mk_RVFI_DII_Execution_Packet(zero_extend(0b0,704)) - -val rvfi_halt_exec_packet : unit -> unit effect {wreg} - -function rvfi_halt_exec_packet () = - rvfi_exec->rvfi_halt() = 0x01 - -val rvfi_get_exec_packet : unit -> bits(704) effect {rreg} - -function rvfi_get_exec_packet() = rvfi_exec.bits() - -val print_rvfi_exec : unit -> unit effect {rreg} - -function print_rvfi_exec () = { - print_bits("rvfi_intr : ", rvfi_exec.rvfi_intr()); - print_bits("rvfi_halt : ", rvfi_exec.rvfi_halt()); - print_bits("rvfi_trap : ", rvfi_exec.rvfi_trap()); - print_bits("rvfi_rd_addr : ", rvfi_exec.rvfi_rd_addr()); - print_bits("rvfi_rs2_addr : ", rvfi_exec.rvfi_rs2_addr()); - print_bits("rvfi_rs1_addr : ", rvfi_exec.rvfi_rs1_addr()); - print_bits("rvfi_mem_wmask: ", rvfi_exec.rvfi_mem_wmask()); - print_bits("rvfi_mem_rmask: ", rvfi_exec.rvfi_mem_rmask()); - print_bits("rvfi_mem_wdata: ", rvfi_exec.rvfi_mem_wdata()); - print_bits("rvfi_mem_rdata: ", rvfi_exec.rvfi_mem_rdata()); - print_bits("rvfi_mem_addr : ", rvfi_exec.rvfi_mem_addr()); - print_bits("rvfi_rd_wdata : ", rvfi_exec.rvfi_rd_wdata()); - print_bits("rvfi_rs2_data : ", rvfi_exec.rvfi_rs2_data()); - print_bits("rvfi_rs1_data : ", rvfi_exec.rvfi_rs1_data()); - print_bits("rvfi_insn : ", rvfi_exec.rvfi_insn()); - print_bits("rvfi_pc_wdata : ", rvfi_exec.rvfi_pc_wdata()); - print_bits("rvfi_pc_rdata : ", rvfi_exec.rvfi_pc_rdata()); - print_bits("rvfi_order : ", rvfi_exec.rvfi_order()); -} diff --git a/riscv/tracecmp.ml b/riscv/tracecmp.ml deleted file mode 100644 index 64a918d5..00000000 --- a/riscv/tracecmp.ml +++ /dev/null @@ -1,300 +0,0 @@ -(* Simple trace comparison checker *) - -type csr_read = { - csrr : string; - rdval : int64 -} - -type csr_write = { - csrw : string; - wrval : int64; - inval : int64 -} - -type reg_write = { - reg : int; - rval : int64 -} - -type inst = { - count : int; - priv : char; - pc : int64; - inst: int32 -} - -type tick = { - time : int64 -} - -type htif = { - tohost : int64 -} - -type ld_res = - | Res_make of int64 - | Res_match of int64 * int64 - | Res_cancel - -type line = - | L_none - | L_inst of inst - | L_reg_write of reg_write - | L_csr_read of csr_read - | L_csr_write of csr_write - | L_tick of tick - | L_htif of htif - | L_ld_res of ld_res - -let inst_count = ref 0 - -(* csr reads - CSR mscratch -> 0x0000000000000000 - *) - -let parse_csr_read l = - try Scanf.sscanf l " CSR %s -> 0x%Lx" (fun csrr rdval -> L_csr_read { csrr; rdval }) - with - | Scanf.Scan_failure _ -> L_none - | End_of_file -> L_none - -let sprint_csr_read r = - Printf.sprintf "CSR %s -> 0x%Lx" r.csrr r.rdval - -(* csr writes - CSR mstatus <- 0x0000000a00020800 (input: 0x0000000a00020800) - *) - -let parse_csr_write l = - try Scanf.sscanf l " CSR %s <- 0x%Lx (input: 0x%Lx)" - (fun csrw wrval inval -> L_csr_write { csrw; wrval; inval }) - with - | Scanf.Scan_failure _ -> L_none - | End_of_file -> L_none - -let sprint_csr_write r = - Printf.sprintf "CSR %s <- 0x%Lx (input: 0x%Lx)" r.csrw r.wrval r.inval - -(* reg writes - x16 <- 0x0000000000000000 - *) - -let parse_reg_write l = - try Scanf.sscanf l " x%u <- 0x%Lx" - (fun reg rval -> L_reg_write { reg; rval }) - with - | Scanf.Scan_failure _ -> L_none - | End_of_file -> L_none - -let sprint_reg_write r = - Printf.sprintf "x%u <- 0x%Lx" r.reg r.rval - -(* instructions *) - -let sprint_inst r = - Printf.sprintf "[%u] [%c]: 0x%Lx (0x%lx)" r.count r.priv r.pc r.inst - -(* sail instruction line: - [13000] [M]: 0x0000000080000E4A (0x0107971B) slli a4, a5, 0b10000 - *) - -let parse_sail_inst l = - try Scanf.sscanf l " [%u] [%c]: 0x%Lx (0x%lx) %s" - (fun count priv pc inst _ -> - inst_count := count; - L_inst { count; priv; pc; inst }) - with - | Scanf.Scan_failure _ -> L_none - | End_of_file -> L_none - -(* spike instruction line: - [2] core 0 [M]: 0x0000000000001008 (0xf1402573) csrr a0, mhartid - *) - -let parse_spike_inst l = - try Scanf.sscanf l " [%u] core 0 [%c]: 0x%Lx (0x%lx) %s" - (fun count priv pc inst _ -> - inst_count := count; - L_inst { count; priv; pc; inst }) - with - | Scanf.Scan_failure _ -> L_none - | End_of_file -> L_none - -(* clock tick - clint::tick mtime <- 0x1 - *) - -let parse_tick l = - try Scanf.sscanf l " clint::tick mtime <- 0x%Lx" - (fun time -> L_tick { time }) - with - | Scanf.Scan_failure _ -> L_none - | End_of_file -> L_none - -let sprint_tick t = - Printf.sprintf "clint::tick mtime <- 0x%Lx" t.time - -(* htif tick - htif::tick 0x1 - *) - -let parse_htif l = - try Scanf.sscanf l " htif::tick 0x%Lx" - (fun tohost -> L_htif { tohost }) - with - | Scanf.Scan_failure _ -> L_none - | End_of_file -> L_none - -let sprint_htif t = - Printf.sprintf "htif::tick 0x%Lx" t.tohost - -(* Load reservations: - make: reservation <- 0x80002008 - match: reservation: 0xffffffffffffffff, key=0x80002008 - cancel: reservation <- none - - *) -let parse_ldres_match l = - try Scanf.sscanf - l " reservation: 0x%Lx, key=0x%Lx" - (fun res key -> L_ld_res (Res_match (res, key))) - with - | Scanf.Scan_failure _ -> L_none - | End_of_file -> L_none - -let parse_ldres_match_sail l = - try Scanf.sscanf - l " reservation: none, key=0x%Lx" - (fun key -> L_ld_res (Res_match (Int64.minus_one, key))) - with - | Scanf.Scan_failure _ -> L_none - | End_of_file -> L_none - -let parse_ldres_change l = - try if l = "reservation <- none" - then L_ld_res Res_cancel - else Scanf.sscanf - l " reservation <- 0x%Lx" - (fun res -> L_ld_res (Res_make res)) - with - | Scanf.Scan_failure _ -> L_none - | End_of_file -> L_none - -let sprint_ldres = function - | Res_make res -> Printf.sprintf "reservation <- 0x%Lx" res - | Res_match (res, key) -> Printf.sprintf "reservation: 0x%Lx, key=0x%Lx" res key - | Res_cancel -> Printf.sprintf "reservation <- none" - -(* scanners *) - -let popt p l = function - | L_none -> p l - | res -> res - -let parse_line l = - parse_csr_read l |> popt parse_csr_write l - |> popt parse_reg_write l |> popt parse_tick l |> popt parse_htif l - |> popt parse_ldres_change l |> popt parse_ldres_match l - -let parse_sail_line l = - parse_line l |> popt parse_sail_inst l |> popt parse_ldres_match_sail l - -let parse_spike_line l = - parse_line l |> popt parse_spike_inst l - -(* printer *) -let sprint_line = function - | L_none -> "" - | L_inst i -> sprint_inst i - | L_reg_write r -> Printf.sprintf "<%d> %s" !inst_count (sprint_reg_write r) - | L_csr_read r -> Printf.sprintf "<%d> %s" !inst_count (sprint_csr_read r) - | L_csr_write r -> Printf.sprintf "<%d> %s" !inst_count (sprint_csr_write r) - | L_tick t -> Printf.sprintf "<%d> %s" !inst_count (sprint_tick t) - | L_htif t -> Printf.sprintf "<%d> %s" !inst_count (sprint_htif t) - | L_ld_res r -> Printf.sprintf "<%d> %s" !inst_count (sprint_ldres r) - -(* file processing *) - -let rec get_line ch parse = - let line = try Some (input_line ch) - with End_of_file -> None in - match line with - | Some l -> (match parse l with - | L_none -> get_line ch parse - | r -> r - ) - | None -> L_none - -let rec print_lines ch parse = - match (get_line ch parse) with - | L_none -> () - | l -> (print_endline (sprint_line l); - print_lines ch parse) - - -let lines_matched k l = - match k, l with - (* Special case for CSR writes to sie/sip/sstatus, since spike - * does a recursive call which messes the trace log. For these - * registers, we just match the final written value, and need to - * unfortunately ignore the input value. - *) - | L_csr_write kw, L_csr_write lw -> - if ( (kw.csrw = "mie" && lw.csrw = "sie") - || (kw.csrw = "mip" && lw.csrw = "sip") - || (kw.csrw = "mstatus" && lw.csrw = "sstatus")) - then kw.wrval = lw.wrval - else kw = lw - | _, _ -> k = l - -let rec compare_traces k l cnt = - let kro = get_line k parse_spike_line in - let lro = get_line l parse_sail_line in - match kro, lro with - | L_none, L_none -> - print_endline (Printf.sprintf "Matched %d instructions" cnt) - | L_none, lr -> - print_endline "Spike: not reached"; - print_endline ("Sail: " ^ sprint_line lr); - exit 1 - | kr, L_none -> - print_endline ("Spike: " ^ sprint_line kr); - print_endline "Sail: not reached"; - exit 1 - | kr, lr -> - if lines_matched kr lr - then compare_traces k l (cnt + 1) - else (print_endline ("Spike: " ^ sprint_line kr); - print_endline ("Sail: " ^ sprint_line lr); - exit 1) - -let spike_log = ref (None : string option) -let sail_log = ref (None : string option) -let uncompress = ref false - -let in_file f = - if !uncompress - then Unix.open_process_in ("gunzip -c " ^ f) - else open_in f - -let options = - Arg.align ([( "-z", - Arg.Set uncompress, - " uncompress trace files"); - ( "-k", - Arg.String (fun f -> spike_log := Some f), - " spike trace log"); - ( "-l", - Arg.String (fun f -> sail_log := Some f), - " sail trace log")]) -let usage = "usage: tracecmp [options]\n" - -let _ = - Arg.parse options (fun s -> print_endline usage; exit 0) - usage; - match !spike_log, !sail_log with - | None, None -> (print_endline usage; exit 0) - | Some l, None -> print_lines (in_file l) parse_spike_line - | None, Some l -> print_lines (in_file l) parse_sail_line - | Some k, Some l -> compare_traces (in_file k) (in_file l) 0 - diff --git a/test/riscv/run_tests.sh b/test/riscv/run_tests.sh deleted file mode 100755 index c64c7dca..00000000 --- a/test/riscv/run_tests.sh +++ /dev/null @@ -1,89 +0,0 @@ -#!/usr/bin/env bash -set -e - -DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )" -cd $DIR -SAILDIR="$DIR/../.." - -RED='\033[0;91m' -GREEN='\033[0;92m' -YELLOW='\033[0;93m' -NC='\033[0m' - -rm -f $DIR/tests.xml - -pass=0 -fail=0 -XML="" - -function green { - (( pass += 1 )) - printf "$1: ${GREEN}$2${NC}\n" - XML+=" \n" -} - -function yellow { - (( fail += 1 )) - printf "$1: ${YELLOW}$2${NC}\n" - XML+=" \n $2\n \n" -} - -function red { - (( fail += 1 )) - printf "$1: ${RED}$2${NC}\n" - XML+=" \n $2\n \n" -} - -function finish_suite { - printf "$1: Passed ${pass} out of $(( pass + fail ))\n\n" - XML=" \n$XML \n" - printf "$XML" >> $DIR/tests.xml - XML="" - pass=0 - fail=0 -} - -SAILLIBDIR="$DIR/../../lib/" - -printf "\n" >> $DIR/tests.xml - -cd $SAILDIR/riscv - -printf "Building RISCV specification...\n" - -if make -C $SAILDIR/riscv platform ; -then - green "Building RISCV specification" "ok" -else - red "Building RISCV specification" "fail" -fi - -for test in $DIR/tests/*.elf; do - if $SAILDIR/riscv/platform "$test" >"${test/.elf/.out}" 2>&1 && grep -q SUCCESS "${test/.elf/.out}" - then - green "$(basename $test)" "ok" - else - red "$(basename $test)" "fail" - fi -done - -if make -C $SAILDIR/riscv riscv_sim; -then - green "Building RISCV specification to C" "ok" -else - red "Building RISCV specification to C" "fail" -fi - -for test in $DIR/tests/*.elf; do - if timeout 5 $SAILDIR/riscv/riscv_sim $test > ${test%.elf}.cout 2>&1 && grep -q SUCCESS ${test%.elf}.cout - then - green "$(basename $test)" "ok" - else - red "$(basename $test)" "fail" - fi -done - -finish_suite "RISCV tests" - -printf "\n" >> $DIR/tests.xml - diff --git a/test/riscv/tests/.gitignore b/test/riscv/tests/.gitignore deleted file mode 100644 index 72a5e441..00000000 --- a/test/riscv/tests/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -*.out -*.cout diff --git a/test/riscv/tests/README b/test/riscv/tests/README deleted file mode 100644 index cb1e5105..00000000 --- a/test/riscv/tests/README +++ /dev/null @@ -1,27 +0,0 @@ -Copyright (c) 2012-2015, The Regents of the University of California (Regents). -All Rights Reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: -1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. -3. Neither the name of the Regents nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - -IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING -OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS -BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED -HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE -MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - -The tests in this directory were built from -https://github.com/riscv/riscv-tools commit 84e9d5bf515908d15215cd8ee5b5beb6f7519491 . diff --git a/test/riscv/tests/disabled/rv64mi-p-sbreak.dump b/test/riscv/tests/disabled/rv64mi-p-sbreak.dump deleted file mode 100644 index 8e03511c..00000000 --- a/test/riscv/tests/disabled/rv64mi-p-sbreak.dump +++ /dev/null @@ -1,130 +0,0 @@ - -rv64mi-p-sbreak: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 00000f17 auipc t5,0x0 - 80000024: 118f0f13 addi t5,t5,280 # 80000138 - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00002537 lui a0,0x2 - 800000ec: 8005051b addiw a0,a0,-2048 - 800000f0: 30052073 csrs mstatus,a0 - 800000f4: 00000297 auipc t0,0x0 - 800000f8: 01428293 addi t0,t0,20 # 80000108 - 800000fc: 34129073 csrw mepc,t0 - 80000100: f1402573 csrr a0,mhartid - 80000104: 30200073 mret - 80000108: 00200193 li gp,2 - -000000008000010c : - 8000010c: 00100073 ebreak - 80000110: 0080006f j 80000118 - 80000114: 00301c63 bne zero,gp,8000012c - -0000000080000118 : - 80000118: 0ff0000f fence - 8000011c: 00018063 beqz gp,8000011c - 80000120: 00119193 slli gp,gp,0x1 - 80000124: 0011e193 ori gp,gp,1 - 80000128: 00000073 ecall - -000000008000012c : - 8000012c: 0ff0000f fence - 80000130: 00100193 li gp,1 - 80000134: 00000073 ecall - -0000000080000138 : - 80000138: 00300313 li t1,3 - 8000013c: 342022f3 csrr t0,mcause - 80000140: fc629ce3 bne t0,t1,80000118 - 80000144: 00000317 auipc t1,0x0 - 80000148: fc830313 addi t1,t1,-56 # 8000010c - 8000014c: 341022f3 csrr t0,mepc - 80000150: fc6294e3 bne t0,t1,80000118 - 80000154: fd9ff06f j 8000012c - 80000158: c0001073 unimp - 8000015c: 0000 unimp - 8000015e: 0000 unimp - 80000160: 0000 unimp - 80000162: 0000 unimp - 80000164: 0000 unimp - 80000166: 0000 unimp - 80000168: 0000 unimp - 8000016a: 0000 unimp - 8000016c: 0000 unimp - 8000016e: 0000 unimp - 80000170: 0000 unimp - 80000172: 0000 unimp - 80000174: 0000 unimp - 80000176: 0000 unimp - 80000178: 0000 unimp - 8000017a: 0000 unimp - 8000017c: 0000 unimp - 8000017e: 0000 unimp - 80000180: 0000 unimp - 80000182: 0000 unimp diff --git a/test/riscv/tests/disabled/rv64si-p-sbreak.dump b/test/riscv/tests/disabled/rv64si-p-sbreak.dump deleted file mode 100644 index e981c549..00000000 --- a/test/riscv/tests/disabled/rv64si-p-sbreak.dump +++ /dev/null @@ -1,128 +0,0 @@ - -rv64si-p-sbreak: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 00000297 auipc t0,0x0 - 800000c4: 08028293 addi t0,t0,128 # 80000140 - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00001537 lui a0,0x1 - 800000ec: 8005051b addiw a0,a0,-2048 - 800000f0: 30052073 csrs mstatus,a0 - 800000f4: 02200513 li a0,34 - 800000f8: 30352073 csrs mideleg,a0 - 800000fc: 00000297 auipc t0,0x0 - 80000100: 01428293 addi t0,t0,20 # 80000110 - 80000104: 34129073 csrw mepc,t0 - 80000108: f1402573 csrr a0,mhartid - 8000010c: 30200073 mret - 80000110: 00200193 li gp,2 - -0000000080000114 : - 80000114: 00100073 ebreak - 80000118: 0080006f j 80000120 - 8000011c: 00301c63 bne zero,gp,80000134 - -0000000080000120 : - 80000120: 0ff0000f fence - 80000124: 00018063 beqz gp,80000124 - 80000128: 00119193 slli gp,gp,0x1 - 8000012c: 0011e193 ori gp,gp,1 - 80000130: 00000073 ecall - -0000000080000134 : - 80000134: 0ff0000f fence - 80000138: 00100193 li gp,1 - 8000013c: 00000073 ecall - -0000000080000140 : - 80000140: 00300313 li t1,3 - 80000144: 142022f3 csrr t0,scause - 80000148: fc629ce3 bne t0,t1,80000120 - 8000014c: 00000317 auipc t1,0x0 - 80000150: fc830313 addi t1,t1,-56 # 80000114 - 80000154: 141022f3 csrr t0,sepc - 80000158: fc6294e3 bne t0,t1,80000120 - 8000015c: fd9ff06f j 80000134 - 80000160: c0001073 unimp - 80000164: 0000 unimp - 80000166: 0000 unimp - 80000168: 0000 unimp - 8000016a: 0000 unimp - 8000016c: 0000 unimp - 8000016e: 0000 unimp - 80000170: 0000 unimp - 80000172: 0000 unimp - 80000174: 0000 unimp - 80000176: 0000 unimp - 80000178: 0000 unimp - 8000017a: 0000 unimp - 8000017c: 0000 unimp - 8000017e: 0000 unimp - 80000180: 0000 unimp - 80000182: 0000 unimp diff --git a/test/riscv/tests/disabled/rv64ua-p-lrsc.dump b/test/riscv/tests/disabled/rv64ua-p-lrsc.dump deleted file mode 100644 index 4aec511e..00000000 --- a/test/riscv/tests/disabled/rv64ua-p-lrsc.dump +++ /dev/null @@ -1,178 +0,0 @@ - -rv64ua-p-lrsc: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - 800000fc: 00002517 auipc a0,0x2 - 80000100: f0450513 addi a0,a0,-252 # 80002000 - 80000104: 00100593 li a1,1 - 80000108: 00b5262f amoadd.w a2,a1,(a0) - 8000010c: 00100693 li a3,1 - 80000110: fed67ee3 bleu a3,a2,8000010c - 80000114: 00052583 lw a1,0(a0) - 80000118: fed5eee3 bltu a1,a3,80000114 - -000000008000011c : - 8000011c: 00002517 auipc a0,0x2 - 80000120: eec50513 addi a0,a0,-276 # 80002008 - 80000124: 1805272f sc.w a4,zero,(a0) - 80000128: 00100e93 li t4,1 - 8000012c: 00200193 li gp,2 - 80000130: 09d71863 bne a4,t4,800001c0 - -0000000080000134 : - 80000134: 00002517 auipc a0,0x2 - 80000138: ed450513 addi a0,a0,-300 # 80002008 - 8000013c: 40050593 addi a1,a0,1024 - 80000140: 1005a5af lr.w a1,(a1) - 80000144: 18b5272f sc.w a4,a1,(a0) - 80000148: 00100e93 li t4,1 - 8000014c: 00300193 li gp,3 - 80000150: 07d71863 bne a4,t4,800001c0 - 80000154: 00002517 auipc a0,0x2 - 80000158: eb450513 addi a0,a0,-332 # 80002008 - 8000015c: 40000593 li a1,1024 - 80000160: 00160613 addi a2,a2,1 - 80000164: 1005272f lr.w a4,(a0) - 80000168: 00c70733 add a4,a4,a2 - 8000016c: 18e5272f sc.w a4,a4,(a0) - 80000170: fe071ae3 bnez a4,80000164 - 80000174: fff58593 addi a1,a1,-1 - 80000178: fe0596e3 bnez a1,80000164 - 8000017c: 00002517 auipc a0,0x2 - 80000180: e8850513 addi a0,a0,-376 # 80002004 - 80000184: 00100593 li a1,1 - 80000188: 00b5202f amoadd.w zero,a1,(a0) - 8000018c: 00052583 lw a1,0(a0) - 80000190: fed5cee3 blt a1,a3,8000018c - 80000194: 0ff0000f fence - -0000000080000198 : - 80000198: 00002517 auipc a0,0x2 - 8000019c: e7052503 lw a0,-400(a0) # 80002008 - 800001a0: 00969593 slli a1,a3,0x9 - 800001a4: 40b50533 sub a0,a0,a1 - 800001a8: fff68693 addi a3,a3,-1 - 800001ac: fe06dce3 bgez a3,800001a4 - 800001b0: 00000e93 li t4,0 - 800001b4: 00400193 li gp,4 - 800001b8: 01d51463 bne a0,t4,800001c0 - 800001bc: 00301c63 bne zero,gp,800001d4 - -00000000800001c0 : - 800001c0: 0ff0000f fence - 800001c4: 00018063 beqz gp,800001c4 - 800001c8: 00119193 slli gp,gp,0x1 - 800001cc: 0011e193 ori gp,gp,1 - 800001d0: 00000073 ecall - -00000000800001d4 : - 800001d4: 0ff0000f fence - 800001d8: 00100193 li gp,1 - 800001dc: 00000073 ecall - 800001e0: c0001073 unimp - 800001e4: 0000 unimp - 800001e6: 0000 unimp - 800001e8: 0000 unimp - 800001ea: 0000 unimp - 800001ec: 0000 unimp - 800001ee: 0000 unimp - 800001f0: 0000 unimp - 800001f2: 0000 unimp - 800001f4: 0000 unimp - 800001f6: 0000 unimp - 800001f8: 0000 unimp - 800001fa: 0000 unimp - 800001fc: 0000 unimp - 800001fe: 0000 unimp - 80000200: 0000 unimp - 80000202: 0000 unimp - -Disassembly of section .data: - -0000000080002000 : - 80002000: 0000 unimp - 80002002: 0000 unimp - -0000000080002004 : - 80002004: 0000 unimp - 80002006: 0000 unimp - -0000000080002008 : - 80002008: 0000 unimp - 8000200a: 0000 unimp - 8000200c: 0000 unimp - 8000200e: 0000 unimp diff --git a/test/riscv/tests/disabled/rv64ua-p-lrsc.elf b/test/riscv/tests/disabled/rv64ua-p-lrsc.elf deleted file mode 100644 index bff66644..00000000 Binary files a/test/riscv/tests/disabled/rv64ua-p-lrsc.elf and /dev/null differ diff --git a/test/riscv/tests/rv64mi-p-access.dump b/test/riscv/tests/rv64mi-p-access.dump deleted file mode 100644 index 5b35e596..00000000 --- a/test/riscv/tests/rv64mi-p-access.dump +++ /dev/null @@ -1,142 +0,0 @@ - -rv64mi-p-access: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 00000f17 auipc t5,0x0 - 80000024: 158f0f13 addi t5,t5,344 # 80000178 - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00002537 lui a0,0x2 - 800000ec: 8005051b addiw a0,a0,-2048 - 800000f0: 30052073 csrs mstatus,a0 - 800000f4: 00000297 auipc t0,0x0 - 800000f8: 01428293 addi t0,t0,20 # 80000108 - 800000fc: 34129073 csrw mepc,t0 - 80000100: f1402573 csrr a0,mhartid - 80000104: 30200073 mret - 80000108: 00000397 auipc t2,0x0 - 8000010c: 05038393 addi t2,t2,80 # 80000158 - 80000110: fff0029b addiw t0,zero,-1 - 80000114: 03f29293 slli t0,t0,0x3f - 80000118: 0072c2b3 xor t0,t0,t2 - 8000011c: 00200193 li gp,2 - 80000120: 00100313 li t1,1 - 80000124: 00000e17 auipc t3,0x0 - 80000128: 010e0e13 addi t3,t3,16 # 80000134 - 8000012c: 00000393 li t2,0 - 80000130: 000283e7 jalr t2,t0 - 80000134: 00300193 li gp,3 - 80000138: 00500313 li t1,5 - 8000013c: 00000e17 auipc t3,0x0 - 80000140: 014e0e13 addi t3,t3,20 # 80000150 - 80000144: 000e0393 mv t2,t3 - 80000148: 00028383 lb t2,0(t0) - 8000014c: 00c0006f j 80000158 - 80000150: 01c0006f j 8000016c - 80000154: 00301c63 bne zero,gp,8000016c - -0000000080000158 : - 80000158: 0ff0000f fence - 8000015c: 00018063 beqz gp,8000015c - 80000160: 00119193 slli gp,gp,0x1 - 80000164: 0011e193 ori gp,gp,1 - 80000168: 00000073 ecall - -000000008000016c : - 8000016c: 0ff0000f fence - 80000170: 00100193 li gp,1 - 80000174: 00000073 ecall - -0000000080000178 : - 80000178: 00200513 li a0,2 - 8000017c: 00a18863 beq gp,a0,8000018c - 80000180: 00300513 li a0,3 - 80000184: 00a18463 beq gp,a0,8000018c - 80000188: fd1ff06f j 80000158 - 8000018c: fdc396e3 bne t2,t3,80000158 - 80000190: 342023f3 csrr t2,mcause - 80000194: fc6392e3 bne t2,t1,80000158 - 80000198: 341e1073 csrw mepc,t3 - 8000019c: 30200073 mret - 800001a0: c0001073 unimp - 800001a4: 0000 unimp - 800001a6: 0000 unimp - 800001a8: 0000 unimp - 800001aa: 0000 unimp - 800001ac: 0000 unimp - 800001ae: 0000 unimp - 800001b0: 0000 unimp - 800001b2: 0000 unimp - 800001b4: 0000 unimp - 800001b6: 0000 unimp - 800001b8: 0000 unimp - 800001ba: 0000 unimp - 800001bc: 0000 unimp - 800001be: 0000 unimp - 800001c0: 0000 unimp - 800001c2: 0000 unimp diff --git a/test/riscv/tests/rv64mi-p-breakpoint.dump b/test/riscv/tests/rv64mi-p-breakpoint.dump deleted file mode 100644 index d882b10a..00000000 --- a/test/riscv/tests/rv64mi-p-breakpoint.dump +++ /dev/null @@ -1,207 +0,0 @@ - -rv64mi-p-breakpoint: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 00000f17 auipc t5,0x0 - 80000024: 210f0f13 addi t5,t5,528 # 80000230 - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00002537 lui a0,0x2 - 800000ec: 8005051b addiw a0,a0,-2048 - 800000f0: 30052073 csrs mstatus,a0 - 800000f4: 00000297 auipc t0,0x0 - 800000f8: 01428293 addi t0,t0,20 # 80000108 - 800000fc: 34129073 csrw mepc,t0 - 80000100: f1402573 csrr a0,mhartid - 80000104: 30200073 mret - 80000108: 00200193 li gp,2 - 8000010c: 7a001073 csrw tselect,zero - 80000110: 7a0025f3 csrr a1,tselect - 80000114: 10b01863 bne zero,a1,80000224 - 80000118: 7a102573 csrr a0,tdata1 - 8000011c: 03c55513 srli a0,a0,0x3c - 80000120: 00200593 li a1,2 - 80000124: 10b51063 bne a0,a1,80000224 - 80000128: 00000617 auipc a2,0x0 - 8000012c: 02060613 addi a2,a2,32 # 80000148 - 80000130: 7a261073 csrw tdata2,a2 - 80000134: 04400513 li a0,68 - 80000138: 7a151073 csrw tdata1,a0 - 8000013c: 7a1025f3 csrr a1,tdata1 - 80000140: 7ff5f593 andi a1,a1,2047 - 80000144: 00b51863 bne a0,a1,80000154 - 80000148: 0c000463 beqz zero,80000210 - 8000014c: 00300193 li gp,3 - 80000150: 00062503 lw a0,0(a2) - 80000154: 00400193 li gp,4 - 80000158: 04100513 li a0,65 - 8000015c: 7a151073 csrw tdata1,a0 - 80000160: 7a1025f3 csrr a1,tdata1 - 80000164: 7ff5f593 andi a1,a1,2047 - 80000168: 02b51063 bne a0,a1,80000188 - 8000016c: 00002617 auipc a2,0x2 - 80000170: e9460613 addi a2,a2,-364 # 80002000 - 80000174: 7a261073 csrw tdata2,a2 - 80000178: 00062603 lw a2,0(a2) - 8000017c: 08060a63 beqz a2,80000210 - 80000180: 00500193 li gp,5 - 80000184: 00062023 sw zero,0(a2) - 80000188: 00600193 li gp,6 - 8000018c: 04200513 li a0,66 - 80000190: 7a151073 csrw tdata1,a0 - 80000194: 7a1025f3 csrr a1,tdata1 - 80000198: 7ff5f593 andi a1,a1,2047 - 8000019c: 06b51863 bne a0,a1,8000020c - 800001a0: 00c62023 sw a2,0(a2) - 800001a4: 00700193 li gp,7 - 800001a8: 00062603 lw a2,0(a2) - 800001ac: 06061263 bnez a2,80000210 - 800001b0: 00100513 li a0,1 - 800001b4: 7a051073 csrw tselect,a0 - 800001b8: 7a0025f3 csrr a1,tselect - 800001bc: 06b51463 bne a0,a1,80000224 - 800001c0: 7a102573 csrr a0,tdata1 - 800001c4: 03c55513 srli a0,a0,0x3c - 800001c8: 00200593 li a1,2 - 800001cc: 04b51c63 bne a0,a1,80000224 - 800001d0: 04100513 li a0,65 - 800001d4: 7a151073 csrw tdata1,a0 - 800001d8: 00002697 auipc a3,0x2 - 800001dc: e2c68693 addi a3,a3,-468 # 80002004 - 800001e0: 7a269073 csrw tdata2,a3 - 800001e4: 00800193 li gp,8 - 800001e8: 0006a683 lw a3,0(a3) - 800001ec: 02068263 beqz a3,80000210 - 800001f0: 00a00193 li gp,10 - 800001f4: 00002617 auipc a2,0x2 - 800001f8: e0c60613 addi a2,a2,-500 # 80002000 - 800001fc: 00c62023 sw a2,0(a2) - 80000200: 00b00193 li gp,11 - 80000204: 00062603 lw a2,0(a2) - 80000208: 00061463 bnez a2,80000210 - 8000020c: 00301c63 bne zero,gp,80000224 - -0000000080000210 : - 80000210: 0ff0000f fence - 80000214: 00018063 beqz gp,80000214 - 80000218: 00119193 slli gp,gp,0x1 - 8000021c: 0011e193 ori gp,gp,1 - 80000220: 00000073 ecall - -0000000080000224 : - 80000224: 0ff0000f fence - 80000228: 00100193 li gp,1 - 8000022c: 00000073 ecall - -0000000080000230 : - 80000230: 0011f293 andi t0,gp,1 - 80000234: fc029ee3 bnez t0,80000210 - 80000238: 00300293 li t0,3 - 8000023c: 34202373 csrr t1,mcause - 80000240: fc6298e3 bne t0,t1,80000210 - 80000244: 341022f3 csrr t0,mepc - 80000248: 00428293 addi t0,t0,4 - 8000024c: 34129073 csrw mepc,t0 - 80000250: 30200073 mret - 80000254: c0001073 unimp - 80000258: 0000 unimp - 8000025a: 0000 unimp - 8000025c: 0000 unimp - 8000025e: 0000 unimp - 80000260: 0000 unimp - 80000262: 0000 unimp - 80000264: 0000 unimp - 80000266: 0000 unimp - 80000268: 0000 unimp - 8000026a: 0000 unimp - 8000026c: 0000 unimp - 8000026e: 0000 unimp - 80000270: 0000 unimp - 80000272: 0000 unimp - 80000274: 0000 unimp - 80000276: 0000 unimp - 80000278: 0000 unimp - 8000027a: 0000 unimp - 8000027c: 0000 unimp - 8000027e: 0000 unimp - 80000280: 0000 unimp - 80000282: 0000 unimp - -Disassembly of section .data: - -0000000080002000 : - 80002000: 0000 unimp - 80002002: 0000 unimp - -0000000080002004 : - 80002004: 0000 unimp - 80002006: 0000 unimp - 80002008: 0000 unimp - 8000200a: 0000 unimp - 8000200c: 0000 unimp - 8000200e: 0000 unimp diff --git a/test/riscv/tests/rv64mi-p-breakpoint.elf b/test/riscv/tests/rv64mi-p-breakpoint.elf deleted file mode 100644 index 04af6b26..00000000 Binary files a/test/riscv/tests/rv64mi-p-breakpoint.elf and /dev/null differ diff --git a/test/riscv/tests/rv64mi-p-csr.dump b/test/riscv/tests/rv64mi-p-csr.dump deleted file mode 100644 index e2ccda2f..00000000 --- a/test/riscv/tests/rv64mi-p-csr.dump +++ /dev/null @@ -1,287 +0,0 @@ - -rv64mi-p-csr: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 00000f17 auipc t5,0x0 - 80000024: 2a0f0f13 addi t5,t5,672 # 800002c0 - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00002537 lui a0,0x2 - 800000ec: 8005051b addiw a0,a0,-2048 - 800000f0: 30052073 csrs mstatus,a0 - 800000f4: 00000297 auipc t0,0x0 - 800000f8: 01428293 addi t0,t0,20 # 80000108 - 800000fc: 34129073 csrw mepc,t0 - 80000100: f1402573 csrr a0,mhartid - 80000104: 30200073 mret - 80000108: 000022b7 lui t0,0x2 - 8000010c: 8002829b addiw t0,t0,-2048 - 80000110: 3002b073 csrc mstatus,t0 - 80000114: 30002373 csrr t1,mstatus - 80000118: 0062f2b3 and t0,t0,t1 - 8000011c: 02029463 bnez t0,80000144 - -0000000080000120 : - 80000120: 30002573 csrr a0,mstatus - 80000124: 0030059b addiw a1,zero,3 - 80000128: 02059593 slli a1,a1,0x20 - 8000012c: 00b57533 and a0,a0,a1 - 80000130: 00100e9b addiw t4,zero,1 - 80000134: 021e9e93 slli t4,t4,0x21 - 80000138: 00d00193 li gp,13 - 8000013c: 17d51263 bne a0,t4,800002a0 - 80000140: 0200006f j 80000160 - -0000000080000144 : - 80000144: 30002573 csrr a0,mstatus - 80000148: 0030059b addiw a1,zero,3 - 8000014c: 02059593 slli a1,a1,0x20 - 80000150: 00b57533 and a0,a0,a1 - 80000154: 00000e93 li t4,0 - 80000158: 00e00193 li gp,14 - 8000015c: 15d51263 bne a0,t4,800002a0 - 80000160: 3401d073 csrwi mscratch,3 - -0000000080000164 : - 80000164: 34002573 csrr a0,mscratch - 80000168: 00300e93 li t4,3 - 8000016c: 00200193 li gp,2 - 80000170: 13d51863 bne a0,t4,800002a0 - -0000000080000174 : - 80000174: 3400f5f3 csrrci a1,mscratch,1 - 80000178: 00300e93 li t4,3 - 8000017c: 00300193 li gp,3 - 80000180: 13d59063 bne a1,t4,800002a0 - -0000000080000184 : - 80000184: 34026673 csrrsi a2,mscratch,4 - 80000188: 00200e93 li t4,2 - 8000018c: 00400193 li gp,4 - 80000190: 11d61863 bne a2,t4,800002a0 - -0000000080000194 : - 80000194: 340156f3 csrrwi a3,mscratch,2 - 80000198: 00600e93 li t4,6 - 8000019c: 00500193 li gp,5 - 800001a0: 11d69063 bne a3,t4,800002a0 - -00000000800001a4 : - 800001a4: 0bad2537 lui a0,0xbad2 - 800001a8: dea5051b addiw a0,a0,-534 - 800001ac: 340515f3 csrrw a1,mscratch,a0 - 800001b0: 00200e93 li t4,2 - 800001b4: 00600193 li gp,6 - 800001b8: 0fd59463 bne a1,t4,800002a0 - -00000000800001bc : - 800001bc: 00002537 lui a0,0x2 - 800001c0: dea5051b addiw a0,a0,-534 - 800001c4: 34053573 csrrc a0,mscratch,a0 - 800001c8: 0bad2eb7 lui t4,0xbad2 - 800001cc: deae8e9b addiw t4,t4,-534 - 800001d0: 00700193 li gp,7 - 800001d4: 0dd51663 bne a0,t4,800002a0 - -00000000800001d8 : - 800001d8: 0000c537 lui a0,0xc - 800001dc: eef5051b addiw a0,a0,-273 - 800001e0: 34052573 csrrs a0,mscratch,a0 - 800001e4: 0bad0eb7 lui t4,0xbad0 - 800001e8: 00800193 li gp,8 - 800001ec: 0bd51a63 bne a0,t4,800002a0 - -00000000800001f0 : - 800001f0: 34002573 csrr a0,mscratch - 800001f4: 0badceb7 lui t4,0xbadc - 800001f8: eefe8e9b addiw t4,t4,-273 - 800001fc: 00900193 li gp,9 - 80000200: 0bd51063 bne a0,t4,800002a0 - 80000204: 30102573 csrr a0,misa - 80000208: 02057513 andi a0,a0,32 - 8000020c: 02050863 beqz a0,8000023c - 80000210: 000065b7 lui a1,0x6 - 80000214: 3005a073 csrs mstatus,a1 - 80000218: f0000053 fmv.w.x ft0,zero - 8000021c: 3005b073 csrc mstatus,a1 - 80000220: 00002597 auipc a1,0x2 - 80000224: de058593 addi a1,a1,-544 # 80002000 - -0000000080000228 : - 80000228: 0005a027 fsw ft0,0(a1) - 8000022c: 0005a503 lw a0,0(a1) - 80000230: 00100e93 li t4,1 - 80000234: 00a00193 li gp,10 - 80000238: 07d51463 bne a0,t4,800002a0 - 8000023c: 30102573 csrr a0,misa - 80000240: 01455513 srli a0,a0,0x14 - 80000244: 00157513 andi a0,a0,1 - 80000248: 04050463 beqz a0,80000290 - 8000024c: 000022b7 lui t0,0x2 - 80000250: 8002829b addiw t0,t0,-2048 - 80000254: 3002b073 csrc mstatus,t0 - 80000258: 00000297 auipc t0,0x0 - 8000025c: 01028293 addi t0,t0,16 # 80000268 - 80000260: 34129073 csrw mepc,t0 - 80000264: 30200073 mret - -0000000080000268 : - 80000268: 0ff00513 li a0,255 - 8000026c: c0001573 csrrw a0,cycle,zero - 80000270: 0ff00e93 li t4,255 - 80000274: 00b00193 li gp,11 - 80000278: 03d51463 bne a0,t4,800002a0 - -000000008000027c : - 8000027c: 0ff00513 li a0,255 - 80000280: 30002573 csrr a0,mstatus - 80000284: 0ff00e93 li t4,255 - 80000288: 00c00193 li gp,12 - 8000028c: 01d51a63 bne a0,t4,800002a0 - -0000000080000290 : - 80000290: 0ff0000f fence - 80000294: 00100193 li gp,1 - 80000298: 00000073 ecall - 8000029c: 00301c63 bne zero,gp,800002b4 - -00000000800002a0 : - 800002a0: 0ff0000f fence - 800002a4: 00018063 beqz gp,800002a4 - 800002a8: 00119193 slli gp,gp,0x1 - 800002ac: 0011e193 ori gp,gp,1 - 800002b0: 00000073 ecall - -00000000800002b4 : - 800002b4: 0ff0000f fence - 800002b8: 00100193 li gp,1 - 800002bc: 00000073 ecall - -00000000800002c0 : - 800002c0: 00900293 li t0,9 - 800002c4: 0051e663 bltu gp,t0,800002d0 - 800002c8: 00b00293 li t0,11 - 800002cc: 0032fe63 bleu gp,t0,800002e8 - 800002d0: 342022f3 csrr t0,mcause - 800002d4: 00800313 li t1,8 - 800002d8: fc6294e3 bne t0,t1,800002a0 - 800002dc: 0ff0000f fence - 800002e0: 00100193 li gp,1 - 800002e4: 00000073 ecall - -00000000800002e8 : - 800002e8: 342022f3 csrr t0,mcause - 800002ec: 00200313 li t1,2 - 800002f0: fa6298e3 bne t0,t1,800002a0 - 800002f4: 341022f3 csrr t0,mepc - 800002f8: 00428293 addi t0,t0,4 - 800002fc: 34129073 csrw mepc,t0 - 80000300: 30200073 mret - 80000304: c0001073 unimp - 80000308: 0000 unimp - 8000030a: 0000 unimp - 8000030c: 0000 unimp - 8000030e: 0000 unimp - 80000310: 0000 unimp - 80000312: 0000 unimp - 80000314: 0000 unimp - 80000316: 0000 unimp - 80000318: 0000 unimp - 8000031a: 0000 unimp - 8000031c: 0000 unimp - 8000031e: 0000 unimp - 80000320: 0000 unimp - 80000322: 0000 unimp - 80000324: 0000 unimp - 80000326: 0000 unimp - 80000328: 0000 unimp - 8000032a: 0000 unimp - 8000032c: 0000 unimp - 8000032e: 0000 unimp - 80000330: 0000 unimp - 80000332: 0000 unimp - 80000334: 0000 unimp - 80000336: 0000 unimp - 80000338: 0000 unimp - 8000033a: 0000 unimp - 8000033c: 0000 unimp - 8000033e: 0000 unimp - 80000340: 0000 unimp - 80000342: 0000 unimp - -Disassembly of section .data: - -0000000080002000 : - 80002000: 0001 nop - 80002002: 0000 unimp - 80002004: 0000 unimp - 80002006: 0000 unimp - 80002008: 0000 unimp - 8000200a: 0000 unimp - 8000200c: 0000 unimp - 8000200e: 0000 unimp diff --git a/test/riscv/tests/rv64mi-p-csr.elf b/test/riscv/tests/rv64mi-p-csr.elf deleted file mode 100644 index d7c74bc2..00000000 Binary files a/test/riscv/tests/rv64mi-p-csr.elf and /dev/null differ diff --git a/test/riscv/tests/rv64mi-p-illegal.dump b/test/riscv/tests/rv64mi-p-illegal.dump deleted file mode 100644 index 56485c4a..00000000 --- a/test/riscv/tests/rv64mi-p-illegal.dump +++ /dev/null @@ -1,383 +0,0 @@ - -rv64mi-p-illegal: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 00000f17 auipc t5,0x0 - 80000024: 2e0f0f13 addi t5,t5,736 # 80000300 - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00002537 lui a0,0x2 - 800000ec: 8005051b addiw a0,a0,-2048 - 800000f0: 30052073 csrs mstatus,a0 - 800000f4: 00000297 auipc t0,0x0 - 800000f8: 01428293 addi t0,t0,20 # 80000108 - 800000fc: 34129073 csrw mepc,t0 - 80000100: f1402573 csrr a0,mhartid - 80000104: 30200073 mret - 80000108: 00200193 li gp,2 - -000000008000010c : - 8000010c: 0000 unimp - 8000010e: 0000 unimp - 80000110: 0f40006f j 80000204 - 80000114: 000022b7 lui t0,0x2 - 80000118: 8002829b addiw t0,t0,-2048 - 8000011c: 3002b073 csrc mstatus,t0 - 80000120: 00001337 lui t1,0x1 - 80000124: 8003031b addiw t1,t1,-2048 - 80000128: 30032073 csrs mstatus,t1 - 8000012c: 300023f3 csrr t2,mstatus - 80000130: 0053f3b3 and t2,t2,t0 - 80000134: 0e731263 bne t1,t2,80000218 - -0000000080000138 : - 80000138: 34415073 csrwi mip,2 - 8000013c: 30415073 csrwi mie,2 - 80000140: 00000297 auipc t0,0x0 - 80000144: 1c128293 addi t0,t0,449 # 80000301 - 80000148: 30529473 csrrw s0,mtvec,t0 - 8000014c: 305022f3 csrr t0,mtvec - 80000150: 0012f293 andi t0,t0,1 - 80000154: 00028663 beqz t0,80000160 - 80000158: 30046073 csrsi mstatus,8 - 8000015c: 0000006f j 8000015c - -0000000080000160 : - 80000160: 30541073 csrw mtvec,s0 - 80000164: 30315073 csrwi mideleg,2 - 80000168: 00000297 auipc t0,0x0 - 8000016c: 02828293 addi t0,t0,40 # 80000190 - 80000170: 34129073 csrw mepc,t0 - 80000174: 000022b7 lui t0,0x2 - 80000178: 8002829b addiw t0,t0,-2048 - 8000017c: 3002b073 csrc mstatus,t0 - 80000180: 00001337 lui t1,0x1 - 80000184: 8003031b addiw t1,t1,-2048 - 80000188: 30032073 csrs mstatus,t1 - 8000018c: 30200073 mret - 80000190: 10500073 wfi - -0000000080000194 : - 80000194: 0000 unimp - 80000196: 0000 unimp - 80000198: 06c0006f j 80000204 - -000000008000019c : - 8000019c: 10500073 wfi - 800001a0: 0640006f j 80000204 - 800001a4: 12000073 sfence.vma - 800001a8: 180022f3 csrr t0,satp - -00000000800001ac : - 800001ac: 0000 unimp - 800001ae: 0000 unimp - 800001b0: 0540006f j 80000204 - -00000000800001b4 : - 800001b4: 12000073 sfence.vma - 800001b8: 04c0006f j 80000204 - -00000000800001bc : - 800001bc: 180022f3 csrr t0,satp - 800001c0: 0440006f j 80000204 - 800001c4: 00000297 auipc t0,0x0 - 800001c8: 02028293 addi t0,t0,32 # 800001e4 - 800001cc: 14129073 csrw sepc,t0 - 800001d0: 10000293 li t0,256 - 800001d4: 1002a073 csrs sstatus,t0 - 800001d8: 02000293 li t0,32 - 800001dc: 1002b073 csrc sstatus,t0 - 800001e0: 10200073 sret - -00000000800001e4 : - 800001e4: 0000 unimp - 800001e6: 0000 unimp - 800001e8: 01c0006f j 80000204 - 800001ec: 00000297 auipc t0,0x0 - 800001f0: 01028293 addi t0,t0,16 # 800001fc - 800001f4: 14129073 csrw sepc,t0 - -00000000800001f8 : - 800001f8: 10200073 sret - 800001fc: 0080006f j 80000204 - 80000200: 00301c63 bne zero,gp,80000218 - -0000000080000204 : - 80000204: 0ff0000f fence - 80000208: 00018063 beqz gp,80000208 - 8000020c: 00119193 slli gp,gp,0x1 - 80000210: 0011e193 ori gp,gp,1 - 80000214: 00000073 ecall - -0000000080000218 : - 80000218: 0ff0000f fence - 8000021c: 00100193 li gp,1 - 80000220: 00000073 ecall - 80000224: 00000013 nop - 80000228: 00000013 nop - 8000022c: 00000013 nop - 80000230: 00000013 nop - 80000234: 00000013 nop - 80000238: 00000013 nop - 8000023c: 00000013 nop - 80000240: 00000013 nop - 80000244: 00000013 nop - 80000248: 00000013 nop - 8000024c: 00000013 nop - 80000250: 00000013 nop - 80000254: 00000013 nop - 80000258: 00000013 nop - 8000025c: 00000013 nop - 80000260: 00000013 nop - 80000264: 00000013 nop - 80000268: 00000013 nop - 8000026c: 00000013 nop - 80000270: 00000013 nop - 80000274: 00000013 nop - 80000278: 00000013 nop - 8000027c: 00000013 nop - 80000280: 00000013 nop - 80000284: 00000013 nop - 80000288: 00000013 nop - 8000028c: 00000013 nop - 80000290: 00000013 nop - 80000294: 00000013 nop - 80000298: 00000013 nop - 8000029c: 00000013 nop - 800002a0: 00000013 nop - 800002a4: 00000013 nop - 800002a8: 00000013 nop - 800002ac: 00000013 nop - 800002b0: 00000013 nop - 800002b4: 00000013 nop - 800002b8: 00000013 nop - 800002bc: 00000013 nop - 800002c0: 00000013 nop - 800002c4: 00000013 nop - 800002c8: 00000013 nop - 800002cc: 00000013 nop - 800002d0: 00000013 nop - 800002d4: 00000013 nop - 800002d8: 00000013 nop - 800002dc: 00000013 nop - 800002e0: 00000013 nop - 800002e4: 00000013 nop - 800002e8: 00000013 nop - 800002ec: 00000013 nop - 800002f0: 00000013 nop - 800002f4: 00000013 nop - 800002f8: 00000013 nop - 800002fc: 00000013 nop - -0000000080000300 : - 80000300: 0400006f j 80000340 - 80000304: e5dff06f j 80000160 - 80000308: efdff06f j 80000204 - 8000030c: ef9ff06f j 80000204 - 80000310: ef5ff06f j 80000204 - 80000314: ef1ff06f j 80000204 - 80000318: eedff06f j 80000204 - 8000031c: ee9ff06f j 80000204 - 80000320: ee5ff06f j 80000204 - 80000324: ee1ff06f j 80000204 - 80000328: eddff06f j 80000204 - 8000032c: ed9ff06f j 80000204 - 80000330: ed5ff06f j 80000204 - 80000334: ed1ff06f j 80000204 - 80000338: ecdff06f j 80000204 - 8000033c: ec9ff06f j 80000204 - -0000000080000340 : - 80000340: 00200313 li t1,2 - 80000344: 342022f3 csrr t0,mcause - 80000348: ea629ee3 bne t0,t1,80000204 - 8000034c: 341022f3 csrr t0,mepc - 80000350: 343023f3 csrr t2,mbadaddr - 80000354: 00038c63 beqz t2,8000036c - 80000358: 0002de03 lhu t3,0(t0) - 8000035c: 0022de83 lhu t4,2(t0) - 80000360: 010e9e93 slli t4,t4,0x10 - 80000364: 01de6e33 or t3,t3,t4 - 80000368: e9c39ee3 bne t2,t3,80000204 - 8000036c: 00000317 auipc t1,0x0 - 80000370: da030313 addi t1,t1,-608 # 8000010c - 80000374: 04628e63 beq t0,t1,800003d0 - 80000378: 00000317 auipc t1,0x0 - 8000037c: e1c30313 addi t1,t1,-484 # 80000194 - 80000380: 04628e63 beq t0,t1,800003dc - 80000384: 00000317 auipc t1,0x0 - 80000388: e1830313 addi t1,t1,-488 # 8000019c - 8000038c: 04628263 beq t0,t1,800003d0 - 80000390: 00000317 auipc t1,0x0 - 80000394: e1c30313 addi t1,t1,-484 # 800001ac - 80000398: 04628863 beq t0,t1,800003e8 - 8000039c: 00000317 auipc t1,0x0 - 800003a0: e1830313 addi t1,t1,-488 # 800001b4 - 800003a4: 02628663 beq t0,t1,800003d0 - 800003a8: 00000317 auipc t1,0x0 - 800003ac: e1430313 addi t1,t1,-492 # 800001bc - 800003b0: 02628063 beq t0,t1,800003d0 - 800003b4: 00000317 auipc t1,0x0 - 800003b8: e3030313 addi t1,t1,-464 # 800001e4 - 800003bc: 02628c63 beq t0,t1,800003f4 - 800003c0: 00000317 auipc t1,0x0 - 800003c4: e3830313 addi t1,t1,-456 # 800001f8 - 800003c8: 02628c63 beq t0,t1,80000400 - 800003cc: e39ff06f j 80000204 - 800003d0: 00828293 addi t0,t0,8 - 800003d4: 34129073 csrw mepc,t0 - 800003d8: 30200073 mret - 800003dc: 00200337 lui t1,0x200 - 800003e0: 30032073 csrs mstatus,t1 - 800003e4: fedff06f j 800003d0 - 800003e8: 00100337 lui t1,0x100 - 800003ec: 30032073 csrs mstatus,t1 - 800003f0: fe1ff06f j 800003d0 - 800003f4: 00400337 lui t1,0x400 - 800003f8: 30032073 csrs mstatus,t1 - 800003fc: fd5ff06f j 800003d0 - 80000400: fd1ff06f j 800003d0 - 80000404: c0001073 unimp - 80000408: 0000 unimp - 8000040a: 0000 unimp - 8000040c: 0000 unimp - 8000040e: 0000 unimp - 80000410: 0000 unimp - 80000412: 0000 unimp - 80000414: 0000 unimp - 80000416: 0000 unimp - 80000418: 0000 unimp - 8000041a: 0000 unimp - 8000041c: 0000 unimp - 8000041e: 0000 unimp - 80000420: 0000 unimp - 80000422: 0000 unimp - 80000424: 0000 unimp - 80000426: 0000 unimp - 80000428: 0000 unimp - 8000042a: 0000 unimp - 8000042c: 0000 unimp - 8000042e: 0000 unimp - 80000430: 0000 unimp - 80000432: 0000 unimp - 80000434: 0000 unimp - 80000436: 0000 unimp - 80000438: 0000 unimp - 8000043a: 0000 unimp - 8000043c: 0000 unimp - 8000043e: 0000 unimp - 80000440: 0000 unimp - 80000442: 0000 unimp - 80000444: 0000 unimp - 80000446: 0000 unimp - 80000448: 0000 unimp - 8000044a: 0000 unimp - 8000044c: 0000 unimp - 8000044e: 0000 unimp - 80000450: 0000 unimp - 80000452: 0000 unimp - 80000454: 0000 unimp - 80000456: 0000 unimp - 80000458: 0000 unimp - 8000045a: 0000 unimp - 8000045c: 0000 unimp - 8000045e: 0000 unimp - 80000460: 0000 unimp - 80000462: 0000 unimp - 80000464: 0000 unimp - 80000466: 0000 unimp - 80000468: 0000 unimp - 8000046a: 0000 unimp - 8000046c: 0000 unimp - 8000046e: 0000 unimp - 80000470: 0000 unimp - 80000472: 0000 unimp - 80000474: 0000 unimp - 80000476: 0000 unimp - 80000478: 0000 unimp - 8000047a: 0000 unimp - 8000047c: 0000 unimp - 8000047e: 0000 unimp - 80000480: 0000 unimp - 80000482: 0000 unimp - 80000484: 0000 unimp - 80000486: 0000 unimp - 80000488: 0000 unimp - 8000048a: 0000 unimp - 8000048c: 0000 unimp - 8000048e: 0000 unimp - 80000490: 0000 unimp - 80000492: 0000 unimp - 80000494: 0000 unimp - 80000496: 0000 unimp - 80000498: 0000 unimp - 8000049a: 0000 unimp - 8000049c: 0000 unimp - 8000049e: 0000 unimp - 800004a0: 0000 unimp - 800004a2: 0000 unimp diff --git a/test/riscv/tests/rv64mi-p-illegal.elf b/test/riscv/tests/rv64mi-p-illegal.elf deleted file mode 100644 index 7441498d..00000000 Binary files a/test/riscv/tests/rv64mi-p-illegal.elf and /dev/null differ diff --git a/test/riscv/tests/rv64mi-p-ma_addr.dump b/test/riscv/tests/rv64mi-p-ma_addr.dump deleted file mode 100644 index b5595679..00000000 --- a/test/riscv/tests/rv64mi-p-ma_addr.dump +++ /dev/null @@ -1,563 +0,0 @@ - -rv64mi-p-ma_addr: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 00000f17 auipc t5,0x0 - 80000024: 5e8f0f13 addi t5,t5,1512 # 80000608 - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00002537 lui a0,0x2 - 800000ec: 8005051b addiw a0,a0,-2048 - 800000f0: 30052073 csrs mstatus,a0 - 800000f4: 00000297 auipc t0,0x0 - 800000f8: 01428293 addi t0,t0,20 # 80000108 - 800000fc: 34129073 csrw mepc,t0 - 80000100: f1402573 csrr a0,mhartid - 80000104: 30200073 mret - 80000108: 00002417 auipc s0,0x2 - 8000010c: ef840413 addi s0,s0,-264 # 80002000 - 80000110: 00400493 li s1,4 - 80000114: 00200193 li gp,2 - 80000118: 00000397 auipc t2,0x0 - 8000011c: 01c38393 addi t2,t2,28 # 80000134 - 80000120: 00140313 addi t1,s0,1 - 80000124: 00141303 lh t1,1(s0) - 80000128: ffffc3b7 lui t2,0xffffc - 8000012c: bcc3839b addiw t2,t2,-1076 - 80000130: 4a731c63 bne t1,t2,800005e8 - 80000134: 00300193 li gp,3 - 80000138: 00000397 auipc t2,0x0 - 8000013c: 01c38393 addi t2,t2,28 # 80000154 - 80000140: 00140313 addi t1,s0,1 - 80000144: 00145303 lhu t1,1(s0) - 80000148: 0000c3b7 lui t2,0xc - 8000014c: bcc3839b addiw t2,t2,-1076 - 80000150: 48731c63 bne t1,t2,800005e8 - 80000154: 00400193 li gp,4 - 80000158: 00000397 auipc t2,0x0 - 8000015c: 01c38393 addi t2,t2,28 # 80000174 - 80000160: 00140313 addi t1,s0,1 - 80000164: 00142303 lw t1,1(s0) - 80000168: 99aac3b7 lui t2,0x99aac - 8000016c: bcc3839b addiw t2,t2,-1076 - 80000170: 46731c63 bne t1,t2,800005e8 - 80000174: 00500193 li gp,5 - 80000178: 00000397 auipc t2,0x0 - 8000017c: 01c38393 addi t2,t2,28 # 80000194 - 80000180: 00240313 addi t1,s0,2 - 80000184: 00242303 lw t1,2(s0) - 80000188: 8899b3b7 lui t2,0x8899b - 8000018c: abb3839b addiw t2,t2,-1349 - 80000190: 44731c63 bne t1,t2,800005e8 - 80000194: 00600193 li gp,6 - 80000198: 00000397 auipc t2,0x0 - 8000019c: 01c38393 addi t2,t2,28 # 800001b4 - 800001a0: 00340313 addi t1,s0,3 - 800001a4: 00342303 lw t1,3(s0) - 800001a8: 7788a3b7 lui t2,0x7788a - 800001ac: 9aa3839b addiw t2,t2,-1622 - 800001b0: 42731c63 bne t1,t2,800005e8 - 800001b4: 00700193 li gp,7 - 800001b8: 00000397 auipc t2,0x0 - 800001bc: 02438393 addi t2,t2,36 # 800001dc - 800001c0: 00140313 addi t1,s0,1 - 800001c4: 00146303 lwu t1,1(s0) - 800001c8: 000263b7 lui t2,0x26 - 800001cc: 6ab3839b addiw t2,t2,1707 - 800001d0: 00e39393 slli t2,t2,0xe - 800001d4: bcc38393 addi t2,t2,-1076 # 25bcc <_start-0x7ffda434> - 800001d8: 40731863 bne t1,t2,800005e8 - 800001dc: 00800193 li gp,8 - 800001e0: 00000397 auipc t2,0x0 - 800001e4: 02438393 addi t2,t2,36 # 80000204 - 800001e8: 00240313 addi t1,s0,2 - 800001ec: 00246303 lwu t1,2(s0) - 800001f0: 000893b7 lui t2,0x89 - 800001f4: 99b3839b addiw t2,t2,-1637 - 800001f8: 00c39393 slli t2,t2,0xc - 800001fc: abb38393 addi t2,t2,-1349 # 88abb <_start-0x7ff77545> - 80000200: 3e731463 bne t1,t2,800005e8 - 80000204: 00900193 li gp,9 - 80000208: 00000397 auipc t2,0x0 - 8000020c: 01c38393 addi t2,t2,28 # 80000224 - 80000210: 00340313 addi t1,s0,3 - 80000214: 00346303 lwu t1,3(s0) - 80000218: 7788a3b7 lui t2,0x7788a - 8000021c: 9aa3839b addiw t2,t2,-1622 - 80000220: 3c731463 bne t1,t2,800005e8 - 80000224: 00a00193 li gp,10 - 80000228: 00000397 auipc t2,0x0 - 8000022c: 03438393 addi t2,t2,52 # 8000025c - 80000230: 00140313 addi t1,s0,1 - 80000234: 00143303 ld t1,1(s0) - 80000238: 00aad3b7 lui t2,0xaad - 8000023c: cef3839b addiw t2,t2,-785 - 80000240: 00c39393 slli t2,t2,0xc - 80000244: 11338393 addi t2,t2,275 # aad113 <_start-0x7f552eed> - 80000248: 00d39393 slli t2,t2,0xd - 8000024c: 6ab38393 addi t2,t2,1707 - 80000250: 00e39393 slli t2,t2,0xe - 80000254: bcc38393 addi t2,t2,-1076 - 80000258: 38731863 bne t1,t2,800005e8 - 8000025c: 00b00193 li gp,11 - 80000260: 00000397 auipc t2,0x0 - 80000264: 03438393 addi t2,t2,52 # 80000294 - 80000268: 00240313 addi t1,s0,2 - 8000026c: 00243303 ld t1,2(s0) - 80000270: 044553b7 lui t2,0x4455 - 80000274: 6673839b addiw t2,t2,1639 - 80000278: 00c39393 slli t2,t2,0xc - 8000027c: 78938393 addi t2,t2,1929 # 4455789 <_start-0x7bbaa877> - 80000280: 00c39393 slli t2,t2,0xc - 80000284: 99b38393 addi t2,t2,-1637 - 80000288: 00c39393 slli t2,t2,0xc - 8000028c: abb38393 addi t2,t2,-1349 - 80000290: 34731c63 bne t1,t2,800005e8 - 80000294: 00c00193 li gp,12 - 80000298: 00000397 auipc t2,0x0 - 8000029c: 03438393 addi t2,t2,52 # 800002cc - 800002a0: 00340313 addi t1,s0,3 - 800002a4: 00343303 ld t1,3(s0) - 800002a8: 006693b7 lui t2,0x669 - 800002ac: 8ab3839b addiw t2,t2,-1877 - 800002b0: 00c39393 slli t2,t2,0xc - 800002b4: ccf38393 addi t2,t2,-817 # 668ccf <_start-0x7f997331> - 800002b8: 00e39393 slli t2,t2,0xe - 800002bc: c4538393 addi t2,t2,-955 - 800002c0: 00d39393 slli t2,t2,0xd - 800002c4: 9aa38393 addi t2,t2,-1622 - 800002c8: 32731063 bne t1,t2,800005e8 - 800002cc: 00d00193 li gp,13 - 800002d0: 00000397 auipc t2,0x0 - 800002d4: 03438393 addi t2,t2,52 # 80000304 - 800002d8: 00440313 addi t1,s0,4 - 800002dc: 00443303 ld t1,4(s0) - 800002e0: 0111a3b7 lui t2,0x111a - 800002e4: a233839b addiw t2,t2,-1501 - 800002e8: 00c39393 slli t2,t2,0xc - 800002ec: ab338393 addi t2,t2,-1357 # 1119ab3 <_start-0x7eee654d> - 800002f0: 00d39393 slli t2,t2,0xd - 800002f4: 77938393 addi t2,t2,1913 - 800002f8: 00c39393 slli t2,t2,0xc - 800002fc: 89938393 addi t2,t2,-1895 - 80000300: 2e731463 bne t1,t2,800005e8 - 80000304: 00e00193 li gp,14 - 80000308: 00000397 auipc t2,0x0 - 8000030c: 03438393 addi t2,t2,52 # 8000033c - 80000310: 00540313 addi t1,s0,5 - 80000314: 00543303 ld t1,5(s0) - 80000318: 004493b7 lui t2,0x449 - 8000031c: 8cd3839b addiw t2,t2,-1843 - 80000320: 00e39393 slli t2,t2,0xe - 80000324: 45538393 addi t2,t2,1109 # 449455 <_start-0x7fbb6bab> - 80000328: 00c39393 slli t2,t2,0xc - 8000032c: 66738393 addi t2,t2,1639 - 80000330: 00c39393 slli t2,t2,0xc - 80000334: 78838393 addi t2,t2,1928 - 80000338: 2a731863 bne t1,t2,800005e8 - 8000033c: 00f00193 li gp,15 - 80000340: 00000397 auipc t2,0x0 - 80000344: 03438393 addi t2,t2,52 # 80000374 - 80000348: 00640313 addi t1,s0,6 - 8000034c: 00643303 ld t1,6(s0) - 80000350: ffb843b7 lui t2,0xffb84 - 80000354: 4893839b addiw t2,t2,1161 - 80000358: 00c39393 slli t2,t2,0xc - 8000035c: cd138393 addi t2,t2,-815 # ffffffffffb83cd1 <_end+0xffffffff7fb81bc1> - 80000360: 00d39393 slli t2,t2,0xd - 80000364: 2ab38393 addi t2,t2,683 - 80000368: 00d39393 slli t2,t2,0xd - 8000036c: 67738393 addi t2,t2,1655 - 80000370: 26731c63 bne t1,t2,800005e8 - 80000374: 01000193 li gp,16 - 80000378: 00000397 auipc t2,0x0 - 8000037c: 02c38393 addi t2,t2,44 # 800003a4 - 80000380: 00740313 addi t1,s0,7 - 80000384: 00743303 ld t1,7(s0) - 80000388: ee1123b7 lui t2,0xee112 - 8000038c: 2333839b addiw t2,t2,563 - 80000390: 00c39393 slli t2,t2,0xc - 80000394: 44538393 addi t2,t2,1093 # ffffffffee112445 <_end+0xffffffff6e110335> - 80000398: 00c39393 slli t2,t2,0xc - 8000039c: 56638393 addi t2,t2,1382 - 800003a0: 24731463 bne t1,t2,800005e8 - 800003a4: 00600493 li s1,6 - 800003a8: 01600193 li gp,22 - 800003ac: 00000397 auipc t2,0x0 - 800003b0: 03038393 addi t2,t2,48 # 800003dc - 800003b4: 00140313 addi t1,s0,1 - 800003b8: 000410a3 sh zero,1(s0) - 800003bc: 00040303 lb t1,0(s0) - 800003c0: 22030463 beqz t1,800005e8 - 800003c4: 00340303 lb t1,3(s0) - 800003c8: 22030063 beqz t1,800005e8 - 800003cc: 00140303 lb t1,1(s0) - 800003d0: 20031c63 bnez t1,800005e8 - 800003d4: 00240303 lb t1,2(s0) - 800003d8: 20031863 bnez t1,800005e8 - 800003dc: 01700193 li gp,23 - 800003e0: 00000397 auipc t2,0x0 - 800003e4: 03038393 addi t2,t2,48 # 80000410 - 800003e8: 00540313 addi t1,s0,5 - 800003ec: 000422a3 sw zero,5(s0) - 800003f0: 00440303 lb t1,4(s0) - 800003f4: 1e030a63 beqz t1,800005e8 - 800003f8: 00940303 lb t1,9(s0) - 800003fc: 1e030663 beqz t1,800005e8 - 80000400: 00540303 lb t1,5(s0) - 80000404: 1e031263 bnez t1,800005e8 - 80000408: 00840303 lb t1,8(s0) - 8000040c: 1c031e63 bnez t1,800005e8 - 80000410: 01800193 li gp,24 - 80000414: 00000397 auipc t2,0x0 - 80000418: 03038393 addi t2,t2,48 # 80000444 - 8000041c: 00a40313 addi t1,s0,10 - 80000420: 00042523 sw zero,10(s0) - 80000424: 00940303 lb t1,9(s0) - 80000428: 1c030063 beqz t1,800005e8 - 8000042c: 00e40303 lb t1,14(s0) - 80000430: 1a030c63 beqz t1,800005e8 - 80000434: 00a40303 lb t1,10(s0) - 80000438: 1a031863 bnez t1,800005e8 - 8000043c: 00d40303 lb t1,13(s0) - 80000440: 1a031463 bnez t1,800005e8 - 80000444: 01900193 li gp,25 - 80000448: 00000397 auipc t2,0x0 - 8000044c: 03038393 addi t2,t2,48 # 80000478 - 80000450: 00f40313 addi t1,s0,15 - 80000454: 000427a3 sw zero,15(s0) - 80000458: 00e40303 lb t1,14(s0) - 8000045c: 18030663 beqz t1,800005e8 - 80000460: 01340303 lb t1,19(s0) - 80000464: 18030263 beqz t1,800005e8 - 80000468: 00f40303 lb t1,15(s0) - 8000046c: 16031e63 bnez t1,800005e8 - 80000470: 01240303 lb t1,18(s0) - 80000474: 16031a63 bnez t1,800005e8 - 80000478: 01a00193 li gp,26 - 8000047c: 00000397 auipc t2,0x0 - 80000480: 03038393 addi t2,t2,48 # 800004ac - 80000484: 01940313 addi t1,s0,25 - 80000488: 00043ca3 sd zero,25(s0) - 8000048c: 01840303 lb t1,24(s0) - 80000490: 14030c63 beqz t1,800005e8 - 80000494: 02140303 lb t1,33(s0) - 80000498: 14030863 beqz t1,800005e8 - 8000049c: 01940303 lb t1,25(s0) - 800004a0: 14031463 bnez t1,800005e8 - 800004a4: 02040303 lb t1,32(s0) - 800004a8: 14031063 bnez t1,800005e8 - 800004ac: 01b00193 li gp,27 - 800004b0: 00000397 auipc t2,0x0 - 800004b4: 03038393 addi t2,t2,48 # 800004e0 - 800004b8: 02240313 addi t1,s0,34 - 800004bc: 02043123 sd zero,34(s0) - 800004c0: 02140303 lb t1,33(s0) - 800004c4: 12030263 beqz t1,800005e8 - 800004c8: 02a40303 lb t1,42(s0) - 800004cc: 10030e63 beqz t1,800005e8 - 800004d0: 02240303 lb t1,34(s0) - 800004d4: 10031a63 bnez t1,800005e8 - 800004d8: 02940303 lb t1,41(s0) - 800004dc: 10031663 bnez t1,800005e8 - 800004e0: 01c00193 li gp,28 - 800004e4: 00000397 auipc t2,0x0 - 800004e8: 03038393 addi t2,t2,48 # 80000514 - 800004ec: 02b40313 addi t1,s0,43 - 800004f0: 020435a3 sd zero,43(s0) - 800004f4: 02a40303 lb t1,42(s0) - 800004f8: 0e030863 beqz t1,800005e8 - 800004fc: 03340303 lb t1,51(s0) - 80000500: 0e030463 beqz t1,800005e8 - 80000504: 02b40303 lb t1,43(s0) - 80000508: 0e031063 bnez t1,800005e8 - 8000050c: 03240303 lb t1,50(s0) - 80000510: 0c031c63 bnez t1,800005e8 - 80000514: 01d00193 li gp,29 - 80000518: 00000397 auipc t2,0x0 - 8000051c: 03038393 addi t2,t2,48 # 80000548 - 80000520: 03440313 addi t1,s0,52 - 80000524: 02043a23 sd zero,52(s0) - 80000528: 03340303 lb t1,51(s0) - 8000052c: 0a030e63 beqz t1,800005e8 - 80000530: 03c40303 lb t1,60(s0) - 80000534: 0a030a63 beqz t1,800005e8 - 80000538: 03440303 lb t1,52(s0) - 8000053c: 0a031663 bnez t1,800005e8 - 80000540: 03b40303 lb t1,59(s0) - 80000544: 0a031263 bnez t1,800005e8 - 80000548: 01e00193 li gp,30 - 8000054c: 00000397 auipc t2,0x0 - 80000550: 03038393 addi t2,t2,48 # 8000057c - 80000554: 03d40313 addi t1,s0,61 - 80000558: 02043ea3 sd zero,61(s0) - 8000055c: 03c40303 lb t1,60(s0) - 80000560: 08030463 beqz t1,800005e8 - 80000564: 04540303 lb t1,69(s0) - 80000568: 08030063 beqz t1,800005e8 - 8000056c: 03d40303 lb t1,61(s0) - 80000570: 06031c63 bnez t1,800005e8 - 80000574: 04440303 lb t1,68(s0) - 80000578: 06031863 bnez t1,800005e8 - 8000057c: 01f00193 li gp,31 - 80000580: 00000397 auipc t2,0x0 - 80000584: 03038393 addi t2,t2,48 # 800005b0 - 80000588: 04640313 addi t1,s0,70 - 8000058c: 04043323 sd zero,70(s0) - 80000590: 04540303 lb t1,69(s0) - 80000594: 04030a63 beqz t1,800005e8 - 80000598: 04e40303 lb t1,78(s0) - 8000059c: 04030663 beqz t1,800005e8 - 800005a0: 04640303 lb t1,70(s0) - 800005a4: 04031263 bnez t1,800005e8 - 800005a8: 04d40303 lb t1,77(s0) - 800005ac: 02031e63 bnez t1,800005e8 - 800005b0: 02000193 li gp,32 - 800005b4: 00000397 auipc t2,0x0 - 800005b8: 03038393 addi t2,t2,48 # 800005e4 - 800005bc: 04f40313 addi t1,s0,79 - 800005c0: 040437a3 sd zero,79(s0) - 800005c4: 04e40303 lb t1,78(s0) - 800005c8: 02030063 beqz t1,800005e8 - 800005cc: 05740303 lb t1,87(s0) - 800005d0: 00030c63 beqz t1,800005e8 - 800005d4: 04f40303 lb t1,79(s0) - 800005d8: 00031863 bnez t1,800005e8 - 800005dc: 05640303 lb t1,86(s0) - 800005e0: 00031463 bnez t1,800005e8 - 800005e4: 00301c63 bne zero,gp,800005fc - -00000000800005e8 : - 800005e8: 0ff0000f fence - 800005ec: 00018063 beqz gp,800005ec - 800005f0: 00119193 slli gp,gp,0x1 - 800005f4: 0011e193 ori gp,gp,1 - 800005f8: 00000073 ecall - -00000000800005fc : - 800005fc: 0ff0000f fence - 80000600: 00100193 li gp,1 - 80000604: 00000073 ecall - -0000000080000608 : - 80000608: 342022f3 csrr t0,mcause - 8000060c: fc929ee3 bne t0,s1,800005e8 - 80000610: 343022f3 csrr t0,mbadaddr - 80000614: fc629ae3 bne t0,t1,800005e8 - 80000618: 00028283 lb t0,0(t0) - 8000061c: fc0286e3 beqz t0,800005e8 - 80000620: 34139073 csrw mepc,t2 - 80000624: 30200073 mret - 80000628: c0001073 unimp - 8000062c: 0000 unimp - 8000062e: 0000 unimp - 80000630: 0000 unimp - 80000632: 0000 unimp - 80000634: 0000 unimp - 80000636: 0000 unimp - 80000638: 0000 unimp - 8000063a: 0000 unimp - 8000063c: 0000 unimp - 8000063e: 0000 unimp - -Disassembly of section .data: - -0000000080002000 : - 80002000: ccdd beqz s1,800020be - 80002002: 8899aabb 0x8899aabb - 80002006: 44556677 0x44556677 - 8000200a: ee112233 0xee112233 - 8000200e: eeff 0xeeff - 80002010: 5050 lw a2,36(s0) - 80002012: 5050 lw a2,36(s0) - 80002014: 5050 lw a2,36(s0) - 80002016: 5050 lw a2,36(s0) - 80002018: 5050 lw a2,36(s0) - 8000201a: 5050 lw a2,36(s0) - 8000201c: 5050 lw a2,36(s0) - 8000201e: 5050 lw a2,36(s0) - 80002020: 5050 lw a2,36(s0) - 80002022: 5050 lw a2,36(s0) - 80002024: 5050 lw a2,36(s0) - 80002026: 5050 lw a2,36(s0) - 80002028: 5050 lw a2,36(s0) - 8000202a: 5050 lw a2,36(s0) - 8000202c: 5050 lw a2,36(s0) - 8000202e: 5050 lw a2,36(s0) - 80002030: 5050 lw a2,36(s0) - 80002032: 5050 lw a2,36(s0) - 80002034: 5050 lw a2,36(s0) - 80002036: 5050 lw a2,36(s0) - 80002038: 5050 lw a2,36(s0) - 8000203a: 5050 lw a2,36(s0) - 8000203c: 5050 lw a2,36(s0) - 8000203e: 5050 lw a2,36(s0) - 80002040: 5050 lw a2,36(s0) - 80002042: 5050 lw a2,36(s0) - 80002044: 5050 lw a2,36(s0) - 80002046: 5050 lw a2,36(s0) - 80002048: 5050 lw a2,36(s0) - 8000204a: 5050 lw a2,36(s0) - 8000204c: 5050 lw a2,36(s0) - 8000204e: 5050 lw a2,36(s0) - 80002050: 5050 lw a2,36(s0) - 80002052: 5050 lw a2,36(s0) - 80002054: 5050 lw a2,36(s0) - 80002056: 5050 lw a2,36(s0) - 80002058: 5050 lw a2,36(s0) - 8000205a: 5050 lw a2,36(s0) - 8000205c: 5050 lw a2,36(s0) - 8000205e: 5050 lw a2,36(s0) - 80002060: 5050 lw a2,36(s0) - 80002062: 5050 lw a2,36(s0) - 80002064: 5050 lw a2,36(s0) - 80002066: 5050 lw a2,36(s0) - 80002068: 5050 lw a2,36(s0) - 8000206a: 5050 lw a2,36(s0) - 8000206c: 5050 lw a2,36(s0) - 8000206e: 5050 lw a2,36(s0) - 80002070: 5050 lw a2,36(s0) - 80002072: 5050 lw a2,36(s0) - 80002074: 5050 lw a2,36(s0) - 80002076: 5050 lw a2,36(s0) - 80002078: 5050 lw a2,36(s0) - 8000207a: 5050 lw a2,36(s0) - 8000207c: 5050 lw a2,36(s0) - 8000207e: 5050 lw a2,36(s0) - 80002080: 5050 lw a2,36(s0) - 80002082: 5050 lw a2,36(s0) - 80002084: 5050 lw a2,36(s0) - 80002086: 5050 lw a2,36(s0) - 80002088: 5050 lw a2,36(s0) - 8000208a: 5050 lw a2,36(s0) - 8000208c: 5050 lw a2,36(s0) - 8000208e: 5050 lw a2,36(s0) - 80002090: 5050 lw a2,36(s0) - 80002092: 5050 lw a2,36(s0) - 80002094: 5050 lw a2,36(s0) - 80002096: 5050 lw a2,36(s0) - 80002098: 5050 lw a2,36(s0) - 8000209a: 5050 lw a2,36(s0) - 8000209c: 5050 lw a2,36(s0) - 8000209e: 5050 lw a2,36(s0) - 800020a0: 5050 lw a2,36(s0) - 800020a2: 5050 lw a2,36(s0) - 800020a4: 5050 lw a2,36(s0) - 800020a6: 5050 lw a2,36(s0) - 800020a8: 5050 lw a2,36(s0) - 800020aa: 5050 lw a2,36(s0) - 800020ac: 5050 lw a2,36(s0) - 800020ae: 5050 lw a2,36(s0) - 800020b0: 5050 lw a2,36(s0) - 800020b2: 5050 lw a2,36(s0) - 800020b4: 5050 lw a2,36(s0) - 800020b6: 5050 lw a2,36(s0) - 800020b8: 5050 lw a2,36(s0) - 800020ba: 5050 lw a2,36(s0) - 800020bc: 5050 lw a2,36(s0) - 800020be: 5050 lw a2,36(s0) - 800020c0: 5050 lw a2,36(s0) - 800020c2: 5050 lw a2,36(s0) - 800020c4: 5050 lw a2,36(s0) - 800020c6: 5050 lw a2,36(s0) - 800020c8: 5050 lw a2,36(s0) - 800020ca: 5050 lw a2,36(s0) - 800020cc: 5050 lw a2,36(s0) - 800020ce: 5050 lw a2,36(s0) - 800020d0: 5050 lw a2,36(s0) - 800020d2: 5050 lw a2,36(s0) - 800020d4: 5050 lw a2,36(s0) - 800020d6: 5050 lw a2,36(s0) - 800020d8: 5050 lw a2,36(s0) - 800020da: 5050 lw a2,36(s0) - 800020dc: 5050 lw a2,36(s0) - 800020de: 5050 lw a2,36(s0) - 800020e0: 5050 lw a2,36(s0) - 800020e2: 5050 lw a2,36(s0) - 800020e4: 5050 lw a2,36(s0) - 800020e6: 5050 lw a2,36(s0) - 800020e8: 5050 lw a2,36(s0) - 800020ea: 5050 lw a2,36(s0) - 800020ec: 5050 lw a2,36(s0) - 800020ee: 5050 lw a2,36(s0) - 800020f0: 5050 lw a2,36(s0) - 800020f2: 5050 lw a2,36(s0) - 800020f4: 5050 lw a2,36(s0) - 800020f6: 5050 lw a2,36(s0) - 800020f8: 5050 lw a2,36(s0) - 800020fa: 5050 lw a2,36(s0) - 800020fc: 5050 lw a2,36(s0) - 800020fe: 5050 lw a2,36(s0) - 80002100: 5050 lw a2,36(s0) - 80002102: 5050 lw a2,36(s0) - 80002104: 5050 lw a2,36(s0) - 80002106: 5050 lw a2,36(s0) - 80002108: 5050 lw a2,36(s0) - 8000210a: 5050 lw a2,36(s0) - 8000210c: 5050 lw a2,36(s0) - 8000210e: 0050 addi a2,sp,4 diff --git a/test/riscv/tests/rv64mi-p-ma_addr.elf b/test/riscv/tests/rv64mi-p-ma_addr.elf deleted file mode 100644 index fc326628..00000000 Binary files a/test/riscv/tests/rv64mi-p-ma_addr.elf and /dev/null differ diff --git a/test/riscv/tests/rv64mi-p-ma_fetch.dump b/test/riscv/tests/rv64mi-p-ma_fetch.dump deleted file mode 100644 index 6a5285a6..00000000 --- a/test/riscv/tests/rv64mi-p-ma_fetch.dump +++ /dev/null @@ -1,219 +0,0 @@ - -rv64mi-p-ma_fetch: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 00000f17 auipc t5,0x0 - 80000024: 208f0f13 addi t5,t5,520 # 80000228 - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00002537 lui a0,0x2 - 800000ec: 8005051b addiw a0,a0,-2048 - 800000f0: 30052073 csrs mstatus,a0 - 800000f4: 00000297 auipc t0,0x0 - 800000f8: 01428293 addi t0,t0,20 # 80000108 - 800000fc: 34129073 csrw mepc,t0 - 80000100: f1402573 csrr a0,mhartid - 80000104: 30200073 mret - 80000108: 00200193 li gp,2 - 8000010c: 00000313 li t1,0 - 80000110: 00000297 auipc t0,0x0 - 80000114: 00c28293 addi t0,t0,12 # 8000011c - 80000118: 00228367 jalr t1,2(t0) - 8000011c: a011 j 80000120 - 8000011e: a019 j 80000124 - 80000120: 0e80006f j 80000208 - 80000124: 00300193 li gp,3 - 80000128: 00000297 auipc t0,0x0 - 8000012c: 00c28293 addi t0,t0,12 # 80000134 - 80000130: 00128367 jalr t1,1(t0) - 80000134: 0080006f j 8000013c - 80000138: 0d00006f j 80000208 - 8000013c: 00400193 li gp,4 - 80000140: 00000313 li t1,0 - 80000144: 00000297 auipc t0,0x0 - 80000148: 00c28293 addi t0,t0,12 # 80000150 - 8000014c: 00328367 jalr t1,3(t0) - 80000150: a011 j 80000154 - 80000152: a019 j 80000158 - 80000154: 0b40006f j 80000208 - 80000158: 00500193 li gp,5 - 8000015c: 00000313 li t1,0 - 80000160: 00000297 auipc t0,0x0 - 80000164: 00c28293 addi t0,t0,12 # 8000016c - 80000168: 0060036f jal t1,8000016e - 8000016c: a011 j 80000170 - 8000016e: a019 j 80000174 - 80000170: 0980006f j 80000208 - 80000174: 00600193 li gp,6 - 80000178: 00000313 li t1,0 - 8000017c: 00000297 auipc t0,0x0 - 80000180: 00c28293 addi t0,t0,12 # 80000188 - 80000184: 00000363 beqz zero,8000018a - 80000188: a011 j 8000018c - 8000018a: a019 j 80000190 - 8000018c: 07c0006f j 80000208 - 80000190: 00700193 li gp,7 - 80000194: 00001563 bnez zero,8000019e - 80000198: 00c0006f j 800001a4 - 8000019c: a009 j 8000019e - 8000019e: a009 j 800001a0 - 800001a0: 0680006f j 80000208 - 800001a4: 00800193 li gp,8 - 800001a8: 301023f3 csrr t2,misa - 800001ac: 0043f393 andi t2,t2,4 - 800001b0: 04038863 beqz t2,80000200 - 800001b4: 0001 nop - 800001b6: 30127073 csrci misa,4 - 800001ba: 0001 nop - 800001bc: 301023f3 csrr t2,misa - 800001c0: 0043f393 andi t2,t2,4 - 800001c4: 04038263 beqz t2,80000208 - 800001c8: 00000297 auipc t0,0x0 - 800001cc: 03428293 addi t0,t0,52 # 800001fc - 800001d0: ffe28293 addi t0,t0,-2 - 800001d4: 34129073 csrw mepc,t0 - 800001d8: 30127073 csrci misa,4 - 800001dc: 301023f3 csrr t2,misa - 800001e0: 0043f393 andi t2,t2,4 - 800001e4: 00039e63 bnez t2,80000200 - 800001e8: 000023b7 lui t2,0x2 - 800001ec: 8003839b addiw t2,t2,-2048 - 800001f0: 3003a073 csrs mstatus,t2 - 800001f4: 30200073 mret - 800001f8: 00000263 beqz zero,800001fc - 800001fc: 30126073 csrsi misa,4 - 80000200: 01c0006f j 8000021c - 80000204: 00301c63 bne zero,gp,8000021c - -0000000080000208 : - 80000208: 0ff0000f fence - 8000020c: 00018063 beqz gp,8000020c - 80000210: 00119193 slli gp,gp,0x1 - 80000214: 0011e193 ori gp,gp,1 - 80000218: 00000073 ecall - -000000008000021c : - 8000021c: 0ff0000f fence - 80000220: 00100193 li gp,1 - 80000224: 00000073 ecall - -0000000080000228 : - 80000228: 00200513 li a0,2 - 8000022c: 02a18063 beq gp,a0,8000024c - 80000230: 00400513 li a0,4 - 80000234: 00a18c63 beq gp,a0,8000024c - 80000238: 00500513 li a0,5 - 8000023c: 00a18863 beq gp,a0,8000024c - 80000240: 00600513 li a0,6 - 80000244: 00a18463 beq gp,a0,8000024c - 80000248: fc1ff06f j 80000208 - 8000024c: fa031ee3 bnez t1,80000208 - 80000250: 00000593 li a1,0 - 80000254: 34202573 csrr a0,mcause - 80000258: fab518e3 bne a0,a1,80000208 - 8000025c: 341025f3 csrr a1,mepc - 80000260: 00458593 addi a1,a1,4 - 80000264: fab292e3 bne t0,a1,80000208 - 80000268: 34302573 csrr a0,mbadaddr - 8000026c: 00050663 beqz a0,80000278 - 80000270: ffe50513 addi a0,a0,-2 # 1ffe <_start-0x7fffe002> - 80000274: f8551ae3 bne a0,t0,80000208 - 80000278: 00c58593 addi a1,a1,12 - 8000027c: 34159073 csrw mepc,a1 - 80000280: 30200073 mret - 80000284: c0001073 unimp - 80000288: 0000 unimp - 8000028a: 0000 unimp - 8000028c: 0000 unimp - 8000028e: 0000 unimp - 80000290: 0000 unimp - 80000292: 0000 unimp - 80000294: 0000 unimp - 80000296: 0000 unimp - 80000298: 0000 unimp - 8000029a: 0000 unimp - 8000029c: 0000 unimp - 8000029e: 0000 unimp - 800002a0: 0000 unimp - 800002a2: 0000 unimp - 800002a4: 0000 unimp - 800002a6: 0000 unimp - 800002a8: 0000 unimp - 800002aa: 0000 unimp - 800002ac: 0000 unimp - 800002ae: 0000 unimp - 800002b0: 0000 unimp - 800002b2: 0000 unimp - 800002b4: 0000 unimp - 800002b6: 0000 unimp - 800002b8: 0000 unimp - 800002ba: 0000 unimp - 800002bc: 0000 unimp - 800002be: 0000 unimp - 800002c0: 0000 unimp - 800002c2: 0000 unimp diff --git a/test/riscv/tests/rv64mi-p-ma_fetch.elf b/test/riscv/tests/rv64mi-p-ma_fetch.elf deleted file mode 100644 index 40ffdf38..00000000 Binary files a/test/riscv/tests/rv64mi-p-ma_fetch.elf and /dev/null differ diff --git a/test/riscv/tests/rv64mi-p-mcsr.dump b/test/riscv/tests/rv64mi-p-mcsr.dump deleted file mode 100644 index befb1931..00000000 --- a/test/riscv/tests/rv64mi-p-mcsr.dump +++ /dev/null @@ -1,126 +0,0 @@ - -rv64mi-p-mcsr: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00002537 lui a0,0x2 - 800000ec: 8005051b addiw a0,a0,-2048 - 800000f0: 30052073 csrs mstatus,a0 - 800000f4: 00000297 auipc t0,0x0 - 800000f8: 01428293 addi t0,t0,20 # 80000108 - 800000fc: 34129073 csrw mepc,t0 - 80000100: f1402573 csrr a0,mhartid - 80000104: 30200073 mret - -0000000080000108 : - 80000108: 30102573 csrr a0,misa - 8000010c: 03e55513 srli a0,a0,0x3e - 80000110: 00200e93 li t4,2 - 80000114: 00200193 li gp,2 - 80000118: 03d51863 bne a0,t4,80000148 - -000000008000011c : - 8000011c: f1402573 csrr a0,mhartid - 80000120: 00000e93 li t4,0 - 80000124: 00300193 li gp,3 - 80000128: 03d51063 bne a0,t4,80000148 - 8000012c: f1302573 csrr a0,mimpid - 80000130: f1202573 csrr a0,marchid - 80000134: f1102573 csrr a0,mvendorid - 80000138: 00000293 li t0,0 - 8000013c: 3052a073 csrs mtvec,t0 - 80000140: 3412a073 csrs mepc,t0 - 80000144: 00301c63 bne zero,gp,8000015c - -0000000080000148 : - 80000148: 0ff0000f fence - 8000014c: 00018063 beqz gp,8000014c - 80000150: 00119193 slli gp,gp,0x1 - 80000154: 0011e193 ori gp,gp,1 - 80000158: 00000073 ecall - -000000008000015c : - 8000015c: 0ff0000f fence - 80000160: 00100193 li gp,1 - 80000164: 00000073 ecall - 80000168: c0001073 unimp - 8000016c: 0000 unimp - 8000016e: 0000 unimp - 80000170: 0000 unimp - 80000172: 0000 unimp - 80000174: 0000 unimp - 80000176: 0000 unimp - 80000178: 0000 unimp - 8000017a: 0000 unimp - 8000017c: 0000 unimp - 8000017e: 0000 unimp - 80000180: 0000 unimp - 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64mi-p-mcsr.elf b/test/riscv/tests/rv64mi-p-mcsr.elf deleted file mode 100644 index 4ce3d35f..00000000 Binary files a/test/riscv/tests/rv64mi-p-mcsr.elf and /dev/null differ diff --git a/test/riscv/tests/rv64mi-p-scall.dump b/test/riscv/tests/rv64mi-p-scall.dump deleted file mode 100644 index 940db038..00000000 --- a/test/riscv/tests/rv64mi-p-scall.dump +++ /dev/null @@ -1,147 +0,0 @@ - -rv64mi-p-scall: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 00000f17 auipc t5,0x0 - 80000024: 158f0f13 addi t5,t5,344 # 80000178 - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00002537 lui a0,0x2 - 800000ec: 8005051b addiw a0,a0,-2048 - 800000f0: 30052073 csrs mstatus,a0 - 800000f4: 00000297 auipc t0,0x0 - 800000f8: 01428293 addi t0,t0,20 # 80000108 - 800000fc: 34129073 csrw mepc,t0 - 80000100: f1402573 csrr a0,mhartid - 80000104: 30200073 mret - 80000108: 00200193 li gp,2 - 8000010c: 00800313 li t1,8 - 80000110: 000022b7 lui t0,0x2 - 80000114: 8002829b addiw t0,t0,-2048 - 80000118: 3002b073 csrc mstatus,t0 - 8000011c: 30002373 csrr t1,mstatus - 80000120: 0062f2b3 and t0,t0,t1 - 80000124: 00028463 beqz t0,8000012c - 80000128: 00b00313 li t1,11 - 8000012c: 000022b7 lui t0,0x2 - 80000130: 8002829b addiw t0,t0,-2048 - 80000134: 3002b073 csrc mstatus,t0 - 80000138: 00000297 auipc t0,0x0 - 8000013c: 01028293 addi t0,t0,16 # 80000148 - 80000140: 34129073 csrw mepc,t0 - 80000144: 30200073 mret - 80000148: 00100193 li gp,1 - -000000008000014c : - 8000014c: 00000073 ecall - 80000150: 0080006f j 80000158 - 80000154: 00301c63 bne zero,gp,8000016c - -0000000080000158 : - 80000158: 0ff0000f fence - 8000015c: 00018063 beqz gp,8000015c - 80000160: 00119193 slli gp,gp,0x1 - 80000164: 0011e193 ori gp,gp,1 - 80000168: 00000073 ecall - -000000008000016c : - 8000016c: 0ff0000f fence - 80000170: 00100193 li gp,1 - 80000174: 00000073 ecall - -0000000080000178 : - 80000178: 342022f3 csrr t0,mcause - 8000017c: fc629ee3 bne t0,t1,80000158 - 80000180: 00000397 auipc t2,0x0 - 80000184: fcc38393 addi t2,t2,-52 # 8000014c - 80000188: 341022f3 csrr t0,mepc - 8000018c: fc7296e3 bne t0,t2,80000158 - 80000190: fddff06f j 8000016c - 80000194: c0001073 unimp - 80000198: 0000 unimp - 8000019a: 0000 unimp - 8000019c: 0000 unimp - 8000019e: 0000 unimp - 800001a0: 0000 unimp - 800001a2: 0000 unimp - 800001a4: 0000 unimp - 800001a6: 0000 unimp - 800001a8: 0000 unimp - 800001aa: 0000 unimp - 800001ac: 0000 unimp - 800001ae: 0000 unimp - 800001b0: 0000 unimp - 800001b2: 0000 unimp - 800001b4: 0000 unimp - 800001b6: 0000 unimp - 800001b8: 0000 unimp - 800001ba: 0000 unimp - 800001bc: 0000 unimp - 800001be: 0000 unimp - 800001c0: 0000 unimp - 800001c2: 0000 unimp diff --git a/test/riscv/tests/rv64mi-p-scall.elf b/test/riscv/tests/rv64mi-p-scall.elf deleted file mode 100644 index bbb1526b..00000000 Binary files a/test/riscv/tests/rv64mi-p-scall.elf and /dev/null differ diff --git a/test/riscv/tests/rv64si-p-csr.dump b/test/riscv/tests/rv64si-p-csr.dump deleted file mode 100644 index e4e92ac7..00000000 --- a/test/riscv/tests/rv64si-p-csr.dump +++ /dev/null @@ -1,222 +0,0 @@ - -rv64si-p-csr: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 00000297 auipc t0,0x0 - 800000c4: 16c28293 addi t0,t0,364 # 8000022c - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00001537 lui a0,0x1 - 800000ec: 8005051b addiw a0,a0,-2048 - 800000f0: 30052073 csrs mstatus,a0 - 800000f4: 02200513 li a0,34 - 800000f8: 30352073 csrs mideleg,a0 - 800000fc: 00000297 auipc t0,0x0 - 80000100: 01428293 addi t0,t0,20 # 80000110 - 80000104: 34129073 csrw mepc,t0 - 80000108: f1402573 csrr a0,mhartid - 8000010c: 30200073 mret - -0000000080000110 : - 80000110: 10002573 csrr a0,sstatus - 80000114: 0030059b addiw a1,zero,3 - 80000118: 02059593 slli a1,a1,0x20 - 8000011c: 00b57533 and a0,a0,a1 - 80000120: 00100e9b addiw t4,zero,1 - 80000124: 021e9e93 slli t4,t4,0x21 - 80000128: 00d00193 li gp,13 - 8000012c: 0fd51063 bne a0,t4,8000020c - 80000130: 1401d073 csrwi sscratch,3 - -0000000080000134 : - 80000134: 14002573 csrr a0,sscratch - 80000138: 00300e93 li t4,3 - 8000013c: 00200193 li gp,2 - 80000140: 0dd51663 bne a0,t4,8000020c - -0000000080000144 : - 80000144: 1400f5f3 csrrci a1,sscratch,1 - 80000148: 00300e93 li t4,3 - 8000014c: 00300193 li gp,3 - 80000150: 0bd59e63 bne a1,t4,8000020c - -0000000080000154 : - 80000154: 14026673 csrrsi a2,sscratch,4 - 80000158: 00200e93 li t4,2 - 8000015c: 00400193 li gp,4 - 80000160: 0bd61663 bne a2,t4,8000020c - -0000000080000164 : - 80000164: 140156f3 csrrwi a3,sscratch,2 - 80000168: 00600e93 li t4,6 - 8000016c: 00500193 li gp,5 - 80000170: 09d69e63 bne a3,t4,8000020c - -0000000080000174 : - 80000174: 0bad2537 lui a0,0xbad2 - 80000178: dea5051b addiw a0,a0,-534 - 8000017c: 140515f3 csrrw a1,sscratch,a0 - 80000180: 00200e93 li t4,2 - 80000184: 00600193 li gp,6 - 80000188: 09d59263 bne a1,t4,8000020c - -000000008000018c : - 8000018c: 00002537 lui a0,0x2 - 80000190: dea5051b addiw a0,a0,-534 - 80000194: 14053573 csrrc a0,sscratch,a0 - 80000198: 0bad2eb7 lui t4,0xbad2 - 8000019c: deae8e9b addiw t4,t4,-534 - 800001a0: 00700193 li gp,7 - 800001a4: 07d51463 bne a0,t4,8000020c - -00000000800001a8 : - 800001a8: 0000c537 lui a0,0xc - 800001ac: eef5051b addiw a0,a0,-273 - 800001b0: 14052573 csrrs a0,sscratch,a0 - 800001b4: 0bad0eb7 lui t4,0xbad0 - 800001b8: 00800193 li gp,8 - 800001bc: 05d51863 bne a0,t4,8000020c - -00000000800001c0 : - 800001c0: 14002573 csrr a0,sscratch - 800001c4: 0badceb7 lui t4,0xbadc - 800001c8: eefe8e9b addiw t4,t4,-273 - 800001cc: 00900193 li gp,9 - 800001d0: 03d51e63 bne a0,t4,8000020c - 800001d4: 10000293 li t0,256 - 800001d8: 1002b073 csrc sstatus,t0 - 800001dc: 00000297 auipc t0,0x0 - 800001e0: 01028293 addi t0,t0,16 # 800001ec - 800001e4: 14129073 csrw sepc,t0 - 800001e8: 10200073 sret - -00000000800001ec : - 800001ec: 00000013 nop - 800001f0: 00000e93 li t4,0 - 800001f4: 00c00193 li gp,12 - 800001f8: 01d01a63 bne zero,t4,8000020c - -00000000800001fc : - 800001fc: 0ff0000f fence - 80000200: 00100193 li gp,1 - 80000204: 00000073 ecall - 80000208: 00301c63 bne zero,gp,80000220 - -000000008000020c : - 8000020c: 0ff0000f fence - 80000210: 00018063 beqz gp,80000210 - 80000214: 00119193 slli gp,gp,0x1 - 80000218: 0011e193 ori gp,gp,1 - 8000021c: 00000073 ecall - -0000000080000220 : - 80000220: 0ff0000f fence - 80000224: 00100193 li gp,1 - 80000228: 00000073 ecall - -000000008000022c : - 8000022c: 00900293 li t0,9 - 80000230: 0051e663 bltu gp,t0,8000023c - 80000234: 00b00293 li t0,11 - 80000238: 0032fe63 bleu gp,t0,80000254 - 8000023c: 142022f3 csrr t0,scause - 80000240: 00800313 li t1,8 - 80000244: fc6294e3 bne t0,t1,8000020c - 80000248: 0ff0000f fence - 8000024c: 00100193 li gp,1 - 80000250: 00000073 ecall - -0000000080000254 : - 80000254: 142022f3 csrr t0,scause - 80000258: 00200313 li t1,2 - 8000025c: fa6298e3 bne t0,t1,8000020c - 80000260: 141022f3 csrr t0,sepc - 80000264: 00428293 addi t0,t0,4 - 80000268: 14129073 csrw sepc,t0 - 8000026c: 10200073 sret - 80000270: c0001073 unimp - 80000274: 0000 unimp - 80000276: 0000 unimp - 80000278: 0000 unimp - 8000027a: 0000 unimp - 8000027c: 0000 unimp - 8000027e: 0000 unimp - 80000280: 0000 unimp - 80000282: 0000 unimp - -Disassembly of section .data: - -0000000080002000 : - 80002000: 0001 nop - 80002002: 0000 unimp - 80002004: 0000 unimp - 80002006: 0000 unimp - 80002008: 0000 unimp - 8000200a: 0000 unimp - 8000200c: 0000 unimp - 8000200e: 0000 unimp diff --git a/test/riscv/tests/rv64si-p-csr.elf b/test/riscv/tests/rv64si-p-csr.elf deleted file mode 100644 index 3f0921cb..00000000 Binary files a/test/riscv/tests/rv64si-p-csr.elf and /dev/null differ diff --git a/test/riscv/tests/rv64si-p-dirty.dump b/test/riscv/tests/rv64si-p-dirty.dump deleted file mode 100644 index a92c70da..00000000 --- a/test/riscv/tests/rv64si-p-dirty.dump +++ /dev/null @@ -1,202 +0,0 @@ - -rv64si-p-dirty: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 00000f17 auipc t5,0x0 - 80000024: 1d0f0f13 addi t5,t5,464 # 800001f0 - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00002537 lui a0,0x2 - 800000ec: 8005051b addiw a0,a0,-2048 - 800000f0: 30052073 csrs mstatus,a0 - 800000f4: 00000297 auipc t0,0x0 - 800000f8: 01428293 addi t0,t0,20 # 80000108 - 800000fc: 34129073 csrw mepc,t0 - 80000100: f1402573 csrr a0,mhartid - 80000104: 30200073 mret - 80000108: fff0051b addiw a0,zero,-1 - 8000010c: 03f51513 slli a0,a0,0x3f - 80000110: 00002597 auipc a1,0x2 - 80000114: ef058593 addi a1,a1,-272 # 80002000 - 80000118: 00c5d593 srli a1,a1,0xc - 8000011c: 00a5e5b3 or a1,a1,a0 - 80000120: 18059073 csrw satp,a1 - 80000124: 12000073 sfence.vma - 80000128: 000215b7 lui a1,0x21 - 8000012c: 8005859b addiw a1,a1,-2048 - 80000130: 3005a073 csrs mstatus,a1 - 80000134: 00200193 li gp,2 - 80000138: 00100393 li t2,1 - 8000013c: 80002517 auipc a0,0x80002 - 80000140: ec752623 sw t2,-308(a0) # 2008 <_start-0x7fffdff8> - 80000144: 00300193 li gp,3 - 80000148: 000415b7 lui a1,0x41 - 8000014c: 8005859b addiw a1,a1,-2048 - 80000150: 3005a073 csrs mstatus,a1 - 80000154: 80002297 auipc t0,0x80002 - 80000158: eb42a283 lw t0,-332(t0) # 2008 <_start-0x7fffdff8> - 8000015c: 10029063 bnez t0,8000025c - 80000160: 80002517 auipc a0,0x80002 - 80000164: ea752423 sw t2,-344(a0) # 2008 <_start-0x7fffdff8> - 80000168: 80002297 auipc t0,0x80002 - 8000016c: ea02a283 lw t0,-352(t0) # 2008 <_start-0x7fffdff8> - 80000170: 0e729663 bne t0,t2,8000025c - 80000174: 000202b7 lui t0,0x20 - 80000178: 3002b073 csrc mstatus,t0 - 8000017c: 00002297 auipc t0,0x2 - 80000180: e842a283 lw t0,-380(t0) # 80002000 - 80000184: 0c000513 li a0,192 - 80000188: 00a2f2b3 and t0,t0,a0 - 8000018c: 0ca29863 bne t0,a0,8000025c - 80000190: 000202b7 lui t0,0x20 - 80000194: 3002a073 csrs mstatus,t0 - 80000198: 00400193 li gp,4 - 8000019c: 80002517 auipc a0,0x80002 - 800001a0: e6452503 lw a0,-412(a0) # 2000 <_start-0x7fffe000> - 800001a4: 40056513 ori a0,a0,1024 - 800001a8: 80002297 auipc t0,0x80002 - 800001ac: e4a2ac23 sw a0,-424(t0) # 2000 <_start-0x7fffe000> - 800001b0: 12000073 sfence.vma - 800001b4: 80002297 auipc t0,0x80002 - 800001b8: e4a2a623 sw a0,-436(t0) # 2000 <_start-0x7fffe000> - 800001bc: 0a00006f j 8000025c - 800001c0: 0ff0000f fence - 800001c4: 00100193 li gp,1 - 800001c8: 00000073 ecall - 800001cc: 00301c63 bne zero,gp,800001e4 - -00000000800001d0 : - 800001d0: 0ff0000f fence - 800001d4: 00018063 beqz gp,800001d4 - 800001d8: 00119193 slli gp,gp,0x1 - 800001dc: 0011e193 ori gp,gp,1 - 800001e0: 00000073 ecall - -00000000800001e4 : - 800001e4: 0ff0000f fence - 800001e8: 00100193 li gp,1 - 800001ec: 00000073 ecall - -00000000800001f0 : - 800001f0: 342022f3 csrr t0,mcause - 800001f4: ff128293 addi t0,t0,-15 - 800001f8: 06029263 bnez t0,8000025c - 800001fc: 00200313 li t1,2 - 80000200: 02619263 bne gp,t1,80000224 - 80000204: 00002297 auipc t0,0x2 - 80000208: dfc2a283 lw t0,-516(t0) # 80002000 - 8000020c: 0802f313 andi t1,t0,128 - 80000210: 04031663 bnez t1,8000025c - -0000000080000214 : - 80000214: 341022f3 csrr t0,mepc - 80000218: 00428293 addi t0,t0,4 - 8000021c: 34129073 csrw mepc,t0 - 80000220: 30200073 mret - 80000224: 00300313 li t1,3 - 80000228: 02619463 bne gp,t1,80000250 - 8000022c: 00002297 auipc t0,0x2 - 80000230: dd42a283 lw t0,-556(t0) # 80002000 - 80000234: 0802f313 andi t1,t0,128 - 80000238: 02031263 bnez t1,8000025c - 8000023c: 0802e293 ori t0,t0,128 - 80000240: 00002317 auipc t1,0x2 - 80000244: dc532023 sw t0,-576(t1) # 80002000 - 80000248: 12000073 sfence.vma - 8000024c: 30200073 mret - 80000250: 00400313 li t1,4 - 80000254: 00619463 bne gp,t1,8000025c - 80000258: f8dff06f j 800001e4 - -000000008000025c : - 8000025c: 0ff0000f fence - 80000260: 00018063 beqz gp,80000260 - 80000264: 00119193 slli gp,gp,0x1 - 80000268: 0011e193 ori gp,gp,1 - 8000026c: 00000073 ecall - 80000270: c0001073 unimp - 80000274: 0000 unimp - 80000276: 0000 unimp - 80000278: 0000 unimp - 8000027a: 0000 unimp - 8000027c: 0000 unimp - 8000027e: 0000 unimp - 80000280: 0000 unimp - 80000282: 0000 unimp - -Disassembly of section .data: - -0000000080002000 : - 80002000: 005f 2000 0000 0x2000005f - 80002006: 0000 unimp - -0000000080002008 : - 80002008: 0000 unimp - 8000200a: 0000 unimp - 8000200c: 0000 unimp - 8000200e: 0000 unimp diff --git a/test/riscv/tests/rv64si-p-dirty.elf b/test/riscv/tests/rv64si-p-dirty.elf deleted file mode 100644 index 7ff11e51..00000000 Binary files a/test/riscv/tests/rv64si-p-dirty.elf and /dev/null differ diff --git a/test/riscv/tests/rv64si-p-ma_fetch.dump b/test/riscv/tests/rv64si-p-ma_fetch.dump deleted file mode 100644 index bd8178ba..00000000 --- a/test/riscv/tests/rv64si-p-ma_fetch.dump +++ /dev/null @@ -1,175 +0,0 @@ - -rv64si-p-ma_fetch: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 00000297 auipc t0,0x0 - 800000c4: 11428293 addi t0,t0,276 # 800001d4 - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00001537 lui a0,0x1 - 800000ec: 8005051b addiw a0,a0,-2048 - 800000f0: 30052073 csrs mstatus,a0 - 800000f4: 02200513 li a0,34 - 800000f8: 30352073 csrs mideleg,a0 - 800000fc: 00000297 auipc t0,0x0 - 80000100: 01428293 addi t0,t0,20 # 80000110 - 80000104: 34129073 csrw mepc,t0 - 80000108: f1402573 csrr a0,mhartid - 8000010c: 30200073 mret - 80000110: 00200193 li gp,2 - 80000114: 00000313 li t1,0 - 80000118: 00000297 auipc t0,0x0 - 8000011c: 00c28293 addi t0,t0,12 # 80000124 - 80000120: 00228367 jalr t1,2(t0) - 80000124: a011 j 80000128 - 80000126: a019 j 8000012c - 80000128: 08c0006f j 800001b4 - 8000012c: 00300193 li gp,3 - 80000130: 00000297 auipc t0,0x0 - 80000134: 00c28293 addi t0,t0,12 # 8000013c - 80000138: 00128367 jalr t1,1(t0) - 8000013c: 0080006f j 80000144 - 80000140: 0740006f j 800001b4 - 80000144: 00400193 li gp,4 - 80000148: 00000313 li t1,0 - 8000014c: 00000297 auipc t0,0x0 - 80000150: 00c28293 addi t0,t0,12 # 80000158 - 80000154: 00328367 jalr t1,3(t0) - 80000158: a011 j 8000015c - 8000015a: a019 j 80000160 - 8000015c: 0580006f j 800001b4 - 80000160: 00500193 li gp,5 - 80000164: 00000313 li t1,0 - 80000168: 00000297 auipc t0,0x0 - 8000016c: 00c28293 addi t0,t0,12 # 80000174 - 80000170: 0060036f jal t1,80000176 - 80000174: a011 j 80000178 - 80000176: a019 j 8000017c - 80000178: 03c0006f j 800001b4 - 8000017c: 00600193 li gp,6 - 80000180: 00000313 li t1,0 - 80000184: 00000297 auipc t0,0x0 - 80000188: 00c28293 addi t0,t0,12 # 80000190 - 8000018c: 00000363 beqz zero,80000192 - 80000190: a011 j 80000194 - 80000192: a019 j 80000198 - 80000194: 0200006f j 800001b4 - 80000198: 00700193 li gp,7 - 8000019c: 00001563 bnez zero,800001a6 - 800001a0: 00c0006f j 800001ac - 800001a4: a009 j 800001a6 - 800001a6: a009 j 800001a8 - 800001a8: 00c0006f j 800001b4 - 800001ac: 01c0006f j 800001c8 - 800001b0: 00301c63 bne zero,gp,800001c8 - -00000000800001b4 : - 800001b4: 0ff0000f fence - 800001b8: 00018063 beqz gp,800001b8 - 800001bc: 00119193 slli gp,gp,0x1 - 800001c0: 0011e193 ori gp,gp,1 - 800001c4: 00000073 ecall - -00000000800001c8 : - 800001c8: 0ff0000f fence - 800001cc: 00100193 li gp,1 - 800001d0: 00000073 ecall - -00000000800001d4 : - 800001d4: 00200513 li a0,2 - 800001d8: 02a18063 beq gp,a0,800001f8 - 800001dc: 00400513 li a0,4 - 800001e0: 00a18c63 beq gp,a0,800001f8 - 800001e4: 00500513 li a0,5 - 800001e8: 00a18863 beq gp,a0,800001f8 - 800001ec: 00600513 li a0,6 - 800001f0: 00a18463 beq gp,a0,800001f8 - 800001f4: fc1ff06f j 800001b4 - 800001f8: fa031ee3 bnez t1,800001b4 - 800001fc: 00000593 li a1,0 - 80000200: 14202573 csrr a0,scause - 80000204: fab518e3 bne a0,a1,800001b4 - 80000208: 141025f3 csrr a1,sepc - 8000020c: 00458593 addi a1,a1,4 - 80000210: fab292e3 bne t0,a1,800001b4 - 80000214: 14302573 csrr a0,sbadaddr - 80000218: 00050663 beqz a0,80000224 - 8000021c: ffe50513 addi a0,a0,-2 # ffe <_start-0x7ffff002> - 80000220: f8551ae3 bne a0,t0,800001b4 - 80000224: 00c58593 addi a1,a1,12 - 80000228: 14159073 csrw sepc,a1 - 8000022c: 10200073 sret - 80000230: c0001073 unimp - 80000234: 0000 unimp - 80000236: 0000 unimp - 80000238: 0000 unimp - 8000023a: 0000 unimp - 8000023c: 0000 unimp - 8000023e: 0000 unimp - 80000240: 0000 unimp - 80000242: 0000 unimp diff --git a/test/riscv/tests/rv64si-p-ma_fetch.elf b/test/riscv/tests/rv64si-p-ma_fetch.elf deleted file mode 100644 index 23977add..00000000 Binary files a/test/riscv/tests/rv64si-p-ma_fetch.elf and /dev/null differ diff --git a/test/riscv/tests/rv64si-p-scall.dump b/test/riscv/tests/rv64si-p-scall.dump deleted file mode 100644 index 99674507..00000000 --- a/test/riscv/tests/rv64si-p-scall.dump +++ /dev/null @@ -1,121 +0,0 @@ - -rv64si-p-scall: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 00000297 auipc t0,0x0 - 800000c4: 0a028293 addi t0,t0,160 # 80000160 - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00001537 lui a0,0x1 - 800000ec: 8005051b addiw a0,a0,-2048 - 800000f0: 30052073 csrs mstatus,a0 - 800000f4: 02200513 li a0,34 - 800000f8: 30352073 csrs mideleg,a0 - 800000fc: 00000297 auipc t0,0x0 - 80000100: 01428293 addi t0,t0,20 # 80000110 - 80000104: 34129073 csrw mepc,t0 - 80000108: f1402573 csrr a0,mhartid - 8000010c: 30200073 mret - 80000110: 00200193 li gp,2 - 80000114: 00800313 li t1,8 - 80000118: 10000293 li t0,256 - 8000011c: 1002b073 csrc sstatus,t0 - 80000120: 00000297 auipc t0,0x0 - 80000124: 01028293 addi t0,t0,16 # 80000130 - 80000128: 14129073 csrw sepc,t0 - 8000012c: 10200073 sret - 80000130: 00100193 li gp,1 - -0000000080000134 : - 80000134: 00000073 ecall - 80000138: 0080006f j 80000140 - 8000013c: 00301c63 bne zero,gp,80000154 - -0000000080000140 : - 80000140: 0ff0000f fence - 80000144: 00018063 beqz gp,80000144 - 80000148: 00119193 slli gp,gp,0x1 - 8000014c: 0011e193 ori gp,gp,1 - 80000150: 00000073 ecall - -0000000080000154 : - 80000154: 0ff0000f fence - 80000158: 00100193 li gp,1 - 8000015c: 00000073 ecall - -0000000080000160 : - 80000160: 142022f3 csrr t0,scause - 80000164: fc629ee3 bne t0,t1,80000140 - 80000168: 00000397 auipc t2,0x0 - 8000016c: fcc38393 addi t2,t2,-52 # 80000134 - 80000170: 141022f3 csrr t0,sepc - 80000174: fc7296e3 bne t0,t2,80000140 - 80000178: fddff06f j 80000154 - 8000017c: c0001073 unimp - 80000180: 0000 unimp - 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64si-p-scall.elf b/test/riscv/tests/rv64si-p-scall.elf deleted file mode 100644 index 4d7dc278..00000000 Binary files a/test/riscv/tests/rv64si-p-scall.elf and /dev/null differ diff --git a/test/riscv/tests/rv64si-p-wfi.dump b/test/riscv/tests/rv64si-p-wfi.dump deleted file mode 100644 index 2cd7bf86..00000000 --- a/test/riscv/tests/rv64si-p-wfi.dump +++ /dev/null @@ -1,128 +0,0 @@ - -rv64si-p-wfi: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00001537 lui a0,0x1 - 800000ec: 8005051b addiw a0,a0,-2048 - 800000f0: 30052073 csrs mstatus,a0 - 800000f4: 02200513 li a0,34 - 800000f8: 30352073 csrs mideleg,a0 - 800000fc: 00000297 auipc t0,0x0 - 80000100: 01428293 addi t0,t0,20 # 80000110 - 80000104: 34129073 csrw mepc,t0 - 80000108: f1402573 csrr a0,mhartid - 8000010c: 30200073 mret - 80000110: 10017073 csrci sstatus,2 - 80000114: 10416073 csrsi sie,2 - 80000118: 14416073 csrsi sip,2 - 8000011c: 10500073 wfi - 80000120: 0ff0000f fence - 80000124: 00100193 li gp,1 - 80000128: 00000073 ecall - 8000012c: 00301c63 bne zero,gp,80000144 - -0000000080000130 : - 80000130: 0ff0000f fence - 80000134: 00018063 beqz gp,80000134 - 80000138: 00119193 slli gp,gp,0x1 - 8000013c: 0011e193 ori gp,gp,1 - 80000140: 00000073 ecall - -0000000080000144 : - 80000144: 0ff0000f fence - 80000148: 00100193 li gp,1 - 8000014c: 00000073 ecall - 80000150: c0001073 unimp - 80000154: 0000 unimp - 80000156: 0000 unimp - 80000158: 0000 unimp - 8000015a: 0000 unimp - 8000015c: 0000 unimp - 8000015e: 0000 unimp - 80000160: 0000 unimp - 80000162: 0000 unimp - 80000164: 0000 unimp - 80000166: 0000 unimp - 80000168: 0000 unimp - 8000016a: 0000 unimp - 8000016c: 0000 unimp - 8000016e: 0000 unimp - 80000170: 0000 unimp - 80000172: 0000 unimp - 80000174: 0000 unimp - 80000176: 0000 unimp - 80000178: 0000 unimp - 8000017a: 0000 unimp - 8000017c: 0000 unimp - 8000017e: 0000 unimp - 80000180: 0000 unimp - 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64si-p-wfi.elf b/test/riscv/tests/rv64si-p-wfi.elf deleted file mode 100644 index 23d0c0cc..00000000 Binary files a/test/riscv/tests/rv64si-p-wfi.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-p-amoadd_d.dump b/test/riscv/tests/rv64ua-p-amoadd_d.dump deleted file mode 100644 index e90473bb..00000000 --- a/test/riscv/tests/rv64ua-p-amoadd_d.dump +++ /dev/null @@ -1,153 +0,0 @@ - -rv64ua-p-amoadd_d: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 80000537 lui a0,0x80000 - 80000100: 80000593 li a1,-2048 - 80000104: 00002697 auipc a3,0x2 - 80000108: efc68693 addi a3,a3,-260 # 80002000 - 8000010c: 00a6b023 sd a0,0(a3) - 80000110: 00b6b72f amoadd.d a4,a1,(a3) - 80000114: 80000eb7 lui t4,0x80000 - 80000118: 00200193 li gp,2 - 8000011c: 05d71863 bne a4,t4,8000016c - -0000000080000120 : - 80000120: 0006b783 ld a5,0(a3) - 80000124: fff00e9b addiw t4,zero,-1 - 80000128: 01fe9e93 slli t4,t4,0x1f - 8000012c: 800e8e93 addi t4,t4,-2048 # ffffffff7ffff800 <_end+0xfffffffeffffd7f8> - 80000130: 00300193 li gp,3 - 80000134: 03d79c63 bne a5,t4,8000016c - -0000000080000138 : - 80000138: 00b6b72f amoadd.d a4,a1,(a3) - 8000013c: fff00e9b addiw t4,zero,-1 - 80000140: 01fe9e93 slli t4,t4,0x1f - 80000144: 800e8e93 addi t4,t4,-2048 - 80000148: 00400193 li gp,4 - 8000014c: 03d71063 bne a4,t4,8000016c - -0000000080000150 : - 80000150: 0006b783 ld a5,0(a3) - 80000154: fff80eb7 lui t4,0xfff80 - 80000158: fffe8e9b addiw t4,t4,-1 - 8000015c: 00ce9e93 slli t4,t4,0xc - 80000160: 00500193 li gp,5 - 80000164: 01d79463 bne a5,t4,8000016c - 80000168: 00301c63 bne zero,gp,80000180 - -000000008000016c : - 8000016c: 0ff0000f fence - 80000170: 00018063 beqz gp,80000170 - 80000174: 00119193 slli gp,gp,0x1 - 80000178: 0011e193 ori gp,gp,1 - 8000017c: 00000073 ecall - -0000000080000180 : - 80000180: 0ff0000f fence - 80000184: 00100193 li gp,1 - 80000188: 00000073 ecall - 8000018c: c0001073 unimp - 80000190: 0000 unimp - 80000192: 0000 unimp - 80000194: 0000 unimp - 80000196: 0000 unimp - 80000198: 0000 unimp - 8000019a: 0000 unimp - 8000019c: 0000 unimp - 8000019e: 0000 unimp - 800001a0: 0000 unimp - 800001a2: 0000 unimp - 800001a4: 0000 unimp - 800001a6: 0000 unimp - 800001a8: 0000 unimp - 800001aa: 0000 unimp - 800001ac: 0000 unimp - 800001ae: 0000 unimp - 800001b0: 0000 unimp - 800001b2: 0000 unimp - 800001b4: 0000 unimp - 800001b6: 0000 unimp - 800001b8: 0000 unimp - 800001ba: 0000 unimp - 800001bc: 0000 unimp - 800001be: 0000 unimp - 800001c0: 0000 unimp - 800001c2: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amoadd_d.elf b/test/riscv/tests/rv64ua-p-amoadd_d.elf deleted file mode 100644 index e20d2903..00000000 Binary files a/test/riscv/tests/rv64ua-p-amoadd_d.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-p-amoadd_w.dump b/test/riscv/tests/rv64ua-p-amoadd_w.dump deleted file mode 100644 index a0bc84ef..00000000 --- a/test/riscv/tests/rv64ua-p-amoadd_w.dump +++ /dev/null @@ -1,124 +0,0 @@ - -rv64ua-p-amoadd_w: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 80000537 lui a0,0x80000 - 80000100: 80000593 li a1,-2048 - 80000104: 00002697 auipc a3,0x2 - 80000108: efc68693 addi a3,a3,-260 # 80002000 - 8000010c: 00a6a023 sw a0,0(a3) - 80000110: 00b6a72f amoadd.w a4,a1,(a3) - 80000114: 80000eb7 lui t4,0x80000 - 80000118: 00200193 li gp,2 - 8000011c: 05d71263 bne a4,t4,80000160 - -0000000080000120 : - 80000120: 0006a783 lw a5,0(a3) - 80000124: 80000eb7 lui t4,0x80000 - 80000128: 800e8e9b addiw t4,t4,-2048 - 8000012c: 00300193 li gp,3 - 80000130: 03d79863 bne a5,t4,80000160 - -0000000080000134 : - 80000134: 800005b7 lui a1,0x80000 - 80000138: 00b6a72f amoadd.w a4,a1,(a3) - 8000013c: 80000eb7 lui t4,0x80000 - 80000140: 800e8e9b addiw t4,t4,-2048 - 80000144: 00400193 li gp,4 - 80000148: 01d71c63 bne a4,t4,80000160 - -000000008000014c : - 8000014c: 0006a783 lw a5,0(a3) - 80000150: 80000e93 li t4,-2048 - 80000154: 00500193 li gp,5 - 80000158: 01d79463 bne a5,t4,80000160 - 8000015c: 00301c63 bne zero,gp,80000174 - -0000000080000160 : - 80000160: 0ff0000f fence - 80000164: 00018063 beqz gp,80000164 - 80000168: 00119193 slli gp,gp,0x1 - 8000016c: 0011e193 ori gp,gp,1 - 80000170: 00000073 ecall - -0000000080000174 : - 80000174: 0ff0000f fence - 80000178: 00100193 li gp,1 - 8000017c: 00000073 ecall - 80000180: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-p-amoadd_w.elf b/test/riscv/tests/rv64ua-p-amoadd_w.elf deleted file mode 100644 index f8c15af6..00000000 Binary files a/test/riscv/tests/rv64ua-p-amoadd_w.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-p-amoand_d.dump b/test/riscv/tests/rv64ua-p-amoand_d.dump deleted file mode 100644 index cb398f8d..00000000 --- a/test/riscv/tests/rv64ua-p-amoand_d.dump +++ /dev/null @@ -1,124 +0,0 @@ - -rv64ua-p-amoand_d: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 80000537 lui a0,0x80000 - 80000100: 80000593 li a1,-2048 - 80000104: 00002697 auipc a3,0x2 - 80000108: efc68693 addi a3,a3,-260 # 80002000 - 8000010c: 00a6b023 sd a0,0(a3) - 80000110: 60b6b72f amoand.d a4,a1,(a3) - 80000114: 80000eb7 lui t4,0x80000 - 80000118: 00200193 li gp,2 - 8000011c: 05d71263 bne a4,t4,80000160 - -0000000080000120 : - 80000120: 0006b783 ld a5,0(a3) - 80000124: 80000eb7 lui t4,0x80000 - 80000128: 00300193 li gp,3 - 8000012c: 03d79a63 bne a5,t4,80000160 - -0000000080000130 : - 80000130: 0010059b addiw a1,zero,1 - 80000134: 01f59593 slli a1,a1,0x1f - 80000138: 60b6b72f amoand.d a4,a1,(a3) - 8000013c: 80000eb7 lui t4,0x80000 - 80000140: 00400193 li gp,4 - 80000144: 01d71e63 bne a4,t4,80000160 - -0000000080000148 : - 80000148: 0006b783 ld a5,0(a3) - 8000014c: 00100e9b addiw t4,zero,1 - 80000150: 01fe9e93 slli t4,t4,0x1f - 80000154: 00500193 li gp,5 - 80000158: 01d79463 bne a5,t4,80000160 - 8000015c: 00301c63 bne zero,gp,80000174 - -0000000080000160 : - 80000160: 0ff0000f fence - 80000164: 00018063 beqz gp,80000164 - 80000168: 00119193 slli gp,gp,0x1 - 8000016c: 0011e193 ori gp,gp,1 - 80000170: 00000073 ecall - -0000000080000174 : - 80000174: 0ff0000f fence - 80000178: 00100193 li gp,1 - 8000017c: 00000073 ecall - 80000180: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-p-amoand_d.elf b/test/riscv/tests/rv64ua-p-amoand_d.elf deleted file mode 100644 index 6f9ec5cf..00000000 Binary files a/test/riscv/tests/rv64ua-p-amoand_d.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-p-amoand_w.dump b/test/riscv/tests/rv64ua-p-amoand_w.dump deleted file mode 100644 index 83ce206d..00000000 --- a/test/riscv/tests/rv64ua-p-amoand_w.dump +++ /dev/null @@ -1,125 +0,0 @@ - -rv64ua-p-amoand_w: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 80000537 lui a0,0x80000 - 80000100: 80000593 li a1,-2048 - 80000104: 00002697 auipc a3,0x2 - 80000108: efc68693 addi a3,a3,-260 # 80002000 - 8000010c: 00a6a023 sw a0,0(a3) - 80000110: 60b6a72f amoand.w a4,a1,(a3) - 80000114: 80000eb7 lui t4,0x80000 - 80000118: 00200193 li gp,2 - 8000011c: 05d71063 bne a4,t4,8000015c - -0000000080000120 : - 80000120: 0006a783 lw a5,0(a3) - 80000124: 80000eb7 lui t4,0x80000 - 80000128: 00300193 li gp,3 - 8000012c: 03d79863 bne a5,t4,8000015c - -0000000080000130 : - 80000130: 0010059b addiw a1,zero,1 - 80000134: 01f59593 slli a1,a1,0x1f - 80000138: 60b6a72f amoand.w a4,a1,(a3) - 8000013c: 80000eb7 lui t4,0x80000 - 80000140: 00400193 li gp,4 - 80000144: 01d71c63 bne a4,t4,8000015c - -0000000080000148 : - 80000148: 0006a783 lw a5,0(a3) - 8000014c: 80000eb7 lui t4,0x80000 - 80000150: 00500193 li gp,5 - 80000154: 01d79463 bne a5,t4,8000015c - 80000158: 00301c63 bne zero,gp,80000170 - -000000008000015c : - 8000015c: 0ff0000f fence - 80000160: 00018063 beqz gp,80000160 - 80000164: 00119193 slli gp,gp,0x1 - 80000168: 0011e193 ori gp,gp,1 - 8000016c: 00000073 ecall - -0000000080000170 : - 80000170: 0ff0000f fence - 80000174: 00100193 li gp,1 - 80000178: 00000073 ecall - 8000017c: c0001073 unimp - 80000180: 0000 unimp - 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amoand_w.elf b/test/riscv/tests/rv64ua-p-amoand_w.elf deleted file mode 100644 index fefc4fc0..00000000 Binary files a/test/riscv/tests/rv64ua-p-amoand_w.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-p-amomax_d.dump b/test/riscv/tests/rv64ua-p-amomax_d.dump deleted file mode 100644 index c91c2c8a..00000000 --- a/test/riscv/tests/rv64ua-p-amomax_d.dump +++ /dev/null @@ -1,125 +0,0 @@ - -rv64ua-p-amomax_d: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 80000537 lui a0,0x80000 - 80000100: 80000593 li a1,-2048 - 80000104: 00002697 auipc a3,0x2 - 80000108: efc68693 addi a3,a3,-260 # 80002000 - 8000010c: 00a6b023 sd a0,0(a3) - 80000110: a0b6b72f amomax.d a4,a1,(a3) - 80000114: 80000eb7 lui t4,0x80000 - 80000118: 00200193 li gp,2 - 8000011c: 05d71063 bne a4,t4,8000015c - -0000000080000120 : - 80000120: 0006b783 ld a5,0(a3) - 80000124: 80000e93 li t4,-2048 - 80000128: 00300193 li gp,3 - 8000012c: 03d79863 bne a5,t4,8000015c - -0000000080000130 : - 80000130: 00100593 li a1,1 - 80000134: 0006b023 sd zero,0(a3) - 80000138: a0b6b72f amomax.d a4,a1,(a3) - 8000013c: 00000e93 li t4,0 - 80000140: 00400193 li gp,4 - 80000144: 01d71c63 bne a4,t4,8000015c - -0000000080000148 : - 80000148: 0006b783 ld a5,0(a3) - 8000014c: 00100e93 li t4,1 - 80000150: 00500193 li gp,5 - 80000154: 01d79463 bne a5,t4,8000015c - 80000158: 00301c63 bne zero,gp,80000170 - -000000008000015c : - 8000015c: 0ff0000f fence - 80000160: 00018063 beqz gp,80000160 - 80000164: 00119193 slli gp,gp,0x1 - 80000168: 0011e193 ori gp,gp,1 - 8000016c: 00000073 ecall - -0000000080000170 : - 80000170: 0ff0000f fence - 80000174: 00100193 li gp,1 - 80000178: 00000073 ecall - 8000017c: c0001073 unimp - 80000180: 0000 unimp - 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amomax_d.elf b/test/riscv/tests/rv64ua-p-amomax_d.elf deleted file mode 100644 index 051cf481..00000000 Binary files a/test/riscv/tests/rv64ua-p-amomax_d.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-p-amomax_w.dump b/test/riscv/tests/rv64ua-p-amomax_w.dump deleted file mode 100644 index 5de2185e..00000000 --- a/test/riscv/tests/rv64ua-p-amomax_w.dump +++ /dev/null @@ -1,125 +0,0 @@ - -rv64ua-p-amomax_w: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 80000537 lui a0,0x80000 - 80000100: 80000593 li a1,-2048 - 80000104: 00002697 auipc a3,0x2 - 80000108: efc68693 addi a3,a3,-260 # 80002000 - 8000010c: 00a6a023 sw a0,0(a3) - 80000110: a0b6a72f amomax.w a4,a1,(a3) - 80000114: 80000eb7 lui t4,0x80000 - 80000118: 00200193 li gp,2 - 8000011c: 05d71063 bne a4,t4,8000015c - -0000000080000120 : - 80000120: 0006a783 lw a5,0(a3) - 80000124: 80000e93 li t4,-2048 - 80000128: 00300193 li gp,3 - 8000012c: 03d79863 bne a5,t4,8000015c - -0000000080000130 : - 80000130: 00100593 li a1,1 - 80000134: 0006a023 sw zero,0(a3) - 80000138: a0b6a72f amomax.w a4,a1,(a3) - 8000013c: 00000e93 li t4,0 - 80000140: 00400193 li gp,4 - 80000144: 01d71c63 bne a4,t4,8000015c - -0000000080000148 : - 80000148: 0006a783 lw a5,0(a3) - 8000014c: 00100e93 li t4,1 - 80000150: 00500193 li gp,5 - 80000154: 01d79463 bne a5,t4,8000015c - 80000158: 00301c63 bne zero,gp,80000170 - -000000008000015c : - 8000015c: 0ff0000f fence - 80000160: 00018063 beqz gp,80000160 - 80000164: 00119193 slli gp,gp,0x1 - 80000168: 0011e193 ori gp,gp,1 - 8000016c: 00000073 ecall - -0000000080000170 : - 80000170: 0ff0000f fence - 80000174: 00100193 li gp,1 - 80000178: 00000073 ecall - 8000017c: c0001073 unimp - 80000180: 0000 unimp - 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amomax_w.elf b/test/riscv/tests/rv64ua-p-amomax_w.elf deleted file mode 100644 index 59d12a1f..00000000 Binary files a/test/riscv/tests/rv64ua-p-amomax_w.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-p-amomaxu_d.dump b/test/riscv/tests/rv64ua-p-amomaxu_d.dump deleted file mode 100644 index 8492cd4d..00000000 --- a/test/riscv/tests/rv64ua-p-amomaxu_d.dump +++ /dev/null @@ -1,125 +0,0 @@ - -rv64ua-p-amomaxu_d: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 80000537 lui a0,0x80000 - 80000100: 80000593 li a1,-2048 - 80000104: 00002697 auipc a3,0x2 - 80000108: efc68693 addi a3,a3,-260 # 80002000 - 8000010c: 00a6b023 sd a0,0(a3) - 80000110: e0b6b72f amomaxu.d a4,a1,(a3) - 80000114: 80000eb7 lui t4,0x80000 - 80000118: 00200193 li gp,2 - 8000011c: 05d71063 bne a4,t4,8000015c - -0000000080000120 : - 80000120: 0006b783 ld a5,0(a3) - 80000124: 80000e93 li t4,-2048 - 80000128: 00300193 li gp,3 - 8000012c: 03d79863 bne a5,t4,8000015c - -0000000080000130 : - 80000130: fff00593 li a1,-1 - 80000134: 0006b023 sd zero,0(a3) - 80000138: e0b6b72f amomaxu.d a4,a1,(a3) - 8000013c: 00000e93 li t4,0 - 80000140: 00400193 li gp,4 - 80000144: 01d71c63 bne a4,t4,8000015c - -0000000080000148 : - 80000148: 0006b783 ld a5,0(a3) - 8000014c: fff00e93 li t4,-1 - 80000150: 00500193 li gp,5 - 80000154: 01d79463 bne a5,t4,8000015c - 80000158: 00301c63 bne zero,gp,80000170 - -000000008000015c : - 8000015c: 0ff0000f fence - 80000160: 00018063 beqz gp,80000160 - 80000164: 00119193 slli gp,gp,0x1 - 80000168: 0011e193 ori gp,gp,1 - 8000016c: 00000073 ecall - -0000000080000170 : - 80000170: 0ff0000f fence - 80000174: 00100193 li gp,1 - 80000178: 00000073 ecall - 8000017c: c0001073 unimp - 80000180: 0000 unimp - 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amomaxu_d.elf b/test/riscv/tests/rv64ua-p-amomaxu_d.elf deleted file mode 100644 index 4c13c12c..00000000 Binary files a/test/riscv/tests/rv64ua-p-amomaxu_d.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-p-amomaxu_w.dump b/test/riscv/tests/rv64ua-p-amomaxu_w.dump deleted file mode 100644 index 1f01067b..00000000 --- a/test/riscv/tests/rv64ua-p-amomaxu_w.dump +++ /dev/null @@ -1,125 +0,0 @@ - -rv64ua-p-amomaxu_w: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 80000537 lui a0,0x80000 - 80000100: 80000593 li a1,-2048 - 80000104: 00002697 auipc a3,0x2 - 80000108: efc68693 addi a3,a3,-260 # 80002000 - 8000010c: 00a6a023 sw a0,0(a3) - 80000110: e0b6a72f amomaxu.w a4,a1,(a3) - 80000114: 80000eb7 lui t4,0x80000 - 80000118: 00200193 li gp,2 - 8000011c: 05d71063 bne a4,t4,8000015c - -0000000080000120 : - 80000120: 0006a783 lw a5,0(a3) - 80000124: 80000e93 li t4,-2048 - 80000128: 00300193 li gp,3 - 8000012c: 03d79863 bne a5,t4,8000015c - -0000000080000130 : - 80000130: fff00593 li a1,-1 - 80000134: 0006a023 sw zero,0(a3) - 80000138: e0b6a72f amomaxu.w a4,a1,(a3) - 8000013c: 00000e93 li t4,0 - 80000140: 00400193 li gp,4 - 80000144: 01d71c63 bne a4,t4,8000015c - -0000000080000148 : - 80000148: 0006a783 lw a5,0(a3) - 8000014c: fff00e93 li t4,-1 - 80000150: 00500193 li gp,5 - 80000154: 01d79463 bne a5,t4,8000015c - 80000158: 00301c63 bne zero,gp,80000170 - -000000008000015c : - 8000015c: 0ff0000f fence - 80000160: 00018063 beqz gp,80000160 - 80000164: 00119193 slli gp,gp,0x1 - 80000168: 0011e193 ori gp,gp,1 - 8000016c: 00000073 ecall - -0000000080000170 : - 80000170: 0ff0000f fence - 80000174: 00100193 li gp,1 - 80000178: 00000073 ecall - 8000017c: c0001073 unimp - 80000180: 0000 unimp - 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amomaxu_w.elf b/test/riscv/tests/rv64ua-p-amomaxu_w.elf deleted file mode 100644 index 0c97a3a9..00000000 Binary files a/test/riscv/tests/rv64ua-p-amomaxu_w.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-p-amomin_d.dump b/test/riscv/tests/rv64ua-p-amomin_d.dump deleted file mode 100644 index a45ab4fd..00000000 --- a/test/riscv/tests/rv64ua-p-amomin_d.dump +++ /dev/null @@ -1,125 +0,0 @@ - -rv64ua-p-amomin_d: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 80000537 lui a0,0x80000 - 80000100: 80000593 li a1,-2048 - 80000104: 00002697 auipc a3,0x2 - 80000108: efc68693 addi a3,a3,-260 # 80002000 - 8000010c: 00a6b023 sd a0,0(a3) - 80000110: 80b6b72f amomin.d a4,a1,(a3) - 80000114: 80000eb7 lui t4,0x80000 - 80000118: 00200193 li gp,2 - 8000011c: 05d71063 bne a4,t4,8000015c - -0000000080000120 : - 80000120: 0006b783 ld a5,0(a3) - 80000124: 80000eb7 lui t4,0x80000 - 80000128: 00300193 li gp,3 - 8000012c: 03d79863 bne a5,t4,8000015c - -0000000080000130 : - 80000130: fff00593 li a1,-1 - 80000134: 0006b023 sd zero,0(a3) - 80000138: 80b6b72f amomin.d a4,a1,(a3) - 8000013c: 00000e93 li t4,0 - 80000140: 00400193 li gp,4 - 80000144: 01d71c63 bne a4,t4,8000015c - -0000000080000148 : - 80000148: 0006b783 ld a5,0(a3) - 8000014c: fff00e93 li t4,-1 - 80000150: 00500193 li gp,5 - 80000154: 01d79463 bne a5,t4,8000015c - 80000158: 00301c63 bne zero,gp,80000170 - -000000008000015c : - 8000015c: 0ff0000f fence - 80000160: 00018063 beqz gp,80000160 - 80000164: 00119193 slli gp,gp,0x1 - 80000168: 0011e193 ori gp,gp,1 - 8000016c: 00000073 ecall - -0000000080000170 : - 80000170: 0ff0000f fence - 80000174: 00100193 li gp,1 - 80000178: 00000073 ecall - 8000017c: c0001073 unimp - 80000180: 0000 unimp - 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amomin_d.elf b/test/riscv/tests/rv64ua-p-amomin_d.elf deleted file mode 100644 index 791c78fe..00000000 Binary files a/test/riscv/tests/rv64ua-p-amomin_d.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-p-amomin_w.dump b/test/riscv/tests/rv64ua-p-amomin_w.dump deleted file mode 100644 index b97ec5a8..00000000 --- a/test/riscv/tests/rv64ua-p-amomin_w.dump +++ /dev/null @@ -1,125 +0,0 @@ - -rv64ua-p-amomin_w: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 80000537 lui a0,0x80000 - 80000100: 80000593 li a1,-2048 - 80000104: 00002697 auipc a3,0x2 - 80000108: efc68693 addi a3,a3,-260 # 80002000 - 8000010c: 00a6a023 sw a0,0(a3) - 80000110: 80b6a72f amomin.w a4,a1,(a3) - 80000114: 80000eb7 lui t4,0x80000 - 80000118: 00200193 li gp,2 - 8000011c: 05d71063 bne a4,t4,8000015c - -0000000080000120 : - 80000120: 0006a783 lw a5,0(a3) - 80000124: 80000eb7 lui t4,0x80000 - 80000128: 00300193 li gp,3 - 8000012c: 03d79863 bne a5,t4,8000015c - -0000000080000130 : - 80000130: fff00593 li a1,-1 - 80000134: 0006a023 sw zero,0(a3) - 80000138: 80b6a72f amomin.w a4,a1,(a3) - 8000013c: 00000e93 li t4,0 - 80000140: 00400193 li gp,4 - 80000144: 01d71c63 bne a4,t4,8000015c - -0000000080000148 : - 80000148: 0006a783 lw a5,0(a3) - 8000014c: fff00e93 li t4,-1 - 80000150: 00500193 li gp,5 - 80000154: 01d79463 bne a5,t4,8000015c - 80000158: 00301c63 bne zero,gp,80000170 - -000000008000015c : - 8000015c: 0ff0000f fence - 80000160: 00018063 beqz gp,80000160 - 80000164: 00119193 slli gp,gp,0x1 - 80000168: 0011e193 ori gp,gp,1 - 8000016c: 00000073 ecall - -0000000080000170 : - 80000170: 0ff0000f fence - 80000174: 00100193 li gp,1 - 80000178: 00000073 ecall - 8000017c: c0001073 unimp - 80000180: 0000 unimp - 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amomin_w.elf b/test/riscv/tests/rv64ua-p-amomin_w.elf deleted file mode 100644 index 7bf86a36..00000000 Binary files a/test/riscv/tests/rv64ua-p-amomin_w.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-p-amominu_d.dump b/test/riscv/tests/rv64ua-p-amominu_d.dump deleted file mode 100644 index c4b90c66..00000000 --- a/test/riscv/tests/rv64ua-p-amominu_d.dump +++ /dev/null @@ -1,125 +0,0 @@ - -rv64ua-p-amominu_d: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 80000537 lui a0,0x80000 - 80000100: 80000593 li a1,-2048 - 80000104: 00002697 auipc a3,0x2 - 80000108: efc68693 addi a3,a3,-260 # 80002000 - 8000010c: 00a6b023 sd a0,0(a3) - 80000110: c0b6b72f amominu.d a4,a1,(a3) - 80000114: 80000eb7 lui t4,0x80000 - 80000118: 00200193 li gp,2 - 8000011c: 05d71063 bne a4,t4,8000015c - -0000000080000120 : - 80000120: 0006b783 ld a5,0(a3) - 80000124: 80000eb7 lui t4,0x80000 - 80000128: 00300193 li gp,3 - 8000012c: 03d79863 bne a5,t4,8000015c - -0000000080000130 : - 80000130: fff00593 li a1,-1 - 80000134: 0006b023 sd zero,0(a3) - 80000138: c0b6b72f amominu.d a4,a1,(a3) - 8000013c: 00000e93 li t4,0 - 80000140: 00400193 li gp,4 - 80000144: 01d71c63 bne a4,t4,8000015c - -0000000080000148 : - 80000148: 0006b783 ld a5,0(a3) - 8000014c: 00000e93 li t4,0 - 80000150: 00500193 li gp,5 - 80000154: 01d79463 bne a5,t4,8000015c - 80000158: 00301c63 bne zero,gp,80000170 - -000000008000015c : - 8000015c: 0ff0000f fence - 80000160: 00018063 beqz gp,80000160 - 80000164: 00119193 slli gp,gp,0x1 - 80000168: 0011e193 ori gp,gp,1 - 8000016c: 00000073 ecall - -0000000080000170 : - 80000170: 0ff0000f fence - 80000174: 00100193 li gp,1 - 80000178: 00000073 ecall - 8000017c: c0001073 unimp - 80000180: 0000 unimp - 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amominu_d.elf b/test/riscv/tests/rv64ua-p-amominu_d.elf deleted file mode 100644 index 1c6d6adb..00000000 Binary files a/test/riscv/tests/rv64ua-p-amominu_d.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-p-amominu_w.dump b/test/riscv/tests/rv64ua-p-amominu_w.dump deleted file mode 100644 index 7a80790f..00000000 --- a/test/riscv/tests/rv64ua-p-amominu_w.dump +++ /dev/null @@ -1,125 +0,0 @@ - -rv64ua-p-amominu_w: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 80000537 lui a0,0x80000 - 80000100: 80000593 li a1,-2048 - 80000104: 00002697 auipc a3,0x2 - 80000108: efc68693 addi a3,a3,-260 # 80002000 - 8000010c: 00a6a023 sw a0,0(a3) - 80000110: c0b6a72f amominu.w a4,a1,(a3) - 80000114: 80000eb7 lui t4,0x80000 - 80000118: 00200193 li gp,2 - 8000011c: 05d71063 bne a4,t4,8000015c - -0000000080000120 : - 80000120: 0006a783 lw a5,0(a3) - 80000124: 80000eb7 lui t4,0x80000 - 80000128: 00300193 li gp,3 - 8000012c: 03d79863 bne a5,t4,8000015c - -0000000080000130 : - 80000130: fff00593 li a1,-1 - 80000134: 0006a023 sw zero,0(a3) - 80000138: c0b6a72f amominu.w a4,a1,(a3) - 8000013c: 00000e93 li t4,0 - 80000140: 00400193 li gp,4 - 80000144: 01d71c63 bne a4,t4,8000015c - -0000000080000148 : - 80000148: 0006a783 lw a5,0(a3) - 8000014c: 00000e93 li t4,0 - 80000150: 00500193 li gp,5 - 80000154: 01d79463 bne a5,t4,8000015c - 80000158: 00301c63 bne zero,gp,80000170 - -000000008000015c : - 8000015c: 0ff0000f fence - 80000160: 00018063 beqz gp,80000160 - 80000164: 00119193 slli gp,gp,0x1 - 80000168: 0011e193 ori gp,gp,1 - 8000016c: 00000073 ecall - -0000000080000170 : - 80000170: 0ff0000f fence - 80000174: 00100193 li gp,1 - 80000178: 00000073 ecall - 8000017c: c0001073 unimp - 80000180: 0000 unimp - 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amominu_w.elf b/test/riscv/tests/rv64ua-p-amominu_w.elf deleted file mode 100644 index af14db97..00000000 Binary files a/test/riscv/tests/rv64ua-p-amominu_w.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-p-amoor_d.dump b/test/riscv/tests/rv64ua-p-amoor_d.dump deleted file mode 100644 index 0248704e..00000000 --- a/test/riscv/tests/rv64ua-p-amoor_d.dump +++ /dev/null @@ -1,126 +0,0 @@ - -rv64ua-p-amoor_d: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 80000537 lui a0,0x80000 - 80000100: 80000593 li a1,-2048 - 80000104: 00002697 auipc a3,0x2 - 80000108: efc68693 addi a3,a3,-260 # 80002000 - 8000010c: 00a6b023 sd a0,0(a3) - 80000110: 40b6b72f amoor.d a4,a1,(a3) - 80000114: 80000eb7 lui t4,0x80000 - 80000118: 00200193 li gp,2 - 8000011c: 03d71e63 bne a4,t4,80000158 - -0000000080000120 : - 80000120: 0006b783 ld a5,0(a3) - 80000124: 80000e93 li t4,-2048 - 80000128: 00300193 li gp,3 - 8000012c: 03d79663 bne a5,t4,80000158 - -0000000080000130 : - 80000130: 00100593 li a1,1 - 80000134: 40b6b72f amoor.d a4,a1,(a3) - 80000138: 80000e93 li t4,-2048 - 8000013c: 00400193 li gp,4 - 80000140: 01d71c63 bne a4,t4,80000158 - -0000000080000144 : - 80000144: 0006b783 ld a5,0(a3) - 80000148: 80100e93 li t4,-2047 - 8000014c: 00500193 li gp,5 - 80000150: 01d79463 bne a5,t4,80000158 - 80000154: 00301c63 bne zero,gp,8000016c - -0000000080000158 : - 80000158: 0ff0000f fence - 8000015c: 00018063 beqz gp,8000015c - 80000160: 00119193 slli gp,gp,0x1 - 80000164: 0011e193 ori gp,gp,1 - 80000168: 00000073 ecall - -000000008000016c : - 8000016c: 0ff0000f fence - 80000170: 00100193 li gp,1 - 80000174: 00000073 ecall - 80000178: c0001073 unimp - 8000017c: 0000 unimp - 8000017e: 0000 unimp - 80000180: 0000 unimp - 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amoor_d.elf b/test/riscv/tests/rv64ua-p-amoor_d.elf deleted file mode 100644 index a00b97c5..00000000 Binary files a/test/riscv/tests/rv64ua-p-amoor_d.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-p-amoor_w.dump b/test/riscv/tests/rv64ua-p-amoor_w.dump deleted file mode 100644 index d20d20a6..00000000 --- a/test/riscv/tests/rv64ua-p-amoor_w.dump +++ /dev/null @@ -1,126 +0,0 @@ - -rv64ua-p-amoor_w: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 80000537 lui a0,0x80000 - 80000100: 80000593 li a1,-2048 - 80000104: 00002697 auipc a3,0x2 - 80000108: efc68693 addi a3,a3,-260 # 80002000 - 8000010c: 00a6a023 sw a0,0(a3) - 80000110: 40b6a72f amoor.w a4,a1,(a3) - 80000114: 80000eb7 lui t4,0x80000 - 80000118: 00200193 li gp,2 - 8000011c: 03d71e63 bne a4,t4,80000158 - -0000000080000120 : - 80000120: 0006a783 lw a5,0(a3) - 80000124: 80000e93 li t4,-2048 - 80000128: 00300193 li gp,3 - 8000012c: 03d79663 bne a5,t4,80000158 - -0000000080000130 : - 80000130: 00100593 li a1,1 - 80000134: 40b6a72f amoor.w a4,a1,(a3) - 80000138: 80000e93 li t4,-2048 - 8000013c: 00400193 li gp,4 - 80000140: 01d71c63 bne a4,t4,80000158 - -0000000080000144 : - 80000144: 0006a783 lw a5,0(a3) - 80000148: 80100e93 li t4,-2047 - 8000014c: 00500193 li gp,5 - 80000150: 01d79463 bne a5,t4,80000158 - 80000154: 00301c63 bne zero,gp,8000016c - -0000000080000158 : - 80000158: 0ff0000f fence - 8000015c: 00018063 beqz gp,8000015c - 80000160: 00119193 slli gp,gp,0x1 - 80000164: 0011e193 ori gp,gp,1 - 80000168: 00000073 ecall - -000000008000016c : - 8000016c: 0ff0000f fence - 80000170: 00100193 li gp,1 - 80000174: 00000073 ecall - 80000178: c0001073 unimp - 8000017c: 0000 unimp - 8000017e: 0000 unimp - 80000180: 0000 unimp - 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amoor_w.elf b/test/riscv/tests/rv64ua-p-amoor_w.elf deleted file mode 100644 index e35c29f2..00000000 Binary files a/test/riscv/tests/rv64ua-p-amoor_w.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-p-amoswap_d.dump b/test/riscv/tests/rv64ua-p-amoswap_d.dump deleted file mode 100644 index f61e23bd..00000000 --- a/test/riscv/tests/rv64ua-p-amoswap_d.dump +++ /dev/null @@ -1,124 +0,0 @@ - -rv64ua-p-amoswap_d: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 80000537 lui a0,0x80000 - 80000100: 80000593 li a1,-2048 - 80000104: 00002697 auipc a3,0x2 - 80000108: efc68693 addi a3,a3,-260 # 80002000 - 8000010c: 00a6b023 sd a0,0(a3) - 80000110: 08b6b72f amoswap.d a4,a1,(a3) - 80000114: 80000eb7 lui t4,0x80000 - 80000118: 00200193 li gp,2 - 8000011c: 05d71263 bne a4,t4,80000160 - -0000000080000120 : - 80000120: 0006b783 ld a5,0(a3) - 80000124: 80000e93 li t4,-2048 - 80000128: 00300193 li gp,3 - 8000012c: 03d79a63 bne a5,t4,80000160 - -0000000080000130 : - 80000130: 0010059b addiw a1,zero,1 - 80000134: 01f59593 slli a1,a1,0x1f - 80000138: 08b6b72f amoswap.d a4,a1,(a3) - 8000013c: 80000e93 li t4,-2048 - 80000140: 00400193 li gp,4 - 80000144: 01d71e63 bne a4,t4,80000160 - -0000000080000148 : - 80000148: 0006b783 ld a5,0(a3) - 8000014c: 00100e9b addiw t4,zero,1 - 80000150: 01fe9e93 slli t4,t4,0x1f - 80000154: 00500193 li gp,5 - 80000158: 01d79463 bne a5,t4,80000160 - 8000015c: 00301c63 bne zero,gp,80000174 - -0000000080000160 : - 80000160: 0ff0000f fence - 80000164: 00018063 beqz gp,80000164 - 80000168: 00119193 slli gp,gp,0x1 - 8000016c: 0011e193 ori gp,gp,1 - 80000170: 00000073 ecall - -0000000080000174 : - 80000174: 0ff0000f fence - 80000178: 00100193 li gp,1 - 8000017c: 00000073 ecall - 80000180: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-p-amoswap_d.elf b/test/riscv/tests/rv64ua-p-amoswap_d.elf deleted file mode 100644 index 63d01a74..00000000 Binary files a/test/riscv/tests/rv64ua-p-amoswap_d.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-p-amoswap_w.dump b/test/riscv/tests/rv64ua-p-amoswap_w.dump deleted file mode 100644 index e43f3820..00000000 --- a/test/riscv/tests/rv64ua-p-amoswap_w.dump +++ /dev/null @@ -1,125 +0,0 @@ - -rv64ua-p-amoswap_w: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 80000537 lui a0,0x80000 - 80000100: 80000593 li a1,-2048 - 80000104: 00002697 auipc a3,0x2 - 80000108: efc68693 addi a3,a3,-260 # 80002000 - 8000010c: 00a6a023 sw a0,0(a3) - 80000110: 08b6a72f amoswap.w a4,a1,(a3) - 80000114: 80000eb7 lui t4,0x80000 - 80000118: 00200193 li gp,2 - 8000011c: 05d71063 bne a4,t4,8000015c - -0000000080000120 : - 80000120: 0006a783 lw a5,0(a3) - 80000124: 80000e93 li t4,-2048 - 80000128: 00300193 li gp,3 - 8000012c: 03d79863 bne a5,t4,8000015c - -0000000080000130 : - 80000130: 0010059b addiw a1,zero,1 - 80000134: 01f59593 slli a1,a1,0x1f - 80000138: 08b6a72f amoswap.w a4,a1,(a3) - 8000013c: 80000e93 li t4,-2048 - 80000140: 00400193 li gp,4 - 80000144: 01d71c63 bne a4,t4,8000015c - -0000000080000148 : - 80000148: 0006a783 lw a5,0(a3) - 8000014c: 80000eb7 lui t4,0x80000 - 80000150: 00500193 li gp,5 - 80000154: 01d79463 bne a5,t4,8000015c - 80000158: 00301c63 bne zero,gp,80000170 - -000000008000015c : - 8000015c: 0ff0000f fence - 80000160: 00018063 beqz gp,80000160 - 80000164: 00119193 slli gp,gp,0x1 - 80000168: 0011e193 ori gp,gp,1 - 8000016c: 00000073 ecall - -0000000080000170 : - 80000170: 0ff0000f fence - 80000174: 00100193 li gp,1 - 80000178: 00000073 ecall - 8000017c: c0001073 unimp - 80000180: 0000 unimp - 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amoswap_w.elf b/test/riscv/tests/rv64ua-p-amoswap_w.elf deleted file mode 100644 index 011d5e2f..00000000 Binary files a/test/riscv/tests/rv64ua-p-amoswap_w.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-p-amoxor_d.dump b/test/riscv/tests/rv64ua-p-amoxor_d.dump deleted file mode 100644 index 992a22e1..00000000 --- a/test/riscv/tests/rv64ua-p-amoxor_d.dump +++ /dev/null @@ -1,155 +0,0 @@ - -rv64ua-p-amoxor_d: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 80000537 lui a0,0x80000 - 80000100: 80000593 li a1,-2048 - 80000104: 00002697 auipc a3,0x2 - 80000108: efc68693 addi a3,a3,-260 # 80002000 - 8000010c: 00a6b023 sd a0,0(a3) - 80000110: 20b6b72f amoxor.d a4,a1,(a3) - 80000114: 80000eb7 lui t4,0x80000 - 80000118: 00200193 li gp,2 - 8000011c: 05d71463 bne a4,t4,80000164 - -0000000080000120 : - 80000120: 0006b783 ld a5,0(a3) - 80000124: 80000eb7 lui t4,0x80000 - 80000128: 800e8e9b addiw t4,t4,-2048 - 8000012c: 00300193 li gp,3 - 80000130: 03d79a63 bne a5,t4,80000164 - -0000000080000134 : - 80000134: 00100593 li a1,1 - 80000138: 20b6b72f amoxor.d a4,a1,(a3) - 8000013c: 80000eb7 lui t4,0x80000 - 80000140: 800e8e9b addiw t4,t4,-2048 - 80000144: 00400193 li gp,4 - 80000148: 01d71e63 bne a4,t4,80000164 - -000000008000014c : - 8000014c: 0006b783 ld a5,0(a3) - 80000150: 80000eb7 lui t4,0x80000 - 80000154: 801e8e9b addiw t4,t4,-2047 - 80000158: 00500193 li gp,5 - 8000015c: 01d79463 bne a5,t4,80000164 - 80000160: 00301c63 bne zero,gp,80000178 - -0000000080000164 : - 80000164: 0ff0000f fence - 80000168: 00018063 beqz gp,80000168 - 8000016c: 00119193 slli gp,gp,0x1 - 80000170: 0011e193 ori gp,gp,1 - 80000174: 00000073 ecall - -0000000080000178 : - 80000178: 0ff0000f fence - 8000017c: 00100193 li gp,1 - 80000180: 00000073 ecall - 80000184: c0001073 unimp - 80000188: 0000 unimp - 8000018a: 0000 unimp - 8000018c: 0000 unimp - 8000018e: 0000 unimp - 80000190: 0000 unimp - 80000192: 0000 unimp - 80000194: 0000 unimp - 80000196: 0000 unimp - 80000198: 0000 unimp - 8000019a: 0000 unimp - 8000019c: 0000 unimp - 8000019e: 0000 unimp - 800001a0: 0000 unimp - 800001a2: 0000 unimp - 800001a4: 0000 unimp - 800001a6: 0000 unimp - 800001a8: 0000 unimp - 800001aa: 0000 unimp - 800001ac: 0000 unimp - 800001ae: 0000 unimp - 800001b0: 0000 unimp - 800001b2: 0000 unimp - 800001b4: 0000 unimp - 800001b6: 0000 unimp - 800001b8: 0000 unimp - 800001ba: 0000 unimp - 800001bc: 0000 unimp - 800001be: 0000 unimp - 800001c0: 0000 unimp - 800001c2: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amoxor_d.elf b/test/riscv/tests/rv64ua-p-amoxor_d.elf deleted file mode 100644 index 4bec6cca..00000000 Binary files a/test/riscv/tests/rv64ua-p-amoxor_d.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-p-amoxor_w.dump b/test/riscv/tests/rv64ua-p-amoxor_w.dump deleted file mode 100644 index 6bca3f65..00000000 --- a/test/riscv/tests/rv64ua-p-amoxor_w.dump +++ /dev/null @@ -1,153 +0,0 @@ - -rv64ua-p-amoxor_w: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 80000537 lui a0,0x80000 - 80000100: 80000593 li a1,-2048 - 80000104: 00002697 auipc a3,0x2 - 80000108: efc68693 addi a3,a3,-260 # 80002000 - 8000010c: 00a6a023 sw a0,0(a3) - 80000110: 20b6a72f amoxor.w a4,a1,(a3) - 80000114: 80000eb7 lui t4,0x80000 - 80000118: 00200193 li gp,2 - 8000011c: 05d71863 bne a4,t4,8000016c - -0000000080000120 : - 80000120: 0006a783 lw a5,0(a3) - 80000124: 80000eb7 lui t4,0x80000 - 80000128: 800e8e9b addiw t4,t4,-2048 - 8000012c: 00300193 li gp,3 - 80000130: 03d79e63 bne a5,t4,8000016c - -0000000080000134 : - 80000134: 0030059b addiw a1,zero,3 - 80000138: 01e59593 slli a1,a1,0x1e - 8000013c: 00158593 addi a1,a1,1 - 80000140: 20b6a72f amoxor.w a4,a1,(a3) - 80000144: 80000eb7 lui t4,0x80000 - 80000148: 800e8e9b addiw t4,t4,-2048 - 8000014c: 00400193 li gp,4 - 80000150: 01d71e63 bne a4,t4,8000016c - -0000000080000154 : - 80000154: 0006a783 lw a5,0(a3) - 80000158: c0000eb7 lui t4,0xc0000 - 8000015c: 801e8e9b addiw t4,t4,-2047 - 80000160: 00500193 li gp,5 - 80000164: 01d79463 bne a5,t4,8000016c - 80000168: 00301c63 bne zero,gp,80000180 - -000000008000016c : - 8000016c: 0ff0000f fence - 80000170: 00018063 beqz gp,80000170 - 80000174: 00119193 slli gp,gp,0x1 - 80000178: 0011e193 ori gp,gp,1 - 8000017c: 00000073 ecall - -0000000080000180 : - 80000180: 0ff0000f fence - 80000184: 00100193 li gp,1 - 80000188: 00000073 ecall - 8000018c: c0001073 unimp - 80000190: 0000 unimp - 80000192: 0000 unimp - 80000194: 0000 unimp - 80000196: 0000 unimp - 80000198: 0000 unimp - 8000019a: 0000 unimp - 8000019c: 0000 unimp - 8000019e: 0000 unimp - 800001a0: 0000 unimp - 800001a2: 0000 unimp - 800001a4: 0000 unimp - 800001a6: 0000 unimp - 800001a8: 0000 unimp - 800001aa: 0000 unimp - 800001ac: 0000 unimp - 800001ae: 0000 unimp - 800001b0: 0000 unimp - 800001b2: 0000 unimp - 800001b4: 0000 unimp - 800001b6: 0000 unimp - 800001b8: 0000 unimp - 800001ba: 0000 unimp - 800001bc: 0000 unimp - 800001be: 0000 unimp - 800001c0: 0000 unimp - 800001c2: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amoxor_w.elf b/test/riscv/tests/rv64ua-p-amoxor_w.elf deleted file mode 100644 index 22e8ba98..00000000 Binary files a/test/riscv/tests/rv64ua-p-amoxor_w.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-p-lrsc.dump b/test/riscv/tests/rv64ua-p-lrsc.dump deleted file mode 100644 index bcca392e..00000000 --- a/test/riscv/tests/rv64ua-p-lrsc.dump +++ /dev/null @@ -1,691 +0,0 @@ - -rv64ua-p-lrsc: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - 800000fc: 00002517 auipc a0,0x2 - 80000100: f0450513 addi a0,a0,-252 # 80002000 - 80000104: 00100593 li a1,1 - 80000108: 00b5262f amoadd.w a2,a1,(a0) - 8000010c: 00100693 li a3,1 - 80000110: fed67ee3 bleu a3,a2,8000010c - 80000114: 00052583 lw a1,0(a0) - 80000118: fed5eee3 bltu a1,a3,80000114 - -000000008000011c : - 8000011c: 00002517 auipc a0,0x2 - 80000120: eec50513 addi a0,a0,-276 # 80002008 - 80000124: 1805272f sc.w a4,zero,(a0) - 80000128: 00100e93 li t4,1 - 8000012c: 00200193 li gp,2 - 80000130: 09d71a63 bne a4,t4,800001c4 - -0000000080000134 : - 80000134: 00002517 auipc a0,0x2 - 80000138: ed450513 addi a0,a0,-300 # 80002008 - 8000013c: 00002597 auipc a1,0x2 - 80000140: 2d058593 addi a1,a1,720 # 8000240c - 80000144: 1005a5af lr.w a1,(a1) - 80000148: 18b5272f sc.w a4,a1,(a0) - 8000014c: 00100e93 li t4,1 - 80000150: 00300193 li gp,3 - 80000154: 07d71863 bne a4,t4,800001c4 - 80000158: 00002517 auipc a0,0x2 - 8000015c: eb050513 addi a0,a0,-336 # 80002008 - 80000160: 40000593 li a1,1024 - 80000164: 00160613 addi a2,a2,1 - 80000168: 1005272f lr.w a4,(a0) - 8000016c: 00c70733 add a4,a4,a2 - 80000170: 18e5272f sc.w a4,a4,(a0) - 80000174: fe071ae3 bnez a4,80000168 - 80000178: fff58593 addi a1,a1,-1 - 8000017c: fe0596e3 bnez a1,80000168 - 80000180: 00002517 auipc a0,0x2 - 80000184: e8450513 addi a0,a0,-380 # 80002004 - 80000188: 00100593 li a1,1 - 8000018c: 00b5202f amoadd.w zero,a1,(a0) - 80000190: 00052583 lw a1,0(a0) - 80000194: fed5cee3 blt a1,a3,80000190 - 80000198: 0ff0000f fence - -000000008000019c : - 8000019c: 00002517 auipc a0,0x2 - 800001a0: e6c52503 lw a0,-404(a0) # 80002008 - 800001a4: 00969593 slli a1,a3,0x9 - 800001a8: 40b50533 sub a0,a0,a1 - 800001ac: fff68693 addi a3,a3,-1 - 800001b0: fe06dce3 bgez a3,800001a8 - 800001b4: 00000e93 li t4,0 - 800001b8: 00400193 li gp,4 - 800001bc: 01d51463 bne a0,t4,800001c4 - 800001c0: 00301c63 bne zero,gp,800001d8 - -00000000800001c4 : - 800001c4: 0ff0000f fence - 800001c8: 00018063 beqz gp,800001c8 - 800001cc: 00119193 slli gp,gp,0x1 - 800001d0: 0011e193 ori gp,gp,1 - 800001d4: 00000073 ecall - -00000000800001d8 : - 800001d8: 0ff0000f fence - 800001dc: 00100193 li gp,1 - 800001e0: 00000073 ecall - 800001e4: c0001073 unimp - 800001e8: 0000 unimp - 800001ea: 0000 unimp - 800001ec: 0000 unimp - 800001ee: 0000 unimp - 800001f0: 0000 unimp - 800001f2: 0000 unimp - 800001f4: 0000 unimp - 800001f6: 0000 unimp - 800001f8: 0000 unimp - 800001fa: 0000 unimp - 800001fc: 0000 unimp - 800001fe: 0000 unimp - 80000200: 0000 unimp - 80000202: 0000 unimp - -Disassembly of section .data: - -0000000080002000 : - 80002000: 0000 unimp - 80002002: 0000 unimp - -0000000080002004 : - 80002004: 0000 unimp - 80002006: 0000 unimp - -0000000080002008 : - 80002008: 0000 unimp - 8000200a: 0000 unimp - 8000200c: 0000 unimp - 8000200e: 0000 unimp - 80002010: 0000 unimp - 80002012: 0000 unimp - 80002014: 0000 unimp - 80002016: 0000 unimp - 80002018: 0000 unimp - 8000201a: 0000 unimp - 8000201c: 0000 unimp - 8000201e: 0000 unimp - 80002020: 0000 unimp - 80002022: 0000 unimp - 80002024: 0000 unimp - 80002026: 0000 unimp - 80002028: 0000 unimp - 8000202a: 0000 unimp - 8000202c: 0000 unimp - 8000202e: 0000 unimp - 80002030: 0000 unimp - 80002032: 0000 unimp - 80002034: 0000 unimp - 80002036: 0000 unimp - 80002038: 0000 unimp - 8000203a: 0000 unimp - 8000203c: 0000 unimp - 8000203e: 0000 unimp - 80002040: 0000 unimp - 80002042: 0000 unimp - 80002044: 0000 unimp - 80002046: 0000 unimp - 80002048: 0000 unimp - 8000204a: 0000 unimp - 8000204c: 0000 unimp - 8000204e: 0000 unimp - 80002050: 0000 unimp - 80002052: 0000 unimp - 80002054: 0000 unimp - 80002056: 0000 unimp - 80002058: 0000 unimp - 8000205a: 0000 unimp - 8000205c: 0000 unimp - 8000205e: 0000 unimp - 80002060: 0000 unimp - 80002062: 0000 unimp - 80002064: 0000 unimp - 80002066: 0000 unimp - 80002068: 0000 unimp - 8000206a: 0000 unimp - 8000206c: 0000 unimp - 8000206e: 0000 unimp - 80002070: 0000 unimp - 80002072: 0000 unimp - 80002074: 0000 unimp - 80002076: 0000 unimp - 80002078: 0000 unimp - 8000207a: 0000 unimp - 8000207c: 0000 unimp - 8000207e: 0000 unimp - 80002080: 0000 unimp - 80002082: 0000 unimp - 80002084: 0000 unimp - 80002086: 0000 unimp - 80002088: 0000 unimp - 8000208a: 0000 unimp - 8000208c: 0000 unimp - 8000208e: 0000 unimp - 80002090: 0000 unimp - 80002092: 0000 unimp - 80002094: 0000 unimp - 80002096: 0000 unimp - 80002098: 0000 unimp - 8000209a: 0000 unimp - 8000209c: 0000 unimp - 8000209e: 0000 unimp - 800020a0: 0000 unimp - 800020a2: 0000 unimp - 800020a4: 0000 unimp - 800020a6: 0000 unimp - 800020a8: 0000 unimp - 800020aa: 0000 unimp - 800020ac: 0000 unimp - 800020ae: 0000 unimp - 800020b0: 0000 unimp - 800020b2: 0000 unimp - 800020b4: 0000 unimp - 800020b6: 0000 unimp - 800020b8: 0000 unimp - 800020ba: 0000 unimp - 800020bc: 0000 unimp - 800020be: 0000 unimp - 800020c0: 0000 unimp - 800020c2: 0000 unimp - 800020c4: 0000 unimp - 800020c6: 0000 unimp - 800020c8: 0000 unimp - 800020ca: 0000 unimp - 800020cc: 0000 unimp - 800020ce: 0000 unimp - 800020d0: 0000 unimp - 800020d2: 0000 unimp - 800020d4: 0000 unimp - 800020d6: 0000 unimp - 800020d8: 0000 unimp - 800020da: 0000 unimp - 800020dc: 0000 unimp - 800020de: 0000 unimp - 800020e0: 0000 unimp - 800020e2: 0000 unimp - 800020e4: 0000 unimp - 800020e6: 0000 unimp - 800020e8: 0000 unimp - 800020ea: 0000 unimp - 800020ec: 0000 unimp - 800020ee: 0000 unimp - 800020f0: 0000 unimp - 800020f2: 0000 unimp - 800020f4: 0000 unimp - 800020f6: 0000 unimp - 800020f8: 0000 unimp - 800020fa: 0000 unimp - 800020fc: 0000 unimp - 800020fe: 0000 unimp - 80002100: 0000 unimp - 80002102: 0000 unimp - 80002104: 0000 unimp - 80002106: 0000 unimp - 80002108: 0000 unimp - 8000210a: 0000 unimp - 8000210c: 0000 unimp - 8000210e: 0000 unimp - 80002110: 0000 unimp - 80002112: 0000 unimp - 80002114: 0000 unimp - 80002116: 0000 unimp - 80002118: 0000 unimp - 8000211a: 0000 unimp - 8000211c: 0000 unimp - 8000211e: 0000 unimp - 80002120: 0000 unimp - 80002122: 0000 unimp - 80002124: 0000 unimp - 80002126: 0000 unimp - 80002128: 0000 unimp - 8000212a: 0000 unimp - 8000212c: 0000 unimp - 8000212e: 0000 unimp - 80002130: 0000 unimp - 80002132: 0000 unimp - 80002134: 0000 unimp - 80002136: 0000 unimp - 80002138: 0000 unimp - 8000213a: 0000 unimp - 8000213c: 0000 unimp - 8000213e: 0000 unimp - 80002140: 0000 unimp - 80002142: 0000 unimp - 80002144: 0000 unimp - 80002146: 0000 unimp - 80002148: 0000 unimp - 8000214a: 0000 unimp - 8000214c: 0000 unimp - 8000214e: 0000 unimp - 80002150: 0000 unimp - 80002152: 0000 unimp - 80002154: 0000 unimp - 80002156: 0000 unimp - 80002158: 0000 unimp - 8000215a: 0000 unimp - 8000215c: 0000 unimp - 8000215e: 0000 unimp - 80002160: 0000 unimp - 80002162: 0000 unimp - 80002164: 0000 unimp - 80002166: 0000 unimp - 80002168: 0000 unimp - 8000216a: 0000 unimp - 8000216c: 0000 unimp - 8000216e: 0000 unimp - 80002170: 0000 unimp - 80002172: 0000 unimp - 80002174: 0000 unimp - 80002176: 0000 unimp - 80002178: 0000 unimp - 8000217a: 0000 unimp - 8000217c: 0000 unimp - 8000217e: 0000 unimp - 80002180: 0000 unimp - 80002182: 0000 unimp - 80002184: 0000 unimp - 80002186: 0000 unimp - 80002188: 0000 unimp - 8000218a: 0000 unimp - 8000218c: 0000 unimp - 8000218e: 0000 unimp - 80002190: 0000 unimp - 80002192: 0000 unimp - 80002194: 0000 unimp - 80002196: 0000 unimp - 80002198: 0000 unimp - 8000219a: 0000 unimp - 8000219c: 0000 unimp - 8000219e: 0000 unimp - 800021a0: 0000 unimp - 800021a2: 0000 unimp - 800021a4: 0000 unimp - 800021a6: 0000 unimp - 800021a8: 0000 unimp - 800021aa: 0000 unimp - 800021ac: 0000 unimp - 800021ae: 0000 unimp - 800021b0: 0000 unimp - 800021b2: 0000 unimp - 800021b4: 0000 unimp - 800021b6: 0000 unimp - 800021b8: 0000 unimp - 800021ba: 0000 unimp - 800021bc: 0000 unimp - 800021be: 0000 unimp - 800021c0: 0000 unimp - 800021c2: 0000 unimp - 800021c4: 0000 unimp - 800021c6: 0000 unimp - 800021c8: 0000 unimp - 800021ca: 0000 unimp - 800021cc: 0000 unimp - 800021ce: 0000 unimp - 800021d0: 0000 unimp - 800021d2: 0000 unimp - 800021d4: 0000 unimp - 800021d6: 0000 unimp - 800021d8: 0000 unimp - 800021da: 0000 unimp - 800021dc: 0000 unimp - 800021de: 0000 unimp - 800021e0: 0000 unimp - 800021e2: 0000 unimp - 800021e4: 0000 unimp - 800021e6: 0000 unimp - 800021e8: 0000 unimp - 800021ea: 0000 unimp - 800021ec: 0000 unimp - 800021ee: 0000 unimp - 800021f0: 0000 unimp - 800021f2: 0000 unimp - 800021f4: 0000 unimp - 800021f6: 0000 unimp - 800021f8: 0000 unimp - 800021fa: 0000 unimp - 800021fc: 0000 unimp - 800021fe: 0000 unimp - 80002200: 0000 unimp - 80002202: 0000 unimp - 80002204: 0000 unimp - 80002206: 0000 unimp - 80002208: 0000 unimp - 8000220a: 0000 unimp - 8000220c: 0000 unimp - 8000220e: 0000 unimp - 80002210: 0000 unimp - 80002212: 0000 unimp - 80002214: 0000 unimp - 80002216: 0000 unimp - 80002218: 0000 unimp - 8000221a: 0000 unimp - 8000221c: 0000 unimp - 8000221e: 0000 unimp - 80002220: 0000 unimp - 80002222: 0000 unimp - 80002224: 0000 unimp - 80002226: 0000 unimp - 80002228: 0000 unimp - 8000222a: 0000 unimp - 8000222c: 0000 unimp - 8000222e: 0000 unimp - 80002230: 0000 unimp - 80002232: 0000 unimp - 80002234: 0000 unimp - 80002236: 0000 unimp - 80002238: 0000 unimp - 8000223a: 0000 unimp - 8000223c: 0000 unimp - 8000223e: 0000 unimp - 80002240: 0000 unimp - 80002242: 0000 unimp - 80002244: 0000 unimp - 80002246: 0000 unimp - 80002248: 0000 unimp - 8000224a: 0000 unimp - 8000224c: 0000 unimp - 8000224e: 0000 unimp - 80002250: 0000 unimp - 80002252: 0000 unimp - 80002254: 0000 unimp - 80002256: 0000 unimp - 80002258: 0000 unimp - 8000225a: 0000 unimp - 8000225c: 0000 unimp - 8000225e: 0000 unimp - 80002260: 0000 unimp - 80002262: 0000 unimp - 80002264: 0000 unimp - 80002266: 0000 unimp - 80002268: 0000 unimp - 8000226a: 0000 unimp - 8000226c: 0000 unimp - 8000226e: 0000 unimp - 80002270: 0000 unimp - 80002272: 0000 unimp - 80002274: 0000 unimp - 80002276: 0000 unimp - 80002278: 0000 unimp - 8000227a: 0000 unimp - 8000227c: 0000 unimp - 8000227e: 0000 unimp - 80002280: 0000 unimp - 80002282: 0000 unimp - 80002284: 0000 unimp - 80002286: 0000 unimp - 80002288: 0000 unimp - 8000228a: 0000 unimp - 8000228c: 0000 unimp - 8000228e: 0000 unimp - 80002290: 0000 unimp - 80002292: 0000 unimp - 80002294: 0000 unimp - 80002296: 0000 unimp - 80002298: 0000 unimp - 8000229a: 0000 unimp - 8000229c: 0000 unimp - 8000229e: 0000 unimp - 800022a0: 0000 unimp - 800022a2: 0000 unimp - 800022a4: 0000 unimp - 800022a6: 0000 unimp - 800022a8: 0000 unimp - 800022aa: 0000 unimp - 800022ac: 0000 unimp - 800022ae: 0000 unimp - 800022b0: 0000 unimp - 800022b2: 0000 unimp - 800022b4: 0000 unimp - 800022b6: 0000 unimp - 800022b8: 0000 unimp - 800022ba: 0000 unimp - 800022bc: 0000 unimp - 800022be: 0000 unimp - 800022c0: 0000 unimp - 800022c2: 0000 unimp - 800022c4: 0000 unimp - 800022c6: 0000 unimp - 800022c8: 0000 unimp - 800022ca: 0000 unimp - 800022cc: 0000 unimp - 800022ce: 0000 unimp - 800022d0: 0000 unimp - 800022d2: 0000 unimp - 800022d4: 0000 unimp - 800022d6: 0000 unimp - 800022d8: 0000 unimp - 800022da: 0000 unimp - 800022dc: 0000 unimp - 800022de: 0000 unimp - 800022e0: 0000 unimp - 800022e2: 0000 unimp - 800022e4: 0000 unimp - 800022e6: 0000 unimp - 800022e8: 0000 unimp - 800022ea: 0000 unimp - 800022ec: 0000 unimp - 800022ee: 0000 unimp - 800022f0: 0000 unimp - 800022f2: 0000 unimp - 800022f4: 0000 unimp - 800022f6: 0000 unimp - 800022f8: 0000 unimp - 800022fa: 0000 unimp - 800022fc: 0000 unimp - 800022fe: 0000 unimp - 80002300: 0000 unimp - 80002302: 0000 unimp - 80002304: 0000 unimp - 80002306: 0000 unimp - 80002308: 0000 unimp - 8000230a: 0000 unimp - 8000230c: 0000 unimp - 8000230e: 0000 unimp - 80002310: 0000 unimp - 80002312: 0000 unimp - 80002314: 0000 unimp - 80002316: 0000 unimp - 80002318: 0000 unimp - 8000231a: 0000 unimp - 8000231c: 0000 unimp - 8000231e: 0000 unimp - 80002320: 0000 unimp - 80002322: 0000 unimp - 80002324: 0000 unimp - 80002326: 0000 unimp - 80002328: 0000 unimp - 8000232a: 0000 unimp - 8000232c: 0000 unimp - 8000232e: 0000 unimp - 80002330: 0000 unimp - 80002332: 0000 unimp - 80002334: 0000 unimp - 80002336: 0000 unimp - 80002338: 0000 unimp - 8000233a: 0000 unimp - 8000233c: 0000 unimp - 8000233e: 0000 unimp - 80002340: 0000 unimp - 80002342: 0000 unimp - 80002344: 0000 unimp - 80002346: 0000 unimp - 80002348: 0000 unimp - 8000234a: 0000 unimp - 8000234c: 0000 unimp - 8000234e: 0000 unimp - 80002350: 0000 unimp - 80002352: 0000 unimp - 80002354: 0000 unimp - 80002356: 0000 unimp - 80002358: 0000 unimp - 8000235a: 0000 unimp - 8000235c: 0000 unimp - 8000235e: 0000 unimp - 80002360: 0000 unimp - 80002362: 0000 unimp - 80002364: 0000 unimp - 80002366: 0000 unimp - 80002368: 0000 unimp - 8000236a: 0000 unimp - 8000236c: 0000 unimp - 8000236e: 0000 unimp - 80002370: 0000 unimp - 80002372: 0000 unimp - 80002374: 0000 unimp - 80002376: 0000 unimp - 80002378: 0000 unimp - 8000237a: 0000 unimp - 8000237c: 0000 unimp - 8000237e: 0000 unimp - 80002380: 0000 unimp - 80002382: 0000 unimp - 80002384: 0000 unimp - 80002386: 0000 unimp - 80002388: 0000 unimp - 8000238a: 0000 unimp - 8000238c: 0000 unimp - 8000238e: 0000 unimp - 80002390: 0000 unimp - 80002392: 0000 unimp - 80002394: 0000 unimp - 80002396: 0000 unimp - 80002398: 0000 unimp - 8000239a: 0000 unimp - 8000239c: 0000 unimp - 8000239e: 0000 unimp - 800023a0: 0000 unimp - 800023a2: 0000 unimp - 800023a4: 0000 unimp - 800023a6: 0000 unimp - 800023a8: 0000 unimp - 800023aa: 0000 unimp - 800023ac: 0000 unimp - 800023ae: 0000 unimp - 800023b0: 0000 unimp - 800023b2: 0000 unimp - 800023b4: 0000 unimp - 800023b6: 0000 unimp - 800023b8: 0000 unimp - 800023ba: 0000 unimp - 800023bc: 0000 unimp - 800023be: 0000 unimp - 800023c0: 0000 unimp - 800023c2: 0000 unimp - 800023c4: 0000 unimp - 800023c6: 0000 unimp - 800023c8: 0000 unimp - 800023ca: 0000 unimp - 800023cc: 0000 unimp - 800023ce: 0000 unimp - 800023d0: 0000 unimp - 800023d2: 0000 unimp - 800023d4: 0000 unimp - 800023d6: 0000 unimp - 800023d8: 0000 unimp - 800023da: 0000 unimp - 800023dc: 0000 unimp - 800023de: 0000 unimp - 800023e0: 0000 unimp - 800023e2: 0000 unimp - 800023e4: 0000 unimp - 800023e6: 0000 unimp - 800023e8: 0000 unimp - 800023ea: 0000 unimp - 800023ec: 0000 unimp - 800023ee: 0000 unimp - 800023f0: 0000 unimp - 800023f2: 0000 unimp - 800023f4: 0000 unimp - 800023f6: 0000 unimp - 800023f8: 0000 unimp - 800023fa: 0000 unimp - 800023fc: 0000 unimp - 800023fe: 0000 unimp - 80002400: 0000 unimp - 80002402: 0000 unimp - 80002404: 0000 unimp - 80002406: 0000 unimp - 80002408: 0000 unimp - 8000240a: 0000 unimp - -000000008000240c : - 8000240c: 0000 unimp - 8000240e: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-lrsc.elf b/test/riscv/tests/rv64ua-p-lrsc.elf deleted file mode 100755 index 0fb5b44e..00000000 Binary files a/test/riscv/tests/rv64ua-p-lrsc.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-v-amoadd_d.dump b/test/riscv/tests/rv64ua-v-amoadd_d.dump deleted file mode 100644 index 6e2c6142..00000000 --- a/test/riscv/tests/rv64ua-v-amoadd_d.dump +++ /dev/null @@ -1,874 +0,0 @@ - -rv64ua-v-amoadd_d: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 70068693 addi a3,a3,1792 # 80002b58 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 73460613 addi a2,a2,1844 # 80002be8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6fc60613 addi a2,a2,1788 # 80002c00 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 64c68693 addi a3,a3,1612 # 80002ba0 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 66868693 addi a3,a3,1640 # 80002cd8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5e860613 addi a2,a2,1512 # 80002cb0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 51c68693 addi a3,a3,1308 # 80002d08 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 43c68693 addi a3,a3,1084 # 80002c78 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 3cc68693 addi a3,a3,972 # 80002c40 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 03e00793 li a5,62 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0f6267b7 lui a5,0xf626 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 79178793 addi a5,a5,1937 # f626791 <_start-0x709d986f> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 80000537 lui a0,0x80000 - 80002acc: 80000593 li a1,-2048 - 80002ad0: 00000697 auipc a3,0x0 - 80002ad4: 53068693 addi a3,a3,1328 # 80003000 - 80002ad8: 00a6b023 sd a0,0(a3) - 80002adc: 00b6b72f amoadd.d a4,a1,(a3) - 80002ae0: 80000eb7 lui t4,0x80000 - 80002ae4: 00200193 li gp,2 - 80002ae8: 05d71863 bne a4,t4,80002b38 - -0000000080002aec : - 80002aec: 0006b783 ld a5,0(a3) - 80002af0: fff00e9b addiw t4,zero,-1 - 80002af4: 01fe9e93 slli t4,t4,0x1f - 80002af8: 800e8e93 addi t4,t4,-2048 # ffffffff7ffff800 <_end+0xfffffffeffff7010> - 80002afc: 00300193 li gp,3 - 80002b00: 03d79c63 bne a5,t4,80002b38 - -0000000080002b04 : - 80002b04: 00b6b72f amoadd.d a4,a1,(a3) - 80002b08: fff00e9b addiw t4,zero,-1 - 80002b0c: 01fe9e93 slli t4,t4,0x1f - 80002b10: 800e8e93 addi t4,t4,-2048 - 80002b14: 00400193 li gp,4 - 80002b18: 03d71063 bne a4,t4,80002b38 - -0000000080002b1c : - 80002b1c: 0006b783 ld a5,0(a3) - 80002b20: fff80eb7 lui t4,0xfff80 - 80002b24: fffe8e9b addiw t4,t4,-1 - 80002b28: 00ce9e93 slli t4,t4,0xc - 80002b2c: 00500193 li gp,5 - 80002b30: 01d79463 bne a5,t4,80002b38 - 80002b34: 00301a63 bne zero,gp,80002b48 - -0000000080002b38 : - 80002b38: 00119513 slli a0,gp,0x1 - 80002b3c: 00050063 beqz a0,80002b3c - 80002b40: 00156513 ori a0,a0,1 - 80002b44: 00000073 ecall - -0000000080002b48 : - 80002b48: 00100513 li a0,1 - 80002b4c: 00000073 ecall - 80002b50: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amoadd_d.elf b/test/riscv/tests/rv64ua-v-amoadd_d.elf deleted file mode 100644 index 655f27c6..00000000 Binary files a/test/riscv/tests/rv64ua-v-amoadd_d.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-v-amoadd_w.dump b/test/riscv/tests/rv64ua-v-amoadd_w.dump deleted file mode 100644 index b8ca9c8d..00000000 --- a/test/riscv/tests/rv64ua-v-amoadd_w.dump +++ /dev/null @@ -1,871 +0,0 @@ - -rv64ua-v-amoadd_w: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 63c68693 addi a3,a3,1596 # 80002b90 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 65868693 addi a3,a3,1624 # 80002cc8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 42c68693 addi a3,a3,1068 # 80002c68 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 3bc68693 addi a3,a3,956 # 80002c30 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 00100793 li a5,1 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0806d7b7 lui a5,0x806d - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 4f578793 addi a5,a5,1269 # 806d4f5 <_start-0x77f92b0b> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 80000537 lui a0,0x80000 - 80002acc: 80000593 li a1,-2048 - 80002ad0: 00000697 auipc a3,0x0 - 80002ad4: 53068693 addi a3,a3,1328 # 80003000 - 80002ad8: 00a6a023 sw a0,0(a3) - 80002adc: 00b6a72f amoadd.w a4,a1,(a3) - 80002ae0: 80000eb7 lui t4,0x80000 - 80002ae4: 00200193 li gp,2 - 80002ae8: 05d71263 bne a4,t4,80002b2c - -0000000080002aec : - 80002aec: 0006a783 lw a5,0(a3) - 80002af0: 80000eb7 lui t4,0x80000 - 80002af4: 800e8e9b addiw t4,t4,-2048 - 80002af8: 00300193 li gp,3 - 80002afc: 03d79863 bne a5,t4,80002b2c - -0000000080002b00 : - 80002b00: 800005b7 lui a1,0x80000 - 80002b04: 00b6a72f amoadd.w a4,a1,(a3) - 80002b08: 80000eb7 lui t4,0x80000 - 80002b0c: 800e8e9b addiw t4,t4,-2048 - 80002b10: 00400193 li gp,4 - 80002b14: 01d71c63 bne a4,t4,80002b2c - -0000000080002b18 : - 80002b18: 0006a783 lw a5,0(a3) - 80002b1c: 80000e93 li t4,-2048 - 80002b20: 00500193 li gp,5 - 80002b24: 01d79463 bne a5,t4,80002b2c - 80002b28: 00301a63 bne zero,gp,80002b3c - -0000000080002b2c : - 80002b2c: 00119513 slli a0,gp,0x1 - 80002b30: 00050063 beqz a0,80002b30 - 80002b34: 00156513 ori a0,a0,1 - 80002b38: 00000073 ecall - -0000000080002b3c : - 80002b3c: 00100513 li a0,1 - 80002b40: 00000073 ecall - 80002b44: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amoadd_w.elf b/test/riscv/tests/rv64ua-v-amoadd_w.elf deleted file mode 100644 index 32d6c1a9..00000000 Binary files a/test/riscv/tests/rv64ua-v-amoadd_w.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-v-amoand_d.dump b/test/riscv/tests/rv64ua-v-amoand_d.dump deleted file mode 100644 index 89e47221..00000000 --- a/test/riscv/tests/rv64ua-v-amoand_d.dump +++ /dev/null @@ -1,871 +0,0 @@ - -rv64ua-v-amoand_d: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 63c68693 addi a3,a3,1596 # 80002b90 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 65868693 addi a3,a3,1624 # 80002cc8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 42c68693 addi a3,a3,1068 # 80002c68 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 3bc68693 addi a3,a3,956 # 80002c30 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 02800793 li a5,40 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 02f8b7b7 lui a5,0x2f8b - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 4c878793 addi a5,a5,1224 # 2f8b4c8 <_start-0x7d074b38> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 80000537 lui a0,0x80000 - 80002acc: 80000593 li a1,-2048 - 80002ad0: 00000697 auipc a3,0x0 - 80002ad4: 53068693 addi a3,a3,1328 # 80003000 - 80002ad8: 00a6b023 sd a0,0(a3) - 80002adc: 60b6b72f amoand.d a4,a1,(a3) - 80002ae0: 80000eb7 lui t4,0x80000 - 80002ae4: 00200193 li gp,2 - 80002ae8: 05d71263 bne a4,t4,80002b2c - -0000000080002aec : - 80002aec: 0006b783 ld a5,0(a3) - 80002af0: 80000eb7 lui t4,0x80000 - 80002af4: 00300193 li gp,3 - 80002af8: 03d79a63 bne a5,t4,80002b2c - -0000000080002afc : - 80002afc: 0010059b addiw a1,zero,1 - 80002b00: 01f59593 slli a1,a1,0x1f - 80002b04: 60b6b72f amoand.d a4,a1,(a3) - 80002b08: 80000eb7 lui t4,0x80000 - 80002b0c: 00400193 li gp,4 - 80002b10: 01d71e63 bne a4,t4,80002b2c - -0000000080002b14 : - 80002b14: 0006b783 ld a5,0(a3) - 80002b18: 00100e9b addiw t4,zero,1 - 80002b1c: 01fe9e93 slli t4,t4,0x1f - 80002b20: 00500193 li gp,5 - 80002b24: 01d79463 bne a5,t4,80002b2c - 80002b28: 00301a63 bne zero,gp,80002b3c - -0000000080002b2c : - 80002b2c: 00119513 slli a0,gp,0x1 - 80002b30: 00050063 beqz a0,80002b30 - 80002b34: 00156513 ori a0,a0,1 - 80002b38: 00000073 ecall - -0000000080002b3c : - 80002b3c: 00100513 li a0,1 - 80002b40: 00000073 ecall - 80002b44: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amoand_d.elf b/test/riscv/tests/rv64ua-v-amoand_d.elf deleted file mode 100644 index ae0fa7c0..00000000 Binary files a/test/riscv/tests/rv64ua-v-amoand_d.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-v-amoand_w.dump b/test/riscv/tests/rv64ua-v-amoand_w.dump deleted file mode 100644 index 0fdbc133..00000000 --- a/test/riscv/tests/rv64ua-v-amoand_w.dump +++ /dev/null @@ -1,870 +0,0 @@ - -rv64ua-v-amoand_w: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 63c68693 addi a3,a3,1596 # 80002b90 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 65868693 addi a3,a3,1624 # 80002cc8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 42c68693 addi a3,a3,1068 # 80002c68 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 3bc68693 addi a3,a3,956 # 80002c30 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 00900793 li a5,9 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 068a27b7 lui a5,0x68a2 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: d4878793 addi a5,a5,-696 # 68a1d48 <_start-0x7975e2b8> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 80000537 lui a0,0x80000 - 80002acc: 80000593 li a1,-2048 - 80002ad0: 00000697 auipc a3,0x0 - 80002ad4: 53068693 addi a3,a3,1328 # 80003000 - 80002ad8: 00a6a023 sw a0,0(a3) - 80002adc: 60b6a72f amoand.w a4,a1,(a3) - 80002ae0: 80000eb7 lui t4,0x80000 - 80002ae4: 00200193 li gp,2 - 80002ae8: 05d71063 bne a4,t4,80002b28 - -0000000080002aec : - 80002aec: 0006a783 lw a5,0(a3) - 80002af0: 80000eb7 lui t4,0x80000 - 80002af4: 00300193 li gp,3 - 80002af8: 03d79863 bne a5,t4,80002b28 - -0000000080002afc : - 80002afc: 0010059b addiw a1,zero,1 - 80002b00: 01f59593 slli a1,a1,0x1f - 80002b04: 60b6a72f amoand.w a4,a1,(a3) - 80002b08: 80000eb7 lui t4,0x80000 - 80002b0c: 00400193 li gp,4 - 80002b10: 01d71c63 bne a4,t4,80002b28 - -0000000080002b14 : - 80002b14: 0006a783 lw a5,0(a3) - 80002b18: 80000eb7 lui t4,0x80000 - 80002b1c: 00500193 li gp,5 - 80002b20: 01d79463 bne a5,t4,80002b28 - 80002b24: 00301a63 bne zero,gp,80002b38 - -0000000080002b28 : - 80002b28: 00119513 slli a0,gp,0x1 - 80002b2c: 00050063 beqz a0,80002b2c - 80002b30: 00156513 ori a0,a0,1 - 80002b34: 00000073 ecall - -0000000080002b38 : - 80002b38: 00100513 li a0,1 - 80002b3c: 00000073 ecall - 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amoand_w.elf b/test/riscv/tests/rv64ua-v-amoand_w.elf deleted file mode 100644 index 97e45f4f..00000000 Binary files a/test/riscv/tests/rv64ua-v-amoand_w.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-v-amomax_d.dump b/test/riscv/tests/rv64ua-v-amomax_d.dump deleted file mode 100644 index d69d15d2..00000000 --- a/test/riscv/tests/rv64ua-v-amomax_d.dump +++ /dev/null @@ -1,870 +0,0 @@ - -rv64ua-v-amomax_d: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 63c68693 addi a3,a3,1596 # 80002b90 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 65868693 addi a3,a3,1624 # 80002cc8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 42c68693 addi a3,a3,1068 # 80002c68 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 3bc68693 addi a3,a3,956 # 80002c30 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 03c00793 li a5,60 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 09d2d7b7 lui a5,0x9d2d - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 6b578793 addi a5,a5,1717 # 9d2d6b5 <_start-0x762d294b> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 80000537 lui a0,0x80000 - 80002acc: 80000593 li a1,-2048 - 80002ad0: 00000697 auipc a3,0x0 - 80002ad4: 53068693 addi a3,a3,1328 # 80003000 - 80002ad8: 00a6b023 sd a0,0(a3) - 80002adc: a0b6b72f amomax.d a4,a1,(a3) - 80002ae0: 80000eb7 lui t4,0x80000 - 80002ae4: 00200193 li gp,2 - 80002ae8: 05d71063 bne a4,t4,80002b28 - -0000000080002aec : - 80002aec: 0006b783 ld a5,0(a3) - 80002af0: 80000e93 li t4,-2048 - 80002af4: 00300193 li gp,3 - 80002af8: 03d79863 bne a5,t4,80002b28 - -0000000080002afc : - 80002afc: 00100593 li a1,1 - 80002b00: 0006b023 sd zero,0(a3) - 80002b04: a0b6b72f amomax.d a4,a1,(a3) - 80002b08: 00000e93 li t4,0 - 80002b0c: 00400193 li gp,4 - 80002b10: 01d71c63 bne a4,t4,80002b28 - -0000000080002b14 : - 80002b14: 0006b783 ld a5,0(a3) - 80002b18: 00100e93 li t4,1 - 80002b1c: 00500193 li gp,5 - 80002b20: 01d79463 bne a5,t4,80002b28 - 80002b24: 00301a63 bne zero,gp,80002b38 - -0000000080002b28 : - 80002b28: 00119513 slli a0,gp,0x1 - 80002b2c: 00050063 beqz a0,80002b2c - 80002b30: 00156513 ori a0,a0,1 - 80002b34: 00000073 ecall - -0000000080002b38 : - 80002b38: 00100513 li a0,1 - 80002b3c: 00000073 ecall - 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amomax_d.elf b/test/riscv/tests/rv64ua-v-amomax_d.elf deleted file mode 100644 index 04dfdae4..00000000 Binary files a/test/riscv/tests/rv64ua-v-amomax_d.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-v-amomax_w.dump b/test/riscv/tests/rv64ua-v-amomax_w.dump deleted file mode 100644 index eb204ee5..00000000 --- a/test/riscv/tests/rv64ua-v-amomax_w.dump +++ /dev/null @@ -1,870 +0,0 @@ - -rv64ua-v-amomax_w: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 63c68693 addi a3,a3,1596 # 80002b90 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 65868693 addi a3,a3,1624 # 80002cc8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 42c68693 addi a3,a3,1068 # 80002c68 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 3bc68693 addi a3,a3,956 # 80002c30 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 02700793 li a5,39 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 06a237b7 lui a5,0x6a23 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 87378793 addi a5,a5,-1933 # 6a22873 <_start-0x795dd78d> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 80000537 lui a0,0x80000 - 80002acc: 80000593 li a1,-2048 - 80002ad0: 00000697 auipc a3,0x0 - 80002ad4: 53068693 addi a3,a3,1328 # 80003000 - 80002ad8: 00a6a023 sw a0,0(a3) - 80002adc: a0b6a72f amomax.w a4,a1,(a3) - 80002ae0: 80000eb7 lui t4,0x80000 - 80002ae4: 00200193 li gp,2 - 80002ae8: 05d71063 bne a4,t4,80002b28 - -0000000080002aec : - 80002aec: 0006a783 lw a5,0(a3) - 80002af0: 80000e93 li t4,-2048 - 80002af4: 00300193 li gp,3 - 80002af8: 03d79863 bne a5,t4,80002b28 - -0000000080002afc : - 80002afc: 00100593 li a1,1 - 80002b00: 0006a023 sw zero,0(a3) - 80002b04: a0b6a72f amomax.w a4,a1,(a3) - 80002b08: 00000e93 li t4,0 - 80002b0c: 00400193 li gp,4 - 80002b10: 01d71c63 bne a4,t4,80002b28 - -0000000080002b14 : - 80002b14: 0006a783 lw a5,0(a3) - 80002b18: 00100e93 li t4,1 - 80002b1c: 00500193 li gp,5 - 80002b20: 01d79463 bne a5,t4,80002b28 - 80002b24: 00301a63 bne zero,gp,80002b38 - -0000000080002b28 : - 80002b28: 00119513 slli a0,gp,0x1 - 80002b2c: 00050063 beqz a0,80002b2c - 80002b30: 00156513 ori a0,a0,1 - 80002b34: 00000073 ecall - -0000000080002b38 : - 80002b38: 00100513 li a0,1 - 80002b3c: 00000073 ecall - 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amomax_w.elf b/test/riscv/tests/rv64ua-v-amomax_w.elf deleted file mode 100644 index 49521793..00000000 Binary files a/test/riscv/tests/rv64ua-v-amomax_w.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-v-amomaxu_d.dump b/test/riscv/tests/rv64ua-v-amomaxu_d.dump deleted file mode 100644 index 271a03c5..00000000 --- a/test/riscv/tests/rv64ua-v-amomaxu_d.dump +++ /dev/null @@ -1,870 +0,0 @@ - -rv64ua-v-amomaxu_d: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 63c68693 addi a3,a3,1596 # 80002b90 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 65868693 addi a3,a3,1624 # 80002cc8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 42c68693 addi a3,a3,1068 # 80002c68 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 3bc68693 addi a3,a3,956 # 80002c30 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 03700793 li a5,55 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 00b117b7 lui a5,0xb11 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: cc678793 addi a5,a5,-826 # b10cc6 <_start-0x7f4ef33a> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 80000537 lui a0,0x80000 - 80002acc: 80000593 li a1,-2048 - 80002ad0: 00000697 auipc a3,0x0 - 80002ad4: 53068693 addi a3,a3,1328 # 80003000 - 80002ad8: 00a6b023 sd a0,0(a3) - 80002adc: e0b6b72f amomaxu.d a4,a1,(a3) - 80002ae0: 80000eb7 lui t4,0x80000 - 80002ae4: 00200193 li gp,2 - 80002ae8: 05d71063 bne a4,t4,80002b28 - -0000000080002aec : - 80002aec: 0006b783 ld a5,0(a3) - 80002af0: 80000e93 li t4,-2048 - 80002af4: 00300193 li gp,3 - 80002af8: 03d79863 bne a5,t4,80002b28 - -0000000080002afc : - 80002afc: fff00593 li a1,-1 - 80002b00: 0006b023 sd zero,0(a3) - 80002b04: e0b6b72f amomaxu.d a4,a1,(a3) - 80002b08: 00000e93 li t4,0 - 80002b0c: 00400193 li gp,4 - 80002b10: 01d71c63 bne a4,t4,80002b28 - -0000000080002b14 : - 80002b14: 0006b783 ld a5,0(a3) - 80002b18: fff00e93 li t4,-1 - 80002b1c: 00500193 li gp,5 - 80002b20: 01d79463 bne a5,t4,80002b28 - 80002b24: 00301a63 bne zero,gp,80002b38 - -0000000080002b28 : - 80002b28: 00119513 slli a0,gp,0x1 - 80002b2c: 00050063 beqz a0,80002b2c - 80002b30: 00156513 ori a0,a0,1 - 80002b34: 00000073 ecall - -0000000080002b38 : - 80002b38: 00100513 li a0,1 - 80002b3c: 00000073 ecall - 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amomaxu_d.elf b/test/riscv/tests/rv64ua-v-amomaxu_d.elf deleted file mode 100644 index 0b9930fe..00000000 Binary files a/test/riscv/tests/rv64ua-v-amomaxu_d.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-v-amomaxu_w.dump b/test/riscv/tests/rv64ua-v-amomaxu_w.dump deleted file mode 100644 index d6f336eb..00000000 --- a/test/riscv/tests/rv64ua-v-amomaxu_w.dump +++ /dev/null @@ -1,870 +0,0 @@ - -rv64ua-v-amomaxu_w: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 63c68693 addi a3,a3,1596 # 80002b90 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 65868693 addi a3,a3,1624 # 80002cc8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 42c68693 addi a3,a3,1068 # 80002c68 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 3bc68693 addi a3,a3,956 # 80002c30 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 00700793 li a5,7 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0d8487b7 lui a5,0xd848 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: c5e78793 addi a5,a5,-930 # d847c5e <_start-0x727b83a2> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 80000537 lui a0,0x80000 - 80002acc: 80000593 li a1,-2048 - 80002ad0: 00000697 auipc a3,0x0 - 80002ad4: 53068693 addi a3,a3,1328 # 80003000 - 80002ad8: 00a6a023 sw a0,0(a3) - 80002adc: e0b6a72f amomaxu.w a4,a1,(a3) - 80002ae0: 80000eb7 lui t4,0x80000 - 80002ae4: 00200193 li gp,2 - 80002ae8: 05d71063 bne a4,t4,80002b28 - -0000000080002aec : - 80002aec: 0006a783 lw a5,0(a3) - 80002af0: 80000e93 li t4,-2048 - 80002af4: 00300193 li gp,3 - 80002af8: 03d79863 bne a5,t4,80002b28 - -0000000080002afc : - 80002afc: fff00593 li a1,-1 - 80002b00: 0006a023 sw zero,0(a3) - 80002b04: e0b6a72f amomaxu.w a4,a1,(a3) - 80002b08: 00000e93 li t4,0 - 80002b0c: 00400193 li gp,4 - 80002b10: 01d71c63 bne a4,t4,80002b28 - -0000000080002b14 : - 80002b14: 0006a783 lw a5,0(a3) - 80002b18: fff00e93 li t4,-1 - 80002b1c: 00500193 li gp,5 - 80002b20: 01d79463 bne a5,t4,80002b28 - 80002b24: 00301a63 bne zero,gp,80002b38 - -0000000080002b28 : - 80002b28: 00119513 slli a0,gp,0x1 - 80002b2c: 00050063 beqz a0,80002b2c - 80002b30: 00156513 ori a0,a0,1 - 80002b34: 00000073 ecall - -0000000080002b38 : - 80002b38: 00100513 li a0,1 - 80002b3c: 00000073 ecall - 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amomaxu_w.elf b/test/riscv/tests/rv64ua-v-amomaxu_w.elf deleted file mode 100644 index 989ad0c5..00000000 Binary files a/test/riscv/tests/rv64ua-v-amomaxu_w.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-v-amomin_d.dump b/test/riscv/tests/rv64ua-v-amomin_d.dump deleted file mode 100644 index a97febdb..00000000 --- a/test/riscv/tests/rv64ua-v-amomin_d.dump +++ /dev/null @@ -1,870 +0,0 @@ - -rv64ua-v-amomin_d: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 63c68693 addi a3,a3,1596 # 80002b90 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 65868693 addi a3,a3,1624 # 80002cc8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 42c68693 addi a3,a3,1068 # 80002c68 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 3bc68693 addi a3,a3,956 # 80002c30 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 00500793 li a5,5 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0353d7b7 lui a5,0x353d - 80002a70: 000805b7 lui a1,0x80 - 80002a74: a0778793 addi a5,a5,-1529 # 353ca07 <_start-0x7cac35f9> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 80000537 lui a0,0x80000 - 80002acc: 80000593 li a1,-2048 - 80002ad0: 00000697 auipc a3,0x0 - 80002ad4: 53068693 addi a3,a3,1328 # 80003000 - 80002ad8: 00a6b023 sd a0,0(a3) - 80002adc: 80b6b72f amomin.d a4,a1,(a3) - 80002ae0: 80000eb7 lui t4,0x80000 - 80002ae4: 00200193 li gp,2 - 80002ae8: 05d71063 bne a4,t4,80002b28 - -0000000080002aec : - 80002aec: 0006b783 ld a5,0(a3) - 80002af0: 80000eb7 lui t4,0x80000 - 80002af4: 00300193 li gp,3 - 80002af8: 03d79863 bne a5,t4,80002b28 - -0000000080002afc : - 80002afc: fff00593 li a1,-1 - 80002b00: 0006b023 sd zero,0(a3) - 80002b04: 80b6b72f amomin.d a4,a1,(a3) - 80002b08: 00000e93 li t4,0 - 80002b0c: 00400193 li gp,4 - 80002b10: 01d71c63 bne a4,t4,80002b28 - -0000000080002b14 : - 80002b14: 0006b783 ld a5,0(a3) - 80002b18: fff00e93 li t4,-1 - 80002b1c: 00500193 li gp,5 - 80002b20: 01d79463 bne a5,t4,80002b28 - 80002b24: 00301a63 bne zero,gp,80002b38 - -0000000080002b28 : - 80002b28: 00119513 slli a0,gp,0x1 - 80002b2c: 00050063 beqz a0,80002b2c - 80002b30: 00156513 ori a0,a0,1 - 80002b34: 00000073 ecall - -0000000080002b38 : - 80002b38: 00100513 li a0,1 - 80002b3c: 00000073 ecall - 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amomin_d.elf b/test/riscv/tests/rv64ua-v-amomin_d.elf deleted file mode 100644 index c1364087..00000000 Binary files a/test/riscv/tests/rv64ua-v-amomin_d.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-v-amomin_w.dump b/test/riscv/tests/rv64ua-v-amomin_w.dump deleted file mode 100644 index a436c950..00000000 --- a/test/riscv/tests/rv64ua-v-amomin_w.dump +++ /dev/null @@ -1,870 +0,0 @@ - -rv64ua-v-amomin_w: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 63c68693 addi a3,a3,1596 # 80002b90 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 65868693 addi a3,a3,1624 # 80002cc8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 42c68693 addi a3,a3,1068 # 80002c68 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 3bc68693 addi a3,a3,956 # 80002c30 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 03800793 li a5,56 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0ccca7b7 lui a5,0xccca - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 0ea78793 addi a5,a5,234 # ccca0ea <_start-0x73335f16> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 80000537 lui a0,0x80000 - 80002acc: 80000593 li a1,-2048 - 80002ad0: 00000697 auipc a3,0x0 - 80002ad4: 53068693 addi a3,a3,1328 # 80003000 - 80002ad8: 00a6a023 sw a0,0(a3) - 80002adc: 80b6a72f amomin.w a4,a1,(a3) - 80002ae0: 80000eb7 lui t4,0x80000 - 80002ae4: 00200193 li gp,2 - 80002ae8: 05d71063 bne a4,t4,80002b28 - -0000000080002aec : - 80002aec: 0006a783 lw a5,0(a3) - 80002af0: 80000eb7 lui t4,0x80000 - 80002af4: 00300193 li gp,3 - 80002af8: 03d79863 bne a5,t4,80002b28 - -0000000080002afc : - 80002afc: fff00593 li a1,-1 - 80002b00: 0006a023 sw zero,0(a3) - 80002b04: 80b6a72f amomin.w a4,a1,(a3) - 80002b08: 00000e93 li t4,0 - 80002b0c: 00400193 li gp,4 - 80002b10: 01d71c63 bne a4,t4,80002b28 - -0000000080002b14 : - 80002b14: 0006a783 lw a5,0(a3) - 80002b18: fff00e93 li t4,-1 - 80002b1c: 00500193 li gp,5 - 80002b20: 01d79463 bne a5,t4,80002b28 - 80002b24: 00301a63 bne zero,gp,80002b38 - -0000000080002b28 : - 80002b28: 00119513 slli a0,gp,0x1 - 80002b2c: 00050063 beqz a0,80002b2c - 80002b30: 00156513 ori a0,a0,1 - 80002b34: 00000073 ecall - -0000000080002b38 : - 80002b38: 00100513 li a0,1 - 80002b3c: 00000073 ecall - 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amomin_w.elf b/test/riscv/tests/rv64ua-v-amomin_w.elf deleted file mode 100644 index 46fa3ac6..00000000 Binary files a/test/riscv/tests/rv64ua-v-amomin_w.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-v-amominu_d.dump b/test/riscv/tests/rv64ua-v-amominu_d.dump deleted file mode 100644 index 693d6a66..00000000 --- a/test/riscv/tests/rv64ua-v-amominu_d.dump +++ /dev/null @@ -1,870 +0,0 @@ - -rv64ua-v-amominu_d: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 63c68693 addi a3,a3,1596 # 80002b90 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 65868693 addi a3,a3,1624 # 80002cc8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 42c68693 addi a3,a3,1068 # 80002c68 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 3bc68693 addi a3,a3,956 # 80002c30 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 02800793 li a5,40 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 08b4f7b7 lui a5,0x8b4f - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 5cb78793 addi a5,a5,1483 # 8b4f5cb <_start-0x774b0a35> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 80000537 lui a0,0x80000 - 80002acc: 80000593 li a1,-2048 - 80002ad0: 00000697 auipc a3,0x0 - 80002ad4: 53068693 addi a3,a3,1328 # 80003000 - 80002ad8: 00a6b023 sd a0,0(a3) - 80002adc: c0b6b72f amominu.d a4,a1,(a3) - 80002ae0: 80000eb7 lui t4,0x80000 - 80002ae4: 00200193 li gp,2 - 80002ae8: 05d71063 bne a4,t4,80002b28 - -0000000080002aec : - 80002aec: 0006b783 ld a5,0(a3) - 80002af0: 80000eb7 lui t4,0x80000 - 80002af4: 00300193 li gp,3 - 80002af8: 03d79863 bne a5,t4,80002b28 - -0000000080002afc : - 80002afc: fff00593 li a1,-1 - 80002b00: 0006b023 sd zero,0(a3) - 80002b04: c0b6b72f amominu.d a4,a1,(a3) - 80002b08: 00000e93 li t4,0 - 80002b0c: 00400193 li gp,4 - 80002b10: 01d71c63 bne a4,t4,80002b28 - -0000000080002b14 : - 80002b14: 0006b783 ld a5,0(a3) - 80002b18: 00000e93 li t4,0 - 80002b1c: 00500193 li gp,5 - 80002b20: 01d79463 bne a5,t4,80002b28 - 80002b24: 00301a63 bne zero,gp,80002b38 - -0000000080002b28 : - 80002b28: 00119513 slli a0,gp,0x1 - 80002b2c: 00050063 beqz a0,80002b2c - 80002b30: 00156513 ori a0,a0,1 - 80002b34: 00000073 ecall - -0000000080002b38 : - 80002b38: 00100513 li a0,1 - 80002b3c: 00000073 ecall - 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amominu_d.elf b/test/riscv/tests/rv64ua-v-amominu_d.elf deleted file mode 100644 index 1c7e7db1..00000000 Binary files a/test/riscv/tests/rv64ua-v-amominu_d.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-v-amominu_w.dump b/test/riscv/tests/rv64ua-v-amominu_w.dump deleted file mode 100644 index ac8240d7..00000000 --- a/test/riscv/tests/rv64ua-v-amominu_w.dump +++ /dev/null @@ -1,870 +0,0 @@ - -rv64ua-v-amominu_w: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 63c68693 addi a3,a3,1596 # 80002b90 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 65868693 addi a3,a3,1624 # 80002cc8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 42c68693 addi a3,a3,1068 # 80002c68 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 3bc68693 addi a3,a3,956 # 80002c30 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 01500793 li a5,21 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 083c07b7 lui a5,0x83c0 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 36f78793 addi a5,a5,879 # 83c036f <_start-0x77c3fc91> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 80000537 lui a0,0x80000 - 80002acc: 80000593 li a1,-2048 - 80002ad0: 00000697 auipc a3,0x0 - 80002ad4: 53068693 addi a3,a3,1328 # 80003000 - 80002ad8: 00a6a023 sw a0,0(a3) - 80002adc: c0b6a72f amominu.w a4,a1,(a3) - 80002ae0: 80000eb7 lui t4,0x80000 - 80002ae4: 00200193 li gp,2 - 80002ae8: 05d71063 bne a4,t4,80002b28 - -0000000080002aec : - 80002aec: 0006a783 lw a5,0(a3) - 80002af0: 80000eb7 lui t4,0x80000 - 80002af4: 00300193 li gp,3 - 80002af8: 03d79863 bne a5,t4,80002b28 - -0000000080002afc : - 80002afc: fff00593 li a1,-1 - 80002b00: 0006a023 sw zero,0(a3) - 80002b04: c0b6a72f amominu.w a4,a1,(a3) - 80002b08: 00000e93 li t4,0 - 80002b0c: 00400193 li gp,4 - 80002b10: 01d71c63 bne a4,t4,80002b28 - -0000000080002b14 : - 80002b14: 0006a783 lw a5,0(a3) - 80002b18: 00000e93 li t4,0 - 80002b1c: 00500193 li gp,5 - 80002b20: 01d79463 bne a5,t4,80002b28 - 80002b24: 00301a63 bne zero,gp,80002b38 - -0000000080002b28 : - 80002b28: 00119513 slli a0,gp,0x1 - 80002b2c: 00050063 beqz a0,80002b2c - 80002b30: 00156513 ori a0,a0,1 - 80002b34: 00000073 ecall - -0000000080002b38 : - 80002b38: 00100513 li a0,1 - 80002b3c: 00000073 ecall - 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amominu_w.elf b/test/riscv/tests/rv64ua-v-amominu_w.elf deleted file mode 100644 index b2556893..00000000 Binary files a/test/riscv/tests/rv64ua-v-amominu_w.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-v-amoor_d.dump b/test/riscv/tests/rv64ua-v-amoor_d.dump deleted file mode 100644 index 6bf5fa12..00000000 --- a/test/riscv/tests/rv64ua-v-amoor_d.dump +++ /dev/null @@ -1,869 +0,0 @@ - -rv64ua-v-amoor_d: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 6e868693 addi a3,a3,1768 # 80002b40 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 71c60613 addi a2,a2,1820 # 80002bd0 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6e460613 addi a2,a2,1764 # 80002be8 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 63468693 addi a3,a3,1588 # 80002b88 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 65068693 addi a3,a3,1616 # 80002cc0 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5d060613 addi a2,a2,1488 # 80002c98 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 50468693 addi a3,a3,1284 # 80002cf0 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 42468693 addi a3,a3,1060 # 80002c60 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 3b468693 addi a3,a3,948 # 80002c28 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 02d00793 li a5,45 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 006937b7 lui a5,0x693 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: b1378793 addi a5,a5,-1261 # 692b13 <_start-0x7f96d4ed> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 80000537 lui a0,0x80000 - 80002acc: 80000593 li a1,-2048 - 80002ad0: 00000697 auipc a3,0x0 - 80002ad4: 53068693 addi a3,a3,1328 # 80003000 - 80002ad8: 00a6b023 sd a0,0(a3) - 80002adc: 40b6b72f amoor.d a4,a1,(a3) - 80002ae0: 80000eb7 lui t4,0x80000 - 80002ae4: 00200193 li gp,2 - 80002ae8: 03d71e63 bne a4,t4,80002b24 - -0000000080002aec : - 80002aec: 0006b783 ld a5,0(a3) - 80002af0: 80000e93 li t4,-2048 - 80002af4: 00300193 li gp,3 - 80002af8: 03d79663 bne a5,t4,80002b24 - -0000000080002afc : - 80002afc: 00100593 li a1,1 - 80002b00: 40b6b72f amoor.d a4,a1,(a3) - 80002b04: 80000e93 li t4,-2048 - 80002b08: 00400193 li gp,4 - 80002b0c: 01d71c63 bne a4,t4,80002b24 - -0000000080002b10 : - 80002b10: 0006b783 ld a5,0(a3) - 80002b14: 80100e93 li t4,-2047 - 80002b18: 00500193 li gp,5 - 80002b1c: 01d79463 bne a5,t4,80002b24 - 80002b20: 00301a63 bne zero,gp,80002b34 - -0000000080002b24 : - 80002b24: 00119513 slli a0,gp,0x1 - 80002b28: 00050063 beqz a0,80002b28 - 80002b2c: 00156513 ori a0,a0,1 - 80002b30: 00000073 ecall - -0000000080002b34 : - 80002b34: 00100513 li a0,1 - 80002b38: 00000073 ecall - 80002b3c: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amoor_d.elf b/test/riscv/tests/rv64ua-v-amoor_d.elf deleted file mode 100644 index ce15b22d..00000000 Binary files a/test/riscv/tests/rv64ua-v-amoor_d.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-v-amoor_w.dump b/test/riscv/tests/rv64ua-v-amoor_w.dump deleted file mode 100644 index 71a4ebee..00000000 --- a/test/riscv/tests/rv64ua-v-amoor_w.dump +++ /dev/null @@ -1,869 +0,0 @@ - -rv64ua-v-amoor_w: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 6e868693 addi a3,a3,1768 # 80002b40 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 71c60613 addi a2,a2,1820 # 80002bd0 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6e460613 addi a2,a2,1764 # 80002be8 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 63468693 addi a3,a3,1588 # 80002b88 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 65068693 addi a3,a3,1616 # 80002cc0 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5d060613 addi a2,a2,1488 # 80002c98 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 50468693 addi a3,a3,1284 # 80002cf0 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 42468693 addi a3,a3,1060 # 80002c60 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 3b468693 addi a3,a3,948 # 80002c28 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 00f00793 li a5,15 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 092c77b7 lui a5,0x92c7 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: f3678793 addi a5,a5,-202 # 92c6f36 <_start-0x76d390ca> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 80000537 lui a0,0x80000 - 80002acc: 80000593 li a1,-2048 - 80002ad0: 00000697 auipc a3,0x0 - 80002ad4: 53068693 addi a3,a3,1328 # 80003000 - 80002ad8: 00a6a023 sw a0,0(a3) - 80002adc: 40b6a72f amoor.w a4,a1,(a3) - 80002ae0: 80000eb7 lui t4,0x80000 - 80002ae4: 00200193 li gp,2 - 80002ae8: 03d71e63 bne a4,t4,80002b24 - -0000000080002aec : - 80002aec: 0006a783 lw a5,0(a3) - 80002af0: 80000e93 li t4,-2048 - 80002af4: 00300193 li gp,3 - 80002af8: 03d79663 bne a5,t4,80002b24 - -0000000080002afc : - 80002afc: 00100593 li a1,1 - 80002b00: 40b6a72f amoor.w a4,a1,(a3) - 80002b04: 80000e93 li t4,-2048 - 80002b08: 00400193 li gp,4 - 80002b0c: 01d71c63 bne a4,t4,80002b24 - -0000000080002b10 : - 80002b10: 0006a783 lw a5,0(a3) - 80002b14: 80100e93 li t4,-2047 - 80002b18: 00500193 li gp,5 - 80002b1c: 01d79463 bne a5,t4,80002b24 - 80002b20: 00301a63 bne zero,gp,80002b34 - -0000000080002b24 : - 80002b24: 00119513 slli a0,gp,0x1 - 80002b28: 00050063 beqz a0,80002b28 - 80002b2c: 00156513 ori a0,a0,1 - 80002b30: 00000073 ecall - -0000000080002b34 : - 80002b34: 00100513 li a0,1 - 80002b38: 00000073 ecall - 80002b3c: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amoor_w.elf b/test/riscv/tests/rv64ua-v-amoor_w.elf deleted file mode 100644 index 44f0a915..00000000 Binary files a/test/riscv/tests/rv64ua-v-amoor_w.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-v-amoswap_d.dump b/test/riscv/tests/rv64ua-v-amoswap_d.dump deleted file mode 100644 index bcb607be..00000000 --- a/test/riscv/tests/rv64ua-v-amoswap_d.dump +++ /dev/null @@ -1,871 +0,0 @@ - -rv64ua-v-amoswap_d: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 63c68693 addi a3,a3,1596 # 80002b90 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 65868693 addi a3,a3,1624 # 80002cc8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 42c68693 addi a3,a3,1068 # 80002c68 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 3bc68693 addi a3,a3,956 # 80002c30 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 03700793 li a5,55 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 039c87b7 lui a5,0x39c8 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: e8a78793 addi a5,a5,-374 # 39c7e8a <_start-0x7c638176> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 80000537 lui a0,0x80000 - 80002acc: 80000593 li a1,-2048 - 80002ad0: 00000697 auipc a3,0x0 - 80002ad4: 53068693 addi a3,a3,1328 # 80003000 - 80002ad8: 00a6b023 sd a0,0(a3) - 80002adc: 08b6b72f amoswap.d a4,a1,(a3) - 80002ae0: 80000eb7 lui t4,0x80000 - 80002ae4: 00200193 li gp,2 - 80002ae8: 05d71263 bne a4,t4,80002b2c - -0000000080002aec : - 80002aec: 0006b783 ld a5,0(a3) - 80002af0: 80000e93 li t4,-2048 - 80002af4: 00300193 li gp,3 - 80002af8: 03d79a63 bne a5,t4,80002b2c - -0000000080002afc : - 80002afc: 0010059b addiw a1,zero,1 - 80002b00: 01f59593 slli a1,a1,0x1f - 80002b04: 08b6b72f amoswap.d a4,a1,(a3) - 80002b08: 80000e93 li t4,-2048 - 80002b0c: 00400193 li gp,4 - 80002b10: 01d71e63 bne a4,t4,80002b2c - -0000000080002b14 : - 80002b14: 0006b783 ld a5,0(a3) - 80002b18: 00100e9b addiw t4,zero,1 - 80002b1c: 01fe9e93 slli t4,t4,0x1f - 80002b20: 00500193 li gp,5 - 80002b24: 01d79463 bne a5,t4,80002b2c - 80002b28: 00301a63 bne zero,gp,80002b3c - -0000000080002b2c : - 80002b2c: 00119513 slli a0,gp,0x1 - 80002b30: 00050063 beqz a0,80002b30 - 80002b34: 00156513 ori a0,a0,1 - 80002b38: 00000073 ecall - -0000000080002b3c : - 80002b3c: 00100513 li a0,1 - 80002b40: 00000073 ecall - 80002b44: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amoswap_d.elf b/test/riscv/tests/rv64ua-v-amoswap_d.elf deleted file mode 100644 index 6f8a8173..00000000 Binary files a/test/riscv/tests/rv64ua-v-amoswap_d.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-v-amoswap_w.dump b/test/riscv/tests/rv64ua-v-amoswap_w.dump deleted file mode 100644 index 2369b0d6..00000000 --- a/test/riscv/tests/rv64ua-v-amoswap_w.dump +++ /dev/null @@ -1,870 +0,0 @@ - -rv64ua-v-amoswap_w: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 63c68693 addi a3,a3,1596 # 80002b90 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 65868693 addi a3,a3,1624 # 80002cc8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 42c68693 addi a3,a3,1068 # 80002c68 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 3bc68693 addi a3,a3,956 # 80002c30 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 00d00793 li a5,13 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0788e7b7 lui a5,0x788e - 80002a70: 000805b7 lui a1,0x80 - 80002a74: c2478793 addi a5,a5,-988 # 788dc24 <_start-0x787723dc> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 80000537 lui a0,0x80000 - 80002acc: 80000593 li a1,-2048 - 80002ad0: 00000697 auipc a3,0x0 - 80002ad4: 53068693 addi a3,a3,1328 # 80003000 - 80002ad8: 00a6a023 sw a0,0(a3) - 80002adc: 08b6a72f amoswap.w a4,a1,(a3) - 80002ae0: 80000eb7 lui t4,0x80000 - 80002ae4: 00200193 li gp,2 - 80002ae8: 05d71063 bne a4,t4,80002b28 - -0000000080002aec : - 80002aec: 0006a783 lw a5,0(a3) - 80002af0: 80000e93 li t4,-2048 - 80002af4: 00300193 li gp,3 - 80002af8: 03d79863 bne a5,t4,80002b28 - -0000000080002afc : - 80002afc: 0010059b addiw a1,zero,1 - 80002b00: 01f59593 slli a1,a1,0x1f - 80002b04: 08b6a72f amoswap.w a4,a1,(a3) - 80002b08: 80000e93 li t4,-2048 - 80002b0c: 00400193 li gp,4 - 80002b10: 01d71c63 bne a4,t4,80002b28 - -0000000080002b14 : - 80002b14: 0006a783 lw a5,0(a3) - 80002b18: 80000eb7 lui t4,0x80000 - 80002b1c: 00500193 li gp,5 - 80002b20: 01d79463 bne a5,t4,80002b28 - 80002b24: 00301a63 bne zero,gp,80002b38 - -0000000080002b28 : - 80002b28: 00119513 slli a0,gp,0x1 - 80002b2c: 00050063 beqz a0,80002b2c - 80002b30: 00156513 ori a0,a0,1 - 80002b34: 00000073 ecall - -0000000080002b38 : - 80002b38: 00100513 li a0,1 - 80002b3c: 00000073 ecall - 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amoswap_w.elf b/test/riscv/tests/rv64ua-v-amoswap_w.elf deleted file mode 100644 index 58a23d37..00000000 Binary files a/test/riscv/tests/rv64ua-v-amoswap_w.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-v-amoxor_d.dump b/test/riscv/tests/rv64ua-v-amoxor_d.dump deleted file mode 100644 index 6fa564d8..00000000 --- a/test/riscv/tests/rv64ua-v-amoxor_d.dump +++ /dev/null @@ -1,872 +0,0 @@ - -rv64ua-v-amoxor_d: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 6f868693 addi a3,a3,1784 # 80002b50 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 72c60613 addi a2,a2,1836 # 80002be0 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6f460613 addi a2,a2,1780 # 80002bf8 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 64468693 addi a3,a3,1604 # 80002b98 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 66068693 addi a3,a3,1632 # 80002cd0 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5e060613 addi a2,a2,1504 # 80002ca8 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 51468693 addi a3,a3,1300 # 80002d00 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 43468693 addi a3,a3,1076 # 80002c70 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 3c468693 addi a3,a3,964 # 80002c38 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 02e00793 li a5,46 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0a9e67b7 lui a5,0xa9e6 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 11178793 addi a5,a5,273 # a9e6111 <_start-0x75619eef> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 80000537 lui a0,0x80000 - 80002acc: 80000593 li a1,-2048 - 80002ad0: 00000697 auipc a3,0x0 - 80002ad4: 53068693 addi a3,a3,1328 # 80003000 - 80002ad8: 00a6b023 sd a0,0(a3) - 80002adc: 20b6b72f amoxor.d a4,a1,(a3) - 80002ae0: 80000eb7 lui t4,0x80000 - 80002ae4: 00200193 li gp,2 - 80002ae8: 05d71463 bne a4,t4,80002b30 - -0000000080002aec : - 80002aec: 0006b783 ld a5,0(a3) - 80002af0: 80000eb7 lui t4,0x80000 - 80002af4: 800e8e9b addiw t4,t4,-2048 - 80002af8: 00300193 li gp,3 - 80002afc: 03d79a63 bne a5,t4,80002b30 - -0000000080002b00 : - 80002b00: 00100593 li a1,1 - 80002b04: 20b6b72f amoxor.d a4,a1,(a3) - 80002b08: 80000eb7 lui t4,0x80000 - 80002b0c: 800e8e9b addiw t4,t4,-2048 - 80002b10: 00400193 li gp,4 - 80002b14: 01d71e63 bne a4,t4,80002b30 - -0000000080002b18 : - 80002b18: 0006b783 ld a5,0(a3) - 80002b1c: 80000eb7 lui t4,0x80000 - 80002b20: 801e8e9b addiw t4,t4,-2047 - 80002b24: 00500193 li gp,5 - 80002b28: 01d79463 bne a5,t4,80002b30 - 80002b2c: 00301a63 bne zero,gp,80002b40 - -0000000080002b30 : - 80002b30: 00119513 slli a0,gp,0x1 - 80002b34: 00050063 beqz a0,80002b34 - 80002b38: 00156513 ori a0,a0,1 - 80002b3c: 00000073 ecall - -0000000080002b40 : - 80002b40: 00100513 li a0,1 - 80002b44: 00000073 ecall - 80002b48: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amoxor_d.elf b/test/riscv/tests/rv64ua-v-amoxor_d.elf deleted file mode 100644 index 963af595..00000000 Binary files a/test/riscv/tests/rv64ua-v-amoxor_d.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-v-amoxor_w.dump b/test/riscv/tests/rv64ua-v-amoxor_w.dump deleted file mode 100644 index 6ced7407..00000000 --- a/test/riscv/tests/rv64ua-v-amoxor_w.dump +++ /dev/null @@ -1,874 +0,0 @@ - -rv64ua-v-amoxor_w: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 70068693 addi a3,a3,1792 # 80002b58 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 73460613 addi a2,a2,1844 # 80002be8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6fc60613 addi a2,a2,1788 # 80002c00 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 64c68693 addi a3,a3,1612 # 80002ba0 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 66868693 addi a3,a3,1640 # 80002cd8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5e860613 addi a2,a2,1512 # 80002cb0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 51c68693 addi a3,a3,1308 # 80002d08 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 43c68693 addi a3,a3,1084 # 80002c78 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 3cc68693 addi a3,a3,972 # 80002c40 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 00600793 li a5,6 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 078757b7 lui a5,0x7875 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 2db78793 addi a5,a5,731 # 78752db <_start-0x7878ad25> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 80000537 lui a0,0x80000 - 80002acc: 80000593 li a1,-2048 - 80002ad0: 00000697 auipc a3,0x0 - 80002ad4: 53068693 addi a3,a3,1328 # 80003000 - 80002ad8: 00a6a023 sw a0,0(a3) - 80002adc: 20b6a72f amoxor.w a4,a1,(a3) - 80002ae0: 80000eb7 lui t4,0x80000 - 80002ae4: 00200193 li gp,2 - 80002ae8: 05d71863 bne a4,t4,80002b38 - -0000000080002aec : - 80002aec: 0006a783 lw a5,0(a3) - 80002af0: 80000eb7 lui t4,0x80000 - 80002af4: 800e8e9b addiw t4,t4,-2048 - 80002af8: 00300193 li gp,3 - 80002afc: 03d79e63 bne a5,t4,80002b38 - -0000000080002b00 : - 80002b00: 0030059b addiw a1,zero,3 - 80002b04: 01e59593 slli a1,a1,0x1e - 80002b08: 00158593 addi a1,a1,1 - 80002b0c: 20b6a72f amoxor.w a4,a1,(a3) - 80002b10: 80000eb7 lui t4,0x80000 - 80002b14: 800e8e9b addiw t4,t4,-2048 - 80002b18: 00400193 li gp,4 - 80002b1c: 01d71e63 bne a4,t4,80002b38 - -0000000080002b20 : - 80002b20: 0006a783 lw a5,0(a3) - 80002b24: c0000eb7 lui t4,0xc0000 - 80002b28: 801e8e9b addiw t4,t4,-2047 - 80002b2c: 00500193 li gp,5 - 80002b30: 01d79463 bne a5,t4,80002b38 - 80002b34: 00301a63 bne zero,gp,80002b48 - -0000000080002b38 : - 80002b38: 00119513 slli a0,gp,0x1 - 80002b3c: 00050063 beqz a0,80002b3c - 80002b40: 00156513 ori a0,a0,1 - 80002b44: 00000073 ecall - -0000000080002b48 : - 80002b48: 00100513 li a0,1 - 80002b4c: 00000073 ecall - 80002b50: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-v-amoxor_w.elf b/test/riscv/tests/rv64ua-v-amoxor_w.elf deleted file mode 100644 index 3b91cc1e..00000000 Binary files a/test/riscv/tests/rv64ua-v-amoxor_w.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ua-v-lrsc.dump b/test/riscv/tests/rv64ua-v-lrsc.dump deleted file mode 100644 index 5678673c..00000000 --- a/test/riscv/tests/rv64ua-v-lrsc.dump +++ /dev/null @@ -1,1426 +0,0 @@ - -rv64ua-v-lrsc: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 75868693 addi a3,a3,1880 # 80002bb0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 78c60613 addi a2,a2,1932 # 80002c40 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 75460613 addi a2,a2,1876 # 80002c58 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 6a468693 addi a3,a3,1700 # 80002bf8 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 6c068693 addi a3,a3,1728 # 80002d30 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 64060613 addi a2,a2,1600 # 80002d08 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 57468693 addi a3,a3,1396 # 80002d60 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 49468693 addi a3,a3,1172 # 80002cd0 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 42468693 addi a3,a3,1060 # 80002c98 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 02c00793 li a5,44 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0b4d77b7 lui a5,0xb4d7 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 59f78793 addi a5,a5,1439 # b4d759f <_start-0x74b28a61> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000517 auipc a0,0x0 - 80002acc: 53850513 addi a0,a0,1336 # 80003000 - 80002ad0: 00100593 li a1,1 - 80002ad4: 00b5262f amoadd.w a2,a1,(a0) - 80002ad8: 00100693 li a3,1 - 80002adc: fed67ee3 bleu a3,a2,80002ad8 - 80002ae0: 00052583 lw a1,0(a0) - 80002ae4: fed5eee3 bltu a1,a3,80002ae0 - -0000000080002ae8 : - 80002ae8: 00000517 auipc a0,0x0 - 80002aec: 52050513 addi a0,a0,1312 # 80003008 - 80002af0: 1805272f sc.w a4,zero,(a0) - 80002af4: 00100e93 li t4,1 - 80002af8: 00200193 li gp,2 - 80002afc: 09d71a63 bne a4,t4,80002b90 - -0000000080002b00 : - 80002b00: 00000517 auipc a0,0x0 - 80002b04: 50850513 addi a0,a0,1288 # 80003008 - 80002b08: 00001597 auipc a1,0x1 - 80002b0c: 90458593 addi a1,a1,-1788 # 8000340c - 80002b10: 1005a5af lr.w a1,(a1) - 80002b14: 18b5272f sc.w a4,a1,(a0) - 80002b18: 00100e93 li t4,1 - 80002b1c: 00300193 li gp,3 - 80002b20: 07d71863 bne a4,t4,80002b90 - 80002b24: 00000517 auipc a0,0x0 - 80002b28: 4e450513 addi a0,a0,1252 # 80003008 - 80002b2c: 40000593 li a1,1024 - 80002b30: 00160613 addi a2,a2,1 - 80002b34: 1005272f lr.w a4,(a0) - 80002b38: 00c70733 add a4,a4,a2 - 80002b3c: 18e5272f sc.w a4,a4,(a0) - 80002b40: fe071ae3 bnez a4,80002b34 - 80002b44: fff58593 addi a1,a1,-1 - 80002b48: fe0596e3 bnez a1,80002b34 - 80002b4c: 00000517 auipc a0,0x0 - 80002b50: 4b850513 addi a0,a0,1208 # 80003004 - 80002b54: 00100593 li a1,1 - 80002b58: 00b5202f amoadd.w zero,a1,(a0) - 80002b5c: 00052583 lw a1,0(a0) - 80002b60: fed5cee3 blt a1,a3,80002b5c - 80002b64: 0ff0000f fence - -0000000080002b68 : - 80002b68: 00000517 auipc a0,0x0 - 80002b6c: 4a052503 lw a0,1184(a0) # 80003008 - 80002b70: 00969593 slli a1,a3,0x9 - 80002b74: 40b50533 sub a0,a0,a1 - 80002b78: fff68693 addi a3,a3,-1 - 80002b7c: fe06dce3 bgez a3,80002b74 - 80002b80: 00000e93 li t4,0 - 80002b84: 00400193 li gp,4 - 80002b88: 01d51463 bne a0,t4,80002b90 - 80002b8c: 00301a63 bne zero,gp,80002ba0 - -0000000080002b90 : - 80002b90: 00119513 slli a0,gp,0x1 - 80002b94: 00050063 beqz a0,80002b94 - 80002b98: 00156513 ori a0,a0,1 - 80002b9c: 00000073 ecall - -0000000080002ba0 : - 80002ba0: 00100513 li a0,1 - 80002ba4: 00000073 ecall - 80002ba8: c0001073 unimp - -Disassembly of section .data: - -0000000080003000 : - 80003000: 0000 unimp - 80003002: 0000 unimp - -0000000080003004 : - 80003004: 0000 unimp - 80003006: 0000 unimp - -0000000080003008 : - 80003008: 0000 unimp - 8000300a: 0000 unimp - 8000300c: 0000 unimp - 8000300e: 0000 unimp - 80003010: 0000 unimp - 80003012: 0000 unimp - 80003014: 0000 unimp - 80003016: 0000 unimp - 80003018: 0000 unimp - 8000301a: 0000 unimp - 8000301c: 0000 unimp - 8000301e: 0000 unimp - 80003020: 0000 unimp - 80003022: 0000 unimp - 80003024: 0000 unimp - 80003026: 0000 unimp - 80003028: 0000 unimp - 8000302a: 0000 unimp - 8000302c: 0000 unimp - 8000302e: 0000 unimp - 80003030: 0000 unimp - 80003032: 0000 unimp - 80003034: 0000 unimp - 80003036: 0000 unimp - 80003038: 0000 unimp - 8000303a: 0000 unimp - 8000303c: 0000 unimp - 8000303e: 0000 unimp - 80003040: 0000 unimp - 80003042: 0000 unimp - 80003044: 0000 unimp - 80003046: 0000 unimp - 80003048: 0000 unimp - 8000304a: 0000 unimp - 8000304c: 0000 unimp - 8000304e: 0000 unimp - 80003050: 0000 unimp - 80003052: 0000 unimp - 80003054: 0000 unimp - 80003056: 0000 unimp - 80003058: 0000 unimp - 8000305a: 0000 unimp - 8000305c: 0000 unimp - 8000305e: 0000 unimp - 80003060: 0000 unimp - 80003062: 0000 unimp - 80003064: 0000 unimp - 80003066: 0000 unimp - 80003068: 0000 unimp - 8000306a: 0000 unimp - 8000306c: 0000 unimp - 8000306e: 0000 unimp - 80003070: 0000 unimp - 80003072: 0000 unimp - 80003074: 0000 unimp - 80003076: 0000 unimp - 80003078: 0000 unimp - 8000307a: 0000 unimp - 8000307c: 0000 unimp - 8000307e: 0000 unimp - 80003080: 0000 unimp - 80003082: 0000 unimp - 80003084: 0000 unimp - 80003086: 0000 unimp - 80003088: 0000 unimp - 8000308a: 0000 unimp - 8000308c: 0000 unimp - 8000308e: 0000 unimp - 80003090: 0000 unimp - 80003092: 0000 unimp - 80003094: 0000 unimp - 80003096: 0000 unimp - 80003098: 0000 unimp - 8000309a: 0000 unimp - 8000309c: 0000 unimp - 8000309e: 0000 unimp - 800030a0: 0000 unimp - 800030a2: 0000 unimp - 800030a4: 0000 unimp - 800030a6: 0000 unimp - 800030a8: 0000 unimp - 800030aa: 0000 unimp - 800030ac: 0000 unimp - 800030ae: 0000 unimp - 800030b0: 0000 unimp - 800030b2: 0000 unimp - 800030b4: 0000 unimp - 800030b6: 0000 unimp - 800030b8: 0000 unimp - 800030ba: 0000 unimp - 800030bc: 0000 unimp - 800030be: 0000 unimp - 800030c0: 0000 unimp - 800030c2: 0000 unimp - 800030c4: 0000 unimp - 800030c6: 0000 unimp - 800030c8: 0000 unimp - 800030ca: 0000 unimp - 800030cc: 0000 unimp - 800030ce: 0000 unimp - 800030d0: 0000 unimp - 800030d2: 0000 unimp - 800030d4: 0000 unimp - 800030d6: 0000 unimp - 800030d8: 0000 unimp - 800030da: 0000 unimp - 800030dc: 0000 unimp - 800030de: 0000 unimp - 800030e0: 0000 unimp - 800030e2: 0000 unimp - 800030e4: 0000 unimp - 800030e6: 0000 unimp - 800030e8: 0000 unimp - 800030ea: 0000 unimp - 800030ec: 0000 unimp - 800030ee: 0000 unimp - 800030f0: 0000 unimp - 800030f2: 0000 unimp - 800030f4: 0000 unimp - 800030f6: 0000 unimp - 800030f8: 0000 unimp - 800030fa: 0000 unimp - 800030fc: 0000 unimp - 800030fe: 0000 unimp - 80003100: 0000 unimp - 80003102: 0000 unimp - 80003104: 0000 unimp - 80003106: 0000 unimp - 80003108: 0000 unimp - 8000310a: 0000 unimp - 8000310c: 0000 unimp - 8000310e: 0000 unimp - 80003110: 0000 unimp - 80003112: 0000 unimp - 80003114: 0000 unimp - 80003116: 0000 unimp - 80003118: 0000 unimp - 8000311a: 0000 unimp - 8000311c: 0000 unimp - 8000311e: 0000 unimp - 80003120: 0000 unimp - 80003122: 0000 unimp - 80003124: 0000 unimp - 80003126: 0000 unimp - 80003128: 0000 unimp - 8000312a: 0000 unimp - 8000312c: 0000 unimp - 8000312e: 0000 unimp - 80003130: 0000 unimp - 80003132: 0000 unimp - 80003134: 0000 unimp - 80003136: 0000 unimp - 80003138: 0000 unimp - 8000313a: 0000 unimp - 8000313c: 0000 unimp - 8000313e: 0000 unimp - 80003140: 0000 unimp - 80003142: 0000 unimp - 80003144: 0000 unimp - 80003146: 0000 unimp - 80003148: 0000 unimp - 8000314a: 0000 unimp - 8000314c: 0000 unimp - 8000314e: 0000 unimp - 80003150: 0000 unimp - 80003152: 0000 unimp - 80003154: 0000 unimp - 80003156: 0000 unimp - 80003158: 0000 unimp - 8000315a: 0000 unimp - 8000315c: 0000 unimp - 8000315e: 0000 unimp - 80003160: 0000 unimp - 80003162: 0000 unimp - 80003164: 0000 unimp - 80003166: 0000 unimp - 80003168: 0000 unimp - 8000316a: 0000 unimp - 8000316c: 0000 unimp - 8000316e: 0000 unimp - 80003170: 0000 unimp - 80003172: 0000 unimp - 80003174: 0000 unimp - 80003176: 0000 unimp - 80003178: 0000 unimp - 8000317a: 0000 unimp - 8000317c: 0000 unimp - 8000317e: 0000 unimp - 80003180: 0000 unimp - 80003182: 0000 unimp - 80003184: 0000 unimp - 80003186: 0000 unimp - 80003188: 0000 unimp - 8000318a: 0000 unimp - 8000318c: 0000 unimp - 8000318e: 0000 unimp - 80003190: 0000 unimp - 80003192: 0000 unimp - 80003194: 0000 unimp - 80003196: 0000 unimp - 80003198: 0000 unimp - 8000319a: 0000 unimp - 8000319c: 0000 unimp - 8000319e: 0000 unimp - 800031a0: 0000 unimp - 800031a2: 0000 unimp - 800031a4: 0000 unimp - 800031a6: 0000 unimp - 800031a8: 0000 unimp - 800031aa: 0000 unimp - 800031ac: 0000 unimp - 800031ae: 0000 unimp - 800031b0: 0000 unimp - 800031b2: 0000 unimp - 800031b4: 0000 unimp - 800031b6: 0000 unimp - 800031b8: 0000 unimp - 800031ba: 0000 unimp - 800031bc: 0000 unimp - 800031be: 0000 unimp - 800031c0: 0000 unimp - 800031c2: 0000 unimp - 800031c4: 0000 unimp - 800031c6: 0000 unimp - 800031c8: 0000 unimp - 800031ca: 0000 unimp - 800031cc: 0000 unimp - 800031ce: 0000 unimp - 800031d0: 0000 unimp - 800031d2: 0000 unimp - 800031d4: 0000 unimp - 800031d6: 0000 unimp - 800031d8: 0000 unimp - 800031da: 0000 unimp - 800031dc: 0000 unimp - 800031de: 0000 unimp - 800031e0: 0000 unimp - 800031e2: 0000 unimp - 800031e4: 0000 unimp - 800031e6: 0000 unimp - 800031e8: 0000 unimp - 800031ea: 0000 unimp - 800031ec: 0000 unimp - 800031ee: 0000 unimp - 800031f0: 0000 unimp - 800031f2: 0000 unimp - 800031f4: 0000 unimp - 800031f6: 0000 unimp - 800031f8: 0000 unimp - 800031fa: 0000 unimp - 800031fc: 0000 unimp - 800031fe: 0000 unimp - 80003200: 0000 unimp - 80003202: 0000 unimp - 80003204: 0000 unimp - 80003206: 0000 unimp - 80003208: 0000 unimp - 8000320a: 0000 unimp - 8000320c: 0000 unimp - 8000320e: 0000 unimp - 80003210: 0000 unimp - 80003212: 0000 unimp - 80003214: 0000 unimp - 80003216: 0000 unimp - 80003218: 0000 unimp - 8000321a: 0000 unimp - 8000321c: 0000 unimp - 8000321e: 0000 unimp - 80003220: 0000 unimp - 80003222: 0000 unimp - 80003224: 0000 unimp - 80003226: 0000 unimp - 80003228: 0000 unimp - 8000322a: 0000 unimp - 8000322c: 0000 unimp - 8000322e: 0000 unimp - 80003230: 0000 unimp - 80003232: 0000 unimp - 80003234: 0000 unimp - 80003236: 0000 unimp - 80003238: 0000 unimp - 8000323a: 0000 unimp - 8000323c: 0000 unimp - 8000323e: 0000 unimp - 80003240: 0000 unimp - 80003242: 0000 unimp - 80003244: 0000 unimp - 80003246: 0000 unimp - 80003248: 0000 unimp - 8000324a: 0000 unimp - 8000324c: 0000 unimp - 8000324e: 0000 unimp - 80003250: 0000 unimp - 80003252: 0000 unimp - 80003254: 0000 unimp - 80003256: 0000 unimp - 80003258: 0000 unimp - 8000325a: 0000 unimp - 8000325c: 0000 unimp - 8000325e: 0000 unimp - 80003260: 0000 unimp - 80003262: 0000 unimp - 80003264: 0000 unimp - 80003266: 0000 unimp - 80003268: 0000 unimp - 8000326a: 0000 unimp - 8000326c: 0000 unimp - 8000326e: 0000 unimp - 80003270: 0000 unimp - 80003272: 0000 unimp - 80003274: 0000 unimp - 80003276: 0000 unimp - 80003278: 0000 unimp - 8000327a: 0000 unimp - 8000327c: 0000 unimp - 8000327e: 0000 unimp - 80003280: 0000 unimp - 80003282: 0000 unimp - 80003284: 0000 unimp - 80003286: 0000 unimp - 80003288: 0000 unimp - 8000328a: 0000 unimp - 8000328c: 0000 unimp - 8000328e: 0000 unimp - 80003290: 0000 unimp - 80003292: 0000 unimp - 80003294: 0000 unimp - 80003296: 0000 unimp - 80003298: 0000 unimp - 8000329a: 0000 unimp - 8000329c: 0000 unimp - 8000329e: 0000 unimp - 800032a0: 0000 unimp - 800032a2: 0000 unimp - 800032a4: 0000 unimp - 800032a6: 0000 unimp - 800032a8: 0000 unimp - 800032aa: 0000 unimp - 800032ac: 0000 unimp - 800032ae: 0000 unimp - 800032b0: 0000 unimp - 800032b2: 0000 unimp - 800032b4: 0000 unimp - 800032b6: 0000 unimp - 800032b8: 0000 unimp - 800032ba: 0000 unimp - 800032bc: 0000 unimp - 800032be: 0000 unimp - 800032c0: 0000 unimp - 800032c2: 0000 unimp - 800032c4: 0000 unimp - 800032c6: 0000 unimp - 800032c8: 0000 unimp - 800032ca: 0000 unimp - 800032cc: 0000 unimp - 800032ce: 0000 unimp - 800032d0: 0000 unimp - 800032d2: 0000 unimp - 800032d4: 0000 unimp - 800032d6: 0000 unimp - 800032d8: 0000 unimp - 800032da: 0000 unimp - 800032dc: 0000 unimp - 800032de: 0000 unimp - 800032e0: 0000 unimp - 800032e2: 0000 unimp - 800032e4: 0000 unimp - 800032e6: 0000 unimp - 800032e8: 0000 unimp - 800032ea: 0000 unimp - 800032ec: 0000 unimp - 800032ee: 0000 unimp - 800032f0: 0000 unimp - 800032f2: 0000 unimp - 800032f4: 0000 unimp - 800032f6: 0000 unimp - 800032f8: 0000 unimp - 800032fa: 0000 unimp - 800032fc: 0000 unimp - 800032fe: 0000 unimp - 80003300: 0000 unimp - 80003302: 0000 unimp - 80003304: 0000 unimp - 80003306: 0000 unimp - 80003308: 0000 unimp - 8000330a: 0000 unimp - 8000330c: 0000 unimp - 8000330e: 0000 unimp - 80003310: 0000 unimp - 80003312: 0000 unimp - 80003314: 0000 unimp - 80003316: 0000 unimp - 80003318: 0000 unimp - 8000331a: 0000 unimp - 8000331c: 0000 unimp - 8000331e: 0000 unimp - 80003320: 0000 unimp - 80003322: 0000 unimp - 80003324: 0000 unimp - 80003326: 0000 unimp - 80003328: 0000 unimp - 8000332a: 0000 unimp - 8000332c: 0000 unimp - 8000332e: 0000 unimp - 80003330: 0000 unimp - 80003332: 0000 unimp - 80003334: 0000 unimp - 80003336: 0000 unimp - 80003338: 0000 unimp - 8000333a: 0000 unimp - 8000333c: 0000 unimp - 8000333e: 0000 unimp - 80003340: 0000 unimp - 80003342: 0000 unimp - 80003344: 0000 unimp - 80003346: 0000 unimp - 80003348: 0000 unimp - 8000334a: 0000 unimp - 8000334c: 0000 unimp - 8000334e: 0000 unimp - 80003350: 0000 unimp - 80003352: 0000 unimp - 80003354: 0000 unimp - 80003356: 0000 unimp - 80003358: 0000 unimp - 8000335a: 0000 unimp - 8000335c: 0000 unimp - 8000335e: 0000 unimp - 80003360: 0000 unimp - 80003362: 0000 unimp - 80003364: 0000 unimp - 80003366: 0000 unimp - 80003368: 0000 unimp - 8000336a: 0000 unimp - 8000336c: 0000 unimp - 8000336e: 0000 unimp - 80003370: 0000 unimp - 80003372: 0000 unimp - 80003374: 0000 unimp - 80003376: 0000 unimp - 80003378: 0000 unimp - 8000337a: 0000 unimp - 8000337c: 0000 unimp - 8000337e: 0000 unimp - 80003380: 0000 unimp - 80003382: 0000 unimp - 80003384: 0000 unimp - 80003386: 0000 unimp - 80003388: 0000 unimp - 8000338a: 0000 unimp - 8000338c: 0000 unimp - 8000338e: 0000 unimp - 80003390: 0000 unimp - 80003392: 0000 unimp - 80003394: 0000 unimp - 80003396: 0000 unimp - 80003398: 0000 unimp - 8000339a: 0000 unimp - 8000339c: 0000 unimp - 8000339e: 0000 unimp - 800033a0: 0000 unimp - 800033a2: 0000 unimp - 800033a4: 0000 unimp - 800033a6: 0000 unimp - 800033a8: 0000 unimp - 800033aa: 0000 unimp - 800033ac: 0000 unimp - 800033ae: 0000 unimp - 800033b0: 0000 unimp - 800033b2: 0000 unimp - 800033b4: 0000 unimp - 800033b6: 0000 unimp - 800033b8: 0000 unimp - 800033ba: 0000 unimp - 800033bc: 0000 unimp - 800033be: 0000 unimp - 800033c0: 0000 unimp - 800033c2: 0000 unimp - 800033c4: 0000 unimp - 800033c6: 0000 unimp - 800033c8: 0000 unimp - 800033ca: 0000 unimp - 800033cc: 0000 unimp - 800033ce: 0000 unimp - 800033d0: 0000 unimp - 800033d2: 0000 unimp - 800033d4: 0000 unimp - 800033d6: 0000 unimp - 800033d8: 0000 unimp - 800033da: 0000 unimp - 800033dc: 0000 unimp - 800033de: 0000 unimp - 800033e0: 0000 unimp - 800033e2: 0000 unimp - 800033e4: 0000 unimp - 800033e6: 0000 unimp - 800033e8: 0000 unimp - 800033ea: 0000 unimp - 800033ec: 0000 unimp - 800033ee: 0000 unimp - 800033f0: 0000 unimp - 800033f2: 0000 unimp - 800033f4: 0000 unimp - 800033f6: 0000 unimp - 800033f8: 0000 unimp - 800033fa: 0000 unimp - 800033fc: 0000 unimp - 800033fe: 0000 unimp - 80003400: 0000 unimp - 80003402: 0000 unimp - 80003404: 0000 unimp - 80003406: 0000 unimp - 80003408: 0000 unimp - 8000340a: 0000 unimp - -000000008000340c : - 8000340c: 0000 unimp - 8000340e: 0000 unimp diff --git a/test/riscv/tests/rv64ua-v-lrsc.elf b/test/riscv/tests/rv64ua-v-lrsc.elf deleted file mode 100755 index 3f49c87c..00000000 Binary files a/test/riscv/tests/rv64ua-v-lrsc.elf and /dev/null differ diff --git a/test/riscv/tests/rv64uc-p-rvc.dump b/test/riscv/tests/rv64uc-p-rvc.dump deleted file mode 100644 index 616e38fe..00000000 --- a/test/riscv/tests/rv64uc-p-rvc.dump +++ /dev/null @@ -1,4878 +0,0 @@ - -rv64uc-p-rvc: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00003f17 auipc t5,0x3 - 80000044: fc3f2023 sw gp,-64(t5) # 80003000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - 800000fc: 00200193 li gp,2 - 80000100: 29a00593 li a1,666 - -0000000080000104 : - 80000104: 6fb0106f j 80001ffe - -0000000080000108 : - 80000108: 3210 fld fa2,32(a2) - 8000010a: 7654 ld a3,168(a2) - 8000010c: ba98 fsd fa4,48(a3) - 8000010e: fedc sd a5,184(a3) - 80000110: 3210 fld fa2,32(a2) - 80000112: 7654 ld a3,168(a2) - 80000114: ba98 fsd fa4,48(a3) - 80000116: fedc sd a5,184(a3) - 80000118: 00000013 nop - 8000011c: 00000013 nop - 80000120: 00000013 nop - 80000124: 00000013 nop - 80000128: 00000013 nop - 8000012c: 00000013 nop - 80000130: 00000013 nop - 80000134: 00000013 nop - 80000138: 00000013 nop - 8000013c: 00000013 nop - 80000140: 00000013 nop - 80000144: 00000013 nop - 80000148: 00000013 nop - 8000014c: 00000013 nop - 80000150: 00000013 nop - 80000154: 00000013 nop - 80000158: 00000013 nop - 8000015c: 00000013 nop - 80000160: 00000013 nop - 80000164: 00000013 nop - 80000168: 00000013 nop - 8000016c: 00000013 nop - 80000170: 00000013 nop - 80000174: 00000013 nop - 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80001042: 0000 unimp - 80001044: 0000 unimp - 80001046: 0000 unimp - 80001048: 0000 unimp - 8000104a: 0000 unimp - 8000104c: 0000 unimp - 8000104e: 0000 unimp - 80001050: 0000 unimp - 80001052: 0000 unimp - 80001054: 0000 unimp - 80001056: 0000 unimp - 80001058: 0000 unimp - 8000105a: 0000 unimp - 8000105c: 0000 unimp - 8000105e: 0000 unimp - 80001060: 0000 unimp - 80001062: 0000 unimp - 80001064: 0000 unimp - 80001066: 0000 unimp - 80001068: 0000 unimp - 8000106a: 0000 unimp - 8000106c: 0000 unimp - 8000106e: 0000 unimp - 80001070: 0000 unimp - 80001072: 0000 unimp - 80001074: 0000 unimp - 80001076: 0000 unimp - 80001078: 0000 unimp - 8000107a: 0000 unimp - 8000107c: 0000 unimp - 8000107e: 0000 unimp - 80001080: 0000 unimp - 80001082: 0000 unimp - 80001084: 0000 unimp - 80001086: 0000 unimp - 80001088: 0000 unimp - 8000108a: 0000 unimp - 8000108c: 0000 unimp - 8000108e: 0000 unimp - 80001090: 0000 unimp - 80001092: 0000 unimp - 80001094: 0000 unimp - 80001096: 0000 unimp - 80001098: 0000 unimp - 8000109a: 0000 unimp - 8000109c: 0000 unimp - 8000109e: 0000 unimp - 800010a0: 0000 unimp - 800010a2: 0000 unimp - 800010a4: 0000 unimp - 800010a6: 0000 unimp - 800010a8: 0000 unimp - 800010aa: 0000 unimp - 800010ac: 0000 unimp - 800010ae: 0000 unimp - 800010b0: 0000 unimp - 800010b2: 0000 unimp - 800010b4: 0000 unimp - 800010b6: 0000 unimp - 800010b8: 0000 unimp - 800010ba: 0000 unimp - 800010bc: 0000 unimp - 800010be: 0000 unimp - 800010c0: 0000 unimp - 800010c2: 0000 unimp - 800010c4: 0000 unimp - 800010c6: 0000 unimp - 800010c8: 0000 unimp - 800010ca: 0000 unimp - 800010cc: 0000 unimp - 800010ce: 0000 unimp - 800010d0: 0000 unimp - 800010d2: 0000 unimp - 800010d4: 0000 unimp - 800010d6: 0000 unimp - 800010d8: 0000 unimp - 800010da: 0000 unimp - 800010dc: 0000 unimp - 800010de: 0000 unimp - 800010e0: 0000 unimp - 800010e2: 0000 unimp - 800010e4: 0000 unimp - 800010e6: 0000 unimp - 800010e8: 0000 unimp - 800010ea: 0000 unimp - 800010ec: 0000 unimp - 800010ee: 0000 unimp - 800010f0: 0000 unimp - 800010f2: 0000 unimp - 800010f4: 0000 unimp - 800010f6: 0000 unimp - 800010f8: 0000 unimp - 800010fa: 0000 unimp - 800010fc: 0000 unimp - 800010fe: 0000 unimp - 80001100: 0000 unimp - 80001102: 0000 unimp - 80001104: 0000 unimp - 80001106: 0000 unimp - 80001108: 0000 unimp - 8000110a: 0000 unimp - 8000110c: 0000 unimp - 8000110e: 0000 unimp - 80001110: 0000 unimp - 80001112: 0000 unimp - 80001114: 0000 unimp - 80001116: 0000 unimp - 80001118: 0000 unimp - 8000111a: 0000 unimp - 8000111c: 0000 unimp - 8000111e: 0000 unimp - 80001120: 0000 unimp - 80001122: 0000 unimp - 80001124: 0000 unimp - 80001126: 0000 unimp - 80001128: 0000 unimp - 8000112a: 0000 unimp - 8000112c: 0000 unimp - 8000112e: 0000 unimp - 80001130: 0000 unimp - 80001132: 0000 unimp - 80001134: 0000 unimp - 80001136: 0000 unimp - 80001138: 0000 unimp - 8000113a: 0000 unimp - 8000113c: 0000 unimp - 8000113e: 0000 unimp - 80001140: 0000 unimp - 80001142: 0000 unimp - 80001144: 0000 unimp - 80001146: 0000 unimp - 80001148: 0000 unimp - 8000114a: 0000 unimp - 8000114c: 0000 unimp - 8000114e: 0000 unimp - 80001150: 0000 unimp - 80001152: 0000 unimp - 80001154: 0000 unimp - 80001156: 0000 unimp - 80001158: 0000 unimp - 8000115a: 0000 unimp - 8000115c: 0000 unimp - 8000115e: 0000 unimp - 80001160: 0000 unimp - 80001162: 0000 unimp - 80001164: 0000 unimp - 80001166: 0000 unimp - 80001168: 0000 unimp - 8000116a: 0000 unimp - 8000116c: 0000 unimp - 8000116e: 0000 unimp - 80001170: 0000 unimp - 80001172: 0000 unimp - 80001174: 0000 unimp - 80001176: 0000 unimp - 80001178: 0000 unimp - 8000117a: 0000 unimp - 8000117c: 0000 unimp - 8000117e: 0000 unimp - 80001180: 0000 unimp - 80001182: 0000 unimp - 80001184: 0000 unimp - 80001186: 0000 unimp - 80001188: 0000 unimp - 8000118a: 0000 unimp - 8000118c: 0000 unimp - 8000118e: 0000 unimp - 80001190: 0000 unimp - 80001192: 0000 unimp - 80001194: 0000 unimp - 80001196: 0000 unimp - 80001198: 0000 unimp - 8000119a: 0000 unimp - 8000119c: 0000 unimp - 8000119e: 0000 unimp - 800011a0: 0000 unimp - 800011a2: 0000 unimp - 800011a4: 0000 unimp - 800011a6: 0000 unimp - 800011a8: 0000 unimp - 800011aa: 0000 unimp - 800011ac: 0000 unimp - 800011ae: 0000 unimp - 800011b0: 0000 unimp - 800011b2: 0000 unimp - 800011b4: 0000 unimp - 800011b6: 0000 unimp - 800011b8: 0000 unimp - 800011ba: 0000 unimp - 800011bc: 0000 unimp - 800011be: 0000 unimp - 800011c0: 0000 unimp - 800011c2: 0000 unimp - 800011c4: 0000 unimp - 800011c6: 0000 unimp - 800011c8: 0000 unimp - 800011ca: 0000 unimp - 800011cc: 0000 unimp - 800011ce: 0000 unimp - 800011d0: 0000 unimp - 800011d2: 0000 unimp - 800011d4: 0000 unimp - 800011d6: 0000 unimp - 800011d8: 0000 unimp - 800011da: 0000 unimp - 800011dc: 0000 unimp - 800011de: 0000 unimp - 800011e0: 0000 unimp - 800011e2: 0000 unimp - 800011e4: 0000 unimp - 800011e6: 0000 unimp - 800011e8: 0000 unimp - 800011ea: 0000 unimp - 800011ec: 0000 unimp - 800011ee: 0000 unimp - 800011f0: 0000 unimp - 800011f2: 0000 unimp - 800011f4: 0000 unimp - 800011f6: 0000 unimp - 800011f8: 0000 unimp - 800011fa: 0000 unimp - 800011fc: 0000 unimp - 800011fe: 0000 unimp - 80001200: 0000 unimp - 80001202: 0000 unimp - 80001204: 0000 unimp - 80001206: 0000 unimp - 80001208: 0000 unimp - 8000120a: 0000 unimp - 8000120c: 0000 unimp - 8000120e: 0000 unimp - 80001210: 0000 unimp - 80001212: 0000 unimp - 80001214: 0000 unimp - 80001216: 0000 unimp - 80001218: 0000 unimp - 8000121a: 0000 unimp - 8000121c: 0000 unimp - 8000121e: 0000 unimp - 80001220: 0000 unimp - 80001222: 0000 unimp - 80001224: 0000 unimp - 80001226: 0000 unimp - 80001228: 0000 unimp - 8000122a: 0000 unimp - 8000122c: 0000 unimp - 8000122e: 0000 unimp - 80001230: 0000 unimp - 80001232: 0000 unimp - 80001234: 0000 unimp - 80001236: 0000 unimp - 80001238: 0000 unimp - 8000123a: 0000 unimp - 8000123c: 0000 unimp - 8000123e: 0000 unimp - 80001240: 0000 unimp - 80001242: 0000 unimp - 80001244: 0000 unimp - 80001246: 0000 unimp - 80001248: 0000 unimp - 8000124a: 0000 unimp - 8000124c: 0000 unimp - 8000124e: 0000 unimp - 80001250: 0000 unimp - 80001252: 0000 unimp - 80001254: 0000 unimp - 80001256: 0000 unimp - 80001258: 0000 unimp - 8000125a: 0000 unimp - 8000125c: 0000 unimp - 8000125e: 0000 unimp - 80001260: 0000 unimp - 80001262: 0000 unimp - 80001264: 0000 unimp - 80001266: 0000 unimp - 80001268: 0000 unimp - 8000126a: 0000 unimp - 8000126c: 0000 unimp - 8000126e: 0000 unimp - 80001270: 0000 unimp - 80001272: 0000 unimp - 80001274: 0000 unimp - 80001276: 0000 unimp - 80001278: 0000 unimp - 8000127a: 0000 unimp - 8000127c: 0000 unimp - 8000127e: 0000 unimp - 80001280: 0000 unimp - 80001282: 0000 unimp - 80001284: 0000 unimp - 80001286: 0000 unimp - 80001288: 0000 unimp - 8000128a: 0000 unimp - 8000128c: 0000 unimp - 8000128e: 0000 unimp - 80001290: 0000 unimp - 80001292: 0000 unimp - 80001294: 0000 unimp - 80001296: 0000 unimp - 80001298: 0000 unimp - 8000129a: 0000 unimp - 8000129c: 0000 unimp - 8000129e: 0000 unimp - 800012a0: 0000 unimp - 800012a2: 0000 unimp - 800012a4: 0000 unimp - 800012a6: 0000 unimp - 800012a8: 0000 unimp - 800012aa: 0000 unimp - 800012ac: 0000 unimp - 800012ae: 0000 unimp - 800012b0: 0000 unimp - 800012b2: 0000 unimp - 800012b4: 0000 unimp - 800012b6: 0000 unimp - 800012b8: 0000 unimp - 800012ba: 0000 unimp - 800012bc: 0000 unimp - 800012be: 0000 unimp - 800012c0: 0000 unimp - 800012c2: 0000 unimp - 800012c4: 0000 unimp - 800012c6: 0000 unimp - 800012c8: 0000 unimp - 800012ca: 0000 unimp - 800012cc: 0000 unimp - 800012ce: 0000 unimp - 800012d0: 0000 unimp - 800012d2: 0000 unimp - 800012d4: 0000 unimp - 800012d6: 0000 unimp - 800012d8: 0000 unimp - 800012da: 0000 unimp - 800012dc: 0000 unimp - 800012de: 0000 unimp - 800012e0: 0000 unimp - 800012e2: 0000 unimp - 800012e4: 0000 unimp - 800012e6: 0000 unimp - 800012e8: 0000 unimp - 800012ea: 0000 unimp - 800012ec: 0000 unimp - 800012ee: 0000 unimp - 800012f0: 0000 unimp - 800012f2: 0000 unimp - 800012f4: 0000 unimp - 800012f6: 0000 unimp - 800012f8: 0000 unimp - 800012fa: 0000 unimp - 800012fc: 0000 unimp - 800012fe: 0000 unimp - 80001300: 0000 unimp - 80001302: 0000 unimp - 80001304: 0000 unimp - 80001306: 0000 unimp - 80001308: 0000 unimp - 8000130a: 0000 unimp - 8000130c: 0000 unimp - 8000130e: 0000 unimp - 80001310: 0000 unimp - 80001312: 0000 unimp - 80001314: 0000 unimp - 80001316: 0000 unimp - 80001318: 0000 unimp - 8000131a: 0000 unimp - 8000131c: 0000 unimp - 8000131e: 0000 unimp - 80001320: 0000 unimp - 80001322: 0000 unimp - 80001324: 0000 unimp - 80001326: 0000 unimp - 80001328: 0000 unimp - 8000132a: 0000 unimp - 8000132c: 0000 unimp - 8000132e: 0000 unimp - 80001330: 0000 unimp - 80001332: 0000 unimp - 80001334: 0000 unimp - 80001336: 0000 unimp - 80001338: 0000 unimp - 8000133a: 0000 unimp - 8000133c: 0000 unimp - 8000133e: 0000 unimp - 80001340: 0000 unimp - 80001342: 0000 unimp - 80001344: 0000 unimp - 80001346: 0000 unimp - 80001348: 0000 unimp - 8000134a: 0000 unimp - 8000134c: 0000 unimp - 8000134e: 0000 unimp - 80001350: 0000 unimp - 80001352: 0000 unimp - 80001354: 0000 unimp - 80001356: 0000 unimp - 80001358: 0000 unimp - 8000135a: 0000 unimp - 8000135c: 0000 unimp - 8000135e: 0000 unimp - 80001360: 0000 unimp - 80001362: 0000 unimp - 80001364: 0000 unimp - 80001366: 0000 unimp - 80001368: 0000 unimp - 8000136a: 0000 unimp - 8000136c: 0000 unimp - 8000136e: 0000 unimp - 80001370: 0000 unimp - 80001372: 0000 unimp - 80001374: 0000 unimp - 80001376: 0000 unimp - 80001378: 0000 unimp - 8000137a: 0000 unimp - 8000137c: 0000 unimp - 8000137e: 0000 unimp - 80001380: 0000 unimp - 80001382: 0000 unimp - 80001384: 0000 unimp - 80001386: 0000 unimp - 80001388: 0000 unimp - 8000138a: 0000 unimp - 8000138c: 0000 unimp - 8000138e: 0000 unimp - 80001390: 0000 unimp - 80001392: 0000 unimp - 80001394: 0000 unimp - 80001396: 0000 unimp - 80001398: 0000 unimp - 8000139a: 0000 unimp - 8000139c: 0000 unimp - 8000139e: 0000 unimp - 800013a0: 0000 unimp - 800013a2: 0000 unimp - 800013a4: 0000 unimp - 800013a6: 0000 unimp - 800013a8: 0000 unimp - 800013aa: 0000 unimp - 800013ac: 0000 unimp - 800013ae: 0000 unimp - 800013b0: 0000 unimp - 800013b2: 0000 unimp - 800013b4: 0000 unimp - 800013b6: 0000 unimp - 800013b8: 0000 unimp - 800013ba: 0000 unimp - 800013bc: 0000 unimp - 800013be: 0000 unimp - 800013c0: 0000 unimp - 800013c2: 0000 unimp - 800013c4: 0000 unimp - 800013c6: 0000 unimp - 800013c8: 0000 unimp - 800013ca: 0000 unimp - 800013cc: 0000 unimp - 800013ce: 0000 unimp - 800013d0: 0000 unimp - 800013d2: 0000 unimp - 800013d4: 0000 unimp - 800013d6: 0000 unimp - 800013d8: 0000 unimp - 800013da: 0000 unimp - 800013dc: 0000 unimp - 800013de: 0000 unimp - 800013e0: 0000 unimp - 800013e2: 0000 unimp - 800013e4: 0000 unimp - 800013e6: 0000 unimp - 800013e8: 0000 unimp - 800013ea: 0000 unimp - 800013ec: 0000 unimp - 800013ee: 0000 unimp - 800013f0: 0000 unimp - 800013f2: 0000 unimp - 800013f4: 0000 unimp - 800013f6: 0000 unimp - 800013f8: 0000 unimp - 800013fa: 0000 unimp - 800013fc: 0000 unimp - 800013fe: 0000 unimp - 80001400: 0000 unimp - 80001402: 0000 unimp - 80001404: 0000 unimp - 80001406: 0000 unimp - 80001408: 0000 unimp - 8000140a: 0000 unimp - 8000140c: 0000 unimp - 8000140e: 0000 unimp - 80001410: 0000 unimp - 80001412: 0000 unimp - 80001414: 0000 unimp - 80001416: 0000 unimp - 80001418: 0000 unimp - 8000141a: 0000 unimp - 8000141c: 0000 unimp - 8000141e: 0000 unimp - 80001420: 0000 unimp - 80001422: 0000 unimp - 80001424: 0000 unimp - 80001426: 0000 unimp - 80001428: 0000 unimp - 8000142a: 0000 unimp - 8000142c: 0000 unimp - 8000142e: 0000 unimp - 80001430: 0000 unimp - 80001432: 0000 unimp - 80001434: 0000 unimp - 80001436: 0000 unimp - 80001438: 0000 unimp - 8000143a: 0000 unimp - 8000143c: 0000 unimp - 8000143e: 0000 unimp - 80001440: 0000 unimp - 80001442: 0000 unimp - 80001444: 0000 unimp - 80001446: 0000 unimp - 80001448: 0000 unimp - 8000144a: 0000 unimp - 8000144c: 0000 unimp - 8000144e: 0000 unimp - 80001450: 0000 unimp - 80001452: 0000 unimp - 80001454: 0000 unimp - 80001456: 0000 unimp - 80001458: 0000 unimp - 8000145a: 0000 unimp - 8000145c: 0000 unimp - 8000145e: 0000 unimp - 80001460: 0000 unimp - 80001462: 0000 unimp - 80001464: 0000 unimp - 80001466: 0000 unimp - 80001468: 0000 unimp - 8000146a: 0000 unimp - 8000146c: 0000 unimp - 8000146e: 0000 unimp - 80001470: 0000 unimp - 80001472: 0000 unimp - 80001474: 0000 unimp - 80001476: 0000 unimp - 80001478: 0000 unimp - 8000147a: 0000 unimp - 8000147c: 0000 unimp - 8000147e: 0000 unimp - 80001480: 0000 unimp - 80001482: 0000 unimp - 80001484: 0000 unimp - 80001486: 0000 unimp - 80001488: 0000 unimp - 8000148a: 0000 unimp - 8000148c: 0000 unimp - 8000148e: 0000 unimp - 80001490: 0000 unimp - 80001492: 0000 unimp - 80001494: 0000 unimp - 80001496: 0000 unimp - 80001498: 0000 unimp - 8000149a: 0000 unimp - 8000149c: 0000 unimp - 8000149e: 0000 unimp - 800014a0: 0000 unimp - 800014a2: 0000 unimp - 800014a4: 0000 unimp - 800014a6: 0000 unimp - 800014a8: 0000 unimp - 800014aa: 0000 unimp - 800014ac: 0000 unimp - 800014ae: 0000 unimp - 800014b0: 0000 unimp - 800014b2: 0000 unimp - 800014b4: 0000 unimp - 800014b6: 0000 unimp - 800014b8: 0000 unimp - 800014ba: 0000 unimp - 800014bc: 0000 unimp - 800014be: 0000 unimp - 800014c0: 0000 unimp - 800014c2: 0000 unimp - 800014c4: 0000 unimp - 800014c6: 0000 unimp - 800014c8: 0000 unimp - 800014ca: 0000 unimp - 800014cc: 0000 unimp - 800014ce: 0000 unimp - 800014d0: 0000 unimp - 800014d2: 0000 unimp - 800014d4: 0000 unimp - 800014d6: 0000 unimp - 800014d8: 0000 unimp - 800014da: 0000 unimp - 800014dc: 0000 unimp - 800014de: 0000 unimp - 800014e0: 0000 unimp - 800014e2: 0000 unimp - 800014e4: 0000 unimp - 800014e6: 0000 unimp - 800014e8: 0000 unimp - 800014ea: 0000 unimp - 800014ec: 0000 unimp - 800014ee: 0000 unimp - 800014f0: 0000 unimp - 800014f2: 0000 unimp - 800014f4: 0000 unimp - 800014f6: 0000 unimp - 800014f8: 0000 unimp - 800014fa: 0000 unimp - 800014fc: 0000 unimp - 800014fe: 0000 unimp - 80001500: 0000 unimp - 80001502: 0000 unimp - 80001504: 0000 unimp - 80001506: 0000 unimp - 80001508: 0000 unimp - 8000150a: 0000 unimp - 8000150c: 0000 unimp - 8000150e: 0000 unimp - 80001510: 0000 unimp - 80001512: 0000 unimp - 80001514: 0000 unimp - 80001516: 0000 unimp - 80001518: 0000 unimp - 8000151a: 0000 unimp - 8000151c: 0000 unimp - 8000151e: 0000 unimp - 80001520: 0000 unimp - 80001522: 0000 unimp - 80001524: 0000 unimp - 80001526: 0000 unimp - 80001528: 0000 unimp - 8000152a: 0000 unimp - 8000152c: 0000 unimp - 8000152e: 0000 unimp - 80001530: 0000 unimp - 80001532: 0000 unimp - 80001534: 0000 unimp - 80001536: 0000 unimp - 80001538: 0000 unimp - 8000153a: 0000 unimp - 8000153c: 0000 unimp - 8000153e: 0000 unimp - 80001540: 0000 unimp - 80001542: 0000 unimp - 80001544: 0000 unimp - 80001546: 0000 unimp - 80001548: 0000 unimp - 8000154a: 0000 unimp - 8000154c: 0000 unimp - 8000154e: 0000 unimp - 80001550: 0000 unimp - 80001552: 0000 unimp - 80001554: 0000 unimp - 80001556: 0000 unimp - 80001558: 0000 unimp - 8000155a: 0000 unimp - 8000155c: 0000 unimp - 8000155e: 0000 unimp - 80001560: 0000 unimp - 80001562: 0000 unimp - 80001564: 0000 unimp - 80001566: 0000 unimp - 80001568: 0000 unimp - 8000156a: 0000 unimp - 8000156c: 0000 unimp - 8000156e: 0000 unimp - 80001570: 0000 unimp - 80001572: 0000 unimp - 80001574: 0000 unimp - 80001576: 0000 unimp - 80001578: 0000 unimp - 8000157a: 0000 unimp - 8000157c: 0000 unimp - 8000157e: 0000 unimp - 80001580: 0000 unimp - 80001582: 0000 unimp - 80001584: 0000 unimp - 80001586: 0000 unimp - 80001588: 0000 unimp - 8000158a: 0000 unimp - 8000158c: 0000 unimp - 8000158e: 0000 unimp - 80001590: 0000 unimp - 80001592: 0000 unimp - 80001594: 0000 unimp - 80001596: 0000 unimp - 80001598: 0000 unimp - 8000159a: 0000 unimp - 8000159c: 0000 unimp - 8000159e: 0000 unimp - 800015a0: 0000 unimp - 800015a2: 0000 unimp - 800015a4: 0000 unimp - 800015a6: 0000 unimp - 800015a8: 0000 unimp - 800015aa: 0000 unimp - 800015ac: 0000 unimp - 800015ae: 0000 unimp - 800015b0: 0000 unimp - 800015b2: 0000 unimp - 800015b4: 0000 unimp - 800015b6: 0000 unimp - 800015b8: 0000 unimp - 800015ba: 0000 unimp - 800015bc: 0000 unimp - 800015be: 0000 unimp - 800015c0: 0000 unimp - 800015c2: 0000 unimp - 800015c4: 0000 unimp - 800015c6: 0000 unimp - 800015c8: 0000 unimp - 800015ca: 0000 unimp - 800015cc: 0000 unimp - 800015ce: 0000 unimp - 800015d0: 0000 unimp - 800015d2: 0000 unimp - 800015d4: 0000 unimp - 800015d6: 0000 unimp - 800015d8: 0000 unimp - 800015da: 0000 unimp - 800015dc: 0000 unimp - 800015de: 0000 unimp - 800015e0: 0000 unimp - 800015e2: 0000 unimp - 800015e4: 0000 unimp - 800015e6: 0000 unimp - 800015e8: 0000 unimp - 800015ea: 0000 unimp - 800015ec: 0000 unimp - 800015ee: 0000 unimp - 800015f0: 0000 unimp - 800015f2: 0000 unimp - 800015f4: 0000 unimp - 800015f6: 0000 unimp - 800015f8: 0000 unimp - 800015fa: 0000 unimp - 800015fc: 0000 unimp - 800015fe: 0000 unimp - 80001600: 0000 unimp - 80001602: 0000 unimp - 80001604: 0000 unimp - 80001606: 0000 unimp - 80001608: 0000 unimp - 8000160a: 0000 unimp - 8000160c: 0000 unimp - 8000160e: 0000 unimp - 80001610: 0000 unimp - 80001612: 0000 unimp - 80001614: 0000 unimp - 80001616: 0000 unimp - 80001618: 0000 unimp - 8000161a: 0000 unimp - 8000161c: 0000 unimp - 8000161e: 0000 unimp - 80001620: 0000 unimp - 80001622: 0000 unimp - 80001624: 0000 unimp - 80001626: 0000 unimp - 80001628: 0000 unimp - 8000162a: 0000 unimp - 8000162c: 0000 unimp - 8000162e: 0000 unimp - 80001630: 0000 unimp - 80001632: 0000 unimp - 80001634: 0000 unimp - 80001636: 0000 unimp - 80001638: 0000 unimp - 8000163a: 0000 unimp - 8000163c: 0000 unimp - 8000163e: 0000 unimp - 80001640: 0000 unimp - 80001642: 0000 unimp - 80001644: 0000 unimp - 80001646: 0000 unimp - 80001648: 0000 unimp - 8000164a: 0000 unimp - 8000164c: 0000 unimp - 8000164e: 0000 unimp - 80001650: 0000 unimp - 80001652: 0000 unimp - 80001654: 0000 unimp - 80001656: 0000 unimp - 80001658: 0000 unimp - 8000165a: 0000 unimp - 8000165c: 0000 unimp - 8000165e: 0000 unimp - 80001660: 0000 unimp - 80001662: 0000 unimp - 80001664: 0000 unimp - 80001666: 0000 unimp - 80001668: 0000 unimp - 8000166a: 0000 unimp - 8000166c: 0000 unimp - 8000166e: 0000 unimp - 80001670: 0000 unimp - 80001672: 0000 unimp - 80001674: 0000 unimp - 80001676: 0000 unimp - 80001678: 0000 unimp - 8000167a: 0000 unimp - 8000167c: 0000 unimp - 8000167e: 0000 unimp - 80001680: 0000 unimp - 80001682: 0000 unimp - 80001684: 0000 unimp - 80001686: 0000 unimp - 80001688: 0000 unimp - 8000168a: 0000 unimp - 8000168c: 0000 unimp - 8000168e: 0000 unimp - 80001690: 0000 unimp - 80001692: 0000 unimp - 80001694: 0000 unimp - 80001696: 0000 unimp - 80001698: 0000 unimp - 8000169a: 0000 unimp - 8000169c: 0000 unimp - 8000169e: 0000 unimp - 800016a0: 0000 unimp - 800016a2: 0000 unimp - 800016a4: 0000 unimp - 800016a6: 0000 unimp - 800016a8: 0000 unimp - 800016aa: 0000 unimp - 800016ac: 0000 unimp - 800016ae: 0000 unimp - 800016b0: 0000 unimp - 800016b2: 0000 unimp - 800016b4: 0000 unimp - 800016b6: 0000 unimp - 800016b8: 0000 unimp - 800016ba: 0000 unimp - 800016bc: 0000 unimp - 800016be: 0000 unimp - 800016c0: 0000 unimp - 800016c2: 0000 unimp - 800016c4: 0000 unimp - 800016c6: 0000 unimp - 800016c8: 0000 unimp - 800016ca: 0000 unimp - 800016cc: 0000 unimp - 800016ce: 0000 unimp - 800016d0: 0000 unimp - 800016d2: 0000 unimp - 800016d4: 0000 unimp - 800016d6: 0000 unimp - 800016d8: 0000 unimp - 800016da: 0000 unimp - 800016dc: 0000 unimp - 800016de: 0000 unimp - 800016e0: 0000 unimp - 800016e2: 0000 unimp - 800016e4: 0000 unimp - 800016e6: 0000 unimp - 800016e8: 0000 unimp - 800016ea: 0000 unimp - 800016ec: 0000 unimp - 800016ee: 0000 unimp - 800016f0: 0000 unimp - 800016f2: 0000 unimp - 800016f4: 0000 unimp - 800016f6: 0000 unimp - 800016f8: 0000 unimp - 800016fa: 0000 unimp - 800016fc: 0000 unimp - 800016fe: 0000 unimp - 80001700: 0000 unimp - 80001702: 0000 unimp - 80001704: 0000 unimp - 80001706: 0000 unimp - 80001708: 0000 unimp - 8000170a: 0000 unimp - 8000170c: 0000 unimp - 8000170e: 0000 unimp - 80001710: 0000 unimp - 80001712: 0000 unimp - 80001714: 0000 unimp - 80001716: 0000 unimp - 80001718: 0000 unimp - 8000171a: 0000 unimp - 8000171c: 0000 unimp - 8000171e: 0000 unimp - 80001720: 0000 unimp - 80001722: 0000 unimp - 80001724: 0000 unimp - 80001726: 0000 unimp - 80001728: 0000 unimp - 8000172a: 0000 unimp - 8000172c: 0000 unimp - 8000172e: 0000 unimp - 80001730: 0000 unimp - 80001732: 0000 unimp - 80001734: 0000 unimp - 80001736: 0000 unimp - 80001738: 0000 unimp - 8000173a: 0000 unimp - 8000173c: 0000 unimp - 8000173e: 0000 unimp - 80001740: 0000 unimp - 80001742: 0000 unimp - 80001744: 0000 unimp - 80001746: 0000 unimp - 80001748: 0000 unimp - 8000174a: 0000 unimp - 8000174c: 0000 unimp - 8000174e: 0000 unimp - 80001750: 0000 unimp - 80001752: 0000 unimp - 80001754: 0000 unimp - 80001756: 0000 unimp - 80001758: 0000 unimp - 8000175a: 0000 unimp - 8000175c: 0000 unimp - 8000175e: 0000 unimp - 80001760: 0000 unimp - 80001762: 0000 unimp - 80001764: 0000 unimp - 80001766: 0000 unimp - 80001768: 0000 unimp - 8000176a: 0000 unimp - 8000176c: 0000 unimp - 8000176e: 0000 unimp - 80001770: 0000 unimp - 80001772: 0000 unimp - 80001774: 0000 unimp - 80001776: 0000 unimp - 80001778: 0000 unimp - 8000177a: 0000 unimp - 8000177c: 0000 unimp - 8000177e: 0000 unimp - 80001780: 0000 unimp - 80001782: 0000 unimp - 80001784: 0000 unimp - 80001786: 0000 unimp - 80001788: 0000 unimp - 8000178a: 0000 unimp - 8000178c: 0000 unimp - 8000178e: 0000 unimp - 80001790: 0000 unimp - 80001792: 0000 unimp - 80001794: 0000 unimp - 80001796: 0000 unimp - 80001798: 0000 unimp - 8000179a: 0000 unimp - 8000179c: 0000 unimp - 8000179e: 0000 unimp - 800017a0: 0000 unimp - 800017a2: 0000 unimp - 800017a4: 0000 unimp - 800017a6: 0000 unimp - 800017a8: 0000 unimp - 800017aa: 0000 unimp - 800017ac: 0000 unimp - 800017ae: 0000 unimp - 800017b0: 0000 unimp - 800017b2: 0000 unimp - 800017b4: 0000 unimp - 800017b6: 0000 unimp - 800017b8: 0000 unimp - 800017ba: 0000 unimp - 800017bc: 0000 unimp - 800017be: 0000 unimp - 800017c0: 0000 unimp - 800017c2: 0000 unimp - 800017c4: 0000 unimp - 800017c6: 0000 unimp - 800017c8: 0000 unimp - 800017ca: 0000 unimp - 800017cc: 0000 unimp - 800017ce: 0000 unimp - 800017d0: 0000 unimp - 800017d2: 0000 unimp - 800017d4: 0000 unimp - 800017d6: 0000 unimp - 800017d8: 0000 unimp - 800017da: 0000 unimp - 800017dc: 0000 unimp - 800017de: 0000 unimp - 800017e0: 0000 unimp - 800017e2: 0000 unimp - 800017e4: 0000 unimp - 800017e6: 0000 unimp - 800017e8: 0000 unimp - 800017ea: 0000 unimp - 800017ec: 0000 unimp - 800017ee: 0000 unimp - 800017f0: 0000 unimp - 800017f2: 0000 unimp - 800017f4: 0000 unimp - 800017f6: 0000 unimp - 800017f8: 0000 unimp - 800017fa: 0000 unimp - 800017fc: 0000 unimp - 800017fe: 0000 unimp - 80001800: 0000 unimp - 80001802: 0000 unimp - 80001804: 0000 unimp - 80001806: 0000 unimp - 80001808: 0000 unimp - 8000180a: 0000 unimp - 8000180c: 0000 unimp - 8000180e: 0000 unimp - 80001810: 0000 unimp - 80001812: 0000 unimp - 80001814: 0000 unimp - 80001816: 0000 unimp - 80001818: 0000 unimp - 8000181a: 0000 unimp - 8000181c: 0000 unimp - 8000181e: 0000 unimp - 80001820: 0000 unimp - 80001822: 0000 unimp - 80001824: 0000 unimp - 80001826: 0000 unimp - 80001828: 0000 unimp - 8000182a: 0000 unimp - 8000182c: 0000 unimp - 8000182e: 0000 unimp - 80001830: 0000 unimp - 80001832: 0000 unimp - 80001834: 0000 unimp - 80001836: 0000 unimp - 80001838: 0000 unimp - 8000183a: 0000 unimp - 8000183c: 0000 unimp - 8000183e: 0000 unimp - 80001840: 0000 unimp - 80001842: 0000 unimp - 80001844: 0000 unimp - 80001846: 0000 unimp - 80001848: 0000 unimp - 8000184a: 0000 unimp - 8000184c: 0000 unimp - 8000184e: 0000 unimp - 80001850: 0000 unimp - 80001852: 0000 unimp - 80001854: 0000 unimp - 80001856: 0000 unimp - 80001858: 0000 unimp - 8000185a: 0000 unimp - 8000185c: 0000 unimp - 8000185e: 0000 unimp - 80001860: 0000 unimp - 80001862: 0000 unimp - 80001864: 0000 unimp - 80001866: 0000 unimp - 80001868: 0000 unimp - 8000186a: 0000 unimp - 8000186c: 0000 unimp - 8000186e: 0000 unimp - 80001870: 0000 unimp - 80001872: 0000 unimp - 80001874: 0000 unimp - 80001876: 0000 unimp - 80001878: 0000 unimp - 8000187a: 0000 unimp - 8000187c: 0000 unimp - 8000187e: 0000 unimp - 80001880: 0000 unimp - 80001882: 0000 unimp - 80001884: 0000 unimp - 80001886: 0000 unimp - 80001888: 0000 unimp - 8000188a: 0000 unimp - 8000188c: 0000 unimp - 8000188e: 0000 unimp - 80001890: 0000 unimp - 80001892: 0000 unimp - 80001894: 0000 unimp - 80001896: 0000 unimp - 80001898: 0000 unimp - 8000189a: 0000 unimp - 8000189c: 0000 unimp - 8000189e: 0000 unimp - 800018a0: 0000 unimp - 800018a2: 0000 unimp - 800018a4: 0000 unimp - 800018a6: 0000 unimp - 800018a8: 0000 unimp - 800018aa: 0000 unimp - 800018ac: 0000 unimp - 800018ae: 0000 unimp - 800018b0: 0000 unimp - 800018b2: 0000 unimp - 800018b4: 0000 unimp - 800018b6: 0000 unimp - 800018b8: 0000 unimp - 800018ba: 0000 unimp - 800018bc: 0000 unimp - 800018be: 0000 unimp - 800018c0: 0000 unimp - 800018c2: 0000 unimp - 800018c4: 0000 unimp - 800018c6: 0000 unimp - 800018c8: 0000 unimp - 800018ca: 0000 unimp - 800018cc: 0000 unimp - 800018ce: 0000 unimp - 800018d0: 0000 unimp - 800018d2: 0000 unimp - 800018d4: 0000 unimp - 800018d6: 0000 unimp - 800018d8: 0000 unimp - 800018da: 0000 unimp - 800018dc: 0000 unimp - 800018de: 0000 unimp - 800018e0: 0000 unimp - 800018e2: 0000 unimp - 800018e4: 0000 unimp - 800018e6: 0000 unimp - 800018e8: 0000 unimp - 800018ea: 0000 unimp - 800018ec: 0000 unimp - 800018ee: 0000 unimp - 800018f0: 0000 unimp - 800018f2: 0000 unimp - 800018f4: 0000 unimp - 800018f6: 0000 unimp - 800018f8: 0000 unimp - 800018fa: 0000 unimp - 800018fc: 0000 unimp - 800018fe: 0000 unimp - 80001900: 0000 unimp - 80001902: 0000 unimp - 80001904: 0000 unimp - 80001906: 0000 unimp - 80001908: 0000 unimp - 8000190a: 0000 unimp - 8000190c: 0000 unimp - 8000190e: 0000 unimp - 80001910: 0000 unimp - 80001912: 0000 unimp - 80001914: 0000 unimp - 80001916: 0000 unimp - 80001918: 0000 unimp - 8000191a: 0000 unimp - 8000191c: 0000 unimp - 8000191e: 0000 unimp - 80001920: 0000 unimp - 80001922: 0000 unimp - 80001924: 0000 unimp - 80001926: 0000 unimp - 80001928: 0000 unimp - 8000192a: 0000 unimp - 8000192c: 0000 unimp - 8000192e: 0000 unimp - 80001930: 0000 unimp - 80001932: 0000 unimp - 80001934: 0000 unimp - 80001936: 0000 unimp - 80001938: 0000 unimp - 8000193a: 0000 unimp - 8000193c: 0000 unimp - 8000193e: 0000 unimp - 80001940: 0000 unimp - 80001942: 0000 unimp - 80001944: 0000 unimp - 80001946: 0000 unimp - 80001948: 0000 unimp - 8000194a: 0000 unimp - 8000194c: 0000 unimp - 8000194e: 0000 unimp - 80001950: 0000 unimp - 80001952: 0000 unimp - 80001954: 0000 unimp - 80001956: 0000 unimp - 80001958: 0000 unimp - 8000195a: 0000 unimp - 8000195c: 0000 unimp - 8000195e: 0000 unimp - 80001960: 0000 unimp - 80001962: 0000 unimp - 80001964: 0000 unimp - 80001966: 0000 unimp - 80001968: 0000 unimp - 8000196a: 0000 unimp - 8000196c: 0000 unimp - 8000196e: 0000 unimp - 80001970: 0000 unimp - 80001972: 0000 unimp - 80001974: 0000 unimp - 80001976: 0000 unimp - 80001978: 0000 unimp - 8000197a: 0000 unimp - 8000197c: 0000 unimp - 8000197e: 0000 unimp - 80001980: 0000 unimp - 80001982: 0000 unimp - 80001984: 0000 unimp - 80001986: 0000 unimp - 80001988: 0000 unimp - 8000198a: 0000 unimp - 8000198c: 0000 unimp - 8000198e: 0000 unimp - 80001990: 0000 unimp - 80001992: 0000 unimp - 80001994: 0000 unimp - 80001996: 0000 unimp - 80001998: 0000 unimp - 8000199a: 0000 unimp - 8000199c: 0000 unimp - 8000199e: 0000 unimp - 800019a0: 0000 unimp - 800019a2: 0000 unimp - 800019a4: 0000 unimp - 800019a6: 0000 unimp - 800019a8: 0000 unimp - 800019aa: 0000 unimp - 800019ac: 0000 unimp - 800019ae: 0000 unimp - 800019b0: 0000 unimp - 800019b2: 0000 unimp - 800019b4: 0000 unimp - 800019b6: 0000 unimp - 800019b8: 0000 unimp - 800019ba: 0000 unimp - 800019bc: 0000 unimp - 800019be: 0000 unimp - 800019c0: 0000 unimp - 800019c2: 0000 unimp - 800019c4: 0000 unimp - 800019c6: 0000 unimp - 800019c8: 0000 unimp - 800019ca: 0000 unimp - 800019cc: 0000 unimp - 800019ce: 0000 unimp - 800019d0: 0000 unimp - 800019d2: 0000 unimp - 800019d4: 0000 unimp - 800019d6: 0000 unimp - 800019d8: 0000 unimp - 800019da: 0000 unimp - 800019dc: 0000 unimp - 800019de: 0000 unimp - 800019e0: 0000 unimp - 800019e2: 0000 unimp - 800019e4: 0000 unimp - 800019e6: 0000 unimp - 800019e8: 0000 unimp - 800019ea: 0000 unimp - 800019ec: 0000 unimp - 800019ee: 0000 unimp - 800019f0: 0000 unimp - 800019f2: 0000 unimp - 800019f4: 0000 unimp - 800019f6: 0000 unimp - 800019f8: 0000 unimp - 800019fa: 0000 unimp - 800019fc: 0000 unimp - 800019fe: 0000 unimp - 80001a00: 0000 unimp - 80001a02: 0000 unimp - 80001a04: 0000 unimp - 80001a06: 0000 unimp - 80001a08: 0000 unimp - 80001a0a: 0000 unimp - 80001a0c: 0000 unimp - 80001a0e: 0000 unimp - 80001a10: 0000 unimp - 80001a12: 0000 unimp - 80001a14: 0000 unimp - 80001a16: 0000 unimp - 80001a18: 0000 unimp - 80001a1a: 0000 unimp - 80001a1c: 0000 unimp - 80001a1e: 0000 unimp - 80001a20: 0000 unimp - 80001a22: 0000 unimp - 80001a24: 0000 unimp - 80001a26: 0000 unimp - 80001a28: 0000 unimp - 80001a2a: 0000 unimp - 80001a2c: 0000 unimp - 80001a2e: 0000 unimp - 80001a30: 0000 unimp - 80001a32: 0000 unimp - 80001a34: 0000 unimp - 80001a36: 0000 unimp - 80001a38: 0000 unimp - 80001a3a: 0000 unimp - 80001a3c: 0000 unimp - 80001a3e: 0000 unimp - 80001a40: 0000 unimp - 80001a42: 0000 unimp - 80001a44: 0000 unimp - 80001a46: 0000 unimp - 80001a48: 0000 unimp - 80001a4a: 0000 unimp - 80001a4c: 0000 unimp - 80001a4e: 0000 unimp - 80001a50: 0000 unimp - 80001a52: 0000 unimp - 80001a54: 0000 unimp - 80001a56: 0000 unimp - 80001a58: 0000 unimp - 80001a5a: 0000 unimp - 80001a5c: 0000 unimp - 80001a5e: 0000 unimp - 80001a60: 0000 unimp - 80001a62: 0000 unimp - 80001a64: 0000 unimp - 80001a66: 0000 unimp - 80001a68: 0000 unimp - 80001a6a: 0000 unimp - 80001a6c: 0000 unimp - 80001a6e: 0000 unimp - 80001a70: 0000 unimp - 80001a72: 0000 unimp - 80001a74: 0000 unimp - 80001a76: 0000 unimp - 80001a78: 0000 unimp - 80001a7a: 0000 unimp - 80001a7c: 0000 unimp - 80001a7e: 0000 unimp - 80001a80: 0000 unimp - 80001a82: 0000 unimp - 80001a84: 0000 unimp - 80001a86: 0000 unimp - 80001a88: 0000 unimp - 80001a8a: 0000 unimp - 80001a8c: 0000 unimp - 80001a8e: 0000 unimp - 80001a90: 0000 unimp - 80001a92: 0000 unimp - 80001a94: 0000 unimp - 80001a96: 0000 unimp - 80001a98: 0000 unimp - 80001a9a: 0000 unimp - 80001a9c: 0000 unimp - 80001a9e: 0000 unimp - 80001aa0: 0000 unimp - 80001aa2: 0000 unimp - 80001aa4: 0000 unimp - 80001aa6: 0000 unimp - 80001aa8: 0000 unimp - 80001aaa: 0000 unimp - 80001aac: 0000 unimp - 80001aae: 0000 unimp - 80001ab0: 0000 unimp - 80001ab2: 0000 unimp - 80001ab4: 0000 unimp - 80001ab6: 0000 unimp - 80001ab8: 0000 unimp - 80001aba: 0000 unimp - 80001abc: 0000 unimp - 80001abe: 0000 unimp - 80001ac0: 0000 unimp - 80001ac2: 0000 unimp - 80001ac4: 0000 unimp - 80001ac6: 0000 unimp - 80001ac8: 0000 unimp - 80001aca: 0000 unimp - 80001acc: 0000 unimp - 80001ace: 0000 unimp - 80001ad0: 0000 unimp - 80001ad2: 0000 unimp - 80001ad4: 0000 unimp - 80001ad6: 0000 unimp - 80001ad8: 0000 unimp - 80001ada: 0000 unimp - 80001adc: 0000 unimp - 80001ade: 0000 unimp - 80001ae0: 0000 unimp - 80001ae2: 0000 unimp - 80001ae4: 0000 unimp - 80001ae6: 0000 unimp - 80001ae8: 0000 unimp - 80001aea: 0000 unimp - 80001aec: 0000 unimp - 80001aee: 0000 unimp - 80001af0: 0000 unimp - 80001af2: 0000 unimp - 80001af4: 0000 unimp - 80001af6: 0000 unimp - 80001af8: 0000 unimp - 80001afa: 0000 unimp - 80001afc: 0000 unimp - 80001afe: 0000 unimp - 80001b00: 0000 unimp - 80001b02: 0000 unimp - 80001b04: 0000 unimp - 80001b06: 0000 unimp - 80001b08: 0000 unimp - 80001b0a: 0000 unimp - 80001b0c: 0000 unimp - 80001b0e: 0000 unimp - 80001b10: 0000 unimp - 80001b12: 0000 unimp - 80001b14: 0000 unimp - 80001b16: 0000 unimp - 80001b18: 0000 unimp - 80001b1a: 0000 unimp - 80001b1c: 0000 unimp - 80001b1e: 0000 unimp - 80001b20: 0000 unimp - 80001b22: 0000 unimp - 80001b24: 0000 unimp - 80001b26: 0000 unimp - 80001b28: 0000 unimp - 80001b2a: 0000 unimp - 80001b2c: 0000 unimp - 80001b2e: 0000 unimp - 80001b30: 0000 unimp - 80001b32: 0000 unimp - 80001b34: 0000 unimp - 80001b36: 0000 unimp - 80001b38: 0000 unimp - 80001b3a: 0000 unimp - 80001b3c: 0000 unimp - 80001b3e: 0000 unimp - 80001b40: 0000 unimp - 80001b42: 0000 unimp - 80001b44: 0000 unimp - 80001b46: 0000 unimp - 80001b48: 0000 unimp - 80001b4a: 0000 unimp - 80001b4c: 0000 unimp - 80001b4e: 0000 unimp - 80001b50: 0000 unimp - 80001b52: 0000 unimp - 80001b54: 0000 unimp - 80001b56: 0000 unimp - 80001b58: 0000 unimp - 80001b5a: 0000 unimp - 80001b5c: 0000 unimp - 80001b5e: 0000 unimp - 80001b60: 0000 unimp - 80001b62: 0000 unimp - 80001b64: 0000 unimp - 80001b66: 0000 unimp - 80001b68: 0000 unimp - 80001b6a: 0000 unimp - 80001b6c: 0000 unimp - 80001b6e: 0000 unimp - 80001b70: 0000 unimp - 80001b72: 0000 unimp - 80001b74: 0000 unimp - 80001b76: 0000 unimp - 80001b78: 0000 unimp - 80001b7a: 0000 unimp - 80001b7c: 0000 unimp - 80001b7e: 0000 unimp - 80001b80: 0000 unimp - 80001b82: 0000 unimp - 80001b84: 0000 unimp - 80001b86: 0000 unimp - 80001b88: 0000 unimp - 80001b8a: 0000 unimp - 80001b8c: 0000 unimp - 80001b8e: 0000 unimp - 80001b90: 0000 unimp - 80001b92: 0000 unimp - 80001b94: 0000 unimp - 80001b96: 0000 unimp - 80001b98: 0000 unimp - 80001b9a: 0000 unimp - 80001b9c: 0000 unimp - 80001b9e: 0000 unimp - 80001ba0: 0000 unimp - 80001ba2: 0000 unimp - 80001ba4: 0000 unimp - 80001ba6: 0000 unimp - 80001ba8: 0000 unimp - 80001baa: 0000 unimp - 80001bac: 0000 unimp - 80001bae: 0000 unimp - 80001bb0: 0000 unimp - 80001bb2: 0000 unimp - 80001bb4: 0000 unimp - 80001bb6: 0000 unimp - 80001bb8: 0000 unimp - 80001bba: 0000 unimp - 80001bbc: 0000 unimp - 80001bbe: 0000 unimp - 80001bc0: 0000 unimp - 80001bc2: 0000 unimp - 80001bc4: 0000 unimp - 80001bc6: 0000 unimp - 80001bc8: 0000 unimp - 80001bca: 0000 unimp - 80001bcc: 0000 unimp - 80001bce: 0000 unimp - 80001bd0: 0000 unimp - 80001bd2: 0000 unimp - 80001bd4: 0000 unimp - 80001bd6: 0000 unimp - 80001bd8: 0000 unimp - 80001bda: 0000 unimp - 80001bdc: 0000 unimp - 80001bde: 0000 unimp - 80001be0: 0000 unimp - 80001be2: 0000 unimp - 80001be4: 0000 unimp - 80001be6: 0000 unimp - 80001be8: 0000 unimp - 80001bea: 0000 unimp - 80001bec: 0000 unimp - 80001bee: 0000 unimp - 80001bf0: 0000 unimp - 80001bf2: 0000 unimp - 80001bf4: 0000 unimp - 80001bf6: 0000 unimp - 80001bf8: 0000 unimp - 80001bfa: 0000 unimp - 80001bfc: 0000 unimp - 80001bfe: 0000 unimp - 80001c00: 0000 unimp - 80001c02: 0000 unimp - 80001c04: 0000 unimp - 80001c06: 0000 unimp - 80001c08: 0000 unimp - 80001c0a: 0000 unimp - 80001c0c: 0000 unimp - 80001c0e: 0000 unimp - 80001c10: 0000 unimp - 80001c12: 0000 unimp - 80001c14: 0000 unimp - 80001c16: 0000 unimp - 80001c18: 0000 unimp - 80001c1a: 0000 unimp - 80001c1c: 0000 unimp - 80001c1e: 0000 unimp - 80001c20: 0000 unimp - 80001c22: 0000 unimp - 80001c24: 0000 unimp - 80001c26: 0000 unimp - 80001c28: 0000 unimp - 80001c2a: 0000 unimp - 80001c2c: 0000 unimp - 80001c2e: 0000 unimp - 80001c30: 0000 unimp - 80001c32: 0000 unimp - 80001c34: 0000 unimp - 80001c36: 0000 unimp - 80001c38: 0000 unimp - 80001c3a: 0000 unimp - 80001c3c: 0000 unimp - 80001c3e: 0000 unimp - 80001c40: 0000 unimp - 80001c42: 0000 unimp - 80001c44: 0000 unimp - 80001c46: 0000 unimp - 80001c48: 0000 unimp - 80001c4a: 0000 unimp - 80001c4c: 0000 unimp - 80001c4e: 0000 unimp - 80001c50: 0000 unimp - 80001c52: 0000 unimp - 80001c54: 0000 unimp - 80001c56: 0000 unimp - 80001c58: 0000 unimp - 80001c5a: 0000 unimp - 80001c5c: 0000 unimp - 80001c5e: 0000 unimp - 80001c60: 0000 unimp - 80001c62: 0000 unimp - 80001c64: 0000 unimp - 80001c66: 0000 unimp - 80001c68: 0000 unimp - 80001c6a: 0000 unimp - 80001c6c: 0000 unimp - 80001c6e: 0000 unimp - 80001c70: 0000 unimp - 80001c72: 0000 unimp - 80001c74: 0000 unimp - 80001c76: 0000 unimp - 80001c78: 0000 unimp - 80001c7a: 0000 unimp - 80001c7c: 0000 unimp - 80001c7e: 0000 unimp - 80001c80: 0000 unimp - 80001c82: 0000 unimp - 80001c84: 0000 unimp - 80001c86: 0000 unimp - 80001c88: 0000 unimp - 80001c8a: 0000 unimp - 80001c8c: 0000 unimp - 80001c8e: 0000 unimp - 80001c90: 0000 unimp - 80001c92: 0000 unimp - 80001c94: 0000 unimp - 80001c96: 0000 unimp - 80001c98: 0000 unimp - 80001c9a: 0000 unimp - 80001c9c: 0000 unimp - 80001c9e: 0000 unimp - 80001ca0: 0000 unimp - 80001ca2: 0000 unimp - 80001ca4: 0000 unimp - 80001ca6: 0000 unimp - 80001ca8: 0000 unimp - 80001caa: 0000 unimp - 80001cac: 0000 unimp - 80001cae: 0000 unimp - 80001cb0: 0000 unimp - 80001cb2: 0000 unimp - 80001cb4: 0000 unimp - 80001cb6: 0000 unimp - 80001cb8: 0000 unimp - 80001cba: 0000 unimp - 80001cbc: 0000 unimp - 80001cbe: 0000 unimp - 80001cc0: 0000 unimp - 80001cc2: 0000 unimp - 80001cc4: 0000 unimp - 80001cc6: 0000 unimp - 80001cc8: 0000 unimp - 80001cca: 0000 unimp - 80001ccc: 0000 unimp - 80001cce: 0000 unimp - 80001cd0: 0000 unimp - 80001cd2: 0000 unimp - 80001cd4: 0000 unimp - 80001cd6: 0000 unimp - 80001cd8: 0000 unimp - 80001cda: 0000 unimp - 80001cdc: 0000 unimp - 80001cde: 0000 unimp - 80001ce0: 0000 unimp - 80001ce2: 0000 unimp - 80001ce4: 0000 unimp - 80001ce6: 0000 unimp - 80001ce8: 0000 unimp - 80001cea: 0000 unimp - 80001cec: 0000 unimp - 80001cee: 0000 unimp - 80001cf0: 0000 unimp - 80001cf2: 0000 unimp - 80001cf4: 0000 unimp - 80001cf6: 0000 unimp - 80001cf8: 0000 unimp - 80001cfa: 0000 unimp - 80001cfc: 0000 unimp - 80001cfe: 0000 unimp - 80001d00: 0000 unimp - 80001d02: 0000 unimp - 80001d04: 0000 unimp - 80001d06: 0000 unimp - 80001d08: 0000 unimp - 80001d0a: 0000 unimp - 80001d0c: 0000 unimp - 80001d0e: 0000 unimp - 80001d10: 0000 unimp - 80001d12: 0000 unimp - 80001d14: 0000 unimp - 80001d16: 0000 unimp - 80001d18: 0000 unimp - 80001d1a: 0000 unimp - 80001d1c: 0000 unimp - 80001d1e: 0000 unimp - 80001d20: 0000 unimp - 80001d22: 0000 unimp - 80001d24: 0000 unimp - 80001d26: 0000 unimp - 80001d28: 0000 unimp - 80001d2a: 0000 unimp - 80001d2c: 0000 unimp - 80001d2e: 0000 unimp - 80001d30: 0000 unimp - 80001d32: 0000 unimp - 80001d34: 0000 unimp - 80001d36: 0000 unimp - 80001d38: 0000 unimp - 80001d3a: 0000 unimp - 80001d3c: 0000 unimp - 80001d3e: 0000 unimp - 80001d40: 0000 unimp - 80001d42: 0000 unimp - 80001d44: 0000 unimp - 80001d46: 0000 unimp - 80001d48: 0000 unimp - 80001d4a: 0000 unimp - 80001d4c: 0000 unimp - 80001d4e: 0000 unimp - 80001d50: 0000 unimp - 80001d52: 0000 unimp - 80001d54: 0000 unimp - 80001d56: 0000 unimp - 80001d58: 0000 unimp - 80001d5a: 0000 unimp - 80001d5c: 0000 unimp - 80001d5e: 0000 unimp - 80001d60: 0000 unimp - 80001d62: 0000 unimp - 80001d64: 0000 unimp - 80001d66: 0000 unimp - 80001d68: 0000 unimp - 80001d6a: 0000 unimp - 80001d6c: 0000 unimp - 80001d6e: 0000 unimp - 80001d70: 0000 unimp - 80001d72: 0000 unimp - 80001d74: 0000 unimp - 80001d76: 0000 unimp - 80001d78: 0000 unimp - 80001d7a: 0000 unimp - 80001d7c: 0000 unimp - 80001d7e: 0000 unimp - 80001d80: 0000 unimp - 80001d82: 0000 unimp - 80001d84: 0000 unimp - 80001d86: 0000 unimp - 80001d88: 0000 unimp - 80001d8a: 0000 unimp - 80001d8c: 0000 unimp - 80001d8e: 0000 unimp - 80001d90: 0000 unimp - 80001d92: 0000 unimp - 80001d94: 0000 unimp - 80001d96: 0000 unimp - 80001d98: 0000 unimp - 80001d9a: 0000 unimp - 80001d9c: 0000 unimp - 80001d9e: 0000 unimp - 80001da0: 0000 unimp - 80001da2: 0000 unimp - 80001da4: 0000 unimp - 80001da6: 0000 unimp - 80001da8: 0000 unimp - 80001daa: 0000 unimp - 80001dac: 0000 unimp - 80001dae: 0000 unimp - 80001db0: 0000 unimp - 80001db2: 0000 unimp - 80001db4: 0000 unimp - 80001db6: 0000 unimp - 80001db8: 0000 unimp - 80001dba: 0000 unimp - 80001dbc: 0000 unimp - 80001dbe: 0000 unimp - 80001dc0: 0000 unimp - 80001dc2: 0000 unimp - 80001dc4: 0000 unimp - 80001dc6: 0000 unimp - 80001dc8: 0000 unimp - 80001dca: 0000 unimp - 80001dcc: 0000 unimp - 80001dce: 0000 unimp - 80001dd0: 0000 unimp - 80001dd2: 0000 unimp - 80001dd4: 0000 unimp - 80001dd6: 0000 unimp - 80001dd8: 0000 unimp - 80001dda: 0000 unimp - 80001ddc: 0000 unimp - 80001dde: 0000 unimp - 80001de0: 0000 unimp - 80001de2: 0000 unimp - 80001de4: 0000 unimp - 80001de6: 0000 unimp - 80001de8: 0000 unimp - 80001dea: 0000 unimp - 80001dec: 0000 unimp - 80001dee: 0000 unimp - 80001df0: 0000 unimp - 80001df2: 0000 unimp - 80001df4: 0000 unimp - 80001df6: 0000 unimp - 80001df8: 0000 unimp - 80001dfa: 0000 unimp - 80001dfc: 0000 unimp - 80001dfe: 0000 unimp - 80001e00: 0000 unimp - 80001e02: 0000 unimp - 80001e04: 0000 unimp - 80001e06: 0000 unimp - 80001e08: 0000 unimp - 80001e0a: 0000 unimp - 80001e0c: 0000 unimp - 80001e0e: 0000 unimp - 80001e10: 0000 unimp - 80001e12: 0000 unimp - 80001e14: 0000 unimp - 80001e16: 0000 unimp - 80001e18: 0000 unimp - 80001e1a: 0000 unimp - 80001e1c: 0000 unimp - 80001e1e: 0000 unimp - 80001e20: 0000 unimp - 80001e22: 0000 unimp - 80001e24: 0000 unimp - 80001e26: 0000 unimp - 80001e28: 0000 unimp - 80001e2a: 0000 unimp - 80001e2c: 0000 unimp - 80001e2e: 0000 unimp - 80001e30: 0000 unimp - 80001e32: 0000 unimp - 80001e34: 0000 unimp - 80001e36: 0000 unimp - 80001e38: 0000 unimp - 80001e3a: 0000 unimp - 80001e3c: 0000 unimp - 80001e3e: 0000 unimp - 80001e40: 0000 unimp - 80001e42: 0000 unimp - 80001e44: 0000 unimp - 80001e46: 0000 unimp - 80001e48: 0000 unimp - 80001e4a: 0000 unimp - 80001e4c: 0000 unimp - 80001e4e: 0000 unimp - 80001e50: 0000 unimp - 80001e52: 0000 unimp - 80001e54: 0000 unimp - 80001e56: 0000 unimp - 80001e58: 0000 unimp - 80001e5a: 0000 unimp - 80001e5c: 0000 unimp - 80001e5e: 0000 unimp - 80001e60: 0000 unimp - 80001e62: 0000 unimp - 80001e64: 0000 unimp - 80001e66: 0000 unimp - 80001e68: 0000 unimp - 80001e6a: 0000 unimp - 80001e6c: 0000 unimp - 80001e6e: 0000 unimp - 80001e70: 0000 unimp - 80001e72: 0000 unimp - 80001e74: 0000 unimp - 80001e76: 0000 unimp - 80001e78: 0000 unimp - 80001e7a: 0000 unimp - 80001e7c: 0000 unimp - 80001e7e: 0000 unimp - 80001e80: 0000 unimp - 80001e82: 0000 unimp - 80001e84: 0000 unimp - 80001e86: 0000 unimp - 80001e88: 0000 unimp - 80001e8a: 0000 unimp - 80001e8c: 0000 unimp - 80001e8e: 0000 unimp - 80001e90: 0000 unimp - 80001e92: 0000 unimp - 80001e94: 0000 unimp - 80001e96: 0000 unimp - 80001e98: 0000 unimp - 80001e9a: 0000 unimp - 80001e9c: 0000 unimp - 80001e9e: 0000 unimp - 80001ea0: 0000 unimp - 80001ea2: 0000 unimp - 80001ea4: 0000 unimp - 80001ea6: 0000 unimp - 80001ea8: 0000 unimp - 80001eaa: 0000 unimp - 80001eac: 0000 unimp - 80001eae: 0000 unimp - 80001eb0: 0000 unimp - 80001eb2: 0000 unimp - 80001eb4: 0000 unimp - 80001eb6: 0000 unimp - 80001eb8: 0000 unimp - 80001eba: 0000 unimp - 80001ebc: 0000 unimp - 80001ebe: 0000 unimp - 80001ec0: 0000 unimp - 80001ec2: 0000 unimp - 80001ec4: 0000 unimp - 80001ec6: 0000 unimp - 80001ec8: 0000 unimp - 80001eca: 0000 unimp - 80001ecc: 0000 unimp - 80001ece: 0000 unimp - 80001ed0: 0000 unimp - 80001ed2: 0000 unimp - 80001ed4: 0000 unimp - 80001ed6: 0000 unimp - 80001ed8: 0000 unimp - 80001eda: 0000 unimp - 80001edc: 0000 unimp - 80001ede: 0000 unimp - 80001ee0: 0000 unimp - 80001ee2: 0000 unimp - 80001ee4: 0000 unimp - 80001ee6: 0000 unimp - 80001ee8: 0000 unimp - 80001eea: 0000 unimp - 80001eec: 0000 unimp - 80001eee: 0000 unimp - 80001ef0: 0000 unimp - 80001ef2: 0000 unimp - 80001ef4: 0000 unimp - 80001ef6: 0000 unimp - 80001ef8: 0000 unimp - 80001efa: 0000 unimp - 80001efc: 0000 unimp - 80001efe: 0000 unimp - 80001f00: 0000 unimp - 80001f02: 0000 unimp - 80001f04: 0000 unimp - 80001f06: 0000 unimp - 80001f08: 0000 unimp - 80001f0a: 0000 unimp - 80001f0c: 0000 unimp - 80001f0e: 0000 unimp - 80001f10: 0000 unimp - 80001f12: 0000 unimp - 80001f14: 0000 unimp - 80001f16: 0000 unimp - 80001f18: 0000 unimp - 80001f1a: 0000 unimp - 80001f1c: 0000 unimp - 80001f1e: 0000 unimp - 80001f20: 0000 unimp - 80001f22: 0000 unimp - 80001f24: 0000 unimp - 80001f26: 0000 unimp - 80001f28: 0000 unimp - 80001f2a: 0000 unimp - 80001f2c: 0000 unimp - 80001f2e: 0000 unimp - 80001f30: 0000 unimp - 80001f32: 0000 unimp - 80001f34: 0000 unimp - 80001f36: 0000 unimp - 80001f38: 0000 unimp - 80001f3a: 0000 unimp - 80001f3c: 0000 unimp - 80001f3e: 0000 unimp - 80001f40: 0000 unimp - 80001f42: 0000 unimp - 80001f44: 0000 unimp - 80001f46: 0000 unimp - 80001f48: 0000 unimp - 80001f4a: 0000 unimp - 80001f4c: 0000 unimp - 80001f4e: 0000 unimp - 80001f50: 0000 unimp - 80001f52: 0000 unimp - 80001f54: 0000 unimp - 80001f56: 0000 unimp - 80001f58: 0000 unimp - 80001f5a: 0000 unimp - 80001f5c: 0000 unimp - 80001f5e: 0000 unimp - 80001f60: 0000 unimp - 80001f62: 0000 unimp - 80001f64: 0000 unimp - 80001f66: 0000 unimp - 80001f68: 0000 unimp - 80001f6a: 0000 unimp - 80001f6c: 0000 unimp - 80001f6e: 0000 unimp - 80001f70: 0000 unimp - 80001f72: 0000 unimp - 80001f74: 0000 unimp - 80001f76: 0000 unimp - 80001f78: 0000 unimp - 80001f7a: 0000 unimp - 80001f7c: 0000 unimp - 80001f7e: 0000 unimp - 80001f80: 0000 unimp - 80001f82: 0000 unimp - 80001f84: 0000 unimp - 80001f86: 0000 unimp - 80001f88: 0000 unimp - 80001f8a: 0000 unimp - 80001f8c: 0000 unimp - 80001f8e: 0000 unimp - 80001f90: 0000 unimp - 80001f92: 0000 unimp - 80001f94: 0000 unimp - 80001f96: 0000 unimp - 80001f98: 0000 unimp - 80001f9a: 0000 unimp - 80001f9c: 0000 unimp - 80001f9e: 0000 unimp - 80001fa0: 0000 unimp - 80001fa2: 0000 unimp - 80001fa4: 0000 unimp - 80001fa6: 0000 unimp - 80001fa8: 0000 unimp - 80001faa: 0000 unimp - 80001fac: 0000 unimp - 80001fae: 0000 unimp - 80001fb0: 0000 unimp - 80001fb2: 0000 unimp - 80001fb4: 0000 unimp - 80001fb6: 0000 unimp - 80001fb8: 0000 unimp - 80001fba: 0000 unimp - 80001fbc: 0000 unimp - 80001fbe: 0000 unimp - 80001fc0: 0000 unimp - 80001fc2: 0000 unimp - 80001fc4: 0000 unimp - 80001fc6: 0000 unimp - 80001fc8: 0000 unimp - 80001fca: 0000 unimp - 80001fcc: 0000 unimp - 80001fce: 0000 unimp - 80001fd0: 0000 unimp - 80001fd2: 0000 unimp - 80001fd4: 0000 unimp - 80001fd6: 0000 unimp - 80001fd8: 0000 unimp - 80001fda: 0000 unimp - 80001fdc: 0000 unimp - 80001fde: 0000 unimp - 80001fe0: 0000 unimp - 80001fe2: 0000 unimp - 80001fe4: 0000 unimp - 80001fe6: 0000 unimp - 80001fe8: 0000 unimp - 80001fea: 0000 unimp - 80001fec: 0000 unimp - 80001fee: 0000 unimp - 80001ff0: 0000 unimp - 80001ff2: 0000 unimp - 80001ff4: 0000 unimp - 80001ff6: 0000 unimp - 80001ff8: 0000 unimp - 80001ffa: 0000 unimp - 80001ffc: 0000 unimp - 80001ffe: 00158593 addi a1,a1,1 - 80002002: 29b00e93 li t4,667 - 80002006: 00200193 li gp,2 - 8000200a: 2dd59163 bne a1,t4,800022cc - 8000200e: 00001137 lui sp,0x1 - 80002012: 2341011b addiw sp,sp,564 - -0000000080002016 : - 80002016: 1fe8 addi a0,sp,1020 - 80002018: 00001eb7 lui t4,0x1 - 8000201c: 630e8e9b addiw t4,t4,1584 - 80002020: 00300193 li gp,3 - 80002024: 2bd51463 bne a0,t4,800022cc - -0000000080002028 : - 80002028: 617d addi sp,sp,496 - 8000202a: 0001 nop - 8000202c: 00001eb7 lui t4,0x1 - 80002030: 424e8e9b addiw t4,t4,1060 - 80002034: 00400193 li gp,4 - 80002038: 29d11a63 bne sp,t4,800022cc - -000000008000203c : - 8000203c: 7101 addi sp,sp,-512 - 8000203e: 0001 nop - 80002040: 00001eb7 lui t4,0x1 - 80002044: 224e8e9b addiw t4,t4,548 - 80002048: 00500193 li gp,5 - 8000204c: 29d11063 bne sp,t4,800022cc - 80002050: ffffe597 auipc a1,0xffffe - 80002054: 0b858593 addi a1,a1,184 # 80000108 - -0000000080002058 : - 80002058: 41c8 lw a0,4(a1) - 8000205a: 0505 addi a0,a0,1 - 8000205c: c1c8 sw a0,4(a1) - 8000205e: 41d0 lw a2,4(a1) - 80002060: fedcceb7 lui t4,0xfedcc - 80002064: a99e8e9b addiw t4,t4,-1383 - 80002068: 00600193 li gp,6 - 8000206c: 27d61063 bne a2,t4,800022cc - -0000000080002070 : - 80002070: 6188 ld a0,0(a1) - 80002072: 0505 addi a0,a0,1 - 80002074: e188 sd a0,0(a1) - 80002076: 6190 ld a2,0(a1) - 80002078: fff6eeb7 lui t4,0xfff6e - 8000207c: 5d5e8e9b addiw t4,t4,1493 - 80002080: 00ce9e93 slli t4,t4,0xc - 80002084: cbbe8e93 addi t4,t4,-837 # fffffffffff6dcbb <_end+0xffffffff7ff69cbb> - 80002088: 00de9e93 slli t4,t4,0xd - 8000208c: 543e8e93 addi t4,t4,1347 - 80002090: 00ce9e93 slli t4,t4,0xc - 80002094: 211e8e93 addi t4,t4,529 - 80002098: 00700193 li gp,7 - 8000209c: 23d61863 bne a2,t4,800022cc - -00000000800020a0 : - 800020a0: 00106513 ori a0,zero,1 - 800020a4: 1541 addi a0,a0,-16 - 800020a6: 0001 nop - 800020a8: ff100e93 li t4,-15 - 800020ac: 00800193 li gp,8 - 800020b0: 21d51e63 bne a0,t4,800022cc - -00000000800020b4 : - 800020b4: 00106793 ori a5,zero,1 - 800020b8: 57c1 li a5,-16 - 800020ba: 0001 nop - 800020bc: ff000e93 li t4,-16 - 800020c0: 00900193 li gp,9 - 800020c4: 21d79463 bne a5,t4,800022cc - -00000000800020c8 : - 800020c8: 6188 ld a0,0(a1) - 800020ca: 357d addiw a0,a0,-1 - 800020cc: 76543eb7 lui t4,0x76543 - 800020d0: 210e8e9b addiw t4,t4,528 - 800020d4: 00a00193 li gp,10 - 800020d8: 1fd51a63 bne a0,t4,800022cc - -00000000800020dc : - 800020dc: 7405 lui s0,0xfffe1 - 800020de: 8431 srai s0,s0,0xc - 800020e0: fe100e93 li t4,-31 - 800020e4: 00b00193 li gp,11 - 800020e8: 1fd41263 bne s0,t4,800022cc - -00000000800020ec : - 800020ec: 7405 lui s0,0xfffe1 - 800020ee: 8031 srli s0,s0,0xc - 800020f0: 00100e9b addiw t4,zero,1 - 800020f4: 034e9e93 slli t4,t4,0x34 - 800020f8: fe1e8e93 addi t4,t4,-31 # 76542fe1 <_start-0x9abd01f> - 800020fc: 00c00193 li gp,12 - 80002100: 1dd41663 bne s0,t4,800022cc - -0000000080002104 : - 80002104: 5479 li s0,-2 - 80002106: 983d andi s0,s0,-17 - 80002108: fee00e93 li t4,-18 - 8000210c: 00e00193 li gp,14 - 80002110: 1bd41e63 bne s0,t4,800022cc - -0000000080002114 : - 80002114: 44d1 li s1,20 - 80002116: 4519 li a0,6 - 80002118: 8c89 sub s1,s1,a0 - 8000211a: 0001 nop - 8000211c: 00e00e93 li t4,14 - 80002120: 00f00193 li gp,15 - 80002124: 1bd49463 bne s1,t4,800022cc - -0000000080002128 : - 80002128: 44d1 li s1,20 - 8000212a: 4519 li a0,6 - 8000212c: 8ca9 xor s1,s1,a0 - 8000212e: 0001 nop - 80002130: 01200e93 li t4,18 - 80002134: 01000193 li gp,16 - 80002138: 19d49a63 bne s1,t4,800022cc - -000000008000213c : - 8000213c: 44d1 li s1,20 - 8000213e: 4519 li a0,6 - 80002140: 8cc9 or s1,s1,a0 - 80002142: 0001 nop - 80002144: 01600e93 li t4,22 - 80002148: 01100193 li gp,17 - 8000214c: 19d49063 bne s1,t4,800022cc - -0000000080002150 : - 80002150: 44d1 li s1,20 - 80002152: 4519 li a0,6 - 80002154: 8ce9 and s1,s1,a0 - 80002156: 0001 nop - 80002158: 00400e93 li t4,4 - 8000215c: 01200193 li gp,18 - 80002160: 17d49663 bne s1,t4,800022cc - -0000000080002164 : - 80002164: 800004b7 lui s1,0x80000 - 80002168: fff4849b addiw s1,s1,-1 - 8000216c: 557d li a0,-1 - 8000216e: 9c89 subw s1,s1,a0 - 80002170: 80000eb7 lui t4,0x80000 - 80002174: 01300193 li gp,19 - 80002178: 15d49a63 bne s1,t4,800022cc - -000000008000217c : - 8000217c: 800004b7 lui s1,0x80000 - 80002180: fff4849b addiw s1,s1,-1 - 80002184: 4505 li a0,1 - 80002186: 9ca9 addw s1,s1,a0 - 80002188: 80000eb7 lui t4,0x80000 - 8000218c: 01400193 li gp,20 - 80002190: 13d49e63 bne s1,t4,800022cc - -0000000080002194 : - 80002194: 00001437 lui s0,0x1 - 80002198: 2344041b addiw s0,s0,564 - 8000219c: 0412 slli s0,s0,0x4 - 8000219e: 0001 nop - 800021a0: 00012eb7 lui t4,0x12 - 800021a4: 340e8e9b addiw t4,t4,832 - 800021a8: 01500193 li gp,21 - 800021ac: 13d41063 bne s0,t4,800022cc - -00000000800021b0 : - 800021b0: 4081 li ra,0 - 800021b2: a011 j 800021b6 - 800021b4: a011 j 800021b8 - 800021b6: a011 j 800021ba - 800021b8: aa11 j 800022cc - 800021ba: 0001 nop - 800021bc: 00000e93 li t4,0 - 800021c0: 01e00193 li gp,30 - 800021c4: 11d09463 bne ra,t4,800022cc - -00000000800021c8 : - 800021c8: 4501 li a0,0 - 800021ca: c111 beqz a0,800021ce - 800021cc: a011 j 800021d0 - 800021ce: a011 j 800021d2 - 800021d0: a8f5 j 800022cc - 800021d2: 0001 nop - 800021d4: 00000e93 li t4,0 - 800021d8: 01f00193 li gp,31 - 800021dc: 0fd01863 bne zero,t4,800022cc - -00000000800021e0 : - 800021e0: 4505 li a0,1 - 800021e2: e111 bnez a0,800021e6 - 800021e4: a011 j 800021e8 - 800021e6: a011 j 800021ea - 800021e8: a0d5 j 800022cc - 800021ea: 0001 nop - 800021ec: 00000e93 li t4,0 - 800021f0: 02000193 li gp,32 - 800021f4: 0dd01c63 bne zero,t4,800022cc - -00000000800021f8 : - 800021f8: 4505 li a0,1 - 800021fa: c111 beqz a0,800021fe - 800021fc: a011 j 80002200 - 800021fe: a0f9 j 800022cc - 80002200: 00000e93 li t4,0 - 80002204: 02100193 li gp,33 - 80002208: 0dd01263 bne zero,t4,800022cc - -000000008000220c : - 8000220c: 4501 li a0,0 - 8000220e: e111 bnez a0,80002212 - 80002210: a011 j 80002214 - 80002212: a86d j 800022cc - 80002214: 00000e93 li t4,0 - 80002218: 02200193 li gp,34 - 8000221c: 0bd01863 bne zero,t4,800022cc - -0000000080002220 : - 80002220: 00000297 auipc t0,0x0 - 80002224: 00e28293 addi t0,t0,14 # 8000222e - 80002228: 4081 li ra,0 - 8000222a: 8282 jr t0 - 8000222c: a011 j 80002230 - 8000222e: a011 j 80002232 - 80002230: a871 j 800022cc - 80002232: 0001 nop - 80002234: 00000e93 li t4,0 - 80002238: 02300193 li gp,35 - 8000223c: 09d09863 bne ra,t4,800022cc - -0000000080002240 : - 80002240: 00000297 auipc t0,0x0 - 80002244: 00e28293 addi t0,t0,14 # 8000224e - 80002248: 4081 li ra,0 - 8000224a: 9282 jalr t0 - 8000224c: a011 j 80002250 - 8000224e: a011 j 80002252 - 80002250: a8b5 j 800022cc - 80002252: 405080b3 sub ra,ra,t0 - 80002256: 0001 nop - 80002258: ffe00e93 li t4,-2 - 8000225c: 02400193 li gp,36 - 80002260: 07d09663 bne ra,t4,800022cc - 80002264: ffffe117 auipc sp,0xffffe - 80002268: ea410113 addi sp,sp,-348 # 80000108 - -000000008000226c : - 8000226c: 4532 lw a0,12(sp) - 8000226e: 0505 addi a0,a0,1 - 80002270: c62a sw a0,12(sp) - 80002272: 4632 lw a2,12(sp) - 80002274: fedcceb7 lui t4,0xfedcc - 80002278: a99e8e9b addiw t4,t4,-1383 - 8000227c: 02800193 li gp,40 - 80002280: 05d61663 bne a2,t4,800022cc - -0000000080002284 : - 80002284: 6522 ld a0,8(sp) - 80002286: 0505 addi a0,a0,1 - 80002288: e42a sd a0,8(sp) - 8000228a: 6622 ld a2,8(sp) - 8000228c: fff6eeb7 lui t4,0xfff6e - 80002290: 5d5e8e9b addiw t4,t4,1493 - 80002294: 00ce9e93 slli t4,t4,0xc - 80002298: cbbe8e93 addi t4,t4,-837 # fffffffffff6dcbb <_end+0xffffffff7ff69cbb> - 8000229c: 00de9e93 slli t4,t4,0xd - 800022a0: 543e8e93 addi t4,t4,1347 - 800022a4: 00ce9e93 slli t4,t4,0xc - 800022a8: 211e8e93 addi t4,t4,529 - 800022ac: 02900193 li gp,41 - 800022b0: 01d61e63 bne a2,t4,800022cc - -00000000800022b4 : - 800022b4: 12300513 li a0,291 - 800022b8: 82aa mv t0,a0 - 800022ba: 92aa add t0,t0,a0 - 800022bc: 24600e93 li t4,582 - 800022c0: 02a00193 li gp,42 - 800022c4: 01d29463 bne t0,t4,800022cc - 800022c8: 00301c63 bne zero,gp,800022e0 - -00000000800022cc : - 800022cc: 0ff0000f fence - 800022d0: 00018063 beqz gp,800022d0 - 800022d4: 00119193 slli gp,gp,0x1 - 800022d8: 0011e193 ori gp,gp,1 - 800022dc: 00000073 ecall - -00000000800022e0 : - 800022e0: 0ff0000f fence - 800022e4: 00100193 li gp,1 - 800022e8: 00000073 ecall - 800022ec: c0001073 unimp - 800022f0: 0000 unimp - 800022f2: 0000 unimp - 800022f4: 0000 unimp - 800022f6: 0000 unimp - 800022f8: 0000 unimp - 800022fa: 0000 unimp - 800022fc: 0000 unimp - 800022fe: 0000 unimp - 80002300: 0000 unimp - 80002302: 0000 unimp - 80002304: 0000 unimp - 80002306: 0000 unimp - 80002308: 0000 unimp - 8000230a: 0000 unimp - 8000230c: 0000 unimp - 8000230e: 0000 unimp - 80002310: 0000 unimp - 80002312: 0000 unimp - 80002314: 0000 unimp - 80002316: 0000 unimp - 80002318: 0000 unimp - 8000231a: 0000 unimp - 8000231c: 0000 unimp - 8000231e: 0000 unimp - 80002320: 0000 unimp - 80002322: 0000 unimp - 80002324: 0000 unimp - 80002326: 0000 unimp - 80002328: 0000 unimp - 8000232a: 0000 unimp - 8000232c: 0000 unimp - 8000232e: 0000 unimp - 80002330: 0000 unimp - 80002332: 0000 unimp - 80002334: 0000 unimp - 80002336: 0000 unimp - 80002338: 0000 unimp - 8000233a: 0000 unimp - 8000233c: 0000 unimp - 8000233e: 0000 unimp - 80002340: 0000 unimp - 80002342: 0000 unimp - 80002344: 0000 unimp - 80002346: 0000 unimp - 80002348: 0000 unimp - 8000234a: 0000 unimp - 8000234c: 0000 unimp - 8000234e: 0000 unimp - 80002350: 0000 unimp - 80002352: 0000 unimp - 80002354: 0000 unimp - 80002356: 0000 unimp - 80002358: 0000 unimp - 8000235a: 0000 unimp - 8000235c: 0000 unimp - 8000235e: 0000 unimp - 80002360: 0000 unimp - 80002362: 0000 unimp - 80002364: 0000 unimp - 80002366: 0000 unimp - 80002368: 0000 unimp - 8000236a: 0000 unimp - 8000236c: 0000 unimp - 8000236e: 0000 unimp - 80002370: 0000 unimp - 80002372: 0000 unimp - 80002374: 0000 unimp - 80002376: 0000 unimp - 80002378: 0000 unimp - 8000237a: 0000 unimp - 8000237c: 0000 unimp - 8000237e: 0000 unimp - 80002380: 0000 unimp - 80002382: 0000 unimp - 80002384: 0000 unimp - 80002386: 0000 unimp - 80002388: 0000 unimp - 8000238a: 0000 unimp - 8000238c: 0000 unimp - 8000238e: 0000 unimp - 80002390: 0000 unimp - 80002392: 0000 unimp - 80002394: 0000 unimp - 80002396: 0000 unimp - 80002398: 0000 unimp - 8000239a: 0000 unimp - 8000239c: 0000 unimp - 8000239e: 0000 unimp - 800023a0: 0000 unimp - 800023a2: 0000 unimp - 800023a4: 0000 unimp - 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80002a2e: 0000 unimp - 80002a30: 0000 unimp - 80002a32: 0000 unimp - 80002a34: 0000 unimp - 80002a36: 0000 unimp - 80002a38: 0000 unimp - 80002a3a: 0000 unimp - 80002a3c: 0000 unimp - 80002a3e: 0000 unimp - 80002a40: 0000 unimp - 80002a42: 0000 unimp - 80002a44: 0000 unimp - 80002a46: 0000 unimp - 80002a48: 0000 unimp - 80002a4a: 0000 unimp - 80002a4c: 0000 unimp - 80002a4e: 0000 unimp - 80002a50: 0000 unimp - 80002a52: 0000 unimp - 80002a54: 0000 unimp - 80002a56: 0000 unimp - 80002a58: 0000 unimp - 80002a5a: 0000 unimp - 80002a5c: 0000 unimp - 80002a5e: 0000 unimp - 80002a60: 0000 unimp - 80002a62: 0000 unimp - 80002a64: 0000 unimp - 80002a66: 0000 unimp - 80002a68: 0000 unimp - 80002a6a: 0000 unimp - 80002a6c: 0000 unimp - 80002a6e: 0000 unimp - 80002a70: 0000 unimp - 80002a72: 0000 unimp - 80002a74: 0000 unimp - 80002a76: 0000 unimp - 80002a78: 0000 unimp - 80002a7a: 0000 unimp - 80002a7c: 0000 unimp - 80002a7e: 0000 unimp - 80002a80: 0000 unimp - 80002a82: 0000 unimp - 80002a84: 0000 unimp - 80002a86: 0000 unimp - 80002a88: 0000 unimp - 80002a8a: 0000 unimp - 80002a8c: 0000 unimp - 80002a8e: 0000 unimp - 80002a90: 0000 unimp - 80002a92: 0000 unimp - 80002a94: 0000 unimp - 80002a96: 0000 unimp - 80002a98: 0000 unimp - 80002a9a: 0000 unimp - 80002a9c: 0000 unimp - 80002a9e: 0000 unimp - 80002aa0: 0000 unimp - 80002aa2: 0000 unimp - 80002aa4: 0000 unimp - 80002aa6: 0000 unimp - 80002aa8: 0000 unimp - 80002aaa: 0000 unimp - 80002aac: 0000 unimp - 80002aae: 0000 unimp - 80002ab0: 0000 unimp - 80002ab2: 0000 unimp - 80002ab4: 0000 unimp - 80002ab6: 0000 unimp - 80002ab8: 0000 unimp - 80002aba: 0000 unimp - 80002abc: 0000 unimp - 80002abe: 0000 unimp - 80002ac0: 0000 unimp - 80002ac2: 0000 unimp - 80002ac4: 0000 unimp - 80002ac6: 0000 unimp - 80002ac8: 0000 unimp - 80002aca: 0000 unimp - 80002acc: 0000 unimp - 80002ace: 0000 unimp - 80002ad0: 0000 unimp - 80002ad2: 0000 unimp - 80002ad4: 0000 unimp - 80002ad6: 0000 unimp - 80002ad8: 0000 unimp - 80002ada: 0000 unimp - 80002adc: 0000 unimp - 80002ade: 0000 unimp - 80002ae0: 0000 unimp - 80002ae2: 0000 unimp - 80002ae4: 0000 unimp - 80002ae6: 0000 unimp - 80002ae8: 0000 unimp - 80002aea: 0000 unimp - 80002aec: 0000 unimp - 80002aee: 0000 unimp - 80002af0: 0000 unimp - 80002af2: 0000 unimp - 80002af4: 0000 unimp - 80002af6: 0000 unimp - 80002af8: 0000 unimp - 80002afa: 0000 unimp - 80002afc: 0000 unimp - 80002afe: 0000 unimp - 80002b00: 0000 unimp - 80002b02: 0000 unimp - 80002b04: 0000 unimp - 80002b06: 0000 unimp - 80002b08: 0000 unimp - 80002b0a: 0000 unimp - 80002b0c: 0000 unimp - 80002b0e: 0000 unimp - 80002b10: 0000 unimp - 80002b12: 0000 unimp - 80002b14: 0000 unimp - 80002b16: 0000 unimp - 80002b18: 0000 unimp - 80002b1a: 0000 unimp - 80002b1c: 0000 unimp - 80002b1e: 0000 unimp - 80002b20: 0000 unimp - 80002b22: 0000 unimp - 80002b24: 0000 unimp - 80002b26: 0000 unimp - 80002b28: 0000 unimp - 80002b2a: 0000 unimp - 80002b2c: 0000 unimp - 80002b2e: 0000 unimp - 80002b30: 0000 unimp - 80002b32: 0000 unimp - 80002b34: 0000 unimp - 80002b36: 0000 unimp - 80002b38: 0000 unimp - 80002b3a: 0000 unimp - 80002b3c: 0000 unimp - 80002b3e: 0000 unimp - 80002b40: 0000 unimp - 80002b42: 0000 unimp - 80002b44: 0000 unimp - 80002b46: 0000 unimp - 80002b48: 0000 unimp - 80002b4a: 0000 unimp - 80002b4c: 0000 unimp - 80002b4e: 0000 unimp - 80002b50: 0000 unimp - 80002b52: 0000 unimp - 80002b54: 0000 unimp - 80002b56: 0000 unimp - 80002b58: 0000 unimp - 80002b5a: 0000 unimp - 80002b5c: 0000 unimp - 80002b5e: 0000 unimp - 80002b60: 0000 unimp - 80002b62: 0000 unimp - 80002b64: 0000 unimp - 80002b66: 0000 unimp - 80002b68: 0000 unimp - 80002b6a: 0000 unimp - 80002b6c: 0000 unimp - 80002b6e: 0000 unimp - 80002b70: 0000 unimp - 80002b72: 0000 unimp - 80002b74: 0000 unimp - 80002b76: 0000 unimp - 80002b78: 0000 unimp - 80002b7a: 0000 unimp - 80002b7c: 0000 unimp - 80002b7e: 0000 unimp - 80002b80: 0000 unimp - 80002b82: 0000 unimp - 80002b84: 0000 unimp - 80002b86: 0000 unimp - 80002b88: 0000 unimp - 80002b8a: 0000 unimp - 80002b8c: 0000 unimp - 80002b8e: 0000 unimp - 80002b90: 0000 unimp - 80002b92: 0000 unimp - 80002b94: 0000 unimp - 80002b96: 0000 unimp - 80002b98: 0000 unimp - 80002b9a: 0000 unimp - 80002b9c: 0000 unimp - 80002b9e: 0000 unimp - 80002ba0: 0000 unimp - 80002ba2: 0000 unimp - 80002ba4: 0000 unimp - 80002ba6: 0000 unimp - 80002ba8: 0000 unimp - 80002baa: 0000 unimp - 80002bac: 0000 unimp - 80002bae: 0000 unimp - 80002bb0: 0000 unimp - 80002bb2: 0000 unimp - 80002bb4: 0000 unimp - 80002bb6: 0000 unimp - 80002bb8: 0000 unimp - 80002bba: 0000 unimp - 80002bbc: 0000 unimp - 80002bbe: 0000 unimp - 80002bc0: 0000 unimp - 80002bc2: 0000 unimp - 80002bc4: 0000 unimp - 80002bc6: 0000 unimp - 80002bc8: 0000 unimp - 80002bca: 0000 unimp - 80002bcc: 0000 unimp - 80002bce: 0000 unimp - 80002bd0: 0000 unimp - 80002bd2: 0000 unimp - 80002bd4: 0000 unimp - 80002bd6: 0000 unimp - 80002bd8: 0000 unimp - 80002bda: 0000 unimp - 80002bdc: 0000 unimp - 80002bde: 0000 unimp - 80002be0: 0000 unimp - 80002be2: 0000 unimp - 80002be4: 0000 unimp - 80002be6: 0000 unimp - 80002be8: 0000 unimp - 80002bea: 0000 unimp - 80002bec: 0000 unimp - 80002bee: 0000 unimp - 80002bf0: 0000 unimp - 80002bf2: 0000 unimp - 80002bf4: 0000 unimp - 80002bf6: 0000 unimp - 80002bf8: 0000 unimp - 80002bfa: 0000 unimp - 80002bfc: 0000 unimp - 80002bfe: 0000 unimp - 80002c00: 0000 unimp - 80002c02: 0000 unimp - 80002c04: 0000 unimp - 80002c06: 0000 unimp - 80002c08: 0000 unimp - 80002c0a: 0000 unimp - 80002c0c: 0000 unimp - 80002c0e: 0000 unimp - 80002c10: 0000 unimp - 80002c12: 0000 unimp - 80002c14: 0000 unimp - 80002c16: 0000 unimp - 80002c18: 0000 unimp - 80002c1a: 0000 unimp - 80002c1c: 0000 unimp - 80002c1e: 0000 unimp - 80002c20: 0000 unimp - 80002c22: 0000 unimp - 80002c24: 0000 unimp - 80002c26: 0000 unimp - 80002c28: 0000 unimp - 80002c2a: 0000 unimp - 80002c2c: 0000 unimp - 80002c2e: 0000 unimp - 80002c30: 0000 unimp - 80002c32: 0000 unimp - 80002c34: 0000 unimp - 80002c36: 0000 unimp - 80002c38: 0000 unimp - 80002c3a: 0000 unimp - 80002c3c: 0000 unimp - 80002c3e: 0000 unimp - 80002c40: 0000 unimp - 80002c42: 0000 unimp - 80002c44: 0000 unimp - 80002c46: 0000 unimp - 80002c48: 0000 unimp - 80002c4a: 0000 unimp - 80002c4c: 0000 unimp - 80002c4e: 0000 unimp - 80002c50: 0000 unimp - 80002c52: 0000 unimp - 80002c54: 0000 unimp - 80002c56: 0000 unimp - 80002c58: 0000 unimp - 80002c5a: 0000 unimp - 80002c5c: 0000 unimp - 80002c5e: 0000 unimp - 80002c60: 0000 unimp - 80002c62: 0000 unimp - 80002c64: 0000 unimp - 80002c66: 0000 unimp - 80002c68: 0000 unimp - 80002c6a: 0000 unimp - 80002c6c: 0000 unimp - 80002c6e: 0000 unimp - 80002c70: 0000 unimp - 80002c72: 0000 unimp - 80002c74: 0000 unimp - 80002c76: 0000 unimp - 80002c78: 0000 unimp - 80002c7a: 0000 unimp - 80002c7c: 0000 unimp - 80002c7e: 0000 unimp - 80002c80: 0000 unimp - 80002c82: 0000 unimp - 80002c84: 0000 unimp - 80002c86: 0000 unimp - 80002c88: 0000 unimp - 80002c8a: 0000 unimp - 80002c8c: 0000 unimp - 80002c8e: 0000 unimp - 80002c90: 0000 unimp - 80002c92: 0000 unimp - 80002c94: 0000 unimp - 80002c96: 0000 unimp - 80002c98: 0000 unimp - 80002c9a: 0000 unimp - 80002c9c: 0000 unimp - 80002c9e: 0000 unimp - 80002ca0: 0000 unimp - 80002ca2: 0000 unimp - 80002ca4: 0000 unimp - 80002ca6: 0000 unimp - 80002ca8: 0000 unimp - 80002caa: 0000 unimp - 80002cac: 0000 unimp - 80002cae: 0000 unimp - 80002cb0: 0000 unimp - 80002cb2: 0000 unimp - 80002cb4: 0000 unimp - 80002cb6: 0000 unimp - 80002cb8: 0000 unimp - 80002cba: 0000 unimp - 80002cbc: 0000 unimp - 80002cbe: 0000 unimp - 80002cc0: 0000 unimp - 80002cc2: 0000 unimp - 80002cc4: 0000 unimp - 80002cc6: 0000 unimp - 80002cc8: 0000 unimp - 80002cca: 0000 unimp - 80002ccc: 0000 unimp - 80002cce: 0000 unimp - 80002cd0: 0000 unimp - 80002cd2: 0000 unimp - 80002cd4: 0000 unimp - 80002cd6: 0000 unimp - 80002cd8: 0000 unimp - 80002cda: 0000 unimp - 80002cdc: 0000 unimp - 80002cde: 0000 unimp - 80002ce0: 0000 unimp - 80002ce2: 0000 unimp - 80002ce4: 0000 unimp - 80002ce6: 0000 unimp - 80002ce8: 0000 unimp - 80002cea: 0000 unimp - 80002cec: 0000 unimp - 80002cee: 0000 unimp - 80002cf0: 0000 unimp - 80002cf2: 0000 unimp - 80002cf4: 0000 unimp - 80002cf6: 0000 unimp - 80002cf8: 0000 unimp - 80002cfa: 0000 unimp - 80002cfc: 0000 unimp - 80002cfe: 0000 unimp - 80002d00: 0000 unimp - 80002d02: 0000 unimp - 80002d04: 0000 unimp - 80002d06: 0000 unimp - 80002d08: 0000 unimp - 80002d0a: 0000 unimp - 80002d0c: 0000 unimp - 80002d0e: 0000 unimp - 80002d10: 0000 unimp - 80002d12: 0000 unimp - 80002d14: 0000 unimp - 80002d16: 0000 unimp - 80002d18: 0000 unimp - 80002d1a: 0000 unimp - 80002d1c: 0000 unimp - 80002d1e: 0000 unimp - 80002d20: 0000 unimp - 80002d22: 0000 unimp - 80002d24: 0000 unimp - 80002d26: 0000 unimp - 80002d28: 0000 unimp - 80002d2a: 0000 unimp - 80002d2c: 0000 unimp - 80002d2e: 0000 unimp - 80002d30: 0000 unimp - 80002d32: 0000 unimp - 80002d34: 0000 unimp - 80002d36: 0000 unimp - 80002d38: 0000 unimp - 80002d3a: 0000 unimp - 80002d3c: 0000 unimp - 80002d3e: 0000 unimp - 80002d40: 0000 unimp - 80002d42: 0000 unimp - 80002d44: 0000 unimp - 80002d46: 0000 unimp - 80002d48: 0000 unimp - 80002d4a: 0000 unimp - 80002d4c: 0000 unimp - 80002d4e: 0000 unimp - 80002d50: 0000 unimp - 80002d52: 0000 unimp - 80002d54: 0000 unimp - 80002d56: 0000 unimp - 80002d58: 0000 unimp - 80002d5a: 0000 unimp - 80002d5c: 0000 unimp - 80002d5e: 0000 unimp - 80002d60: 0000 unimp - 80002d62: 0000 unimp - 80002d64: 0000 unimp - 80002d66: 0000 unimp - 80002d68: 0000 unimp - 80002d6a: 0000 unimp - 80002d6c: 0000 unimp - 80002d6e: 0000 unimp - 80002d70: 0000 unimp - 80002d72: 0000 unimp - 80002d74: 0000 unimp - 80002d76: 0000 unimp - 80002d78: 0000 unimp - 80002d7a: 0000 unimp - 80002d7c: 0000 unimp - 80002d7e: 0000 unimp - 80002d80: 0000 unimp - 80002d82: 0000 unimp - 80002d84: 0000 unimp - 80002d86: 0000 unimp - 80002d88: 0000 unimp - 80002d8a: 0000 unimp - 80002d8c: 0000 unimp - 80002d8e: 0000 unimp - 80002d90: 0000 unimp - 80002d92: 0000 unimp - 80002d94: 0000 unimp - 80002d96: 0000 unimp - 80002d98: 0000 unimp - 80002d9a: 0000 unimp - 80002d9c: 0000 unimp - 80002d9e: 0000 unimp - 80002da0: 0000 unimp - 80002da2: 0000 unimp - 80002da4: 0000 unimp - 80002da6: 0000 unimp - 80002da8: 0000 unimp - 80002daa: 0000 unimp - 80002dac: 0000 unimp - 80002dae: 0000 unimp - 80002db0: 0000 unimp - 80002db2: 0000 unimp - 80002db4: 0000 unimp - 80002db6: 0000 unimp - 80002db8: 0000 unimp - 80002dba: 0000 unimp - 80002dbc: 0000 unimp - 80002dbe: 0000 unimp - 80002dc0: 0000 unimp - 80002dc2: 0000 unimp - 80002dc4: 0000 unimp - 80002dc6: 0000 unimp - 80002dc8: 0000 unimp - 80002dca: 0000 unimp - 80002dcc: 0000 unimp - 80002dce: 0000 unimp - 80002dd0: 0000 unimp - 80002dd2: 0000 unimp - 80002dd4: 0000 unimp - 80002dd6: 0000 unimp - 80002dd8: 0000 unimp - 80002dda: 0000 unimp - 80002ddc: 0000 unimp - 80002dde: 0000 unimp - 80002de0: 0000 unimp - 80002de2: 0000 unimp - 80002de4: 0000 unimp - 80002de6: 0000 unimp - 80002de8: 0000 unimp - 80002dea: 0000 unimp - 80002dec: 0000 unimp - 80002dee: 0000 unimp - 80002df0: 0000 unimp - 80002df2: 0000 unimp - 80002df4: 0000 unimp - 80002df6: 0000 unimp - 80002df8: 0000 unimp - 80002dfa: 0000 unimp - 80002dfc: 0000 unimp - 80002dfe: 0000 unimp - 80002e00: 0000 unimp - 80002e02: 0000 unimp - 80002e04: 0000 unimp - 80002e06: 0000 unimp - 80002e08: 0000 unimp - 80002e0a: 0000 unimp - 80002e0c: 0000 unimp - 80002e0e: 0000 unimp - 80002e10: 0000 unimp - 80002e12: 0000 unimp - 80002e14: 0000 unimp - 80002e16: 0000 unimp - 80002e18: 0000 unimp - 80002e1a: 0000 unimp - 80002e1c: 0000 unimp - 80002e1e: 0000 unimp - 80002e20: 0000 unimp - 80002e22: 0000 unimp - 80002e24: 0000 unimp - 80002e26: 0000 unimp - 80002e28: 0000 unimp - 80002e2a: 0000 unimp - 80002e2c: 0000 unimp - 80002e2e: 0000 unimp - 80002e30: 0000 unimp - 80002e32: 0000 unimp - 80002e34: 0000 unimp - 80002e36: 0000 unimp - 80002e38: 0000 unimp - 80002e3a: 0000 unimp - 80002e3c: 0000 unimp - 80002e3e: 0000 unimp - 80002e40: 0000 unimp - 80002e42: 0000 unimp - 80002e44: 0000 unimp - 80002e46: 0000 unimp - 80002e48: 0000 unimp - 80002e4a: 0000 unimp - 80002e4c: 0000 unimp - 80002e4e: 0000 unimp - 80002e50: 0000 unimp - 80002e52: 0000 unimp - 80002e54: 0000 unimp - 80002e56: 0000 unimp - 80002e58: 0000 unimp - 80002e5a: 0000 unimp - 80002e5c: 0000 unimp - 80002e5e: 0000 unimp - 80002e60: 0000 unimp - 80002e62: 0000 unimp - 80002e64: 0000 unimp - 80002e66: 0000 unimp - 80002e68: 0000 unimp - 80002e6a: 0000 unimp - 80002e6c: 0000 unimp - 80002e6e: 0000 unimp - 80002e70: 0000 unimp - 80002e72: 0000 unimp - 80002e74: 0000 unimp - 80002e76: 0000 unimp - 80002e78: 0000 unimp - 80002e7a: 0000 unimp - 80002e7c: 0000 unimp - 80002e7e: 0000 unimp - 80002e80: 0000 unimp - 80002e82: 0000 unimp - 80002e84: 0000 unimp - 80002e86: 0000 unimp - 80002e88: 0000 unimp - 80002e8a: 0000 unimp - 80002e8c: 0000 unimp - 80002e8e: 0000 unimp diff --git a/test/riscv/tests/rv64uc-p-rvc.elf b/test/riscv/tests/rv64uc-p-rvc.elf deleted file mode 100644 index 3421d31b..00000000 Binary files a/test/riscv/tests/rv64uc-p-rvc.elf and /dev/null differ diff --git a/test/riscv/tests/rv64uc-v-rvc.dump b/test/riscv/tests/rv64uc-v-rvc.dump deleted file mode 100644 index 696b038d..00000000 --- a/test/riscv/tests/rv64uc-v-rvc.dump +++ /dev/null @@ -1,6518 +0,0 @@ - -rv64uc-v-rvc: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 0000c117 auipc sp,0xc - 8000001c: 6b810113 addi sp,sp,1720 # 8000c6d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: fd050513 addi a0,a0,-48 # 80003000 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00005617 auipc a2,0x5 - 80002318: cec60613 addi a2,a2,-788 # 80007000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00009797 auipc a5,0x9 - 80002334: 4b878793 addi a5,a5,1208 # 8000b7e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00009717 auipc a4,0x9 - 80002348: 49c70713 addi a4,a4,1180 # 8000b7e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00009897 auipc a7,0x9 - 80002354: 48f8bc23 sd a5,1176(a7) # 8000b7e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00009797 auipc a5,0x9 - 80002384: 07078793 addi a5,a5,112 # 8000b3f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf4810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00009797 auipc a5,0x9 - 80002448: 3807be23 sd zero,924(a5) # 8000b7e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00004697 auipc a3,0x4 - 8000245c: b7068693 addi a3,a3,-1168 # 80005fc8 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00004617 auipc a2,0x4 - 800024b8: ba460613 addi a2,a2,-1116 # 80006058 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00004617 auipc a2,0x4 - 80002508: b6c60613 addi a2,a2,-1172 # 80006070 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00004697 auipc a3,0x4 - 80002558: abc68693 addi a3,a3,-1348 # 80006010 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00004697 auipc a3,0x4 - 80002674: ad868693 addi a3,a3,-1320 # 80006148 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00004617 auipc a2,0x4 - 800026cc: a5860613 addi a2,a2,-1448 # 80006120 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00009d17 auipc s10,0x9 - 80002720: cd4d0d13 addi s10,s10,-812 # 8000b3f0 - 80002724: 00005b97 auipc s7,0x5 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80007000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00009a17 auipc s4,0x9 - 80002738: 0aca0a13 addi s4,s4,172 # 8000b7e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00009717 auipc a4,0x9 - 8000274c: 08f73c23 sd a5,152(a4) # 8000b7e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00009717 auipc a4,0x9 - 800027d4: 00f73823 sd a5,16(a4) # 8000b7e0 - 800027d8: 00009717 auipc a4,0x9 - 800027dc: 00f73823 sd a5,16(a4) # 8000b7e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00004697 auipc a3,0x4 - 800027f0: 98c68693 addi a3,a3,-1652 # 80006178 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00004697 auipc a3,0x4 - 80002840: 8ac68693 addi a3,a3,-1876 # 800060e8 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00004697 auipc a3,0x4 - 80002878: 83c68693 addi a3,a3,-1988 # 800060b0 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00005697 auipc a3,0x5 - 800028e0: 72468693 addi a3,a3,1828 # 80008000 - 800028e4: 00006717 auipc a4,0x6 - 800028e8: 71c70713 addi a4,a4,1820 # 80009000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00007797 auipc a5,0x7 - 800028f8: 70c78793 addi a5,a5,1804 # 8000a000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00004897 auipc a7,0x4 - 80002914: 6ed8b823 sd a3,1776(a7) # 80007000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00005697 auipc a3,0x5 - 80002920: 6ce6be23 sd a4,1756(a3) # 80007ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00004617 auipc a2,0x4 - 80002938: 6cc60613 addi a2,a2,1740 # 80007000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00007697 auipc a3,0x7 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80009ff8 - 8000294c: 00005717 auipc a4,0x5 - 80002950: 6af73a23 sd a5,1716(a4) # 80008000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00008697 auipc a3,0x8 - 800029c0: 64468693 addi a3,a3,1604 # 8000b000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00009617 auipc a2,0x9 - 800029d0: e0f63e23 sd a5,-484(a2) # 8000b7e8 - 800029d4: 00009797 auipc a5,0x9 - 800029d8: e0e7b623 sd a4,-500(a5) # 8000b7e0 - 800029dc: 00009317 auipc t1,0x9 - 800029e0: a1430313 addi t1,t1,-1516 # 8000b3f0 - 800029e4: 03000793 li a5,48 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00009797 auipc a5,0x9 - 80002a40: 9a07b623 sd zero,-1620(a5) # 8000b3e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0db157b7 lui a5,0xdb15 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 50c78793 addi a5,a5,1292 # db1550c <_start-0x724eaaf4> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - 80002ac8: 0000 unimp - 80002aca: 0000 unimp - 80002acc: 0000 unimp - 80002ace: 0000 unimp - 80002ad0: 0000 unimp - 80002ad2: 0000 unimp - 80002ad4: 0000 unimp - 80002ad6: 0000 unimp - 80002ad8: 0000 unimp - 80002ada: 0000 unimp - 80002adc: 0000 unimp - 80002ade: 0000 unimp - 80002ae0: 0000 unimp - 80002ae2: 0000 unimp - 80002ae4: 0000 unimp - 80002ae6: 0000 unimp - 80002ae8: 0000 unimp - 80002aea: 0000 unimp - 80002aec: 0000 unimp - 80002aee: 0000 unimp - 80002af0: 0000 unimp - 80002af2: 0000 unimp - 80002af4: 0000 unimp - 80002af6: 0000 unimp - 80002af8: 0000 unimp - 80002afa: 0000 unimp - 80002afc: 0000 unimp - 80002afe: 0000 unimp - 80002b00: 0000 unimp - 80002b02: 0000 unimp - 80002b04: 0000 unimp - 80002b06: 0000 unimp - 80002b08: 0000 unimp - 80002b0a: 0000 unimp - 80002b0c: 0000 unimp - 80002b0e: 0000 unimp - 80002b10: 0000 unimp - 80002b12: 0000 unimp - 80002b14: 0000 unimp - 80002b16: 0000 unimp - 80002b18: 0000 unimp - 80002b1a: 0000 unimp - 80002b1c: 0000 unimp - 80002b1e: 0000 unimp - 80002b20: 0000 unimp - 80002b22: 0000 unimp - 80002b24: 0000 unimp - 80002b26: 0000 unimp - 80002b28: 0000 unimp - 80002b2a: 0000 unimp - 80002b2c: 0000 unimp - 80002b2e: 0000 unimp - 80002b30: 0000 unimp - 80002b32: 0000 unimp - 80002b34: 0000 unimp - 80002b36: 0000 unimp - 80002b38: 0000 unimp - 80002b3a: 0000 unimp - 80002b3c: 0000 unimp - 80002b3e: 0000 unimp - 80002b40: 0000 unimp - 80002b42: 0000 unimp - 80002b44: 0000 unimp - 80002b46: 0000 unimp - 80002b48: 0000 unimp - 80002b4a: 0000 unimp - 80002b4c: 0000 unimp - 80002b4e: 0000 unimp - 80002b50: 0000 unimp - 80002b52: 0000 unimp - 80002b54: 0000 unimp - 80002b56: 0000 unimp - 80002b58: 0000 unimp - 80002b5a: 0000 unimp - 80002b5c: 0000 unimp - 80002b5e: 0000 unimp - 80002b60: 0000 unimp - 80002b62: 0000 unimp - 80002b64: 0000 unimp - 80002b66: 0000 unimp - 80002b68: 0000 unimp - 80002b6a: 0000 unimp - 80002b6c: 0000 unimp - 80002b6e: 0000 unimp - 80002b70: 0000 unimp - 80002b72: 0000 unimp - 80002b74: 0000 unimp - 80002b76: 0000 unimp - 80002b78: 0000 unimp - 80002b7a: 0000 unimp - 80002b7c: 0000 unimp - 80002b7e: 0000 unimp - 80002b80: 0000 unimp - 80002b82: 0000 unimp - 80002b84: 0000 unimp - 80002b86: 0000 unimp - 80002b88: 0000 unimp - 80002b8a: 0000 unimp - 80002b8c: 0000 unimp - 80002b8e: 0000 unimp - 80002b90: 0000 unimp - 80002b92: 0000 unimp - 80002b94: 0000 unimp - 80002b96: 0000 unimp - 80002b98: 0000 unimp - 80002b9a: 0000 unimp - 80002b9c: 0000 unimp - 80002b9e: 0000 unimp - 80002ba0: 0000 unimp - 80002ba2: 0000 unimp - 80002ba4: 0000 unimp - 80002ba6: 0000 unimp - 80002ba8: 0000 unimp - 80002baa: 0000 unimp - 80002bac: 0000 unimp - 80002bae: 0000 unimp - 80002bb0: 0000 unimp - 80002bb2: 0000 unimp - 80002bb4: 0000 unimp - 80002bb6: 0000 unimp - 80002bb8: 0000 unimp - 80002bba: 0000 unimp - 80002bbc: 0000 unimp - 80002bbe: 0000 unimp - 80002bc0: 0000 unimp - 80002bc2: 0000 unimp - 80002bc4: 0000 unimp - 80002bc6: 0000 unimp - 80002bc8: 0000 unimp - 80002bca: 0000 unimp - 80002bcc: 0000 unimp - 80002bce: 0000 unimp - 80002bd0: 0000 unimp - 80002bd2: 0000 unimp - 80002bd4: 0000 unimp - 80002bd6: 0000 unimp - 80002bd8: 0000 unimp - 80002bda: 0000 unimp - 80002bdc: 0000 unimp - 80002bde: 0000 unimp - 80002be0: 0000 unimp - 80002be2: 0000 unimp - 80002be4: 0000 unimp - 80002be6: 0000 unimp - 80002be8: 0000 unimp - 80002bea: 0000 unimp - 80002bec: 0000 unimp - 80002bee: 0000 unimp - 80002bf0: 0000 unimp - 80002bf2: 0000 unimp - 80002bf4: 0000 unimp - 80002bf6: 0000 unimp - 80002bf8: 0000 unimp - 80002bfa: 0000 unimp - 80002bfc: 0000 unimp - 80002bfe: 0000 unimp - 80002c00: 0000 unimp - 80002c02: 0000 unimp - 80002c04: 0000 unimp - 80002c06: 0000 unimp - 80002c08: 0000 unimp - 80002c0a: 0000 unimp - 80002c0c: 0000 unimp - 80002c0e: 0000 unimp - 80002c10: 0000 unimp - 80002c12: 0000 unimp - 80002c14: 0000 unimp - 80002c16: 0000 unimp - 80002c18: 0000 unimp - 80002c1a: 0000 unimp - 80002c1c: 0000 unimp - 80002c1e: 0000 unimp - 80002c20: 0000 unimp - 80002c22: 0000 unimp - 80002c24: 0000 unimp - 80002c26: 0000 unimp - 80002c28: 0000 unimp - 80002c2a: 0000 unimp - 80002c2c: 0000 unimp - 80002c2e: 0000 unimp - 80002c30: 0000 unimp - 80002c32: 0000 unimp - 80002c34: 0000 unimp - 80002c36: 0000 unimp - 80002c38: 0000 unimp - 80002c3a: 0000 unimp - 80002c3c: 0000 unimp - 80002c3e: 0000 unimp - 80002c40: 0000 unimp - 80002c42: 0000 unimp - 80002c44: 0000 unimp - 80002c46: 0000 unimp - 80002c48: 0000 unimp - 80002c4a: 0000 unimp - 80002c4c: 0000 unimp - 80002c4e: 0000 unimp - 80002c50: 0000 unimp - 80002c52: 0000 unimp - 80002c54: 0000 unimp - 80002c56: 0000 unimp - 80002c58: 0000 unimp - 80002c5a: 0000 unimp - 80002c5c: 0000 unimp - 80002c5e: 0000 unimp - 80002c60: 0000 unimp - 80002c62: 0000 unimp - 80002c64: 0000 unimp - 80002c66: 0000 unimp - 80002c68: 0000 unimp - 80002c6a: 0000 unimp - 80002c6c: 0000 unimp - 80002c6e: 0000 unimp - 80002c70: 0000 unimp - 80002c72: 0000 unimp - 80002c74: 0000 unimp - 80002c76: 0000 unimp - 80002c78: 0000 unimp - 80002c7a: 0000 unimp - 80002c7c: 0000 unimp - 80002c7e: 0000 unimp - 80002c80: 0000 unimp - 80002c82: 0000 unimp - 80002c84: 0000 unimp - 80002c86: 0000 unimp - 80002c88: 0000 unimp - 80002c8a: 0000 unimp - 80002c8c: 0000 unimp - 80002c8e: 0000 unimp - 80002c90: 0000 unimp - 80002c92: 0000 unimp - 80002c94: 0000 unimp - 80002c96: 0000 unimp - 80002c98: 0000 unimp - 80002c9a: 0000 unimp - 80002c9c: 0000 unimp - 80002c9e: 0000 unimp - 80002ca0: 0000 unimp - 80002ca2: 0000 unimp - 80002ca4: 0000 unimp - 80002ca6: 0000 unimp - 80002ca8: 0000 unimp - 80002caa: 0000 unimp - 80002cac: 0000 unimp - 80002cae: 0000 unimp - 80002cb0: 0000 unimp - 80002cb2: 0000 unimp - 80002cb4: 0000 unimp - 80002cb6: 0000 unimp - 80002cb8: 0000 unimp - 80002cba: 0000 unimp - 80002cbc: 0000 unimp - 80002cbe: 0000 unimp - 80002cc0: 0000 unimp - 80002cc2: 0000 unimp - 80002cc4: 0000 unimp - 80002cc6: 0000 unimp - 80002cc8: 0000 unimp - 80002cca: 0000 unimp - 80002ccc: 0000 unimp - 80002cce: 0000 unimp - 80002cd0: 0000 unimp - 80002cd2: 0000 unimp - 80002cd4: 0000 unimp - 80002cd6: 0000 unimp - 80002cd8: 0000 unimp - 80002cda: 0000 unimp - 80002cdc: 0000 unimp - 80002cde: 0000 unimp - 80002ce0: 0000 unimp - 80002ce2: 0000 unimp - 80002ce4: 0000 unimp - 80002ce6: 0000 unimp - 80002ce8: 0000 unimp - 80002cea: 0000 unimp - 80002cec: 0000 unimp - 80002cee: 0000 unimp - 80002cf0: 0000 unimp - 80002cf2: 0000 unimp - 80002cf4: 0000 unimp - 80002cf6: 0000 unimp - 80002cf8: 0000 unimp - 80002cfa: 0000 unimp - 80002cfc: 0000 unimp - 80002cfe: 0000 unimp - 80002d00: 0000 unimp - 80002d02: 0000 unimp - 80002d04: 0000 unimp - 80002d06: 0000 unimp - 80002d08: 0000 unimp - 80002d0a: 0000 unimp - 80002d0c: 0000 unimp - 80002d0e: 0000 unimp - 80002d10: 0000 unimp - 80002d12: 0000 unimp - 80002d14: 0000 unimp - 80002d16: 0000 unimp - 80002d18: 0000 unimp - 80002d1a: 0000 unimp - 80002d1c: 0000 unimp - 80002d1e: 0000 unimp - 80002d20: 0000 unimp - 80002d22: 0000 unimp - 80002d24: 0000 unimp - 80002d26: 0000 unimp - 80002d28: 0000 unimp - 80002d2a: 0000 unimp - 80002d2c: 0000 unimp - 80002d2e: 0000 unimp - 80002d30: 0000 unimp - 80002d32: 0000 unimp - 80002d34: 0000 unimp - 80002d36: 0000 unimp - 80002d38: 0000 unimp - 80002d3a: 0000 unimp - 80002d3c: 0000 unimp - 80002d3e: 0000 unimp - 80002d40: 0000 unimp - 80002d42: 0000 unimp - 80002d44: 0000 unimp - 80002d46: 0000 unimp - 80002d48: 0000 unimp - 80002d4a: 0000 unimp - 80002d4c: 0000 unimp - 80002d4e: 0000 unimp - 80002d50: 0000 unimp - 80002d52: 0000 unimp - 80002d54: 0000 unimp - 80002d56: 0000 unimp - 80002d58: 0000 unimp - 80002d5a: 0000 unimp - 80002d5c: 0000 unimp - 80002d5e: 0000 unimp - 80002d60: 0000 unimp - 80002d62: 0000 unimp - 80002d64: 0000 unimp - 80002d66: 0000 unimp - 80002d68: 0000 unimp - 80002d6a: 0000 unimp - 80002d6c: 0000 unimp - 80002d6e: 0000 unimp - 80002d70: 0000 unimp - 80002d72: 0000 unimp - 80002d74: 0000 unimp - 80002d76: 0000 unimp - 80002d78: 0000 unimp - 80002d7a: 0000 unimp - 80002d7c: 0000 unimp - 80002d7e: 0000 unimp - 80002d80: 0000 unimp - 80002d82: 0000 unimp - 80002d84: 0000 unimp - 80002d86: 0000 unimp - 80002d88: 0000 unimp - 80002d8a: 0000 unimp - 80002d8c: 0000 unimp - 80002d8e: 0000 unimp - 80002d90: 0000 unimp - 80002d92: 0000 unimp - 80002d94: 0000 unimp - 80002d96: 0000 unimp - 80002d98: 0000 unimp - 80002d9a: 0000 unimp - 80002d9c: 0000 unimp - 80002d9e: 0000 unimp - 80002da0: 0000 unimp - 80002da2: 0000 unimp - 80002da4: 0000 unimp - 80002da6: 0000 unimp - 80002da8: 0000 unimp - 80002daa: 0000 unimp - 80002dac: 0000 unimp - 80002dae: 0000 unimp - 80002db0: 0000 unimp - 80002db2: 0000 unimp - 80002db4: 0000 unimp - 80002db6: 0000 unimp - 80002db8: 0000 unimp - 80002dba: 0000 unimp - 80002dbc: 0000 unimp - 80002dbe: 0000 unimp - 80002dc0: 0000 unimp - 80002dc2: 0000 unimp - 80002dc4: 0000 unimp - 80002dc6: 0000 unimp - 80002dc8: 0000 unimp - 80002dca: 0000 unimp - 80002dcc: 0000 unimp - 80002dce: 0000 unimp - 80002dd0: 0000 unimp - 80002dd2: 0000 unimp - 80002dd4: 0000 unimp - 80002dd6: 0000 unimp - 80002dd8: 0000 unimp - 80002dda: 0000 unimp - 80002ddc: 0000 unimp - 80002dde: 0000 unimp - 80002de0: 0000 unimp - 80002de2: 0000 unimp - 80002de4: 0000 unimp - 80002de6: 0000 unimp - 80002de8: 0000 unimp - 80002dea: 0000 unimp - 80002dec: 0000 unimp - 80002dee: 0000 unimp - 80002df0: 0000 unimp - 80002df2: 0000 unimp - 80002df4: 0000 unimp - 80002df6: 0000 unimp - 80002df8: 0000 unimp - 80002dfa: 0000 unimp - 80002dfc: 0000 unimp - 80002dfe: 0000 unimp - 80002e00: 0000 unimp - 80002e02: 0000 unimp - 80002e04: 0000 unimp - 80002e06: 0000 unimp - 80002e08: 0000 unimp - 80002e0a: 0000 unimp - 80002e0c: 0000 unimp - 80002e0e: 0000 unimp - 80002e10: 0000 unimp - 80002e12: 0000 unimp - 80002e14: 0000 unimp - 80002e16: 0000 unimp - 80002e18: 0000 unimp - 80002e1a: 0000 unimp - 80002e1c: 0000 unimp - 80002e1e: 0000 unimp - 80002e20: 0000 unimp - 80002e22: 0000 unimp - 80002e24: 0000 unimp - 80002e26: 0000 unimp - 80002e28: 0000 unimp - 80002e2a: 0000 unimp - 80002e2c: 0000 unimp - 80002e2e: 0000 unimp - 80002e30: 0000 unimp - 80002e32: 0000 unimp - 80002e34: 0000 unimp - 80002e36: 0000 unimp - 80002e38: 0000 unimp - 80002e3a: 0000 unimp - 80002e3c: 0000 unimp - 80002e3e: 0000 unimp - 80002e40: 0000 unimp - 80002e42: 0000 unimp - 80002e44: 0000 unimp - 80002e46: 0000 unimp - 80002e48: 0000 unimp - 80002e4a: 0000 unimp - 80002e4c: 0000 unimp - 80002e4e: 0000 unimp - 80002e50: 0000 unimp - 80002e52: 0000 unimp - 80002e54: 0000 unimp - 80002e56: 0000 unimp - 80002e58: 0000 unimp - 80002e5a: 0000 unimp - 80002e5c: 0000 unimp - 80002e5e: 0000 unimp - 80002e60: 0000 unimp - 80002e62: 0000 unimp - 80002e64: 0000 unimp - 80002e66: 0000 unimp - 80002e68: 0000 unimp - 80002e6a: 0000 unimp - 80002e6c: 0000 unimp - 80002e6e: 0000 unimp - 80002e70: 0000 unimp - 80002e72: 0000 unimp - 80002e74: 0000 unimp - 80002e76: 0000 unimp - 80002e78: 0000 unimp - 80002e7a: 0000 unimp - 80002e7c: 0000 unimp - 80002e7e: 0000 unimp - 80002e80: 0000 unimp - 80002e82: 0000 unimp - 80002e84: 0000 unimp - 80002e86: 0000 unimp - 80002e88: 0000 unimp - 80002e8a: 0000 unimp - 80002e8c: 0000 unimp - 80002e8e: 0000 unimp - 80002e90: 0000 unimp - 80002e92: 0000 unimp - 80002e94: 0000 unimp - 80002e96: 0000 unimp - 80002e98: 0000 unimp - 80002e9a: 0000 unimp - 80002e9c: 0000 unimp - 80002e9e: 0000 unimp - 80002ea0: 0000 unimp - 80002ea2: 0000 unimp - 80002ea4: 0000 unimp - 80002ea6: 0000 unimp - 80002ea8: 0000 unimp - 80002eaa: 0000 unimp - 80002eac: 0000 unimp - 80002eae: 0000 unimp - 80002eb0: 0000 unimp - 80002eb2: 0000 unimp - 80002eb4: 0000 unimp - 80002eb6: 0000 unimp - 80002eb8: 0000 unimp - 80002eba: 0000 unimp - 80002ebc: 0000 unimp - 80002ebe: 0000 unimp - 80002ec0: 0000 unimp - 80002ec2: 0000 unimp - 80002ec4: 0000 unimp - 80002ec6: 0000 unimp - 80002ec8: 0000 unimp - 80002eca: 0000 unimp - 80002ecc: 0000 unimp - 80002ece: 0000 unimp - 80002ed0: 0000 unimp - 80002ed2: 0000 unimp - 80002ed4: 0000 unimp - 80002ed6: 0000 unimp - 80002ed8: 0000 unimp - 80002eda: 0000 unimp - 80002edc: 0000 unimp - 80002ede: 0000 unimp - 80002ee0: 0000 unimp - 80002ee2: 0000 unimp - 80002ee4: 0000 unimp - 80002ee6: 0000 unimp - 80002ee8: 0000 unimp - 80002eea: 0000 unimp - 80002eec: 0000 unimp - 80002eee: 0000 unimp - 80002ef0: 0000 unimp - 80002ef2: 0000 unimp - 80002ef4: 0000 unimp - 80002ef6: 0000 unimp - 80002ef8: 0000 unimp - 80002efa: 0000 unimp - 80002efc: 0000 unimp - 80002efe: 0000 unimp - 80002f00: 0000 unimp - 80002f02: 0000 unimp - 80002f04: 0000 unimp - 80002f06: 0000 unimp - 80002f08: 0000 unimp - 80002f0a: 0000 unimp - 80002f0c: 0000 unimp - 80002f0e: 0000 unimp - 80002f10: 0000 unimp - 80002f12: 0000 unimp - 80002f14: 0000 unimp - 80002f16: 0000 unimp - 80002f18: 0000 unimp - 80002f1a: 0000 unimp - 80002f1c: 0000 unimp - 80002f1e: 0000 unimp - 80002f20: 0000 unimp - 80002f22: 0000 unimp - 80002f24: 0000 unimp - 80002f26: 0000 unimp - 80002f28: 0000 unimp - 80002f2a: 0000 unimp - 80002f2c: 0000 unimp - 80002f2e: 0000 unimp - 80002f30: 0000 unimp - 80002f32: 0000 unimp - 80002f34: 0000 unimp - 80002f36: 0000 unimp - 80002f38: 0000 unimp - 80002f3a: 0000 unimp - 80002f3c: 0000 unimp - 80002f3e: 0000 unimp - 80002f40: 0000 unimp - 80002f42: 0000 unimp - 80002f44: 0000 unimp - 80002f46: 0000 unimp - 80002f48: 0000 unimp - 80002f4a: 0000 unimp - 80002f4c: 0000 unimp - 80002f4e: 0000 unimp - 80002f50: 0000 unimp - 80002f52: 0000 unimp - 80002f54: 0000 unimp - 80002f56: 0000 unimp - 80002f58: 0000 unimp - 80002f5a: 0000 unimp - 80002f5c: 0000 unimp - 80002f5e: 0000 unimp - 80002f60: 0000 unimp - 80002f62: 0000 unimp - 80002f64: 0000 unimp - 80002f66: 0000 unimp - 80002f68: 0000 unimp - 80002f6a: 0000 unimp - 80002f6c: 0000 unimp - 80002f6e: 0000 unimp - 80002f70: 0000 unimp - 80002f72: 0000 unimp - 80002f74: 0000 unimp - 80002f76: 0000 unimp - 80002f78: 0000 unimp - 80002f7a: 0000 unimp - 80002f7c: 0000 unimp - 80002f7e: 0000 unimp - 80002f80: 0000 unimp - 80002f82: 0000 unimp - 80002f84: 0000 unimp - 80002f86: 0000 unimp - 80002f88: 0000 unimp - 80002f8a: 0000 unimp - 80002f8c: 0000 unimp - 80002f8e: 0000 unimp - 80002f90: 0000 unimp - 80002f92: 0000 unimp - 80002f94: 0000 unimp - 80002f96: 0000 unimp - 80002f98: 0000 unimp - 80002f9a: 0000 unimp - 80002f9c: 0000 unimp - 80002f9e: 0000 unimp - 80002fa0: 0000 unimp - 80002fa2: 0000 unimp - 80002fa4: 0000 unimp - 80002fa6: 0000 unimp - 80002fa8: 0000 unimp - 80002faa: 0000 unimp - 80002fac: 0000 unimp - 80002fae: 0000 unimp - 80002fb0: 0000 unimp - 80002fb2: 0000 unimp - 80002fb4: 0000 unimp - 80002fb6: 0000 unimp - 80002fb8: 0000 unimp - 80002fba: 0000 unimp - 80002fbc: 0000 unimp - 80002fbe: 0000 unimp - 80002fc0: 0000 unimp - 80002fc2: 0000 unimp - 80002fc4: 0000 unimp - 80002fc6: 0000 unimp - 80002fc8: 0000 unimp - 80002fca: 0000 unimp - 80002fcc: 0000 unimp - 80002fce: 0000 unimp - 80002fd0: 0000 unimp - 80002fd2: 0000 unimp - 80002fd4: 0000 unimp - 80002fd6: 0000 unimp - 80002fd8: 0000 unimp - 80002fda: 0000 unimp - 80002fdc: 0000 unimp - 80002fde: 0000 unimp - 80002fe0: 0000 unimp - 80002fe2: 0000 unimp - 80002fe4: 0000 unimp - 80002fe6: 0000 unimp - 80002fe8: 0000 unimp - 80002fea: 0000 unimp - 80002fec: 0000 unimp - 80002fee: 0000 unimp - 80002ff0: 0000 unimp - 80002ff2: 0000 unimp - 80002ff4: 0000 unimp - 80002ff6: 0000 unimp - 80002ff8: 0000 unimp - 80002ffa: 0000 unimp - 80002ffc: 0000 unimp - 80002ffe: 0000 unimp - -0000000080003000 : - 80003000: 00200193 li gp,2 - 80003004: 29a00593 li a1,666 - -0000000080003008 : - 80003008: 7f70106f j 80004ffe - 8000300c: 00000013 nop - -0000000080003010 : - 80003010: 3210 fld fa2,32(a2) - 80003012: 7654 ld a3,168(a2) - 80003014: ba98 fsd fa4,48(a3) - 80003016: fedc sd a5,184(a3) - 80003018: 3210 fld fa2,32(a2) - 8000301a: 7654 ld a3,168(a2) - 8000301c: ba98 fsd fa4,48(a3) - 8000301e: fedc sd a5,184(a3) - 80003020: 00000013 nop - 80003024: 00000013 nop - 80003028: 00000013 nop - 8000302c: 00000013 nop - 80003030: 00000013 nop - 80003034: 00000013 nop - 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80004a92: 0000 unimp - 80004a94: 0000 unimp - 80004a96: 0000 unimp - 80004a98: 0000 unimp - 80004a9a: 0000 unimp - 80004a9c: 0000 unimp - 80004a9e: 0000 unimp - 80004aa0: 0000 unimp - 80004aa2: 0000 unimp - 80004aa4: 0000 unimp - 80004aa6: 0000 unimp - 80004aa8: 0000 unimp - 80004aaa: 0000 unimp - 80004aac: 0000 unimp - 80004aae: 0000 unimp - 80004ab0: 0000 unimp - 80004ab2: 0000 unimp - 80004ab4: 0000 unimp - 80004ab6: 0000 unimp - 80004ab8: 0000 unimp - 80004aba: 0000 unimp - 80004abc: 0000 unimp - 80004abe: 0000 unimp - 80004ac0: 0000 unimp - 80004ac2: 0000 unimp - 80004ac4: 0000 unimp - 80004ac6: 0000 unimp - 80004ac8: 0000 unimp - 80004aca: 0000 unimp - 80004acc: 0000 unimp - 80004ace: 0000 unimp - 80004ad0: 0000 unimp - 80004ad2: 0000 unimp - 80004ad4: 0000 unimp - 80004ad6: 0000 unimp - 80004ad8: 0000 unimp - 80004ada: 0000 unimp - 80004adc: 0000 unimp - 80004ade: 0000 unimp - 80004ae0: 0000 unimp - 80004ae2: 0000 unimp - 80004ae4: 0000 unimp - 80004ae6: 0000 unimp - 80004ae8: 0000 unimp - 80004aea: 0000 unimp - 80004aec: 0000 unimp - 80004aee: 0000 unimp - 80004af0: 0000 unimp - 80004af2: 0000 unimp - 80004af4: 0000 unimp - 80004af6: 0000 unimp - 80004af8: 0000 unimp - 80004afa: 0000 unimp - 80004afc: 0000 unimp - 80004afe: 0000 unimp - 80004b00: 0000 unimp - 80004b02: 0000 unimp - 80004b04: 0000 unimp - 80004b06: 0000 unimp - 80004b08: 0000 unimp - 80004b0a: 0000 unimp - 80004b0c: 0000 unimp - 80004b0e: 0000 unimp - 80004b10: 0000 unimp - 80004b12: 0000 unimp - 80004b14: 0000 unimp - 80004b16: 0000 unimp - 80004b18: 0000 unimp - 80004b1a: 0000 unimp - 80004b1c: 0000 unimp - 80004b1e: 0000 unimp - 80004b20: 0000 unimp - 80004b22: 0000 unimp - 80004b24: 0000 unimp - 80004b26: 0000 unimp - 80004b28: 0000 unimp - 80004b2a: 0000 unimp - 80004b2c: 0000 unimp - 80004b2e: 0000 unimp - 80004b30: 0000 unimp - 80004b32: 0000 unimp - 80004b34: 0000 unimp - 80004b36: 0000 unimp - 80004b38: 0000 unimp - 80004b3a: 0000 unimp - 80004b3c: 0000 unimp - 80004b3e: 0000 unimp - 80004b40: 0000 unimp - 80004b42: 0000 unimp - 80004b44: 0000 unimp - 80004b46: 0000 unimp - 80004b48: 0000 unimp - 80004b4a: 0000 unimp - 80004b4c: 0000 unimp - 80004b4e: 0000 unimp - 80004b50: 0000 unimp - 80004b52: 0000 unimp - 80004b54: 0000 unimp - 80004b56: 0000 unimp - 80004b58: 0000 unimp - 80004b5a: 0000 unimp - 80004b5c: 0000 unimp - 80004b5e: 0000 unimp - 80004b60: 0000 unimp - 80004b62: 0000 unimp - 80004b64: 0000 unimp - 80004b66: 0000 unimp - 80004b68: 0000 unimp - 80004b6a: 0000 unimp - 80004b6c: 0000 unimp - 80004b6e: 0000 unimp - 80004b70: 0000 unimp - 80004b72: 0000 unimp - 80004b74: 0000 unimp - 80004b76: 0000 unimp - 80004b78: 0000 unimp - 80004b7a: 0000 unimp - 80004b7c: 0000 unimp - 80004b7e: 0000 unimp - 80004b80: 0000 unimp - 80004b82: 0000 unimp - 80004b84: 0000 unimp - 80004b86: 0000 unimp - 80004b88: 0000 unimp - 80004b8a: 0000 unimp - 80004b8c: 0000 unimp - 80004b8e: 0000 unimp - 80004b90: 0000 unimp - 80004b92: 0000 unimp - 80004b94: 0000 unimp - 80004b96: 0000 unimp - 80004b98: 0000 unimp - 80004b9a: 0000 unimp - 80004b9c: 0000 unimp - 80004b9e: 0000 unimp - 80004ba0: 0000 unimp - 80004ba2: 0000 unimp - 80004ba4: 0000 unimp - 80004ba6: 0000 unimp - 80004ba8: 0000 unimp - 80004baa: 0000 unimp - 80004bac: 0000 unimp - 80004bae: 0000 unimp - 80004bb0: 0000 unimp - 80004bb2: 0000 unimp - 80004bb4: 0000 unimp - 80004bb6: 0000 unimp - 80004bb8: 0000 unimp - 80004bba: 0000 unimp - 80004bbc: 0000 unimp - 80004bbe: 0000 unimp - 80004bc0: 0000 unimp - 80004bc2: 0000 unimp - 80004bc4: 0000 unimp - 80004bc6: 0000 unimp - 80004bc8: 0000 unimp - 80004bca: 0000 unimp - 80004bcc: 0000 unimp - 80004bce: 0000 unimp - 80004bd0: 0000 unimp - 80004bd2: 0000 unimp - 80004bd4: 0000 unimp - 80004bd6: 0000 unimp - 80004bd8: 0000 unimp - 80004bda: 0000 unimp - 80004bdc: 0000 unimp - 80004bde: 0000 unimp - 80004be0: 0000 unimp - 80004be2: 0000 unimp - 80004be4: 0000 unimp - 80004be6: 0000 unimp - 80004be8: 0000 unimp - 80004bea: 0000 unimp - 80004bec: 0000 unimp - 80004bee: 0000 unimp - 80004bf0: 0000 unimp - 80004bf2: 0000 unimp - 80004bf4: 0000 unimp - 80004bf6: 0000 unimp - 80004bf8: 0000 unimp - 80004bfa: 0000 unimp - 80004bfc: 0000 unimp - 80004bfe: 0000 unimp - 80004c00: 0000 unimp - 80004c02: 0000 unimp - 80004c04: 0000 unimp - 80004c06: 0000 unimp - 80004c08: 0000 unimp - 80004c0a: 0000 unimp - 80004c0c: 0000 unimp - 80004c0e: 0000 unimp - 80004c10: 0000 unimp - 80004c12: 0000 unimp - 80004c14: 0000 unimp - 80004c16: 0000 unimp - 80004c18: 0000 unimp - 80004c1a: 0000 unimp - 80004c1c: 0000 unimp - 80004c1e: 0000 unimp - 80004c20: 0000 unimp - 80004c22: 0000 unimp - 80004c24: 0000 unimp - 80004c26: 0000 unimp - 80004c28: 0000 unimp - 80004c2a: 0000 unimp - 80004c2c: 0000 unimp - 80004c2e: 0000 unimp - 80004c30: 0000 unimp - 80004c32: 0000 unimp - 80004c34: 0000 unimp - 80004c36: 0000 unimp - 80004c38: 0000 unimp - 80004c3a: 0000 unimp - 80004c3c: 0000 unimp - 80004c3e: 0000 unimp - 80004c40: 0000 unimp - 80004c42: 0000 unimp - 80004c44: 0000 unimp - 80004c46: 0000 unimp - 80004c48: 0000 unimp - 80004c4a: 0000 unimp - 80004c4c: 0000 unimp - 80004c4e: 0000 unimp - 80004c50: 0000 unimp - 80004c52: 0000 unimp - 80004c54: 0000 unimp - 80004c56: 0000 unimp - 80004c58: 0000 unimp - 80004c5a: 0000 unimp - 80004c5c: 0000 unimp - 80004c5e: 0000 unimp - 80004c60: 0000 unimp - 80004c62: 0000 unimp - 80004c64: 0000 unimp - 80004c66: 0000 unimp - 80004c68: 0000 unimp - 80004c6a: 0000 unimp - 80004c6c: 0000 unimp - 80004c6e: 0000 unimp - 80004c70: 0000 unimp - 80004c72: 0000 unimp - 80004c74: 0000 unimp - 80004c76: 0000 unimp - 80004c78: 0000 unimp - 80004c7a: 0000 unimp - 80004c7c: 0000 unimp - 80004c7e: 0000 unimp - 80004c80: 0000 unimp - 80004c82: 0000 unimp - 80004c84: 0000 unimp - 80004c86: 0000 unimp - 80004c88: 0000 unimp - 80004c8a: 0000 unimp - 80004c8c: 0000 unimp - 80004c8e: 0000 unimp - 80004c90: 0000 unimp - 80004c92: 0000 unimp - 80004c94: 0000 unimp - 80004c96: 0000 unimp - 80004c98: 0000 unimp - 80004c9a: 0000 unimp - 80004c9c: 0000 unimp - 80004c9e: 0000 unimp - 80004ca0: 0000 unimp - 80004ca2: 0000 unimp - 80004ca4: 0000 unimp - 80004ca6: 0000 unimp - 80004ca8: 0000 unimp - 80004caa: 0000 unimp - 80004cac: 0000 unimp - 80004cae: 0000 unimp - 80004cb0: 0000 unimp - 80004cb2: 0000 unimp - 80004cb4: 0000 unimp - 80004cb6: 0000 unimp - 80004cb8: 0000 unimp - 80004cba: 0000 unimp - 80004cbc: 0000 unimp - 80004cbe: 0000 unimp - 80004cc0: 0000 unimp - 80004cc2: 0000 unimp - 80004cc4: 0000 unimp - 80004cc6: 0000 unimp - 80004cc8: 0000 unimp - 80004cca: 0000 unimp - 80004ccc: 0000 unimp - 80004cce: 0000 unimp - 80004cd0: 0000 unimp - 80004cd2: 0000 unimp - 80004cd4: 0000 unimp - 80004cd6: 0000 unimp - 80004cd8: 0000 unimp - 80004cda: 0000 unimp - 80004cdc: 0000 unimp - 80004cde: 0000 unimp - 80004ce0: 0000 unimp - 80004ce2: 0000 unimp - 80004ce4: 0000 unimp - 80004ce6: 0000 unimp - 80004ce8: 0000 unimp - 80004cea: 0000 unimp - 80004cec: 0000 unimp - 80004cee: 0000 unimp - 80004cf0: 0000 unimp - 80004cf2: 0000 unimp - 80004cf4: 0000 unimp - 80004cf6: 0000 unimp - 80004cf8: 0000 unimp - 80004cfa: 0000 unimp - 80004cfc: 0000 unimp - 80004cfe: 0000 unimp - 80004d00: 0000 unimp - 80004d02: 0000 unimp - 80004d04: 0000 unimp - 80004d06: 0000 unimp - 80004d08: 0000 unimp - 80004d0a: 0000 unimp - 80004d0c: 0000 unimp - 80004d0e: 0000 unimp - 80004d10: 0000 unimp - 80004d12: 0000 unimp - 80004d14: 0000 unimp - 80004d16: 0000 unimp - 80004d18: 0000 unimp - 80004d1a: 0000 unimp - 80004d1c: 0000 unimp - 80004d1e: 0000 unimp - 80004d20: 0000 unimp - 80004d22: 0000 unimp - 80004d24: 0000 unimp - 80004d26: 0000 unimp - 80004d28: 0000 unimp - 80004d2a: 0000 unimp - 80004d2c: 0000 unimp - 80004d2e: 0000 unimp - 80004d30: 0000 unimp - 80004d32: 0000 unimp - 80004d34: 0000 unimp - 80004d36: 0000 unimp - 80004d38: 0000 unimp - 80004d3a: 0000 unimp - 80004d3c: 0000 unimp - 80004d3e: 0000 unimp - 80004d40: 0000 unimp - 80004d42: 0000 unimp - 80004d44: 0000 unimp - 80004d46: 0000 unimp - 80004d48: 0000 unimp - 80004d4a: 0000 unimp - 80004d4c: 0000 unimp - 80004d4e: 0000 unimp - 80004d50: 0000 unimp - 80004d52: 0000 unimp - 80004d54: 0000 unimp - 80004d56: 0000 unimp - 80004d58: 0000 unimp - 80004d5a: 0000 unimp - 80004d5c: 0000 unimp - 80004d5e: 0000 unimp - 80004d60: 0000 unimp - 80004d62: 0000 unimp - 80004d64: 0000 unimp - 80004d66: 0000 unimp - 80004d68: 0000 unimp - 80004d6a: 0000 unimp - 80004d6c: 0000 unimp - 80004d6e: 0000 unimp - 80004d70: 0000 unimp - 80004d72: 0000 unimp - 80004d74: 0000 unimp - 80004d76: 0000 unimp - 80004d78: 0000 unimp - 80004d7a: 0000 unimp - 80004d7c: 0000 unimp - 80004d7e: 0000 unimp - 80004d80: 0000 unimp - 80004d82: 0000 unimp - 80004d84: 0000 unimp - 80004d86: 0000 unimp - 80004d88: 0000 unimp - 80004d8a: 0000 unimp - 80004d8c: 0000 unimp - 80004d8e: 0000 unimp - 80004d90: 0000 unimp - 80004d92: 0000 unimp - 80004d94: 0000 unimp - 80004d96: 0000 unimp - 80004d98: 0000 unimp - 80004d9a: 0000 unimp - 80004d9c: 0000 unimp - 80004d9e: 0000 unimp - 80004da0: 0000 unimp - 80004da2: 0000 unimp - 80004da4: 0000 unimp - 80004da6: 0000 unimp - 80004da8: 0000 unimp - 80004daa: 0000 unimp - 80004dac: 0000 unimp - 80004dae: 0000 unimp - 80004db0: 0000 unimp - 80004db2: 0000 unimp - 80004db4: 0000 unimp - 80004db6: 0000 unimp - 80004db8: 0000 unimp - 80004dba: 0000 unimp - 80004dbc: 0000 unimp - 80004dbe: 0000 unimp - 80004dc0: 0000 unimp - 80004dc2: 0000 unimp - 80004dc4: 0000 unimp - 80004dc6: 0000 unimp - 80004dc8: 0000 unimp - 80004dca: 0000 unimp - 80004dcc: 0000 unimp - 80004dce: 0000 unimp - 80004dd0: 0000 unimp - 80004dd2: 0000 unimp - 80004dd4: 0000 unimp - 80004dd6: 0000 unimp - 80004dd8: 0000 unimp - 80004dda: 0000 unimp - 80004ddc: 0000 unimp - 80004dde: 0000 unimp - 80004de0: 0000 unimp - 80004de2: 0000 unimp - 80004de4: 0000 unimp - 80004de6: 0000 unimp - 80004de8: 0000 unimp - 80004dea: 0000 unimp - 80004dec: 0000 unimp - 80004dee: 0000 unimp - 80004df0: 0000 unimp - 80004df2: 0000 unimp - 80004df4: 0000 unimp - 80004df6: 0000 unimp - 80004df8: 0000 unimp - 80004dfa: 0000 unimp - 80004dfc: 0000 unimp - 80004dfe: 0000 unimp - 80004e00: 0000 unimp - 80004e02: 0000 unimp - 80004e04: 0000 unimp - 80004e06: 0000 unimp - 80004e08: 0000 unimp - 80004e0a: 0000 unimp - 80004e0c: 0000 unimp - 80004e0e: 0000 unimp - 80004e10: 0000 unimp - 80004e12: 0000 unimp - 80004e14: 0000 unimp - 80004e16: 0000 unimp - 80004e18: 0000 unimp - 80004e1a: 0000 unimp - 80004e1c: 0000 unimp - 80004e1e: 0000 unimp - 80004e20: 0000 unimp - 80004e22: 0000 unimp - 80004e24: 0000 unimp - 80004e26: 0000 unimp - 80004e28: 0000 unimp - 80004e2a: 0000 unimp - 80004e2c: 0000 unimp - 80004e2e: 0000 unimp - 80004e30: 0000 unimp - 80004e32: 0000 unimp - 80004e34: 0000 unimp - 80004e36: 0000 unimp - 80004e38: 0000 unimp - 80004e3a: 0000 unimp - 80004e3c: 0000 unimp - 80004e3e: 0000 unimp - 80004e40: 0000 unimp - 80004e42: 0000 unimp - 80004e44: 0000 unimp - 80004e46: 0000 unimp - 80004e48: 0000 unimp - 80004e4a: 0000 unimp - 80004e4c: 0000 unimp - 80004e4e: 0000 unimp - 80004e50: 0000 unimp - 80004e52: 0000 unimp - 80004e54: 0000 unimp - 80004e56: 0000 unimp - 80004e58: 0000 unimp - 80004e5a: 0000 unimp - 80004e5c: 0000 unimp - 80004e5e: 0000 unimp - 80004e60: 0000 unimp - 80004e62: 0000 unimp - 80004e64: 0000 unimp - 80004e66: 0000 unimp - 80004e68: 0000 unimp - 80004e6a: 0000 unimp - 80004e6c: 0000 unimp - 80004e6e: 0000 unimp - 80004e70: 0000 unimp - 80004e72: 0000 unimp - 80004e74: 0000 unimp - 80004e76: 0000 unimp - 80004e78: 0000 unimp - 80004e7a: 0000 unimp - 80004e7c: 0000 unimp - 80004e7e: 0000 unimp - 80004e80: 0000 unimp - 80004e82: 0000 unimp - 80004e84: 0000 unimp - 80004e86: 0000 unimp - 80004e88: 0000 unimp - 80004e8a: 0000 unimp - 80004e8c: 0000 unimp - 80004e8e: 0000 unimp - 80004e90: 0000 unimp - 80004e92: 0000 unimp - 80004e94: 0000 unimp - 80004e96: 0000 unimp - 80004e98: 0000 unimp - 80004e9a: 0000 unimp - 80004e9c: 0000 unimp - 80004e9e: 0000 unimp - 80004ea0: 0000 unimp - 80004ea2: 0000 unimp - 80004ea4: 0000 unimp - 80004ea6: 0000 unimp - 80004ea8: 0000 unimp - 80004eaa: 0000 unimp - 80004eac: 0000 unimp - 80004eae: 0000 unimp - 80004eb0: 0000 unimp - 80004eb2: 0000 unimp - 80004eb4: 0000 unimp - 80004eb6: 0000 unimp - 80004eb8: 0000 unimp - 80004eba: 0000 unimp - 80004ebc: 0000 unimp - 80004ebe: 0000 unimp - 80004ec0: 0000 unimp - 80004ec2: 0000 unimp - 80004ec4: 0000 unimp - 80004ec6: 0000 unimp - 80004ec8: 0000 unimp - 80004eca: 0000 unimp - 80004ecc: 0000 unimp - 80004ece: 0000 unimp - 80004ed0: 0000 unimp - 80004ed2: 0000 unimp - 80004ed4: 0000 unimp - 80004ed6: 0000 unimp - 80004ed8: 0000 unimp - 80004eda: 0000 unimp - 80004edc: 0000 unimp - 80004ede: 0000 unimp - 80004ee0: 0000 unimp - 80004ee2: 0000 unimp - 80004ee4: 0000 unimp - 80004ee6: 0000 unimp - 80004ee8: 0000 unimp - 80004eea: 0000 unimp - 80004eec: 0000 unimp - 80004eee: 0000 unimp - 80004ef0: 0000 unimp - 80004ef2: 0000 unimp - 80004ef4: 0000 unimp - 80004ef6: 0000 unimp - 80004ef8: 0000 unimp - 80004efa: 0000 unimp - 80004efc: 0000 unimp - 80004efe: 0000 unimp - 80004f00: 0000 unimp - 80004f02: 0000 unimp - 80004f04: 0000 unimp - 80004f06: 0000 unimp - 80004f08: 0000 unimp - 80004f0a: 0000 unimp - 80004f0c: 0000 unimp - 80004f0e: 0000 unimp - 80004f10: 0000 unimp - 80004f12: 0000 unimp - 80004f14: 0000 unimp - 80004f16: 0000 unimp - 80004f18: 0000 unimp - 80004f1a: 0000 unimp - 80004f1c: 0000 unimp - 80004f1e: 0000 unimp - 80004f20: 0000 unimp - 80004f22: 0000 unimp - 80004f24: 0000 unimp - 80004f26: 0000 unimp - 80004f28: 0000 unimp - 80004f2a: 0000 unimp - 80004f2c: 0000 unimp - 80004f2e: 0000 unimp - 80004f30: 0000 unimp - 80004f32: 0000 unimp - 80004f34: 0000 unimp - 80004f36: 0000 unimp - 80004f38: 0000 unimp - 80004f3a: 0000 unimp - 80004f3c: 0000 unimp - 80004f3e: 0000 unimp - 80004f40: 0000 unimp - 80004f42: 0000 unimp - 80004f44: 0000 unimp - 80004f46: 0000 unimp - 80004f48: 0000 unimp - 80004f4a: 0000 unimp - 80004f4c: 0000 unimp - 80004f4e: 0000 unimp - 80004f50: 0000 unimp - 80004f52: 0000 unimp - 80004f54: 0000 unimp - 80004f56: 0000 unimp - 80004f58: 0000 unimp - 80004f5a: 0000 unimp - 80004f5c: 0000 unimp - 80004f5e: 0000 unimp - 80004f60: 0000 unimp - 80004f62: 0000 unimp - 80004f64: 0000 unimp - 80004f66: 0000 unimp - 80004f68: 0000 unimp - 80004f6a: 0000 unimp - 80004f6c: 0000 unimp - 80004f6e: 0000 unimp - 80004f70: 0000 unimp - 80004f72: 0000 unimp - 80004f74: 0000 unimp - 80004f76: 0000 unimp - 80004f78: 0000 unimp - 80004f7a: 0000 unimp - 80004f7c: 0000 unimp - 80004f7e: 0000 unimp - 80004f80: 0000 unimp - 80004f82: 0000 unimp - 80004f84: 0000 unimp - 80004f86: 0000 unimp - 80004f88: 0000 unimp - 80004f8a: 0000 unimp - 80004f8c: 0000 unimp - 80004f8e: 0000 unimp - 80004f90: 0000 unimp - 80004f92: 0000 unimp - 80004f94: 0000 unimp - 80004f96: 0000 unimp - 80004f98: 0000 unimp - 80004f9a: 0000 unimp - 80004f9c: 0000 unimp - 80004f9e: 0000 unimp - 80004fa0: 0000 unimp - 80004fa2: 0000 unimp - 80004fa4: 0000 unimp - 80004fa6: 0000 unimp - 80004fa8: 0000 unimp - 80004faa: 0000 unimp - 80004fac: 0000 unimp - 80004fae: 0000 unimp - 80004fb0: 0000 unimp - 80004fb2: 0000 unimp - 80004fb4: 0000 unimp - 80004fb6: 0000 unimp - 80004fb8: 0000 unimp - 80004fba: 0000 unimp - 80004fbc: 0000 unimp - 80004fbe: 0000 unimp - 80004fc0: 0000 unimp - 80004fc2: 0000 unimp - 80004fc4: 0000 unimp - 80004fc6: 0000 unimp - 80004fc8: 0000 unimp - 80004fca: 0000 unimp - 80004fcc: 0000 unimp - 80004fce: 0000 unimp - 80004fd0: 0000 unimp - 80004fd2: 0000 unimp - 80004fd4: 0000 unimp - 80004fd6: 0000 unimp - 80004fd8: 0000 unimp - 80004fda: 0000 unimp - 80004fdc: 0000 unimp - 80004fde: 0000 unimp - 80004fe0: 0000 unimp - 80004fe2: 0000 unimp - 80004fe4: 0000 unimp - 80004fe6: 0000 unimp - 80004fe8: 0000 unimp - 80004fea: 0000 unimp - 80004fec: 0000 unimp - 80004fee: 0000 unimp - 80004ff0: 0000 unimp - 80004ff2: 0000 unimp - 80004ff4: 0000 unimp - 80004ff6: 0000 unimp - 80004ff8: 0000 unimp - 80004ffa: 0000 unimp - 80004ffc: 0000 unimp - 80004ffe: 00158593 addi a1,a1,1 - 80005002: 29b00e93 li t4,667 - 80005006: 00200193 li gp,2 - 8000500a: 2dd59163 bne a1,t4,800052cc - 8000500e: 00001137 lui sp,0x1 - 80005012: 2341011b addiw sp,sp,564 - -0000000080005016 : - 80005016: 1fe8 addi a0,sp,1020 - 80005018: 00001eb7 lui t4,0x1 - 8000501c: 630e8e9b addiw t4,t4,1584 - 80005020: 00300193 li gp,3 - 80005024: 2bd51463 bne a0,t4,800052cc - -0000000080005028 : - 80005028: 617d addi sp,sp,496 - 8000502a: 0001 nop - 8000502c: 00001eb7 lui t4,0x1 - 80005030: 424e8e9b addiw t4,t4,1060 - 80005034: 00400193 li gp,4 - 80005038: 29d11a63 bne sp,t4,800052cc - -000000008000503c : - 8000503c: 7101 addi sp,sp,-512 - 8000503e: 0001 nop - 80005040: 00001eb7 lui t4,0x1 - 80005044: 224e8e9b addiw t4,t4,548 - 80005048: 00500193 li gp,5 - 8000504c: 29d11063 bne sp,t4,800052cc - 80005050: ffffe597 auipc a1,0xffffe - 80005054: fc058593 addi a1,a1,-64 # 80003010 - -0000000080005058 : - 80005058: 41c8 lw a0,4(a1) - 8000505a: 0505 addi a0,a0,1 - 8000505c: c1c8 sw a0,4(a1) - 8000505e: 41d0 lw a2,4(a1) - 80005060: fedcceb7 lui t4,0xfedcc - 80005064: a99e8e9b addiw t4,t4,-1383 - 80005068: 00600193 li gp,6 - 8000506c: 27d61063 bne a2,t4,800052cc - -0000000080005070 : - 80005070: 6188 ld a0,0(a1) - 80005072: 0505 addi a0,a0,1 - 80005074: e188 sd a0,0(a1) - 80005076: 6190 ld a2,0(a1) - 80005078: fff6eeb7 lui t4,0xfff6e - 8000507c: 5d5e8e9b addiw t4,t4,1493 - 80005080: 00ce9e93 slli t4,t4,0xc - 80005084: cbbe8e93 addi t4,t4,-837 # fffffffffff6dcbb <_end+0xffffffff7ff624cb> - 80005088: 00de9e93 slli t4,t4,0xd - 8000508c: 543e8e93 addi t4,t4,1347 - 80005090: 00ce9e93 slli t4,t4,0xc - 80005094: 211e8e93 addi t4,t4,529 - 80005098: 00700193 li gp,7 - 8000509c: 23d61863 bne a2,t4,800052cc - -00000000800050a0 : - 800050a0: 00106513 ori a0,zero,1 - 800050a4: 1541 addi a0,a0,-16 - 800050a6: 0001 nop - 800050a8: ff100e93 li t4,-15 - 800050ac: 00800193 li gp,8 - 800050b0: 21d51e63 bne a0,t4,800052cc - -00000000800050b4 : - 800050b4: 00106793 ori a5,zero,1 - 800050b8: 57c1 li a5,-16 - 800050ba: 0001 nop - 800050bc: ff000e93 li t4,-16 - 800050c0: 00900193 li gp,9 - 800050c4: 21d79463 bne a5,t4,800052cc - -00000000800050c8 : - 800050c8: 6188 ld a0,0(a1) - 800050ca: 357d addiw a0,a0,-1 - 800050cc: 76543eb7 lui t4,0x76543 - 800050d0: 210e8e9b addiw t4,t4,528 - 800050d4: 00a00193 li gp,10 - 800050d8: 1fd51a63 bne a0,t4,800052cc - -00000000800050dc : - 800050dc: 7405 lui s0,0xfffe1 - 800050de: 8431 srai s0,s0,0xc - 800050e0: fe100e93 li t4,-31 - 800050e4: 00b00193 li gp,11 - 800050e8: 1fd41263 bne s0,t4,800052cc - -00000000800050ec : - 800050ec: 7405 lui s0,0xfffe1 - 800050ee: 8031 srli s0,s0,0xc - 800050f0: 00100e9b addiw t4,zero,1 - 800050f4: 034e9e93 slli t4,t4,0x34 - 800050f8: fe1e8e93 addi t4,t4,-31 # 76542fe1 <_start-0x9abd01f> - 800050fc: 00c00193 li gp,12 - 80005100: 1dd41663 bne s0,t4,800052cc - -0000000080005104 : - 80005104: 5479 li s0,-2 - 80005106: 983d andi s0,s0,-17 - 80005108: fee00e93 li t4,-18 - 8000510c: 00e00193 li gp,14 - 80005110: 1bd41e63 bne s0,t4,800052cc - -0000000080005114 : - 80005114: 44d1 li s1,20 - 80005116: 4519 li a0,6 - 80005118: 8c89 sub s1,s1,a0 - 8000511a: 0001 nop - 8000511c: 00e00e93 li t4,14 - 80005120: 00f00193 li gp,15 - 80005124: 1bd49463 bne s1,t4,800052cc - -0000000080005128 : - 80005128: 44d1 li s1,20 - 8000512a: 4519 li a0,6 - 8000512c: 8ca9 xor s1,s1,a0 - 8000512e: 0001 nop - 80005130: 01200e93 li t4,18 - 80005134: 01000193 li gp,16 - 80005138: 19d49a63 bne s1,t4,800052cc - -000000008000513c : - 8000513c: 44d1 li s1,20 - 8000513e: 4519 li a0,6 - 80005140: 8cc9 or s1,s1,a0 - 80005142: 0001 nop - 80005144: 01600e93 li t4,22 - 80005148: 01100193 li gp,17 - 8000514c: 19d49063 bne s1,t4,800052cc - -0000000080005150 : - 80005150: 44d1 li s1,20 - 80005152: 4519 li a0,6 - 80005154: 8ce9 and s1,s1,a0 - 80005156: 0001 nop - 80005158: 00400e93 li t4,4 - 8000515c: 01200193 li gp,18 - 80005160: 17d49663 bne s1,t4,800052cc - -0000000080005164 : - 80005164: 800004b7 lui s1,0x80000 - 80005168: fff4849b addiw s1,s1,-1 - 8000516c: 557d li a0,-1 - 8000516e: 9c89 subw s1,s1,a0 - 80005170: 80000eb7 lui t4,0x80000 - 80005174: 01300193 li gp,19 - 80005178: 15d49a63 bne s1,t4,800052cc - -000000008000517c : - 8000517c: 800004b7 lui s1,0x80000 - 80005180: fff4849b addiw s1,s1,-1 - 80005184: 4505 li a0,1 - 80005186: 9ca9 addw s1,s1,a0 - 80005188: 80000eb7 lui t4,0x80000 - 8000518c: 01400193 li gp,20 - 80005190: 13d49e63 bne s1,t4,800052cc - -0000000080005194 : - 80005194: 00001437 lui s0,0x1 - 80005198: 2344041b addiw s0,s0,564 - 8000519c: 0412 slli s0,s0,0x4 - 8000519e: 0001 nop - 800051a0: 00012eb7 lui t4,0x12 - 800051a4: 340e8e9b addiw t4,t4,832 - 800051a8: 01500193 li gp,21 - 800051ac: 13d41063 bne s0,t4,800052cc - -00000000800051b0 : - 800051b0: 4081 li ra,0 - 800051b2: a011 j 800051b6 - 800051b4: a011 j 800051b8 - 800051b6: a011 j 800051ba - 800051b8: aa11 j 800052cc - 800051ba: 0001 nop - 800051bc: 00000e93 li t4,0 - 800051c0: 01e00193 li gp,30 - 800051c4: 11d09463 bne ra,t4,800052cc - -00000000800051c8 : - 800051c8: 4501 li a0,0 - 800051ca: c111 beqz a0,800051ce - 800051cc: a011 j 800051d0 - 800051ce: a011 j 800051d2 - 800051d0: a8f5 j 800052cc - 800051d2: 0001 nop - 800051d4: 00000e93 li t4,0 - 800051d8: 01f00193 li gp,31 - 800051dc: 0fd01863 bne zero,t4,800052cc - -00000000800051e0 : - 800051e0: 4505 li a0,1 - 800051e2: e111 bnez a0,800051e6 - 800051e4: a011 j 800051e8 - 800051e6: a011 j 800051ea - 800051e8: a0d5 j 800052cc - 800051ea: 0001 nop - 800051ec: 00000e93 li t4,0 - 800051f0: 02000193 li gp,32 - 800051f4: 0dd01c63 bne zero,t4,800052cc - -00000000800051f8 : - 800051f8: 4505 li a0,1 - 800051fa: c111 beqz a0,800051fe - 800051fc: a011 j 80005200 - 800051fe: a0f9 j 800052cc - 80005200: 00000e93 li t4,0 - 80005204: 02100193 li gp,33 - 80005208: 0dd01263 bne zero,t4,800052cc - -000000008000520c : - 8000520c: 4501 li a0,0 - 8000520e: e111 bnez a0,80005212 - 80005210: a011 j 80005214 - 80005212: a86d j 800052cc - 80005214: 00000e93 li t4,0 - 80005218: 02200193 li gp,34 - 8000521c: 0bd01863 bne zero,t4,800052cc - -0000000080005220 : - 80005220: 00000297 auipc t0,0x0 - 80005224: 00e28293 addi t0,t0,14 # 8000522e - 80005228: 4081 li ra,0 - 8000522a: 8282 jr t0 - 8000522c: a011 j 80005230 - 8000522e: a011 j 80005232 - 80005230: a871 j 800052cc - 80005232: 0001 nop - 80005234: 00000e93 li t4,0 - 80005238: 02300193 li gp,35 - 8000523c: 09d09863 bne ra,t4,800052cc - -0000000080005240 : - 80005240: 00000297 auipc t0,0x0 - 80005244: 00e28293 addi t0,t0,14 # 8000524e - 80005248: 4081 li ra,0 - 8000524a: 9282 jalr t0 - 8000524c: a011 j 80005250 - 8000524e: a011 j 80005252 - 80005250: a8b5 j 800052cc - 80005252: 405080b3 sub ra,ra,t0 - 80005256: 0001 nop - 80005258: ffe00e93 li t4,-2 - 8000525c: 02400193 li gp,36 - 80005260: 07d09663 bne ra,t4,800052cc - 80005264: ffffe117 auipc sp,0xffffe - 80005268: dac10113 addi sp,sp,-596 # 80003010 - -000000008000526c : - 8000526c: 4532 lw a0,12(sp) - 8000526e: 0505 addi a0,a0,1 - 80005270: c62a sw a0,12(sp) - 80005272: 4632 lw a2,12(sp) - 80005274: fedcceb7 lui t4,0xfedcc - 80005278: a99e8e9b addiw t4,t4,-1383 - 8000527c: 02800193 li gp,40 - 80005280: 05d61663 bne a2,t4,800052cc - -0000000080005284 : - 80005284: 6522 ld a0,8(sp) - 80005286: 0505 addi a0,a0,1 - 80005288: e42a sd a0,8(sp) - 8000528a: 6622 ld a2,8(sp) - 8000528c: fff6eeb7 lui t4,0xfff6e - 80005290: 5d5e8e9b addiw t4,t4,1493 - 80005294: 00ce9e93 slli t4,t4,0xc - 80005298: cbbe8e93 addi t4,t4,-837 # fffffffffff6dcbb <_end+0xffffffff7ff624cb> - 8000529c: 00de9e93 slli t4,t4,0xd - 800052a0: 543e8e93 addi t4,t4,1347 - 800052a4: 00ce9e93 slli t4,t4,0xc - 800052a8: 211e8e93 addi t4,t4,529 - 800052ac: 02900193 li gp,41 - 800052b0: 01d61e63 bne a2,t4,800052cc - -00000000800052b4 : - 800052b4: 12300513 li a0,291 - 800052b8: 82aa mv t0,a0 - 800052ba: 92aa add t0,t0,a0 - 800052bc: 24600e93 li t4,582 - 800052c0: 02a00193 li gp,42 - 800052c4: 01d29463 bne t0,t4,800052cc - 800052c8: 00301a63 bne zero,gp,800052dc - -00000000800052cc : - 800052cc: 00119513 slli a0,gp,0x1 - 800052d0: 00050063 beqz a0,800052d0 - 800052d4: 00156513 ori a0,a0,1 - 800052d8: 00000073 ecall - -00000000800052dc : - 800052dc: 00100513 li a0,1 - 800052e0: 00000073 ecall - 800052e4: c0001073 unimp - 800052e8: 0000 unimp - 800052ea: 0000 unimp - 800052ec: 0000 unimp - 800052ee: 0000 unimp - 800052f0: 0000 unimp - 800052f2: 0000 unimp - 800052f4: 0000 unimp - 800052f6: 0000 unimp - 800052f8: 0000 unimp - 800052fa: 0000 unimp - 800052fc: 0000 unimp - 800052fe: 0000 unimp - 80005300: 0000 unimp - 80005302: 0000 unimp - 80005304: 0000 unimp - 80005306: 0000 unimp - 80005308: 0000 unimp - 8000530a: 0000 unimp - 8000530c: 0000 unimp - 8000530e: 0000 unimp - 80005310: 0000 unimp - 80005312: 0000 unimp - 80005314: 0000 unimp - 80005316: 0000 unimp - 80005318: 0000 unimp - 8000531a: 0000 unimp - 8000531c: 0000 unimp - 8000531e: 0000 unimp - 80005320: 0000 unimp - 80005322: 0000 unimp - 80005324: 0000 unimp - 80005326: 0000 unimp - 80005328: 0000 unimp - 8000532a: 0000 unimp - 8000532c: 0000 unimp - 8000532e: 0000 unimp - 80005330: 0000 unimp - 80005332: 0000 unimp - 80005334: 0000 unimp - 80005336: 0000 unimp - 80005338: 0000 unimp - 8000533a: 0000 unimp - 8000533c: 0000 unimp - 8000533e: 0000 unimp - 80005340: 0000 unimp - 80005342: 0000 unimp - 80005344: 0000 unimp - 80005346: 0000 unimp - 80005348: 0000 unimp - 8000534a: 0000 unimp - 8000534c: 0000 unimp - 8000534e: 0000 unimp - 80005350: 0000 unimp - 80005352: 0000 unimp - 80005354: 0000 unimp - 80005356: 0000 unimp - 80005358: 0000 unimp - 8000535a: 0000 unimp - 8000535c: 0000 unimp - 8000535e: 0000 unimp - 80005360: 0000 unimp - 80005362: 0000 unimp - 80005364: 0000 unimp - 80005366: 0000 unimp - 80005368: 0000 unimp - 8000536a: 0000 unimp - 8000536c: 0000 unimp - 8000536e: 0000 unimp - 80005370: 0000 unimp - 80005372: 0000 unimp - 80005374: 0000 unimp - 80005376: 0000 unimp - 80005378: 0000 unimp - 8000537a: 0000 unimp - 8000537c: 0000 unimp - 8000537e: 0000 unimp - 80005380: 0000 unimp - 80005382: 0000 unimp - 80005384: 0000 unimp - 80005386: 0000 unimp - 80005388: 0000 unimp - 8000538a: 0000 unimp - 8000538c: 0000 unimp - 8000538e: 0000 unimp - 80005390: 0000 unimp - 80005392: 0000 unimp - 80005394: 0000 unimp - 80005396: 0000 unimp - 80005398: 0000 unimp - 8000539a: 0000 unimp - 8000539c: 0000 unimp - 8000539e: 0000 unimp - 800053a0: 0000 unimp - 800053a2: 0000 unimp - 800053a4: 0000 unimp - 800053a6: 0000 unimp - 800053a8: 0000 unimp - 800053aa: 0000 unimp - 800053ac: 0000 unimp - 800053ae: 0000 unimp - 800053b0: 0000 unimp - 800053b2: 0000 unimp - 800053b4: 0000 unimp - 800053b6: 0000 unimp - 800053b8: 0000 unimp - 800053ba: 0000 unimp - 800053bc: 0000 unimp - 800053be: 0000 unimp - 800053c0: 0000 unimp - 800053c2: 0000 unimp - 800053c4: 0000 unimp - 800053c6: 0000 unimp - 800053c8: 0000 unimp - 800053ca: 0000 unimp - 800053cc: 0000 unimp - 800053ce: 0000 unimp - 800053d0: 0000 unimp - 800053d2: 0000 unimp - 800053d4: 0000 unimp - 800053d6: 0000 unimp - 800053d8: 0000 unimp - 800053da: 0000 unimp - 800053dc: 0000 unimp - 800053de: 0000 unimp - 800053e0: 0000 unimp - 800053e2: 0000 unimp - 800053e4: 0000 unimp - 800053e6: 0000 unimp - 800053e8: 0000 unimp - 800053ea: 0000 unimp - 800053ec: 0000 unimp - 800053ee: 0000 unimp - 800053f0: 0000 unimp - 800053f2: 0000 unimp - 800053f4: 0000 unimp - 800053f6: 0000 unimp - 800053f8: 0000 unimp - 800053fa: 0000 unimp - 800053fc: 0000 unimp - 800053fe: 0000 unimp - 80005400: 0000 unimp - 80005402: 0000 unimp - 80005404: 0000 unimp - 80005406: 0000 unimp - 80005408: 0000 unimp - 8000540a: 0000 unimp - 8000540c: 0000 unimp - 8000540e: 0000 unimp - 80005410: 0000 unimp - 80005412: 0000 unimp - 80005414: 0000 unimp - 80005416: 0000 unimp - 80005418: 0000 unimp - 8000541a: 0000 unimp - 8000541c: 0000 unimp - 8000541e: 0000 unimp - 80005420: 0000 unimp - 80005422: 0000 unimp - 80005424: 0000 unimp - 80005426: 0000 unimp - 80005428: 0000 unimp - 8000542a: 0000 unimp - 8000542c: 0000 unimp - 8000542e: 0000 unimp - 80005430: 0000 unimp - 80005432: 0000 unimp - 80005434: 0000 unimp - 80005436: 0000 unimp - 80005438: 0000 unimp - 8000543a: 0000 unimp - 8000543c: 0000 unimp - 8000543e: 0000 unimp - 80005440: 0000 unimp - 80005442: 0000 unimp - 80005444: 0000 unimp - 80005446: 0000 unimp - 80005448: 0000 unimp - 8000544a: 0000 unimp - 8000544c: 0000 unimp - 8000544e: 0000 unimp - 80005450: 0000 unimp - 80005452: 0000 unimp - 80005454: 0000 unimp - 80005456: 0000 unimp - 80005458: 0000 unimp - 8000545a: 0000 unimp - 8000545c: 0000 unimp - 8000545e: 0000 unimp - 80005460: 0000 unimp - 80005462: 0000 unimp - 80005464: 0000 unimp - 80005466: 0000 unimp - 80005468: 0000 unimp - 8000546a: 0000 unimp - 8000546c: 0000 unimp - 8000546e: 0000 unimp - 80005470: 0000 unimp - 80005472: 0000 unimp - 80005474: 0000 unimp - 80005476: 0000 unimp - 80005478: 0000 unimp - 8000547a: 0000 unimp - 8000547c: 0000 unimp - 8000547e: 0000 unimp - 80005480: 0000 unimp - 80005482: 0000 unimp - 80005484: 0000 unimp - 80005486: 0000 unimp - 80005488: 0000 unimp - 8000548a: 0000 unimp - 8000548c: 0000 unimp - 8000548e: 0000 unimp - 80005490: 0000 unimp - 80005492: 0000 unimp - 80005494: 0000 unimp - 80005496: 0000 unimp - 80005498: 0000 unimp - 8000549a: 0000 unimp - 8000549c: 0000 unimp - 8000549e: 0000 unimp - 800054a0: 0000 unimp - 800054a2: 0000 unimp - 800054a4: 0000 unimp - 800054a6: 0000 unimp - 800054a8: 0000 unimp - 800054aa: 0000 unimp - 800054ac: 0000 unimp - 800054ae: 0000 unimp - 800054b0: 0000 unimp - 800054b2: 0000 unimp - 800054b4: 0000 unimp - 800054b6: 0000 unimp - 800054b8: 0000 unimp - 800054ba: 0000 unimp - 800054bc: 0000 unimp - 800054be: 0000 unimp - 800054c0: 0000 unimp - 800054c2: 0000 unimp - 800054c4: 0000 unimp - 800054c6: 0000 unimp - 800054c8: 0000 unimp - 800054ca: 0000 unimp - 800054cc: 0000 unimp - 800054ce: 0000 unimp - 800054d0: 0000 unimp - 800054d2: 0000 unimp - 800054d4: 0000 unimp - 800054d6: 0000 unimp - 800054d8: 0000 unimp - 800054da: 0000 unimp - 800054dc: 0000 unimp - 800054de: 0000 unimp - 800054e0: 0000 unimp - 800054e2: 0000 unimp - 800054e4: 0000 unimp - 800054e6: 0000 unimp - 800054e8: 0000 unimp - 800054ea: 0000 unimp - 800054ec: 0000 unimp - 800054ee: 0000 unimp - 800054f0: 0000 unimp - 800054f2: 0000 unimp - 800054f4: 0000 unimp - 800054f6: 0000 unimp - 800054f8: 0000 unimp - 800054fa: 0000 unimp - 800054fc: 0000 unimp - 800054fe: 0000 unimp - 80005500: 0000 unimp - 80005502: 0000 unimp - 80005504: 0000 unimp - 80005506: 0000 unimp - 80005508: 0000 unimp - 8000550a: 0000 unimp - 8000550c: 0000 unimp - 8000550e: 0000 unimp - 80005510: 0000 unimp - 80005512: 0000 unimp - 80005514: 0000 unimp - 80005516: 0000 unimp - 80005518: 0000 unimp - 8000551a: 0000 unimp - 8000551c: 0000 unimp - 8000551e: 0000 unimp - 80005520: 0000 unimp - 80005522: 0000 unimp - 80005524: 0000 unimp - 80005526: 0000 unimp - 80005528: 0000 unimp - 8000552a: 0000 unimp - 8000552c: 0000 unimp - 8000552e: 0000 unimp - 80005530: 0000 unimp - 80005532: 0000 unimp - 80005534: 0000 unimp - 80005536: 0000 unimp - 80005538: 0000 unimp - 8000553a: 0000 unimp - 8000553c: 0000 unimp - 8000553e: 0000 unimp - 80005540: 0000 unimp - 80005542: 0000 unimp - 80005544: 0000 unimp - 80005546: 0000 unimp - 80005548: 0000 unimp - 8000554a: 0000 unimp - 8000554c: 0000 unimp - 8000554e: 0000 unimp - 80005550: 0000 unimp - 80005552: 0000 unimp - 80005554: 0000 unimp - 80005556: 0000 unimp - 80005558: 0000 unimp - 8000555a: 0000 unimp - 8000555c: 0000 unimp - 8000555e: 0000 unimp - 80005560: 0000 unimp - 80005562: 0000 unimp - 80005564: 0000 unimp - 80005566: 0000 unimp - 80005568: 0000 unimp - 8000556a: 0000 unimp - 8000556c: 0000 unimp - 8000556e: 0000 unimp - 80005570: 0000 unimp - 80005572: 0000 unimp - 80005574: 0000 unimp - 80005576: 0000 unimp - 80005578: 0000 unimp - 8000557a: 0000 unimp - 8000557c: 0000 unimp - 8000557e: 0000 unimp - 80005580: 0000 unimp - 80005582: 0000 unimp - 80005584: 0000 unimp - 80005586: 0000 unimp - 80005588: 0000 unimp - 8000558a: 0000 unimp - 8000558c: 0000 unimp - 8000558e: 0000 unimp - 80005590: 0000 unimp - 80005592: 0000 unimp - 80005594: 0000 unimp - 80005596: 0000 unimp - 80005598: 0000 unimp - 8000559a: 0000 unimp - 8000559c: 0000 unimp - 8000559e: 0000 unimp - 800055a0: 0000 unimp - 800055a2: 0000 unimp - 800055a4: 0000 unimp - 800055a6: 0000 unimp - 800055a8: 0000 unimp - 800055aa: 0000 unimp - 800055ac: 0000 unimp - 800055ae: 0000 unimp - 800055b0: 0000 unimp - 800055b2: 0000 unimp - 800055b4: 0000 unimp - 800055b6: 0000 unimp - 800055b8: 0000 unimp - 800055ba: 0000 unimp - 800055bc: 0000 unimp - 800055be: 0000 unimp - 800055c0: 0000 unimp - 800055c2: 0000 unimp - 800055c4: 0000 unimp - 800055c6: 0000 unimp - 800055c8: 0000 unimp - 800055ca: 0000 unimp - 800055cc: 0000 unimp - 800055ce: 0000 unimp - 800055d0: 0000 unimp - 800055d2: 0000 unimp - 800055d4: 0000 unimp - 800055d6: 0000 unimp - 800055d8: 0000 unimp - 800055da: 0000 unimp - 800055dc: 0000 unimp - 800055de: 0000 unimp - 800055e0: 0000 unimp - 800055e2: 0000 unimp - 800055e4: 0000 unimp - 800055e6: 0000 unimp - 800055e8: 0000 unimp - 800055ea: 0000 unimp - 800055ec: 0000 unimp - 800055ee: 0000 unimp - 800055f0: 0000 unimp - 800055f2: 0000 unimp - 800055f4: 0000 unimp - 800055f6: 0000 unimp - 800055f8: 0000 unimp - 800055fa: 0000 unimp - 800055fc: 0000 unimp - 800055fe: 0000 unimp - 80005600: 0000 unimp - 80005602: 0000 unimp - 80005604: 0000 unimp - 80005606: 0000 unimp - 80005608: 0000 unimp - 8000560a: 0000 unimp - 8000560c: 0000 unimp - 8000560e: 0000 unimp - 80005610: 0000 unimp - 80005612: 0000 unimp - 80005614: 0000 unimp - 80005616: 0000 unimp - 80005618: 0000 unimp - 8000561a: 0000 unimp - 8000561c: 0000 unimp - 8000561e: 0000 unimp - 80005620: 0000 unimp - 80005622: 0000 unimp - 80005624: 0000 unimp - 80005626: 0000 unimp - 80005628: 0000 unimp - 8000562a: 0000 unimp - 8000562c: 0000 unimp - 8000562e: 0000 unimp - 80005630: 0000 unimp - 80005632: 0000 unimp - 80005634: 0000 unimp - 80005636: 0000 unimp - 80005638: 0000 unimp - 8000563a: 0000 unimp - 8000563c: 0000 unimp - 8000563e: 0000 unimp - 80005640: 0000 unimp - 80005642: 0000 unimp - 80005644: 0000 unimp - 80005646: 0000 unimp - 80005648: 0000 unimp - 8000564a: 0000 unimp - 8000564c: 0000 unimp - 8000564e: 0000 unimp - 80005650: 0000 unimp - 80005652: 0000 unimp - 80005654: 0000 unimp - 80005656: 0000 unimp - 80005658: 0000 unimp - 8000565a: 0000 unimp - 8000565c: 0000 unimp - 8000565e: 0000 unimp - 80005660: 0000 unimp - 80005662: 0000 unimp - 80005664: 0000 unimp - 80005666: 0000 unimp - 80005668: 0000 unimp - 8000566a: 0000 unimp - 8000566c: 0000 unimp - 8000566e: 0000 unimp - 80005670: 0000 unimp - 80005672: 0000 unimp - 80005674: 0000 unimp - 80005676: 0000 unimp - 80005678: 0000 unimp - 8000567a: 0000 unimp - 8000567c: 0000 unimp - 8000567e: 0000 unimp - 80005680: 0000 unimp - 80005682: 0000 unimp - 80005684: 0000 unimp - 80005686: 0000 unimp - 80005688: 0000 unimp - 8000568a: 0000 unimp - 8000568c: 0000 unimp - 8000568e: 0000 unimp - 80005690: 0000 unimp - 80005692: 0000 unimp - 80005694: 0000 unimp - 80005696: 0000 unimp - 80005698: 0000 unimp - 8000569a: 0000 unimp - 8000569c: 0000 unimp - 8000569e: 0000 unimp - 800056a0: 0000 unimp - 800056a2: 0000 unimp - 800056a4: 0000 unimp - 800056a6: 0000 unimp - 800056a8: 0000 unimp - 800056aa: 0000 unimp - 800056ac: 0000 unimp - 800056ae: 0000 unimp - 800056b0: 0000 unimp - 800056b2: 0000 unimp - 800056b4: 0000 unimp - 800056b6: 0000 unimp - 800056b8: 0000 unimp - 800056ba: 0000 unimp - 800056bc: 0000 unimp - 800056be: 0000 unimp - 800056c0: 0000 unimp - 800056c2: 0000 unimp - 800056c4: 0000 unimp - 800056c6: 0000 unimp - 800056c8: 0000 unimp - 800056ca: 0000 unimp - 800056cc: 0000 unimp - 800056ce: 0000 unimp - 800056d0: 0000 unimp - 800056d2: 0000 unimp - 800056d4: 0000 unimp - 800056d6: 0000 unimp - 800056d8: 0000 unimp - 800056da: 0000 unimp - 800056dc: 0000 unimp - 800056de: 0000 unimp - 800056e0: 0000 unimp - 800056e2: 0000 unimp - 800056e4: 0000 unimp - 800056e6: 0000 unimp - 800056e8: 0000 unimp - 800056ea: 0000 unimp - 800056ec: 0000 unimp - 800056ee: 0000 unimp - 800056f0: 0000 unimp - 800056f2: 0000 unimp - 800056f4: 0000 unimp - 800056f6: 0000 unimp - 800056f8: 0000 unimp - 800056fa: 0000 unimp - 800056fc: 0000 unimp - 800056fe: 0000 unimp - 80005700: 0000 unimp - 80005702: 0000 unimp - 80005704: 0000 unimp - 80005706: 0000 unimp - 80005708: 0000 unimp - 8000570a: 0000 unimp - 8000570c: 0000 unimp - 8000570e: 0000 unimp - 80005710: 0000 unimp - 80005712: 0000 unimp - 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800059d4: 0000 unimp - 800059d6: 0000 unimp - 800059d8: 0000 unimp - 800059da: 0000 unimp - 800059dc: 0000 unimp - 800059de: 0000 unimp - 800059e0: 0000 unimp - 800059e2: 0000 unimp - 800059e4: 0000 unimp - 800059e6: 0000 unimp - 800059e8: 0000 unimp - 800059ea: 0000 unimp - 800059ec: 0000 unimp - 800059ee: 0000 unimp - 800059f0: 0000 unimp - 800059f2: 0000 unimp - 800059f4: 0000 unimp - 800059f6: 0000 unimp - 800059f8: 0000 unimp - 800059fa: 0000 unimp - 800059fc: 0000 unimp - 800059fe: 0000 unimp - 80005a00: 0000 unimp - 80005a02: 0000 unimp - 80005a04: 0000 unimp - 80005a06: 0000 unimp - 80005a08: 0000 unimp - 80005a0a: 0000 unimp - 80005a0c: 0000 unimp - 80005a0e: 0000 unimp - 80005a10: 0000 unimp - 80005a12: 0000 unimp - 80005a14: 0000 unimp - 80005a16: 0000 unimp - 80005a18: 0000 unimp - 80005a1a: 0000 unimp - 80005a1c: 0000 unimp - 80005a1e: 0000 unimp - 80005a20: 0000 unimp - 80005a22: 0000 unimp - 80005a24: 0000 unimp - 80005a26: 0000 unimp - 80005a28: 0000 unimp - 80005a2a: 0000 unimp - 80005a2c: 0000 unimp - 80005a2e: 0000 unimp - 80005a30: 0000 unimp - 80005a32: 0000 unimp - 80005a34: 0000 unimp - 80005a36: 0000 unimp - 80005a38: 0000 unimp - 80005a3a: 0000 unimp - 80005a3c: 0000 unimp - 80005a3e: 0000 unimp - 80005a40: 0000 unimp - 80005a42: 0000 unimp - 80005a44: 0000 unimp - 80005a46: 0000 unimp - 80005a48: 0000 unimp - 80005a4a: 0000 unimp - 80005a4c: 0000 unimp - 80005a4e: 0000 unimp - 80005a50: 0000 unimp - 80005a52: 0000 unimp - 80005a54: 0000 unimp - 80005a56: 0000 unimp - 80005a58: 0000 unimp - 80005a5a: 0000 unimp - 80005a5c: 0000 unimp - 80005a5e: 0000 unimp - 80005a60: 0000 unimp - 80005a62: 0000 unimp - 80005a64: 0000 unimp - 80005a66: 0000 unimp - 80005a68: 0000 unimp - 80005a6a: 0000 unimp - 80005a6c: 0000 unimp - 80005a6e: 0000 unimp - 80005a70: 0000 unimp - 80005a72: 0000 unimp - 80005a74: 0000 unimp - 80005a76: 0000 unimp - 80005a78: 0000 unimp - 80005a7a: 0000 unimp - 80005a7c: 0000 unimp - 80005a7e: 0000 unimp - 80005a80: 0000 unimp - 80005a82: 0000 unimp - 80005a84: 0000 unimp - 80005a86: 0000 unimp - 80005a88: 0000 unimp - 80005a8a: 0000 unimp - 80005a8c: 0000 unimp - 80005a8e: 0000 unimp - 80005a90: 0000 unimp - 80005a92: 0000 unimp - 80005a94: 0000 unimp - 80005a96: 0000 unimp - 80005a98: 0000 unimp - 80005a9a: 0000 unimp - 80005a9c: 0000 unimp - 80005a9e: 0000 unimp - 80005aa0: 0000 unimp - 80005aa2: 0000 unimp - 80005aa4: 0000 unimp - 80005aa6: 0000 unimp - 80005aa8: 0000 unimp - 80005aaa: 0000 unimp - 80005aac: 0000 unimp - 80005aae: 0000 unimp - 80005ab0: 0000 unimp - 80005ab2: 0000 unimp - 80005ab4: 0000 unimp - 80005ab6: 0000 unimp - 80005ab8: 0000 unimp - 80005aba: 0000 unimp - 80005abc: 0000 unimp - 80005abe: 0000 unimp - 80005ac0: 0000 unimp - 80005ac2: 0000 unimp - 80005ac4: 0000 unimp - 80005ac6: 0000 unimp - 80005ac8: 0000 unimp - 80005aca: 0000 unimp - 80005acc: 0000 unimp - 80005ace: 0000 unimp - 80005ad0: 0000 unimp - 80005ad2: 0000 unimp - 80005ad4: 0000 unimp - 80005ad6: 0000 unimp - 80005ad8: 0000 unimp - 80005ada: 0000 unimp - 80005adc: 0000 unimp - 80005ade: 0000 unimp - 80005ae0: 0000 unimp - 80005ae2: 0000 unimp - 80005ae4: 0000 unimp - 80005ae6: 0000 unimp - 80005ae8: 0000 unimp - 80005aea: 0000 unimp - 80005aec: 0000 unimp - 80005aee: 0000 unimp - 80005af0: 0000 unimp - 80005af2: 0000 unimp - 80005af4: 0000 unimp - 80005af6: 0000 unimp - 80005af8: 0000 unimp - 80005afa: 0000 unimp - 80005afc: 0000 unimp - 80005afe: 0000 unimp - 80005b00: 0000 unimp - 80005b02: 0000 unimp - 80005b04: 0000 unimp - 80005b06: 0000 unimp - 80005b08: 0000 unimp - 80005b0a: 0000 unimp - 80005b0c: 0000 unimp - 80005b0e: 0000 unimp - 80005b10: 0000 unimp - 80005b12: 0000 unimp - 80005b14: 0000 unimp - 80005b16: 0000 unimp - 80005b18: 0000 unimp - 80005b1a: 0000 unimp - 80005b1c: 0000 unimp - 80005b1e: 0000 unimp - 80005b20: 0000 unimp - 80005b22: 0000 unimp - 80005b24: 0000 unimp - 80005b26: 0000 unimp - 80005b28: 0000 unimp - 80005b2a: 0000 unimp - 80005b2c: 0000 unimp - 80005b2e: 0000 unimp - 80005b30: 0000 unimp - 80005b32: 0000 unimp - 80005b34: 0000 unimp - 80005b36: 0000 unimp - 80005b38: 0000 unimp - 80005b3a: 0000 unimp - 80005b3c: 0000 unimp - 80005b3e: 0000 unimp - 80005b40: 0000 unimp - 80005b42: 0000 unimp - 80005b44: 0000 unimp - 80005b46: 0000 unimp - 80005b48: 0000 unimp - 80005b4a: 0000 unimp - 80005b4c: 0000 unimp - 80005b4e: 0000 unimp - 80005b50: 0000 unimp - 80005b52: 0000 unimp - 80005b54: 0000 unimp - 80005b56: 0000 unimp - 80005b58: 0000 unimp - 80005b5a: 0000 unimp - 80005b5c: 0000 unimp - 80005b5e: 0000 unimp - 80005b60: 0000 unimp - 80005b62: 0000 unimp - 80005b64: 0000 unimp - 80005b66: 0000 unimp - 80005b68: 0000 unimp - 80005b6a: 0000 unimp - 80005b6c: 0000 unimp - 80005b6e: 0000 unimp - 80005b70: 0000 unimp - 80005b72: 0000 unimp - 80005b74: 0000 unimp - 80005b76: 0000 unimp - 80005b78: 0000 unimp - 80005b7a: 0000 unimp - 80005b7c: 0000 unimp - 80005b7e: 0000 unimp - 80005b80: 0000 unimp - 80005b82: 0000 unimp - 80005b84: 0000 unimp - 80005b86: 0000 unimp - 80005b88: 0000 unimp - 80005b8a: 0000 unimp - 80005b8c: 0000 unimp - 80005b8e: 0000 unimp - 80005b90: 0000 unimp - 80005b92: 0000 unimp - 80005b94: 0000 unimp - 80005b96: 0000 unimp - 80005b98: 0000 unimp - 80005b9a: 0000 unimp - 80005b9c: 0000 unimp - 80005b9e: 0000 unimp - 80005ba0: 0000 unimp - 80005ba2: 0000 unimp - 80005ba4: 0000 unimp - 80005ba6: 0000 unimp - 80005ba8: 0000 unimp - 80005baa: 0000 unimp - 80005bac: 0000 unimp - 80005bae: 0000 unimp - 80005bb0: 0000 unimp - 80005bb2: 0000 unimp - 80005bb4: 0000 unimp - 80005bb6: 0000 unimp - 80005bb8: 0000 unimp - 80005bba: 0000 unimp - 80005bbc: 0000 unimp - 80005bbe: 0000 unimp - 80005bc0: 0000 unimp - 80005bc2: 0000 unimp - 80005bc4: 0000 unimp - 80005bc6: 0000 unimp - 80005bc8: 0000 unimp - 80005bca: 0000 unimp - 80005bcc: 0000 unimp - 80005bce: 0000 unimp - 80005bd0: 0000 unimp - 80005bd2: 0000 unimp - 80005bd4: 0000 unimp - 80005bd6: 0000 unimp - 80005bd8: 0000 unimp - 80005bda: 0000 unimp - 80005bdc: 0000 unimp - 80005bde: 0000 unimp - 80005be0: 0000 unimp - 80005be2: 0000 unimp - 80005be4: 0000 unimp - 80005be6: 0000 unimp - 80005be8: 0000 unimp - 80005bea: 0000 unimp - 80005bec: 0000 unimp - 80005bee: 0000 unimp - 80005bf0: 0000 unimp - 80005bf2: 0000 unimp - 80005bf4: 0000 unimp - 80005bf6: 0000 unimp - 80005bf8: 0000 unimp - 80005bfa: 0000 unimp - 80005bfc: 0000 unimp - 80005bfe: 0000 unimp - 80005c00: 0000 unimp - 80005c02: 0000 unimp - 80005c04: 0000 unimp - 80005c06: 0000 unimp - 80005c08: 0000 unimp - 80005c0a: 0000 unimp - 80005c0c: 0000 unimp - 80005c0e: 0000 unimp - 80005c10: 0000 unimp - 80005c12: 0000 unimp - 80005c14: 0000 unimp - 80005c16: 0000 unimp - 80005c18: 0000 unimp - 80005c1a: 0000 unimp - 80005c1c: 0000 unimp - 80005c1e: 0000 unimp - 80005c20: 0000 unimp - 80005c22: 0000 unimp - 80005c24: 0000 unimp - 80005c26: 0000 unimp - 80005c28: 0000 unimp - 80005c2a: 0000 unimp - 80005c2c: 0000 unimp - 80005c2e: 0000 unimp - 80005c30: 0000 unimp - 80005c32: 0000 unimp - 80005c34: 0000 unimp - 80005c36: 0000 unimp - 80005c38: 0000 unimp - 80005c3a: 0000 unimp - 80005c3c: 0000 unimp - 80005c3e: 0000 unimp - 80005c40: 0000 unimp - 80005c42: 0000 unimp - 80005c44: 0000 unimp - 80005c46: 0000 unimp - 80005c48: 0000 unimp - 80005c4a: 0000 unimp - 80005c4c: 0000 unimp - 80005c4e: 0000 unimp - 80005c50: 0000 unimp - 80005c52: 0000 unimp - 80005c54: 0000 unimp - 80005c56: 0000 unimp - 80005c58: 0000 unimp - 80005c5a: 0000 unimp - 80005c5c: 0000 unimp - 80005c5e: 0000 unimp - 80005c60: 0000 unimp - 80005c62: 0000 unimp - 80005c64: 0000 unimp - 80005c66: 0000 unimp - 80005c68: 0000 unimp - 80005c6a: 0000 unimp - 80005c6c: 0000 unimp - 80005c6e: 0000 unimp - 80005c70: 0000 unimp - 80005c72: 0000 unimp - 80005c74: 0000 unimp - 80005c76: 0000 unimp - 80005c78: 0000 unimp - 80005c7a: 0000 unimp - 80005c7c: 0000 unimp - 80005c7e: 0000 unimp - 80005c80: 0000 unimp - 80005c82: 0000 unimp - 80005c84: 0000 unimp - 80005c86: 0000 unimp - 80005c88: 0000 unimp - 80005c8a: 0000 unimp - 80005c8c: 0000 unimp - 80005c8e: 0000 unimp - 80005c90: 0000 unimp - 80005c92: 0000 unimp - 80005c94: 0000 unimp - 80005c96: 0000 unimp - 80005c98: 0000 unimp - 80005c9a: 0000 unimp - 80005c9c: 0000 unimp - 80005c9e: 0000 unimp - 80005ca0: 0000 unimp - 80005ca2: 0000 unimp - 80005ca4: 0000 unimp - 80005ca6: 0000 unimp - 80005ca8: 0000 unimp - 80005caa: 0000 unimp - 80005cac: 0000 unimp - 80005cae: 0000 unimp - 80005cb0: 0000 unimp - 80005cb2: 0000 unimp - 80005cb4: 0000 unimp - 80005cb6: 0000 unimp - 80005cb8: 0000 unimp - 80005cba: 0000 unimp - 80005cbc: 0000 unimp - 80005cbe: 0000 unimp - 80005cc0: 0000 unimp - 80005cc2: 0000 unimp - 80005cc4: 0000 unimp - 80005cc6: 0000 unimp - 80005cc8: 0000 unimp - 80005cca: 0000 unimp - 80005ccc: 0000 unimp - 80005cce: 0000 unimp - 80005cd0: 0000 unimp - 80005cd2: 0000 unimp - 80005cd4: 0000 unimp - 80005cd6: 0000 unimp - 80005cd8: 0000 unimp - 80005cda: 0000 unimp - 80005cdc: 0000 unimp - 80005cde: 0000 unimp - 80005ce0: 0000 unimp - 80005ce2: 0000 unimp - 80005ce4: 0000 unimp - 80005ce6: 0000 unimp - 80005ce8: 0000 unimp - 80005cea: 0000 unimp - 80005cec: 0000 unimp - 80005cee: 0000 unimp - 80005cf0: 0000 unimp - 80005cf2: 0000 unimp - 80005cf4: 0000 unimp - 80005cf6: 0000 unimp - 80005cf8: 0000 unimp - 80005cfa: 0000 unimp - 80005cfc: 0000 unimp - 80005cfe: 0000 unimp - 80005d00: 0000 unimp - 80005d02: 0000 unimp - 80005d04: 0000 unimp - 80005d06: 0000 unimp - 80005d08: 0000 unimp - 80005d0a: 0000 unimp - 80005d0c: 0000 unimp - 80005d0e: 0000 unimp - 80005d10: 0000 unimp - 80005d12: 0000 unimp - 80005d14: 0000 unimp - 80005d16: 0000 unimp - 80005d18: 0000 unimp - 80005d1a: 0000 unimp - 80005d1c: 0000 unimp - 80005d1e: 0000 unimp - 80005d20: 0000 unimp - 80005d22: 0000 unimp - 80005d24: 0000 unimp - 80005d26: 0000 unimp - 80005d28: 0000 unimp - 80005d2a: 0000 unimp - 80005d2c: 0000 unimp - 80005d2e: 0000 unimp - 80005d30: 0000 unimp - 80005d32: 0000 unimp - 80005d34: 0000 unimp - 80005d36: 0000 unimp - 80005d38: 0000 unimp - 80005d3a: 0000 unimp - 80005d3c: 0000 unimp - 80005d3e: 0000 unimp - 80005d40: 0000 unimp - 80005d42: 0000 unimp - 80005d44: 0000 unimp - 80005d46: 0000 unimp - 80005d48: 0000 unimp - 80005d4a: 0000 unimp - 80005d4c: 0000 unimp - 80005d4e: 0000 unimp - 80005d50: 0000 unimp - 80005d52: 0000 unimp - 80005d54: 0000 unimp - 80005d56: 0000 unimp - 80005d58: 0000 unimp - 80005d5a: 0000 unimp - 80005d5c: 0000 unimp - 80005d5e: 0000 unimp - 80005d60: 0000 unimp - 80005d62: 0000 unimp - 80005d64: 0000 unimp - 80005d66: 0000 unimp - 80005d68: 0000 unimp - 80005d6a: 0000 unimp - 80005d6c: 0000 unimp - 80005d6e: 0000 unimp - 80005d70: 0000 unimp - 80005d72: 0000 unimp - 80005d74: 0000 unimp - 80005d76: 0000 unimp - 80005d78: 0000 unimp - 80005d7a: 0000 unimp - 80005d7c: 0000 unimp - 80005d7e: 0000 unimp - 80005d80: 0000 unimp - 80005d82: 0000 unimp - 80005d84: 0000 unimp - 80005d86: 0000 unimp - 80005d88: 0000 unimp - 80005d8a: 0000 unimp - 80005d8c: 0000 unimp - 80005d8e: 0000 unimp - 80005d90: 0000 unimp - 80005d92: 0000 unimp - 80005d94: 0000 unimp - 80005d96: 0000 unimp - 80005d98: 0000 unimp - 80005d9a: 0000 unimp - 80005d9c: 0000 unimp - 80005d9e: 0000 unimp - 80005da0: 0000 unimp - 80005da2: 0000 unimp - 80005da4: 0000 unimp - 80005da6: 0000 unimp - 80005da8: 0000 unimp - 80005daa: 0000 unimp - 80005dac: 0000 unimp - 80005dae: 0000 unimp - 80005db0: 0000 unimp - 80005db2: 0000 unimp - 80005db4: 0000 unimp - 80005db6: 0000 unimp - 80005db8: 0000 unimp - 80005dba: 0000 unimp - 80005dbc: 0000 unimp - 80005dbe: 0000 unimp - 80005dc0: 0000 unimp - 80005dc2: 0000 unimp - 80005dc4: 0000 unimp - 80005dc6: 0000 unimp - 80005dc8: 0000 unimp - 80005dca: 0000 unimp - 80005dcc: 0000 unimp - 80005dce: 0000 unimp - 80005dd0: 0000 unimp - 80005dd2: 0000 unimp - 80005dd4: 0000 unimp - 80005dd6: 0000 unimp - 80005dd8: 0000 unimp - 80005dda: 0000 unimp - 80005ddc: 0000 unimp - 80005dde: 0000 unimp - 80005de0: 0000 unimp - 80005de2: 0000 unimp - 80005de4: 0000 unimp - 80005de6: 0000 unimp - 80005de8: 0000 unimp - 80005dea: 0000 unimp - 80005dec: 0000 unimp - 80005dee: 0000 unimp - 80005df0: 0000 unimp - 80005df2: 0000 unimp - 80005df4: 0000 unimp - 80005df6: 0000 unimp - 80005df8: 0000 unimp - 80005dfa: 0000 unimp - 80005dfc: 0000 unimp - 80005dfe: 0000 unimp - 80005e00: 0000 unimp - 80005e02: 0000 unimp - 80005e04: 0000 unimp - 80005e06: 0000 unimp - 80005e08: 0000 unimp - 80005e0a: 0000 unimp - 80005e0c: 0000 unimp - 80005e0e: 0000 unimp - 80005e10: 0000 unimp - 80005e12: 0000 unimp - 80005e14: 0000 unimp - 80005e16: 0000 unimp - 80005e18: 0000 unimp - 80005e1a: 0000 unimp - 80005e1c: 0000 unimp - 80005e1e: 0000 unimp - 80005e20: 0000 unimp - 80005e22: 0000 unimp - 80005e24: 0000 unimp - 80005e26: 0000 unimp - 80005e28: 0000 unimp - 80005e2a: 0000 unimp - 80005e2c: 0000 unimp - 80005e2e: 0000 unimp - 80005e30: 0000 unimp - 80005e32: 0000 unimp - 80005e34: 0000 unimp - 80005e36: 0000 unimp - 80005e38: 0000 unimp - 80005e3a: 0000 unimp - 80005e3c: 0000 unimp - 80005e3e: 0000 unimp - 80005e40: 0000 unimp - 80005e42: 0000 unimp - 80005e44: 0000 unimp - 80005e46: 0000 unimp - 80005e48: 0000 unimp - 80005e4a: 0000 unimp - 80005e4c: 0000 unimp - 80005e4e: 0000 unimp - 80005e50: 0000 unimp - 80005e52: 0000 unimp - 80005e54: 0000 unimp - 80005e56: 0000 unimp - 80005e58: 0000 unimp - 80005e5a: 0000 unimp - 80005e5c: 0000 unimp - 80005e5e: 0000 unimp - 80005e60: 0000 unimp - 80005e62: 0000 unimp - 80005e64: 0000 unimp - 80005e66: 0000 unimp - 80005e68: 0000 unimp - 80005e6a: 0000 unimp - 80005e6c: 0000 unimp - 80005e6e: 0000 unimp - 80005e70: 0000 unimp - 80005e72: 0000 unimp - 80005e74: 0000 unimp - 80005e76: 0000 unimp - 80005e78: 0000 unimp - 80005e7a: 0000 unimp - 80005e7c: 0000 unimp - 80005e7e: 0000 unimp - 80005e80: 0000 unimp - 80005e82: 0000 unimp - 80005e84: 0000 unimp - 80005e86: 0000 unimp - 80005e88: 0000 unimp - 80005e8a: 0000 unimp - 80005e8c: 0000 unimp - 80005e8e: 0000 unimp - 80005e90: 0000 unimp - 80005e92: 0000 unimp - 80005e94: 0000 unimp - 80005e96: 0000 unimp - 80005e98: 0000 unimp - 80005e9a: 0000 unimp - 80005e9c: 0000 unimp - 80005e9e: 0000 unimp - 80005ea0: 0000 unimp - 80005ea2: 0000 unimp - 80005ea4: 0000 unimp - 80005ea6: 0000 unimp - 80005ea8: 0000 unimp - 80005eaa: 0000 unimp - 80005eac: 0000 unimp - 80005eae: 0000 unimp - 80005eb0: 0000 unimp - 80005eb2: 0000 unimp - 80005eb4: 0000 unimp - 80005eb6: 0000 unimp - 80005eb8: 0000 unimp - 80005eba: 0000 unimp - 80005ebc: 0000 unimp - 80005ebe: 0000 unimp - 80005ec0: 0000 unimp - 80005ec2: 0000 unimp - 80005ec4: 0000 unimp - 80005ec6: 0000 unimp - 80005ec8: 0000 unimp - 80005eca: 0000 unimp - 80005ecc: 0000 unimp - 80005ece: 0000 unimp - 80005ed0: 0000 unimp - 80005ed2: 0000 unimp - 80005ed4: 0000 unimp - 80005ed6: 0000 unimp - 80005ed8: 0000 unimp - 80005eda: 0000 unimp - 80005edc: 0000 unimp - 80005ede: 0000 unimp - 80005ee0: 0000 unimp - 80005ee2: 0000 unimp - 80005ee4: 0000 unimp - 80005ee6: 0000 unimp - 80005ee8: 0000 unimp - 80005eea: 0000 unimp - 80005eec: 0000 unimp - 80005eee: 0000 unimp - 80005ef0: 0000 unimp - 80005ef2: 0000 unimp - 80005ef4: 0000 unimp - 80005ef6: 0000 unimp - 80005ef8: 0000 unimp - 80005efa: 0000 unimp - 80005efc: 0000 unimp - 80005efe: 0000 unimp - 80005f00: 0000 unimp - 80005f02: 0000 unimp - 80005f04: 0000 unimp - 80005f06: 0000 unimp - 80005f08: 0000 unimp - 80005f0a: 0000 unimp - 80005f0c: 0000 unimp - 80005f0e: 0000 unimp - 80005f10: 0000 unimp - 80005f12: 0000 unimp - 80005f14: 0000 unimp - 80005f16: 0000 unimp - 80005f18: 0000 unimp - 80005f1a: 0000 unimp - 80005f1c: 0000 unimp - 80005f1e: 0000 unimp - 80005f20: 0000 unimp - 80005f22: 0000 unimp - 80005f24: 0000 unimp - 80005f26: 0000 unimp - 80005f28: 0000 unimp - 80005f2a: 0000 unimp - 80005f2c: 0000 unimp - 80005f2e: 0000 unimp - 80005f30: 0000 unimp - 80005f32: 0000 unimp - 80005f34: 0000 unimp - 80005f36: 0000 unimp - 80005f38: 0000 unimp - 80005f3a: 0000 unimp - 80005f3c: 0000 unimp - 80005f3e: 0000 unimp - 80005f40: 0000 unimp - 80005f42: 0000 unimp - 80005f44: 0000 unimp - 80005f46: 0000 unimp - 80005f48: 0000 unimp - 80005f4a: 0000 unimp - 80005f4c: 0000 unimp - 80005f4e: 0000 unimp - 80005f50: 0000 unimp - 80005f52: 0000 unimp - 80005f54: 0000 unimp - 80005f56: 0000 unimp - 80005f58: 0000 unimp - 80005f5a: 0000 unimp - 80005f5c: 0000 unimp - 80005f5e: 0000 unimp - 80005f60: 0000 unimp - 80005f62: 0000 unimp - 80005f64: 0000 unimp - 80005f66: 0000 unimp - 80005f68: 0000 unimp - 80005f6a: 0000 unimp - 80005f6c: 0000 unimp - 80005f6e: 0000 unimp - 80005f70: 0000 unimp - 80005f72: 0000 unimp - 80005f74: 0000 unimp - 80005f76: 0000 unimp - 80005f78: 0000 unimp - 80005f7a: 0000 unimp - 80005f7c: 0000 unimp - 80005f7e: 0000 unimp - 80005f80: 0000 unimp - 80005f82: 0000 unimp - 80005f84: 0000 unimp - 80005f86: 0000 unimp - 80005f88: 0000 unimp - 80005f8a: 0000 unimp - 80005f8c: 0000 unimp - 80005f8e: 0000 unimp - 80005f90: 0000 unimp - 80005f92: 0000 unimp - 80005f94: 0000 unimp - 80005f96: 0000 unimp - 80005f98: 0000 unimp - 80005f9a: 0000 unimp - 80005f9c: 0000 unimp - 80005f9e: 0000 unimp - 80005fa0: 0000 unimp - 80005fa2: 0000 unimp - 80005fa4: 0000 unimp - 80005fa6: 0000 unimp - 80005fa8: 0000 unimp - 80005faa: 0000 unimp - 80005fac: 0000 unimp - 80005fae: 0000 unimp - 80005fb0: 0000 unimp - 80005fb2: 0000 unimp - 80005fb4: 0000 unimp - 80005fb6: 0000 unimp - 80005fb8: 0000 unimp - 80005fba: 0000 unimp - 80005fbc: 0000 unimp - 80005fbe: 0000 unimp - 80005fc0: 0000 unimp - 80005fc2: 0000 unimp - 80005fc4: 0000 unimp - 80005fc6: 0000 unimp diff --git a/test/riscv/tests/rv64uc-v-rvc.elf b/test/riscv/tests/rv64uc-v-rvc.elf deleted file mode 100644 index 89152b9c..00000000 Binary files a/test/riscv/tests/rv64uc-v-rvc.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-add.dump b/test/riscv/tests/rv64ui-p-add.dump deleted file mode 100644 index 83e5cedc..00000000 --- a/test/riscv/tests/rv64ui-p-add.dump +++ /dev/null @@ -1,506 +0,0 @@ - -rv64ui-p-add: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00000093 li ra,0 - 80000100: 00000113 li sp,0 - 80000104: 00208f33 add t5,ra,sp - 80000108: 00000e93 li t4,0 - 8000010c: 00200193 li gp,2 - 80000110: 4fdf1063 bne t5,t4,800005f0 - -0000000080000114 : - 80000114: 00100093 li ra,1 - 80000118: 00100113 li sp,1 - 8000011c: 00208f33 add t5,ra,sp - 80000120: 00200e93 li t4,2 - 80000124: 00300193 li gp,3 - 80000128: 4ddf1463 bne t5,t4,800005f0 - -000000008000012c : - 8000012c: 00300093 li ra,3 - 80000130: 00700113 li sp,7 - 80000134: 00208f33 add t5,ra,sp - 80000138: 00a00e93 li t4,10 - 8000013c: 00400193 li gp,4 - 80000140: 4bdf1863 bne t5,t4,800005f0 - -0000000080000144 : - 80000144: 00000093 li ra,0 - 80000148: ffff8137 lui sp,0xffff8 - 8000014c: 00208f33 add t5,ra,sp - 80000150: ffff8eb7 lui t4,0xffff8 - 80000154: 00500193 li gp,5 - 80000158: 49df1c63 bne t5,t4,800005f0 - -000000008000015c : - 8000015c: 800000b7 lui ra,0x80000 - 80000160: 00000113 li sp,0 - 80000164: 00208f33 add t5,ra,sp - 80000168: 80000eb7 lui t4,0x80000 - 8000016c: 00600193 li gp,6 - 80000170: 49df1063 bne t5,t4,800005f0 - -0000000080000174 : - 80000174: 800000b7 lui ra,0x80000 - 80000178: ffff8137 lui sp,0xffff8 - 8000017c: 00208f33 add t5,ra,sp - 80000180: ffff0eb7 lui t4,0xffff0 - 80000184: fffe8e9b addiw t4,t4,-1 - 80000188: 00fe9e93 slli t4,t4,0xf - 8000018c: 00700193 li gp,7 - 80000190: 47df1063 bne t5,t4,800005f0 - -0000000080000194 : - 80000194: 00000093 li ra,0 - 80000198: 00008137 lui sp,0x8 - 8000019c: fff1011b addiw sp,sp,-1 - 800001a0: 00208f33 add t5,ra,sp - 800001a4: 00008eb7 lui t4,0x8 - 800001a8: fffe8e9b addiw t4,t4,-1 - 800001ac: 00800193 li gp,8 - 800001b0: 45df1063 bne t5,t4,800005f0 - -00000000800001b4 : - 800001b4: 800000b7 lui ra,0x80000 - 800001b8: fff0809b addiw ra,ra,-1 - 800001bc: 00000113 li sp,0 - 800001c0: 00208f33 add t5,ra,sp - 800001c4: 80000eb7 lui t4,0x80000 - 800001c8: fffe8e9b addiw t4,t4,-1 - 800001cc: 00900193 li gp,9 - 800001d0: 43df1063 bne t5,t4,800005f0 - -00000000800001d4 : - 800001d4: 800000b7 lui ra,0x80000 - 800001d8: fff0809b addiw ra,ra,-1 - 800001dc: 00008137 lui sp,0x8 - 800001e0: fff1011b addiw sp,sp,-1 - 800001e4: 00208f33 add t5,ra,sp - 800001e8: 00010eb7 lui t4,0x10 - 800001ec: 001e8e9b addiw t4,t4,1 - 800001f0: 00fe9e93 slli t4,t4,0xf - 800001f4: ffee8e93 addi t4,t4,-2 # fffe <_start-0x7fff0002> - 800001f8: 00a00193 li gp,10 - 800001fc: 3fdf1a63 bne t5,t4,800005f0 - -0000000080000200 : - 80000200: 800000b7 lui ra,0x80000 - 80000204: 00008137 lui sp,0x8 - 80000208: fff1011b addiw sp,sp,-1 - 8000020c: 00208f33 add t5,ra,sp - 80000210: 80008eb7 lui t4,0x80008 - 80000214: fffe8e9b addiw t4,t4,-1 - 80000218: 00b00193 li gp,11 - 8000021c: 3ddf1a63 bne t5,t4,800005f0 - -0000000080000220 : - 80000220: 800000b7 lui ra,0x80000 - 80000224: fff0809b addiw ra,ra,-1 - 80000228: ffff8137 lui sp,0xffff8 - 8000022c: 00208f33 add t5,ra,sp - 80000230: 7fff8eb7 lui t4,0x7fff8 - 80000234: fffe8e9b addiw t4,t4,-1 - 80000238: 00c00193 li gp,12 - 8000023c: 3bdf1a63 bne t5,t4,800005f0 - -0000000080000240 : - 80000240: 00000093 li ra,0 - 80000244: fff00113 li sp,-1 - 80000248: 00208f33 add t5,ra,sp - 8000024c: fff00e93 li t4,-1 - 80000250: 00d00193 li gp,13 - 80000254: 39df1e63 bne t5,t4,800005f0 - -0000000080000258 : - 80000258: fff00093 li ra,-1 - 8000025c: 00100113 li sp,1 - 80000260: 00208f33 add t5,ra,sp - 80000264: 00000e93 li t4,0 - 80000268: 00e00193 li gp,14 - 8000026c: 39df1263 bne t5,t4,800005f0 - -0000000080000270 : - 80000270: fff00093 li ra,-1 - 80000274: fff00113 li sp,-1 - 80000278: 00208f33 add t5,ra,sp - 8000027c: ffe00e93 li t4,-2 - 80000280: 00f00193 li gp,15 - 80000284: 37df1663 bne t5,t4,800005f0 - -0000000080000288 : - 80000288: 00100093 li ra,1 - 8000028c: 80000137 lui sp,0x80000 - 80000290: fff1011b addiw sp,sp,-1 - 80000294: 00208f33 add t5,ra,sp - 80000298: 00100e9b addiw t4,zero,1 - 8000029c: 01fe9e93 slli t4,t4,0x1f - 800002a0: 01000193 li gp,16 - 800002a4: 35df1663 bne t5,t4,800005f0 - -00000000800002a8 : - 800002a8: 00d00093 li ra,13 - 800002ac: 00b00113 li sp,11 - 800002b0: 002080b3 add ra,ra,sp - 800002b4: 01800e93 li t4,24 - 800002b8: 01100193 li gp,17 - 800002bc: 33d09a63 bne ra,t4,800005f0 - -00000000800002c0 : - 800002c0: 00e00093 li ra,14 - 800002c4: 00b00113 li sp,11 - 800002c8: 00208133 add sp,ra,sp - 800002cc: 01900e93 li t4,25 - 800002d0: 01200193 li gp,18 - 800002d4: 31d11e63 bne sp,t4,800005f0 - -00000000800002d8 : - 800002d8: 00d00093 li ra,13 - 800002dc: 001080b3 add ra,ra,ra - 800002e0: 01a00e93 li t4,26 - 800002e4: 01300193 li gp,19 - 800002e8: 31d09463 bne ra,t4,800005f0 - -00000000800002ec : - 800002ec: 00000213 li tp,0 - 800002f0: 00d00093 li ra,13 - 800002f4: 00b00113 li sp,11 - 800002f8: 00208f33 add t5,ra,sp - 800002fc: 000f0313 mv t1,t5 - 80000300: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000304: 00200293 li t0,2 - 80000308: fe5214e3 bne tp,t0,800002f0 - 8000030c: 01800e93 li t4,24 - 80000310: 01400193 li gp,20 - 80000314: 2dd31e63 bne t1,t4,800005f0 - -0000000080000318 : - 80000318: 00000213 li tp,0 - 8000031c: 00e00093 li ra,14 - 80000320: 00b00113 li sp,11 - 80000324: 00208f33 add t5,ra,sp - 80000328: 00000013 nop - 8000032c: 000f0313 mv t1,t5 - 80000330: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000334: 00200293 li t0,2 - 80000338: fe5212e3 bne tp,t0,8000031c - 8000033c: 01900e93 li t4,25 - 80000340: 01500193 li gp,21 - 80000344: 2bd31663 bne t1,t4,800005f0 - -0000000080000348 : - 80000348: 00000213 li tp,0 - 8000034c: 00f00093 li ra,15 - 80000350: 00b00113 li sp,11 - 80000354: 00208f33 add t5,ra,sp - 80000358: 00000013 nop - 8000035c: 00000013 nop - 80000360: 000f0313 mv t1,t5 - 80000364: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000368: 00200293 li t0,2 - 8000036c: fe5210e3 bne tp,t0,8000034c - 80000370: 01a00e93 li t4,26 - 80000374: 01600193 li gp,22 - 80000378: 27d31c63 bne t1,t4,800005f0 - -000000008000037c : - 8000037c: 00000213 li tp,0 - 80000380: 00d00093 li ra,13 - 80000384: 00b00113 li sp,11 - 80000388: 00208f33 add t5,ra,sp - 8000038c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000390: 00200293 li t0,2 - 80000394: fe5216e3 bne tp,t0,80000380 - 80000398: 01800e93 li t4,24 - 8000039c: 01700193 li gp,23 - 800003a0: 25df1863 bne t5,t4,800005f0 - -00000000800003a4 : - 800003a4: 00000213 li tp,0 - 800003a8: 00e00093 li ra,14 - 800003ac: 00b00113 li sp,11 - 800003b0: 00000013 nop - 800003b4: 00208f33 add t5,ra,sp - 800003b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003bc: 00200293 li t0,2 - 800003c0: fe5214e3 bne tp,t0,800003a8 - 800003c4: 01900e93 li t4,25 - 800003c8: 01800193 li gp,24 - 800003cc: 23df1263 bne t5,t4,800005f0 - -00000000800003d0 : - 800003d0: 00000213 li tp,0 - 800003d4: 00f00093 li ra,15 - 800003d8: 00b00113 li sp,11 - 800003dc: 00000013 nop - 800003e0: 00000013 nop - 800003e4: 00208f33 add t5,ra,sp - 800003e8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003ec: 00200293 li t0,2 - 800003f0: fe5212e3 bne tp,t0,800003d4 - 800003f4: 01a00e93 li t4,26 - 800003f8: 01900193 li gp,25 - 800003fc: 1fdf1a63 bne t5,t4,800005f0 - -0000000080000400 : - 80000400: 00000213 li tp,0 - 80000404: 00d00093 li ra,13 - 80000408: 00000013 nop - 8000040c: 00b00113 li sp,11 - 80000410: 00208f33 add t5,ra,sp - 80000414: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000418: 00200293 li t0,2 - 8000041c: fe5214e3 bne tp,t0,80000404 - 80000420: 01800e93 li t4,24 - 80000424: 01a00193 li gp,26 - 80000428: 1ddf1463 bne t5,t4,800005f0 - -000000008000042c : - 8000042c: 00000213 li tp,0 - 80000430: 00e00093 li ra,14 - 80000434: 00000013 nop - 80000438: 00b00113 li sp,11 - 8000043c: 00000013 nop - 80000440: 00208f33 add t5,ra,sp - 80000444: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000448: 00200293 li t0,2 - 8000044c: fe5212e3 bne tp,t0,80000430 - 80000450: 01900e93 li t4,25 - 80000454: 01b00193 li gp,27 - 80000458: 19df1c63 bne t5,t4,800005f0 - -000000008000045c : - 8000045c: 00000213 li tp,0 - 80000460: 00f00093 li ra,15 - 80000464: 00000013 nop - 80000468: 00000013 nop - 8000046c: 00b00113 li sp,11 - 80000470: 00208f33 add t5,ra,sp - 80000474: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000478: 00200293 li t0,2 - 8000047c: fe5212e3 bne tp,t0,80000460 - 80000480: 01a00e93 li t4,26 - 80000484: 01c00193 li gp,28 - 80000488: 17df1463 bne t5,t4,800005f0 - -000000008000048c : - 8000048c: 00000213 li tp,0 - 80000490: 00b00113 li sp,11 - 80000494: 00d00093 li ra,13 - 80000498: 00208f33 add t5,ra,sp - 8000049c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004a0: 00200293 li t0,2 - 800004a4: fe5216e3 bne tp,t0,80000490 - 800004a8: 01800e93 li t4,24 - 800004ac: 01d00193 li gp,29 - 800004b0: 15df1063 bne t5,t4,800005f0 - -00000000800004b4 : - 800004b4: 00000213 li tp,0 - 800004b8: 00b00113 li sp,11 - 800004bc: 00e00093 li ra,14 - 800004c0: 00000013 nop - 800004c4: 00208f33 add t5,ra,sp - 800004c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004cc: 00200293 li t0,2 - 800004d0: fe5214e3 bne tp,t0,800004b8 - 800004d4: 01900e93 li t4,25 - 800004d8: 01e00193 li gp,30 - 800004dc: 11df1a63 bne t5,t4,800005f0 - -00000000800004e0 : - 800004e0: 00000213 li tp,0 - 800004e4: 00b00113 li sp,11 - 800004e8: 00f00093 li ra,15 - 800004ec: 00000013 nop - 800004f0: 00000013 nop - 800004f4: 00208f33 add t5,ra,sp - 800004f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004fc: 00200293 li t0,2 - 80000500: fe5212e3 bne tp,t0,800004e4 - 80000504: 01a00e93 li t4,26 - 80000508: 01f00193 li gp,31 - 8000050c: 0fdf1263 bne t5,t4,800005f0 - -0000000080000510 : - 80000510: 00000213 li tp,0 - 80000514: 00b00113 li sp,11 - 80000518: 00000013 nop - 8000051c: 00d00093 li ra,13 - 80000520: 00208f33 add t5,ra,sp - 80000524: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000528: 00200293 li t0,2 - 8000052c: fe5214e3 bne tp,t0,80000514 - 80000530: 01800e93 li t4,24 - 80000534: 02000193 li gp,32 - 80000538: 0bdf1c63 bne t5,t4,800005f0 - -000000008000053c : - 8000053c: 00000213 li tp,0 - 80000540: 00b00113 li sp,11 - 80000544: 00000013 nop - 80000548: 00e00093 li ra,14 - 8000054c: 00000013 nop - 80000550: 00208f33 add t5,ra,sp - 80000554: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000558: 00200293 li t0,2 - 8000055c: fe5212e3 bne tp,t0,80000540 - 80000560: 01900e93 li t4,25 - 80000564: 02100193 li gp,33 - 80000568: 09df1463 bne t5,t4,800005f0 - -000000008000056c : - 8000056c: 00000213 li tp,0 - 80000570: 00b00113 li sp,11 - 80000574: 00000013 nop - 80000578: 00000013 nop - 8000057c: 00f00093 li ra,15 - 80000580: 00208f33 add t5,ra,sp - 80000584: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000588: 00200293 li t0,2 - 8000058c: fe5212e3 bne tp,t0,80000570 - 80000590: 01a00e93 li t4,26 - 80000594: 02200193 li gp,34 - 80000598: 05df1c63 bne t5,t4,800005f0 - -000000008000059c : - 8000059c: 00f00093 li ra,15 - 800005a0: 00100133 add sp,zero,ra - 800005a4: 00f00e93 li t4,15 - 800005a8: 02300193 li gp,35 - 800005ac: 05d11263 bne sp,t4,800005f0 - -00000000800005b0 : - 800005b0: 02000093 li ra,32 - 800005b4: 00008133 add sp,ra,zero - 800005b8: 02000e93 li t4,32 - 800005bc: 02400193 li gp,36 - 800005c0: 03d11863 bne sp,t4,800005f0 - -00000000800005c4 : - 800005c4: 000000b3 add ra,zero,zero - 800005c8: 00000e93 li t4,0 - 800005cc: 02500193 li gp,37 - 800005d0: 03d09063 bne ra,t4,800005f0 - -00000000800005d4 : - 800005d4: 01000093 li ra,16 - 800005d8: 01e00113 li sp,30 - 800005dc: 00208033 add zero,ra,sp - 800005e0: 00000e93 li t4,0 - 800005e4: 02600193 li gp,38 - 800005e8: 01d01463 bne zero,t4,800005f0 - 800005ec: 00301c63 bne zero,gp,80000604 - -00000000800005f0 : - 800005f0: 0ff0000f fence - 800005f4: 00018063 beqz gp,800005f4 - 800005f8: 00119193 slli gp,gp,0x1 - 800005fc: 0011e193 ori gp,gp,1 - 80000600: 00000073 ecall - -0000000080000604 : - 80000604: 0ff0000f fence - 80000608: 00100193 li gp,1 - 8000060c: 00000073 ecall - 80000610: c0001073 unimp - 80000614: 0000 unimp - 80000616: 0000 unimp - 80000618: 0000 unimp - 8000061a: 0000 unimp - 8000061c: 0000 unimp - 8000061e: 0000 unimp - 80000620: 0000 unimp - 80000622: 0000 unimp - 80000624: 0000 unimp - 80000626: 0000 unimp - 80000628: 0000 unimp - 8000062a: 0000 unimp - 8000062c: 0000 unimp - 8000062e: 0000 unimp - 80000630: 0000 unimp - 80000632: 0000 unimp - 80000634: 0000 unimp - 80000636: 0000 unimp - 80000638: 0000 unimp - 8000063a: 0000 unimp - 8000063c: 0000 unimp - 8000063e: 0000 unimp - 80000640: 0000 unimp - 80000642: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-add.elf b/test/riscv/tests/rv64ui-p-add.elf deleted file mode 100644 index 711d4fc8..00000000 Binary files a/test/riscv/tests/rv64ui-p-add.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-addi.dump b/test/riscv/tests/rv64ui-p-addi.dump deleted file mode 100644 index dc5acc09..00000000 --- a/test/riscv/tests/rv64ui-p-addi.dump +++ /dev/null @@ -1,312 +0,0 @@ - -rv64ui-p-addi: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00000093 li ra,0 - 80000100: 00008f13 mv t5,ra - 80000104: 00000e93 li t4,0 - 80000108: 00200193 li gp,2 - 8000010c: 29df1263 bne t5,t4,80000390 - -0000000080000110 : - 80000110: 00100093 li ra,1 - 80000114: 00108f13 addi t5,ra,1 - 80000118: 00200e93 li t4,2 - 8000011c: 00300193 li gp,3 - 80000120: 27df1863 bne t5,t4,80000390 - -0000000080000124 : - 80000124: 00300093 li ra,3 - 80000128: 00708f13 addi t5,ra,7 - 8000012c: 00a00e93 li t4,10 - 80000130: 00400193 li gp,4 - 80000134: 25df1e63 bne t5,t4,80000390 - -0000000080000138 : - 80000138: 00000093 li ra,0 - 8000013c: 80008f13 addi t5,ra,-2048 - 80000140: 80000e93 li t4,-2048 - 80000144: 00500193 li gp,5 - 80000148: 25df1463 bne t5,t4,80000390 - -000000008000014c : - 8000014c: 800000b7 lui ra,0x80000 - 80000150: 00008f13 mv t5,ra - 80000154: 80000eb7 lui t4,0x80000 - 80000158: 00600193 li gp,6 - 8000015c: 23df1a63 bne t5,t4,80000390 - -0000000080000160 : - 80000160: 800000b7 lui ra,0x80000 - 80000164: 80008f13 addi t5,ra,-2048 # ffffffff7ffff800 <_end+0xfffffffeffffd800> - 80000168: fff00e9b addiw t4,zero,-1 - 8000016c: 01fe9e93 slli t4,t4,0x1f - 80000170: 800e8e93 addi t4,t4,-2048 # ffffffff7ffff800 <_end+0xfffffffeffffd800> - 80000174: 00700193 li gp,7 - 80000178: 21df1c63 bne t5,t4,80000390 - -000000008000017c : - 8000017c: 00000093 li ra,0 - 80000180: 7ff08f13 addi t5,ra,2047 - 80000184: 7ff00e93 li t4,2047 - 80000188: 00800193 li gp,8 - 8000018c: 21df1263 bne t5,t4,80000390 - -0000000080000190 : - 80000190: 800000b7 lui ra,0x80000 - 80000194: fff0809b addiw ra,ra,-1 - 80000198: 00008f13 mv t5,ra - 8000019c: 80000eb7 lui t4,0x80000 - 800001a0: fffe8e9b addiw t4,t4,-1 - 800001a4: 00900193 li gp,9 - 800001a8: 1fdf1463 bne t5,t4,80000390 - -00000000800001ac : - 800001ac: 800000b7 lui ra,0x80000 - 800001b0: fff0809b addiw ra,ra,-1 - 800001b4: 7ff08f13 addi t5,ra,2047 # ffffffff800007ff <_end+0xfffffffeffffe7ff> - 800001b8: 00100e9b addiw t4,zero,1 - 800001bc: 01fe9e93 slli t4,t4,0x1f - 800001c0: 7fee8e93 addi t4,t4,2046 # ffffffff800007fe <_end+0xfffffffeffffe7fe> - 800001c4: 00a00193 li gp,10 - 800001c8: 1ddf1463 bne t5,t4,80000390 - -00000000800001cc : - 800001cc: 800000b7 lui ra,0x80000 - 800001d0: 7ff08f13 addi t5,ra,2047 # ffffffff800007ff <_end+0xfffffffeffffe7ff> - 800001d4: 80000eb7 lui t4,0x80000 - 800001d8: 7ffe8e9b addiw t4,t4,2047 - 800001dc: 00b00193 li gp,11 - 800001e0: 1bdf1863 bne t5,t4,80000390 - -00000000800001e4 : - 800001e4: 800000b7 lui ra,0x80000 - 800001e8: fff0809b addiw ra,ra,-1 - 800001ec: 80008f13 addi t5,ra,-2048 # ffffffff7ffff800 <_end+0xfffffffeffffd800> - 800001f0: 7ffffeb7 lui t4,0x7ffff - 800001f4: 7ffe8e9b addiw t4,t4,2047 - 800001f8: 00c00193 li gp,12 - 800001fc: 19df1a63 bne t5,t4,80000390 - -0000000080000200 : - 80000200: 00000093 li ra,0 - 80000204: fff08f13 addi t5,ra,-1 - 80000208: fff00e93 li t4,-1 - 8000020c: 00d00193 li gp,13 - 80000210: 19df1063 bne t5,t4,80000390 - -0000000080000214 : - 80000214: fff00093 li ra,-1 - 80000218: 00108f13 addi t5,ra,1 - 8000021c: 00000e93 li t4,0 - 80000220: 00e00193 li gp,14 - 80000224: 17df1663 bne t5,t4,80000390 - -0000000080000228 : - 80000228: fff00093 li ra,-1 - 8000022c: fff08f13 addi t5,ra,-1 - 80000230: ffe00e93 li t4,-2 - 80000234: 00f00193 li gp,15 - 80000238: 15df1c63 bne t5,t4,80000390 - -000000008000023c : - 8000023c: 800000b7 lui ra,0x80000 - 80000240: fff0809b addiw ra,ra,-1 - 80000244: 00108f13 addi t5,ra,1 # ffffffff80000001 <_end+0xfffffffeffffe001> - 80000248: 00100e9b addiw t4,zero,1 - 8000024c: 01fe9e93 slli t4,t4,0x1f - 80000250: 01000193 li gp,16 - 80000254: 13df1e63 bne t5,t4,80000390 - -0000000080000258 : - 80000258: 00d00093 li ra,13 - 8000025c: 00b08093 addi ra,ra,11 - 80000260: 01800e93 li t4,24 - 80000264: 01100193 li gp,17 - 80000268: 13d09463 bne ra,t4,80000390 - -000000008000026c : - 8000026c: 00000213 li tp,0 - 80000270: 00d00093 li ra,13 - 80000274: 00b08f13 addi t5,ra,11 - 80000278: 000f0313 mv t1,t5 - 8000027c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000280: 00200293 li t0,2 - 80000284: fe5216e3 bne tp,t0,80000270 - 80000288: 01800e93 li t4,24 - 8000028c: 01200193 li gp,18 - 80000290: 11d31063 bne t1,t4,80000390 - -0000000080000294 : - 80000294: 00000213 li tp,0 - 80000298: 00d00093 li ra,13 - 8000029c: 00a08f13 addi t5,ra,10 - 800002a0: 00000013 nop - 800002a4: 000f0313 mv t1,t5 - 800002a8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002ac: 00200293 li t0,2 - 800002b0: fe5214e3 bne tp,t0,80000298 - 800002b4: 01700e93 li t4,23 - 800002b8: 01300193 li gp,19 - 800002bc: 0dd31a63 bne t1,t4,80000390 - -00000000800002c0 : - 800002c0: 00000213 li tp,0 - 800002c4: 00d00093 li ra,13 - 800002c8: 00908f13 addi t5,ra,9 - 800002cc: 00000013 nop - 800002d0: 00000013 nop - 800002d4: 000f0313 mv t1,t5 - 800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002dc: 00200293 li t0,2 - 800002e0: fe5212e3 bne tp,t0,800002c4 - 800002e4: 01600e93 li t4,22 - 800002e8: 01400193 li gp,20 - 800002ec: 0bd31263 bne t1,t4,80000390 - -00000000800002f0 : - 800002f0: 00000213 li tp,0 - 800002f4: 00d00093 li ra,13 - 800002f8: 00b08f13 addi t5,ra,11 - 800002fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000300: 00200293 li t0,2 - 80000304: fe5218e3 bne tp,t0,800002f4 - 80000308: 01800e93 li t4,24 - 8000030c: 01500193 li gp,21 - 80000310: 09df1063 bne t5,t4,80000390 - -0000000080000314 : - 80000314: 00000213 li tp,0 - 80000318: 00d00093 li ra,13 - 8000031c: 00000013 nop - 80000320: 00a08f13 addi t5,ra,10 - 80000324: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000328: 00200293 li t0,2 - 8000032c: fe5216e3 bne tp,t0,80000318 - 80000330: 01700e93 li t4,23 - 80000334: 01600193 li gp,22 - 80000338: 05df1c63 bne t5,t4,80000390 - -000000008000033c : - 8000033c: 00000213 li tp,0 - 80000340: 00d00093 li ra,13 - 80000344: 00000013 nop - 80000348: 00000013 nop - 8000034c: 00908f13 addi t5,ra,9 - 80000350: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000354: 00200293 li t0,2 - 80000358: fe5214e3 bne tp,t0,80000340 - 8000035c: 01600e93 li t4,22 - 80000360: 01700193 li gp,23 - 80000364: 03df1663 bne t5,t4,80000390 - -0000000080000368 : - 80000368: 02000093 li ra,32 - 8000036c: 02000e93 li t4,32 - 80000370: 01800193 li gp,24 - 80000374: 01d09e63 bne ra,t4,80000390 - -0000000080000378 : - 80000378: 02100093 li ra,33 - 8000037c: 03208013 addi zero,ra,50 - 80000380: 00000e93 li t4,0 - 80000384: 01900193 li gp,25 - 80000388: 01d01463 bne zero,t4,80000390 - 8000038c: 00301c63 bne zero,gp,800003a4 - -0000000080000390 : - 80000390: 0ff0000f fence - 80000394: 00018063 beqz gp,80000394 - 80000398: 00119193 slli gp,gp,0x1 - 8000039c: 0011e193 ori gp,gp,1 - 800003a0: 00000073 ecall - -00000000800003a4 : - 800003a4: 0ff0000f fence - 800003a8: 00100193 li gp,1 - 800003ac: 00000073 ecall - 800003b0: c0001073 unimp - 800003b4: 0000 unimp - 800003b6: 0000 unimp - 800003b8: 0000 unimp - 800003ba: 0000 unimp - 800003bc: 0000 unimp - 800003be: 0000 unimp - 800003c0: 0000 unimp - 800003c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-addi.elf b/test/riscv/tests/rv64ui-p-addi.elf deleted file mode 100644 index 511253ab..00000000 Binary files a/test/riscv/tests/rv64ui-p-addi.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-addiw.dump b/test/riscv/tests/rv64ui-p-addiw.dump deleted file mode 100644 index a84bd35c..00000000 --- a/test/riscv/tests/rv64ui-p-addiw.dump +++ /dev/null @@ -1,315 +0,0 @@ - -rv64ui-p-addiw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00000093 li ra,0 - 80000100: 00008f1b sext.w t5,ra - 80000104: 00000e93 li t4,0 - 80000108: 00200193 li gp,2 - 8000010c: 27df1c63 bne t5,t4,80000384 - -0000000080000110 : - 80000110: 00100093 li ra,1 - 80000114: 00108f1b addiw t5,ra,1 - 80000118: 00200e93 li t4,2 - 8000011c: 00300193 li gp,3 - 80000120: 27df1263 bne t5,t4,80000384 - -0000000080000124 : - 80000124: 00300093 li ra,3 - 80000128: 00708f1b addiw t5,ra,7 - 8000012c: 00a00e93 li t4,10 - 80000130: 00400193 li gp,4 - 80000134: 25df1863 bne t5,t4,80000384 - -0000000080000138 : - 80000138: 00000093 li ra,0 - 8000013c: 80008f1b addiw t5,ra,-2048 - 80000140: 80000e93 li t4,-2048 - 80000144: 00500193 li gp,5 - 80000148: 23df1e63 bne t5,t4,80000384 - -000000008000014c : - 8000014c: 800000b7 lui ra,0x80000 - 80000150: 00008f1b sext.w t5,ra - 80000154: 80000eb7 lui t4,0x80000 - 80000158: 00600193 li gp,6 - 8000015c: 23df1463 bne t5,t4,80000384 - -0000000080000160 : - 80000160: 800000b7 lui ra,0x80000 - 80000164: 80008f1b addiw t5,ra,-2048 - 80000168: 80000eb7 lui t4,0x80000 - 8000016c: 800e8e9b addiw t4,t4,-2048 - 80000170: 00700193 li gp,7 - 80000174: 21df1863 bne t5,t4,80000384 - -0000000080000178 : - 80000178: 00000093 li ra,0 - 8000017c: 7ff08f1b addiw t5,ra,2047 - 80000180: 7ff00e93 li t4,2047 - 80000184: 00800193 li gp,8 - 80000188: 1fdf1e63 bne t5,t4,80000384 - -000000008000018c : - 8000018c: 800000b7 lui ra,0x80000 - 80000190: fff0809b addiw ra,ra,-1 - 80000194: 00008f1b sext.w t5,ra - 80000198: 80000eb7 lui t4,0x80000 - 8000019c: fffe8e9b addiw t4,t4,-1 - 800001a0: 00900193 li gp,9 - 800001a4: 1fdf1063 bne t5,t4,80000384 - -00000000800001a8 : - 800001a8: 800000b7 lui ra,0x80000 - 800001ac: fff0809b addiw ra,ra,-1 - 800001b0: 7ff08f1b addiw t5,ra,2047 - 800001b4: 80000eb7 lui t4,0x80000 - 800001b8: 7fee8e9b addiw t4,t4,2046 - 800001bc: 00a00193 li gp,10 - 800001c0: 1ddf1263 bne t5,t4,80000384 - -00000000800001c4 : - 800001c4: 800000b7 lui ra,0x80000 - 800001c8: 7ff08f1b addiw t5,ra,2047 - 800001cc: 80000eb7 lui t4,0x80000 - 800001d0: 7ffe8e9b addiw t4,t4,2047 - 800001d4: 00b00193 li gp,11 - 800001d8: 1bdf1663 bne t5,t4,80000384 - -00000000800001dc : - 800001dc: 800000b7 lui ra,0x80000 - 800001e0: fff0809b addiw ra,ra,-1 - 800001e4: 80008f1b addiw t5,ra,-2048 - 800001e8: 7ffffeb7 lui t4,0x7ffff - 800001ec: 7ffe8e9b addiw t4,t4,2047 - 800001f0: 00c00193 li gp,12 - 800001f4: 19df1863 bne t5,t4,80000384 - -00000000800001f8 : - 800001f8: 00000093 li ra,0 - 800001fc: fff08f1b addiw t5,ra,-1 - 80000200: fff00e93 li t4,-1 - 80000204: 00d00193 li gp,13 - 80000208: 17df1e63 bne t5,t4,80000384 - -000000008000020c : - 8000020c: fff00093 li ra,-1 - 80000210: 00108f1b addiw t5,ra,1 - 80000214: 00000e93 li t4,0 - 80000218: 00e00193 li gp,14 - 8000021c: 17df1463 bne t5,t4,80000384 - -0000000080000220 : - 80000220: fff00093 li ra,-1 - 80000224: fff08f1b addiw t5,ra,-1 - 80000228: ffe00e93 li t4,-2 - 8000022c: 00f00193 li gp,15 - 80000230: 15df1a63 bne t5,t4,80000384 - -0000000080000234 : - 80000234: 800000b7 lui ra,0x80000 - 80000238: fff0809b addiw ra,ra,-1 - 8000023c: 00108f1b addiw t5,ra,1 - 80000240: 80000eb7 lui t4,0x80000 - 80000244: 01000193 li gp,16 - 80000248: 13df1e63 bne t5,t4,80000384 - -000000008000024c : - 8000024c: 00d00093 li ra,13 - 80000250: 00b0809b addiw ra,ra,11 - 80000254: 01800e93 li t4,24 - 80000258: 01100193 li gp,17 - 8000025c: 13d09463 bne ra,t4,80000384 - -0000000080000260 : - 80000260: 00000213 li tp,0 - 80000264: 00d00093 li ra,13 - 80000268: 00b08f1b addiw t5,ra,11 - 8000026c: 000f0313 mv t1,t5 - 80000270: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000274: 00200293 li t0,2 - 80000278: fe5216e3 bne tp,t0,80000264 - 8000027c: 01800e93 li t4,24 - 80000280: 01200193 li gp,18 - 80000284: 11d31063 bne t1,t4,80000384 - -0000000080000288 : - 80000288: 00000213 li tp,0 - 8000028c: 00d00093 li ra,13 - 80000290: 00a08f1b addiw t5,ra,10 - 80000294: 00000013 nop - 80000298: 000f0313 mv t1,t5 - 8000029c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002a0: 00200293 li t0,2 - 800002a4: fe5214e3 bne tp,t0,8000028c - 800002a8: 01700e93 li t4,23 - 800002ac: 01300193 li gp,19 - 800002b0: 0dd31a63 bne t1,t4,80000384 - -00000000800002b4 : - 800002b4: 00000213 li tp,0 - 800002b8: 00d00093 li ra,13 - 800002bc: 00908f1b addiw t5,ra,9 - 800002c0: 00000013 nop - 800002c4: 00000013 nop - 800002c8: 000f0313 mv t1,t5 - 800002cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002d0: 00200293 li t0,2 - 800002d4: fe5212e3 bne tp,t0,800002b8 - 800002d8: 01600e93 li t4,22 - 800002dc: 01400193 li gp,20 - 800002e0: 0bd31263 bne t1,t4,80000384 - -00000000800002e4 : - 800002e4: 00000213 li tp,0 - 800002e8: 00d00093 li ra,13 - 800002ec: 00b08f1b addiw t5,ra,11 - 800002f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002f4: 00200293 li t0,2 - 800002f8: fe5218e3 bne tp,t0,800002e8 - 800002fc: 01800e93 li t4,24 - 80000300: 01500193 li gp,21 - 80000304: 09df1063 bne t5,t4,80000384 - -0000000080000308 : - 80000308: 00000213 li tp,0 - 8000030c: 00d00093 li ra,13 - 80000310: 00000013 nop - 80000314: 00a08f1b addiw t5,ra,10 - 80000318: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000031c: 00200293 li t0,2 - 80000320: fe5216e3 bne tp,t0,8000030c - 80000324: 01700e93 li t4,23 - 80000328: 01600193 li gp,22 - 8000032c: 05df1c63 bne t5,t4,80000384 - -0000000080000330 : - 80000330: 00000213 li tp,0 - 80000334: 00d00093 li ra,13 - 80000338: 00000013 nop - 8000033c: 00000013 nop - 80000340: 00908f1b addiw t5,ra,9 - 80000344: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000348: 00200293 li t0,2 - 8000034c: fe5214e3 bne tp,t0,80000334 - 80000350: 01600e93 li t4,22 - 80000354: 01700193 li gp,23 - 80000358: 03df1663 bne t5,t4,80000384 - -000000008000035c : - 8000035c: 0200009b addiw ra,zero,32 - 80000360: 02000e93 li t4,32 - 80000364: 01800193 li gp,24 - 80000368: 01d09e63 bne ra,t4,80000384 - -000000008000036c : - 8000036c: 02100093 li ra,33 - 80000370: 0320801b addiw zero,ra,50 - 80000374: 00000e93 li t4,0 - 80000378: 01900193 li gp,25 - 8000037c: 01d01463 bne zero,t4,80000384 - 80000380: 00301c63 bne zero,gp,80000398 - -0000000080000384 : - 80000384: 0ff0000f fence - 80000388: 00018063 beqz gp,80000388 - 8000038c: 00119193 slli gp,gp,0x1 - 80000390: 0011e193 ori gp,gp,1 - 80000394: 00000073 ecall - -0000000080000398 : - 80000398: 0ff0000f fence - 8000039c: 00100193 li gp,1 - 800003a0: 00000073 ecall - 800003a4: c0001073 unimp - 800003a8: 0000 unimp - 800003aa: 0000 unimp - 800003ac: 0000 unimp - 800003ae: 0000 unimp - 800003b0: 0000 unimp - 800003b2: 0000 unimp - 800003b4: 0000 unimp - 800003b6: 0000 unimp - 800003b8: 0000 unimp - 800003ba: 0000 unimp - 800003bc: 0000 unimp - 800003be: 0000 unimp - 800003c0: 0000 unimp - 800003c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-addiw.elf b/test/riscv/tests/rv64ui-p-addiw.elf deleted file mode 100644 index c58d5215..00000000 Binary files a/test/riscv/tests/rv64ui-p-addiw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-addw.dump b/test/riscv/tests/rv64ui-p-addw.dump deleted file mode 100644 index 626af6d9..00000000 --- a/test/riscv/tests/rv64ui-p-addw.dump +++ /dev/null @@ -1,479 +0,0 @@ - -rv64ui-p-addw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00000093 li ra,0 - 80000100: 00000113 li sp,0 - 80000104: 00208f3b addw t5,ra,sp - 80000108: 00000e93 li t4,0 - 8000010c: 00200193 li gp,2 - 80000110: 4ddf1663 bne t5,t4,800005dc - -0000000080000114 : - 80000114: 00100093 li ra,1 - 80000118: 00100113 li sp,1 - 8000011c: 00208f3b addw t5,ra,sp - 80000120: 00200e93 li t4,2 - 80000124: 00300193 li gp,3 - 80000128: 4bdf1a63 bne t5,t4,800005dc - -000000008000012c : - 8000012c: 00300093 li ra,3 - 80000130: 00700113 li sp,7 - 80000134: 00208f3b addw t5,ra,sp - 80000138: 00a00e93 li t4,10 - 8000013c: 00400193 li gp,4 - 80000140: 49df1e63 bne t5,t4,800005dc - -0000000080000144 : - 80000144: 00000093 li ra,0 - 80000148: ffff8137 lui sp,0xffff8 - 8000014c: 00208f3b addw t5,ra,sp - 80000150: ffff8eb7 lui t4,0xffff8 - 80000154: 00500193 li gp,5 - 80000158: 49df1263 bne t5,t4,800005dc - -000000008000015c : - 8000015c: 800000b7 lui ra,0x80000 - 80000160: 00000113 li sp,0 - 80000164: 00208f3b addw t5,ra,sp - 80000168: 80000eb7 lui t4,0x80000 - 8000016c: 00600193 li gp,6 - 80000170: 47df1663 bne t5,t4,800005dc - -0000000080000174 : - 80000174: 800000b7 lui ra,0x80000 - 80000178: ffff8137 lui sp,0xffff8 - 8000017c: 00208f3b addw t5,ra,sp - 80000180: 7fff8eb7 lui t4,0x7fff8 - 80000184: 00700193 li gp,7 - 80000188: 45df1a63 bne t5,t4,800005dc - -000000008000018c : - 8000018c: 00000093 li ra,0 - 80000190: 00008137 lui sp,0x8 - 80000194: fff1011b addiw sp,sp,-1 - 80000198: 00208f3b addw t5,ra,sp - 8000019c: 00008eb7 lui t4,0x8 - 800001a0: fffe8e9b addiw t4,t4,-1 - 800001a4: 00800193 li gp,8 - 800001a8: 43df1a63 bne t5,t4,800005dc - -00000000800001ac : - 800001ac: 800000b7 lui ra,0x80000 - 800001b0: fff0809b addiw ra,ra,-1 - 800001b4: 00000113 li sp,0 - 800001b8: 00208f3b addw t5,ra,sp - 800001bc: 80000eb7 lui t4,0x80000 - 800001c0: fffe8e9b addiw t4,t4,-1 - 800001c4: 00900193 li gp,9 - 800001c8: 41df1a63 bne t5,t4,800005dc - -00000000800001cc : - 800001cc: 800000b7 lui ra,0x80000 - 800001d0: fff0809b addiw ra,ra,-1 - 800001d4: 00008137 lui sp,0x8 - 800001d8: fff1011b addiw sp,sp,-1 - 800001dc: 00208f3b addw t5,ra,sp - 800001e0: 80008eb7 lui t4,0x80008 - 800001e4: ffee8e9b addiw t4,t4,-2 - 800001e8: 00a00193 li gp,10 - 800001ec: 3fdf1863 bne t5,t4,800005dc - -00000000800001f0 : - 800001f0: 800000b7 lui ra,0x80000 - 800001f4: 00008137 lui sp,0x8 - 800001f8: fff1011b addiw sp,sp,-1 - 800001fc: 00208f3b addw t5,ra,sp - 80000200: 80008eb7 lui t4,0x80008 - 80000204: fffe8e9b addiw t4,t4,-1 - 80000208: 00b00193 li gp,11 - 8000020c: 3ddf1863 bne t5,t4,800005dc - -0000000080000210 : - 80000210: 800000b7 lui ra,0x80000 - 80000214: fff0809b addiw ra,ra,-1 - 80000218: ffff8137 lui sp,0xffff8 - 8000021c: 00208f3b addw t5,ra,sp - 80000220: 7fff8eb7 lui t4,0x7fff8 - 80000224: fffe8e9b addiw t4,t4,-1 - 80000228: 00c00193 li gp,12 - 8000022c: 3bdf1863 bne t5,t4,800005dc - -0000000080000230 : - 80000230: 00000093 li ra,0 - 80000234: fff00113 li sp,-1 - 80000238: 00208f3b addw t5,ra,sp - 8000023c: fff00e93 li t4,-1 - 80000240: 00d00193 li gp,13 - 80000244: 39df1c63 bne t5,t4,800005dc - -0000000080000248 : - 80000248: fff00093 li ra,-1 - 8000024c: 00100113 li sp,1 - 80000250: 00208f3b addw t5,ra,sp - 80000254: 00000e93 li t4,0 - 80000258: 00e00193 li gp,14 - 8000025c: 39df1063 bne t5,t4,800005dc - -0000000080000260 : - 80000260: fff00093 li ra,-1 - 80000264: fff00113 li sp,-1 - 80000268: 00208f3b addw t5,ra,sp - 8000026c: ffe00e93 li t4,-2 - 80000270: 00f00193 li gp,15 - 80000274: 37df1463 bne t5,t4,800005dc - -0000000080000278 : - 80000278: 00100093 li ra,1 - 8000027c: 80000137 lui sp,0x80000 - 80000280: fff1011b addiw sp,sp,-1 - 80000284: 00208f3b addw t5,ra,sp - 80000288: 80000eb7 lui t4,0x80000 - 8000028c: 01000193 li gp,16 - 80000290: 35df1663 bne t5,t4,800005dc - -0000000080000294 : - 80000294: 00d00093 li ra,13 - 80000298: 00b00113 li sp,11 - 8000029c: 002080bb addw ra,ra,sp - 800002a0: 01800e93 li t4,24 - 800002a4: 01100193 li gp,17 - 800002a8: 33d09a63 bne ra,t4,800005dc - -00000000800002ac : - 800002ac: 00e00093 li ra,14 - 800002b0: 00b00113 li sp,11 - 800002b4: 0020813b addw sp,ra,sp - 800002b8: 01900e93 li t4,25 - 800002bc: 01200193 li gp,18 - 800002c0: 31d11e63 bne sp,t4,800005dc - -00000000800002c4 : - 800002c4: 00d00093 li ra,13 - 800002c8: 001080bb addw ra,ra,ra - 800002cc: 01a00e93 li t4,26 - 800002d0: 01300193 li gp,19 - 800002d4: 31d09463 bne ra,t4,800005dc - -00000000800002d8 : - 800002d8: 00000213 li tp,0 - 800002dc: 00d00093 li ra,13 - 800002e0: 00b00113 li sp,11 - 800002e4: 00208f3b addw t5,ra,sp - 800002e8: 000f0313 mv t1,t5 - 800002ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002f0: 00200293 li t0,2 - 800002f4: fe5214e3 bne tp,t0,800002dc - 800002f8: 01800e93 li t4,24 - 800002fc: 01400193 li gp,20 - 80000300: 2dd31e63 bne t1,t4,800005dc - -0000000080000304 : - 80000304: 00000213 li tp,0 - 80000308: 00e00093 li ra,14 - 8000030c: 00b00113 li sp,11 - 80000310: 00208f3b addw t5,ra,sp - 80000314: 00000013 nop - 80000318: 000f0313 mv t1,t5 - 8000031c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000320: 00200293 li t0,2 - 80000324: fe5212e3 bne tp,t0,80000308 - 80000328: 01900e93 li t4,25 - 8000032c: 01500193 li gp,21 - 80000330: 2bd31663 bne t1,t4,800005dc - -0000000080000334 : - 80000334: 00000213 li tp,0 - 80000338: 00f00093 li ra,15 - 8000033c: 00b00113 li sp,11 - 80000340: 00208f3b addw t5,ra,sp - 80000344: 00000013 nop - 80000348: 00000013 nop - 8000034c: 000f0313 mv t1,t5 - 80000350: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000354: 00200293 li t0,2 - 80000358: fe5210e3 bne tp,t0,80000338 - 8000035c: 01a00e93 li t4,26 - 80000360: 01600193 li gp,22 - 80000364: 27d31c63 bne t1,t4,800005dc - -0000000080000368 : - 80000368: 00000213 li tp,0 - 8000036c: 00d00093 li ra,13 - 80000370: 00b00113 li sp,11 - 80000374: 00208f3b addw t5,ra,sp - 80000378: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000037c: 00200293 li t0,2 - 80000380: fe5216e3 bne tp,t0,8000036c - 80000384: 01800e93 li t4,24 - 80000388: 01700193 li gp,23 - 8000038c: 25df1863 bne t5,t4,800005dc - -0000000080000390 : - 80000390: 00000213 li tp,0 - 80000394: 00e00093 li ra,14 - 80000398: 00b00113 li sp,11 - 8000039c: 00000013 nop - 800003a0: 00208f3b addw t5,ra,sp - 800003a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003a8: 00200293 li t0,2 - 800003ac: fe5214e3 bne tp,t0,80000394 - 800003b0: 01900e93 li t4,25 - 800003b4: 01800193 li gp,24 - 800003b8: 23df1263 bne t5,t4,800005dc - -00000000800003bc : - 800003bc: 00000213 li tp,0 - 800003c0: 00f00093 li ra,15 - 800003c4: 00b00113 li sp,11 - 800003c8: 00000013 nop - 800003cc: 00000013 nop - 800003d0: 00208f3b addw t5,ra,sp - 800003d4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003d8: 00200293 li t0,2 - 800003dc: fe5212e3 bne tp,t0,800003c0 - 800003e0: 01a00e93 li t4,26 - 800003e4: 01900193 li gp,25 - 800003e8: 1fdf1a63 bne t5,t4,800005dc - -00000000800003ec : - 800003ec: 00000213 li tp,0 - 800003f0: 00d00093 li ra,13 - 800003f4: 00000013 nop - 800003f8: 00b00113 li sp,11 - 800003fc: 00208f3b addw t5,ra,sp - 80000400: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000404: 00200293 li t0,2 - 80000408: fe5214e3 bne tp,t0,800003f0 - 8000040c: 01800e93 li t4,24 - 80000410: 01a00193 li gp,26 - 80000414: 1ddf1463 bne t5,t4,800005dc - -0000000080000418 : - 80000418: 00000213 li tp,0 - 8000041c: 00e00093 li ra,14 - 80000420: 00000013 nop - 80000424: 00b00113 li sp,11 - 80000428: 00000013 nop - 8000042c: 00208f3b addw t5,ra,sp - 80000430: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000434: 00200293 li t0,2 - 80000438: fe5212e3 bne tp,t0,8000041c - 8000043c: 01900e93 li t4,25 - 80000440: 01b00193 li gp,27 - 80000444: 19df1c63 bne t5,t4,800005dc - -0000000080000448 : - 80000448: 00000213 li tp,0 - 8000044c: 00f00093 li ra,15 - 80000450: 00000013 nop - 80000454: 00000013 nop - 80000458: 00b00113 li sp,11 - 8000045c: 00208f3b addw t5,ra,sp - 80000460: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000464: 00200293 li t0,2 - 80000468: fe5212e3 bne tp,t0,8000044c - 8000046c: 01a00e93 li t4,26 - 80000470: 01c00193 li gp,28 - 80000474: 17df1463 bne t5,t4,800005dc - -0000000080000478 : - 80000478: 00000213 li tp,0 - 8000047c: 00b00113 li sp,11 - 80000480: 00d00093 li ra,13 - 80000484: 00208f3b addw t5,ra,sp - 80000488: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000048c: 00200293 li t0,2 - 80000490: fe5216e3 bne tp,t0,8000047c - 80000494: 01800e93 li t4,24 - 80000498: 01d00193 li gp,29 - 8000049c: 15df1063 bne t5,t4,800005dc - -00000000800004a0 : - 800004a0: 00000213 li tp,0 - 800004a4: 00b00113 li sp,11 - 800004a8: 00e00093 li ra,14 - 800004ac: 00000013 nop - 800004b0: 00208f3b addw t5,ra,sp - 800004b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004b8: 00200293 li t0,2 - 800004bc: fe5214e3 bne tp,t0,800004a4 - 800004c0: 01900e93 li t4,25 - 800004c4: 01e00193 li gp,30 - 800004c8: 11df1a63 bne t5,t4,800005dc - -00000000800004cc : - 800004cc: 00000213 li tp,0 - 800004d0: 00b00113 li sp,11 - 800004d4: 00f00093 li ra,15 - 800004d8: 00000013 nop - 800004dc: 00000013 nop - 800004e0: 00208f3b addw t5,ra,sp - 800004e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004e8: 00200293 li t0,2 - 800004ec: fe5212e3 bne tp,t0,800004d0 - 800004f0: 01a00e93 li t4,26 - 800004f4: 01f00193 li gp,31 - 800004f8: 0fdf1263 bne t5,t4,800005dc - -00000000800004fc : - 800004fc: 00000213 li tp,0 - 80000500: 00b00113 li sp,11 - 80000504: 00000013 nop - 80000508: 00d00093 li ra,13 - 8000050c: 00208f3b addw t5,ra,sp - 80000510: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000514: 00200293 li t0,2 - 80000518: fe5214e3 bne tp,t0,80000500 - 8000051c: 01800e93 li t4,24 - 80000520: 02000193 li gp,32 - 80000524: 0bdf1c63 bne t5,t4,800005dc - -0000000080000528 : - 80000528: 00000213 li tp,0 - 8000052c: 00b00113 li sp,11 - 80000530: 00000013 nop - 80000534: 00e00093 li ra,14 - 80000538: 00000013 nop - 8000053c: 00208f3b addw t5,ra,sp - 80000540: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000544: 00200293 li t0,2 - 80000548: fe5212e3 bne tp,t0,8000052c - 8000054c: 01900e93 li t4,25 - 80000550: 02100193 li gp,33 - 80000554: 09df1463 bne t5,t4,800005dc - -0000000080000558 : - 80000558: 00000213 li tp,0 - 8000055c: 00b00113 li sp,11 - 80000560: 00000013 nop - 80000564: 00000013 nop - 80000568: 00f00093 li ra,15 - 8000056c: 00208f3b addw t5,ra,sp - 80000570: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000574: 00200293 li t0,2 - 80000578: fe5212e3 bne tp,t0,8000055c - 8000057c: 01a00e93 li t4,26 - 80000580: 02200193 li gp,34 - 80000584: 05df1c63 bne t5,t4,800005dc - -0000000080000588 : - 80000588: 00f00093 li ra,15 - 8000058c: 0010013b addw sp,zero,ra - 80000590: 00f00e93 li t4,15 - 80000594: 02300193 li gp,35 - 80000598: 05d11263 bne sp,t4,800005dc - -000000008000059c : - 8000059c: 02000093 li ra,32 - 800005a0: 0000813b addw sp,ra,zero - 800005a4: 02000e93 li t4,32 - 800005a8: 02400193 li gp,36 - 800005ac: 03d11863 bne sp,t4,800005dc - -00000000800005b0 : - 800005b0: 000000bb addw ra,zero,zero - 800005b4: 00000e93 li t4,0 - 800005b8: 02500193 li gp,37 - 800005bc: 03d09063 bne ra,t4,800005dc - -00000000800005c0 : - 800005c0: 01000093 li ra,16 - 800005c4: 01e00113 li sp,30 - 800005c8: 0020803b addw zero,ra,sp - 800005cc: 00000e93 li t4,0 - 800005d0: 02600193 li gp,38 - 800005d4: 01d01463 bne zero,t4,800005dc - 800005d8: 00301c63 bne zero,gp,800005f0 - -00000000800005dc : - 800005dc: 0ff0000f fence - 800005e0: 00018063 beqz gp,800005e0 - 800005e4: 00119193 slli gp,gp,0x1 - 800005e8: 0011e193 ori gp,gp,1 - 800005ec: 00000073 ecall - -00000000800005f0 : - 800005f0: 0ff0000f fence - 800005f4: 00100193 li gp,1 - 800005f8: 00000073 ecall - 800005fc: c0001073 unimp - 80000600: 0000 unimp - 80000602: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-addw.elf b/test/riscv/tests/rv64ui-p-addw.elf deleted file mode 100644 index b4cc4910..00000000 Binary files a/test/riscv/tests/rv64ui-p-addw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-and.dump b/test/riscv/tests/rv64ui-p-and.dump deleted file mode 100644 index 5851df86..00000000 --- a/test/riscv/tests/rv64ui-p-and.dump +++ /dev/null @@ -1,491 +0,0 @@ - -rv64ui-p-and: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 000100b7 lui ra,0x10 - 80000100: f010809b addiw ra,ra,-255 - 80000104: 01009093 slli ra,ra,0x10 - 80000108: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 8000010c: 0f0f1137 lui sp,0xf0f1 - 80000110: f0f1011b addiw sp,sp,-241 - 80000114: 0020ff33 and t5,ra,sp - 80000118: 0f001eb7 lui t4,0xf001 - 8000011c: f00e8e9b addiw t4,t4,-256 - 80000120: 00200193 li gp,2 - 80000124: 53df1863 bne t5,t4,80000654 - -0000000080000128 : - 80000128: 0ff010b7 lui ra,0xff01 - 8000012c: ff00809b addiw ra,ra,-16 - 80000130: 000f1137 lui sp,0xf1 - 80000134: f0f1011b addiw sp,sp,-241 - 80000138: 00c11113 slli sp,sp,0xc - 8000013c: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80000140: 0020ff33 and t5,ra,sp - 80000144: 00f00eb7 lui t4,0xf00 - 80000148: 0f0e8e9b addiw t4,t4,240 - 8000014c: 00300193 li gp,3 - 80000150: 51df1263 bne t5,t4,80000654 - -0000000080000154 : - 80000154: 00ff00b7 lui ra,0xff0 - 80000158: 0ff0809b addiw ra,ra,255 - 8000015c: 0f0f1137 lui sp,0xf0f1 - 80000160: f0f1011b addiw sp,sp,-241 - 80000164: 0020ff33 and t5,ra,sp - 80000168: 000f0eb7 lui t4,0xf0 - 8000016c: 00fe8e9b addiw t4,t4,15 - 80000170: 00400193 li gp,4 - 80000174: 4fdf1063 bne t5,t4,80000654 - -0000000080000178 : - 80000178: 000f00b7 lui ra,0xf0 - 8000017c: 0ff0809b addiw ra,ra,255 - 80000180: 00c09093 slli ra,ra,0xc - 80000184: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> - 80000188: 000f1137 lui sp,0xf1 - 8000018c: f0f1011b addiw sp,sp,-241 - 80000190: 00c11113 slli sp,sp,0xc - 80000194: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80000198: 0020ff33 and t5,ra,sp - 8000019c: 000f0eb7 lui t4,0xf0 - 800001a0: 00fe8e9b addiw t4,t4,15 - 800001a4: 00ce9e93 slli t4,t4,0xc - 800001a8: 00500193 li gp,5 - 800001ac: 4bdf1463 bne t5,t4,80000654 - -00000000800001b0 : - 800001b0: 000100b7 lui ra,0x10 - 800001b4: f010809b addiw ra,ra,-255 - 800001b8: 01009093 slli ra,ra,0x10 - 800001bc: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 800001c0: 0f0f1137 lui sp,0xf0f1 - 800001c4: f0f1011b addiw sp,sp,-241 - 800001c8: 0020f0b3 and ra,ra,sp - 800001cc: 0f001eb7 lui t4,0xf001 - 800001d0: f00e8e9b addiw t4,t4,-256 - 800001d4: 00600193 li gp,6 - 800001d8: 47d09e63 bne ra,t4,80000654 - -00000000800001dc : - 800001dc: 0ff010b7 lui ra,0xff01 - 800001e0: ff00809b addiw ra,ra,-16 - 800001e4: 000f1137 lui sp,0xf1 - 800001e8: f0f1011b addiw sp,sp,-241 - 800001ec: 00c11113 slli sp,sp,0xc - 800001f0: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 800001f4: 0020f133 and sp,ra,sp - 800001f8: 00f00eb7 lui t4,0xf00 - 800001fc: 0f0e8e9b addiw t4,t4,240 - 80000200: 00700193 li gp,7 - 80000204: 45d11863 bne sp,t4,80000654 - -0000000080000208 : - 80000208: 000100b7 lui ra,0x10 - 8000020c: f010809b addiw ra,ra,-255 - 80000210: 01009093 slli ra,ra,0x10 - 80000214: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80000218: 0010f0b3 and ra,ra,ra - 8000021c: 00010eb7 lui t4,0x10 - 80000220: f01e8e9b addiw t4,t4,-255 - 80000224: 010e9e93 slli t4,t4,0x10 - 80000228: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 8000022c: 00800193 li gp,8 - 80000230: 43d09263 bne ra,t4,80000654 - -0000000080000234 : - 80000234: 00000213 li tp,0 - 80000238: 000100b7 lui ra,0x10 - 8000023c: f010809b addiw ra,ra,-255 - 80000240: 01009093 slli ra,ra,0x10 - 80000244: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80000248: 0f0f1137 lui sp,0xf0f1 - 8000024c: f0f1011b addiw sp,sp,-241 - 80000250: 0020ff33 and t5,ra,sp - 80000254: 000f0313 mv t1,t5 - 80000258: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000025c: 00200293 li t0,2 - 80000260: fc521ce3 bne tp,t0,80000238 - 80000264: 0f001eb7 lui t4,0xf001 - 80000268: f00e8e9b addiw t4,t4,-256 - 8000026c: 00900193 li gp,9 - 80000270: 3fd31263 bne t1,t4,80000654 - -0000000080000274 : - 80000274: 00000213 li tp,0 - 80000278: 0ff010b7 lui ra,0xff01 - 8000027c: ff00809b addiw ra,ra,-16 - 80000280: 000f1137 lui sp,0xf1 - 80000284: f0f1011b addiw sp,sp,-241 - 80000288: 00c11113 slli sp,sp,0xc - 8000028c: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80000290: 0020ff33 and t5,ra,sp - 80000294: 00000013 nop - 80000298: 000f0313 mv t1,t5 - 8000029c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002a0: 00200293 li t0,2 - 800002a4: fc521ae3 bne tp,t0,80000278 - 800002a8: 00f00eb7 lui t4,0xf00 - 800002ac: 0f0e8e9b addiw t4,t4,240 - 800002b0: 00a00193 li gp,10 - 800002b4: 3bd31063 bne t1,t4,80000654 - -00000000800002b8 : - 800002b8: 00000213 li tp,0 - 800002bc: 00ff00b7 lui ra,0xff0 - 800002c0: 0ff0809b addiw ra,ra,255 - 800002c4: 0f0f1137 lui sp,0xf0f1 - 800002c8: f0f1011b addiw sp,sp,-241 - 800002cc: 0020ff33 and t5,ra,sp - 800002d0: 00000013 nop - 800002d4: 00000013 nop - 800002d8: 000f0313 mv t1,t5 - 800002dc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002e0: 00200293 li t0,2 - 800002e4: fc521ce3 bne tp,t0,800002bc - 800002e8: 000f0eb7 lui t4,0xf0 - 800002ec: 00fe8e9b addiw t4,t4,15 - 800002f0: 00b00193 li gp,11 - 800002f4: 37d31063 bne t1,t4,80000654 - -00000000800002f8 : - 800002f8: 00000213 li tp,0 - 800002fc: 000100b7 lui ra,0x10 - 80000300: f010809b addiw ra,ra,-255 - 80000304: 01009093 slli ra,ra,0x10 - 80000308: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 8000030c: 0f0f1137 lui sp,0xf0f1 - 80000310: f0f1011b addiw sp,sp,-241 - 80000314: 0020ff33 and t5,ra,sp - 80000318: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000031c: 00200293 li t0,2 - 80000320: fc521ee3 bne tp,t0,800002fc - 80000324: 0f001eb7 lui t4,0xf001 - 80000328: f00e8e9b addiw t4,t4,-256 - 8000032c: 00c00193 li gp,12 - 80000330: 33df1263 bne t5,t4,80000654 - -0000000080000334 : - 80000334: 00000213 li tp,0 - 80000338: 0ff010b7 lui ra,0xff01 - 8000033c: ff00809b addiw ra,ra,-16 - 80000340: 000f1137 lui sp,0xf1 - 80000344: f0f1011b addiw sp,sp,-241 - 80000348: 00c11113 slli sp,sp,0xc - 8000034c: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80000350: 00000013 nop - 80000354: 0020ff33 and t5,ra,sp - 80000358: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000035c: 00200293 li t0,2 - 80000360: fc521ce3 bne tp,t0,80000338 - 80000364: 00f00eb7 lui t4,0xf00 - 80000368: 0f0e8e9b addiw t4,t4,240 - 8000036c: 00d00193 li gp,13 - 80000370: 2fdf1263 bne t5,t4,80000654 - -0000000080000374 : - 80000374: 00000213 li tp,0 - 80000378: 00ff00b7 lui ra,0xff0 - 8000037c: 0ff0809b addiw ra,ra,255 - 80000380: 0f0f1137 lui sp,0xf0f1 - 80000384: f0f1011b addiw sp,sp,-241 - 80000388: 00000013 nop - 8000038c: 00000013 nop - 80000390: 0020ff33 and t5,ra,sp - 80000394: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000398: 00200293 li t0,2 - 8000039c: fc521ee3 bne tp,t0,80000378 - 800003a0: 000f0eb7 lui t4,0xf0 - 800003a4: 00fe8e9b addiw t4,t4,15 - 800003a8: 00e00193 li gp,14 - 800003ac: 2bdf1463 bne t5,t4,80000654 - -00000000800003b0 : - 800003b0: 00000213 li tp,0 - 800003b4: 000100b7 lui ra,0x10 - 800003b8: f010809b addiw ra,ra,-255 - 800003bc: 01009093 slli ra,ra,0x10 - 800003c0: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 800003c4: 00000013 nop - 800003c8: 0f0f1137 lui sp,0xf0f1 - 800003cc: f0f1011b addiw sp,sp,-241 - 800003d0: 0020ff33 and t5,ra,sp - 800003d4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003d8: 00200293 li t0,2 - 800003dc: fc521ce3 bne tp,t0,800003b4 - 800003e0: 0f001eb7 lui t4,0xf001 - 800003e4: f00e8e9b addiw t4,t4,-256 - 800003e8: 00f00193 li gp,15 - 800003ec: 27df1463 bne t5,t4,80000654 - -00000000800003f0 : - 800003f0: 00000213 li tp,0 - 800003f4: 0ff010b7 lui ra,0xff01 - 800003f8: ff00809b addiw ra,ra,-16 - 800003fc: 00000013 nop - 80000400: 000f1137 lui sp,0xf1 - 80000404: f0f1011b addiw sp,sp,-241 - 80000408: 00c11113 slli sp,sp,0xc - 8000040c: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80000410: 00000013 nop - 80000414: 0020ff33 and t5,ra,sp - 80000418: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000041c: 00200293 li t0,2 - 80000420: fc521ae3 bne tp,t0,800003f4 - 80000424: 00f00eb7 lui t4,0xf00 - 80000428: 0f0e8e9b addiw t4,t4,240 - 8000042c: 01000193 li gp,16 - 80000430: 23df1263 bne t5,t4,80000654 - -0000000080000434 : - 80000434: 00000213 li tp,0 - 80000438: 00ff00b7 lui ra,0xff0 - 8000043c: 0ff0809b addiw ra,ra,255 - 80000440: 00000013 nop - 80000444: 00000013 nop - 80000448: 0f0f1137 lui sp,0xf0f1 - 8000044c: f0f1011b addiw sp,sp,-241 - 80000450: 0020ff33 and t5,ra,sp - 80000454: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000458: 00200293 li t0,2 - 8000045c: fc521ee3 bne tp,t0,80000438 - 80000460: 000f0eb7 lui t4,0xf0 - 80000464: 00fe8e9b addiw t4,t4,15 - 80000468: 01100193 li gp,17 - 8000046c: 1fdf1463 bne t5,t4,80000654 - -0000000080000470 : - 80000470: 00000213 li tp,0 - 80000474: 0f0f1137 lui sp,0xf0f1 - 80000478: f0f1011b addiw sp,sp,-241 - 8000047c: 000100b7 lui ra,0x10 - 80000480: f010809b addiw ra,ra,-255 - 80000484: 01009093 slli ra,ra,0x10 - 80000488: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 8000048c: 0020ff33 and t5,ra,sp - 80000490: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000494: 00200293 li t0,2 - 80000498: fc521ee3 bne tp,t0,80000474 - 8000049c: 0f001eb7 lui t4,0xf001 - 800004a0: f00e8e9b addiw t4,t4,-256 - 800004a4: 01200193 li gp,18 - 800004a8: 1bdf1663 bne t5,t4,80000654 - -00000000800004ac : - 800004ac: 00000213 li tp,0 - 800004b0: 000f1137 lui sp,0xf1 - 800004b4: f0f1011b addiw sp,sp,-241 - 800004b8: 00c11113 slli sp,sp,0xc - 800004bc: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 800004c0: 0ff010b7 lui ra,0xff01 - 800004c4: ff00809b addiw ra,ra,-16 - 800004c8: 00000013 nop - 800004cc: 0020ff33 and t5,ra,sp - 800004d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004d4: 00200293 li t0,2 - 800004d8: fc521ce3 bne tp,t0,800004b0 - 800004dc: 00f00eb7 lui t4,0xf00 - 800004e0: 0f0e8e9b addiw t4,t4,240 - 800004e4: 01300193 li gp,19 - 800004e8: 17df1663 bne t5,t4,80000654 - -00000000800004ec : - 800004ec: 00000213 li tp,0 - 800004f0: 0f0f1137 lui sp,0xf0f1 - 800004f4: f0f1011b addiw sp,sp,-241 - 800004f8: 00ff00b7 lui ra,0xff0 - 800004fc: 0ff0809b addiw ra,ra,255 - 80000500: 00000013 nop - 80000504: 00000013 nop - 80000508: 0020ff33 and t5,ra,sp - 8000050c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000510: 00200293 li t0,2 - 80000514: fc521ee3 bne tp,t0,800004f0 - 80000518: 000f0eb7 lui t4,0xf0 - 8000051c: 00fe8e9b addiw t4,t4,15 - 80000520: 01400193 li gp,20 - 80000524: 13df1863 bne t5,t4,80000654 - -0000000080000528 : - 80000528: 00000213 li tp,0 - 8000052c: 0f0f1137 lui sp,0xf0f1 - 80000530: f0f1011b addiw sp,sp,-241 - 80000534: 00000013 nop - 80000538: 000100b7 lui ra,0x10 - 8000053c: f010809b addiw ra,ra,-255 - 80000540: 01009093 slli ra,ra,0x10 - 80000544: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80000548: 0020ff33 and t5,ra,sp - 8000054c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000550: 00200293 li t0,2 - 80000554: fc521ce3 bne tp,t0,8000052c - 80000558: 0f001eb7 lui t4,0xf001 - 8000055c: f00e8e9b addiw t4,t4,-256 - 80000560: 01500193 li gp,21 - 80000564: 0fdf1863 bne t5,t4,80000654 - -0000000080000568 : - 80000568: 00000213 li tp,0 - 8000056c: 000f1137 lui sp,0xf1 - 80000570: f0f1011b addiw sp,sp,-241 - 80000574: 00c11113 slli sp,sp,0xc - 80000578: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 8000057c: 00000013 nop - 80000580: 0ff010b7 lui ra,0xff01 - 80000584: ff00809b addiw ra,ra,-16 - 80000588: 00000013 nop - 8000058c: 0020ff33 and t5,ra,sp - 80000590: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000594: 00200293 li t0,2 - 80000598: fc521ae3 bne tp,t0,8000056c - 8000059c: 00f00eb7 lui t4,0xf00 - 800005a0: 0f0e8e9b addiw t4,t4,240 - 800005a4: 01600193 li gp,22 - 800005a8: 0bdf1663 bne t5,t4,80000654 - -00000000800005ac : - 800005ac: 00000213 li tp,0 - 800005b0: 0f0f1137 lui sp,0xf0f1 - 800005b4: f0f1011b addiw sp,sp,-241 - 800005b8: 00000013 nop - 800005bc: 00000013 nop - 800005c0: 00ff00b7 lui ra,0xff0 - 800005c4: 0ff0809b addiw ra,ra,255 - 800005c8: 0020ff33 and t5,ra,sp - 800005cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800005d0: 00200293 li t0,2 - 800005d4: fc521ee3 bne tp,t0,800005b0 - 800005d8: 000f0eb7 lui t4,0xf0 - 800005dc: 00fe8e9b addiw t4,t4,15 - 800005e0: 01700193 li gp,23 - 800005e4: 07df1863 bne t5,t4,80000654 - -00000000800005e8 : - 800005e8: 000100b7 lui ra,0x10 - 800005ec: f010809b addiw ra,ra,-255 - 800005f0: 01009093 slli ra,ra,0x10 - 800005f4: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 800005f8: 00107133 and sp,zero,ra - 800005fc: 00000e93 li t4,0 - 80000600: 01800193 li gp,24 - 80000604: 05d11863 bne sp,t4,80000654 - -0000000080000608 : - 80000608: 00ff00b7 lui ra,0xff0 - 8000060c: 0ff0809b addiw ra,ra,255 - 80000610: 0000f133 and sp,ra,zero - 80000614: 00000e93 li t4,0 - 80000618: 01900193 li gp,25 - 8000061c: 03d11c63 bne sp,t4,80000654 - -0000000080000620 : - 80000620: 000070b3 and ra,zero,zero - 80000624: 00000e93 li t4,0 - 80000628: 01a00193 li gp,26 - 8000062c: 03d09463 bne ra,t4,80000654 - -0000000080000630 : - 80000630: 111110b7 lui ra,0x11111 - 80000634: 1110809b addiw ra,ra,273 - 80000638: 22222137 lui sp,0x22222 - 8000063c: 2221011b addiw sp,sp,546 - 80000640: 0020f033 and zero,ra,sp - 80000644: 00000e93 li t4,0 - 80000648: 01b00193 li gp,27 - 8000064c: 01d01463 bne zero,t4,80000654 - 80000650: 00301c63 bne zero,gp,80000668 - -0000000080000654 : - 80000654: 0ff0000f fence - 80000658: 00018063 beqz gp,80000658 - 8000065c: 00119193 slli gp,gp,0x1 - 80000660: 0011e193 ori gp,gp,1 - 80000664: 00000073 ecall - -0000000080000668 : - 80000668: 0ff0000f fence - 8000066c: 00100193 li gp,1 - 80000670: 00000073 ecall - 80000674: c0001073 unimp - 80000678: 0000 unimp - 8000067a: 0000 unimp - 8000067c: 0000 unimp - 8000067e: 0000 unimp - 80000680: 0000 unimp - 80000682: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-and.elf b/test/riscv/tests/rv64ui-p-and.elf deleted file mode 100644 index 6450bbc4..00000000 Binary files a/test/riscv/tests/rv64ui-p-and.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-andi.dump b/test/riscv/tests/rv64ui-p-andi.dump deleted file mode 100644 index 2349dd1c..00000000 --- a/test/riscv/tests/rv64ui-p-andi.dump +++ /dev/null @@ -1,265 +0,0 @@ - -rv64ui-p-andi: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 000100b7 lui ra,0x10 - 80000100: f010809b addiw ra,ra,-255 - 80000104: 01009093 slli ra,ra,0x10 - 80000108: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 8000010c: f0f0ff13 andi t5,ra,-241 - 80000110: 00010eb7 lui t4,0x10 - 80000114: f01e8e9b addiw t4,t4,-255 - 80000118: 010e9e93 slli t4,t4,0x10 - 8000011c: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80000120: 00200193 li gp,2 - 80000124: 1ddf1863 bne t5,t4,800002f4 - -0000000080000128 : - 80000128: 0ff010b7 lui ra,0xff01 - 8000012c: ff00809b addiw ra,ra,-16 - 80000130: 0f00ff13 andi t5,ra,240 - 80000134: 0f000e93 li t4,240 - 80000138: 00300193 li gp,3 - 8000013c: 1bdf1c63 bne t5,t4,800002f4 - -0000000080000140 : - 80000140: 00ff00b7 lui ra,0xff0 - 80000144: 0ff0809b addiw ra,ra,255 - 80000148: 70f0ff13 andi t5,ra,1807 - 8000014c: 00f00e93 li t4,15 - 80000150: 00400193 li gp,4 - 80000154: 1bdf1063 bne t5,t4,800002f4 - -0000000080000158 : - 80000158: 000f00b7 lui ra,0xf0 - 8000015c: 0ff0809b addiw ra,ra,255 - 80000160: 00c09093 slli ra,ra,0xc - 80000164: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> - 80000168: 0f00ff13 andi t5,ra,240 - 8000016c: 00000e93 li t4,0 - 80000170: 00500193 li gp,5 - 80000174: 19df1063 bne t5,t4,800002f4 - -0000000080000178 : - 80000178: 000100b7 lui ra,0x10 - 8000017c: f010809b addiw ra,ra,-255 - 80000180: 01009093 slli ra,ra,0x10 - 80000184: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80000188: 0f00f093 andi ra,ra,240 - 8000018c: 00000e93 li t4,0 - 80000190: 00600193 li gp,6 - 80000194: 17d09063 bne ra,t4,800002f4 - -0000000080000198 : - 80000198: 00000213 li tp,0 - 8000019c: 0ff010b7 lui ra,0xff01 - 800001a0: ff00809b addiw ra,ra,-16 - 800001a4: 70f0ff13 andi t5,ra,1807 - 800001a8: 000f0313 mv t1,t5 - 800001ac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800001b0: 00200293 li t0,2 - 800001b4: fe5214e3 bne tp,t0,8000019c - 800001b8: 70000e93 li t4,1792 - 800001bc: 00700193 li gp,7 - 800001c0: 13d31a63 bne t1,t4,800002f4 - -00000000800001c4 : - 800001c4: 00000213 li tp,0 - 800001c8: 00ff00b7 lui ra,0xff0 - 800001cc: 0ff0809b addiw ra,ra,255 - 800001d0: 0f00ff13 andi t5,ra,240 - 800001d4: 00000013 nop - 800001d8: 000f0313 mv t1,t5 - 800001dc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800001e0: 00200293 li t0,2 - 800001e4: fe5212e3 bne tp,t0,800001c8 - 800001e8: 0f000e93 li t4,240 - 800001ec: 00800193 li gp,8 - 800001f0: 11d31263 bne t1,t4,800002f4 - -00000000800001f4 : - 800001f4: 00000213 li tp,0 - 800001f8: 000f00b7 lui ra,0xf0 - 800001fc: 0ff0809b addiw ra,ra,255 - 80000200: 00c09093 slli ra,ra,0xc - 80000204: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> - 80000208: f0f0ff13 andi t5,ra,-241 - 8000020c: 00000013 nop - 80000210: 00000013 nop - 80000214: 000f0313 mv t1,t5 - 80000218: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000021c: 00200293 li t0,2 - 80000220: fc521ce3 bne tp,t0,800001f8 - 80000224: 000f0eb7 lui t4,0xf0 - 80000228: 0ffe8e9b addiw t4,t4,255 - 8000022c: 00ce9e93 slli t4,t4,0xc - 80000230: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 80000234: 00900193 li gp,9 - 80000238: 0bd31e63 bne t1,t4,800002f4 - -000000008000023c : - 8000023c: 00000213 li tp,0 - 80000240: 0ff010b7 lui ra,0xff01 - 80000244: ff00809b addiw ra,ra,-16 - 80000248: 70f0ff13 andi t5,ra,1807 - 8000024c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000250: 00200293 li t0,2 - 80000254: fe5216e3 bne tp,t0,80000240 - 80000258: 70000e93 li t4,1792 - 8000025c: 00a00193 li gp,10 - 80000260: 09df1a63 bne t5,t4,800002f4 - -0000000080000264 : - 80000264: 00000213 li tp,0 - 80000268: 00ff00b7 lui ra,0xff0 - 8000026c: 0ff0809b addiw ra,ra,255 - 80000270: 00000013 nop - 80000274: 0f00ff13 andi t5,ra,240 - 80000278: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000027c: 00200293 li t0,2 - 80000280: fe5214e3 bne tp,t0,80000268 - 80000284: 0f000e93 li t4,240 - 80000288: 00b00193 li gp,11 - 8000028c: 07df1463 bne t5,t4,800002f4 - -0000000080000290 : - 80000290: 00000213 li tp,0 - 80000294: 000f00b7 lui ra,0xf0 - 80000298: 0ff0809b addiw ra,ra,255 - 8000029c: 00c09093 slli ra,ra,0xc - 800002a0: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> - 800002a4: 00000013 nop - 800002a8: 00000013 nop - 800002ac: 70f0ff13 andi t5,ra,1807 - 800002b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002b4: 00200293 li t0,2 - 800002b8: fc521ee3 bne tp,t0,80000294 - 800002bc: 00f00e93 li t4,15 - 800002c0: 00c00193 li gp,12 - 800002c4: 03df1863 bne t5,t4,800002f4 - -00000000800002c8 : - 800002c8: 0f007093 andi ra,zero,240 - 800002cc: 00000e93 li t4,0 - 800002d0: 00d00193 li gp,13 - 800002d4: 03d09063 bne ra,t4,800002f4 - -00000000800002d8 : - 800002d8: 00ff00b7 lui ra,0xff0 - 800002dc: 0ff0809b addiw ra,ra,255 - 800002e0: 70f0f013 andi zero,ra,1807 - 800002e4: 00000e93 li t4,0 - 800002e8: 00e00193 li gp,14 - 800002ec: 01d01463 bne zero,t4,800002f4 - 800002f0: 00301c63 bne zero,gp,80000308 - -00000000800002f4 : - 800002f4: 0ff0000f fence - 800002f8: 00018063 beqz gp,800002f8 - 800002fc: 00119193 slli gp,gp,0x1 - 80000300: 0011e193 ori gp,gp,1 - 80000304: 00000073 ecall - -0000000080000308 : - 80000308: 0ff0000f fence - 8000030c: 00100193 li gp,1 - 80000310: 00000073 ecall - 80000314: c0001073 unimp - 80000318: 0000 unimp - 8000031a: 0000 unimp - 8000031c: 0000 unimp - 8000031e: 0000 unimp - 80000320: 0000 unimp - 80000322: 0000 unimp - 80000324: 0000 unimp - 80000326: 0000 unimp - 80000328: 0000 unimp - 8000032a: 0000 unimp - 8000032c: 0000 unimp - 8000032e: 0000 unimp - 80000330: 0000 unimp - 80000332: 0000 unimp - 80000334: 0000 unimp - 80000336: 0000 unimp - 80000338: 0000 unimp - 8000033a: 0000 unimp - 8000033c: 0000 unimp - 8000033e: 0000 unimp - 80000340: 0000 unimp - 80000342: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-andi.elf b/test/riscv/tests/rv64ui-p-andi.elf deleted file mode 100644 index 26396d91..00000000 Binary files a/test/riscv/tests/rv64ui-p-andi.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-auipc.dump b/test/riscv/tests/rv64ui-p-auipc.dump deleted file mode 100644 index 0302a06d..00000000 --- a/test/riscv/tests/rv64ui-p-auipc.dump +++ /dev/null @@ -1,125 +0,0 @@ - -rv64ui-p-auipc: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00000013 nop - 80000100: 00002517 auipc a0,0x2 - 80000104: 71c50513 addi a0,a0,1820 # 8000281c <_end+0x81c> - 80000108: 004005ef jal a1,8000010c - 8000010c: 40b50533 sub a0,a0,a1 - 80000110: 00002eb7 lui t4,0x2 - 80000114: 710e8e9b addiw t4,t4,1808 - 80000118: 00200193 li gp,2 - 8000011c: 03d51463 bne a0,t4,80000144 - -0000000080000120 : - 80000120: ffffe517 auipc a0,0xffffe - 80000124: 8fc50513 addi a0,a0,-1796 # 7fffda1c <_start-0x25e4> - 80000128: 004005ef jal a1,8000012c - 8000012c: 40b50533 sub a0,a0,a1 - 80000130: ffffeeb7 lui t4,0xffffe - 80000134: 8f0e8e9b addiw t4,t4,-1808 - 80000138: 00300193 li gp,3 - 8000013c: 01d51463 bne a0,t4,80000144 - 80000140: 00301c63 bne zero,gp,80000158 - -0000000080000144 : - 80000144: 0ff0000f fence - 80000148: 00018063 beqz gp,80000148 - 8000014c: 00119193 slli gp,gp,0x1 - 80000150: 0011e193 ori gp,gp,1 - 80000154: 00000073 ecall - -0000000080000158 : - 80000158: 0ff0000f fence - 8000015c: 00100193 li gp,1 - 80000160: 00000073 ecall - 80000164: c0001073 unimp - 80000168: 0000 unimp - 8000016a: 0000 unimp - 8000016c: 0000 unimp - 8000016e: 0000 unimp - 80000170: 0000 unimp - 80000172: 0000 unimp - 80000174: 0000 unimp - 80000176: 0000 unimp - 80000178: 0000 unimp - 8000017a: 0000 unimp - 8000017c: 0000 unimp - 8000017e: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-auipc.elf b/test/riscv/tests/rv64ui-p-auipc.elf deleted file mode 100644 index 841136eb..00000000 Binary files a/test/riscv/tests/rv64ui-p-auipc.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-beq.dump b/test/riscv/tests/rv64ui-p-beq.dump deleted file mode 100644 index d09e1753..00000000 --- a/test/riscv/tests/rv64ui-p-beq.dump +++ /dev/null @@ -1,325 +0,0 @@ - -rv64ui-p-beq: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00200193 li gp,2 - 80000100: 00000093 li ra,0 - 80000104: 00000113 li sp,0 - 80000108: 00208663 beq ra,sp,80000114 - 8000010c: 2a301863 bne zero,gp,800003bc - 80000110: 00301663 bne zero,gp,8000011c - 80000114: fe208ee3 beq ra,sp,80000110 - 80000118: 2a301263 bne zero,gp,800003bc - -000000008000011c : - 8000011c: 00300193 li gp,3 - 80000120: 00100093 li ra,1 - 80000124: 00100113 li sp,1 - 80000128: 00208663 beq ra,sp,80000134 - 8000012c: 28301863 bne zero,gp,800003bc - 80000130: 00301663 bne zero,gp,8000013c - 80000134: fe208ee3 beq ra,sp,80000130 - 80000138: 28301263 bne zero,gp,800003bc - -000000008000013c : - 8000013c: 00400193 li gp,4 - 80000140: fff00093 li ra,-1 - 80000144: fff00113 li sp,-1 - 80000148: 00208663 beq ra,sp,80000154 - 8000014c: 26301863 bne zero,gp,800003bc - 80000150: 00301663 bne zero,gp,8000015c - 80000154: fe208ee3 beq ra,sp,80000150 - 80000158: 26301263 bne zero,gp,800003bc - -000000008000015c : - 8000015c: 00500193 li gp,5 - 80000160: 00000093 li ra,0 - 80000164: 00100113 li sp,1 - 80000168: 00208463 beq ra,sp,80000170 - 8000016c: 00301463 bne zero,gp,80000174 - 80000170: 24301663 bne zero,gp,800003bc - 80000174: fe208ee3 beq ra,sp,80000170 - -0000000080000178 : - 80000178: 00600193 li gp,6 - 8000017c: 00100093 li ra,1 - 80000180: 00000113 li sp,0 - 80000184: 00208463 beq ra,sp,8000018c - 80000188: 00301463 bne zero,gp,80000190 - 8000018c: 22301863 bne zero,gp,800003bc - 80000190: fe208ee3 beq ra,sp,8000018c - -0000000080000194 : - 80000194: 00700193 li gp,7 - 80000198: fff00093 li ra,-1 - 8000019c: 00100113 li sp,1 - 800001a0: 00208463 beq ra,sp,800001a8 - 800001a4: 00301463 bne zero,gp,800001ac - 800001a8: 20301a63 bne zero,gp,800003bc - 800001ac: fe208ee3 beq ra,sp,800001a8 - -00000000800001b0 : - 800001b0: 00800193 li gp,8 - 800001b4: 00100093 li ra,1 - 800001b8: fff00113 li sp,-1 - 800001bc: 00208463 beq ra,sp,800001c4 - 800001c0: 00301463 bne zero,gp,800001c8 - 800001c4: 1e301c63 bne zero,gp,800003bc - 800001c8: fe208ee3 beq ra,sp,800001c4 - -00000000800001cc : - 800001cc: 00900193 li gp,9 - 800001d0: 00000213 li tp,0 - 800001d4: 00000093 li ra,0 - 800001d8: fff00113 li sp,-1 - 800001dc: 1e208063 beq ra,sp,800003bc - 800001e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800001e4: 00200293 li t0,2 - 800001e8: fe5216e3 bne tp,t0,800001d4 - -00000000800001ec : - 800001ec: 00a00193 li gp,10 - 800001f0: 00000213 li tp,0 - 800001f4: 00000093 li ra,0 - 800001f8: fff00113 li sp,-1 - 800001fc: 00000013 nop - 80000200: 1a208e63 beq ra,sp,800003bc - 80000204: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000208: 00200293 li t0,2 - 8000020c: fe5214e3 bne tp,t0,800001f4 - -0000000080000210 : - 80000210: 00b00193 li gp,11 - 80000214: 00000213 li tp,0 - 80000218: 00000093 li ra,0 - 8000021c: fff00113 li sp,-1 - 80000220: 00000013 nop - 80000224: 00000013 nop - 80000228: 18208a63 beq ra,sp,800003bc - 8000022c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000230: 00200293 li t0,2 - 80000234: fe5212e3 bne tp,t0,80000218 - -0000000080000238 : - 80000238: 00c00193 li gp,12 - 8000023c: 00000213 li tp,0 - 80000240: 00000093 li ra,0 - 80000244: 00000013 nop - 80000248: fff00113 li sp,-1 - 8000024c: 16208863 beq ra,sp,800003bc - 80000250: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000254: 00200293 li t0,2 - 80000258: fe5214e3 bne tp,t0,80000240 - -000000008000025c : - 8000025c: 00d00193 li gp,13 - 80000260: 00000213 li tp,0 - 80000264: 00000093 li ra,0 - 80000268: 00000013 nop - 8000026c: fff00113 li sp,-1 - 80000270: 00000013 nop - 80000274: 14208463 beq ra,sp,800003bc - 80000278: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000027c: 00200293 li t0,2 - 80000280: fe5212e3 bne tp,t0,80000264 - -0000000080000284 : - 80000284: 00e00193 li gp,14 - 80000288: 00000213 li tp,0 - 8000028c: 00000093 li ra,0 - 80000290: 00000013 nop - 80000294: 00000013 nop - 80000298: fff00113 li sp,-1 - 8000029c: 12208063 beq ra,sp,800003bc - 800002a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002a4: 00200293 li t0,2 - 800002a8: fe5212e3 bne tp,t0,8000028c - -00000000800002ac : - 800002ac: 00f00193 li gp,15 - 800002b0: 00000213 li tp,0 - 800002b4: 00000093 li ra,0 - 800002b8: fff00113 li sp,-1 - 800002bc: 10208063 beq ra,sp,800003bc - 800002c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002c4: 00200293 li t0,2 - 800002c8: fe5216e3 bne tp,t0,800002b4 - -00000000800002cc : - 800002cc: 01000193 li gp,16 - 800002d0: 00000213 li tp,0 - 800002d4: 00000093 li ra,0 - 800002d8: fff00113 li sp,-1 - 800002dc: 00000013 nop - 800002e0: 0c208e63 beq ra,sp,800003bc - 800002e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002e8: 00200293 li t0,2 - 800002ec: fe5214e3 bne tp,t0,800002d4 - -00000000800002f0 : - 800002f0: 01100193 li gp,17 - 800002f4: 00000213 li tp,0 - 800002f8: 00000093 li ra,0 - 800002fc: fff00113 li sp,-1 - 80000300: 00000013 nop - 80000304: 00000013 nop - 80000308: 0a208a63 beq ra,sp,800003bc - 8000030c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000310: 00200293 li t0,2 - 80000314: fe5212e3 bne tp,t0,800002f8 - -0000000080000318 : - 80000318: 01200193 li gp,18 - 8000031c: 00000213 li tp,0 - 80000320: 00000093 li ra,0 - 80000324: 00000013 nop - 80000328: fff00113 li sp,-1 - 8000032c: 08208863 beq ra,sp,800003bc - 80000330: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000334: 00200293 li t0,2 - 80000338: fe5214e3 bne tp,t0,80000320 - -000000008000033c : - 8000033c: 01300193 li gp,19 - 80000340: 00000213 li tp,0 - 80000344: 00000093 li ra,0 - 80000348: 00000013 nop - 8000034c: fff00113 li sp,-1 - 80000350: 00000013 nop - 80000354: 06208463 beq ra,sp,800003bc - 80000358: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000035c: 00200293 li t0,2 - 80000360: fe5212e3 bne tp,t0,80000344 - -0000000080000364 : - 80000364: 01400193 li gp,20 - 80000368: 00000213 li tp,0 - 8000036c: 00000093 li ra,0 - 80000370: 00000013 nop - 80000374: 00000013 nop - 80000378: fff00113 li sp,-1 - 8000037c: 04208063 beq ra,sp,800003bc - 80000380: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000384: 00200293 li t0,2 - 80000388: fe5212e3 bne tp,t0,8000036c - -000000008000038c : - 8000038c: 00100093 li ra,1 - 80000390: 00000a63 beqz zero,800003a4 - 80000394: 00108093 addi ra,ra,1 - 80000398: 00108093 addi ra,ra,1 - 8000039c: 00108093 addi ra,ra,1 - 800003a0: 00108093 addi ra,ra,1 - 800003a4: 00108093 addi ra,ra,1 - 800003a8: 00108093 addi ra,ra,1 - 800003ac: 00300e93 li t4,3 - 800003b0: 01500193 li gp,21 - 800003b4: 01d09463 bne ra,t4,800003bc - 800003b8: 00301c63 bne zero,gp,800003d0 - -00000000800003bc : - 800003bc: 0ff0000f fence - 800003c0: 00018063 beqz gp,800003c0 - 800003c4: 00119193 slli gp,gp,0x1 - 800003c8: 0011e193 ori gp,gp,1 - 800003cc: 00000073 ecall - -00000000800003d0 : - 800003d0: 0ff0000f fence - 800003d4: 00100193 li gp,1 - 800003d8: 00000073 ecall - 800003dc: c0001073 unimp - 800003e0: 0000 unimp - 800003e2: 0000 unimp - 800003e4: 0000 unimp - 800003e6: 0000 unimp - 800003e8: 0000 unimp - 800003ea: 0000 unimp - 800003ec: 0000 unimp - 800003ee: 0000 unimp - 800003f0: 0000 unimp - 800003f2: 0000 unimp - 800003f4: 0000 unimp - 800003f6: 0000 unimp - 800003f8: 0000 unimp - 800003fa: 0000 unimp - 800003fc: 0000 unimp - 800003fe: 0000 unimp - 80000400: 0000 unimp - 80000402: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-beq.elf b/test/riscv/tests/rv64ui-p-beq.elf deleted file mode 100644 index 74d63921..00000000 Binary files a/test/riscv/tests/rv64ui-p-beq.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-bge.dump b/test/riscv/tests/rv64ui-p-bge.dump deleted file mode 100644 index bd863ee8..00000000 --- a/test/riscv/tests/rv64ui-p-bge.dump +++ /dev/null @@ -1,339 +0,0 @@ - -rv64ui-p-bge: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00200193 li gp,2 - 80000100: 00000093 li ra,0 - 80000104: 00000113 li sp,0 - 80000108: 0020d663 ble sp,ra,80000114 - 8000010c: 30301863 bne zero,gp,8000041c - 80000110: 00301663 bne zero,gp,8000011c - 80000114: fe20dee3 ble sp,ra,80000110 - 80000118: 30301263 bne zero,gp,8000041c - -000000008000011c : - 8000011c: 00300193 li gp,3 - 80000120: 00100093 li ra,1 - 80000124: 00100113 li sp,1 - 80000128: 0020d663 ble sp,ra,80000134 - 8000012c: 2e301863 bne zero,gp,8000041c - 80000130: 00301663 bne zero,gp,8000013c - 80000134: fe20dee3 ble sp,ra,80000130 - 80000138: 2e301263 bne zero,gp,8000041c - -000000008000013c : - 8000013c: 00400193 li gp,4 - 80000140: fff00093 li ra,-1 - 80000144: fff00113 li sp,-1 - 80000148: 0020d663 ble sp,ra,80000154 - 8000014c: 2c301863 bne zero,gp,8000041c - 80000150: 00301663 bne zero,gp,8000015c - 80000154: fe20dee3 ble sp,ra,80000150 - 80000158: 2c301263 bne zero,gp,8000041c - -000000008000015c : - 8000015c: 00500193 li gp,5 - 80000160: 00100093 li ra,1 - 80000164: 00000113 li sp,0 - 80000168: 0020d663 ble sp,ra,80000174 - 8000016c: 2a301863 bne zero,gp,8000041c - 80000170: 00301663 bne zero,gp,8000017c - 80000174: fe20dee3 ble sp,ra,80000170 - 80000178: 2a301263 bne zero,gp,8000041c - -000000008000017c : - 8000017c: 00600193 li gp,6 - 80000180: 00100093 li ra,1 - 80000184: fff00113 li sp,-1 - 80000188: 0020d663 ble sp,ra,80000194 - 8000018c: 28301863 bne zero,gp,8000041c - 80000190: 00301663 bne zero,gp,8000019c - 80000194: fe20dee3 ble sp,ra,80000190 - 80000198: 28301263 bne zero,gp,8000041c - -000000008000019c : - 8000019c: 00700193 li gp,7 - 800001a0: fff00093 li ra,-1 - 800001a4: ffe00113 li sp,-2 - 800001a8: 0020d663 ble sp,ra,800001b4 - 800001ac: 26301863 bne zero,gp,8000041c - 800001b0: 00301663 bne zero,gp,800001bc - 800001b4: fe20dee3 ble sp,ra,800001b0 - 800001b8: 26301263 bne zero,gp,8000041c - -00000000800001bc : - 800001bc: 00800193 li gp,8 - 800001c0: 00000093 li ra,0 - 800001c4: 00100113 li sp,1 - 800001c8: 0020d463 ble sp,ra,800001d0 - 800001cc: 00301463 bne zero,gp,800001d4 - 800001d0: 24301663 bne zero,gp,8000041c - 800001d4: fe20dee3 ble sp,ra,800001d0 - -00000000800001d8 : - 800001d8: 00900193 li gp,9 - 800001dc: fff00093 li ra,-1 - 800001e0: 00100113 li sp,1 - 800001e4: 0020d463 ble sp,ra,800001ec - 800001e8: 00301463 bne zero,gp,800001f0 - 800001ec: 22301863 bne zero,gp,8000041c - 800001f0: fe20dee3 ble sp,ra,800001ec - -00000000800001f4 : - 800001f4: 00a00193 li gp,10 - 800001f8: ffe00093 li ra,-2 - 800001fc: fff00113 li sp,-1 - 80000200: 0020d463 ble sp,ra,80000208 - 80000204: 00301463 bne zero,gp,8000020c - 80000208: 20301a63 bne zero,gp,8000041c - 8000020c: fe20dee3 ble sp,ra,80000208 - -0000000080000210 : - 80000210: 00b00193 li gp,11 - 80000214: ffe00093 li ra,-2 - 80000218: 00100113 li sp,1 - 8000021c: 0020d463 ble sp,ra,80000224 - 80000220: 00301463 bne zero,gp,80000228 - 80000224: 1e301c63 bne zero,gp,8000041c - 80000228: fe20dee3 ble sp,ra,80000224 - -000000008000022c : - 8000022c: 00c00193 li gp,12 - 80000230: 00000213 li tp,0 - 80000234: fff00093 li ra,-1 - 80000238: 00000113 li sp,0 - 8000023c: 1e20d063 ble sp,ra,8000041c - 80000240: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000244: 00200293 li t0,2 - 80000248: fe5216e3 bne tp,t0,80000234 - -000000008000024c : - 8000024c: 00d00193 li gp,13 - 80000250: 00000213 li tp,0 - 80000254: fff00093 li ra,-1 - 80000258: 00000113 li sp,0 - 8000025c: 00000013 nop - 80000260: 1a20de63 ble sp,ra,8000041c - 80000264: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000268: 00200293 li t0,2 - 8000026c: fe5214e3 bne tp,t0,80000254 - -0000000080000270 : - 80000270: 00e00193 li gp,14 - 80000274: 00000213 li tp,0 - 80000278: fff00093 li ra,-1 - 8000027c: 00000113 li sp,0 - 80000280: 00000013 nop - 80000284: 00000013 nop - 80000288: 1820da63 ble sp,ra,8000041c - 8000028c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000290: 00200293 li t0,2 - 80000294: fe5212e3 bne tp,t0,80000278 - -0000000080000298 : - 80000298: 00f00193 li gp,15 - 8000029c: 00000213 li tp,0 - 800002a0: fff00093 li ra,-1 - 800002a4: 00000013 nop - 800002a8: 00000113 li sp,0 - 800002ac: 1620d863 ble sp,ra,8000041c - 800002b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002b4: 00200293 li t0,2 - 800002b8: fe5214e3 bne tp,t0,800002a0 - -00000000800002bc : - 800002bc: 01000193 li gp,16 - 800002c0: 00000213 li tp,0 - 800002c4: fff00093 li ra,-1 - 800002c8: 00000013 nop - 800002cc: 00000113 li sp,0 - 800002d0: 00000013 nop - 800002d4: 1420d463 ble sp,ra,8000041c - 800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002dc: 00200293 li t0,2 - 800002e0: fe5212e3 bne tp,t0,800002c4 - -00000000800002e4 : - 800002e4: 01100193 li gp,17 - 800002e8: 00000213 li tp,0 - 800002ec: fff00093 li ra,-1 - 800002f0: 00000013 nop - 800002f4: 00000013 nop - 800002f8: 00000113 li sp,0 - 800002fc: 1220d063 ble sp,ra,8000041c - 80000300: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000304: 00200293 li t0,2 - 80000308: fe5212e3 bne tp,t0,800002ec - -000000008000030c : - 8000030c: 01200193 li gp,18 - 80000310: 00000213 li tp,0 - 80000314: fff00093 li ra,-1 - 80000318: 00000113 li sp,0 - 8000031c: 1020d063 ble sp,ra,8000041c - 80000320: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000324: 00200293 li t0,2 - 80000328: fe5216e3 bne tp,t0,80000314 - -000000008000032c : - 8000032c: 01300193 li gp,19 - 80000330: 00000213 li tp,0 - 80000334: fff00093 li ra,-1 - 80000338: 00000113 li sp,0 - 8000033c: 00000013 nop - 80000340: 0c20de63 ble sp,ra,8000041c - 80000344: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000348: 00200293 li t0,2 - 8000034c: fe5214e3 bne tp,t0,80000334 - -0000000080000350 : - 80000350: 01400193 li gp,20 - 80000354: 00000213 li tp,0 - 80000358: fff00093 li ra,-1 - 8000035c: 00000113 li sp,0 - 80000360: 00000013 nop - 80000364: 00000013 nop - 80000368: 0a20da63 ble sp,ra,8000041c - 8000036c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000370: 00200293 li t0,2 - 80000374: fe5212e3 bne tp,t0,80000358 - -0000000080000378 : - 80000378: 01500193 li gp,21 - 8000037c: 00000213 li tp,0 - 80000380: fff00093 li ra,-1 - 80000384: 00000013 nop - 80000388: 00000113 li sp,0 - 8000038c: 0820d863 ble sp,ra,8000041c - 80000390: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000394: 00200293 li t0,2 - 80000398: fe5214e3 bne tp,t0,80000380 - -000000008000039c : - 8000039c: 01600193 li gp,22 - 800003a0: 00000213 li tp,0 - 800003a4: fff00093 li ra,-1 - 800003a8: 00000013 nop - 800003ac: 00000113 li sp,0 - 800003b0: 00000013 nop - 800003b4: 0620d463 ble sp,ra,8000041c - 800003b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003bc: 00200293 li t0,2 - 800003c0: fe5212e3 bne tp,t0,800003a4 - -00000000800003c4 : - 800003c4: 01700193 li gp,23 - 800003c8: 00000213 li tp,0 - 800003cc: fff00093 li ra,-1 - 800003d0: 00000013 nop - 800003d4: 00000013 nop - 800003d8: 00000113 li sp,0 - 800003dc: 0420d063 ble sp,ra,8000041c - 800003e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003e4: 00200293 li t0,2 - 800003e8: fe5212e3 bne tp,t0,800003cc - -00000000800003ec : - 800003ec: 00100093 li ra,1 - 800003f0: 0000da63 bgez ra,80000404 - 800003f4: 00108093 addi ra,ra,1 - 800003f8: 00108093 addi ra,ra,1 - 800003fc: 00108093 addi ra,ra,1 - 80000400: 00108093 addi ra,ra,1 - 80000404: 00108093 addi ra,ra,1 - 80000408: 00108093 addi ra,ra,1 - 8000040c: 00300e93 li t4,3 - 80000410: 01800193 li gp,24 - 80000414: 01d09463 bne ra,t4,8000041c - 80000418: 00301c63 bne zero,gp,80000430 - -000000008000041c : - 8000041c: 0ff0000f fence - 80000420: 00018063 beqz gp,80000420 - 80000424: 00119193 slli gp,gp,0x1 - 80000428: 0011e193 ori gp,gp,1 - 8000042c: 00000073 ecall - -0000000080000430 : - 80000430: 0ff0000f fence - 80000434: 00100193 li gp,1 - 80000438: 00000073 ecall - 8000043c: c0001073 unimp - 80000440: 0000 unimp - 80000442: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-bge.elf b/test/riscv/tests/rv64ui-p-bge.elf deleted file mode 100644 index 6a5c2ef2..00000000 Binary files a/test/riscv/tests/rv64ui-p-bge.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-bgeu.dump b/test/riscv/tests/rv64ui-p-bgeu.dump deleted file mode 100644 index c773c7de..00000000 --- a/test/riscv/tests/rv64ui-p-bgeu.dump +++ /dev/null @@ -1,413 +0,0 @@ - -rv64ui-p-bgeu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00200193 li gp,2 - 80000100: 00000093 li ra,0 - 80000104: 00000113 li sp,0 - 80000108: 0020f663 bleu sp,ra,80000114 - 8000010c: 3e301463 bne zero,gp,800004f4 - 80000110: 00301663 bne zero,gp,8000011c - 80000114: fe20fee3 bleu sp,ra,80000110 - 80000118: 3c301e63 bne zero,gp,800004f4 - -000000008000011c : - 8000011c: 00300193 li gp,3 - 80000120: 00100093 li ra,1 - 80000124: 00100113 li sp,1 - 80000128: 0020f663 bleu sp,ra,80000134 - 8000012c: 3c301463 bne zero,gp,800004f4 - 80000130: 00301663 bne zero,gp,8000013c - 80000134: fe20fee3 bleu sp,ra,80000130 - 80000138: 3a301e63 bne zero,gp,800004f4 - -000000008000013c : - 8000013c: 00400193 li gp,4 - 80000140: 0010009b addiw ra,zero,1 - 80000144: 02009093 slli ra,ra,0x20 - 80000148: fff08093 addi ra,ra,-1 - 8000014c: 0010011b addiw sp,zero,1 - 80000150: 02011113 slli sp,sp,0x20 - 80000154: fff10113 addi sp,sp,-1 - 80000158: 0020f663 bleu sp,ra,80000164 - 8000015c: 38301c63 bne zero,gp,800004f4 - 80000160: 00301663 bne zero,gp,8000016c - 80000164: fe20fee3 bleu sp,ra,80000160 - 80000168: 38301663 bne zero,gp,800004f4 - -000000008000016c : - 8000016c: 00500193 li gp,5 - 80000170: 00100093 li ra,1 - 80000174: 00000113 li sp,0 - 80000178: 0020f663 bleu sp,ra,80000184 - 8000017c: 36301c63 bne zero,gp,800004f4 - 80000180: 00301663 bne zero,gp,8000018c - 80000184: fe20fee3 bleu sp,ra,80000180 - 80000188: 36301663 bne zero,gp,800004f4 - -000000008000018c : - 8000018c: 00600193 li gp,6 - 80000190: 0010009b addiw ra,zero,1 - 80000194: 02009093 slli ra,ra,0x20 - 80000198: fff08093 addi ra,ra,-1 - 8000019c: 0010011b addiw sp,zero,1 - 800001a0: 02011113 slli sp,sp,0x20 - 800001a4: ffe10113 addi sp,sp,-2 - 800001a8: 0020f663 bleu sp,ra,800001b4 - 800001ac: 34301463 bne zero,gp,800004f4 - 800001b0: 00301663 bne zero,gp,800001bc - 800001b4: fe20fee3 bleu sp,ra,800001b0 - 800001b8: 32301e63 bne zero,gp,800004f4 - -00000000800001bc : - 800001bc: 00700193 li gp,7 - 800001c0: 0010009b addiw ra,zero,1 - 800001c4: 02009093 slli ra,ra,0x20 - 800001c8: fff08093 addi ra,ra,-1 - 800001cc: 00000113 li sp,0 - 800001d0: 0020f663 bleu sp,ra,800001dc - 800001d4: 32301063 bne zero,gp,800004f4 - 800001d8: 00301663 bne zero,gp,800001e4 - 800001dc: fe20fee3 bleu sp,ra,800001d8 - 800001e0: 30301a63 bne zero,gp,800004f4 - -00000000800001e4 : - 800001e4: 00800193 li gp,8 - 800001e8: 00000093 li ra,0 - 800001ec: 00100113 li sp,1 - 800001f0: 0020f463 bleu sp,ra,800001f8 - 800001f4: 00301463 bne zero,gp,800001fc - 800001f8: 2e301e63 bne zero,gp,800004f4 - 800001fc: fe20fee3 bleu sp,ra,800001f8 - -0000000080000200 : - 80000200: 00900193 li gp,9 - 80000204: 0010009b addiw ra,zero,1 - 80000208: 02009093 slli ra,ra,0x20 - 8000020c: ffe08093 addi ra,ra,-2 - 80000210: 0010011b addiw sp,zero,1 - 80000214: 02011113 slli sp,sp,0x20 - 80000218: fff10113 addi sp,sp,-1 - 8000021c: 0020f463 bleu sp,ra,80000224 - 80000220: 00301463 bne zero,gp,80000228 - 80000224: 2c301863 bne zero,gp,800004f4 - 80000228: fe20fee3 bleu sp,ra,80000224 - -000000008000022c : - 8000022c: 00a00193 li gp,10 - 80000230: 00000093 li ra,0 - 80000234: 0010011b addiw sp,zero,1 - 80000238: 02011113 slli sp,sp,0x20 - 8000023c: fff10113 addi sp,sp,-1 - 80000240: 0020f463 bleu sp,ra,80000248 - 80000244: 00301463 bne zero,gp,8000024c - 80000248: 2a301663 bne zero,gp,800004f4 - 8000024c: fe20fee3 bleu sp,ra,80000248 - -0000000080000250 : - 80000250: 00b00193 li gp,11 - 80000254: 800000b7 lui ra,0x80000 - 80000258: fff0809b addiw ra,ra,-1 - 8000025c: 0010011b addiw sp,zero,1 - 80000260: 01f11113 slli sp,sp,0x1f - 80000264: 0020f463 bleu sp,ra,8000026c - 80000268: 00301463 bne zero,gp,80000270 - 8000026c: 28301463 bne zero,gp,800004f4 - 80000270: fe20fee3 bleu sp,ra,8000026c - -0000000080000274 : - 80000274: 00c00193 li gp,12 - 80000278: 00000213 li tp,0 - 8000027c: 00f0009b addiw ra,zero,15 - 80000280: 01c09093 slli ra,ra,0x1c - 80000284: fff08093 addi ra,ra,-1 # ffffffff7fffffff <_end+0xfffffffeffffdfff> - 80000288: 00f0011b addiw sp,zero,15 - 8000028c: 01c11113 slli sp,sp,0x1c - 80000290: 2620f263 bleu sp,ra,800004f4 - 80000294: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000298: 00200293 li t0,2 - 8000029c: fe5210e3 bne tp,t0,8000027c - -00000000800002a0 : - 800002a0: 00d00193 li gp,13 - 800002a4: 00000213 li tp,0 - 800002a8: 00f0009b addiw ra,zero,15 - 800002ac: 01c09093 slli ra,ra,0x1c - 800002b0: fff08093 addi ra,ra,-1 - 800002b4: 00f0011b addiw sp,zero,15 - 800002b8: 01c11113 slli sp,sp,0x1c - 800002bc: 00000013 nop - 800002c0: 2220fa63 bleu sp,ra,800004f4 - 800002c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002c8: 00200293 li t0,2 - 800002cc: fc521ee3 bne tp,t0,800002a8 - -00000000800002d0 : - 800002d0: 00e00193 li gp,14 - 800002d4: 00000213 li tp,0 - 800002d8: 00f0009b addiw ra,zero,15 - 800002dc: 01c09093 slli ra,ra,0x1c - 800002e0: fff08093 addi ra,ra,-1 - 800002e4: 00f0011b addiw sp,zero,15 - 800002e8: 01c11113 slli sp,sp,0x1c - 800002ec: 00000013 nop - 800002f0: 00000013 nop - 800002f4: 2020f063 bleu sp,ra,800004f4 - 800002f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002fc: 00200293 li t0,2 - 80000300: fc521ce3 bne tp,t0,800002d8 - -0000000080000304 : - 80000304: 00f00193 li gp,15 - 80000308: 00000213 li tp,0 - 8000030c: 00f0009b addiw ra,zero,15 - 80000310: 01c09093 slli ra,ra,0x1c - 80000314: fff08093 addi ra,ra,-1 - 80000318: 00000013 nop - 8000031c: 00f0011b addiw sp,zero,15 - 80000320: 01c11113 slli sp,sp,0x1c - 80000324: 1c20f863 bleu sp,ra,800004f4 - 80000328: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000032c: 00200293 li t0,2 - 80000330: fc521ee3 bne tp,t0,8000030c - -0000000080000334 : - 80000334: 01000193 li gp,16 - 80000338: 00000213 li tp,0 - 8000033c: 00f0009b addiw ra,zero,15 - 80000340: 01c09093 slli ra,ra,0x1c - 80000344: fff08093 addi ra,ra,-1 - 80000348: 00000013 nop - 8000034c: 00f0011b addiw sp,zero,15 - 80000350: 01c11113 slli sp,sp,0x1c - 80000354: 00000013 nop - 80000358: 1820fe63 bleu sp,ra,800004f4 - 8000035c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000360: 00200293 li t0,2 - 80000364: fc521ce3 bne tp,t0,8000033c - -0000000080000368 : - 80000368: 01100193 li gp,17 - 8000036c: 00000213 li tp,0 - 80000370: 00f0009b addiw ra,zero,15 - 80000374: 01c09093 slli ra,ra,0x1c - 80000378: fff08093 addi ra,ra,-1 - 8000037c: 00000013 nop - 80000380: 00000013 nop - 80000384: 00f0011b addiw sp,zero,15 - 80000388: 01c11113 slli sp,sp,0x1c - 8000038c: 1620f463 bleu sp,ra,800004f4 - 80000390: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000394: 00200293 li t0,2 - 80000398: fc521ce3 bne tp,t0,80000370 - -000000008000039c : - 8000039c: 01200193 li gp,18 - 800003a0: 00000213 li tp,0 - 800003a4: 00f0009b addiw ra,zero,15 - 800003a8: 01c09093 slli ra,ra,0x1c - 800003ac: fff08093 addi ra,ra,-1 - 800003b0: 00f0011b addiw sp,zero,15 - 800003b4: 01c11113 slli sp,sp,0x1c - 800003b8: 1220fe63 bleu sp,ra,800004f4 - 800003bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003c0: 00200293 li t0,2 - 800003c4: fe5210e3 bne tp,t0,800003a4 - -00000000800003c8 : - 800003c8: 01300193 li gp,19 - 800003cc: 00000213 li tp,0 - 800003d0: 00f0009b addiw ra,zero,15 - 800003d4: 01c09093 slli ra,ra,0x1c - 800003d8: fff08093 addi ra,ra,-1 - 800003dc: 00f0011b addiw sp,zero,15 - 800003e0: 01c11113 slli sp,sp,0x1c - 800003e4: 00000013 nop - 800003e8: 1020f663 bleu sp,ra,800004f4 - 800003ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003f0: 00200293 li t0,2 - 800003f4: fc521ee3 bne tp,t0,800003d0 - -00000000800003f8 : - 800003f8: 01400193 li gp,20 - 800003fc: 00000213 li tp,0 - 80000400: 00f0009b addiw ra,zero,15 - 80000404: 01c09093 slli ra,ra,0x1c - 80000408: fff08093 addi ra,ra,-1 - 8000040c: 00f0011b addiw sp,zero,15 - 80000410: 01c11113 slli sp,sp,0x1c - 80000414: 00000013 nop - 80000418: 00000013 nop - 8000041c: 0c20fc63 bleu sp,ra,800004f4 - 80000420: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000424: 00200293 li t0,2 - 80000428: fc521ce3 bne tp,t0,80000400 - -000000008000042c : - 8000042c: 01500193 li gp,21 - 80000430: 00000213 li tp,0 - 80000434: 00f0009b addiw ra,zero,15 - 80000438: 01c09093 slli ra,ra,0x1c - 8000043c: fff08093 addi ra,ra,-1 - 80000440: 00000013 nop - 80000444: 00f0011b addiw sp,zero,15 - 80000448: 01c11113 slli sp,sp,0x1c - 8000044c: 0a20f463 bleu sp,ra,800004f4 - 80000450: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000454: 00200293 li t0,2 - 80000458: fc521ee3 bne tp,t0,80000434 - -000000008000045c : - 8000045c: 01600193 li gp,22 - 80000460: 00000213 li tp,0 - 80000464: 00f0009b addiw ra,zero,15 - 80000468: 01c09093 slli ra,ra,0x1c - 8000046c: fff08093 addi ra,ra,-1 - 80000470: 00000013 nop - 80000474: 00f0011b addiw sp,zero,15 - 80000478: 01c11113 slli sp,sp,0x1c - 8000047c: 00000013 nop - 80000480: 0620fa63 bleu sp,ra,800004f4 - 80000484: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000488: 00200293 li t0,2 - 8000048c: fc521ce3 bne tp,t0,80000464 - -0000000080000490 : - 80000490: 01700193 li gp,23 - 80000494: 00000213 li tp,0 - 80000498: 00f0009b addiw ra,zero,15 - 8000049c: 01c09093 slli ra,ra,0x1c - 800004a0: fff08093 addi ra,ra,-1 - 800004a4: 00000013 nop - 800004a8: 00000013 nop - 800004ac: 00f0011b addiw sp,zero,15 - 800004b0: 01c11113 slli sp,sp,0x1c - 800004b4: 0420f063 bleu sp,ra,800004f4 - 800004b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004bc: 00200293 li t0,2 - 800004c0: fc521ce3 bne tp,t0,80000498 - -00000000800004c4 : - 800004c4: 00100093 li ra,1 - 800004c8: 0000fa63 bleu zero,ra,800004dc - 800004cc: 00108093 addi ra,ra,1 - 800004d0: 00108093 addi ra,ra,1 - 800004d4: 00108093 addi ra,ra,1 - 800004d8: 00108093 addi ra,ra,1 - 800004dc: 00108093 addi ra,ra,1 - 800004e0: 00108093 addi ra,ra,1 - 800004e4: 00300e93 li t4,3 - 800004e8: 01800193 li gp,24 - 800004ec: 01d09463 bne ra,t4,800004f4 - 800004f0: 00301c63 bne zero,gp,80000508 - -00000000800004f4 : - 800004f4: 0ff0000f fence - 800004f8: 00018063 beqz gp,800004f8 - 800004fc: 00119193 slli gp,gp,0x1 - 80000500: 0011e193 ori gp,gp,1 - 80000504: 00000073 ecall - -0000000080000508 : - 80000508: 0ff0000f fence - 8000050c: 00100193 li gp,1 - 80000510: 00000073 ecall - 80000514: c0001073 unimp - 80000518: 0000 unimp - 8000051a: 0000 unimp - 8000051c: 0000 unimp - 8000051e: 0000 unimp - 80000520: 0000 unimp - 80000522: 0000 unimp - 80000524: 0000 unimp - 80000526: 0000 unimp - 80000528: 0000 unimp - 8000052a: 0000 unimp - 8000052c: 0000 unimp - 8000052e: 0000 unimp - 80000530: 0000 unimp - 80000532: 0000 unimp - 80000534: 0000 unimp - 80000536: 0000 unimp - 80000538: 0000 unimp - 8000053a: 0000 unimp - 8000053c: 0000 unimp - 8000053e: 0000 unimp - 80000540: 0000 unimp - 80000542: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-bgeu.elf b/test/riscv/tests/rv64ui-p-bgeu.elf deleted file mode 100644 index a1ae7fea..00000000 Binary files a/test/riscv/tests/rv64ui-p-bgeu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-blt.dump b/test/riscv/tests/rv64ui-p-blt.dump deleted file mode 100644 index 3e6b518b..00000000 --- a/test/riscv/tests/rv64ui-p-blt.dump +++ /dev/null @@ -1,325 +0,0 @@ - -rv64ui-p-blt: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00200193 li gp,2 - 80000100: 00000093 li ra,0 - 80000104: 00100113 li sp,1 - 80000108: 0020c663 blt ra,sp,80000114 - 8000010c: 2a301863 bne zero,gp,800003bc - 80000110: 00301663 bne zero,gp,8000011c - 80000114: fe20cee3 blt ra,sp,80000110 - 80000118: 2a301263 bne zero,gp,800003bc - -000000008000011c : - 8000011c: 00300193 li gp,3 - 80000120: fff00093 li ra,-1 - 80000124: 00100113 li sp,1 - 80000128: 0020c663 blt ra,sp,80000134 - 8000012c: 28301863 bne zero,gp,800003bc - 80000130: 00301663 bne zero,gp,8000013c - 80000134: fe20cee3 blt ra,sp,80000130 - 80000138: 28301263 bne zero,gp,800003bc - -000000008000013c : - 8000013c: 00400193 li gp,4 - 80000140: ffe00093 li ra,-2 - 80000144: fff00113 li sp,-1 - 80000148: 0020c663 blt ra,sp,80000154 - 8000014c: 26301863 bne zero,gp,800003bc - 80000150: 00301663 bne zero,gp,8000015c - 80000154: fe20cee3 blt ra,sp,80000150 - 80000158: 26301263 bne zero,gp,800003bc - -000000008000015c : - 8000015c: 00500193 li gp,5 - 80000160: 00100093 li ra,1 - 80000164: 00000113 li sp,0 - 80000168: 0020c463 blt ra,sp,80000170 - 8000016c: 00301463 bne zero,gp,80000174 - 80000170: 24301663 bne zero,gp,800003bc - 80000174: fe20cee3 blt ra,sp,80000170 - -0000000080000178 : - 80000178: 00600193 li gp,6 - 8000017c: 00100093 li ra,1 - 80000180: fff00113 li sp,-1 - 80000184: 0020c463 blt ra,sp,8000018c - 80000188: 00301463 bne zero,gp,80000190 - 8000018c: 22301863 bne zero,gp,800003bc - 80000190: fe20cee3 blt ra,sp,8000018c - -0000000080000194 : - 80000194: 00700193 li gp,7 - 80000198: fff00093 li ra,-1 - 8000019c: ffe00113 li sp,-2 - 800001a0: 0020c463 blt ra,sp,800001a8 - 800001a4: 00301463 bne zero,gp,800001ac - 800001a8: 20301a63 bne zero,gp,800003bc - 800001ac: fe20cee3 blt ra,sp,800001a8 - -00000000800001b0 : - 800001b0: 00800193 li gp,8 - 800001b4: 00100093 li ra,1 - 800001b8: ffe00113 li sp,-2 - 800001bc: 0020c463 blt ra,sp,800001c4 - 800001c0: 00301463 bne zero,gp,800001c8 - 800001c4: 1e301c63 bne zero,gp,800003bc - 800001c8: fe20cee3 blt ra,sp,800001c4 - -00000000800001cc : - 800001cc: 00900193 li gp,9 - 800001d0: 00000213 li tp,0 - 800001d4: 00000093 li ra,0 - 800001d8: fff00113 li sp,-1 - 800001dc: 1e20c063 blt ra,sp,800003bc - 800001e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800001e4: 00200293 li t0,2 - 800001e8: fe5216e3 bne tp,t0,800001d4 - -00000000800001ec : - 800001ec: 00a00193 li gp,10 - 800001f0: 00000213 li tp,0 - 800001f4: 00000093 li ra,0 - 800001f8: fff00113 li sp,-1 - 800001fc: 00000013 nop - 80000200: 1a20ce63 blt ra,sp,800003bc - 80000204: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000208: 00200293 li t0,2 - 8000020c: fe5214e3 bne tp,t0,800001f4 - -0000000080000210 : - 80000210: 00b00193 li gp,11 - 80000214: 00000213 li tp,0 - 80000218: 00000093 li ra,0 - 8000021c: fff00113 li sp,-1 - 80000220: 00000013 nop - 80000224: 00000013 nop - 80000228: 1820ca63 blt ra,sp,800003bc - 8000022c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000230: 00200293 li t0,2 - 80000234: fe5212e3 bne tp,t0,80000218 - -0000000080000238 : - 80000238: 00c00193 li gp,12 - 8000023c: 00000213 li tp,0 - 80000240: 00000093 li ra,0 - 80000244: 00000013 nop - 80000248: fff00113 li sp,-1 - 8000024c: 1620c863 blt ra,sp,800003bc - 80000250: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000254: 00200293 li t0,2 - 80000258: fe5214e3 bne tp,t0,80000240 - -000000008000025c : - 8000025c: 00d00193 li gp,13 - 80000260: 00000213 li tp,0 - 80000264: 00000093 li ra,0 - 80000268: 00000013 nop - 8000026c: fff00113 li sp,-1 - 80000270: 00000013 nop - 80000274: 1420c463 blt ra,sp,800003bc - 80000278: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000027c: 00200293 li t0,2 - 80000280: fe5212e3 bne tp,t0,80000264 - -0000000080000284 : - 80000284: 00e00193 li gp,14 - 80000288: 00000213 li tp,0 - 8000028c: 00000093 li ra,0 - 80000290: 00000013 nop - 80000294: 00000013 nop - 80000298: fff00113 li sp,-1 - 8000029c: 1220c063 blt ra,sp,800003bc - 800002a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002a4: 00200293 li t0,2 - 800002a8: fe5212e3 bne tp,t0,8000028c - -00000000800002ac : - 800002ac: 00f00193 li gp,15 - 800002b0: 00000213 li tp,0 - 800002b4: 00000093 li ra,0 - 800002b8: fff00113 li sp,-1 - 800002bc: 1020c063 blt ra,sp,800003bc - 800002c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002c4: 00200293 li t0,2 - 800002c8: fe5216e3 bne tp,t0,800002b4 - -00000000800002cc : - 800002cc: 01000193 li gp,16 - 800002d0: 00000213 li tp,0 - 800002d4: 00000093 li ra,0 - 800002d8: fff00113 li sp,-1 - 800002dc: 00000013 nop - 800002e0: 0c20ce63 blt ra,sp,800003bc - 800002e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002e8: 00200293 li t0,2 - 800002ec: fe5214e3 bne tp,t0,800002d4 - -00000000800002f0 : - 800002f0: 01100193 li gp,17 - 800002f4: 00000213 li tp,0 - 800002f8: 00000093 li ra,0 - 800002fc: fff00113 li sp,-1 - 80000300: 00000013 nop - 80000304: 00000013 nop - 80000308: 0a20ca63 blt ra,sp,800003bc - 8000030c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000310: 00200293 li t0,2 - 80000314: fe5212e3 bne tp,t0,800002f8 - -0000000080000318 : - 80000318: 01200193 li gp,18 - 8000031c: 00000213 li tp,0 - 80000320: 00000093 li ra,0 - 80000324: 00000013 nop - 80000328: fff00113 li sp,-1 - 8000032c: 0820c863 blt ra,sp,800003bc - 80000330: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000334: 00200293 li t0,2 - 80000338: fe5214e3 bne tp,t0,80000320 - -000000008000033c : - 8000033c: 01300193 li gp,19 - 80000340: 00000213 li tp,0 - 80000344: 00000093 li ra,0 - 80000348: 00000013 nop - 8000034c: fff00113 li sp,-1 - 80000350: 00000013 nop - 80000354: 0620c463 blt ra,sp,800003bc - 80000358: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000035c: 00200293 li t0,2 - 80000360: fe5212e3 bne tp,t0,80000344 - -0000000080000364 : - 80000364: 01400193 li gp,20 - 80000368: 00000213 li tp,0 - 8000036c: 00000093 li ra,0 - 80000370: 00000013 nop - 80000374: 00000013 nop - 80000378: fff00113 li sp,-1 - 8000037c: 0420c063 blt ra,sp,800003bc - 80000380: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000384: 00200293 li t0,2 - 80000388: fe5212e3 bne tp,t0,8000036c - -000000008000038c : - 8000038c: 00100093 li ra,1 - 80000390: 00104a63 bgtz ra,800003a4 - 80000394: 00108093 addi ra,ra,1 - 80000398: 00108093 addi ra,ra,1 - 8000039c: 00108093 addi ra,ra,1 - 800003a0: 00108093 addi ra,ra,1 - 800003a4: 00108093 addi ra,ra,1 - 800003a8: 00108093 addi ra,ra,1 - 800003ac: 00300e93 li t4,3 - 800003b0: 01500193 li gp,21 - 800003b4: 01d09463 bne ra,t4,800003bc - 800003b8: 00301c63 bne zero,gp,800003d0 - -00000000800003bc : - 800003bc: 0ff0000f fence - 800003c0: 00018063 beqz gp,800003c0 - 800003c4: 00119193 slli gp,gp,0x1 - 800003c8: 0011e193 ori gp,gp,1 - 800003cc: 00000073 ecall - -00000000800003d0 : - 800003d0: 0ff0000f fence - 800003d4: 00100193 li gp,1 - 800003d8: 00000073 ecall - 800003dc: c0001073 unimp - 800003e0: 0000 unimp - 800003e2: 0000 unimp - 800003e4: 0000 unimp - 800003e6: 0000 unimp - 800003e8: 0000 unimp - 800003ea: 0000 unimp - 800003ec: 0000 unimp - 800003ee: 0000 unimp - 800003f0: 0000 unimp - 800003f2: 0000 unimp - 800003f4: 0000 unimp - 800003f6: 0000 unimp - 800003f8: 0000 unimp - 800003fa: 0000 unimp - 800003fc: 0000 unimp - 800003fe: 0000 unimp - 80000400: 0000 unimp - 80000402: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-blt.elf b/test/riscv/tests/rv64ui-p-blt.elf deleted file mode 100644 index 53f06fa5..00000000 Binary files a/test/riscv/tests/rv64ui-p-blt.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-bltu.dump b/test/riscv/tests/rv64ui-p-bltu.dump deleted file mode 100644 index ec344211..00000000 --- a/test/riscv/tests/rv64ui-p-bltu.dump +++ /dev/null @@ -1,371 +0,0 @@ - -rv64ui-p-bltu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00200193 li gp,2 - 80000100: 00000093 li ra,0 - 80000104: 00100113 li sp,1 - 80000108: 0020e663 bltu ra,sp,80000114 - 8000010c: 36301c63 bne zero,gp,80000484 - 80000110: 00301663 bne zero,gp,8000011c - 80000114: fe20eee3 bltu ra,sp,80000110 - 80000118: 36301663 bne zero,gp,80000484 - -000000008000011c : - 8000011c: 00300193 li gp,3 - 80000120: 0010009b addiw ra,zero,1 - 80000124: 02009093 slli ra,ra,0x20 - 80000128: ffe08093 addi ra,ra,-2 - 8000012c: 0010011b addiw sp,zero,1 - 80000130: 02011113 slli sp,sp,0x20 - 80000134: fff10113 addi sp,sp,-1 - 80000138: 0020e663 bltu ra,sp,80000144 - 8000013c: 34301463 bne zero,gp,80000484 - 80000140: 00301663 bne zero,gp,8000014c - 80000144: fe20eee3 bltu ra,sp,80000140 - 80000148: 32301e63 bne zero,gp,80000484 - -000000008000014c : - 8000014c: 00400193 li gp,4 - 80000150: 00000093 li ra,0 - 80000154: 0010011b addiw sp,zero,1 - 80000158: 02011113 slli sp,sp,0x20 - 8000015c: fff10113 addi sp,sp,-1 - 80000160: 0020e663 bltu ra,sp,8000016c - 80000164: 32301063 bne zero,gp,80000484 - 80000168: 00301663 bne zero,gp,80000174 - 8000016c: fe20eee3 bltu ra,sp,80000168 - 80000170: 30301a63 bne zero,gp,80000484 - -0000000080000174 : - 80000174: 00500193 li gp,5 - 80000178: 00100093 li ra,1 - 8000017c: 00000113 li sp,0 - 80000180: 0020e463 bltu ra,sp,80000188 - 80000184: 00301463 bne zero,gp,8000018c - 80000188: 2e301e63 bne zero,gp,80000484 - 8000018c: fe20eee3 bltu ra,sp,80000188 - -0000000080000190 : - 80000190: 00600193 li gp,6 - 80000194: 0010009b addiw ra,zero,1 - 80000198: 02009093 slli ra,ra,0x20 - 8000019c: fff08093 addi ra,ra,-1 - 800001a0: 0010011b addiw sp,zero,1 - 800001a4: 02011113 slli sp,sp,0x20 - 800001a8: ffe10113 addi sp,sp,-2 - 800001ac: 0020e463 bltu ra,sp,800001b4 - 800001b0: 00301463 bne zero,gp,800001b8 - 800001b4: 2c301863 bne zero,gp,80000484 - 800001b8: fe20eee3 bltu ra,sp,800001b4 - -00000000800001bc : - 800001bc: 00700193 li gp,7 - 800001c0: 0010009b addiw ra,zero,1 - 800001c4: 02009093 slli ra,ra,0x20 - 800001c8: fff08093 addi ra,ra,-1 - 800001cc: 00000113 li sp,0 - 800001d0: 0020e463 bltu ra,sp,800001d8 - 800001d4: 00301463 bne zero,gp,800001dc - 800001d8: 2a301663 bne zero,gp,80000484 - 800001dc: fe20eee3 bltu ra,sp,800001d8 - -00000000800001e0 : - 800001e0: 00800193 li gp,8 - 800001e4: 0010009b addiw ra,zero,1 - 800001e8: 01f09093 slli ra,ra,0x1f - 800001ec: 80000137 lui sp,0x80000 - 800001f0: fff1011b addiw sp,sp,-1 - 800001f4: 0020e463 bltu ra,sp,800001fc - 800001f8: 00301463 bne zero,gp,80000200 - 800001fc: 28301463 bne zero,gp,80000484 - 80000200: fe20eee3 bltu ra,sp,800001fc - -0000000080000204 : - 80000204: 00900193 li gp,9 - 80000208: 00000213 li tp,0 - 8000020c: 00f0009b addiw ra,zero,15 - 80000210: 01c09093 slli ra,ra,0x1c - 80000214: 00f0011b addiw sp,zero,15 - 80000218: 01c11113 slli sp,sp,0x1c - 8000021c: fff10113 addi sp,sp,-1 # ffffffff7fffffff <_end+0xfffffffeffffdfff> - 80000220: 2620e263 bltu ra,sp,80000484 - 80000224: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000228: 00200293 li t0,2 - 8000022c: fe5210e3 bne tp,t0,8000020c - -0000000080000230 : - 80000230: 00a00193 li gp,10 - 80000234: 00000213 li tp,0 - 80000238: 00f0009b addiw ra,zero,15 - 8000023c: 01c09093 slli ra,ra,0x1c - 80000240: 00f0011b addiw sp,zero,15 - 80000244: 01c11113 slli sp,sp,0x1c - 80000248: fff10113 addi sp,sp,-1 - 8000024c: 00000013 nop - 80000250: 2220ea63 bltu ra,sp,80000484 - 80000254: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000258: 00200293 li t0,2 - 8000025c: fc521ee3 bne tp,t0,80000238 - -0000000080000260 : - 80000260: 00b00193 li gp,11 - 80000264: 00000213 li tp,0 - 80000268: 00f0009b addiw ra,zero,15 - 8000026c: 01c09093 slli ra,ra,0x1c - 80000270: 00f0011b addiw sp,zero,15 - 80000274: 01c11113 slli sp,sp,0x1c - 80000278: fff10113 addi sp,sp,-1 - 8000027c: 00000013 nop - 80000280: 00000013 nop - 80000284: 2020e063 bltu ra,sp,80000484 - 80000288: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000028c: 00200293 li t0,2 - 80000290: fc521ce3 bne tp,t0,80000268 - -0000000080000294 : - 80000294: 00c00193 li gp,12 - 80000298: 00000213 li tp,0 - 8000029c: 00f0009b addiw ra,zero,15 - 800002a0: 01c09093 slli ra,ra,0x1c - 800002a4: 00000013 nop - 800002a8: 00f0011b addiw sp,zero,15 - 800002ac: 01c11113 slli sp,sp,0x1c - 800002b0: fff10113 addi sp,sp,-1 - 800002b4: 1c20e863 bltu ra,sp,80000484 - 800002b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002bc: 00200293 li t0,2 - 800002c0: fc521ee3 bne tp,t0,8000029c - -00000000800002c4 : - 800002c4: 00d00193 li gp,13 - 800002c8: 00000213 li tp,0 - 800002cc: 00f0009b addiw ra,zero,15 - 800002d0: 01c09093 slli ra,ra,0x1c - 800002d4: 00000013 nop - 800002d8: 00f0011b addiw sp,zero,15 - 800002dc: 01c11113 slli sp,sp,0x1c - 800002e0: fff10113 addi sp,sp,-1 - 800002e4: 00000013 nop - 800002e8: 1820ee63 bltu ra,sp,80000484 - 800002ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002f0: 00200293 li t0,2 - 800002f4: fc521ce3 bne tp,t0,800002cc - -00000000800002f8 : - 800002f8: 00e00193 li gp,14 - 800002fc: 00000213 li tp,0 - 80000300: 00f0009b addiw ra,zero,15 - 80000304: 01c09093 slli ra,ra,0x1c - 80000308: 00000013 nop - 8000030c: 00000013 nop - 80000310: 00f0011b addiw sp,zero,15 - 80000314: 01c11113 slli sp,sp,0x1c - 80000318: fff10113 addi sp,sp,-1 - 8000031c: 1620e463 bltu ra,sp,80000484 - 80000320: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000324: 00200293 li t0,2 - 80000328: fc521ce3 bne tp,t0,80000300 - -000000008000032c : - 8000032c: 00f00193 li gp,15 - 80000330: 00000213 li tp,0 - 80000334: 00f0009b addiw ra,zero,15 - 80000338: 01c09093 slli ra,ra,0x1c - 8000033c: 00f0011b addiw sp,zero,15 - 80000340: 01c11113 slli sp,sp,0x1c - 80000344: fff10113 addi sp,sp,-1 - 80000348: 1220ee63 bltu ra,sp,80000484 - 8000034c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000350: 00200293 li t0,2 - 80000354: fe5210e3 bne tp,t0,80000334 - -0000000080000358 : - 80000358: 01000193 li gp,16 - 8000035c: 00000213 li tp,0 - 80000360: 00f0009b addiw ra,zero,15 - 80000364: 01c09093 slli ra,ra,0x1c - 80000368: 00f0011b addiw sp,zero,15 - 8000036c: 01c11113 slli sp,sp,0x1c - 80000370: fff10113 addi sp,sp,-1 - 80000374: 00000013 nop - 80000378: 1020e663 bltu ra,sp,80000484 - 8000037c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000380: 00200293 li t0,2 - 80000384: fc521ee3 bne tp,t0,80000360 - -0000000080000388 : - 80000388: 01100193 li gp,17 - 8000038c: 00000213 li tp,0 - 80000390: 00f0009b addiw ra,zero,15 - 80000394: 01c09093 slli ra,ra,0x1c - 80000398: 00f0011b addiw sp,zero,15 - 8000039c: 01c11113 slli sp,sp,0x1c - 800003a0: fff10113 addi sp,sp,-1 - 800003a4: 00000013 nop - 800003a8: 00000013 nop - 800003ac: 0c20ec63 bltu ra,sp,80000484 - 800003b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003b4: 00200293 li t0,2 - 800003b8: fc521ce3 bne tp,t0,80000390 - -00000000800003bc : - 800003bc: 01200193 li gp,18 - 800003c0: 00000213 li tp,0 - 800003c4: 00f0009b addiw ra,zero,15 - 800003c8: 01c09093 slli ra,ra,0x1c - 800003cc: 00000013 nop - 800003d0: 00f0011b addiw sp,zero,15 - 800003d4: 01c11113 slli sp,sp,0x1c - 800003d8: fff10113 addi sp,sp,-1 - 800003dc: 0a20e463 bltu ra,sp,80000484 - 800003e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003e4: 00200293 li t0,2 - 800003e8: fc521ee3 bne tp,t0,800003c4 - -00000000800003ec : - 800003ec: 01300193 li gp,19 - 800003f0: 00000213 li tp,0 - 800003f4: 00f0009b addiw ra,zero,15 - 800003f8: 01c09093 slli ra,ra,0x1c - 800003fc: 00000013 nop - 80000400: 00f0011b addiw sp,zero,15 - 80000404: 01c11113 slli sp,sp,0x1c - 80000408: fff10113 addi sp,sp,-1 - 8000040c: 00000013 nop - 80000410: 0620ea63 bltu ra,sp,80000484 - 80000414: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000418: 00200293 li t0,2 - 8000041c: fc521ce3 bne tp,t0,800003f4 - -0000000080000420 : - 80000420: 01400193 li gp,20 - 80000424: 00000213 li tp,0 - 80000428: 00f0009b addiw ra,zero,15 - 8000042c: 01c09093 slli ra,ra,0x1c - 80000430: 00000013 nop - 80000434: 00000013 nop - 80000438: 00f0011b addiw sp,zero,15 - 8000043c: 01c11113 slli sp,sp,0x1c - 80000440: fff10113 addi sp,sp,-1 - 80000444: 0420e063 bltu ra,sp,80000484 - 80000448: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000044c: 00200293 li t0,2 - 80000450: fc521ce3 bne tp,t0,80000428 - -0000000080000454 : - 80000454: 00100093 li ra,1 - 80000458: 00106a63 bltu zero,ra,8000046c - 8000045c: 00108093 addi ra,ra,1 - 80000460: 00108093 addi ra,ra,1 - 80000464: 00108093 addi ra,ra,1 - 80000468: 00108093 addi ra,ra,1 - 8000046c: 00108093 addi ra,ra,1 - 80000470: 00108093 addi ra,ra,1 - 80000474: 00300e93 li t4,3 - 80000478: 01500193 li gp,21 - 8000047c: 01d09463 bne ra,t4,80000484 - 80000480: 00301c63 bne zero,gp,80000498 - -0000000080000484 : - 80000484: 0ff0000f fence - 80000488: 00018063 beqz gp,80000488 - 8000048c: 00119193 slli gp,gp,0x1 - 80000490: 0011e193 ori gp,gp,1 - 80000494: 00000073 ecall - -0000000080000498 : - 80000498: 0ff0000f fence - 8000049c: 00100193 li gp,1 - 800004a0: 00000073 ecall - 800004a4: c0001073 unimp - 800004a8: 0000 unimp - 800004aa: 0000 unimp - 800004ac: 0000 unimp - 800004ae: 0000 unimp - 800004b0: 0000 unimp - 800004b2: 0000 unimp - 800004b4: 0000 unimp - 800004b6: 0000 unimp - 800004b8: 0000 unimp - 800004ba: 0000 unimp - 800004bc: 0000 unimp - 800004be: 0000 unimp - 800004c0: 0000 unimp - 800004c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-bltu.elf b/test/riscv/tests/rv64ui-p-bltu.elf deleted file mode 100644 index a5d06391..00000000 Binary files a/test/riscv/tests/rv64ui-p-bltu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-bne.dump b/test/riscv/tests/rv64ui-p-bne.dump deleted file mode 100644 index 42f4613f..00000000 --- a/test/riscv/tests/rv64ui-p-bne.dump +++ /dev/null @@ -1,324 +0,0 @@ - -rv64ui-p-bne: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00200193 li gp,2 - 80000100: 00000093 li ra,0 - 80000104: 00100113 li sp,1 - 80000108: 00209663 bne ra,sp,80000114 - 8000010c: 2a301a63 bne zero,gp,800003c0 - 80000110: 00301663 bne zero,gp,8000011c - 80000114: fe209ee3 bne ra,sp,80000110 - 80000118: 2a301463 bne zero,gp,800003c0 - -000000008000011c : - 8000011c: 00300193 li gp,3 - 80000120: 00100093 li ra,1 - 80000124: 00000113 li sp,0 - 80000128: 00209663 bne ra,sp,80000134 - 8000012c: 28301a63 bne zero,gp,800003c0 - 80000130: 00301663 bne zero,gp,8000013c - 80000134: fe209ee3 bne ra,sp,80000130 - 80000138: 28301463 bne zero,gp,800003c0 - -000000008000013c : - 8000013c: 00400193 li gp,4 - 80000140: fff00093 li ra,-1 - 80000144: 00100113 li sp,1 - 80000148: 00209663 bne ra,sp,80000154 - 8000014c: 26301a63 bne zero,gp,800003c0 - 80000150: 00301663 bne zero,gp,8000015c - 80000154: fe209ee3 bne ra,sp,80000150 - 80000158: 26301463 bne zero,gp,800003c0 - -000000008000015c : - 8000015c: 00500193 li gp,5 - 80000160: 00100093 li ra,1 - 80000164: fff00113 li sp,-1 - 80000168: 00209663 bne ra,sp,80000174 - 8000016c: 24301a63 bne zero,gp,800003c0 - 80000170: 00301663 bne zero,gp,8000017c - 80000174: fe209ee3 bne ra,sp,80000170 - 80000178: 24301463 bne zero,gp,800003c0 - -000000008000017c : - 8000017c: 00600193 li gp,6 - 80000180: 00000093 li ra,0 - 80000184: 00000113 li sp,0 - 80000188: 00209463 bne ra,sp,80000190 - 8000018c: 00301463 bne zero,gp,80000194 - 80000190: 22301863 bne zero,gp,800003c0 - 80000194: fe209ee3 bne ra,sp,80000190 - -0000000080000198 : - 80000198: 00700193 li gp,7 - 8000019c: 00100093 li ra,1 - 800001a0: 00100113 li sp,1 - 800001a4: 00209463 bne ra,sp,800001ac - 800001a8: 00301463 bne zero,gp,800001b0 - 800001ac: 20301a63 bne zero,gp,800003c0 - 800001b0: fe209ee3 bne ra,sp,800001ac - -00000000800001b4 : - 800001b4: 00800193 li gp,8 - 800001b8: fff00093 li ra,-1 - 800001bc: fff00113 li sp,-1 - 800001c0: 00209463 bne ra,sp,800001c8 - 800001c4: 00301463 bne zero,gp,800001cc - 800001c8: 1e301c63 bne zero,gp,800003c0 - 800001cc: fe209ee3 bne ra,sp,800001c8 - -00000000800001d0 : - 800001d0: 00900193 li gp,9 - 800001d4: 00000213 li tp,0 - 800001d8: 00000093 li ra,0 - 800001dc: 00000113 li sp,0 - 800001e0: 1e209063 bne ra,sp,800003c0 - 800001e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800001e8: 00200293 li t0,2 - 800001ec: fe5216e3 bne tp,t0,800001d8 - -00000000800001f0 : - 800001f0: 00a00193 li gp,10 - 800001f4: 00000213 li tp,0 - 800001f8: 00000093 li ra,0 - 800001fc: 00000113 li sp,0 - 80000200: 00000013 nop - 80000204: 1a209e63 bne ra,sp,800003c0 - 80000208: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000020c: 00200293 li t0,2 - 80000210: fe5214e3 bne tp,t0,800001f8 - -0000000080000214 : - 80000214: 00b00193 li gp,11 - 80000218: 00000213 li tp,0 - 8000021c: 00000093 li ra,0 - 80000220: 00000113 li sp,0 - 80000224: 00000013 nop - 80000228: 00000013 nop - 8000022c: 18209a63 bne ra,sp,800003c0 - 80000230: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000234: 00200293 li t0,2 - 80000238: fe5212e3 bne tp,t0,8000021c - -000000008000023c : - 8000023c: 00c00193 li gp,12 - 80000240: 00000213 li tp,0 - 80000244: 00000093 li ra,0 - 80000248: 00000013 nop - 8000024c: 00000113 li sp,0 - 80000250: 16209863 bne ra,sp,800003c0 - 80000254: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000258: 00200293 li t0,2 - 8000025c: fe5214e3 bne tp,t0,80000244 - -0000000080000260 : - 80000260: 00d00193 li gp,13 - 80000264: 00000213 li tp,0 - 80000268: 00000093 li ra,0 - 8000026c: 00000013 nop - 80000270: 00000113 li sp,0 - 80000274: 00000013 nop - 80000278: 14209463 bne ra,sp,800003c0 - 8000027c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000280: 00200293 li t0,2 - 80000284: fe5212e3 bne tp,t0,80000268 - -0000000080000288 : - 80000288: 00e00193 li gp,14 - 8000028c: 00000213 li tp,0 - 80000290: 00000093 li ra,0 - 80000294: 00000013 nop - 80000298: 00000013 nop - 8000029c: 00000113 li sp,0 - 800002a0: 12209063 bne ra,sp,800003c0 - 800002a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002a8: 00200293 li t0,2 - 800002ac: fe5212e3 bne tp,t0,80000290 - -00000000800002b0 : - 800002b0: 00f00193 li gp,15 - 800002b4: 00000213 li tp,0 - 800002b8: 00000093 li ra,0 - 800002bc: 00000113 li sp,0 - 800002c0: 10209063 bne ra,sp,800003c0 - 800002c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002c8: 00200293 li t0,2 - 800002cc: fe5216e3 bne tp,t0,800002b8 - -00000000800002d0 : - 800002d0: 01000193 li gp,16 - 800002d4: 00000213 li tp,0 - 800002d8: 00000093 li ra,0 - 800002dc: 00000113 li sp,0 - 800002e0: 00000013 nop - 800002e4: 0c209e63 bne ra,sp,800003c0 - 800002e8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002ec: 00200293 li t0,2 - 800002f0: fe5214e3 bne tp,t0,800002d8 - -00000000800002f4 : - 800002f4: 01100193 li gp,17 - 800002f8: 00000213 li tp,0 - 800002fc: 00000093 li ra,0 - 80000300: 00000113 li sp,0 - 80000304: 00000013 nop - 80000308: 00000013 nop - 8000030c: 0a209a63 bne ra,sp,800003c0 - 80000310: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000314: 00200293 li t0,2 - 80000318: fe5212e3 bne tp,t0,800002fc - -000000008000031c : - 8000031c: 01200193 li gp,18 - 80000320: 00000213 li tp,0 - 80000324: 00000093 li ra,0 - 80000328: 00000013 nop - 8000032c: 00000113 li sp,0 - 80000330: 08209863 bne ra,sp,800003c0 - 80000334: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000338: 00200293 li t0,2 - 8000033c: fe5214e3 bne tp,t0,80000324 - -0000000080000340 : - 80000340: 01300193 li gp,19 - 80000344: 00000213 li tp,0 - 80000348: 00000093 li ra,0 - 8000034c: 00000013 nop - 80000350: 00000113 li sp,0 - 80000354: 00000013 nop - 80000358: 06209463 bne ra,sp,800003c0 - 8000035c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000360: 00200293 li t0,2 - 80000364: fe5212e3 bne tp,t0,80000348 - -0000000080000368 : - 80000368: 01400193 li gp,20 - 8000036c: 00000213 li tp,0 - 80000370: 00000093 li ra,0 - 80000374: 00000013 nop - 80000378: 00000013 nop - 8000037c: 00000113 li sp,0 - 80000380: 04209063 bne ra,sp,800003c0 - 80000384: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000388: 00200293 li t0,2 - 8000038c: fe5212e3 bne tp,t0,80000370 - -0000000080000390 : - 80000390: 00100093 li ra,1 - 80000394: 00009a63 bnez ra,800003a8 - 80000398: 00108093 addi ra,ra,1 - 8000039c: 00108093 addi ra,ra,1 - 800003a0: 00108093 addi ra,ra,1 - 800003a4: 00108093 addi ra,ra,1 - 800003a8: 00108093 addi ra,ra,1 - 800003ac: 00108093 addi ra,ra,1 - 800003b0: 00300e93 li t4,3 - 800003b4: 01500193 li gp,21 - 800003b8: 01d09463 bne ra,t4,800003c0 - 800003bc: 00301c63 bne zero,gp,800003d4 - -00000000800003c0 : - 800003c0: 0ff0000f fence - 800003c4: 00018063 beqz gp,800003c4 - 800003c8: 00119193 slli gp,gp,0x1 - 800003cc: 0011e193 ori gp,gp,1 - 800003d0: 00000073 ecall - -00000000800003d4 : - 800003d4: 0ff0000f fence - 800003d8: 00100193 li gp,1 - 800003dc: 00000073 ecall - 800003e0: c0001073 unimp - 800003e4: 0000 unimp - 800003e6: 0000 unimp - 800003e8: 0000 unimp - 800003ea: 0000 unimp - 800003ec: 0000 unimp - 800003ee: 0000 unimp - 800003f0: 0000 unimp - 800003f2: 0000 unimp - 800003f4: 0000 unimp - 800003f6: 0000 unimp - 800003f8: 0000 unimp - 800003fa: 0000 unimp - 800003fc: 0000 unimp - 800003fe: 0000 unimp - 80000400: 0000 unimp - 80000402: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-bne.elf b/test/riscv/tests/rv64ui-p-bne.elf deleted file mode 100644 index 9a83bec4..00000000 Binary files a/test/riscv/tests/rv64ui-p-bne.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-fence_i.dump b/test/riscv/tests/rv64ui-p-fence_i.dump deleted file mode 100644 index 8bbfcfdb..00000000 --- a/test/riscv/tests/rv64ui-p-fence_i.dump +++ /dev/null @@ -1,189 +0,0 @@ - -rv64ui-p-fence_i: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - 800000fc: 06f00693 li a3,111 - 80000100: 00002517 auipc a0,0x2 - 80000104: f0051503 lh a0,-256(a0) # 80002000 - 80000108: 00002597 auipc a1,0x2 - 8000010c: efa59583 lh a1,-262(a1) # 80002002 - 80000110: 00000013 nop - 80000114: 00000013 nop - 80000118: 00000013 nop - 8000011c: 00000013 nop - 80000120: 00000013 nop - 80000124: 00000013 nop - 80000128: 00000013 nop - 8000012c: 00000013 nop - 80000130: 00000013 nop - 80000134: 00000013 nop - 80000138: 00000013 nop - 8000013c: 00000013 nop - 80000140: 00000297 auipc t0,0x0 - 80000144: 00a29a23 sh a0,20(t0) # 80000154 - 80000148: 00000297 auipc t0,0x0 - 8000014c: 00b29723 sh a1,14(t0) # 80000156 - 80000150: 0000100f fence.i - 80000154: 0de68693 addi a3,a3,222 - -0000000080000158 : - 80000158: 00000013 nop - 8000015c: 1bc00e93 li t4,444 - 80000160: 00200193 li gp,2 - 80000164: 07d69a63 bne a3,t4,800001d8 - 80000168: 06400713 li a4,100 - 8000016c: fff70713 addi a4,a4,-1 - 80000170: fe071ee3 bnez a4,8000016c - 80000174: 00000297 auipc t0,0x0 - 80000178: 04a29623 sh a0,76(t0) # 800001c0 - 8000017c: 00000297 auipc t0,0x0 - 80000180: 04b29323 sh a1,70(t0) # 800001c2 - 80000184: 0000100f fence.i - 80000188: 00000013 nop - 8000018c: 00000013 nop - 80000190: 00000013 nop - 80000194: 00000013 nop - 80000198: 00000013 nop - 8000019c: 00000013 nop - 800001a0: 00000013 nop - 800001a4: 00000013 nop - 800001a8: 00000013 nop - 800001ac: 00000013 nop - 800001b0: 00000013 nop - 800001b4: 00000013 nop - 800001b8: 00000013 nop - 800001bc: 00000013 nop - 800001c0: 22b68693 addi a3,a3,555 - -00000000800001c4 : - 800001c4: 00000013 nop - 800001c8: 30900e93 li t4,777 - 800001cc: 00300193 li gp,3 - 800001d0: 01d69463 bne a3,t4,800001d8 - 800001d4: 00301c63 bne zero,gp,800001ec - -00000000800001d8 : - 800001d8: 0ff0000f fence - 800001dc: 00018063 beqz gp,800001dc - 800001e0: 00119193 slli gp,gp,0x1 - 800001e4: 0011e193 ori gp,gp,1 - 800001e8: 00000073 ecall - -00000000800001ec : - 800001ec: 0ff0000f fence - 800001f0: 00100193 li gp,1 - 800001f4: 00000073 ecall - 800001f8: c0001073 unimp - 800001fc: 0000 unimp - 800001fe: 0000 unimp - 80000200: 0000 unimp - 80000202: 0000 unimp - 80000204: 0000 unimp - 80000206: 0000 unimp - 80000208: 0000 unimp - 8000020a: 0000 unimp - 8000020c: 0000 unimp - 8000020e: 0000 unimp - 80000210: 0000 unimp - 80000212: 0000 unimp - 80000214: 0000 unimp - 80000216: 0000 unimp - 80000218: 0000 unimp - 8000021a: 0000 unimp - 8000021c: 0000 unimp - 8000021e: 0000 unimp - 80000220: 0000 unimp - 80000222: 0000 unimp - 80000224: 0000 unimp - 80000226: 0000 unimp - 80000228: 0000 unimp - 8000022a: 0000 unimp - 8000022c: 0000 unimp - 8000022e: 0000 unimp - 80000230: 0000 unimp - 80000232: 0000 unimp - -Disassembly of section .data: - -0000000080002000 : - 80002000: 14d68693 addi a3,a3,333 - 80002004: 0000 unimp - 80002006: 0000 unimp - 80002008: 0000 unimp - 8000200a: 0000 unimp - 8000200c: 0000 unimp - 8000200e: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-fence_i.elf b/test/riscv/tests/rv64ui-p-fence_i.elf deleted file mode 100644 index 9f8d7726..00000000 Binary files a/test/riscv/tests/rv64ui-p-fence_i.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-jal.dump b/test/riscv/tests/rv64ui-p-jal.dump deleted file mode 100644 index 2a86bb86..00000000 --- a/test/riscv/tests/rv64ui-p-jal.dump +++ /dev/null @@ -1,128 +0,0 @@ - -rv64ui-p-jal: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00200193 li gp,2 - 80000100: 00000093 li ra,0 - 80000104: 0100026f jal tp,80000114 - -0000000080000108 : - 80000108: 00000013 nop - 8000010c: 00000013 nop - 80000110: 0400006f j 80000150 - -0000000080000114 : - 80000114: 00000117 auipc sp,0x0 - 80000118: ff410113 addi sp,sp,-12 # 80000108 - 8000011c: 02411a63 bne sp,tp,80000150 - -0000000080000120 : - 80000120: 00100093 li ra,1 - 80000124: 0140006f j 80000138 - 80000128: 00108093 addi ra,ra,1 - 8000012c: 00108093 addi ra,ra,1 - 80000130: 00108093 addi ra,ra,1 - 80000134: 00108093 addi ra,ra,1 - 80000138: 00108093 addi ra,ra,1 - 8000013c: 00108093 addi ra,ra,1 - 80000140: 00300e93 li t4,3 - 80000144: 00300193 li gp,3 - 80000148: 01d09463 bne ra,t4,80000150 - 8000014c: 00301c63 bne zero,gp,80000164 - -0000000080000150 : - 80000150: 0ff0000f fence - 80000154: 00018063 beqz gp,80000154 - 80000158: 00119193 slli gp,gp,0x1 - 8000015c: 0011e193 ori gp,gp,1 - 80000160: 00000073 ecall - -0000000080000164 : - 80000164: 0ff0000f fence - 80000168: 00100193 li gp,1 - 8000016c: 00000073 ecall - 80000170: c0001073 unimp - 80000174: 0000 unimp - 80000176: 0000 unimp - 80000178: 0000 unimp - 8000017a: 0000 unimp - 8000017c: 0000 unimp - 8000017e: 0000 unimp - 80000180: 0000 unimp - 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-jal.elf b/test/riscv/tests/rv64ui-p-jal.elf deleted file mode 100644 index 3741bbb7..00000000 Binary files a/test/riscv/tests/rv64ui-p-jal.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-jalr.dump b/test/riscv/tests/rv64ui-p-jalr.dump deleted file mode 100644 index 029a6922..00000000 --- a/test/riscv/tests/rv64ui-p-jalr.dump +++ /dev/null @@ -1,166 +0,0 @@ - -rv64ui-p-jalr: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00200193 li gp,2 - 80000100: 00000293 li t0,0 - 80000104: 00000317 auipc t1,0x0 - 80000108: 01030313 addi t1,t1,16 # 80000114 - 8000010c: 000302e7 jalr t0,t1 - -0000000080000110 : - 80000110: 0c00006f j 800001d0 - -0000000080000114 : - 80000114: 00000317 auipc t1,0x0 - 80000118: ffc30313 addi t1,t1,-4 # 80000110 - 8000011c: 0a629a63 bne t0,t1,800001d0 - -0000000080000120 : - 80000120: 00400193 li gp,4 - 80000124: 00000213 li tp,0 - 80000128: 00000317 auipc t1,0x0 - 8000012c: 01030313 addi t1,t1,16 # 80000138 - 80000130: 000309e7 jalr s3,t1 - 80000134: 08301e63 bne zero,gp,800001d0 - 80000138: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000013c: 00200293 li t0,2 - 80000140: fe5214e3 bne tp,t0,80000128 - -0000000080000144 : - 80000144: 00500193 li gp,5 - 80000148: 00000213 li tp,0 - 8000014c: 00000317 auipc t1,0x0 - 80000150: 01430313 addi t1,t1,20 # 80000160 - 80000154: 00000013 nop - 80000158: 000309e7 jalr s3,t1 - 8000015c: 06301a63 bne zero,gp,800001d0 - 80000160: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000164: 00200293 li t0,2 - 80000168: fe5212e3 bne tp,t0,8000014c - -000000008000016c : - 8000016c: 00600193 li gp,6 - 80000170: 00000213 li tp,0 - 80000174: 00000317 auipc t1,0x0 - 80000178: 01830313 addi t1,t1,24 # 8000018c - 8000017c: 00000013 nop - 80000180: 00000013 nop - 80000184: 000309e7 jalr s3,t1 - 80000188: 04301463 bne zero,gp,800001d0 - 8000018c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000190: 00200293 li t0,2 - 80000194: fe5210e3 bne tp,t0,80000174 - -0000000080000198 : - 80000198: 00100293 li t0,1 - 8000019c: 00000317 auipc t1,0x0 - 800001a0: 01c30313 addi t1,t1,28 # 800001b8 - 800001a4: ffc30067 jr -4(t1) - 800001a8: 00128293 addi t0,t0,1 - 800001ac: 00128293 addi t0,t0,1 - 800001b0: 00128293 addi t0,t0,1 - 800001b4: 00128293 addi t0,t0,1 - 800001b8: 00128293 addi t0,t0,1 - 800001bc: 00128293 addi t0,t0,1 - 800001c0: 00400e93 li t4,4 - 800001c4: 00700193 li gp,7 - 800001c8: 01d29463 bne t0,t4,800001d0 - 800001cc: 00301c63 bne zero,gp,800001e4 - -00000000800001d0 : - 800001d0: 0ff0000f fence - 800001d4: 00018063 beqz gp,800001d4 - 800001d8: 00119193 slli gp,gp,0x1 - 800001dc: 0011e193 ori gp,gp,1 - 800001e0: 00000073 ecall - -00000000800001e4 : - 800001e4: 0ff0000f fence - 800001e8: 00100193 li gp,1 - 800001ec: 00000073 ecall - 800001f0: c0001073 unimp - 800001f4: 0000 unimp - 800001f6: 0000 unimp - 800001f8: 0000 unimp - 800001fa: 0000 unimp - 800001fc: 0000 unimp - 800001fe: 0000 unimp - 80000200: 0000 unimp - 80000202: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-jalr.elf b/test/riscv/tests/rv64ui-p-jalr.elf deleted file mode 100644 index 9682d86f..00000000 Binary files a/test/riscv/tests/rv64ui-p-jalr.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-lb.dump b/test/riscv/tests/rv64ui-p-lb.dump deleted file mode 100644 index dbf78e7d..00000000 --- a/test/riscv/tests/rv64ui-p-lb.dump +++ /dev/null @@ -1,306 +0,0 @@ - -rv64ui-p-lb: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00002097 auipc ra,0x2 - 80000100: f0408093 addi ra,ra,-252 # 80002000 - 80000104: 00008f03 lb t5,0(ra) - 80000108: fff00e93 li t4,-1 - 8000010c: 00200193 li gp,2 - 80000110: 23df1c63 bne t5,t4,80000348 - -0000000080000114 : - 80000114: 00002097 auipc ra,0x2 - 80000118: eec08093 addi ra,ra,-276 # 80002000 - 8000011c: 00108f03 lb t5,1(ra) - 80000120: 00000e93 li t4,0 - 80000124: 00300193 li gp,3 - 80000128: 23df1063 bne t5,t4,80000348 - -000000008000012c : - 8000012c: 00002097 auipc ra,0x2 - 80000130: ed408093 addi ra,ra,-300 # 80002000 - 80000134: 00208f03 lb t5,2(ra) - 80000138: ff000e93 li t4,-16 - 8000013c: 00400193 li gp,4 - 80000140: 21df1463 bne t5,t4,80000348 - -0000000080000144 : - 80000144: 00002097 auipc ra,0x2 - 80000148: ebc08093 addi ra,ra,-324 # 80002000 - 8000014c: 00308f03 lb t5,3(ra) - 80000150: 00f00e93 li t4,15 - 80000154: 00500193 li gp,5 - 80000158: 1fdf1863 bne t5,t4,80000348 - -000000008000015c : - 8000015c: 00002097 auipc ra,0x2 - 80000160: ea708093 addi ra,ra,-345 # 80002003 - 80000164: ffd08f03 lb t5,-3(ra) - 80000168: fff00e93 li t4,-1 - 8000016c: 00600193 li gp,6 - 80000170: 1ddf1c63 bne t5,t4,80000348 - -0000000080000174 : - 80000174: 00002097 auipc ra,0x2 - 80000178: e8f08093 addi ra,ra,-369 # 80002003 - 8000017c: ffe08f03 lb t5,-2(ra) - 80000180: 00000e93 li t4,0 - 80000184: 00700193 li gp,7 - 80000188: 1ddf1063 bne t5,t4,80000348 - -000000008000018c : - 8000018c: 00002097 auipc ra,0x2 - 80000190: e7708093 addi ra,ra,-393 # 80002003 - 80000194: fff08f03 lb t5,-1(ra) - 80000198: ff000e93 li t4,-16 - 8000019c: 00800193 li gp,8 - 800001a0: 1bdf1463 bne t5,t4,80000348 - -00000000800001a4 : - 800001a4: 00002097 auipc ra,0x2 - 800001a8: e5f08093 addi ra,ra,-417 # 80002003 - 800001ac: 00008f03 lb t5,0(ra) - 800001b0: 00f00e93 li t4,15 - 800001b4: 00900193 li gp,9 - 800001b8: 19df1863 bne t5,t4,80000348 - -00000000800001bc : - 800001bc: 00002097 auipc ra,0x2 - 800001c0: e4408093 addi ra,ra,-444 # 80002000 - 800001c4: fe008093 addi ra,ra,-32 - 800001c8: 02008283 lb t0,32(ra) - 800001cc: fff00e93 li t4,-1 - 800001d0: 00a00193 li gp,10 - 800001d4: 17d29a63 bne t0,t4,80000348 - -00000000800001d8 : - 800001d8: 00002097 auipc ra,0x2 - 800001dc: e2808093 addi ra,ra,-472 # 80002000 - 800001e0: ffa08093 addi ra,ra,-6 - 800001e4: 00708283 lb t0,7(ra) - 800001e8: 00000e93 li t4,0 - 800001ec: 00b00193 li gp,11 - 800001f0: 15d29c63 bne t0,t4,80000348 - -00000000800001f4 : - 800001f4: 00c00193 li gp,12 - 800001f8: 00000213 li tp,0 - 800001fc: 00002097 auipc ra,0x2 - 80000200: e0508093 addi ra,ra,-507 # 80002001 - 80000204: 00108f03 lb t5,1(ra) - 80000208: 000f0313 mv t1,t5 - 8000020c: ff000e93 li t4,-16 - 80000210: 13d31c63 bne t1,t4,80000348 - 80000214: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000218: 00200293 li t0,2 - 8000021c: fe5210e3 bne tp,t0,800001fc - -0000000080000220 : - 80000220: 00d00193 li gp,13 - 80000224: 00000213 li tp,0 - 80000228: 00002097 auipc ra,0x2 - 8000022c: dda08093 addi ra,ra,-550 # 80002002 - 80000230: 00108f03 lb t5,1(ra) - 80000234: 00000013 nop - 80000238: 000f0313 mv t1,t5 - 8000023c: 00f00e93 li t4,15 - 80000240: 11d31463 bne t1,t4,80000348 - 80000244: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000248: 00200293 li t0,2 - 8000024c: fc521ee3 bne tp,t0,80000228 - -0000000080000250 : - 80000250: 00e00193 li gp,14 - 80000254: 00000213 li tp,0 - 80000258: 00002097 auipc ra,0x2 - 8000025c: da808093 addi ra,ra,-600 # 80002000 - 80000260: 00108f03 lb t5,1(ra) - 80000264: 00000013 nop - 80000268: 00000013 nop - 8000026c: 000f0313 mv t1,t5 - 80000270: 00000e93 li t4,0 - 80000274: 0dd31a63 bne t1,t4,80000348 - 80000278: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000027c: 00200293 li t0,2 - 80000280: fc521ce3 bne tp,t0,80000258 - -0000000080000284 : - 80000284: 00f00193 li gp,15 - 80000288: 00000213 li tp,0 - 8000028c: 00002097 auipc ra,0x2 - 80000290: d7508093 addi ra,ra,-651 # 80002001 - 80000294: 00108f03 lb t5,1(ra) - 80000298: ff000e93 li t4,-16 - 8000029c: 0bdf1663 bne t5,t4,80000348 - 800002a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002a4: 00200293 li t0,2 - 800002a8: fe5212e3 bne tp,t0,8000028c - -00000000800002ac : - 800002ac: 01000193 li gp,16 - 800002b0: 00000213 li tp,0 - 800002b4: 00002097 auipc ra,0x2 - 800002b8: d4e08093 addi ra,ra,-690 # 80002002 - 800002bc: 00000013 nop - 800002c0: 00108f03 lb t5,1(ra) - 800002c4: 00f00e93 li t4,15 - 800002c8: 09df1063 bne t5,t4,80000348 - 800002cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002d0: 00200293 li t0,2 - 800002d4: fe5210e3 bne tp,t0,800002b4 - -00000000800002d8 : - 800002d8: 01100193 li gp,17 - 800002dc: 00000213 li tp,0 - 800002e0: 00002097 auipc ra,0x2 - 800002e4: d2008093 addi ra,ra,-736 # 80002000 - 800002e8: 00000013 nop - 800002ec: 00000013 nop - 800002f0: 00108f03 lb t5,1(ra) - 800002f4: 00000e93 li t4,0 - 800002f8: 05df1863 bne t5,t4,80000348 - 800002fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000300: 00200293 li t0,2 - 80000304: fc521ee3 bne tp,t0,800002e0 - -0000000080000308 : - 80000308: 00002297 auipc t0,0x2 - 8000030c: cf828293 addi t0,t0,-776 # 80002000 - 80000310: 00028103 lb sp,0(t0) - 80000314: 00200113 li sp,2 - 80000318: 00200e93 li t4,2 - 8000031c: 01200193 li gp,18 - 80000320: 03d11463 bne sp,t4,80000348 - -0000000080000324 : - 80000324: 00002297 auipc t0,0x2 - 80000328: cdc28293 addi t0,t0,-804 # 80002000 - 8000032c: 00028103 lb sp,0(t0) - 80000330: 00000013 nop - 80000334: 00200113 li sp,2 - 80000338: 00200e93 li t4,2 - 8000033c: 01300193 li gp,19 - 80000340: 01d11463 bne sp,t4,80000348 - 80000344: 00301c63 bne zero,gp,8000035c - -0000000080000348 : - 80000348: 0ff0000f fence - 8000034c: 00018063 beqz gp,8000034c - 80000350: 00119193 slli gp,gp,0x1 - 80000354: 0011e193 ori gp,gp,1 - 80000358: 00000073 ecall - -000000008000035c : - 8000035c: 0ff0000f fence - 80000360: 00100193 li gp,1 - 80000364: 00000073 ecall - 80000368: c0001073 unimp - 8000036c: 0000 unimp - 8000036e: 0000 unimp - 80000370: 0000 unimp - 80000372: 0000 unimp - 80000374: 0000 unimp - 80000376: 0000 unimp - 80000378: 0000 unimp - 8000037a: 0000 unimp - 8000037c: 0000 unimp - 8000037e: 0000 unimp - 80000380: 0000 unimp - 80000382: 0000 unimp - -Disassembly of section .data: - -0000000080002000 : - 80002000: 0xff - -0000000080002001 : - 80002001: sd s0,32(s0) - -0000000080002002 : - 80002002: addi a2,sp,988 - -0000000080002003 : - 80002003: 0000000f fence unknown,unknown - 80002007: 0000 unimp - 80002009: 0000 unimp - 8000200b: 0000 unimp - 8000200d: 0000 unimp - 8000200f: 00 Address 0x000000008000200f is out of bounds. - diff --git a/test/riscv/tests/rv64ui-p-lb.elf b/test/riscv/tests/rv64ui-p-lb.elf deleted file mode 100644 index 7e0a8a40..00000000 Binary files a/test/riscv/tests/rv64ui-p-lb.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-lbu.dump b/test/riscv/tests/rv64ui-p-lbu.dump deleted file mode 100644 index 4365b07b..00000000 --- a/test/riscv/tests/rv64ui-p-lbu.dump +++ /dev/null @@ -1,306 +0,0 @@ - -rv64ui-p-lbu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00002097 auipc ra,0x2 - 80000100: f0408093 addi ra,ra,-252 # 80002000 - 80000104: 0000cf03 lbu t5,0(ra) - 80000108: 0ff00e93 li t4,255 - 8000010c: 00200193 li gp,2 - 80000110: 23df1c63 bne t5,t4,80000348 - -0000000080000114 : - 80000114: 00002097 auipc ra,0x2 - 80000118: eec08093 addi ra,ra,-276 # 80002000 - 8000011c: 0010cf03 lbu t5,1(ra) - 80000120: 00000e93 li t4,0 - 80000124: 00300193 li gp,3 - 80000128: 23df1063 bne t5,t4,80000348 - -000000008000012c : - 8000012c: 00002097 auipc ra,0x2 - 80000130: ed408093 addi ra,ra,-300 # 80002000 - 80000134: 0020cf03 lbu t5,2(ra) - 80000138: 0f000e93 li t4,240 - 8000013c: 00400193 li gp,4 - 80000140: 21df1463 bne t5,t4,80000348 - -0000000080000144 : - 80000144: 00002097 auipc ra,0x2 - 80000148: ebc08093 addi ra,ra,-324 # 80002000 - 8000014c: 0030cf03 lbu t5,3(ra) - 80000150: 00f00e93 li t4,15 - 80000154: 00500193 li gp,5 - 80000158: 1fdf1863 bne t5,t4,80000348 - -000000008000015c : - 8000015c: 00002097 auipc ra,0x2 - 80000160: ea708093 addi ra,ra,-345 # 80002003 - 80000164: ffd0cf03 lbu t5,-3(ra) - 80000168: 0ff00e93 li t4,255 - 8000016c: 00600193 li gp,6 - 80000170: 1ddf1c63 bne t5,t4,80000348 - -0000000080000174 : - 80000174: 00002097 auipc ra,0x2 - 80000178: e8f08093 addi ra,ra,-369 # 80002003 - 8000017c: ffe0cf03 lbu t5,-2(ra) - 80000180: 00000e93 li t4,0 - 80000184: 00700193 li gp,7 - 80000188: 1ddf1063 bne t5,t4,80000348 - -000000008000018c : - 8000018c: 00002097 auipc ra,0x2 - 80000190: e7708093 addi ra,ra,-393 # 80002003 - 80000194: fff0cf03 lbu t5,-1(ra) - 80000198: 0f000e93 li t4,240 - 8000019c: 00800193 li gp,8 - 800001a0: 1bdf1463 bne t5,t4,80000348 - -00000000800001a4 : - 800001a4: 00002097 auipc ra,0x2 - 800001a8: e5f08093 addi ra,ra,-417 # 80002003 - 800001ac: 0000cf03 lbu t5,0(ra) - 800001b0: 00f00e93 li t4,15 - 800001b4: 00900193 li gp,9 - 800001b8: 19df1863 bne t5,t4,80000348 - -00000000800001bc : - 800001bc: 00002097 auipc ra,0x2 - 800001c0: e4408093 addi ra,ra,-444 # 80002000 - 800001c4: fe008093 addi ra,ra,-32 - 800001c8: 0200c283 lbu t0,32(ra) - 800001cc: 0ff00e93 li t4,255 - 800001d0: 00a00193 li gp,10 - 800001d4: 17d29a63 bne t0,t4,80000348 - -00000000800001d8 : - 800001d8: 00002097 auipc ra,0x2 - 800001dc: e2808093 addi ra,ra,-472 # 80002000 - 800001e0: ffa08093 addi ra,ra,-6 - 800001e4: 0070c283 lbu t0,7(ra) - 800001e8: 00000e93 li t4,0 - 800001ec: 00b00193 li gp,11 - 800001f0: 15d29c63 bne t0,t4,80000348 - -00000000800001f4 : - 800001f4: 00c00193 li gp,12 - 800001f8: 00000213 li tp,0 - 800001fc: 00002097 auipc ra,0x2 - 80000200: e0508093 addi ra,ra,-507 # 80002001 - 80000204: 0010cf03 lbu t5,1(ra) - 80000208: 000f0313 mv t1,t5 - 8000020c: 0f000e93 li t4,240 - 80000210: 13d31c63 bne t1,t4,80000348 - 80000214: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000218: 00200293 li t0,2 - 8000021c: fe5210e3 bne tp,t0,800001fc - -0000000080000220 : - 80000220: 00d00193 li gp,13 - 80000224: 00000213 li tp,0 - 80000228: 00002097 auipc ra,0x2 - 8000022c: dda08093 addi ra,ra,-550 # 80002002 - 80000230: 0010cf03 lbu t5,1(ra) - 80000234: 00000013 nop - 80000238: 000f0313 mv t1,t5 - 8000023c: 00f00e93 li t4,15 - 80000240: 11d31463 bne t1,t4,80000348 - 80000244: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000248: 00200293 li t0,2 - 8000024c: fc521ee3 bne tp,t0,80000228 - -0000000080000250 : - 80000250: 00e00193 li gp,14 - 80000254: 00000213 li tp,0 - 80000258: 00002097 auipc ra,0x2 - 8000025c: da808093 addi ra,ra,-600 # 80002000 - 80000260: 0010cf03 lbu t5,1(ra) - 80000264: 00000013 nop - 80000268: 00000013 nop - 8000026c: 000f0313 mv t1,t5 - 80000270: 00000e93 li t4,0 - 80000274: 0dd31a63 bne t1,t4,80000348 - 80000278: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000027c: 00200293 li t0,2 - 80000280: fc521ce3 bne tp,t0,80000258 - -0000000080000284 : - 80000284: 00f00193 li gp,15 - 80000288: 00000213 li tp,0 - 8000028c: 00002097 auipc ra,0x2 - 80000290: d7508093 addi ra,ra,-651 # 80002001 - 80000294: 0010cf03 lbu t5,1(ra) - 80000298: 0f000e93 li t4,240 - 8000029c: 0bdf1663 bne t5,t4,80000348 - 800002a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002a4: 00200293 li t0,2 - 800002a8: fe5212e3 bne tp,t0,8000028c - -00000000800002ac : - 800002ac: 01000193 li gp,16 - 800002b0: 00000213 li tp,0 - 800002b4: 00002097 auipc ra,0x2 - 800002b8: d4e08093 addi ra,ra,-690 # 80002002 - 800002bc: 00000013 nop - 800002c0: 0010cf03 lbu t5,1(ra) - 800002c4: 00f00e93 li t4,15 - 800002c8: 09df1063 bne t5,t4,80000348 - 800002cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002d0: 00200293 li t0,2 - 800002d4: fe5210e3 bne tp,t0,800002b4 - -00000000800002d8 : - 800002d8: 01100193 li gp,17 - 800002dc: 00000213 li tp,0 - 800002e0: 00002097 auipc ra,0x2 - 800002e4: d2008093 addi ra,ra,-736 # 80002000 - 800002e8: 00000013 nop - 800002ec: 00000013 nop - 800002f0: 0010cf03 lbu t5,1(ra) - 800002f4: 00000e93 li t4,0 - 800002f8: 05df1863 bne t5,t4,80000348 - 800002fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000300: 00200293 li t0,2 - 80000304: fc521ee3 bne tp,t0,800002e0 - -0000000080000308 : - 80000308: 00002297 auipc t0,0x2 - 8000030c: cf828293 addi t0,t0,-776 # 80002000 - 80000310: 0002c103 lbu sp,0(t0) - 80000314: 00200113 li sp,2 - 80000318: 00200e93 li t4,2 - 8000031c: 01200193 li gp,18 - 80000320: 03d11463 bne sp,t4,80000348 - -0000000080000324 : - 80000324: 00002297 auipc t0,0x2 - 80000328: cdc28293 addi t0,t0,-804 # 80002000 - 8000032c: 0002c103 lbu sp,0(t0) - 80000330: 00000013 nop - 80000334: 00200113 li sp,2 - 80000338: 00200e93 li t4,2 - 8000033c: 01300193 li gp,19 - 80000340: 01d11463 bne sp,t4,80000348 - 80000344: 00301c63 bne zero,gp,8000035c - -0000000080000348 : - 80000348: 0ff0000f fence - 8000034c: 00018063 beqz gp,8000034c - 80000350: 00119193 slli gp,gp,0x1 - 80000354: 0011e193 ori gp,gp,1 - 80000358: 00000073 ecall - -000000008000035c : - 8000035c: 0ff0000f fence - 80000360: 00100193 li gp,1 - 80000364: 00000073 ecall - 80000368: c0001073 unimp - 8000036c: 0000 unimp - 8000036e: 0000 unimp - 80000370: 0000 unimp - 80000372: 0000 unimp - 80000374: 0000 unimp - 80000376: 0000 unimp - 80000378: 0000 unimp - 8000037a: 0000 unimp - 8000037c: 0000 unimp - 8000037e: 0000 unimp - 80000380: 0000 unimp - 80000382: 0000 unimp - -Disassembly of section .data: - -0000000080002000 : - 80002000: 0xff - -0000000080002001 : - 80002001: sd s0,32(s0) - -0000000080002002 : - 80002002: addi a2,sp,988 - -0000000080002003 : - 80002003: 0000000f fence unknown,unknown - 80002007: 0000 unimp - 80002009: 0000 unimp - 8000200b: 0000 unimp - 8000200d: 0000 unimp - 8000200f: 00 Address 0x000000008000200f is out of bounds. - diff --git a/test/riscv/tests/rv64ui-p-lbu.elf b/test/riscv/tests/rv64ui-p-lbu.elf deleted file mode 100644 index 14f1586b..00000000 Binary files a/test/riscv/tests/rv64ui-p-lbu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-ld.dump b/test/riscv/tests/rv64ui-p-ld.dump deleted file mode 100644 index dcebe2d6..00000000 --- a/test/riscv/tests/rv64ui-p-ld.dump +++ /dev/null @@ -1,406 +0,0 @@ - -rv64ui-p-ld: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00002097 auipc ra,0x2 - 80000100: f0408093 addi ra,ra,-252 # 80002000 - 80000104: 0000bf03 ld t5,0(ra) - 80000108: 00ff0eb7 lui t4,0xff0 - 8000010c: 0ffe8e9b addiw t4,t4,255 - 80000110: 010e9e93 slli t4,t4,0x10 - 80000114: 0ffe8e93 addi t4,t4,255 # ff00ff <_start-0x7f00ff01> - 80000118: 010e9e93 slli t4,t4,0x10 - 8000011c: 0ffe8e93 addi t4,t4,255 - 80000120: 00200193 li gp,2 - 80000124: 3bdf1263 bne t5,t4,800004c8 - -0000000080000128 : - 80000128: 00002097 auipc ra,0x2 - 8000012c: ed808093 addi ra,ra,-296 # 80002000 - 80000130: 0080bf03 ld t5,8(ra) - 80000134: ff010eb7 lui t4,0xff010 - 80000138: f01e8e9b addiw t4,t4,-255 - 8000013c: 010e9e93 slli t4,t4,0x10 - 80000140: f01e8e93 addi t4,t4,-255 # ffffffffff00ff01 <_end+0xffffffff7f00dee1> - 80000144: 010e9e93 slli t4,t4,0x10 - 80000148: f00e8e93 addi t4,t4,-256 - 8000014c: 00300193 li gp,3 - 80000150: 37df1c63 bne t5,t4,800004c8 - -0000000080000154 : - 80000154: 00002097 auipc ra,0x2 - 80000158: eac08093 addi ra,ra,-340 # 80002000 - 8000015c: 0100bf03 ld t5,16(ra) - 80000160: 00010eb7 lui t4,0x10 - 80000164: f01e8e9b addiw t4,t4,-255 - 80000168: 010e9e93 slli t4,t4,0x10 - 8000016c: f01e8e93 addi t4,t4,-255 # ff01 <_start-0x7fff00ff> - 80000170: 010e9e93 slli t4,t4,0x10 - 80000174: f01e8e93 addi t4,t4,-255 - 80000178: 00ce9e93 slli t4,t4,0xc - 8000017c: ff0e8e93 addi t4,t4,-16 - 80000180: 00400193 li gp,4 - 80000184: 35df1263 bne t5,t4,800004c8 - -0000000080000188 : - 80000188: 00002097 auipc ra,0x2 - 8000018c: e7808093 addi ra,ra,-392 # 80002000 - 80000190: 0180bf03 ld t5,24(ra) - 80000194: ffff0eb7 lui t4,0xffff0 - 80000198: 0ffe8e9b addiw t4,t4,255 - 8000019c: 010e9e93 slli t4,t4,0x10 - 800001a0: 0ffe8e93 addi t4,t4,255 # ffffffffffff00ff <_end+0xffffffff7ffee0df> - 800001a4: 010e9e93 slli t4,t4,0x10 - 800001a8: 0ffe8e93 addi t4,t4,255 - 800001ac: 00ce9e93 slli t4,t4,0xc - 800001b0: 00fe8e93 addi t4,t4,15 - 800001b4: 00500193 li gp,5 - 800001b8: 31df1863 bne t5,t4,800004c8 - -00000000800001bc : - 800001bc: 00002097 auipc ra,0x2 - 800001c0: e5c08093 addi ra,ra,-420 # 80002018 - 800001c4: fe80bf03 ld t5,-24(ra) - 800001c8: 00ff0eb7 lui t4,0xff0 - 800001cc: 0ffe8e9b addiw t4,t4,255 - 800001d0: 010e9e93 slli t4,t4,0x10 - 800001d4: 0ffe8e93 addi t4,t4,255 # ff00ff <_start-0x7f00ff01> - 800001d8: 010e9e93 slli t4,t4,0x10 - 800001dc: 0ffe8e93 addi t4,t4,255 - 800001e0: 00600193 li gp,6 - 800001e4: 2fdf1263 bne t5,t4,800004c8 - -00000000800001e8 : - 800001e8: 00002097 auipc ra,0x2 - 800001ec: e3008093 addi ra,ra,-464 # 80002018 - 800001f0: ff00bf03 ld t5,-16(ra) - 800001f4: ff010eb7 lui t4,0xff010 - 800001f8: f01e8e9b addiw t4,t4,-255 - 800001fc: 010e9e93 slli t4,t4,0x10 - 80000200: f01e8e93 addi t4,t4,-255 # ffffffffff00ff01 <_end+0xffffffff7f00dee1> - 80000204: 010e9e93 slli t4,t4,0x10 - 80000208: f00e8e93 addi t4,t4,-256 - 8000020c: 00700193 li gp,7 - 80000210: 2bdf1c63 bne t5,t4,800004c8 - -0000000080000214 : - 80000214: 00002097 auipc ra,0x2 - 80000218: e0408093 addi ra,ra,-508 # 80002018 - 8000021c: ff80bf03 ld t5,-8(ra) - 80000220: 00010eb7 lui t4,0x10 - 80000224: f01e8e9b addiw t4,t4,-255 - 80000228: 010e9e93 slli t4,t4,0x10 - 8000022c: f01e8e93 addi t4,t4,-255 # ff01 <_start-0x7fff00ff> - 80000230: 010e9e93 slli t4,t4,0x10 - 80000234: f01e8e93 addi t4,t4,-255 - 80000238: 00ce9e93 slli t4,t4,0xc - 8000023c: ff0e8e93 addi t4,t4,-16 - 80000240: 00800193 li gp,8 - 80000244: 29df1263 bne t5,t4,800004c8 - -0000000080000248 : - 80000248: 00002097 auipc ra,0x2 - 8000024c: dd008093 addi ra,ra,-560 # 80002018 - 80000250: 0000bf03 ld t5,0(ra) - 80000254: ffff0eb7 lui t4,0xffff0 - 80000258: 0ffe8e9b addiw t4,t4,255 - 8000025c: 010e9e93 slli t4,t4,0x10 - 80000260: 0ffe8e93 addi t4,t4,255 # ffffffffffff00ff <_end+0xffffffff7ffee0df> - 80000264: 010e9e93 slli t4,t4,0x10 - 80000268: 0ffe8e93 addi t4,t4,255 - 8000026c: 00ce9e93 slli t4,t4,0xc - 80000270: 00fe8e93 addi t4,t4,15 - 80000274: 00900193 li gp,9 - 80000278: 25df1863 bne t5,t4,800004c8 - -000000008000027c : - 8000027c: 00002097 auipc ra,0x2 - 80000280: d8408093 addi ra,ra,-636 # 80002000 - 80000284: fe008093 addi ra,ra,-32 - 80000288: 0200b283 ld t0,32(ra) - 8000028c: 00ff0eb7 lui t4,0xff0 - 80000290: 0ffe8e9b addiw t4,t4,255 - 80000294: 010e9e93 slli t4,t4,0x10 - 80000298: 0ffe8e93 addi t4,t4,255 # ff00ff <_start-0x7f00ff01> - 8000029c: 010e9e93 slli t4,t4,0x10 - 800002a0: 0ffe8e93 addi t4,t4,255 - 800002a4: 00a00193 li gp,10 - 800002a8: 23d29063 bne t0,t4,800004c8 - -00000000800002ac : - 800002ac: 00002097 auipc ra,0x2 - 800002b0: d5408093 addi ra,ra,-684 # 80002000 - 800002b4: ffd08093 addi ra,ra,-3 - 800002b8: 00b0b283 ld t0,11(ra) - 800002bc: ff010eb7 lui t4,0xff010 - 800002c0: f01e8e9b addiw t4,t4,-255 - 800002c4: 010e9e93 slli t4,t4,0x10 - 800002c8: f01e8e93 addi t4,t4,-255 # ffffffffff00ff01 <_end+0xffffffff7f00dee1> - 800002cc: 010e9e93 slli t4,t4,0x10 - 800002d0: f00e8e93 addi t4,t4,-256 - 800002d4: 00b00193 li gp,11 - 800002d8: 1fd29863 bne t0,t4,800004c8 - -00000000800002dc : - 800002dc: 00c00193 li gp,12 - 800002e0: 00000213 li tp,0 - 800002e4: 00002097 auipc ra,0x2 - 800002e8: d2408093 addi ra,ra,-732 # 80002008 - 800002ec: 0080bf03 ld t5,8(ra) - 800002f0: 000f0313 mv t1,t5 - 800002f4: 00010eb7 lui t4,0x10 - 800002f8: f01e8e9b addiw t4,t4,-255 - 800002fc: 010e9e93 slli t4,t4,0x10 - 80000300: f01e8e93 addi t4,t4,-255 # ff01 <_start-0x7fff00ff> - 80000304: 010e9e93 slli t4,t4,0x10 - 80000308: f01e8e93 addi t4,t4,-255 - 8000030c: 00ce9e93 slli t4,t4,0xc - 80000310: ff0e8e93 addi t4,t4,-16 - 80000314: 1bd31a63 bne t1,t4,800004c8 - 80000318: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000031c: 00200293 li t0,2 - 80000320: fc5212e3 bne tp,t0,800002e4 - -0000000080000324 : - 80000324: 00d00193 li gp,13 - 80000328: 00000213 li tp,0 - 8000032c: 00002097 auipc ra,0x2 - 80000330: ce408093 addi ra,ra,-796 # 80002010 - 80000334: 0080bf03 ld t5,8(ra) - 80000338: 00000013 nop - 8000033c: 000f0313 mv t1,t5 - 80000340: ffff0eb7 lui t4,0xffff0 - 80000344: 0ffe8e9b addiw t4,t4,255 - 80000348: 010e9e93 slli t4,t4,0x10 - 8000034c: 0ffe8e93 addi t4,t4,255 # ffffffffffff00ff <_end+0xffffffff7ffee0df> - 80000350: 010e9e93 slli t4,t4,0x10 - 80000354: 0ffe8e93 addi t4,t4,255 - 80000358: 00ce9e93 slli t4,t4,0xc - 8000035c: 00fe8e93 addi t4,t4,15 - 80000360: 17d31463 bne t1,t4,800004c8 - 80000364: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000368: 00200293 li t0,2 - 8000036c: fc5210e3 bne tp,t0,8000032c - -0000000080000370 : - 80000370: 00e00193 li gp,14 - 80000374: 00000213 li tp,0 - 80000378: 00002097 auipc ra,0x2 - 8000037c: c8808093 addi ra,ra,-888 # 80002000 - 80000380: 0080bf03 ld t5,8(ra) - 80000384: 00000013 nop - 80000388: 00000013 nop - 8000038c: 000f0313 mv t1,t5 - 80000390: ff010eb7 lui t4,0xff010 - 80000394: f01e8e9b addiw t4,t4,-255 - 80000398: 010e9e93 slli t4,t4,0x10 - 8000039c: f01e8e93 addi t4,t4,-255 # ffffffffff00ff01 <_end+0xffffffff7f00dee1> - 800003a0: 010e9e93 slli t4,t4,0x10 - 800003a4: f00e8e93 addi t4,t4,-256 - 800003a8: 13d31063 bne t1,t4,800004c8 - 800003ac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003b0: 00200293 li t0,2 - 800003b4: fc5212e3 bne tp,t0,80000378 - -00000000800003b8 : - 800003b8: 00f00193 li gp,15 - 800003bc: 00000213 li tp,0 - 800003c0: 00002097 auipc ra,0x2 - 800003c4: c4808093 addi ra,ra,-952 # 80002008 - 800003c8: 0080bf03 ld t5,8(ra) - 800003cc: 00010eb7 lui t4,0x10 - 800003d0: f01e8e9b addiw t4,t4,-255 - 800003d4: 010e9e93 slli t4,t4,0x10 - 800003d8: f01e8e93 addi t4,t4,-255 # ff01 <_start-0x7fff00ff> - 800003dc: 010e9e93 slli t4,t4,0x10 - 800003e0: f01e8e93 addi t4,t4,-255 - 800003e4: 00ce9e93 slli t4,t4,0xc - 800003e8: ff0e8e93 addi t4,t4,-16 - 800003ec: 0ddf1e63 bne t5,t4,800004c8 - 800003f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003f4: 00200293 li t0,2 - 800003f8: fc5214e3 bne tp,t0,800003c0 - -00000000800003fc : - 800003fc: 01000193 li gp,16 - 80000400: 00000213 li tp,0 - 80000404: 00002097 auipc ra,0x2 - 80000408: c0c08093 addi ra,ra,-1012 # 80002010 - 8000040c: 00000013 nop - 80000410: 0080bf03 ld t5,8(ra) - 80000414: ffff0eb7 lui t4,0xffff0 - 80000418: 0ffe8e9b addiw t4,t4,255 - 8000041c: 010e9e93 slli t4,t4,0x10 - 80000420: 0ffe8e93 addi t4,t4,255 # ffffffffffff00ff <_end+0xffffffff7ffee0df> - 80000424: 010e9e93 slli t4,t4,0x10 - 80000428: 0ffe8e93 addi t4,t4,255 - 8000042c: 00ce9e93 slli t4,t4,0xc - 80000430: 00fe8e93 addi t4,t4,15 - 80000434: 09df1a63 bne t5,t4,800004c8 - 80000438: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000043c: 00200293 li t0,2 - 80000440: fc5212e3 bne tp,t0,80000404 - -0000000080000444 : - 80000444: 01100193 li gp,17 - 80000448: 00000213 li tp,0 - 8000044c: 00002097 auipc ra,0x2 - 80000450: bb408093 addi ra,ra,-1100 # 80002000 - 80000454: 00000013 nop - 80000458: 00000013 nop - 8000045c: 0080bf03 ld t5,8(ra) - 80000460: ff010eb7 lui t4,0xff010 - 80000464: f01e8e9b addiw t4,t4,-255 - 80000468: 010e9e93 slli t4,t4,0x10 - 8000046c: f01e8e93 addi t4,t4,-255 # ffffffffff00ff01 <_end+0xffffffff7f00dee1> - 80000470: 010e9e93 slli t4,t4,0x10 - 80000474: f00e8e93 addi t4,t4,-256 - 80000478: 05df1863 bne t5,t4,800004c8 - 8000047c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000480: 00200293 li t0,2 - 80000484: fc5214e3 bne tp,t0,8000044c - -0000000080000488 : - 80000488: 00002297 auipc t0,0x2 - 8000048c: b7828293 addi t0,t0,-1160 # 80002000 - 80000490: 0002b103 ld sp,0(t0) - 80000494: 00200113 li sp,2 - 80000498: 00200e93 li t4,2 - 8000049c: 01200193 li gp,18 - 800004a0: 03d11463 bne sp,t4,800004c8 - -00000000800004a4 : - 800004a4: 00002297 auipc t0,0x2 - 800004a8: b5c28293 addi t0,t0,-1188 # 80002000 - 800004ac: 0002b103 ld sp,0(t0) - 800004b0: 00000013 nop - 800004b4: 00200113 li sp,2 - 800004b8: 00200e93 li t4,2 - 800004bc: 01300193 li gp,19 - 800004c0: 01d11463 bne sp,t4,800004c8 - 800004c4: 00301c63 bne zero,gp,800004dc - -00000000800004c8 : - 800004c8: 0ff0000f fence - 800004cc: 00018063 beqz gp,800004cc - 800004d0: 00119193 slli gp,gp,0x1 - 800004d4: 0011e193 ori gp,gp,1 - 800004d8: 00000073 ecall - -00000000800004dc : - 800004dc: 0ff0000f fence - 800004e0: 00100193 li gp,1 - 800004e4: 00000073 ecall - 800004e8: c0001073 unimp - 800004ec: 0000 unimp - 800004ee: 0000 unimp - 800004f0: 0000 unimp - 800004f2: 0000 unimp - 800004f4: 0000 unimp - 800004f6: 0000 unimp - 800004f8: 0000 unimp - 800004fa: 0000 unimp - 800004fc: 0000 unimp - 800004fe: 0000 unimp - 80000500: 0000 unimp - 80000502: 0000 unimp - -Disassembly of section .data: - -0000000080002000 : - 80002000: 00ff 0xff - 80002002: 00ff 0xff - 80002004: 00ff 0xff - 80002006: 00ff 0xff - -0000000080002008 : - 80002008: ff00 sd s0,56(a4) - 8000200a: ff00 sd s0,56(a4) - 8000200c: ff00 sd s0,56(a4) - 8000200e: ff00 sd s0,56(a4) - -0000000080002010 : - 80002010: 0ff0 addi a2,sp,988 - 80002012: 0ff0 addi a2,sp,988 - 80002014: 0ff0 addi a2,sp,988 - 80002016: 0ff0 addi a2,sp,988 - -0000000080002018 : - 80002018: f00ff00f 0xf00ff00f - 8000201c: f00ff00f 0xf00ff00f diff --git a/test/riscv/tests/rv64ui-p-ld.elf b/test/riscv/tests/rv64ui-p-ld.elf deleted file mode 100644 index df2a7349..00000000 Binary files a/test/riscv/tests/rv64ui-p-ld.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-lh.dump b/test/riscv/tests/rv64ui-p-lh.dump deleted file mode 100644 index 214e5b07..00000000 --- a/test/riscv/tests/rv64ui-p-lh.dump +++ /dev/null @@ -1,327 +0,0 @@ - -rv64ui-p-lh: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00002097 auipc ra,0x2 - 80000100: f0408093 addi ra,ra,-252 # 80002000 - 80000104: 00009f03 lh t5,0(ra) - 80000108: 0ff00e93 li t4,255 - 8000010c: 00200193 li gp,2 - 80000110: 25df1c63 bne t5,t4,80000368 - -0000000080000114 : - 80000114: 00002097 auipc ra,0x2 - 80000118: eec08093 addi ra,ra,-276 # 80002000 - 8000011c: 00209f03 lh t5,2(ra) - 80000120: f0000e93 li t4,-256 - 80000124: 00300193 li gp,3 - 80000128: 25df1063 bne t5,t4,80000368 - -000000008000012c : - 8000012c: 00002097 auipc ra,0x2 - 80000130: ed408093 addi ra,ra,-300 # 80002000 - 80000134: 00409f03 lh t5,4(ra) - 80000138: 00001eb7 lui t4,0x1 - 8000013c: ff0e8e9b addiw t4,t4,-16 - 80000140: 00400193 li gp,4 - 80000144: 23df1263 bne t5,t4,80000368 - -0000000080000148 : - 80000148: 00002097 auipc ra,0x2 - 8000014c: eb808093 addi ra,ra,-328 # 80002000 - 80000150: 00609f03 lh t5,6(ra) - 80000154: fffffeb7 lui t4,0xfffff - 80000158: 00fe8e9b addiw t4,t4,15 - 8000015c: 00500193 li gp,5 - 80000160: 21df1463 bne t5,t4,80000368 - -0000000080000164 : - 80000164: 00002097 auipc ra,0x2 - 80000168: ea208093 addi ra,ra,-350 # 80002006 - 8000016c: ffa09f03 lh t5,-6(ra) - 80000170: 0ff00e93 li t4,255 - 80000174: 00600193 li gp,6 - 80000178: 1fdf1863 bne t5,t4,80000368 - -000000008000017c : - 8000017c: 00002097 auipc ra,0x2 - 80000180: e8a08093 addi ra,ra,-374 # 80002006 - 80000184: ffc09f03 lh t5,-4(ra) - 80000188: f0000e93 li t4,-256 - 8000018c: 00700193 li gp,7 - 80000190: 1ddf1c63 bne t5,t4,80000368 - -0000000080000194 : - 80000194: 00002097 auipc ra,0x2 - 80000198: e7208093 addi ra,ra,-398 # 80002006 - 8000019c: ffe09f03 lh t5,-2(ra) - 800001a0: 00001eb7 lui t4,0x1 - 800001a4: ff0e8e9b addiw t4,t4,-16 - 800001a8: 00800193 li gp,8 - 800001ac: 1bdf1e63 bne t5,t4,80000368 - -00000000800001b0 : - 800001b0: 00002097 auipc ra,0x2 - 800001b4: e5608093 addi ra,ra,-426 # 80002006 - 800001b8: 00009f03 lh t5,0(ra) - 800001bc: fffffeb7 lui t4,0xfffff - 800001c0: 00fe8e9b addiw t4,t4,15 - 800001c4: 00900193 li gp,9 - 800001c8: 1bdf1063 bne t5,t4,80000368 - -00000000800001cc : - 800001cc: 00002097 auipc ra,0x2 - 800001d0: e3408093 addi ra,ra,-460 # 80002000 - 800001d4: fe008093 addi ra,ra,-32 - 800001d8: 02009283 lh t0,32(ra) - 800001dc: 0ff00e93 li t4,255 - 800001e0: 00a00193 li gp,10 - 800001e4: 19d29263 bne t0,t4,80000368 - -00000000800001e8 : - 800001e8: 00002097 auipc ra,0x2 - 800001ec: e1808093 addi ra,ra,-488 # 80002000 - 800001f0: ffb08093 addi ra,ra,-5 - 800001f4: 00709283 lh t0,7(ra) - 800001f8: f0000e93 li t4,-256 - 800001fc: 00b00193 li gp,11 - 80000200: 17d29463 bne t0,t4,80000368 - -0000000080000204 : - 80000204: 00c00193 li gp,12 - 80000208: 00000213 li tp,0 - 8000020c: 00002097 auipc ra,0x2 - 80000210: df608093 addi ra,ra,-522 # 80002002 - 80000214: 00209f03 lh t5,2(ra) - 80000218: 000f0313 mv t1,t5 - 8000021c: 00001eb7 lui t4,0x1 - 80000220: ff0e8e9b addiw t4,t4,-16 - 80000224: 15d31263 bne t1,t4,80000368 - 80000228: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000022c: 00200293 li t0,2 - 80000230: fc521ee3 bne tp,t0,8000020c - -0000000080000234 : - 80000234: 00d00193 li gp,13 - 80000238: 00000213 li tp,0 - 8000023c: 00002097 auipc ra,0x2 - 80000240: dc808093 addi ra,ra,-568 # 80002004 - 80000244: 00209f03 lh t5,2(ra) - 80000248: 00000013 nop - 8000024c: 000f0313 mv t1,t5 - 80000250: fffffeb7 lui t4,0xfffff - 80000254: 00fe8e9b addiw t4,t4,15 - 80000258: 11d31863 bne t1,t4,80000368 - 8000025c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000260: 00200293 li t0,2 - 80000264: fc521ce3 bne tp,t0,8000023c - -0000000080000268 : - 80000268: 00e00193 li gp,14 - 8000026c: 00000213 li tp,0 - 80000270: 00002097 auipc ra,0x2 - 80000274: d9008093 addi ra,ra,-624 # 80002000 - 80000278: 00209f03 lh t5,2(ra) - 8000027c: 00000013 nop - 80000280: 00000013 nop - 80000284: 000f0313 mv t1,t5 - 80000288: f0000e93 li t4,-256 - 8000028c: 0dd31e63 bne t1,t4,80000368 - 80000290: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000294: 00200293 li t0,2 - 80000298: fc521ce3 bne tp,t0,80000270 - -000000008000029c : - 8000029c: 00f00193 li gp,15 - 800002a0: 00000213 li tp,0 - 800002a4: 00002097 auipc ra,0x2 - 800002a8: d5e08093 addi ra,ra,-674 # 80002002 - 800002ac: 00209f03 lh t5,2(ra) - 800002b0: 00001eb7 lui t4,0x1 - 800002b4: ff0e8e9b addiw t4,t4,-16 - 800002b8: 0bdf1863 bne t5,t4,80000368 - 800002bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002c0: 00200293 li t0,2 - 800002c4: fe5210e3 bne tp,t0,800002a4 - -00000000800002c8 : - 800002c8: 01000193 li gp,16 - 800002cc: 00000213 li tp,0 - 800002d0: 00002097 auipc ra,0x2 - 800002d4: d3408093 addi ra,ra,-716 # 80002004 - 800002d8: 00000013 nop - 800002dc: 00209f03 lh t5,2(ra) - 800002e0: fffffeb7 lui t4,0xfffff - 800002e4: 00fe8e9b addiw t4,t4,15 - 800002e8: 09df1063 bne t5,t4,80000368 - 800002ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002f0: 00200293 li t0,2 - 800002f4: fc521ee3 bne tp,t0,800002d0 - -00000000800002f8 : - 800002f8: 01100193 li gp,17 - 800002fc: 00000213 li tp,0 - 80000300: 00002097 auipc ra,0x2 - 80000304: d0008093 addi ra,ra,-768 # 80002000 - 80000308: 00000013 nop - 8000030c: 00000013 nop - 80000310: 00209f03 lh t5,2(ra) - 80000314: f0000e93 li t4,-256 - 80000318: 05df1863 bne t5,t4,80000368 - 8000031c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000320: 00200293 li t0,2 - 80000324: fc521ee3 bne tp,t0,80000300 - -0000000080000328 : - 80000328: 00002297 auipc t0,0x2 - 8000032c: cd828293 addi t0,t0,-808 # 80002000 - 80000330: 00029103 lh sp,0(t0) - 80000334: 00200113 li sp,2 - 80000338: 00200e93 li t4,2 - 8000033c: 01200193 li gp,18 - 80000340: 03d11463 bne sp,t4,80000368 - -0000000080000344 : - 80000344: 00002297 auipc t0,0x2 - 80000348: cbc28293 addi t0,t0,-836 # 80002000 - 8000034c: 00029103 lh sp,0(t0) - 80000350: 00000013 nop - 80000354: 00200113 li sp,2 - 80000358: 00200e93 li t4,2 - 8000035c: 01300193 li gp,19 - 80000360: 01d11463 bne sp,t4,80000368 - 80000364: 00301c63 bne zero,gp,8000037c - -0000000080000368 : - 80000368: 0ff0000f fence - 8000036c: 00018063 beqz gp,8000036c - 80000370: 00119193 slli gp,gp,0x1 - 80000374: 0011e193 ori gp,gp,1 - 80000378: 00000073 ecall - -000000008000037c : - 8000037c: 0ff0000f fence - 80000380: 00100193 li gp,1 - 80000384: 00000073 ecall - 80000388: c0001073 unimp - 8000038c: 0000 unimp - 8000038e: 0000 unimp - 80000390: 0000 unimp - 80000392: 0000 unimp - 80000394: 0000 unimp - 80000396: 0000 unimp - 80000398: 0000 unimp - 8000039a: 0000 unimp - 8000039c: 0000 unimp - 8000039e: 0000 unimp - 800003a0: 0000 unimp - 800003a2: 0000 unimp - 800003a4: 0000 unimp - 800003a6: 0000 unimp - 800003a8: 0000 unimp - 800003aa: 0000 unimp - 800003ac: 0000 unimp - 800003ae: 0000 unimp - 800003b0: 0000 unimp - 800003b2: 0000 unimp - 800003b4: 0000 unimp - 800003b6: 0000 unimp - 800003b8: 0000 unimp - 800003ba: 0000 unimp - 800003bc: 0000 unimp - 800003be: 0000 unimp - 800003c0: 0000 unimp - 800003c2: 0000 unimp - -Disassembly of section .data: - -0000000080002000 : - 80002000: 00ff 0xff - -0000000080002002 : - 80002002: ff00 sd s0,56(a4) - -0000000080002004 : - 80002004: 0ff0 addi a2,sp,988 - -0000000080002006 : - 80002006: 0000f00f 0xf00f - 8000200a: 0000 unimp - 8000200c: 0000 unimp - 8000200e: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-lh.elf b/test/riscv/tests/rv64ui-p-lh.elf deleted file mode 100644 index fcff462f..00000000 Binary files a/test/riscv/tests/rv64ui-p-lh.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-lhu.dump b/test/riscv/tests/rv64ui-p-lhu.dump deleted file mode 100644 index 6cc3defc..00000000 --- a/test/riscv/tests/rv64ui-p-lhu.dump +++ /dev/null @@ -1,322 +0,0 @@ - -rv64ui-p-lhu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00002097 auipc ra,0x2 - 80000100: f0408093 addi ra,ra,-252 # 80002000 - 80000104: 0000df03 lhu t5,0(ra) - 80000108: 0ff00e93 li t4,255 - 8000010c: 00200193 li gp,2 - 80000110: 27df1663 bne t5,t4,8000037c - -0000000080000114 : - 80000114: 00002097 auipc ra,0x2 - 80000118: eec08093 addi ra,ra,-276 # 80002000 - 8000011c: 0020df03 lhu t5,2(ra) - 80000120: 00010eb7 lui t4,0x10 - 80000124: f00e8e9b addiw t4,t4,-256 - 80000128: 00300193 li gp,3 - 8000012c: 25df1863 bne t5,t4,8000037c - -0000000080000130 : - 80000130: 00002097 auipc ra,0x2 - 80000134: ed008093 addi ra,ra,-304 # 80002000 - 80000138: 0040df03 lhu t5,4(ra) - 8000013c: 00001eb7 lui t4,0x1 - 80000140: ff0e8e9b addiw t4,t4,-16 - 80000144: 00400193 li gp,4 - 80000148: 23df1a63 bne t5,t4,8000037c - -000000008000014c : - 8000014c: 00002097 auipc ra,0x2 - 80000150: eb408093 addi ra,ra,-332 # 80002000 - 80000154: 0060df03 lhu t5,6(ra) - 80000158: 0000feb7 lui t4,0xf - 8000015c: 00fe8e9b addiw t4,t4,15 - 80000160: 00500193 li gp,5 - 80000164: 21df1c63 bne t5,t4,8000037c - -0000000080000168 : - 80000168: 00002097 auipc ra,0x2 - 8000016c: e9e08093 addi ra,ra,-354 # 80002006 - 80000170: ffa0df03 lhu t5,-6(ra) - 80000174: 0ff00e93 li t4,255 - 80000178: 00600193 li gp,6 - 8000017c: 21df1063 bne t5,t4,8000037c - -0000000080000180 : - 80000180: 00002097 auipc ra,0x2 - 80000184: e8608093 addi ra,ra,-378 # 80002006 - 80000188: ffc0df03 lhu t5,-4(ra) - 8000018c: 00010eb7 lui t4,0x10 - 80000190: f00e8e9b addiw t4,t4,-256 - 80000194: 00700193 li gp,7 - 80000198: 1fdf1263 bne t5,t4,8000037c - -000000008000019c : - 8000019c: 00002097 auipc ra,0x2 - 800001a0: e6a08093 addi ra,ra,-406 # 80002006 - 800001a4: ffe0df03 lhu t5,-2(ra) - 800001a8: 00001eb7 lui t4,0x1 - 800001ac: ff0e8e9b addiw t4,t4,-16 - 800001b0: 00800193 li gp,8 - 800001b4: 1ddf1463 bne t5,t4,8000037c - -00000000800001b8 : - 800001b8: 00002097 auipc ra,0x2 - 800001bc: e4e08093 addi ra,ra,-434 # 80002006 - 800001c0: 0000df03 lhu t5,0(ra) - 800001c4: 0000feb7 lui t4,0xf - 800001c8: 00fe8e9b addiw t4,t4,15 - 800001cc: 00900193 li gp,9 - 800001d0: 1bdf1663 bne t5,t4,8000037c - -00000000800001d4 : - 800001d4: 00002097 auipc ra,0x2 - 800001d8: e2c08093 addi ra,ra,-468 # 80002000 - 800001dc: fe008093 addi ra,ra,-32 - 800001e0: 0200d283 lhu t0,32(ra) - 800001e4: 0ff00e93 li t4,255 - 800001e8: 00a00193 li gp,10 - 800001ec: 19d29863 bne t0,t4,8000037c - -00000000800001f0 : - 800001f0: 00002097 auipc ra,0x2 - 800001f4: e1008093 addi ra,ra,-496 # 80002000 - 800001f8: ffb08093 addi ra,ra,-5 - 800001fc: 0070d283 lhu t0,7(ra) - 80000200: 00010eb7 lui t4,0x10 - 80000204: f00e8e9b addiw t4,t4,-256 - 80000208: 00b00193 li gp,11 - 8000020c: 17d29863 bne t0,t4,8000037c - -0000000080000210 : - 80000210: 00c00193 li gp,12 - 80000214: 00000213 li tp,0 - 80000218: 00002097 auipc ra,0x2 - 8000021c: dea08093 addi ra,ra,-534 # 80002002 - 80000220: 0020df03 lhu t5,2(ra) - 80000224: 000f0313 mv t1,t5 - 80000228: 00001eb7 lui t4,0x1 - 8000022c: ff0e8e9b addiw t4,t4,-16 - 80000230: 15d31663 bne t1,t4,8000037c - 80000234: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000238: 00200293 li t0,2 - 8000023c: fc521ee3 bne tp,t0,80000218 - -0000000080000240 : - 80000240: 00d00193 li gp,13 - 80000244: 00000213 li tp,0 - 80000248: 00002097 auipc ra,0x2 - 8000024c: dbc08093 addi ra,ra,-580 # 80002004 - 80000250: 0020df03 lhu t5,2(ra) - 80000254: 00000013 nop - 80000258: 000f0313 mv t1,t5 - 8000025c: 0000feb7 lui t4,0xf - 80000260: 00fe8e9b addiw t4,t4,15 - 80000264: 11d31c63 bne t1,t4,8000037c - 80000268: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000026c: 00200293 li t0,2 - 80000270: fc521ce3 bne tp,t0,80000248 - -0000000080000274 : - 80000274: 00e00193 li gp,14 - 80000278: 00000213 li tp,0 - 8000027c: 00002097 auipc ra,0x2 - 80000280: d8408093 addi ra,ra,-636 # 80002000 - 80000284: 0020df03 lhu t5,2(ra) - 80000288: 00000013 nop - 8000028c: 00000013 nop - 80000290: 000f0313 mv t1,t5 - 80000294: 00010eb7 lui t4,0x10 - 80000298: f00e8e9b addiw t4,t4,-256 - 8000029c: 0fd31063 bne t1,t4,8000037c - 800002a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002a4: 00200293 li t0,2 - 800002a8: fc521ae3 bne tp,t0,8000027c - -00000000800002ac : - 800002ac: 00f00193 li gp,15 - 800002b0: 00000213 li tp,0 - 800002b4: 00002097 auipc ra,0x2 - 800002b8: d4e08093 addi ra,ra,-690 # 80002002 - 800002bc: 0020df03 lhu t5,2(ra) - 800002c0: 00001eb7 lui t4,0x1 - 800002c4: ff0e8e9b addiw t4,t4,-16 - 800002c8: 0bdf1a63 bne t5,t4,8000037c - 800002cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002d0: 00200293 li t0,2 - 800002d4: fe5210e3 bne tp,t0,800002b4 - -00000000800002d8 : - 800002d8: 01000193 li gp,16 - 800002dc: 00000213 li tp,0 - 800002e0: 00002097 auipc ra,0x2 - 800002e4: d2408093 addi ra,ra,-732 # 80002004 - 800002e8: 00000013 nop - 800002ec: 0020df03 lhu t5,2(ra) - 800002f0: 0000feb7 lui t4,0xf - 800002f4: 00fe8e9b addiw t4,t4,15 - 800002f8: 09df1263 bne t5,t4,8000037c - 800002fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000300: 00200293 li t0,2 - 80000304: fc521ee3 bne tp,t0,800002e0 - -0000000080000308 : - 80000308: 01100193 li gp,17 - 8000030c: 00000213 li tp,0 - 80000310: 00002097 auipc ra,0x2 - 80000314: cf008093 addi ra,ra,-784 # 80002000 - 80000318: 00000013 nop - 8000031c: 00000013 nop - 80000320: 0020df03 lhu t5,2(ra) - 80000324: 00010eb7 lui t4,0x10 - 80000328: f00e8e9b addiw t4,t4,-256 - 8000032c: 05df1863 bne t5,t4,8000037c - 80000330: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000334: 00200293 li t0,2 - 80000338: fc521ce3 bne tp,t0,80000310 - -000000008000033c : - 8000033c: 00002297 auipc t0,0x2 - 80000340: cc428293 addi t0,t0,-828 # 80002000 - 80000344: 0002d103 lhu sp,0(t0) - 80000348: 00200113 li sp,2 - 8000034c: 00200e93 li t4,2 - 80000350: 01200193 li gp,18 - 80000354: 03d11463 bne sp,t4,8000037c - -0000000080000358 : - 80000358: 00002297 auipc t0,0x2 - 8000035c: ca828293 addi t0,t0,-856 # 80002000 - 80000360: 0002d103 lhu sp,0(t0) - 80000364: 00000013 nop - 80000368: 00200113 li sp,2 - 8000036c: 00200e93 li t4,2 - 80000370: 01300193 li gp,19 - 80000374: 01d11463 bne sp,t4,8000037c - 80000378: 00301c63 bne zero,gp,80000390 - -000000008000037c : - 8000037c: 0ff0000f fence - 80000380: 00018063 beqz gp,80000380 - 80000384: 00119193 slli gp,gp,0x1 - 80000388: 0011e193 ori gp,gp,1 - 8000038c: 00000073 ecall - -0000000080000390 : - 80000390: 0ff0000f fence - 80000394: 00100193 li gp,1 - 80000398: 00000073 ecall - 8000039c: c0001073 unimp - 800003a0: 0000 unimp - 800003a2: 0000 unimp - 800003a4: 0000 unimp - 800003a6: 0000 unimp - 800003a8: 0000 unimp - 800003aa: 0000 unimp - 800003ac: 0000 unimp - 800003ae: 0000 unimp - 800003b0: 0000 unimp - 800003b2: 0000 unimp - 800003b4: 0000 unimp - 800003b6: 0000 unimp - 800003b8: 0000 unimp - 800003ba: 0000 unimp - 800003bc: 0000 unimp - 800003be: 0000 unimp - 800003c0: 0000 unimp - 800003c2: 0000 unimp - -Disassembly of section .data: - -0000000080002000 : - 80002000: 00ff 0xff - -0000000080002002 : - 80002002: ff00 sd s0,56(a4) - -0000000080002004 : - 80002004: 0ff0 addi a2,sp,988 - -0000000080002006 : - 80002006: 0000f00f 0xf00f - 8000200a: 0000 unimp - 8000200c: 0000 unimp - 8000200e: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-lhu.elf b/test/riscv/tests/rv64ui-p-lhu.elf deleted file mode 100644 index 78bb0e92..00000000 Binary files a/test/riscv/tests/rv64ui-p-lhu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-lui.dump b/test/riscv/tests/rv64ui-p-lui.dump deleted file mode 100644 index 329a3c5d..00000000 --- a/test/riscv/tests/rv64ui-p-lui.dump +++ /dev/null @@ -1,127 +0,0 @@ - -rv64ui-p-lui: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 000000b7 lui ra,0x0 - 80000100: 00000e93 li t4,0 - 80000104: 00200193 li gp,2 - 80000108: 05d09a63 bne ra,t4,8000015c - -000000008000010c : - 8000010c: fffff0b7 lui ra,0xfffff - 80000110: 4010d093 srai ra,ra,0x1 - 80000114: 80000e93 li t4,-2048 - 80000118: 00300193 li gp,3 - 8000011c: 05d09063 bne ra,t4,8000015c - -0000000080000120 : - 80000120: 7ffff0b7 lui ra,0x7ffff - 80000124: 4140d093 srai ra,ra,0x14 - 80000128: 7ff00e93 li t4,2047 - 8000012c: 00400193 li gp,4 - 80000130: 03d09663 bne ra,t4,8000015c - -0000000080000134 : - 80000134: 800000b7 lui ra,0x80000 - 80000138: 4140d093 srai ra,ra,0x14 - 8000013c: 80000e93 li t4,-2048 - 80000140: 00500193 li gp,5 - 80000144: 01d09c63 bne ra,t4,8000015c - -0000000080000148 : - 80000148: 80000037 lui zero,0x80000 - 8000014c: 00000e93 li t4,0 - 80000150: 00600193 li gp,6 - 80000154: 01d01463 bne zero,t4,8000015c - 80000158: 00301c63 bne zero,gp,80000170 - -000000008000015c : - 8000015c: 0ff0000f fence - 80000160: 00018063 beqz gp,80000160 - 80000164: 00119193 slli gp,gp,0x1 - 80000168: 0011e193 ori gp,gp,1 - 8000016c: 00000073 ecall - -0000000080000170 : - 80000170: 0ff0000f fence - 80000174: 00100193 li gp,1 - 80000178: 00000073 ecall - 8000017c: c0001073 unimp - 80000180: 0000 unimp - 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-lui.elf b/test/riscv/tests/rv64ui-p-lui.elf deleted file mode 100644 index 67dfe10e..00000000 Binary files a/test/riscv/tests/rv64ui-p-lui.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-lw.dump b/test/riscv/tests/rv64ui-p-lw.dump deleted file mode 100644 index 889c4521..00000000 --- a/test/riscv/tests/rv64ui-p-lw.dump +++ /dev/null @@ -1,319 +0,0 @@ - -rv64ui-p-lw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00002097 auipc ra,0x2 - 80000100: f0408093 addi ra,ra,-252 # 80002000 - 80000104: 0000af03 lw t5,0(ra) - 80000108: 00ff0eb7 lui t4,0xff0 - 8000010c: 0ffe8e9b addiw t4,t4,255 - 80000110: 00200193 li gp,2 - 80000114: 27df1a63 bne t5,t4,80000388 - -0000000080000118 : - 80000118: 00002097 auipc ra,0x2 - 8000011c: ee808093 addi ra,ra,-280 # 80002000 - 80000120: 0040af03 lw t5,4(ra) - 80000124: ff010eb7 lui t4,0xff010 - 80000128: f00e8e9b addiw t4,t4,-256 - 8000012c: 00300193 li gp,3 - 80000130: 25df1c63 bne t5,t4,80000388 - -0000000080000134 : - 80000134: 00002097 auipc ra,0x2 - 80000138: ecc08093 addi ra,ra,-308 # 80002000 - 8000013c: 0080af03 lw t5,8(ra) - 80000140: 0ff01eb7 lui t4,0xff01 - 80000144: ff0e8e9b addiw t4,t4,-16 - 80000148: 00400193 li gp,4 - 8000014c: 23df1e63 bne t5,t4,80000388 - -0000000080000150 : - 80000150: 00002097 auipc ra,0x2 - 80000154: eb008093 addi ra,ra,-336 # 80002000 - 80000158: 00c0af03 lw t5,12(ra) - 8000015c: f00ffeb7 lui t4,0xf00ff - 80000160: 00fe8e9b addiw t4,t4,15 - 80000164: 00500193 li gp,5 - 80000168: 23df1063 bne t5,t4,80000388 - -000000008000016c : - 8000016c: 00002097 auipc ra,0x2 - 80000170: ea008093 addi ra,ra,-352 # 8000200c - 80000174: ff40af03 lw t5,-12(ra) - 80000178: 00ff0eb7 lui t4,0xff0 - 8000017c: 0ffe8e9b addiw t4,t4,255 - 80000180: 00600193 li gp,6 - 80000184: 21df1263 bne t5,t4,80000388 - -0000000080000188 : - 80000188: 00002097 auipc ra,0x2 - 8000018c: e8408093 addi ra,ra,-380 # 8000200c - 80000190: ff80af03 lw t5,-8(ra) - 80000194: ff010eb7 lui t4,0xff010 - 80000198: f00e8e9b addiw t4,t4,-256 - 8000019c: 00700193 li gp,7 - 800001a0: 1fdf1463 bne t5,t4,80000388 - -00000000800001a4 : - 800001a4: 00002097 auipc ra,0x2 - 800001a8: e6808093 addi ra,ra,-408 # 8000200c - 800001ac: ffc0af03 lw t5,-4(ra) - 800001b0: 0ff01eb7 lui t4,0xff01 - 800001b4: ff0e8e9b addiw t4,t4,-16 - 800001b8: 00800193 li gp,8 - 800001bc: 1ddf1663 bne t5,t4,80000388 - -00000000800001c0 : - 800001c0: 00002097 auipc ra,0x2 - 800001c4: e4c08093 addi ra,ra,-436 # 8000200c - 800001c8: 0000af03 lw t5,0(ra) - 800001cc: f00ffeb7 lui t4,0xf00ff - 800001d0: 00fe8e9b addiw t4,t4,15 - 800001d4: 00900193 li gp,9 - 800001d8: 1bdf1863 bne t5,t4,80000388 - -00000000800001dc : - 800001dc: 00002097 auipc ra,0x2 - 800001e0: e2408093 addi ra,ra,-476 # 80002000 - 800001e4: fe008093 addi ra,ra,-32 - 800001e8: 0200a283 lw t0,32(ra) - 800001ec: 00ff0eb7 lui t4,0xff0 - 800001f0: 0ffe8e9b addiw t4,t4,255 - 800001f4: 00a00193 li gp,10 - 800001f8: 19d29863 bne t0,t4,80000388 - -00000000800001fc : - 800001fc: 00002097 auipc ra,0x2 - 80000200: e0408093 addi ra,ra,-508 # 80002000 - 80000204: ffd08093 addi ra,ra,-3 - 80000208: 0070a283 lw t0,7(ra) - 8000020c: ff010eb7 lui t4,0xff010 - 80000210: f00e8e9b addiw t4,t4,-256 - 80000214: 00b00193 li gp,11 - 80000218: 17d29863 bne t0,t4,80000388 - -000000008000021c : - 8000021c: 00c00193 li gp,12 - 80000220: 00000213 li tp,0 - 80000224: 00002097 auipc ra,0x2 - 80000228: de008093 addi ra,ra,-544 # 80002004 - 8000022c: 0040af03 lw t5,4(ra) - 80000230: 000f0313 mv t1,t5 - 80000234: 0ff01eb7 lui t4,0xff01 - 80000238: ff0e8e9b addiw t4,t4,-16 - 8000023c: 15d31663 bne t1,t4,80000388 - 80000240: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000244: 00200293 li t0,2 - 80000248: fc521ee3 bne tp,t0,80000224 - -000000008000024c : - 8000024c: 00d00193 li gp,13 - 80000250: 00000213 li tp,0 - 80000254: 00002097 auipc ra,0x2 - 80000258: db408093 addi ra,ra,-588 # 80002008 - 8000025c: 0040af03 lw t5,4(ra) - 80000260: 00000013 nop - 80000264: 000f0313 mv t1,t5 - 80000268: f00ffeb7 lui t4,0xf00ff - 8000026c: 00fe8e9b addiw t4,t4,15 - 80000270: 11d31c63 bne t1,t4,80000388 - 80000274: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000278: 00200293 li t0,2 - 8000027c: fc521ce3 bne tp,t0,80000254 - -0000000080000280 : - 80000280: 00e00193 li gp,14 - 80000284: 00000213 li tp,0 - 80000288: 00002097 auipc ra,0x2 - 8000028c: d7808093 addi ra,ra,-648 # 80002000 - 80000290: 0040af03 lw t5,4(ra) - 80000294: 00000013 nop - 80000298: 00000013 nop - 8000029c: 000f0313 mv t1,t5 - 800002a0: ff010eb7 lui t4,0xff010 - 800002a4: f00e8e9b addiw t4,t4,-256 - 800002a8: 0fd31063 bne t1,t4,80000388 - 800002ac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002b0: 00200293 li t0,2 - 800002b4: fc521ae3 bne tp,t0,80000288 - -00000000800002b8 : - 800002b8: 00f00193 li gp,15 - 800002bc: 00000213 li tp,0 - 800002c0: 00002097 auipc ra,0x2 - 800002c4: d4408093 addi ra,ra,-700 # 80002004 - 800002c8: 0040af03 lw t5,4(ra) - 800002cc: 0ff01eb7 lui t4,0xff01 - 800002d0: ff0e8e9b addiw t4,t4,-16 - 800002d4: 0bdf1a63 bne t5,t4,80000388 - 800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002dc: 00200293 li t0,2 - 800002e0: fe5210e3 bne tp,t0,800002c0 - -00000000800002e4 : - 800002e4: 01000193 li gp,16 - 800002e8: 00000213 li tp,0 - 800002ec: 00002097 auipc ra,0x2 - 800002f0: d1c08093 addi ra,ra,-740 # 80002008 - 800002f4: 00000013 nop - 800002f8: 0040af03 lw t5,4(ra) - 800002fc: f00ffeb7 lui t4,0xf00ff - 80000300: 00fe8e9b addiw t4,t4,15 - 80000304: 09df1263 bne t5,t4,80000388 - 80000308: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000030c: 00200293 li t0,2 - 80000310: fc521ee3 bne tp,t0,800002ec - -0000000080000314 : - 80000314: 01100193 li gp,17 - 80000318: 00000213 li tp,0 - 8000031c: 00002097 auipc ra,0x2 - 80000320: ce408093 addi ra,ra,-796 # 80002000 - 80000324: 00000013 nop - 80000328: 00000013 nop - 8000032c: 0040af03 lw t5,4(ra) - 80000330: ff010eb7 lui t4,0xff010 - 80000334: f00e8e9b addiw t4,t4,-256 - 80000338: 05df1863 bne t5,t4,80000388 - 8000033c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000340: 00200293 li t0,2 - 80000344: fc521ce3 bne tp,t0,8000031c - -0000000080000348 : - 80000348: 00002297 auipc t0,0x2 - 8000034c: cb828293 addi t0,t0,-840 # 80002000 - 80000350: 0002a103 lw sp,0(t0) - 80000354: 00200113 li sp,2 - 80000358: 00200e93 li t4,2 - 8000035c: 01200193 li gp,18 - 80000360: 03d11463 bne sp,t4,80000388 - -0000000080000364 : - 80000364: 00002297 auipc t0,0x2 - 80000368: c9c28293 addi t0,t0,-868 # 80002000 - 8000036c: 0002a103 lw sp,0(t0) - 80000370: 00000013 nop - 80000374: 00200113 li sp,2 - 80000378: 00200e93 li t4,2 - 8000037c: 01300193 li gp,19 - 80000380: 01d11463 bne sp,t4,80000388 - 80000384: 00301c63 bne zero,gp,8000039c - -0000000080000388 : - 80000388: 0ff0000f fence - 8000038c: 00018063 beqz gp,8000038c - 80000390: 00119193 slli gp,gp,0x1 - 80000394: 0011e193 ori gp,gp,1 - 80000398: 00000073 ecall - -000000008000039c : - 8000039c: 0ff0000f fence - 800003a0: 00100193 li gp,1 - 800003a4: 00000073 ecall - 800003a8: c0001073 unimp - 800003ac: 0000 unimp - 800003ae: 0000 unimp - 800003b0: 0000 unimp - 800003b2: 0000 unimp - 800003b4: 0000 unimp - 800003b6: 0000 unimp - 800003b8: 0000 unimp - 800003ba: 0000 unimp - 800003bc: 0000 unimp - 800003be: 0000 unimp - 800003c0: 0000 unimp - 800003c2: 0000 unimp - -Disassembly of section .data: - -0000000080002000 : - 80002000: 00ff 0xff - 80002002: 00ff 0xff - -0000000080002004 : - 80002004: ff00 sd s0,56(a4) - 80002006: ff00 sd s0,56(a4) - -0000000080002008 : - 80002008: 0ff0 addi a2,sp,988 - 8000200a: 0ff0 addi a2,sp,988 - -000000008000200c : - 8000200c: f00ff00f 0xf00ff00f diff --git a/test/riscv/tests/rv64ui-p-lw.elf b/test/riscv/tests/rv64ui-p-lw.elf deleted file mode 100644 index 714ae850..00000000 Binary files a/test/riscv/tests/rv64ui-p-lw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-lwu.dump b/test/riscv/tests/rv64ui-p-lwu.dump deleted file mode 100644 index 21f50ee3..00000000 --- a/test/riscv/tests/rv64ui-p-lwu.dump +++ /dev/null @@ -1,333 +0,0 @@ - -rv64ui-p-lwu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00002097 auipc ra,0x2 - 80000100: f0408093 addi ra,ra,-252 # 80002000 - 80000104: 0000ef03 lwu t5,0(ra) - 80000108: 00ff0eb7 lui t4,0xff0 - 8000010c: 0ffe8e9b addiw t4,t4,255 - 80000110: 00200193 li gp,2 - 80000114: 2bdf1e63 bne t5,t4,800003d0 - -0000000080000118 : - 80000118: 00002097 auipc ra,0x2 - 8000011c: ee808093 addi ra,ra,-280 # 80002000 - 80000120: 0040ef03 lwu t5,4(ra) - 80000124: 00010eb7 lui t4,0x10 - 80000128: f01e8e9b addiw t4,t4,-255 - 8000012c: 010e9e93 slli t4,t4,0x10 - 80000130: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80000134: 00300193 li gp,3 - 80000138: 29df1c63 bne t5,t4,800003d0 - -000000008000013c : - 8000013c: 00002097 auipc ra,0x2 - 80000140: ec408093 addi ra,ra,-316 # 80002000 - 80000144: 0080ef03 lwu t5,8(ra) - 80000148: 0ff01eb7 lui t4,0xff01 - 8000014c: ff0e8e9b addiw t4,t4,-16 - 80000150: 00400193 li gp,4 - 80000154: 27df1e63 bne t5,t4,800003d0 - -0000000080000158 : - 80000158: 00002097 auipc ra,0x2 - 8000015c: ea808093 addi ra,ra,-344 # 80002000 - 80000160: 00c0ef03 lwu t5,12(ra) - 80000164: 000f0eb7 lui t4,0xf0 - 80000168: 0ffe8e9b addiw t4,t4,255 - 8000016c: 00ce9e93 slli t4,t4,0xc - 80000170: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 80000174: 00500193 li gp,5 - 80000178: 25df1c63 bne t5,t4,800003d0 - -000000008000017c : - 8000017c: 00002097 auipc ra,0x2 - 80000180: e9008093 addi ra,ra,-368 # 8000200c - 80000184: ff40ef03 lwu t5,-12(ra) - 80000188: 00ff0eb7 lui t4,0xff0 - 8000018c: 0ffe8e9b addiw t4,t4,255 - 80000190: 00600193 li gp,6 - 80000194: 23df1e63 bne t5,t4,800003d0 - -0000000080000198 : - 80000198: 00002097 auipc ra,0x2 - 8000019c: e7408093 addi ra,ra,-396 # 8000200c - 800001a0: ff80ef03 lwu t5,-8(ra) - 800001a4: 00010eb7 lui t4,0x10 - 800001a8: f01e8e9b addiw t4,t4,-255 - 800001ac: 010e9e93 slli t4,t4,0x10 - 800001b0: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 800001b4: 00700193 li gp,7 - 800001b8: 21df1c63 bne t5,t4,800003d0 - -00000000800001bc : - 800001bc: 00002097 auipc ra,0x2 - 800001c0: e5008093 addi ra,ra,-432 # 8000200c - 800001c4: ffc0ef03 lwu t5,-4(ra) - 800001c8: 0ff01eb7 lui t4,0xff01 - 800001cc: ff0e8e9b addiw t4,t4,-16 - 800001d0: 00800193 li gp,8 - 800001d4: 1fdf1e63 bne t5,t4,800003d0 - -00000000800001d8 : - 800001d8: 00002097 auipc ra,0x2 - 800001dc: e3408093 addi ra,ra,-460 # 8000200c - 800001e0: 0000ef03 lwu t5,0(ra) - 800001e4: 000f0eb7 lui t4,0xf0 - 800001e8: 0ffe8e9b addiw t4,t4,255 - 800001ec: 00ce9e93 slli t4,t4,0xc - 800001f0: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 800001f4: 00900193 li gp,9 - 800001f8: 1ddf1c63 bne t5,t4,800003d0 - -00000000800001fc : - 800001fc: 00002097 auipc ra,0x2 - 80000200: e0408093 addi ra,ra,-508 # 80002000 - 80000204: fe008093 addi ra,ra,-32 - 80000208: 0200e283 lwu t0,32(ra) - 8000020c: 00ff0eb7 lui t4,0xff0 - 80000210: 0ffe8e9b addiw t4,t4,255 - 80000214: 00a00193 li gp,10 - 80000218: 1bd29c63 bne t0,t4,800003d0 - -000000008000021c : - 8000021c: 00002097 auipc ra,0x2 - 80000220: de408093 addi ra,ra,-540 # 80002000 - 80000224: ffd08093 addi ra,ra,-3 - 80000228: 0070e283 lwu t0,7(ra) - 8000022c: 00010eb7 lui t4,0x10 - 80000230: f01e8e9b addiw t4,t4,-255 - 80000234: 010e9e93 slli t4,t4,0x10 - 80000238: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 8000023c: 00b00193 li gp,11 - 80000240: 19d29863 bne t0,t4,800003d0 - -0000000080000244 : - 80000244: 00c00193 li gp,12 - 80000248: 00000213 li tp,0 - 8000024c: 00002097 auipc ra,0x2 - 80000250: db808093 addi ra,ra,-584 # 80002004 - 80000254: 0040ef03 lwu t5,4(ra) - 80000258: 000f0313 mv t1,t5 - 8000025c: 0ff01eb7 lui t4,0xff01 - 80000260: ff0e8e9b addiw t4,t4,-16 - 80000264: 17d31663 bne t1,t4,800003d0 - 80000268: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000026c: 00200293 li t0,2 - 80000270: fc521ee3 bne tp,t0,8000024c - -0000000080000274 : - 80000274: 00d00193 li gp,13 - 80000278: 00000213 li tp,0 - 8000027c: 00002097 auipc ra,0x2 - 80000280: d8c08093 addi ra,ra,-628 # 80002008 - 80000284: 0040ef03 lwu t5,4(ra) - 80000288: 00000013 nop - 8000028c: 000f0313 mv t1,t5 - 80000290: 000f0eb7 lui t4,0xf0 - 80000294: 0ffe8e9b addiw t4,t4,255 - 80000298: 00ce9e93 slli t4,t4,0xc - 8000029c: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 800002a0: 13d31863 bne t1,t4,800003d0 - 800002a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002a8: 00200293 li t0,2 - 800002ac: fc5218e3 bne tp,t0,8000027c - -00000000800002b0 : - 800002b0: 00e00193 li gp,14 - 800002b4: 00000213 li tp,0 - 800002b8: 00002097 auipc ra,0x2 - 800002bc: d4808093 addi ra,ra,-696 # 80002000 - 800002c0: 0040ef03 lwu t5,4(ra) - 800002c4: 00000013 nop - 800002c8: 00000013 nop - 800002cc: 000f0313 mv t1,t5 - 800002d0: 00010eb7 lui t4,0x10 - 800002d4: f01e8e9b addiw t4,t4,-255 - 800002d8: 010e9e93 slli t4,t4,0x10 - 800002dc: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 800002e0: 0fd31863 bne t1,t4,800003d0 - 800002e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002e8: 00200293 li t0,2 - 800002ec: fc5216e3 bne tp,t0,800002b8 - -00000000800002f0 : - 800002f0: 00f00193 li gp,15 - 800002f4: 00000213 li tp,0 - 800002f8: 00002097 auipc ra,0x2 - 800002fc: d0c08093 addi ra,ra,-756 # 80002004 - 80000300: 0040ef03 lwu t5,4(ra) - 80000304: 0ff01eb7 lui t4,0xff01 - 80000308: ff0e8e9b addiw t4,t4,-16 - 8000030c: 0ddf1263 bne t5,t4,800003d0 - 80000310: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000314: 00200293 li t0,2 - 80000318: fe5210e3 bne tp,t0,800002f8 - -000000008000031c : - 8000031c: 01000193 li gp,16 - 80000320: 00000213 li tp,0 - 80000324: 00002097 auipc ra,0x2 - 80000328: ce408093 addi ra,ra,-796 # 80002008 - 8000032c: 00000013 nop - 80000330: 0040ef03 lwu t5,4(ra) - 80000334: 000f0eb7 lui t4,0xf0 - 80000338: 0ffe8e9b addiw t4,t4,255 - 8000033c: 00ce9e93 slli t4,t4,0xc - 80000340: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 80000344: 09df1663 bne t5,t4,800003d0 - 80000348: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000034c: 00200293 li t0,2 - 80000350: fc521ae3 bne tp,t0,80000324 - -0000000080000354 : - 80000354: 01100193 li gp,17 - 80000358: 00000213 li tp,0 - 8000035c: 00002097 auipc ra,0x2 - 80000360: ca408093 addi ra,ra,-860 # 80002000 - 80000364: 00000013 nop - 80000368: 00000013 nop - 8000036c: 0040ef03 lwu t5,4(ra) - 80000370: 00010eb7 lui t4,0x10 - 80000374: f01e8e9b addiw t4,t4,-255 - 80000378: 010e9e93 slli t4,t4,0x10 - 8000037c: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80000380: 05df1863 bne t5,t4,800003d0 - 80000384: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000388: 00200293 li t0,2 - 8000038c: fc5218e3 bne tp,t0,8000035c - -0000000080000390 : - 80000390: 00002297 auipc t0,0x2 - 80000394: c7028293 addi t0,t0,-912 # 80002000 - 80000398: 0002e103 lwu sp,0(t0) - 8000039c: 00200113 li sp,2 - 800003a0: 00200e93 li t4,2 - 800003a4: 01200193 li gp,18 - 800003a8: 03d11463 bne sp,t4,800003d0 - -00000000800003ac : - 800003ac: 00002297 auipc t0,0x2 - 800003b0: c5428293 addi t0,t0,-940 # 80002000 - 800003b4: 0002e103 lwu sp,0(t0) - 800003b8: 00000013 nop - 800003bc: 00200113 li sp,2 - 800003c0: 00200e93 li t4,2 - 800003c4: 01300193 li gp,19 - 800003c8: 01d11463 bne sp,t4,800003d0 - 800003cc: 00301c63 bne zero,gp,800003e4 - -00000000800003d0 : - 800003d0: 0ff0000f fence - 800003d4: 00018063 beqz gp,800003d4 - 800003d8: 00119193 slli gp,gp,0x1 - 800003dc: 0011e193 ori gp,gp,1 - 800003e0: 00000073 ecall - -00000000800003e4 : - 800003e4: 0ff0000f fence - 800003e8: 00100193 li gp,1 - 800003ec: 00000073 ecall - 800003f0: c0001073 unimp - 800003f4: 0000 unimp - 800003f6: 0000 unimp - 800003f8: 0000 unimp - 800003fa: 0000 unimp - 800003fc: 0000 unimp - 800003fe: 0000 unimp - 80000400: 0000 unimp - 80000402: 0000 unimp - -Disassembly of section .data: - -0000000080002000 : - 80002000: 00ff 0xff - 80002002: 00ff 0xff - -0000000080002004 : - 80002004: ff00 sd s0,56(a4) - 80002006: ff00 sd s0,56(a4) - -0000000080002008 : - 80002008: 0ff0 addi a2,sp,988 - 8000200a: 0ff0 addi a2,sp,988 - -000000008000200c : - 8000200c: f00ff00f 0xf00ff00f diff --git a/test/riscv/tests/rv64ui-p-lwu.elf b/test/riscv/tests/rv64ui-p-lwu.elf deleted file mode 100644 index de88bd29..00000000 Binary files a/test/riscv/tests/rv64ui-p-lwu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-or.dump b/test/riscv/tests/rv64ui-p-or.dump deleted file mode 100644 index 4ca0b79b..00000000 --- a/test/riscv/tests/rv64ui-p-or.dump +++ /dev/null @@ -1,522 +0,0 @@ - -rv64ui-p-or: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 000100b7 lui ra,0x10 - 80000100: f010809b addiw ra,ra,-255 - 80000104: 01009093 slli ra,ra,0x10 - 80000108: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 8000010c: 0f0f1137 lui sp,0xf0f1 - 80000110: f0f1011b addiw sp,sp,-241 - 80000114: 0020ef33 or t5,ra,sp - 80000118: 00001eb7 lui t4,0x1 - 8000011c: ff1e8e9b addiw t4,t4,-15 - 80000120: 014e9e93 slli t4,t4,0x14 - 80000124: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> - 80000128: 00200193 li gp,2 - 8000012c: 5bdf1663 bne t5,t4,800006d8 - -0000000080000130 : - 80000130: 0ff010b7 lui ra,0xff01 - 80000134: ff00809b addiw ra,ra,-16 - 80000138: 000f1137 lui sp,0xf1 - 8000013c: f0f1011b addiw sp,sp,-241 - 80000140: 00c11113 slli sp,sp,0xc - 80000144: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80000148: 0020ef33 or t5,ra,sp - 8000014c: 00010eb7 lui t4,0x10 - 80000150: ff1e8e9b addiw t4,t4,-15 - 80000154: 010e9e93 slli t4,t4,0x10 - 80000158: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> - 8000015c: 00300193 li gp,3 - 80000160: 57df1c63 bne t5,t4,800006d8 - -0000000080000164 : - 80000164: 00ff00b7 lui ra,0xff0 - 80000168: 0ff0809b addiw ra,ra,255 - 8000016c: 0f0f1137 lui sp,0xf0f1 - 80000170: f0f1011b addiw sp,sp,-241 - 80000174: 0020ef33 or t5,ra,sp - 80000178: 0fff1eb7 lui t4,0xfff1 - 8000017c: fffe8e9b addiw t4,t4,-1 - 80000180: 00400193 li gp,4 - 80000184: 55df1a63 bne t5,t4,800006d8 - -0000000080000188 : - 80000188: 000f00b7 lui ra,0xf0 - 8000018c: 0ff0809b addiw ra,ra,255 - 80000190: 00c09093 slli ra,ra,0xc - 80000194: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> - 80000198: 000f1137 lui sp,0xf1 - 8000019c: f0f1011b addiw sp,sp,-241 - 800001a0: 00c11113 slli sp,sp,0xc - 800001a4: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 800001a8: 0020ef33 or t5,ra,sp - 800001ac: 000f1eb7 lui t4,0xf1 - 800001b0: fffe8e9b addiw t4,t4,-1 - 800001b4: 00ce9e93 slli t4,t4,0xc - 800001b8: 0ffe8e93 addi t4,t4,255 # f10ff <_start-0x7ff0ef01> - 800001bc: 00500193 li gp,5 - 800001c0: 51df1c63 bne t5,t4,800006d8 - -00000000800001c4 : - 800001c4: 000100b7 lui ra,0x10 - 800001c8: f010809b addiw ra,ra,-255 - 800001cc: 01009093 slli ra,ra,0x10 - 800001d0: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 800001d4: 0f0f1137 lui sp,0xf0f1 - 800001d8: f0f1011b addiw sp,sp,-241 - 800001dc: 0020e0b3 or ra,ra,sp - 800001e0: 00001eb7 lui t4,0x1 - 800001e4: ff1e8e9b addiw t4,t4,-15 - 800001e8: 014e9e93 slli t4,t4,0x14 - 800001ec: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> - 800001f0: 00600193 li gp,6 - 800001f4: 4fd09263 bne ra,t4,800006d8 - -00000000800001f8 : - 800001f8: 000100b7 lui ra,0x10 - 800001fc: f010809b addiw ra,ra,-255 - 80000200: 01009093 slli ra,ra,0x10 - 80000204: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80000208: 0f0f1137 lui sp,0xf0f1 - 8000020c: f0f1011b addiw sp,sp,-241 - 80000210: 0020e133 or sp,ra,sp - 80000214: 00001eb7 lui t4,0x1 - 80000218: ff1e8e9b addiw t4,t4,-15 - 8000021c: 014e9e93 slli t4,t4,0x14 - 80000220: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> - 80000224: 00700193 li gp,7 - 80000228: 4bd11863 bne sp,t4,800006d8 - -000000008000022c : - 8000022c: 000100b7 lui ra,0x10 - 80000230: f010809b addiw ra,ra,-255 - 80000234: 01009093 slli ra,ra,0x10 - 80000238: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 8000023c: 0010e0b3 or ra,ra,ra - 80000240: 00010eb7 lui t4,0x10 - 80000244: f01e8e9b addiw t4,t4,-255 - 80000248: 010e9e93 slli t4,t4,0x10 - 8000024c: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80000250: 00800193 li gp,8 - 80000254: 49d09263 bne ra,t4,800006d8 - -0000000080000258 : - 80000258: 00000213 li tp,0 - 8000025c: 000100b7 lui ra,0x10 - 80000260: f010809b addiw ra,ra,-255 - 80000264: 01009093 slli ra,ra,0x10 - 80000268: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 8000026c: 0f0f1137 lui sp,0xf0f1 - 80000270: f0f1011b addiw sp,sp,-241 - 80000274: 0020ef33 or t5,ra,sp - 80000278: 000f0313 mv t1,t5 - 8000027c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000280: 00200293 li t0,2 - 80000284: fc521ce3 bne tp,t0,8000025c - 80000288: 00001eb7 lui t4,0x1 - 8000028c: ff1e8e9b addiw t4,t4,-15 - 80000290: 014e9e93 slli t4,t4,0x14 - 80000294: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> - 80000298: 00900193 li gp,9 - 8000029c: 43d31e63 bne t1,t4,800006d8 - -00000000800002a0 : - 800002a0: 00000213 li tp,0 - 800002a4: 0ff010b7 lui ra,0xff01 - 800002a8: ff00809b addiw ra,ra,-16 - 800002ac: 000f1137 lui sp,0xf1 - 800002b0: f0f1011b addiw sp,sp,-241 - 800002b4: 00c11113 slli sp,sp,0xc - 800002b8: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 800002bc: 0020ef33 or t5,ra,sp - 800002c0: 00000013 nop - 800002c4: 000f0313 mv t1,t5 - 800002c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002cc: 00200293 li t0,2 - 800002d0: fc521ae3 bne tp,t0,800002a4 - 800002d4: 00010eb7 lui t4,0x10 - 800002d8: ff1e8e9b addiw t4,t4,-15 - 800002dc: 010e9e93 slli t4,t4,0x10 - 800002e0: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> - 800002e4: 00a00193 li gp,10 - 800002e8: 3fd31863 bne t1,t4,800006d8 - -00000000800002ec : - 800002ec: 00000213 li tp,0 - 800002f0: 00ff00b7 lui ra,0xff0 - 800002f4: 0ff0809b addiw ra,ra,255 - 800002f8: 0f0f1137 lui sp,0xf0f1 - 800002fc: f0f1011b addiw sp,sp,-241 - 80000300: 0020ef33 or t5,ra,sp - 80000304: 00000013 nop - 80000308: 00000013 nop - 8000030c: 000f0313 mv t1,t5 - 80000310: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000314: 00200293 li t0,2 - 80000318: fc521ce3 bne tp,t0,800002f0 - 8000031c: 0fff1eb7 lui t4,0xfff1 - 80000320: fffe8e9b addiw t4,t4,-1 - 80000324: 00b00193 li gp,11 - 80000328: 3bd31863 bne t1,t4,800006d8 - -000000008000032c : - 8000032c: 00000213 li tp,0 - 80000330: 000100b7 lui ra,0x10 - 80000334: f010809b addiw ra,ra,-255 - 80000338: 01009093 slli ra,ra,0x10 - 8000033c: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80000340: 0f0f1137 lui sp,0xf0f1 - 80000344: f0f1011b addiw sp,sp,-241 - 80000348: 0020ef33 or t5,ra,sp - 8000034c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000350: 00200293 li t0,2 - 80000354: fc521ee3 bne tp,t0,80000330 - 80000358: 00001eb7 lui t4,0x1 - 8000035c: ff1e8e9b addiw t4,t4,-15 - 80000360: 014e9e93 slli t4,t4,0x14 - 80000364: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> - 80000368: 00c00193 li gp,12 - 8000036c: 37df1663 bne t5,t4,800006d8 - -0000000080000370 : - 80000370: 00000213 li tp,0 - 80000374: 0ff010b7 lui ra,0xff01 - 80000378: ff00809b addiw ra,ra,-16 - 8000037c: 000f1137 lui sp,0xf1 - 80000380: f0f1011b addiw sp,sp,-241 - 80000384: 00c11113 slli sp,sp,0xc - 80000388: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 8000038c: 00000013 nop - 80000390: 0020ef33 or t5,ra,sp - 80000394: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000398: 00200293 li t0,2 - 8000039c: fc521ce3 bne tp,t0,80000374 - 800003a0: 00010eb7 lui t4,0x10 - 800003a4: ff1e8e9b addiw t4,t4,-15 - 800003a8: 010e9e93 slli t4,t4,0x10 - 800003ac: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> - 800003b0: 00d00193 li gp,13 - 800003b4: 33df1263 bne t5,t4,800006d8 - -00000000800003b8 : - 800003b8: 00000213 li tp,0 - 800003bc: 00ff00b7 lui ra,0xff0 - 800003c0: 0ff0809b addiw ra,ra,255 - 800003c4: 0f0f1137 lui sp,0xf0f1 - 800003c8: f0f1011b addiw sp,sp,-241 - 800003cc: 00000013 nop - 800003d0: 00000013 nop - 800003d4: 0020ef33 or t5,ra,sp - 800003d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003dc: 00200293 li t0,2 - 800003e0: fc521ee3 bne tp,t0,800003bc - 800003e4: 0fff1eb7 lui t4,0xfff1 - 800003e8: fffe8e9b addiw t4,t4,-1 - 800003ec: 00e00193 li gp,14 - 800003f0: 2fdf1463 bne t5,t4,800006d8 - -00000000800003f4 : - 800003f4: 00000213 li tp,0 - 800003f8: 000100b7 lui ra,0x10 - 800003fc: f010809b addiw ra,ra,-255 - 80000400: 01009093 slli ra,ra,0x10 - 80000404: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80000408: 00000013 nop - 8000040c: 0f0f1137 lui sp,0xf0f1 - 80000410: f0f1011b addiw sp,sp,-241 - 80000414: 0020ef33 or t5,ra,sp - 80000418: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000041c: 00200293 li t0,2 - 80000420: fc521ce3 bne tp,t0,800003f8 - 80000424: 00001eb7 lui t4,0x1 - 80000428: ff1e8e9b addiw t4,t4,-15 - 8000042c: 014e9e93 slli t4,t4,0x14 - 80000430: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> - 80000434: 00f00193 li gp,15 - 80000438: 2bdf1063 bne t5,t4,800006d8 - -000000008000043c : - 8000043c: 00000213 li tp,0 - 80000440: 0ff010b7 lui ra,0xff01 - 80000444: ff00809b addiw ra,ra,-16 - 80000448: 00000013 nop - 8000044c: 000f1137 lui sp,0xf1 - 80000450: f0f1011b addiw sp,sp,-241 - 80000454: 00c11113 slli sp,sp,0xc - 80000458: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 8000045c: 00000013 nop - 80000460: 0020ef33 or t5,ra,sp - 80000464: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000468: 00200293 li t0,2 - 8000046c: fc521ae3 bne tp,t0,80000440 - 80000470: 00010eb7 lui t4,0x10 - 80000474: ff1e8e9b addiw t4,t4,-15 - 80000478: 010e9e93 slli t4,t4,0x10 - 8000047c: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> - 80000480: 01000193 li gp,16 - 80000484: 25df1a63 bne t5,t4,800006d8 - -0000000080000488 : - 80000488: 00000213 li tp,0 - 8000048c: 00ff00b7 lui ra,0xff0 - 80000490: 0ff0809b addiw ra,ra,255 - 80000494: 00000013 nop - 80000498: 00000013 nop - 8000049c: 0f0f1137 lui sp,0xf0f1 - 800004a0: f0f1011b addiw sp,sp,-241 - 800004a4: 0020ef33 or t5,ra,sp - 800004a8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004ac: 00200293 li t0,2 - 800004b0: fc521ee3 bne tp,t0,8000048c - 800004b4: 0fff1eb7 lui t4,0xfff1 - 800004b8: fffe8e9b addiw t4,t4,-1 - 800004bc: 01100193 li gp,17 - 800004c0: 21df1c63 bne t5,t4,800006d8 - -00000000800004c4 : - 800004c4: 00000213 li tp,0 - 800004c8: 0f0f1137 lui sp,0xf0f1 - 800004cc: f0f1011b addiw sp,sp,-241 - 800004d0: 000100b7 lui ra,0x10 - 800004d4: f010809b addiw ra,ra,-255 - 800004d8: 01009093 slli ra,ra,0x10 - 800004dc: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 800004e0: 0020ef33 or t5,ra,sp - 800004e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004e8: 00200293 li t0,2 - 800004ec: fc521ee3 bne tp,t0,800004c8 - 800004f0: 00001eb7 lui t4,0x1 - 800004f4: ff1e8e9b addiw t4,t4,-15 - 800004f8: 014e9e93 slli t4,t4,0x14 - 800004fc: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> - 80000500: 01200193 li gp,18 - 80000504: 1ddf1a63 bne t5,t4,800006d8 - -0000000080000508 : - 80000508: 00000213 li tp,0 - 8000050c: 000f1137 lui sp,0xf1 - 80000510: f0f1011b addiw sp,sp,-241 - 80000514: 00c11113 slli sp,sp,0xc - 80000518: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 8000051c: 0ff010b7 lui ra,0xff01 - 80000520: ff00809b addiw ra,ra,-16 - 80000524: 00000013 nop - 80000528: 0020ef33 or t5,ra,sp - 8000052c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000530: 00200293 li t0,2 - 80000534: fc521ce3 bne tp,t0,8000050c - 80000538: 00010eb7 lui t4,0x10 - 8000053c: ff1e8e9b addiw t4,t4,-15 - 80000540: 010e9e93 slli t4,t4,0x10 - 80000544: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> - 80000548: 01300193 li gp,19 - 8000054c: 19df1663 bne t5,t4,800006d8 - -0000000080000550 : - 80000550: 00000213 li tp,0 - 80000554: 0f0f1137 lui sp,0xf0f1 - 80000558: f0f1011b addiw sp,sp,-241 - 8000055c: 00ff00b7 lui ra,0xff0 - 80000560: 0ff0809b addiw ra,ra,255 - 80000564: 00000013 nop - 80000568: 00000013 nop - 8000056c: 0020ef33 or t5,ra,sp - 80000570: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000574: 00200293 li t0,2 - 80000578: fc521ee3 bne tp,t0,80000554 - 8000057c: 0fff1eb7 lui t4,0xfff1 - 80000580: fffe8e9b addiw t4,t4,-1 - 80000584: 01400193 li gp,20 - 80000588: 15df1863 bne t5,t4,800006d8 - -000000008000058c : - 8000058c: 00000213 li tp,0 - 80000590: 0f0f1137 lui sp,0xf0f1 - 80000594: f0f1011b addiw sp,sp,-241 - 80000598: 00000013 nop - 8000059c: 000100b7 lui ra,0x10 - 800005a0: f010809b addiw ra,ra,-255 - 800005a4: 01009093 slli ra,ra,0x10 - 800005a8: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 800005ac: 0020ef33 or t5,ra,sp - 800005b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800005b4: 00200293 li t0,2 - 800005b8: fc521ce3 bne tp,t0,80000590 - 800005bc: 00001eb7 lui t4,0x1 - 800005c0: ff1e8e9b addiw t4,t4,-15 - 800005c4: 014e9e93 slli t4,t4,0x14 - 800005c8: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> - 800005cc: 01500193 li gp,21 - 800005d0: 11df1463 bne t5,t4,800006d8 - -00000000800005d4 : - 800005d4: 00000213 li tp,0 - 800005d8: 000f1137 lui sp,0xf1 - 800005dc: f0f1011b addiw sp,sp,-241 - 800005e0: 00c11113 slli sp,sp,0xc - 800005e4: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 800005e8: 00000013 nop - 800005ec: 0ff010b7 lui ra,0xff01 - 800005f0: ff00809b addiw ra,ra,-16 - 800005f4: 00000013 nop - 800005f8: 0020ef33 or t5,ra,sp - 800005fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000600: 00200293 li t0,2 - 80000604: fc521ae3 bne tp,t0,800005d8 - 80000608: 00010eb7 lui t4,0x10 - 8000060c: ff1e8e9b addiw t4,t4,-15 - 80000610: 010e9e93 slli t4,t4,0x10 - 80000614: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> - 80000618: 01600193 li gp,22 - 8000061c: 0bdf1e63 bne t5,t4,800006d8 - -0000000080000620 : - 80000620: 00000213 li tp,0 - 80000624: 0f0f1137 lui sp,0xf0f1 - 80000628: f0f1011b addiw sp,sp,-241 - 8000062c: 00000013 nop - 80000630: 00000013 nop - 80000634: 00ff00b7 lui ra,0xff0 - 80000638: 0ff0809b addiw ra,ra,255 - 8000063c: 0020ef33 or t5,ra,sp - 80000640: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000644: 00200293 li t0,2 - 80000648: fc521ee3 bne tp,t0,80000624 - 8000064c: 0fff1eb7 lui t4,0xfff1 - 80000650: fffe8e9b addiw t4,t4,-1 - 80000654: 01700193 li gp,23 - 80000658: 09df1063 bne t5,t4,800006d8 - -000000008000065c : - 8000065c: 000100b7 lui ra,0x10 - 80000660: f010809b addiw ra,ra,-255 - 80000664: 01009093 slli ra,ra,0x10 - 80000668: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 8000066c: 00106133 or sp,zero,ra - 80000670: 00010eb7 lui t4,0x10 - 80000674: f01e8e9b addiw t4,t4,-255 - 80000678: 010e9e93 slli t4,t4,0x10 - 8000067c: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80000680: 01800193 li gp,24 - 80000684: 05d11a63 bne sp,t4,800006d8 - -0000000080000688 : - 80000688: 00ff00b7 lui ra,0xff0 - 8000068c: 0ff0809b addiw ra,ra,255 - 80000690: 0000e133 or sp,ra,zero - 80000694: 00ff0eb7 lui t4,0xff0 - 80000698: 0ffe8e9b addiw t4,t4,255 - 8000069c: 01900193 li gp,25 - 800006a0: 03d11c63 bne sp,t4,800006d8 - -00000000800006a4 : - 800006a4: 000060b3 or ra,zero,zero - 800006a8: 00000e93 li t4,0 - 800006ac: 01a00193 li gp,26 - 800006b0: 03d09463 bne ra,t4,800006d8 - -00000000800006b4 : - 800006b4: 111110b7 lui ra,0x11111 - 800006b8: 1110809b addiw ra,ra,273 - 800006bc: 22222137 lui sp,0x22222 - 800006c0: 2221011b addiw sp,sp,546 - 800006c4: 0020e033 or zero,ra,sp - 800006c8: 00000e93 li t4,0 - 800006cc: 01b00193 li gp,27 - 800006d0: 01d01463 bne zero,t4,800006d8 - 800006d4: 00301c63 bne zero,gp,800006ec - -00000000800006d8 : - 800006d8: 0ff0000f fence - 800006dc: 00018063 beqz gp,800006dc - 800006e0: 00119193 slli gp,gp,0x1 - 800006e4: 0011e193 ori gp,gp,1 - 800006e8: 00000073 ecall - -00000000800006ec : - 800006ec: 0ff0000f fence - 800006f0: 00100193 li gp,1 - 800006f4: 00000073 ecall - 800006f8: c0001073 unimp - 800006fc: 0000 unimp - 800006fe: 0000 unimp - 80000700: 0000 unimp - 80000702: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-or.elf b/test/riscv/tests/rv64ui-p-or.elf deleted file mode 100644 index fbd5299f..00000000 Binary files a/test/riscv/tests/rv64ui-p-or.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-ori.dump b/test/riscv/tests/rv64ui-p-ori.dump deleted file mode 100644 index c49630b2..00000000 --- a/test/riscv/tests/rv64ui-p-ori.dump +++ /dev/null @@ -1,268 +0,0 @@ - -rv64ui-p-ori: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: ff0100b7 lui ra,0xff010 - 80000100: f000809b addiw ra,ra,-256 - 80000104: f0f0ef13 ori t5,ra,-241 - 80000108: f0f00e93 li t4,-241 - 8000010c: 00200193 li gp,2 - 80000110: 1ddf1c63 bne t5,t4,800002e8 - -0000000080000114 : - 80000114: 0ff010b7 lui ra,0xff01 - 80000118: ff00809b addiw ra,ra,-16 - 8000011c: 0f00ef13 ori t5,ra,240 - 80000120: 0ff01eb7 lui t4,0xff01 - 80000124: ff0e8e9b addiw t4,t4,-16 - 80000128: 00300193 li gp,3 - 8000012c: 1bdf1e63 bne t5,t4,800002e8 - -0000000080000130 : - 80000130: 00ff00b7 lui ra,0xff0 - 80000134: 0ff0809b addiw ra,ra,255 - 80000138: 70f0ef13 ori t5,ra,1807 - 8000013c: 00ff0eb7 lui t4,0xff0 - 80000140: 7ffe8e9b addiw t4,t4,2047 - 80000144: 00400193 li gp,4 - 80000148: 1bdf1063 bne t5,t4,800002e8 - -000000008000014c : - 8000014c: f00ff0b7 lui ra,0xf00ff - 80000150: 00f0809b addiw ra,ra,15 - 80000154: 0f00ef13 ori t5,ra,240 - 80000158: f00ffeb7 lui t4,0xf00ff - 8000015c: 0ffe8e9b addiw t4,t4,255 - 80000160: 00500193 li gp,5 - 80000164: 19df1263 bne t5,t4,800002e8 - -0000000080000168 : - 80000168: 000100b7 lui ra,0x10 - 8000016c: f010809b addiw ra,ra,-255 - 80000170: 01009093 slli ra,ra,0x10 - 80000174: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80000178: 0f00e093 ori ra,ra,240 - 8000017c: 00010eb7 lui t4,0x10 - 80000180: f01e8e9b addiw t4,t4,-255 - 80000184: 010e9e93 slli t4,t4,0x10 - 80000188: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> - 8000018c: 00600193 li gp,6 - 80000190: 15d09c63 bne ra,t4,800002e8 - -0000000080000194 : - 80000194: 00000213 li tp,0 - 80000198: 0ff010b7 lui ra,0xff01 - 8000019c: ff00809b addiw ra,ra,-16 - 800001a0: 0f00ef13 ori t5,ra,240 - 800001a4: 000f0313 mv t1,t5 - 800001a8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800001ac: 00200293 li t0,2 - 800001b0: fe5214e3 bne tp,t0,80000198 - 800001b4: 0ff01eb7 lui t4,0xff01 - 800001b8: ff0e8e9b addiw t4,t4,-16 - 800001bc: 00700193 li gp,7 - 800001c0: 13d31463 bne t1,t4,800002e8 - -00000000800001c4 : - 800001c4: 00000213 li tp,0 - 800001c8: 00ff00b7 lui ra,0xff0 - 800001cc: 0ff0809b addiw ra,ra,255 - 800001d0: 70f0ef13 ori t5,ra,1807 - 800001d4: 00000013 nop - 800001d8: 000f0313 mv t1,t5 - 800001dc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800001e0: 00200293 li t0,2 - 800001e4: fe5212e3 bne tp,t0,800001c8 - 800001e8: 00ff0eb7 lui t4,0xff0 - 800001ec: 7ffe8e9b addiw t4,t4,2047 - 800001f0: 00800193 li gp,8 - 800001f4: 0fd31a63 bne t1,t4,800002e8 - -00000000800001f8 : - 800001f8: 00000213 li tp,0 - 800001fc: f00ff0b7 lui ra,0xf00ff - 80000200: 00f0809b addiw ra,ra,15 - 80000204: 0f00ef13 ori t5,ra,240 - 80000208: 00000013 nop - 8000020c: 00000013 nop - 80000210: 000f0313 mv t1,t5 - 80000214: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000218: 00200293 li t0,2 - 8000021c: fe5210e3 bne tp,t0,800001fc - 80000220: f00ffeb7 lui t4,0xf00ff - 80000224: 0ffe8e9b addiw t4,t4,255 - 80000228: 00900193 li gp,9 - 8000022c: 0bd31e63 bne t1,t4,800002e8 - -0000000080000230 : - 80000230: 00000213 li tp,0 - 80000234: 0ff010b7 lui ra,0xff01 - 80000238: ff00809b addiw ra,ra,-16 - 8000023c: 0f00ef13 ori t5,ra,240 - 80000240: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000244: 00200293 li t0,2 - 80000248: fe5216e3 bne tp,t0,80000234 - 8000024c: 0ff01eb7 lui t4,0xff01 - 80000250: ff0e8e9b addiw t4,t4,-16 - 80000254: 00a00193 li gp,10 - 80000258: 09df1863 bne t5,t4,800002e8 - -000000008000025c : - 8000025c: 00000213 li tp,0 - 80000260: 00ff00b7 lui ra,0xff0 - 80000264: 0ff0809b addiw ra,ra,255 - 80000268: 00000013 nop - 8000026c: f0f0ef13 ori t5,ra,-241 - 80000270: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000274: 00200293 li t0,2 - 80000278: fe5214e3 bne tp,t0,80000260 - 8000027c: fff00e93 li t4,-1 - 80000280: 00b00193 li gp,11 - 80000284: 07df1263 bne t5,t4,800002e8 - -0000000080000288 : - 80000288: 00000213 li tp,0 - 8000028c: f00ff0b7 lui ra,0xf00ff - 80000290: 00f0809b addiw ra,ra,15 - 80000294: 00000013 nop - 80000298: 00000013 nop - 8000029c: 0f00ef13 ori t5,ra,240 - 800002a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002a4: 00200293 li t0,2 - 800002a8: fe5212e3 bne tp,t0,8000028c - 800002ac: f00ffeb7 lui t4,0xf00ff - 800002b0: 0ffe8e9b addiw t4,t4,255 - 800002b4: 00c00193 li gp,12 - 800002b8: 03df1863 bne t5,t4,800002e8 - -00000000800002bc : - 800002bc: 0f006093 ori ra,zero,240 - 800002c0: 0f000e93 li t4,240 - 800002c4: 00d00193 li gp,13 - 800002c8: 03d09063 bne ra,t4,800002e8 - -00000000800002cc : - 800002cc: 00ff00b7 lui ra,0xff0 - 800002d0: 0ff0809b addiw ra,ra,255 - 800002d4: 70f0e013 ori zero,ra,1807 - 800002d8: 00000e93 li t4,0 - 800002dc: 00e00193 li gp,14 - 800002e0: 01d01463 bne zero,t4,800002e8 - 800002e4: 00301c63 bne zero,gp,800002fc - -00000000800002e8 : - 800002e8: 0ff0000f fence - 800002ec: 00018063 beqz gp,800002ec - 800002f0: 00119193 slli gp,gp,0x1 - 800002f4: 0011e193 ori gp,gp,1 - 800002f8: 00000073 ecall - -00000000800002fc : - 800002fc: 0ff0000f fence - 80000300: 00100193 li gp,1 - 80000304: 00000073 ecall - 80000308: c0001073 unimp - 8000030c: 0000 unimp - 8000030e: 0000 unimp - 80000310: 0000 unimp - 80000312: 0000 unimp - 80000314: 0000 unimp - 80000316: 0000 unimp - 80000318: 0000 unimp - 8000031a: 0000 unimp - 8000031c: 0000 unimp - 8000031e: 0000 unimp - 80000320: 0000 unimp - 80000322: 0000 unimp - 80000324: 0000 unimp - 80000326: 0000 unimp - 80000328: 0000 unimp - 8000032a: 0000 unimp - 8000032c: 0000 unimp - 8000032e: 0000 unimp - 80000330: 0000 unimp - 80000332: 0000 unimp - 80000334: 0000 unimp - 80000336: 0000 unimp - 80000338: 0000 unimp - 8000033a: 0000 unimp - 8000033c: 0000 unimp - 8000033e: 0000 unimp - 80000340: 0000 unimp - 80000342: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-ori.elf b/test/riscv/tests/rv64ui-p-ori.elf deleted file mode 100644 index 81868c2b..00000000 Binary files a/test/riscv/tests/rv64ui-p-ori.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-sb.dump b/test/riscv/tests/rv64ui-p-sb.dump deleted file mode 100644 index 5bf111f7..00000000 --- a/test/riscv/tests/rv64ui-p-sb.dump +++ /dev/null @@ -1,447 +0,0 @@ - -rv64ui-p-sb: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00002097 auipc ra,0x2 - 80000100: f0408093 addi ra,ra,-252 # 80002000 - 80000104: faa00113 li sp,-86 - 80000108: 00208023 sb sp,0(ra) - 8000010c: 00008f03 lb t5,0(ra) - 80000110: faa00e93 li t4,-86 - 80000114: 00200193 li gp,2 - 80000118: 3ddf1c63 bne t5,t4,800004f0 - -000000008000011c : - 8000011c: 00002097 auipc ra,0x2 - 80000120: ee408093 addi ra,ra,-284 # 80002000 - 80000124: 00000113 li sp,0 - 80000128: 002080a3 sb sp,1(ra) - 8000012c: 00108f03 lb t5,1(ra) - 80000130: 00000e93 li t4,0 - 80000134: 00300193 li gp,3 - 80000138: 3bdf1c63 bne t5,t4,800004f0 - -000000008000013c : - 8000013c: 00002097 auipc ra,0x2 - 80000140: ec408093 addi ra,ra,-316 # 80002000 - 80000144: fffff137 lui sp,0xfffff - 80000148: fa01011b addiw sp,sp,-96 - 8000014c: 00208123 sb sp,2(ra) - 80000150: 00209f03 lh t5,2(ra) - 80000154: fffffeb7 lui t4,0xfffff - 80000158: fa0e8e9b addiw t4,t4,-96 - 8000015c: 00400193 li gp,4 - 80000160: 39df1863 bne t5,t4,800004f0 - -0000000080000164 : - 80000164: 00002097 auipc ra,0x2 - 80000168: e9c08093 addi ra,ra,-356 # 80002000 - 8000016c: 00a00113 li sp,10 - 80000170: 002081a3 sb sp,3(ra) - 80000174: 00308f03 lb t5,3(ra) - 80000178: 00a00e93 li t4,10 - 8000017c: 00500193 li gp,5 - 80000180: 37df1863 bne t5,t4,800004f0 - -0000000080000184 : - 80000184: 00002097 auipc ra,0x2 - 80000188: e8308093 addi ra,ra,-381 # 80002007 - 8000018c: faa00113 li sp,-86 - 80000190: fe208ea3 sb sp,-3(ra) - 80000194: ffd08f03 lb t5,-3(ra) - 80000198: faa00e93 li t4,-86 - 8000019c: 00600193 li gp,6 - 800001a0: 35df1863 bne t5,t4,800004f0 - -00000000800001a4 : - 800001a4: 00002097 auipc ra,0x2 - 800001a8: e6308093 addi ra,ra,-413 # 80002007 - 800001ac: 00000113 li sp,0 - 800001b0: fe208f23 sb sp,-2(ra) - 800001b4: ffe08f03 lb t5,-2(ra) - 800001b8: 00000e93 li t4,0 - 800001bc: 00700193 li gp,7 - 800001c0: 33df1863 bne t5,t4,800004f0 - -00000000800001c4 : - 800001c4: 00002097 auipc ra,0x2 - 800001c8: e4308093 addi ra,ra,-445 # 80002007 - 800001cc: fa000113 li sp,-96 - 800001d0: fe208fa3 sb sp,-1(ra) - 800001d4: fff08f03 lb t5,-1(ra) - 800001d8: fa000e93 li t4,-96 - 800001dc: 00800193 li gp,8 - 800001e0: 31df1863 bne t5,t4,800004f0 - -00000000800001e4 : - 800001e4: 00002097 auipc ra,0x2 - 800001e8: e2308093 addi ra,ra,-477 # 80002007 - 800001ec: 00a00113 li sp,10 - 800001f0: 00208023 sb sp,0(ra) - 800001f4: 00008f03 lb t5,0(ra) - 800001f8: 00a00e93 li t4,10 - 800001fc: 00900193 li gp,9 - 80000200: 2fdf1863 bne t5,t4,800004f0 - -0000000080000204 : - 80000204: 00002097 auipc ra,0x2 - 80000208: e0408093 addi ra,ra,-508 # 80002008 - 8000020c: 12345137 lui sp,0x12345 - 80000210: 6781011b addiw sp,sp,1656 - 80000214: fe008213 addi tp,ra,-32 - 80000218: 02220023 sb sp,32(tp) # 20 <_start-0x7fffffe0> - 8000021c: 00008283 lb t0,0(ra) - 80000220: 07800e93 li t4,120 - 80000224: 00a00193 li gp,10 - 80000228: 2dd29463 bne t0,t4,800004f0 - -000000008000022c : - 8000022c: 00002097 auipc ra,0x2 - 80000230: ddc08093 addi ra,ra,-548 # 80002008 - 80000234: 00003137 lui sp,0x3 - 80000238: 0981011b addiw sp,sp,152 - 8000023c: ffa08093 addi ra,ra,-6 - 80000240: 002083a3 sb sp,7(ra) - 80000244: 00002217 auipc tp,0x2 - 80000248: dc520213 addi tp,tp,-571 # 80002009 - 8000024c: 00020283 lb t0,0(tp) # 0 <_start-0x80000000> - 80000250: f9800e93 li t4,-104 - 80000254: 00b00193 li gp,11 - 80000258: 29d29c63 bne t0,t4,800004f0 - -000000008000025c : - 8000025c: 00c00193 li gp,12 - 80000260: 00000213 li tp,0 - 80000264: fdd00093 li ra,-35 - 80000268: 00002117 auipc sp,0x2 - 8000026c: d9810113 addi sp,sp,-616 # 80002000 - 80000270: 00110023 sb ra,0(sp) - 80000274: 00010f03 lb t5,0(sp) - 80000278: fdd00e93 li t4,-35 - 8000027c: 27df1a63 bne t5,t4,800004f0 - 80000280: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000284: 00200293 li t0,2 - 80000288: fc521ee3 bne tp,t0,80000264 - -000000008000028c : - 8000028c: 00d00193 li gp,13 - 80000290: 00000213 li tp,0 - 80000294: fcd00093 li ra,-51 - 80000298: 00002117 auipc sp,0x2 - 8000029c: d6810113 addi sp,sp,-664 # 80002000 - 800002a0: 00000013 nop - 800002a4: 001100a3 sb ra,1(sp) - 800002a8: 00110f03 lb t5,1(sp) - 800002ac: fcd00e93 li t4,-51 - 800002b0: 25df1063 bne t5,t4,800004f0 - 800002b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002b8: 00200293 li t0,2 - 800002bc: fc521ce3 bne tp,t0,80000294 - -00000000800002c0 : - 800002c0: 00e00193 li gp,14 - 800002c4: 00000213 li tp,0 - 800002c8: fcc00093 li ra,-52 - 800002cc: 00002117 auipc sp,0x2 - 800002d0: d3410113 addi sp,sp,-716 # 80002000 - 800002d4: 00000013 nop - 800002d8: 00000013 nop - 800002dc: 00110123 sb ra,2(sp) - 800002e0: 00210f03 lb t5,2(sp) - 800002e4: fcc00e93 li t4,-52 - 800002e8: 21df1463 bne t5,t4,800004f0 - 800002ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002f0: 00200293 li t0,2 - 800002f4: fc521ae3 bne tp,t0,800002c8 - -00000000800002f8 : - 800002f8: 00f00193 li gp,15 - 800002fc: 00000213 li tp,0 - 80000300: fbc00093 li ra,-68 - 80000304: 00000013 nop - 80000308: 00002117 auipc sp,0x2 - 8000030c: cf810113 addi sp,sp,-776 # 80002000 - 80000310: 001101a3 sb ra,3(sp) - 80000314: 00310f03 lb t5,3(sp) - 80000318: fbc00e93 li t4,-68 - 8000031c: 1ddf1a63 bne t5,t4,800004f0 - 80000320: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000324: 00200293 li t0,2 - 80000328: fc521ce3 bne tp,t0,80000300 - -000000008000032c : - 8000032c: 01000193 li gp,16 - 80000330: 00000213 li tp,0 - 80000334: fbb00093 li ra,-69 - 80000338: 00000013 nop - 8000033c: 00002117 auipc sp,0x2 - 80000340: cc410113 addi sp,sp,-828 # 80002000 - 80000344: 00000013 nop - 80000348: 00110223 sb ra,4(sp) - 8000034c: 00410f03 lb t5,4(sp) - 80000350: fbb00e93 li t4,-69 - 80000354: 19df1e63 bne t5,t4,800004f0 - 80000358: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000035c: 00200293 li t0,2 - 80000360: fc521ae3 bne tp,t0,80000334 - -0000000080000364 : - 80000364: 01100193 li gp,17 - 80000368: 00000213 li tp,0 - 8000036c: fab00093 li ra,-85 - 80000370: 00000013 nop - 80000374: 00000013 nop - 80000378: 00002117 auipc sp,0x2 - 8000037c: c8810113 addi sp,sp,-888 # 80002000 - 80000380: 001102a3 sb ra,5(sp) - 80000384: 00510f03 lb t5,5(sp) - 80000388: fab00e93 li t4,-85 - 8000038c: 17df1263 bne t5,t4,800004f0 - 80000390: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000394: 00200293 li t0,2 - 80000398: fc521ae3 bne tp,t0,8000036c - -000000008000039c : - 8000039c: 01200193 li gp,18 - 800003a0: 00000213 li tp,0 - 800003a4: 00002117 auipc sp,0x2 - 800003a8: c5c10113 addi sp,sp,-932 # 80002000 - 800003ac: 03300093 li ra,51 - 800003b0: 00110023 sb ra,0(sp) - 800003b4: 00010f03 lb t5,0(sp) - 800003b8: 03300e93 li t4,51 - 800003bc: 13df1a63 bne t5,t4,800004f0 - 800003c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003c4: 00200293 li t0,2 - 800003c8: fc521ee3 bne tp,t0,800003a4 - -00000000800003cc : - 800003cc: 01300193 li gp,19 - 800003d0: 00000213 li tp,0 - 800003d4: 00002117 auipc sp,0x2 - 800003d8: c2c10113 addi sp,sp,-980 # 80002000 - 800003dc: 02300093 li ra,35 - 800003e0: 00000013 nop - 800003e4: 001100a3 sb ra,1(sp) - 800003e8: 00110f03 lb t5,1(sp) - 800003ec: 02300e93 li t4,35 - 800003f0: 11df1063 bne t5,t4,800004f0 - 800003f4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003f8: 00200293 li t0,2 - 800003fc: fc521ce3 bne tp,t0,800003d4 - -0000000080000400 : - 80000400: 01400193 li gp,20 - 80000404: 00000213 li tp,0 - 80000408: 00002117 auipc sp,0x2 - 8000040c: bf810113 addi sp,sp,-1032 # 80002000 - 80000410: 02200093 li ra,34 - 80000414: 00000013 nop - 80000418: 00000013 nop - 8000041c: 00110123 sb ra,2(sp) - 80000420: 00210f03 lb t5,2(sp) - 80000424: 02200e93 li t4,34 - 80000428: 0ddf1463 bne t5,t4,800004f0 - 8000042c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000430: 00200293 li t0,2 - 80000434: fc521ae3 bne tp,t0,80000408 - -0000000080000438 : - 80000438: 01500193 li gp,21 - 8000043c: 00000213 li tp,0 - 80000440: 00002117 auipc sp,0x2 - 80000444: bc010113 addi sp,sp,-1088 # 80002000 - 80000448: 00000013 nop - 8000044c: 01200093 li ra,18 - 80000450: 001101a3 sb ra,3(sp) - 80000454: 00310f03 lb t5,3(sp) - 80000458: 01200e93 li t4,18 - 8000045c: 09df1a63 bne t5,t4,800004f0 - 80000460: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000464: 00200293 li t0,2 - 80000468: fc521ce3 bne tp,t0,80000440 - -000000008000046c : - 8000046c: 01600193 li gp,22 - 80000470: 00000213 li tp,0 - 80000474: 00002117 auipc sp,0x2 - 80000478: b8c10113 addi sp,sp,-1140 # 80002000 - 8000047c: 00000013 nop - 80000480: 01100093 li ra,17 - 80000484: 00000013 nop - 80000488: 00110223 sb ra,4(sp) - 8000048c: 00410f03 lb t5,4(sp) - 80000490: 01100e93 li t4,17 - 80000494: 05df1e63 bne t5,t4,800004f0 - 80000498: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000049c: 00200293 li t0,2 - 800004a0: fc521ae3 bne tp,t0,80000474 - -00000000800004a4 : - 800004a4: 01700193 li gp,23 - 800004a8: 00000213 li tp,0 - 800004ac: 00002117 auipc sp,0x2 - 800004b0: b5410113 addi sp,sp,-1196 # 80002000 - 800004b4: 00000013 nop - 800004b8: 00000013 nop - 800004bc: 00100093 li ra,1 - 800004c0: 001102a3 sb ra,5(sp) - 800004c4: 00510f03 lb t5,5(sp) - 800004c8: 00100e93 li t4,1 - 800004cc: 03df1263 bne t5,t4,800004f0 - 800004d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004d4: 00200293 li t0,2 - 800004d8: fc521ae3 bne tp,t0,800004ac - 800004dc: 0ef00513 li a0,239 - 800004e0: 00002597 auipc a1,0x2 - 800004e4: b2058593 addi a1,a1,-1248 # 80002000 - 800004e8: 00a581a3 sb a0,3(a1) - 800004ec: 00301c63 bne zero,gp,80000504 - -00000000800004f0 : - 800004f0: 0ff0000f fence - 800004f4: 00018063 beqz gp,800004f4 - 800004f8: 00119193 slli gp,gp,0x1 - 800004fc: 0011e193 ori gp,gp,1 - 80000500: 00000073 ecall - -0000000080000504 : - 80000504: 0ff0000f fence - 80000508: 00100193 li gp,1 - 8000050c: 00000073 ecall - 80000510: c0001073 unimp - 80000514: 0000 unimp - 80000516: 0000 unimp - 80000518: 0000 unimp - 8000051a: 0000 unimp - 8000051c: 0000 unimp - 8000051e: 0000 unimp - 80000520: 0000 unimp - 80000522: 0000 unimp - 80000524: 0000 unimp - 80000526: 0000 unimp - 80000528: 0000 unimp - 8000052a: 0000 unimp - 8000052c: 0000 unimp - 8000052e: 0000 unimp - 80000530: 0000 unimp - 80000532: 0000 unimp - 80000534: 0000 unimp - 80000536: 0000 unimp - 80000538: 0000 unimp - 8000053a: 0000 unimp - 8000053c: 0000 unimp - 8000053e: 0000 unimp - 80000540: 0000 unimp - 80000542: 0000 unimp - -Disassembly of section .data: - -0000000080002000 : - 80002000: jal t6,800006fe - -0000000080002001 : - 80002001: jal t6,800006ff - -0000000080002002 : - 80002002: jal t6,80000700 - -0000000080002003 : - 80002003: jal t6,80000701 - -0000000080002004 : - 80002004: jal t6,80000702 - -0000000080002005 : - 80002005: jal t6,80000703 - -0000000080002006 : - 80002006: jal t6,80000704 - -0000000080002007 : - 80002007: jal t6,80100015 <_end+0xfe005> - -0000000080002008 : - 80002008: jal t6,80010008 <_end+0xdff8> - -0000000080002009 : - 80002009: 000000ef jal ra,80002009 - 8000200d: 0000 unimp - 8000200f: 00 Address 0x000000008000200f is out of bounds. - diff --git a/test/riscv/tests/rv64ui-p-sb.elf b/test/riscv/tests/rv64ui-p-sb.elf deleted file mode 100644 index 0f672c3d..00000000 Binary files a/test/riscv/tests/rv64ui-p-sb.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-sd.dump b/test/riscv/tests/rv64ui-p-sd.dump deleted file mode 100644 index 56249fa2..00000000 --- a/test/riscv/tests/rv64ui-p-sd.dump +++ /dev/null @@ -1,594 +0,0 @@ - -rv64ui-p-sd: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00002097 auipc ra,0x2 - 80000100: f0408093 addi ra,ra,-252 # 80002000 - 80000104: 00550137 lui sp,0x550 - 80000108: 0551011b addiw sp,sp,85 - 8000010c: 01011113 slli sp,sp,0x10 - 80000110: 05510113 addi sp,sp,85 # 550055 <_start-0x7faaffab> - 80000114: 01111113 slli sp,sp,0x11 - 80000118: 0aa10113 addi sp,sp,170 - 8000011c: 0020b023 sd sp,0(ra) - 80000120: 0000bf03 ld t5,0(ra) - 80000124: 00550eb7 lui t4,0x550 - 80000128: 055e8e9b addiw t4,t4,85 - 8000012c: 010e9e93 slli t4,t4,0x10 - 80000130: 055e8e93 addi t4,t4,85 # 550055 <_start-0x7faaffab> - 80000134: 011e9e93 slli t4,t4,0x11 - 80000138: 0aae8e93 addi t4,t4,170 - 8000013c: 00200193 li gp,2 - 80000140: 61df1063 bne t5,t4,80000740 - -0000000080000144 : - 80000144: 00002097 auipc ra,0x2 - 80000148: ebc08093 addi ra,ra,-324 # 80002000 - 8000014c: ffd50137 lui sp,0xffd50 - 80000150: 0551011b addiw sp,sp,85 - 80000154: 01011113 slli sp,sp,0x10 - 80000158: 05510113 addi sp,sp,85 # ffffffffffd50055 <_end+0xffffffff7fd4e005> - 8000015c: 00d11113 slli sp,sp,0xd - 80000160: 00b10113 addi sp,sp,11 - 80000164: 00c11113 slli sp,sp,0xc - 80000168: a0010113 addi sp,sp,-1536 - 8000016c: 0020b423 sd sp,8(ra) - 80000170: 0080bf03 ld t5,8(ra) - 80000174: ffd50eb7 lui t4,0xffd50 - 80000178: 055e8e9b addiw t4,t4,85 - 8000017c: 010e9e93 slli t4,t4,0x10 - 80000180: 055e8e93 addi t4,t4,85 # ffffffffffd50055 <_end+0xffffffff7fd4e005> - 80000184: 00de9e93 slli t4,t4,0xd - 80000188: 00be8e93 addi t4,t4,11 - 8000018c: 00ce9e93 slli t4,t4,0xc - 80000190: a00e8e93 addi t4,t4,-1536 - 80000194: 00300193 li gp,3 - 80000198: 5bdf1463 bne t5,t4,80000740 - -000000008000019c : - 8000019c: 00002097 auipc ra,0x2 - 800001a0: e6408093 addi ra,ra,-412 # 80002000 - 800001a4: 00550137 lui sp,0x550 - 800001a8: 0551011b addiw sp,sp,85 - 800001ac: 00d11113 slli sp,sp,0xd - 800001b0: 00b10113 addi sp,sp,11 # 55000b <_start-0x7faafff5> - 800001b4: 00c11113 slli sp,sp,0xc - 800001b8: a0110113 addi sp,sp,-1535 - 800001bc: 00c11113 slli sp,sp,0xc - 800001c0: aa010113 addi sp,sp,-1376 - 800001c4: 0020b823 sd sp,16(ra) - 800001c8: 0100bf03 ld t5,16(ra) - 800001cc: 00550eb7 lui t4,0x550 - 800001d0: 055e8e9b addiw t4,t4,85 - 800001d4: 00de9e93 slli t4,t4,0xd - 800001d8: 00be8e93 addi t4,t4,11 # 55000b <_start-0x7faafff5> - 800001dc: 00ce9e93 slli t4,t4,0xc - 800001e0: a01e8e93 addi t4,t4,-1535 - 800001e4: 00ce9e93 slli t4,t4,0xc - 800001e8: aa0e8e93 addi t4,t4,-1376 - 800001ec: 00400193 li gp,4 - 800001f0: 55df1863 bne t5,t4,80000740 - -00000000800001f4 : - 800001f4: 00002097 auipc ra,0x2 - 800001f8: e0c08093 addi ra,ra,-500 # 80002000 - 800001fc: fffd0137 lui sp,0xfffd0 - 80000200: 0551011b addiw sp,sp,85 - 80000204: 01011113 slli sp,sp,0x10 - 80000208: 05510113 addi sp,sp,85 # fffffffffffd0055 <_end+0xffffffff7ffce005> - 8000020c: 01011113 slli sp,sp,0x10 - 80000210: 05510113 addi sp,sp,85 - 80000214: 00d11113 slli sp,sp,0xd - 80000218: 00a10113 addi sp,sp,10 - 8000021c: 0020bc23 sd sp,24(ra) - 80000220: 0180bf03 ld t5,24(ra) - 80000224: fffd0eb7 lui t4,0xfffd0 - 80000228: 055e8e9b addiw t4,t4,85 - 8000022c: 010e9e93 slli t4,t4,0x10 - 80000230: 055e8e93 addi t4,t4,85 # fffffffffffd0055 <_end+0xffffffff7ffce005> - 80000234: 010e9e93 slli t4,t4,0x10 - 80000238: 055e8e93 addi t4,t4,85 - 8000023c: 00de9e93 slli t4,t4,0xd - 80000240: 00ae8e93 addi t4,t4,10 - 80000244: 00500193 li gp,5 - 80000248: 4fdf1c63 bne t5,t4,80000740 - -000000008000024c : - 8000024c: 00002097 auipc ra,0x2 - 80000250: dec08093 addi ra,ra,-532 # 80002038 - 80000254: 00550137 lui sp,0x550 - 80000258: 0551011b addiw sp,sp,85 - 8000025c: 01011113 slli sp,sp,0x10 - 80000260: 05510113 addi sp,sp,85 # 550055 <_start-0x7faaffab> - 80000264: 01111113 slli sp,sp,0x11 - 80000268: 0aa10113 addi sp,sp,170 - 8000026c: fe20b423 sd sp,-24(ra) - 80000270: fe80bf03 ld t5,-24(ra) - 80000274: 00550eb7 lui t4,0x550 - 80000278: 055e8e9b addiw t4,t4,85 - 8000027c: 010e9e93 slli t4,t4,0x10 - 80000280: 055e8e93 addi t4,t4,85 # 550055 <_start-0x7faaffab> - 80000284: 011e9e93 slli t4,t4,0x11 - 80000288: 0aae8e93 addi t4,t4,170 - 8000028c: 00600193 li gp,6 - 80000290: 4bdf1863 bne t5,t4,80000740 - -0000000080000294 : - 80000294: 00002097 auipc ra,0x2 - 80000298: da408093 addi ra,ra,-604 # 80002038 - 8000029c: ffd50137 lui sp,0xffd50 - 800002a0: 0551011b addiw sp,sp,85 - 800002a4: 01011113 slli sp,sp,0x10 - 800002a8: 05510113 addi sp,sp,85 # ffffffffffd50055 <_end+0xffffffff7fd4e005> - 800002ac: 00d11113 slli sp,sp,0xd - 800002b0: 00b10113 addi sp,sp,11 - 800002b4: 00c11113 slli sp,sp,0xc - 800002b8: a0010113 addi sp,sp,-1536 - 800002bc: fe20b823 sd sp,-16(ra) - 800002c0: ff00bf03 ld t5,-16(ra) - 800002c4: ffd50eb7 lui t4,0xffd50 - 800002c8: 055e8e9b addiw t4,t4,85 - 800002cc: 010e9e93 slli t4,t4,0x10 - 800002d0: 055e8e93 addi t4,t4,85 # ffffffffffd50055 <_end+0xffffffff7fd4e005> - 800002d4: 00de9e93 slli t4,t4,0xd - 800002d8: 00be8e93 addi t4,t4,11 - 800002dc: 00ce9e93 slli t4,t4,0xc - 800002e0: a00e8e93 addi t4,t4,-1536 - 800002e4: 00700193 li gp,7 - 800002e8: 45df1c63 bne t5,t4,80000740 - -00000000800002ec : - 800002ec: 00002097 auipc ra,0x2 - 800002f0: d4c08093 addi ra,ra,-692 # 80002038 - 800002f4: 00550137 lui sp,0x550 - 800002f8: 0551011b addiw sp,sp,85 - 800002fc: 00d11113 slli sp,sp,0xd - 80000300: 00b10113 addi sp,sp,11 # 55000b <_start-0x7faafff5> - 80000304: 00c11113 slli sp,sp,0xc - 80000308: a0110113 addi sp,sp,-1535 - 8000030c: 00c11113 slli sp,sp,0xc - 80000310: aa010113 addi sp,sp,-1376 - 80000314: fe20bc23 sd sp,-8(ra) - 80000318: ff80bf03 ld t5,-8(ra) - 8000031c: 00550eb7 lui t4,0x550 - 80000320: 055e8e9b addiw t4,t4,85 - 80000324: 00de9e93 slli t4,t4,0xd - 80000328: 00be8e93 addi t4,t4,11 # 55000b <_start-0x7faafff5> - 8000032c: 00ce9e93 slli t4,t4,0xc - 80000330: a01e8e93 addi t4,t4,-1535 - 80000334: 00ce9e93 slli t4,t4,0xc - 80000338: aa0e8e93 addi t4,t4,-1376 - 8000033c: 00800193 li gp,8 - 80000340: 41df1063 bne t5,t4,80000740 - -0000000080000344 : - 80000344: 00002097 auipc ra,0x2 - 80000348: cf408093 addi ra,ra,-780 # 80002038 - 8000034c: fffd0137 lui sp,0xfffd0 - 80000350: 0551011b addiw sp,sp,85 - 80000354: 01011113 slli sp,sp,0x10 - 80000358: 05510113 addi sp,sp,85 # fffffffffffd0055 <_end+0xffffffff7ffce005> - 8000035c: 01011113 slli sp,sp,0x10 - 80000360: 05510113 addi sp,sp,85 - 80000364: 00d11113 slli sp,sp,0xd - 80000368: 00a10113 addi sp,sp,10 - 8000036c: 0020b023 sd sp,0(ra) - 80000370: 0000bf03 ld t5,0(ra) - 80000374: fffd0eb7 lui t4,0xfffd0 - 80000378: 055e8e9b addiw t4,t4,85 - 8000037c: 010e9e93 slli t4,t4,0x10 - 80000380: 055e8e93 addi t4,t4,85 # fffffffffffd0055 <_end+0xffffffff7ffce005> - 80000384: 010e9e93 slli t4,t4,0x10 - 80000388: 055e8e93 addi t4,t4,85 - 8000038c: 00de9e93 slli t4,t4,0xd - 80000390: 00ae8e93 addi t4,t4,10 - 80000394: 00900193 li gp,9 - 80000398: 3bdf1463 bne t5,t4,80000740 - -000000008000039c : - 8000039c: 00002097 auipc ra,0x2 - 800003a0: ca408093 addi ra,ra,-860 # 80002040 - 800003a4: 00247137 lui sp,0x247 - 800003a8: 8ad1011b addiw sp,sp,-1875 - 800003ac: 00e11113 slli sp,sp,0xe - 800003b0: c0910113 addi sp,sp,-1015 # 246c09 <_start-0x7fdb93f7> - 800003b4: 00d11113 slli sp,sp,0xd - 800003b8: 34510113 addi sp,sp,837 - 800003bc: 00c11113 slli sp,sp,0xc - 800003c0: 67810113 addi sp,sp,1656 - 800003c4: fe008213 addi tp,ra,-32 - 800003c8: 02223023 sd sp,32(tp) # 20 <_start-0x7fffffe0> - 800003cc: 0000b283 ld t0,0(ra) - 800003d0: 00247eb7 lui t4,0x247 - 800003d4: 8ade8e9b addiw t4,t4,-1875 - 800003d8: 00ee9e93 slli t4,t4,0xe - 800003dc: c09e8e93 addi t4,t4,-1015 # 246c09 <_start-0x7fdb93f7> - 800003e0: 00de9e93 slli t4,t4,0xd - 800003e4: 345e8e93 addi t4,t4,837 - 800003e8: 00ce9e93 slli t4,t4,0xc - 800003ec: 678e8e93 addi t4,t4,1656 - 800003f0: 00a00193 li gp,10 - 800003f4: 35d29663 bne t0,t4,80000740 - -00000000800003f8 : - 800003f8: 00002097 auipc ra,0x2 - 800003fc: c4808093 addi ra,ra,-952 # 80002040 - 80000400: 00b04137 lui sp,0xb04 - 80000404: 2611011b addiw sp,sp,609 - 80000408: 00c11113 slli sp,sp,0xc - 8000040c: 30b10113 addi sp,sp,779 # b0430b <_start-0x7f4fbcf5> - 80000410: 00f11113 slli sp,sp,0xf - 80000414: 21310113 addi sp,sp,531 - 80000418: 00c11113 slli sp,sp,0xc - 8000041c: 09810113 addi sp,sp,152 - 80000420: ffd08093 addi ra,ra,-3 - 80000424: 0020b5a3 sd sp,11(ra) - 80000428: 00002217 auipc tp,0x2 - 8000042c: c2020213 addi tp,tp,-992 # 80002048 - 80000430: 00023283 ld t0,0(tp) # 0 <_start-0x80000000> - 80000434: 00b04eb7 lui t4,0xb04 - 80000438: 261e8e9b addiw t4,t4,609 - 8000043c: 00ce9e93 slli t4,t4,0xc - 80000440: 30be8e93 addi t4,t4,779 # b0430b <_start-0x7f4fbcf5> - 80000444: 00fe9e93 slli t4,t4,0xf - 80000448: 213e8e93 addi t4,t4,531 - 8000044c: 00ce9e93 slli t4,t4,0xc - 80000450: 098e8e93 addi t4,t4,152 - 80000454: 00b00193 li gp,11 - 80000458: 2fd29463 bne t0,t4,80000740 - -000000008000045c : - 8000045c: 00c00193 li gp,12 - 80000460: 00000213 li tp,0 - 80000464: 0abbd0b7 lui ra,0xabbd - 80000468: cdd0809b addiw ra,ra,-803 - 8000046c: 00002117 auipc sp,0x2 - 80000470: b9410113 addi sp,sp,-1132 # 80002000 - 80000474: 00113023 sd ra,0(sp) - 80000478: 00013f03 ld t5,0(sp) - 8000047c: 0abbdeb7 lui t4,0xabbd - 80000480: cdde8e9b addiw t4,t4,-803 - 80000484: 2bdf1e63 bne t5,t4,80000740 - 80000488: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000048c: 00200293 li t0,2 - 80000490: fc521ae3 bne tp,t0,80000464 - -0000000080000494 : - 80000494: 00d00193 li gp,13 - 80000498: 00000213 li tp,0 - 8000049c: 0aabc0b7 lui ra,0xaabc - 800004a0: ccd0809b addiw ra,ra,-819 - 800004a4: 00002117 auipc sp,0x2 - 800004a8: b5c10113 addi sp,sp,-1188 # 80002000 - 800004ac: 00000013 nop - 800004b0: 00113423 sd ra,8(sp) - 800004b4: 00813f03 ld t5,8(sp) - 800004b8: 0aabceb7 lui t4,0xaabc - 800004bc: ccde8e9b addiw t4,t4,-819 - 800004c0: 29df1063 bne t5,t4,80000740 - 800004c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004c8: 00200293 li t0,2 - 800004cc: fc5218e3 bne tp,t0,8000049c - -00000000800004d0 : - 800004d0: 00e00193 li gp,14 - 800004d4: 00000213 li tp,0 - 800004d8: 0daac0b7 lui ra,0xdaac - 800004dc: bcc0809b addiw ra,ra,-1076 - 800004e0: 00002117 auipc sp,0x2 - 800004e4: b2010113 addi sp,sp,-1248 # 80002000 - 800004e8: 00000013 nop - 800004ec: 00000013 nop - 800004f0: 00113823 sd ra,16(sp) - 800004f4: 01013f03 ld t5,16(sp) - 800004f8: 0daaceb7 lui t4,0xdaac - 800004fc: bcce8e9b addiw t4,t4,-1076 - 80000500: 25df1063 bne t5,t4,80000740 - 80000504: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000508: 00200293 li t0,2 - 8000050c: fc5216e3 bne tp,t0,800004d8 - -0000000080000510 : - 80000510: 00f00193 li gp,15 - 80000514: 00000213 li tp,0 - 80000518: 0ddab0b7 lui ra,0xddab - 8000051c: bbc0809b addiw ra,ra,-1092 - 80000520: 00000013 nop - 80000524: 00002117 auipc sp,0x2 - 80000528: adc10113 addi sp,sp,-1316 # 80002000 - 8000052c: 00113c23 sd ra,24(sp) - 80000530: 01813f03 ld t5,24(sp) - 80000534: 0ddabeb7 lui t4,0xddab - 80000538: bbce8e9b addiw t4,t4,-1092 - 8000053c: 21df1263 bne t5,t4,80000740 - 80000540: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000544: 00200293 li t0,2 - 80000548: fc5218e3 bne tp,t0,80000518 - -000000008000054c : - 8000054c: 01000193 li gp,16 - 80000550: 00000213 li tp,0 - 80000554: 0cddb0b7 lui ra,0xcddb - 80000558: abb0809b addiw ra,ra,-1349 - 8000055c: 00000013 nop - 80000560: 00002117 auipc sp,0x2 - 80000564: aa010113 addi sp,sp,-1376 # 80002000 - 80000568: 00000013 nop - 8000056c: 02113023 sd ra,32(sp) - 80000570: 02013f03 ld t5,32(sp) - 80000574: 0cddbeb7 lui t4,0xcddb - 80000578: abbe8e9b addiw t4,t4,-1349 - 8000057c: 1ddf1263 bne t5,t4,80000740 - 80000580: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000584: 00200293 li t0,2 - 80000588: fc5216e3 bne tp,t0,80000554 - -000000008000058c : - 8000058c: 01100193 li gp,17 - 80000590: 00000213 li tp,0 - 80000594: 0ccde0b7 lui ra,0xccde - 80000598: aab0809b addiw ra,ra,-1365 - 8000059c: 00000013 nop - 800005a0: 00000013 nop - 800005a4: 00002117 auipc sp,0x2 - 800005a8: a5c10113 addi sp,sp,-1444 # 80002000 - 800005ac: 02113423 sd ra,40(sp) - 800005b0: 02813f03 ld t5,40(sp) - 800005b4: 0ccdeeb7 lui t4,0xccde - 800005b8: aabe8e9b addiw t4,t4,-1365 - 800005bc: 19df1263 bne t5,t4,80000740 - 800005c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800005c4: 00200293 li t0,2 - 800005c8: fc5216e3 bne tp,t0,80000594 - -00000000800005cc : - 800005cc: 01200193 li gp,18 - 800005d0: 00000213 li tp,0 - 800005d4: 00002117 auipc sp,0x2 - 800005d8: a2c10113 addi sp,sp,-1492 # 80002000 - 800005dc: 001120b7 lui ra,0x112 - 800005e0: 2330809b addiw ra,ra,563 - 800005e4: 00113023 sd ra,0(sp) - 800005e8: 00013f03 ld t5,0(sp) - 800005ec: 00112eb7 lui t4,0x112 - 800005f0: 233e8e9b addiw t4,t4,563 - 800005f4: 15df1663 bne t5,t4,80000740 - 800005f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800005fc: 00200293 li t0,2 - 80000600: fc521ae3 bne tp,t0,800005d4 - -0000000080000604 : - 80000604: 01300193 li gp,19 - 80000608: 00000213 li tp,0 - 8000060c: 00002117 auipc sp,0x2 - 80000610: 9f410113 addi sp,sp,-1548 # 80002000 - 80000614: 300110b7 lui ra,0x30011 - 80000618: 2230809b addiw ra,ra,547 - 8000061c: 00000013 nop - 80000620: 00113423 sd ra,8(sp) - 80000624: 00813f03 ld t5,8(sp) - 80000628: 30011eb7 lui t4,0x30011 - 8000062c: 223e8e9b addiw t4,t4,547 - 80000630: 11df1863 bne t5,t4,80000740 - 80000634: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000638: 00200293 li t0,2 - 8000063c: fc5218e3 bne tp,t0,8000060c - -0000000080000640 : - 80000640: 01400193 li gp,20 - 80000644: 00000213 li tp,0 - 80000648: 00002117 auipc sp,0x2 - 8000064c: 9b810113 addi sp,sp,-1608 # 80002000 - 80000650: 330010b7 lui ra,0x33001 - 80000654: 1220809b addiw ra,ra,290 - 80000658: 00000013 nop - 8000065c: 00000013 nop - 80000660: 00113823 sd ra,16(sp) - 80000664: 01013f03 ld t5,16(sp) - 80000668: 33001eb7 lui t4,0x33001 - 8000066c: 122e8e9b addiw t4,t4,290 - 80000670: 0ddf1863 bne t5,t4,80000740 - 80000674: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000678: 00200293 li t0,2 - 8000067c: fc5216e3 bne tp,t0,80000648 - -0000000080000680 : - 80000680: 01500193 li gp,21 - 80000684: 00000213 li tp,0 - 80000688: 00002117 auipc sp,0x2 - 8000068c: 97810113 addi sp,sp,-1672 # 80002000 - 80000690: 00000013 nop - 80000694: 233000b7 lui ra,0x23300 - 80000698: 1120809b addiw ra,ra,274 - 8000069c: 00113c23 sd ra,24(sp) - 800006a0: 01813f03 ld t5,24(sp) - 800006a4: 23300eb7 lui t4,0x23300 - 800006a8: 112e8e9b addiw t4,t4,274 - 800006ac: 09df1a63 bne t5,t4,80000740 - 800006b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800006b4: 00200293 li t0,2 - 800006b8: fc5218e3 bne tp,t0,80000688 - -00000000800006bc : - 800006bc: 01600193 li gp,22 - 800006c0: 00000213 li tp,0 - 800006c4: 00002117 auipc sp,0x2 - 800006c8: 93c10113 addi sp,sp,-1732 # 80002000 - 800006cc: 00000013 nop - 800006d0: 223300b7 lui ra,0x22330 - 800006d4: 0110809b addiw ra,ra,17 - 800006d8: 00000013 nop - 800006dc: 02113023 sd ra,32(sp) - 800006e0: 02013f03 ld t5,32(sp) - 800006e4: 22330eb7 lui t4,0x22330 - 800006e8: 011e8e9b addiw t4,t4,17 - 800006ec: 05df1a63 bne t5,t4,80000740 - 800006f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800006f4: 00200293 li t0,2 - 800006f8: fc5216e3 bne tp,t0,800006c4 - -00000000800006fc : - 800006fc: 01700193 li gp,23 - 80000700: 00000213 li tp,0 - 80000704: 00002117 auipc sp,0x2 - 80000708: 8fc10113 addi sp,sp,-1796 # 80002000 - 8000070c: 00000013 nop - 80000710: 00000013 nop - 80000714: 122330b7 lui ra,0x12233 - 80000718: 0010809b addiw ra,ra,1 - 8000071c: 02113423 sd ra,40(sp) - 80000720: 02813f03 ld t5,40(sp) - 80000724: 12233eb7 lui t4,0x12233 - 80000728: 001e8e9b addiw t4,t4,1 - 8000072c: 01df1a63 bne t5,t4,80000740 - 80000730: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000734: 00200293 li t0,2 - 80000738: fc5216e3 bne tp,t0,80000704 - 8000073c: 00301c63 bne zero,gp,80000754 - -0000000080000740 : - 80000740: 0ff0000f fence - 80000744: 00018063 beqz gp,80000744 - 80000748: 00119193 slli gp,gp,0x1 - 8000074c: 0011e193 ori gp,gp,1 - 80000750: 00000073 ecall - -0000000080000754 : - 80000754: 0ff0000f fence - 80000758: 00100193 li gp,1 - 8000075c: 00000073 ecall - 80000760: c0001073 unimp - 80000764: 0000 unimp - 80000766: 0000 unimp - 80000768: 0000 unimp - 8000076a: 0000 unimp - 8000076c: 0000 unimp - 8000076e: 0000 unimp - 80000770: 0000 unimp - 80000772: 0000 unimp - 80000774: 0000 unimp - 80000776: 0000 unimp - 80000778: 0000 unimp - 8000077a: 0000 unimp - 8000077c: 0000 unimp - 8000077e: 0000 unimp - 80000780: 0000 unimp - 80000782: 0000 unimp - -Disassembly of section .data: - -0000000080002000 : - 80002000: deadbeef jal t4,7ffdd5ea <_start-0x22a16> - 80002004: deadbeef jal t4,7ffdd5ee <_start-0x22a12> - -0000000080002008 : - 80002008: deadbeef jal t4,7ffdd5f2 <_start-0x22a0e> - 8000200c: deadbeef jal t4,7ffdd5f6 <_start-0x22a0a> - -0000000080002010 : - 80002010: deadbeef jal t4,7ffdd5fa <_start-0x22a06> - 80002014: deadbeef jal t4,7ffdd5fe <_start-0x22a02> - -0000000080002018 : - 80002018: deadbeef jal t4,7ffdd602 <_start-0x229fe> - 8000201c: deadbeef jal t4,7ffdd606 <_start-0x229fa> - -0000000080002020 : - 80002020: deadbeef jal t4,7ffdd60a <_start-0x229f6> - 80002024: deadbeef jal t4,7ffdd60e <_start-0x229f2> - -0000000080002028 : - 80002028: deadbeef jal t4,7ffdd612 <_start-0x229ee> - 8000202c: deadbeef jal t4,7ffdd616 <_start-0x229ea> - -0000000080002030 : - 80002030: deadbeef jal t4,7ffdd61a <_start-0x229e6> - 80002034: deadbeef jal t4,7ffdd61e <_start-0x229e2> - -0000000080002038 : - 80002038: deadbeef jal t4,7ffdd622 <_start-0x229de> - 8000203c: deadbeef jal t4,7ffdd626 <_start-0x229da> - -0000000080002040 : - 80002040: deadbeef jal t4,7ffdd62a <_start-0x229d6> - 80002044: deadbeef jal t4,7ffdd62e <_start-0x229d2> - -0000000080002048 : - 80002048: deadbeef jal t4,7ffdd632 <_start-0x229ce> - 8000204c: deadbeef jal t4,7ffdd636 <_start-0x229ca> diff --git a/test/riscv/tests/rv64ui-p-sd.elf b/test/riscv/tests/rv64ui-p-sd.elf deleted file mode 100644 index 8ebb0db0..00000000 Binary files a/test/riscv/tests/rv64ui-p-sd.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-sh.dump b/test/riscv/tests/rv64ui-p-sh.dump deleted file mode 100644 index dc11b449..00000000 --- a/test/riscv/tests/rv64ui-p-sh.dump +++ /dev/null @@ -1,480 +0,0 @@ - -rv64ui-p-sh: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00002097 auipc ra,0x2 - 80000100: f0408093 addi ra,ra,-252 # 80002000 - 80000104: 0aa00113 li sp,170 - 80000108: 00209023 sh sp,0(ra) - 8000010c: 00009f03 lh t5,0(ra) - 80000110: 0aa00e93 li t4,170 - 80000114: 00200193 li gp,2 - 80000118: 45df1e63 bne t5,t4,80000574 - -000000008000011c : - 8000011c: 00002097 auipc ra,0x2 - 80000120: ee408093 addi ra,ra,-284 # 80002000 - 80000124: ffffb137 lui sp,0xffffb - 80000128: a001011b addiw sp,sp,-1536 - 8000012c: 00209123 sh sp,2(ra) - 80000130: 00209f03 lh t5,2(ra) - 80000134: ffffbeb7 lui t4,0xffffb - 80000138: a00e8e9b addiw t4,t4,-1536 - 8000013c: 00300193 li gp,3 - 80000140: 43df1a63 bne t5,t4,80000574 - -0000000080000144 : - 80000144: 00002097 auipc ra,0x2 - 80000148: ebc08093 addi ra,ra,-324 # 80002000 - 8000014c: beef1137 lui sp,0xbeef1 - 80000150: aa01011b addiw sp,sp,-1376 - 80000154: 00209223 sh sp,4(ra) - 80000158: 0040af03 lw t5,4(ra) - 8000015c: beef1eb7 lui t4,0xbeef1 - 80000160: aa0e8e9b addiw t4,t4,-1376 - 80000164: 00400193 li gp,4 - 80000168: 41df1663 bne t5,t4,80000574 - -000000008000016c : - 8000016c: 00002097 auipc ra,0x2 - 80000170: e9408093 addi ra,ra,-364 # 80002000 - 80000174: ffffa137 lui sp,0xffffa - 80000178: 00a1011b addiw sp,sp,10 - 8000017c: 00209323 sh sp,6(ra) - 80000180: 00609f03 lh t5,6(ra) - 80000184: ffffaeb7 lui t4,0xffffa - 80000188: 00ae8e9b addiw t4,t4,10 - 8000018c: 00500193 li gp,5 - 80000190: 3fdf1263 bne t5,t4,80000574 - -0000000080000194 : - 80000194: 00002097 auipc ra,0x2 - 80000198: e7a08093 addi ra,ra,-390 # 8000200e - 8000019c: 0aa00113 li sp,170 - 800001a0: fe209d23 sh sp,-6(ra) - 800001a4: ffa09f03 lh t5,-6(ra) - 800001a8: 0aa00e93 li t4,170 - 800001ac: 00600193 li gp,6 - 800001b0: 3ddf1263 bne t5,t4,80000574 - -00000000800001b4 : - 800001b4: 00002097 auipc ra,0x2 - 800001b8: e5a08093 addi ra,ra,-422 # 8000200e - 800001bc: ffffb137 lui sp,0xffffb - 800001c0: a001011b addiw sp,sp,-1536 - 800001c4: fe209e23 sh sp,-4(ra) - 800001c8: ffc09f03 lh t5,-4(ra) - 800001cc: ffffbeb7 lui t4,0xffffb - 800001d0: a00e8e9b addiw t4,t4,-1536 - 800001d4: 00700193 li gp,7 - 800001d8: 39df1e63 bne t5,t4,80000574 - -00000000800001dc : - 800001dc: 00002097 auipc ra,0x2 - 800001e0: e3208093 addi ra,ra,-462 # 8000200e - 800001e4: 00001137 lui sp,0x1 - 800001e8: aa01011b addiw sp,sp,-1376 - 800001ec: fe209f23 sh sp,-2(ra) - 800001f0: ffe09f03 lh t5,-2(ra) - 800001f4: 00001eb7 lui t4,0x1 - 800001f8: aa0e8e9b addiw t4,t4,-1376 - 800001fc: 00800193 li gp,8 - 80000200: 37df1a63 bne t5,t4,80000574 - -0000000080000204 : - 80000204: 00002097 auipc ra,0x2 - 80000208: e0a08093 addi ra,ra,-502 # 8000200e - 8000020c: ffffa137 lui sp,0xffffa - 80000210: 00a1011b addiw sp,sp,10 - 80000214: 00209023 sh sp,0(ra) - 80000218: 00009f03 lh t5,0(ra) - 8000021c: ffffaeb7 lui t4,0xffffa - 80000220: 00ae8e9b addiw t4,t4,10 - 80000224: 00900193 li gp,9 - 80000228: 35df1663 bne t5,t4,80000574 - -000000008000022c : - 8000022c: 00002097 auipc ra,0x2 - 80000230: de408093 addi ra,ra,-540 # 80002010 - 80000234: 12345137 lui sp,0x12345 - 80000238: 6781011b addiw sp,sp,1656 - 8000023c: fe008213 addi tp,ra,-32 - 80000240: 02221023 sh sp,32(tp) # 20 <_start-0x7fffffe0> - 80000244: 00009283 lh t0,0(ra) - 80000248: 00005eb7 lui t4,0x5 - 8000024c: 678e8e9b addiw t4,t4,1656 - 80000250: 00a00193 li gp,10 - 80000254: 33d29063 bne t0,t4,80000574 - -0000000080000258 : - 80000258: 00002097 auipc ra,0x2 - 8000025c: db808093 addi ra,ra,-584 # 80002010 - 80000260: 00003137 lui sp,0x3 - 80000264: 0981011b addiw sp,sp,152 - 80000268: ffb08093 addi ra,ra,-5 - 8000026c: 002093a3 sh sp,7(ra) - 80000270: 00002217 auipc tp,0x2 - 80000274: da220213 addi tp,tp,-606 # 80002012 - 80000278: 00021283 lh t0,0(tp) # 0 <_start-0x80000000> - 8000027c: 00003eb7 lui t4,0x3 - 80000280: 098e8e9b addiw t4,t4,152 - 80000284: 00b00193 li gp,11 - 80000288: 2fd29663 bne t0,t4,80000574 - -000000008000028c : - 8000028c: 00c00193 li gp,12 - 80000290: 00000213 li tp,0 - 80000294: ffffd0b7 lui ra,0xffffd - 80000298: cdd0809b addiw ra,ra,-803 - 8000029c: 00002117 auipc sp,0x2 - 800002a0: d6410113 addi sp,sp,-668 # 80002000 - 800002a4: 00111023 sh ra,0(sp) - 800002a8: 00011f03 lh t5,0(sp) - 800002ac: ffffdeb7 lui t4,0xffffd - 800002b0: cdde8e9b addiw t4,t4,-803 - 800002b4: 2ddf1063 bne t5,t4,80000574 - 800002b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002bc: 00200293 li t0,2 - 800002c0: fc521ae3 bne tp,t0,80000294 - -00000000800002c4 : - 800002c4: 00d00193 li gp,13 - 800002c8: 00000213 li tp,0 - 800002cc: ffffc0b7 lui ra,0xffffc - 800002d0: ccd0809b addiw ra,ra,-819 - 800002d4: 00002117 auipc sp,0x2 - 800002d8: d2c10113 addi sp,sp,-724 # 80002000 - 800002dc: 00000013 nop - 800002e0: 00111123 sh ra,2(sp) - 800002e4: 00211f03 lh t5,2(sp) - 800002e8: ffffceb7 lui t4,0xffffc - 800002ec: ccde8e9b addiw t4,t4,-819 - 800002f0: 29df1263 bne t5,t4,80000574 - 800002f4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002f8: 00200293 li t0,2 - 800002fc: fc5218e3 bne tp,t0,800002cc - -0000000080000300 : - 80000300: 00e00193 li gp,14 - 80000304: 00000213 li tp,0 - 80000308: ffffc0b7 lui ra,0xffffc - 8000030c: bcc0809b addiw ra,ra,-1076 - 80000310: 00002117 auipc sp,0x2 - 80000314: cf010113 addi sp,sp,-784 # 80002000 - 80000318: 00000013 nop - 8000031c: 00000013 nop - 80000320: 00111223 sh ra,4(sp) - 80000324: 00411f03 lh t5,4(sp) - 80000328: ffffceb7 lui t4,0xffffc - 8000032c: bcce8e9b addiw t4,t4,-1076 - 80000330: 25df1263 bne t5,t4,80000574 - 80000334: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000338: 00200293 li t0,2 - 8000033c: fc5216e3 bne tp,t0,80000308 - -0000000080000340 : - 80000340: 00f00193 li gp,15 - 80000344: 00000213 li tp,0 - 80000348: ffffb0b7 lui ra,0xffffb - 8000034c: bbc0809b addiw ra,ra,-1092 - 80000350: 00000013 nop - 80000354: 00002117 auipc sp,0x2 - 80000358: cac10113 addi sp,sp,-852 # 80002000 - 8000035c: 00111323 sh ra,6(sp) - 80000360: 00611f03 lh t5,6(sp) - 80000364: ffffbeb7 lui t4,0xffffb - 80000368: bbce8e9b addiw t4,t4,-1092 - 8000036c: 21df1463 bne t5,t4,80000574 - 80000370: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000374: 00200293 li t0,2 - 80000378: fc5218e3 bne tp,t0,80000348 - -000000008000037c : - 8000037c: 01000193 li gp,16 - 80000380: 00000213 li tp,0 - 80000384: ffffb0b7 lui ra,0xffffb - 80000388: abb0809b addiw ra,ra,-1349 - 8000038c: 00000013 nop - 80000390: 00002117 auipc sp,0x2 - 80000394: c7010113 addi sp,sp,-912 # 80002000 - 80000398: 00000013 nop - 8000039c: 00111423 sh ra,8(sp) - 800003a0: 00811f03 lh t5,8(sp) - 800003a4: ffffbeb7 lui t4,0xffffb - 800003a8: abbe8e9b addiw t4,t4,-1349 - 800003ac: 1ddf1463 bne t5,t4,80000574 - 800003b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003b4: 00200293 li t0,2 - 800003b8: fc5216e3 bne tp,t0,80000384 - -00000000800003bc : - 800003bc: 01100193 li gp,17 - 800003c0: 00000213 li tp,0 - 800003c4: ffffe0b7 lui ra,0xffffe - 800003c8: aab0809b addiw ra,ra,-1365 - 800003cc: 00000013 nop - 800003d0: 00000013 nop - 800003d4: 00002117 auipc sp,0x2 - 800003d8: c2c10113 addi sp,sp,-980 # 80002000 - 800003dc: 00111523 sh ra,10(sp) - 800003e0: 00a11f03 lh t5,10(sp) - 800003e4: ffffeeb7 lui t4,0xffffe - 800003e8: aabe8e9b addiw t4,t4,-1365 - 800003ec: 19df1463 bne t5,t4,80000574 - 800003f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003f4: 00200293 li t0,2 - 800003f8: fc5216e3 bne tp,t0,800003c4 - -00000000800003fc : - 800003fc: 01200193 li gp,18 - 80000400: 00000213 li tp,0 - 80000404: 00002117 auipc sp,0x2 - 80000408: bfc10113 addi sp,sp,-1028 # 80002000 - 8000040c: 000020b7 lui ra,0x2 - 80000410: 2330809b addiw ra,ra,563 - 80000414: 00111023 sh ra,0(sp) - 80000418: 00011f03 lh t5,0(sp) - 8000041c: 00002eb7 lui t4,0x2 - 80000420: 233e8e9b addiw t4,t4,563 - 80000424: 15df1863 bne t5,t4,80000574 - 80000428: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000042c: 00200293 li t0,2 - 80000430: fc521ae3 bne tp,t0,80000404 - -0000000080000434 : - 80000434: 01300193 li gp,19 - 80000438: 00000213 li tp,0 - 8000043c: 00002117 auipc sp,0x2 - 80000440: bc410113 addi sp,sp,-1084 # 80002000 - 80000444: 000010b7 lui ra,0x1 - 80000448: 2230809b addiw ra,ra,547 - 8000044c: 00000013 nop - 80000450: 00111123 sh ra,2(sp) - 80000454: 00211f03 lh t5,2(sp) - 80000458: 00001eb7 lui t4,0x1 - 8000045c: 223e8e9b addiw t4,t4,547 - 80000460: 11df1a63 bne t5,t4,80000574 - 80000464: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000468: 00200293 li t0,2 - 8000046c: fc5218e3 bne tp,t0,8000043c - -0000000080000470 : - 80000470: 01400193 li gp,20 - 80000474: 00000213 li tp,0 - 80000478: 00002117 auipc sp,0x2 - 8000047c: b8810113 addi sp,sp,-1144 # 80002000 - 80000480: 000010b7 lui ra,0x1 - 80000484: 1220809b addiw ra,ra,290 - 80000488: 00000013 nop - 8000048c: 00000013 nop - 80000490: 00111223 sh ra,4(sp) - 80000494: 00411f03 lh t5,4(sp) - 80000498: 00001eb7 lui t4,0x1 - 8000049c: 122e8e9b addiw t4,t4,290 - 800004a0: 0ddf1a63 bne t5,t4,80000574 - 800004a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004a8: 00200293 li t0,2 - 800004ac: fc5216e3 bne tp,t0,80000478 - -00000000800004b0 : - 800004b0: 01500193 li gp,21 - 800004b4: 00000213 li tp,0 - 800004b8: 00002117 auipc sp,0x2 - 800004bc: b4810113 addi sp,sp,-1208 # 80002000 - 800004c0: 00000013 nop - 800004c4: 11200093 li ra,274 - 800004c8: 00111323 sh ra,6(sp) - 800004cc: 00611f03 lh t5,6(sp) - 800004d0: 11200e93 li t4,274 - 800004d4: 0bdf1063 bne t5,t4,80000574 - 800004d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004dc: 00200293 li t0,2 - 800004e0: fc521ce3 bne tp,t0,800004b8 - -00000000800004e4 : - 800004e4: 01600193 li gp,22 - 800004e8: 00000213 li tp,0 - 800004ec: 00002117 auipc sp,0x2 - 800004f0: b1410113 addi sp,sp,-1260 # 80002000 - 800004f4: 00000013 nop - 800004f8: 01100093 li ra,17 - 800004fc: 00000013 nop - 80000500: 00111423 sh ra,8(sp) - 80000504: 00811f03 lh t5,8(sp) - 80000508: 01100e93 li t4,17 - 8000050c: 07df1463 bne t5,t4,80000574 - 80000510: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000514: 00200293 li t0,2 - 80000518: fc521ae3 bne tp,t0,800004ec - -000000008000051c : - 8000051c: 01700193 li gp,23 - 80000520: 00000213 li tp,0 - 80000524: 00002117 auipc sp,0x2 - 80000528: adc10113 addi sp,sp,-1316 # 80002000 - 8000052c: 00000013 nop - 80000530: 00000013 nop - 80000534: 000030b7 lui ra,0x3 - 80000538: 0010809b addiw ra,ra,1 - 8000053c: 00111523 sh ra,10(sp) - 80000540: 00a11f03 lh t5,10(sp) - 80000544: 00003eb7 lui t4,0x3 - 80000548: 001e8e9b addiw t4,t4,1 - 8000054c: 03df1463 bne t5,t4,80000574 - 80000550: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000554: 00200293 li t0,2 - 80000558: fc5216e3 bne tp,t0,80000524 - 8000055c: 0000c537 lui a0,0xc - 80000560: eef5051b addiw a0,a0,-273 - 80000564: 00002597 auipc a1,0x2 - 80000568: a9c58593 addi a1,a1,-1380 # 80002000 - 8000056c: 00a59323 sh a0,6(a1) - 80000570: 00301c63 bne zero,gp,80000588 - -0000000080000574 : - 80000574: 0ff0000f fence - 80000578: 00018063 beqz gp,80000578 - 8000057c: 00119193 slli gp,gp,0x1 - 80000580: 0011e193 ori gp,gp,1 - 80000584: 00000073 ecall - -0000000080000588 : - 80000588: 0ff0000f fence - 8000058c: 00100193 li gp,1 - 80000590: 00000073 ecall - 80000594: c0001073 unimp - 80000598: 0000 unimp - 8000059a: 0000 unimp - 8000059c: 0000 unimp - 8000059e: 0000 unimp - 800005a0: 0000 unimp - 800005a2: 0000 unimp - 800005a4: 0000 unimp - 800005a6: 0000 unimp - 800005a8: 0000 unimp - 800005aa: 0000 unimp - 800005ac: 0000 unimp - 800005ae: 0000 unimp - 800005b0: 0000 unimp - 800005b2: 0000 unimp - 800005b4: 0000 unimp - 800005b6: 0000 unimp - 800005b8: 0000 unimp - 800005ba: 0000 unimp - 800005bc: 0000 unimp - 800005be: 0000 unimp - 800005c0: 0000 unimp - 800005c2: 0000 unimp - -Disassembly of section .data: - -0000000080002000 : - 80002000: jal t4,7fffd3ee <_start-0x2c12> - -0000000080002002 : - 80002002: jal t4,7fffd3f0 <_start-0x2c10> - -0000000080002004 : - 80002004: jal t4,7fffd3f2 <_start-0x2c0e> - -0000000080002006 : - 80002006: jal t4,7fffd3f4 <_start-0x2c0c> - -0000000080002008 : - 80002008: jal t4,7fffd3f6 <_start-0x2c0a> - -000000008000200a : - 8000200a: jal t4,7fffd3f8 <_start-0x2c08> - -000000008000200c : - 8000200c: jal t4,7fffd3fa <_start-0x2c06> - -000000008000200e : - 8000200e: jal t4,7fffd3fc <_start-0x2c04> - -0000000080002010 : - 80002010: jal t4,7fffd3fe <_start-0x2c02> - -0000000080002012 : - 80002012: 0000beef jal t4,8000d012 <_end+0xaff2> - 80002016: 0000 unimp - 80002018: 0000 unimp - 8000201a: 0000 unimp - 8000201c: 0000 unimp - 8000201e: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-sh.elf b/test/riscv/tests/rv64ui-p-sh.elf deleted file mode 100644 index 5ba031e4..00000000 Binary files a/test/riscv/tests/rv64ui-p-sh.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-simple.dump b/test/riscv/tests/rv64ui-p-simple.dump deleted file mode 100644 index 7a05fb7e..00000000 --- a/test/riscv/tests/rv64ui-p-simple.dump +++ /dev/null @@ -1,110 +0,0 @@ - -rv64ui-p-simple: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - 800000fc: 0ff0000f fence - 80000100: 00100193 li gp,1 - 80000104: 00000073 ecall - 80000108: c0001073 unimp - 8000010c: 0000 unimp - 8000010e: 0000 unimp - 80000110: 0000 unimp - 80000112: 0000 unimp - 80000114: 0000 unimp - 80000116: 0000 unimp - 80000118: 0000 unimp - 8000011a: 0000 unimp - 8000011c: 0000 unimp - 8000011e: 0000 unimp - 80000120: 0000 unimp - 80000122: 0000 unimp - 80000124: 0000 unimp - 80000126: 0000 unimp - 80000128: 0000 unimp - 8000012a: 0000 unimp - 8000012c: 0000 unimp - 8000012e: 0000 unimp - 80000130: 0000 unimp - 80000132: 0000 unimp - 80000134: 0000 unimp - 80000136: 0000 unimp - 80000138: 0000 unimp - 8000013a: 0000 unimp - 8000013c: 0000 unimp - 8000013e: 0000 unimp - 80000140: 0000 unimp - 80000142: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-simple.elf b/test/riscv/tests/rv64ui-p-simple.elf deleted file mode 100644 index bc8cb92d..00000000 Binary files a/test/riscv/tests/rv64ui-p-simple.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-sll.dump b/test/riscv/tests/rv64ui-p-sll.dump deleted file mode 100644 index c2ac48ff..00000000 --- a/test/riscv/tests/rv64ui-p-sll.dump +++ /dev/null @@ -1,580 +0,0 @@ - -rv64ui-p-sll: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00100093 li ra,1 - 80000100: 00000113 li sp,0 - 80000104: 00209f33 sll t5,ra,sp - 80000108: 00100e93 li t4,1 - 8000010c: 00200193 li gp,2 - 80000110: 5fdf1c63 bne t5,t4,80000708 - -0000000080000114 : - 80000114: 00100093 li ra,1 - 80000118: 00100113 li sp,1 - 8000011c: 00209f33 sll t5,ra,sp - 80000120: 00200e93 li t4,2 - 80000124: 00300193 li gp,3 - 80000128: 5fdf1063 bne t5,t4,80000708 - -000000008000012c : - 8000012c: 00100093 li ra,1 - 80000130: 00700113 li sp,7 - 80000134: 00209f33 sll t5,ra,sp - 80000138: 08000e93 li t4,128 - 8000013c: 00400193 li gp,4 - 80000140: 5ddf1463 bne t5,t4,80000708 - -0000000080000144 : - 80000144: 00100093 li ra,1 - 80000148: 00e00113 li sp,14 - 8000014c: 00209f33 sll t5,ra,sp - 80000150: 00004eb7 lui t4,0x4 - 80000154: 00500193 li gp,5 - 80000158: 5bdf1863 bne t5,t4,80000708 - -000000008000015c : - 8000015c: 00100093 li ra,1 - 80000160: 01f00113 li sp,31 - 80000164: 00209f33 sll t5,ra,sp - 80000168: 00100e9b addiw t4,zero,1 - 8000016c: 01fe9e93 slli t4,t4,0x1f - 80000170: 00600193 li gp,6 - 80000174: 59df1a63 bne t5,t4,80000708 - -0000000080000178 : - 80000178: fff00093 li ra,-1 - 8000017c: 00000113 li sp,0 - 80000180: 00209f33 sll t5,ra,sp - 80000184: fff00e93 li t4,-1 - 80000188: 00700193 li gp,7 - 8000018c: 57df1e63 bne t5,t4,80000708 - -0000000080000190 : - 80000190: fff00093 li ra,-1 - 80000194: 00100113 li sp,1 - 80000198: 00209f33 sll t5,ra,sp - 8000019c: ffe00e93 li t4,-2 - 800001a0: 00800193 li gp,8 - 800001a4: 57df1263 bne t5,t4,80000708 - -00000000800001a8 : - 800001a8: fff00093 li ra,-1 - 800001ac: 00700113 li sp,7 - 800001b0: 00209f33 sll t5,ra,sp - 800001b4: f8000e93 li t4,-128 - 800001b8: 00900193 li gp,9 - 800001bc: 55df1663 bne t5,t4,80000708 - -00000000800001c0 : - 800001c0: fff00093 li ra,-1 - 800001c4: 00e00113 li sp,14 - 800001c8: 00209f33 sll t5,ra,sp - 800001cc: ffffceb7 lui t4,0xffffc - 800001d0: 00a00193 li gp,10 - 800001d4: 53df1a63 bne t5,t4,80000708 - -00000000800001d8 : - 800001d8: fff00093 li ra,-1 - 800001dc: 01f00113 li sp,31 - 800001e0: 00209f33 sll t5,ra,sp - 800001e4: 80000eb7 lui t4,0x80000 - 800001e8: 00b00193 li gp,11 - 800001ec: 51df1e63 bne t5,t4,80000708 - -00000000800001f0 : - 800001f0: 212120b7 lui ra,0x21212 - 800001f4: 1210809b addiw ra,ra,289 - 800001f8: 00000113 li sp,0 - 800001fc: 00209f33 sll t5,ra,sp - 80000200: 21212eb7 lui t4,0x21212 - 80000204: 121e8e9b addiw t4,t4,289 - 80000208: 00c00193 li gp,12 - 8000020c: 4fdf1e63 bne t5,t4,80000708 - -0000000080000210 : - 80000210: 212120b7 lui ra,0x21212 - 80000214: 1210809b addiw ra,ra,289 - 80000218: 00100113 li sp,1 - 8000021c: 00209f33 sll t5,ra,sp - 80000220: 42424eb7 lui t4,0x42424 - 80000224: 242e8e9b addiw t4,t4,578 - 80000228: 00d00193 li gp,13 - 8000022c: 4ddf1e63 bne t5,t4,80000708 - -0000000080000230 : - 80000230: 212120b7 lui ra,0x21212 - 80000234: 1210809b addiw ra,ra,289 - 80000238: 00700113 li sp,7 - 8000023c: 00209f33 sll t5,ra,sp - 80000240: 01091eb7 lui t4,0x1091 - 80000244: 909e8e9b addiw t4,t4,-1783 - 80000248: 00ce9e93 slli t4,t4,0xc - 8000024c: 080e8e93 addi t4,t4,128 # 1091080 <_start-0x7ef6ef80> - 80000250: 00e00193 li gp,14 - 80000254: 4bdf1a63 bne t5,t4,80000708 - -0000000080000258 : - 80000258: 212120b7 lui ra,0x21212 - 8000025c: 1210809b addiw ra,ra,289 - 80000260: 00e00113 li sp,14 - 80000264: 00209f33 sll t5,ra,sp - 80000268: 21212eb7 lui t4,0x21212 - 8000026c: 121e8e9b addiw t4,t4,289 - 80000270: 00ee9e93 slli t4,t4,0xe - 80000274: 00f00193 li gp,15 - 80000278: 49df1863 bne t5,t4,80000708 - -000000008000027c : - 8000027c: 212120b7 lui ra,0x21212 - 80000280: 1210809b addiw ra,ra,289 - 80000284: 01f00113 li sp,31 - 80000288: 00209f33 sll t5,ra,sp - 8000028c: 21212eb7 lui t4,0x21212 - 80000290: 121e8e9b addiw t4,t4,289 - 80000294: 01fe9e93 slli t4,t4,0x1f - 80000298: 01000193 li gp,16 - 8000029c: 47df1663 bne t5,t4,80000708 - -00000000800002a0 : - 800002a0: 212120b7 lui ra,0x21212 - 800002a4: 1210809b addiw ra,ra,289 - 800002a8: fc000113 li sp,-64 - 800002ac: 00209f33 sll t5,ra,sp - 800002b0: 21212eb7 lui t4,0x21212 - 800002b4: 121e8e9b addiw t4,t4,289 - 800002b8: 01100193 li gp,17 - 800002bc: 45df1663 bne t5,t4,80000708 - -00000000800002c0 : - 800002c0: 212120b7 lui ra,0x21212 - 800002c4: 1210809b addiw ra,ra,289 - 800002c8: fc100113 li sp,-63 - 800002cc: 00209f33 sll t5,ra,sp - 800002d0: 42424eb7 lui t4,0x42424 - 800002d4: 242e8e9b addiw t4,t4,578 - 800002d8: 01200193 li gp,18 - 800002dc: 43df1663 bne t5,t4,80000708 - -00000000800002e0 : - 800002e0: 212120b7 lui ra,0x21212 - 800002e4: 1210809b addiw ra,ra,289 - 800002e8: fc700113 li sp,-57 - 800002ec: 00209f33 sll t5,ra,sp - 800002f0: 01091eb7 lui t4,0x1091 - 800002f4: 909e8e9b addiw t4,t4,-1783 - 800002f8: 00ce9e93 slli t4,t4,0xc - 800002fc: 080e8e93 addi t4,t4,128 # 1091080 <_start-0x7ef6ef80> - 80000300: 01300193 li gp,19 - 80000304: 41df1263 bne t5,t4,80000708 - -0000000080000308 : - 80000308: 212120b7 lui ra,0x21212 - 8000030c: 1210809b addiw ra,ra,289 - 80000310: fce00113 li sp,-50 - 80000314: 00209f33 sll t5,ra,sp - 80000318: 21212eb7 lui t4,0x21212 - 8000031c: 121e8e9b addiw t4,t4,289 - 80000320: 00ee9e93 slli t4,t4,0xe - 80000324: 01400193 li gp,20 - 80000328: 3fdf1063 bne t5,t4,80000708 - -000000008000032c : - 8000032c: 212120b7 lui ra,0x21212 - 80000330: 1210809b addiw ra,ra,289 - 80000334: fff00113 li sp,-1 - 80000338: 00209f33 sll t5,ra,sp - 8000033c: fff00e9b addiw t4,zero,-1 - 80000340: 03fe9e93 slli t4,t4,0x3f - 80000344: 01500193 li gp,21 - 80000348: 3ddf1063 bne t5,t4,80000708 - -000000008000034c : - 8000034c: 00100093 li ra,1 - 80000350: 03f00113 li sp,63 - 80000354: 00209f33 sll t5,ra,sp - 80000358: fff00e9b addiw t4,zero,-1 - 8000035c: 03fe9e93 slli t4,t4,0x3f - 80000360: 03200193 li gp,50 - 80000364: 3bdf1263 bne t5,t4,80000708 - -0000000080000368 : - 80000368: fff00093 li ra,-1 - 8000036c: 02700113 li sp,39 - 80000370: 00209f33 sll t5,ra,sp - 80000374: fff00e9b addiw t4,zero,-1 - 80000378: 027e9e93 slli t4,t4,0x27 - 8000037c: 03300193 li gp,51 - 80000380: 39df1463 bne t5,t4,80000708 - -0000000080000384 : - 80000384: 212120b7 lui ra,0x21212 - 80000388: 1210809b addiw ra,ra,289 - 8000038c: 02b00113 li sp,43 - 80000390: 00209f33 sll t5,ra,sp - 80000394: 00012eb7 lui t4,0x12 - 80000398: 121e8e9b addiw t4,t4,289 - 8000039c: 02be9e93 slli t4,t4,0x2b - 800003a0: 03400193 li gp,52 - 800003a4: 37df1263 bne t5,t4,80000708 - -00000000800003a8 : - 800003a8: 00100093 li ra,1 - 800003ac: 00700113 li sp,7 - 800003b0: 002090b3 sll ra,ra,sp - 800003b4: 08000e93 li t4,128 - 800003b8: 01600193 li gp,22 - 800003bc: 35d09663 bne ra,t4,80000708 - -00000000800003c0 : - 800003c0: 00100093 li ra,1 - 800003c4: 00e00113 li sp,14 - 800003c8: 00209133 sll sp,ra,sp - 800003cc: 00004eb7 lui t4,0x4 - 800003d0: 01700193 li gp,23 - 800003d4: 33d11a63 bne sp,t4,80000708 - -00000000800003d8 : - 800003d8: 00300093 li ra,3 - 800003dc: 001090b3 sll ra,ra,ra - 800003e0: 01800e93 li t4,24 - 800003e4: 01800193 li gp,24 - 800003e8: 33d09063 bne ra,t4,80000708 - -00000000800003ec : - 800003ec: 00000213 li tp,0 - 800003f0: 00100093 li ra,1 - 800003f4: 00700113 li sp,7 - 800003f8: 00209f33 sll t5,ra,sp - 800003fc: 000f0313 mv t1,t5 - 80000400: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000404: 00200293 li t0,2 - 80000408: fe5214e3 bne tp,t0,800003f0 - 8000040c: 08000e93 li t4,128 - 80000410: 01900193 li gp,25 - 80000414: 2fd31a63 bne t1,t4,80000708 - -0000000080000418 : - 80000418: 00000213 li tp,0 - 8000041c: 00100093 li ra,1 - 80000420: 00e00113 li sp,14 - 80000424: 00209f33 sll t5,ra,sp - 80000428: 00000013 nop - 8000042c: 000f0313 mv t1,t5 - 80000430: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000434: 00200293 li t0,2 - 80000438: fe5212e3 bne tp,t0,8000041c - 8000043c: 00004eb7 lui t4,0x4 - 80000440: 01a00193 li gp,26 - 80000444: 2dd31263 bne t1,t4,80000708 - -0000000080000448 : - 80000448: 00000213 li tp,0 - 8000044c: 00100093 li ra,1 - 80000450: 01f00113 li sp,31 - 80000454: 00209f33 sll t5,ra,sp - 80000458: 00000013 nop - 8000045c: 00000013 nop - 80000460: 000f0313 mv t1,t5 - 80000464: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000468: 00200293 li t0,2 - 8000046c: fe5210e3 bne tp,t0,8000044c - 80000470: 00100e9b addiw t4,zero,1 - 80000474: 01fe9e93 slli t4,t4,0x1f - 80000478: 01b00193 li gp,27 - 8000047c: 29d31663 bne t1,t4,80000708 - -0000000080000480 : - 80000480: 00000213 li tp,0 - 80000484: 00100093 li ra,1 - 80000488: 00700113 li sp,7 - 8000048c: 00209f33 sll t5,ra,sp - 80000490: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000494: 00200293 li t0,2 - 80000498: fe5216e3 bne tp,t0,80000484 - 8000049c: 08000e93 li t4,128 - 800004a0: 01c00193 li gp,28 - 800004a4: 27df1263 bne t5,t4,80000708 - -00000000800004a8 : - 800004a8: 00000213 li tp,0 - 800004ac: 00100093 li ra,1 - 800004b0: 00e00113 li sp,14 - 800004b4: 00000013 nop - 800004b8: 00209f33 sll t5,ra,sp - 800004bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004c0: 00200293 li t0,2 - 800004c4: fe5214e3 bne tp,t0,800004ac - 800004c8: 00004eb7 lui t4,0x4 - 800004cc: 01d00193 li gp,29 - 800004d0: 23df1c63 bne t5,t4,80000708 - -00000000800004d4 : - 800004d4: 00000213 li tp,0 - 800004d8: 00100093 li ra,1 - 800004dc: 01f00113 li sp,31 - 800004e0: 00000013 nop - 800004e4: 00000013 nop - 800004e8: 00209f33 sll t5,ra,sp - 800004ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004f0: 00200293 li t0,2 - 800004f4: fe5212e3 bne tp,t0,800004d8 - 800004f8: 00100e9b addiw t4,zero,1 - 800004fc: 01fe9e93 slli t4,t4,0x1f - 80000500: 01e00193 li gp,30 - 80000504: 21df1263 bne t5,t4,80000708 - -0000000080000508 : - 80000508: 00000213 li tp,0 - 8000050c: 00100093 li ra,1 - 80000510: 00000013 nop - 80000514: 00700113 li sp,7 - 80000518: 00209f33 sll t5,ra,sp - 8000051c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000520: 00200293 li t0,2 - 80000524: fe5214e3 bne tp,t0,8000050c - 80000528: 08000e93 li t4,128 - 8000052c: 01f00193 li gp,31 - 80000530: 1ddf1c63 bne t5,t4,80000708 - -0000000080000534 : - 80000534: 00000213 li tp,0 - 80000538: 00100093 li ra,1 - 8000053c: 00000013 nop - 80000540: 00e00113 li sp,14 - 80000544: 00000013 nop - 80000548: 00209f33 sll t5,ra,sp - 8000054c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000550: 00200293 li t0,2 - 80000554: fe5212e3 bne tp,t0,80000538 - 80000558: 00004eb7 lui t4,0x4 - 8000055c: 02000193 li gp,32 - 80000560: 1bdf1463 bne t5,t4,80000708 - -0000000080000564 : - 80000564: 00000213 li tp,0 - 80000568: 00100093 li ra,1 - 8000056c: 00000013 nop - 80000570: 00000013 nop - 80000574: 01f00113 li sp,31 - 80000578: 00209f33 sll t5,ra,sp - 8000057c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000580: 00200293 li t0,2 - 80000584: fe5212e3 bne tp,t0,80000568 - 80000588: 00100e9b addiw t4,zero,1 - 8000058c: 01fe9e93 slli t4,t4,0x1f - 80000590: 02100193 li gp,33 - 80000594: 17df1a63 bne t5,t4,80000708 - -0000000080000598 : - 80000598: 00000213 li tp,0 - 8000059c: 00700113 li sp,7 - 800005a0: 00100093 li ra,1 - 800005a4: 00209f33 sll t5,ra,sp - 800005a8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800005ac: 00200293 li t0,2 - 800005b0: fe5216e3 bne tp,t0,8000059c - 800005b4: 08000e93 li t4,128 - 800005b8: 02200193 li gp,34 - 800005bc: 15df1663 bne t5,t4,80000708 - -00000000800005c0 : - 800005c0: 00000213 li tp,0 - 800005c4: 00e00113 li sp,14 - 800005c8: 00100093 li ra,1 - 800005cc: 00000013 nop - 800005d0: 00209f33 sll t5,ra,sp - 800005d4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800005d8: 00200293 li t0,2 - 800005dc: fe5214e3 bne tp,t0,800005c4 - 800005e0: 00004eb7 lui t4,0x4 - 800005e4: 02300193 li gp,35 - 800005e8: 13df1063 bne t5,t4,80000708 - -00000000800005ec : - 800005ec: 00000213 li tp,0 - 800005f0: 01f00113 li sp,31 - 800005f4: 00100093 li ra,1 - 800005f8: 00000013 nop - 800005fc: 00000013 nop - 80000600: 00209f33 sll t5,ra,sp - 80000604: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000608: 00200293 li t0,2 - 8000060c: fe5212e3 bne tp,t0,800005f0 - 80000610: 00100e9b addiw t4,zero,1 - 80000614: 01fe9e93 slli t4,t4,0x1f - 80000618: 02400193 li gp,36 - 8000061c: 0fdf1663 bne t5,t4,80000708 - -0000000080000620 : - 80000620: 00000213 li tp,0 - 80000624: 00700113 li sp,7 - 80000628: 00000013 nop - 8000062c: 00100093 li ra,1 - 80000630: 00209f33 sll t5,ra,sp - 80000634: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000638: 00200293 li t0,2 - 8000063c: fe5214e3 bne tp,t0,80000624 - 80000640: 08000e93 li t4,128 - 80000644: 02500193 li gp,37 - 80000648: 0ddf1063 bne t5,t4,80000708 - -000000008000064c : - 8000064c: 00000213 li tp,0 - 80000650: 00e00113 li sp,14 - 80000654: 00000013 nop - 80000658: 00100093 li ra,1 - 8000065c: 00000013 nop - 80000660: 00209f33 sll t5,ra,sp - 80000664: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000668: 00200293 li t0,2 - 8000066c: fe5212e3 bne tp,t0,80000650 - 80000670: 00004eb7 lui t4,0x4 - 80000674: 02600193 li gp,38 - 80000678: 09df1863 bne t5,t4,80000708 - -000000008000067c : - 8000067c: 00000213 li tp,0 - 80000680: 01f00113 li sp,31 - 80000684: 00000013 nop - 80000688: 00000013 nop - 8000068c: 00100093 li ra,1 - 80000690: 00209f33 sll t5,ra,sp - 80000694: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000698: 00200293 li t0,2 - 8000069c: fe5212e3 bne tp,t0,80000680 - 800006a0: 00100e9b addiw t4,zero,1 - 800006a4: 01fe9e93 slli t4,t4,0x1f - 800006a8: 02700193 li gp,39 - 800006ac: 05df1e63 bne t5,t4,80000708 - -00000000800006b0 : - 800006b0: 00f00093 li ra,15 - 800006b4: 00101133 sll sp,zero,ra - 800006b8: 00000e93 li t4,0 - 800006bc: 02800193 li gp,40 - 800006c0: 05d11463 bne sp,t4,80000708 - -00000000800006c4 : - 800006c4: 02000093 li ra,32 - 800006c8: 00009133 sll sp,ra,zero - 800006cc: 02000e93 li t4,32 - 800006d0: 02900193 li gp,41 - 800006d4: 03d11a63 bne sp,t4,80000708 - -00000000800006d8 : - 800006d8: 000010b3 sll ra,zero,zero - 800006dc: 00000e93 li t4,0 - 800006e0: 02a00193 li gp,42 - 800006e4: 03d09263 bne ra,t4,80000708 - -00000000800006e8 : - 800006e8: 40000093 li ra,1024 - 800006ec: 00001137 lui sp,0x1 - 800006f0: 8001011b addiw sp,sp,-2048 - 800006f4: 00209033 sll zero,ra,sp - 800006f8: 00000e93 li t4,0 - 800006fc: 02b00193 li gp,43 - 80000700: 01d01463 bne zero,t4,80000708 - 80000704: 00301c63 bne zero,gp,8000071c - -0000000080000708 : - 80000708: 0ff0000f fence - 8000070c: 00018063 beqz gp,8000070c - 80000710: 00119193 slli gp,gp,0x1 - 80000714: 0011e193 ori gp,gp,1 - 80000718: 00000073 ecall - -000000008000071c : - 8000071c: 0ff0000f fence - 80000720: 00100193 li gp,1 - 80000724: 00000073 ecall - 80000728: c0001073 unimp - 8000072c: 0000 unimp - 8000072e: 0000 unimp - 80000730: 0000 unimp - 80000732: 0000 unimp - 80000734: 0000 unimp - 80000736: 0000 unimp - 80000738: 0000 unimp - 8000073a: 0000 unimp - 8000073c: 0000 unimp - 8000073e: 0000 unimp - 80000740: 0000 unimp - 80000742: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-sll.elf b/test/riscv/tests/rv64ui-p-sll.elf deleted file mode 100644 index 75144abf..00000000 Binary files a/test/riscv/tests/rv64ui-p-sll.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-slli.dump b/test/riscv/tests/rv64ui-p-slli.dump deleted file mode 100644 index f04acaad..00000000 --- a/test/riscv/tests/rv64ui-p-slli.dump +++ /dev/null @@ -1,357 +0,0 @@ - -rv64ui-p-slli: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00100093 li ra,1 - 80000100: 00009f13 slli t5,ra,0x0 - 80000104: 00100e93 li t4,1 - 80000108: 00200193 li gp,2 - 8000010c: 2fdf1463 bne t5,t4,800003f4 - -0000000080000110 : - 80000110: 00100093 li ra,1 - 80000114: 00109f13 slli t5,ra,0x1 - 80000118: 00200e93 li t4,2 - 8000011c: 00300193 li gp,3 - 80000120: 2ddf1a63 bne t5,t4,800003f4 - -0000000080000124 : - 80000124: 00100093 li ra,1 - 80000128: 00709f13 slli t5,ra,0x7 - 8000012c: 08000e93 li t4,128 - 80000130: 00400193 li gp,4 - 80000134: 2ddf1063 bne t5,t4,800003f4 - -0000000080000138 : - 80000138: 00100093 li ra,1 - 8000013c: 00e09f13 slli t5,ra,0xe - 80000140: 00004eb7 lui t4,0x4 - 80000144: 00500193 li gp,5 - 80000148: 2bdf1663 bne t5,t4,800003f4 - -000000008000014c : - 8000014c: 00100093 li ra,1 - 80000150: 01f09f13 slli t5,ra,0x1f - 80000154: 00100e9b addiw t4,zero,1 - 80000158: 01fe9e93 slli t4,t4,0x1f - 8000015c: 00600193 li gp,6 - 80000160: 29df1a63 bne t5,t4,800003f4 - -0000000080000164 : - 80000164: fff00093 li ra,-1 - 80000168: 00009f13 slli t5,ra,0x0 - 8000016c: fff00e93 li t4,-1 - 80000170: 00700193 li gp,7 - 80000174: 29df1063 bne t5,t4,800003f4 - -0000000080000178 : - 80000178: fff00093 li ra,-1 - 8000017c: 00109f13 slli t5,ra,0x1 - 80000180: ffe00e93 li t4,-2 - 80000184: 00800193 li gp,8 - 80000188: 27df1663 bne t5,t4,800003f4 - -000000008000018c : - 8000018c: fff00093 li ra,-1 - 80000190: 00709f13 slli t5,ra,0x7 - 80000194: f8000e93 li t4,-128 - 80000198: 00900193 li gp,9 - 8000019c: 25df1c63 bne t5,t4,800003f4 - -00000000800001a0 : - 800001a0: fff00093 li ra,-1 - 800001a4: 00e09f13 slli t5,ra,0xe - 800001a8: ffffceb7 lui t4,0xffffc - 800001ac: 00a00193 li gp,10 - 800001b0: 25df1263 bne t5,t4,800003f4 - -00000000800001b4 : - 800001b4: fff00093 li ra,-1 - 800001b8: 01f09f13 slli t5,ra,0x1f - 800001bc: 80000eb7 lui t4,0x80000 - 800001c0: 00b00193 li gp,11 - 800001c4: 23df1863 bne t5,t4,800003f4 - -00000000800001c8 : - 800001c8: 212120b7 lui ra,0x21212 - 800001cc: 1210809b addiw ra,ra,289 - 800001d0: 00009f13 slli t5,ra,0x0 - 800001d4: 21212eb7 lui t4,0x21212 - 800001d8: 121e8e9b addiw t4,t4,289 - 800001dc: 00c00193 li gp,12 - 800001e0: 21df1a63 bne t5,t4,800003f4 - -00000000800001e4 : - 800001e4: 212120b7 lui ra,0x21212 - 800001e8: 1210809b addiw ra,ra,289 - 800001ec: 00109f13 slli t5,ra,0x1 - 800001f0: 42424eb7 lui t4,0x42424 - 800001f4: 242e8e9b addiw t4,t4,578 - 800001f8: 00d00193 li gp,13 - 800001fc: 1fdf1c63 bne t5,t4,800003f4 - -0000000080000200 : - 80000200: 212120b7 lui ra,0x21212 - 80000204: 1210809b addiw ra,ra,289 - 80000208: 00709f13 slli t5,ra,0x7 - 8000020c: 01091eb7 lui t4,0x1091 - 80000210: 909e8e9b addiw t4,t4,-1783 - 80000214: 00ce9e93 slli t4,t4,0xc - 80000218: 080e8e93 addi t4,t4,128 # 1091080 <_start-0x7ef6ef80> - 8000021c: 00e00193 li gp,14 - 80000220: 1ddf1a63 bne t5,t4,800003f4 - -0000000080000224 : - 80000224: 212120b7 lui ra,0x21212 - 80000228: 1210809b addiw ra,ra,289 - 8000022c: 00e09f13 slli t5,ra,0xe - 80000230: 21212eb7 lui t4,0x21212 - 80000234: 121e8e9b addiw t4,t4,289 - 80000238: 00ee9e93 slli t4,t4,0xe - 8000023c: 00f00193 li gp,15 - 80000240: 1bdf1a63 bne t5,t4,800003f4 - -0000000080000244 : - 80000244: 212120b7 lui ra,0x21212 - 80000248: 1210809b addiw ra,ra,289 - 8000024c: 01f09f13 slli t5,ra,0x1f - 80000250: 21212eb7 lui t4,0x21212 - 80000254: 121e8e9b addiw t4,t4,289 - 80000258: 01fe9e93 slli t4,t4,0x1f - 8000025c: 01000193 li gp,16 - 80000260: 19df1a63 bne t5,t4,800003f4 - -0000000080000264 : - 80000264: 00100093 li ra,1 - 80000268: 03f09f13 slli t5,ra,0x3f - 8000026c: fff00e9b addiw t4,zero,-1 - 80000270: 03fe9e93 slli t4,t4,0x3f - 80000274: 03200193 li gp,50 - 80000278: 17df1e63 bne t5,t4,800003f4 - -000000008000027c : - 8000027c: fff00093 li ra,-1 - 80000280: 02709f13 slli t5,ra,0x27 - 80000284: fff00e9b addiw t4,zero,-1 - 80000288: 027e9e93 slli t4,t4,0x27 - 8000028c: 03300193 li gp,51 - 80000290: 17df1263 bne t5,t4,800003f4 - -0000000080000294 : - 80000294: 212120b7 lui ra,0x21212 - 80000298: 1210809b addiw ra,ra,289 - 8000029c: 02b09f13 slli t5,ra,0x2b - 800002a0: 00012eb7 lui t4,0x12 - 800002a4: 121e8e9b addiw t4,t4,289 - 800002a8: 02be9e93 slli t4,t4,0x2b - 800002ac: 03400193 li gp,52 - 800002b0: 15df1263 bne t5,t4,800003f4 - -00000000800002b4 : - 800002b4: 00100093 li ra,1 - 800002b8: 00709093 slli ra,ra,0x7 - 800002bc: 08000e93 li t4,128 - 800002c0: 01100193 li gp,17 - 800002c4: 13d09863 bne ra,t4,800003f4 - -00000000800002c8 : - 800002c8: 00000213 li tp,0 - 800002cc: 00100093 li ra,1 - 800002d0: 00709f13 slli t5,ra,0x7 - 800002d4: 000f0313 mv t1,t5 - 800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002dc: 00200293 li t0,2 - 800002e0: fe5216e3 bne tp,t0,800002cc - 800002e4: 08000e93 li t4,128 - 800002e8: 01200193 li gp,18 - 800002ec: 11d31463 bne t1,t4,800003f4 - -00000000800002f0 : - 800002f0: 00000213 li tp,0 - 800002f4: 00100093 li ra,1 - 800002f8: 00e09f13 slli t5,ra,0xe - 800002fc: 00000013 nop - 80000300: 000f0313 mv t1,t5 - 80000304: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000308: 00200293 li t0,2 - 8000030c: fe5214e3 bne tp,t0,800002f4 - 80000310: 00004eb7 lui t4,0x4 - 80000314: 01300193 li gp,19 - 80000318: 0dd31e63 bne t1,t4,800003f4 - -000000008000031c : - 8000031c: 00000213 li tp,0 - 80000320: 00100093 li ra,1 - 80000324: 01f09f13 slli t5,ra,0x1f - 80000328: 00000013 nop - 8000032c: 00000013 nop - 80000330: 000f0313 mv t1,t5 - 80000334: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000338: 00200293 li t0,2 - 8000033c: fe5212e3 bne tp,t0,80000320 - 80000340: 00100e9b addiw t4,zero,1 - 80000344: 01fe9e93 slli t4,t4,0x1f - 80000348: 01400193 li gp,20 - 8000034c: 0bd31463 bne t1,t4,800003f4 - -0000000080000350 : - 80000350: 00000213 li tp,0 - 80000354: 00100093 li ra,1 - 80000358: 00709f13 slli t5,ra,0x7 - 8000035c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000360: 00200293 li t0,2 - 80000364: fe5218e3 bne tp,t0,80000354 - 80000368: 08000e93 li t4,128 - 8000036c: 01500193 li gp,21 - 80000370: 09df1263 bne t5,t4,800003f4 - -0000000080000374 : - 80000374: 00000213 li tp,0 - 80000378: 00100093 li ra,1 - 8000037c: 00000013 nop - 80000380: 00e09f13 slli t5,ra,0xe - 80000384: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000388: 00200293 li t0,2 - 8000038c: fe5216e3 bne tp,t0,80000378 - 80000390: 00004eb7 lui t4,0x4 - 80000394: 01600193 li gp,22 - 80000398: 05df1e63 bne t5,t4,800003f4 - -000000008000039c : - 8000039c: 00000213 li tp,0 - 800003a0: 00100093 li ra,1 - 800003a4: 00000013 nop - 800003a8: 00000013 nop - 800003ac: 01f09f13 slli t5,ra,0x1f - 800003b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003b4: 00200293 li t0,2 - 800003b8: fe5214e3 bne tp,t0,800003a0 - 800003bc: 00100e9b addiw t4,zero,1 - 800003c0: 01fe9e93 slli t4,t4,0x1f - 800003c4: 01700193 li gp,23 - 800003c8: 03df1663 bne t5,t4,800003f4 - -00000000800003cc : - 800003cc: 01f01093 slli ra,zero,0x1f - 800003d0: 00000e93 li t4,0 - 800003d4: 01800193 li gp,24 - 800003d8: 01d09e63 bne ra,t4,800003f4 - -00000000800003dc : - 800003dc: 02100093 li ra,33 - 800003e0: 01409013 slli zero,ra,0x14 - 800003e4: 00000e93 li t4,0 - 800003e8: 01900193 li gp,25 - 800003ec: 01d01463 bne zero,t4,800003f4 - 800003f0: 00301c63 bne zero,gp,80000408 - -00000000800003f4 : - 800003f4: 0ff0000f fence - 800003f8: 00018063 beqz gp,800003f8 - 800003fc: 00119193 slli gp,gp,0x1 - 80000400: 0011e193 ori gp,gp,1 - 80000404: 00000073 ecall - -0000000080000408 : - 80000408: 0ff0000f fence - 8000040c: 00100193 li gp,1 - 80000410: 00000073 ecall - 80000414: c0001073 unimp - 80000418: 0000 unimp - 8000041a: 0000 unimp - 8000041c: 0000 unimp - 8000041e: 0000 unimp - 80000420: 0000 unimp - 80000422: 0000 unimp - 80000424: 0000 unimp - 80000426: 0000 unimp - 80000428: 0000 unimp - 8000042a: 0000 unimp - 8000042c: 0000 unimp - 8000042e: 0000 unimp - 80000430: 0000 unimp - 80000432: 0000 unimp - 80000434: 0000 unimp - 80000436: 0000 unimp - 80000438: 0000 unimp - 8000043a: 0000 unimp - 8000043c: 0000 unimp - 8000043e: 0000 unimp - 80000440: 0000 unimp - 80000442: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-slli.elf b/test/riscv/tests/rv64ui-p-slli.elf deleted file mode 100644 index 5214f29b..00000000 Binary files a/test/riscv/tests/rv64ui-p-slli.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-slliw.dump b/test/riscv/tests/rv64ui-p-slliw.dump deleted file mode 100644 index b821b9fc..00000000 --- a/test/riscv/tests/rv64ui-p-slliw.dump +++ /dev/null @@ -1,316 +0,0 @@ - -rv64ui-p-slliw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00100093 li ra,1 - 80000100: 00009f1b slliw t5,ra,0x0 - 80000104: 00100e93 li t4,1 - 80000108: 00200193 li gp,2 - 8000010c: 27df1a63 bne t5,t4,80000380 - -0000000080000110 : - 80000110: 00100093 li ra,1 - 80000114: 00109f1b slliw t5,ra,0x1 - 80000118: 00200e93 li t4,2 - 8000011c: 00300193 li gp,3 - 80000120: 27df1063 bne t5,t4,80000380 - -0000000080000124 : - 80000124: 00100093 li ra,1 - 80000128: 00709f1b slliw t5,ra,0x7 - 8000012c: 08000e93 li t4,128 - 80000130: 00400193 li gp,4 - 80000134: 25df1663 bne t5,t4,80000380 - -0000000080000138 : - 80000138: 00100093 li ra,1 - 8000013c: 00e09f1b slliw t5,ra,0xe - 80000140: 00004eb7 lui t4,0x4 - 80000144: 00500193 li gp,5 - 80000148: 23df1c63 bne t5,t4,80000380 - -000000008000014c : - 8000014c: 00100093 li ra,1 - 80000150: 01f09f1b slliw t5,ra,0x1f - 80000154: 80000eb7 lui t4,0x80000 - 80000158: 00600193 li gp,6 - 8000015c: 23df1263 bne t5,t4,80000380 - -0000000080000160 : - 80000160: fff00093 li ra,-1 - 80000164: 00009f1b slliw t5,ra,0x0 - 80000168: fff00e93 li t4,-1 - 8000016c: 00700193 li gp,7 - 80000170: 21df1863 bne t5,t4,80000380 - -0000000080000174 : - 80000174: fff00093 li ra,-1 - 80000178: 00109f1b slliw t5,ra,0x1 - 8000017c: ffe00e93 li t4,-2 - 80000180: 00800193 li gp,8 - 80000184: 1fdf1e63 bne t5,t4,80000380 - -0000000080000188 : - 80000188: fff00093 li ra,-1 - 8000018c: 00709f1b slliw t5,ra,0x7 - 80000190: f8000e93 li t4,-128 - 80000194: 00900193 li gp,9 - 80000198: 1fdf1463 bne t5,t4,80000380 - -000000008000019c : - 8000019c: fff00093 li ra,-1 - 800001a0: 00e09f1b slliw t5,ra,0xe - 800001a4: ffffceb7 lui t4,0xffffc - 800001a8: 00a00193 li gp,10 - 800001ac: 1ddf1a63 bne t5,t4,80000380 - -00000000800001b0 : - 800001b0: fff00093 li ra,-1 - 800001b4: 01f09f1b slliw t5,ra,0x1f - 800001b8: 80000eb7 lui t4,0x80000 - 800001bc: 00b00193 li gp,11 - 800001c0: 1ddf1063 bne t5,t4,80000380 - -00000000800001c4 : - 800001c4: 212120b7 lui ra,0x21212 - 800001c8: 1210809b addiw ra,ra,289 - 800001cc: 00009f1b slliw t5,ra,0x0 - 800001d0: 21212eb7 lui t4,0x21212 - 800001d4: 121e8e9b addiw t4,t4,289 - 800001d8: 00c00193 li gp,12 - 800001dc: 1bdf1263 bne t5,t4,80000380 - -00000000800001e0 : - 800001e0: 212120b7 lui ra,0x21212 - 800001e4: 1210809b addiw ra,ra,289 - 800001e8: 00109f1b slliw t5,ra,0x1 - 800001ec: 42424eb7 lui t4,0x42424 - 800001f0: 242e8e9b addiw t4,t4,578 - 800001f4: 00d00193 li gp,13 - 800001f8: 19df1463 bne t5,t4,80000380 - -00000000800001fc : - 800001fc: 212120b7 lui ra,0x21212 - 80000200: 1210809b addiw ra,ra,289 - 80000204: 00709f1b slliw t5,ra,0x7 - 80000208: 90909eb7 lui t4,0x90909 - 8000020c: 080e8e9b addiw t4,t4,128 - 80000210: 00e00193 li gp,14 - 80000214: 17df1663 bne t5,t4,80000380 - -0000000080000218 : - 80000218: 212120b7 lui ra,0x21212 - 8000021c: 1210809b addiw ra,ra,289 - 80000220: 00e09f1b slliw t5,ra,0xe - 80000224: 48484eb7 lui t4,0x48484 - 80000228: 00f00193 li gp,15 - 8000022c: 15df1a63 bne t5,t4,80000380 - -0000000080000230 : - 80000230: 212120b7 lui ra,0x21212 - 80000234: 1210809b addiw ra,ra,289 - 80000238: 01f09f1b slliw t5,ra,0x1f - 8000023c: 80000eb7 lui t4,0x80000 - 80000240: 01000193 li gp,16 - 80000244: 13df1e63 bne t5,t4,80000380 - -0000000080000248 : - 80000248: 00100093 li ra,1 - 8000024c: 0070909b slliw ra,ra,0x7 - 80000250: 08000e93 li t4,128 - 80000254: 01100193 li gp,17 - 80000258: 13d09463 bne ra,t4,80000380 - -000000008000025c : - 8000025c: 00000213 li tp,0 - 80000260: 00100093 li ra,1 - 80000264: 00709f1b slliw t5,ra,0x7 - 80000268: 000f0313 mv t1,t5 - 8000026c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000270: 00200293 li t0,2 - 80000274: fe5216e3 bne tp,t0,80000260 - 80000278: 08000e93 li t4,128 - 8000027c: 01200193 li gp,18 - 80000280: 11d31063 bne t1,t4,80000380 - -0000000080000284 : - 80000284: 00000213 li tp,0 - 80000288: 00100093 li ra,1 - 8000028c: 00e09f1b slliw t5,ra,0xe - 80000290: 00000013 nop - 80000294: 000f0313 mv t1,t5 - 80000298: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000029c: 00200293 li t0,2 - 800002a0: fe5214e3 bne tp,t0,80000288 - 800002a4: 00004eb7 lui t4,0x4 - 800002a8: 01300193 li gp,19 - 800002ac: 0dd31a63 bne t1,t4,80000380 - -00000000800002b0 : - 800002b0: 00000213 li tp,0 - 800002b4: 00100093 li ra,1 - 800002b8: 01f09f1b slliw t5,ra,0x1f - 800002bc: 00000013 nop - 800002c0: 00000013 nop - 800002c4: 000f0313 mv t1,t5 - 800002c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002cc: 00200293 li t0,2 - 800002d0: fe5212e3 bne tp,t0,800002b4 - 800002d4: 80000eb7 lui t4,0x80000 - 800002d8: 01400193 li gp,20 - 800002dc: 0bd31263 bne t1,t4,80000380 - -00000000800002e0 : - 800002e0: 00000213 li tp,0 - 800002e4: 00100093 li ra,1 - 800002e8: 00709f1b slliw t5,ra,0x7 - 800002ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002f0: 00200293 li t0,2 - 800002f4: fe5218e3 bne tp,t0,800002e4 - 800002f8: 08000e93 li t4,128 - 800002fc: 01500193 li gp,21 - 80000300: 09df1063 bne t5,t4,80000380 - -0000000080000304 : - 80000304: 00000213 li tp,0 - 80000308: 00100093 li ra,1 - 8000030c: 00000013 nop - 80000310: 00e09f1b slliw t5,ra,0xe - 80000314: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000318: 00200293 li t0,2 - 8000031c: fe5216e3 bne tp,t0,80000308 - 80000320: 00004eb7 lui t4,0x4 - 80000324: 01600193 li gp,22 - 80000328: 05df1c63 bne t5,t4,80000380 - -000000008000032c : - 8000032c: 00000213 li tp,0 - 80000330: 00100093 li ra,1 - 80000334: 00000013 nop - 80000338: 00000013 nop - 8000033c: 01f09f1b slliw t5,ra,0x1f - 80000340: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000344: 00200293 li t0,2 - 80000348: fe5214e3 bne tp,t0,80000330 - 8000034c: 80000eb7 lui t4,0x80000 - 80000350: 01700193 li gp,23 - 80000354: 03df1663 bne t5,t4,80000380 - -0000000080000358 : - 80000358: 01f0109b slliw ra,zero,0x1f - 8000035c: 00000e93 li t4,0 - 80000360: 01800193 li gp,24 - 80000364: 01d09e63 bne ra,t4,80000380 - -0000000080000368 : - 80000368: 01f00093 li ra,31 - 8000036c: 01c0901b slliw zero,ra,0x1c - 80000370: 00000e93 li t4,0 - 80000374: 01900193 li gp,25 - 80000378: 01d01463 bne zero,t4,80000380 - 8000037c: 00301c63 bne zero,gp,80000394 - -0000000080000380 : - 80000380: 0ff0000f fence - 80000384: 00018063 beqz gp,80000384 - 80000388: 00119193 slli gp,gp,0x1 - 8000038c: 0011e193 ori gp,gp,1 - 80000390: 00000073 ecall - -0000000080000394 : - 80000394: 0ff0000f fence - 80000398: 00100193 li gp,1 - 8000039c: 00000073 ecall - 800003a0: c0001073 unimp - 800003a4: 0000 unimp - 800003a6: 0000 unimp - 800003a8: 0000 unimp - 800003aa: 0000 unimp - 800003ac: 0000 unimp - 800003ae: 0000 unimp - 800003b0: 0000 unimp - 800003b2: 0000 unimp - 800003b4: 0000 unimp - 800003b6: 0000 unimp - 800003b8: 0000 unimp - 800003ba: 0000 unimp - 800003bc: 0000 unimp - 800003be: 0000 unimp - 800003c0: 0000 unimp - 800003c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-slliw.elf b/test/riscv/tests/rv64ui-p-slliw.elf deleted file mode 100644 index 556a77e0..00000000 Binary files a/test/riscv/tests/rv64ui-p-slliw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-sllw.dump b/test/riscv/tests/rv64ui-p-sllw.dump deleted file mode 100644 index 45f030a1..00000000 --- a/test/riscv/tests/rv64ui-p-sllw.dump +++ /dev/null @@ -1,550 +0,0 @@ - -rv64ui-p-sllw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00100093 li ra,1 - 80000100: 00000113 li sp,0 - 80000104: 00209f3b sllw t5,ra,sp - 80000108: 00100e93 li t4,1 - 8000010c: 00200193 li gp,2 - 80000110: 55df1c63 bne t5,t4,80000668 - -0000000080000114 : - 80000114: 00100093 li ra,1 - 80000118: 00100113 li sp,1 - 8000011c: 00209f3b sllw t5,ra,sp - 80000120: 00200e93 li t4,2 - 80000124: 00300193 li gp,3 - 80000128: 55df1063 bne t5,t4,80000668 - -000000008000012c : - 8000012c: 00100093 li ra,1 - 80000130: 00700113 li sp,7 - 80000134: 00209f3b sllw t5,ra,sp - 80000138: 08000e93 li t4,128 - 8000013c: 00400193 li gp,4 - 80000140: 53df1463 bne t5,t4,80000668 - -0000000080000144 : - 80000144: 00100093 li ra,1 - 80000148: 00e00113 li sp,14 - 8000014c: 00209f3b sllw t5,ra,sp - 80000150: 00004eb7 lui t4,0x4 - 80000154: 00500193 li gp,5 - 80000158: 51df1863 bne t5,t4,80000668 - -000000008000015c : - 8000015c: 00100093 li ra,1 - 80000160: 01f00113 li sp,31 - 80000164: 00209f3b sllw t5,ra,sp - 80000168: 80000eb7 lui t4,0x80000 - 8000016c: 00600193 li gp,6 - 80000170: 4fdf1c63 bne t5,t4,80000668 - -0000000080000174 : - 80000174: fff00093 li ra,-1 - 80000178: 00000113 li sp,0 - 8000017c: 00209f3b sllw t5,ra,sp - 80000180: fff00e93 li t4,-1 - 80000184: 00700193 li gp,7 - 80000188: 4fdf1063 bne t5,t4,80000668 - -000000008000018c : - 8000018c: fff00093 li ra,-1 - 80000190: 00100113 li sp,1 - 80000194: 00209f3b sllw t5,ra,sp - 80000198: ffe00e93 li t4,-2 - 8000019c: 00800193 li gp,8 - 800001a0: 4ddf1463 bne t5,t4,80000668 - -00000000800001a4 : - 800001a4: fff00093 li ra,-1 - 800001a8: 00700113 li sp,7 - 800001ac: 00209f3b sllw t5,ra,sp - 800001b0: f8000e93 li t4,-128 - 800001b4: 00900193 li gp,9 - 800001b8: 4bdf1863 bne t5,t4,80000668 - -00000000800001bc : - 800001bc: fff00093 li ra,-1 - 800001c0: 00e00113 li sp,14 - 800001c4: 00209f3b sllw t5,ra,sp - 800001c8: ffffceb7 lui t4,0xffffc - 800001cc: 00a00193 li gp,10 - 800001d0: 49df1c63 bne t5,t4,80000668 - -00000000800001d4 : - 800001d4: fff00093 li ra,-1 - 800001d8: 01f00113 li sp,31 - 800001dc: 00209f3b sllw t5,ra,sp - 800001e0: 80000eb7 lui t4,0x80000 - 800001e4: 00b00193 li gp,11 - 800001e8: 49df1063 bne t5,t4,80000668 - -00000000800001ec : - 800001ec: 212120b7 lui ra,0x21212 - 800001f0: 1210809b addiw ra,ra,289 - 800001f4: 00000113 li sp,0 - 800001f8: 00209f3b sllw t5,ra,sp - 800001fc: 21212eb7 lui t4,0x21212 - 80000200: 121e8e9b addiw t4,t4,289 - 80000204: 00c00193 li gp,12 - 80000208: 47df1063 bne t5,t4,80000668 - -000000008000020c : - 8000020c: 212120b7 lui ra,0x21212 - 80000210: 1210809b addiw ra,ra,289 - 80000214: 00100113 li sp,1 - 80000218: 00209f3b sllw t5,ra,sp - 8000021c: 42424eb7 lui t4,0x42424 - 80000220: 242e8e9b addiw t4,t4,578 - 80000224: 00d00193 li gp,13 - 80000228: 45df1063 bne t5,t4,80000668 - -000000008000022c : - 8000022c: 212120b7 lui ra,0x21212 - 80000230: 1210809b addiw ra,ra,289 - 80000234: 00700113 li sp,7 - 80000238: 00209f3b sllw t5,ra,sp - 8000023c: 90909eb7 lui t4,0x90909 - 80000240: 080e8e9b addiw t4,t4,128 - 80000244: 00e00193 li gp,14 - 80000248: 43df1063 bne t5,t4,80000668 - -000000008000024c : - 8000024c: 212120b7 lui ra,0x21212 - 80000250: 1210809b addiw ra,ra,289 - 80000254: 00e00113 li sp,14 - 80000258: 00209f3b sllw t5,ra,sp - 8000025c: 48484eb7 lui t4,0x48484 - 80000260: 00f00193 li gp,15 - 80000264: 41df1263 bne t5,t4,80000668 - -0000000080000268 : - 80000268: 212120b7 lui ra,0x21212 - 8000026c: 1210809b addiw ra,ra,289 - 80000270: 01f00113 li sp,31 - 80000274: 00209f3b sllw t5,ra,sp - 80000278: 80000eb7 lui t4,0x80000 - 8000027c: 01000193 li gp,16 - 80000280: 3fdf1463 bne t5,t4,80000668 - -0000000080000284 : - 80000284: 212120b7 lui ra,0x21212 - 80000288: 1210809b addiw ra,ra,289 - 8000028c: fe000113 li sp,-32 - 80000290: 00209f3b sllw t5,ra,sp - 80000294: 21212eb7 lui t4,0x21212 - 80000298: 121e8e9b addiw t4,t4,289 - 8000029c: 01100193 li gp,17 - 800002a0: 3ddf1463 bne t5,t4,80000668 - -00000000800002a4 : - 800002a4: 212120b7 lui ra,0x21212 - 800002a8: 1210809b addiw ra,ra,289 - 800002ac: fe100113 li sp,-31 - 800002b0: 00209f3b sllw t5,ra,sp - 800002b4: 42424eb7 lui t4,0x42424 - 800002b8: 242e8e9b addiw t4,t4,578 - 800002bc: 01200193 li gp,18 - 800002c0: 3bdf1463 bne t5,t4,80000668 - -00000000800002c4 : - 800002c4: 212120b7 lui ra,0x21212 - 800002c8: 1210809b addiw ra,ra,289 - 800002cc: fe700113 li sp,-25 - 800002d0: 00209f3b sllw t5,ra,sp - 800002d4: 90909eb7 lui t4,0x90909 - 800002d8: 080e8e9b addiw t4,t4,128 - 800002dc: 01300193 li gp,19 - 800002e0: 39df1463 bne t5,t4,80000668 - -00000000800002e4 : - 800002e4: 212120b7 lui ra,0x21212 - 800002e8: 1210809b addiw ra,ra,289 - 800002ec: fee00113 li sp,-18 - 800002f0: 00209f3b sllw t5,ra,sp - 800002f4: 48484eb7 lui t4,0x48484 - 800002f8: 01400193 li gp,20 - 800002fc: 37df1663 bne t5,t4,80000668 - -0000000080000300 : - 80000300: 212120b7 lui ra,0x21212 - 80000304: 1210809b addiw ra,ra,289 - 80000308: fff00113 li sp,-1 - 8000030c: 00209f3b sllw t5,ra,sp - 80000310: 80000eb7 lui t4,0x80000 - 80000314: 01500193 li gp,21 - 80000318: 35df1863 bne t5,t4,80000668 - -000000008000031c : - 8000031c: 00100093 li ra,1 - 80000320: 00700113 li sp,7 - 80000324: 002090bb sllw ra,ra,sp - 80000328: 08000e93 li t4,128 - 8000032c: 01600193 li gp,22 - 80000330: 33d09c63 bne ra,t4,80000668 - -0000000080000334 : - 80000334: 00100093 li ra,1 - 80000338: 00e00113 li sp,14 - 8000033c: 0020913b sllw sp,ra,sp - 80000340: 00004eb7 lui t4,0x4 - 80000344: 01700193 li gp,23 - 80000348: 33d11063 bne sp,t4,80000668 - -000000008000034c : - 8000034c: 00300093 li ra,3 - 80000350: 001090bb sllw ra,ra,ra - 80000354: 01800e93 li t4,24 - 80000358: 01800193 li gp,24 - 8000035c: 31d09663 bne ra,t4,80000668 - -0000000080000360 : - 80000360: 00000213 li tp,0 - 80000364: 00100093 li ra,1 - 80000368: 00700113 li sp,7 - 8000036c: 00209f3b sllw t5,ra,sp - 80000370: 000f0313 mv t1,t5 - 80000374: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000378: 00200293 li t0,2 - 8000037c: fe5214e3 bne tp,t0,80000364 - 80000380: 08000e93 li t4,128 - 80000384: 01900193 li gp,25 - 80000388: 2fd31063 bne t1,t4,80000668 - -000000008000038c : - 8000038c: 00000213 li tp,0 - 80000390: 00100093 li ra,1 - 80000394: 00e00113 li sp,14 - 80000398: 00209f3b sllw t5,ra,sp - 8000039c: 00000013 nop - 800003a0: 000f0313 mv t1,t5 - 800003a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003a8: 00200293 li t0,2 - 800003ac: fe5212e3 bne tp,t0,80000390 - 800003b0: 00004eb7 lui t4,0x4 - 800003b4: 01a00193 li gp,26 - 800003b8: 2bd31863 bne t1,t4,80000668 - -00000000800003bc : - 800003bc: 00000213 li tp,0 - 800003c0: 00100093 li ra,1 - 800003c4: 01f00113 li sp,31 - 800003c8: 00209f3b sllw t5,ra,sp - 800003cc: 00000013 nop - 800003d0: 00000013 nop - 800003d4: 000f0313 mv t1,t5 - 800003d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003dc: 00200293 li t0,2 - 800003e0: fe5210e3 bne tp,t0,800003c0 - 800003e4: 80000eb7 lui t4,0x80000 - 800003e8: 01b00193 li gp,27 - 800003ec: 27d31e63 bne t1,t4,80000668 - -00000000800003f0 : - 800003f0: 00000213 li tp,0 - 800003f4: 00100093 li ra,1 - 800003f8: 00700113 li sp,7 - 800003fc: 00209f3b sllw t5,ra,sp - 80000400: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000404: 00200293 li t0,2 - 80000408: fe5216e3 bne tp,t0,800003f4 - 8000040c: 08000e93 li t4,128 - 80000410: 01c00193 li gp,28 - 80000414: 25df1a63 bne t5,t4,80000668 - -0000000080000418 : - 80000418: 00000213 li tp,0 - 8000041c: 00100093 li ra,1 - 80000420: 00e00113 li sp,14 - 80000424: 00000013 nop - 80000428: 00209f3b sllw t5,ra,sp - 8000042c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000430: 00200293 li t0,2 - 80000434: fe5214e3 bne tp,t0,8000041c - 80000438: 00004eb7 lui t4,0x4 - 8000043c: 01d00193 li gp,29 - 80000440: 23df1463 bne t5,t4,80000668 - -0000000080000444 : - 80000444: 00000213 li tp,0 - 80000448: 00100093 li ra,1 - 8000044c: 01f00113 li sp,31 - 80000450: 00000013 nop - 80000454: 00000013 nop - 80000458: 00209f3b sllw t5,ra,sp - 8000045c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000460: 00200293 li t0,2 - 80000464: fe5212e3 bne tp,t0,80000448 - 80000468: 80000eb7 lui t4,0x80000 - 8000046c: 01e00193 li gp,30 - 80000470: 1fdf1c63 bne t5,t4,80000668 - -0000000080000474 : - 80000474: 00000213 li tp,0 - 80000478: 00100093 li ra,1 - 8000047c: 00000013 nop - 80000480: 00700113 li sp,7 - 80000484: 00209f3b sllw t5,ra,sp - 80000488: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000048c: 00200293 li t0,2 - 80000490: fe5214e3 bne tp,t0,80000478 - 80000494: 08000e93 li t4,128 - 80000498: 01f00193 li gp,31 - 8000049c: 1ddf1663 bne t5,t4,80000668 - -00000000800004a0 : - 800004a0: 00000213 li tp,0 - 800004a4: 00100093 li ra,1 - 800004a8: 00000013 nop - 800004ac: 00e00113 li sp,14 - 800004b0: 00000013 nop - 800004b4: 00209f3b sllw t5,ra,sp - 800004b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004bc: 00200293 li t0,2 - 800004c0: fe5212e3 bne tp,t0,800004a4 - 800004c4: 00004eb7 lui t4,0x4 - 800004c8: 02000193 li gp,32 - 800004cc: 19df1e63 bne t5,t4,80000668 - -00000000800004d0 : - 800004d0: 00000213 li tp,0 - 800004d4: 00100093 li ra,1 - 800004d8: 00000013 nop - 800004dc: 00000013 nop - 800004e0: 01f00113 li sp,31 - 800004e4: 00209f3b sllw t5,ra,sp - 800004e8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004ec: 00200293 li t0,2 - 800004f0: fe5212e3 bne tp,t0,800004d4 - 800004f4: 80000eb7 lui t4,0x80000 - 800004f8: 02100193 li gp,33 - 800004fc: 17df1663 bne t5,t4,80000668 - -0000000080000500 : - 80000500: 00000213 li tp,0 - 80000504: 00700113 li sp,7 - 80000508: 00100093 li ra,1 - 8000050c: 00209f3b sllw t5,ra,sp - 80000510: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000514: 00200293 li t0,2 - 80000518: fe5216e3 bne tp,t0,80000504 - 8000051c: 08000e93 li t4,128 - 80000520: 02200193 li gp,34 - 80000524: 15df1263 bne t5,t4,80000668 - -0000000080000528 : - 80000528: 00000213 li tp,0 - 8000052c: 00e00113 li sp,14 - 80000530: 00100093 li ra,1 - 80000534: 00000013 nop - 80000538: 00209f3b sllw t5,ra,sp - 8000053c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000540: 00200293 li t0,2 - 80000544: fe5214e3 bne tp,t0,8000052c - 80000548: 00004eb7 lui t4,0x4 - 8000054c: 02300193 li gp,35 - 80000550: 11df1c63 bne t5,t4,80000668 - -0000000080000554 : - 80000554: 00000213 li tp,0 - 80000558: 01f00113 li sp,31 - 8000055c: 00100093 li ra,1 - 80000560: 00000013 nop - 80000564: 00000013 nop - 80000568: 00209f3b sllw t5,ra,sp - 8000056c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000570: 00200293 li t0,2 - 80000574: fe5212e3 bne tp,t0,80000558 - 80000578: 80000eb7 lui t4,0x80000 - 8000057c: 02400193 li gp,36 - 80000580: 0fdf1463 bne t5,t4,80000668 - -0000000080000584 : - 80000584: 00000213 li tp,0 - 80000588: 00700113 li sp,7 - 8000058c: 00000013 nop - 80000590: 00100093 li ra,1 - 80000594: 00209f3b sllw t5,ra,sp - 80000598: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000059c: 00200293 li t0,2 - 800005a0: fe5214e3 bne tp,t0,80000588 - 800005a4: 08000e93 li t4,128 - 800005a8: 02500193 li gp,37 - 800005ac: 0bdf1e63 bne t5,t4,80000668 - -00000000800005b0 : - 800005b0: 00000213 li tp,0 - 800005b4: 00e00113 li sp,14 - 800005b8: 00000013 nop - 800005bc: 00100093 li ra,1 - 800005c0: 00000013 nop - 800005c4: 00209f3b sllw t5,ra,sp - 800005c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800005cc: 00200293 li t0,2 - 800005d0: fe5212e3 bne tp,t0,800005b4 - 800005d4: 00004eb7 lui t4,0x4 - 800005d8: 02600193 li gp,38 - 800005dc: 09df1663 bne t5,t4,80000668 - -00000000800005e0 : - 800005e0: 00000213 li tp,0 - 800005e4: 01f00113 li sp,31 - 800005e8: 00000013 nop - 800005ec: 00000013 nop - 800005f0: 00100093 li ra,1 - 800005f4: 00209f3b sllw t5,ra,sp - 800005f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800005fc: 00200293 li t0,2 - 80000600: fe5212e3 bne tp,t0,800005e4 - 80000604: 80000eb7 lui t4,0x80000 - 80000608: 02700193 li gp,39 - 8000060c: 05df1e63 bne t5,t4,80000668 - -0000000080000610 : - 80000610: 00f00093 li ra,15 - 80000614: 0010113b sllw sp,zero,ra - 80000618: 00000e93 li t4,0 - 8000061c: 02800193 li gp,40 - 80000620: 05d11463 bne sp,t4,80000668 - -0000000080000624 : - 80000624: 02000093 li ra,32 - 80000628: 0000913b sllw sp,ra,zero - 8000062c: 02000e93 li t4,32 - 80000630: 02900193 li gp,41 - 80000634: 03d11a63 bne sp,t4,80000668 - -0000000080000638 : - 80000638: 000010bb sllw ra,zero,zero - 8000063c: 00000e93 li t4,0 - 80000640: 02a00193 li gp,42 - 80000644: 03d09263 bne ra,t4,80000668 - -0000000080000648 : - 80000648: 40000093 li ra,1024 - 8000064c: 00001137 lui sp,0x1 - 80000650: 8001011b addiw sp,sp,-2048 - 80000654: 0020903b sllw zero,ra,sp - 80000658: 00000e93 li t4,0 - 8000065c: 02b00193 li gp,43 - 80000660: 01d01463 bne zero,t4,80000668 - 80000664: 00301c63 bne zero,gp,8000067c - -0000000080000668 : - 80000668: 0ff0000f fence - 8000066c: 00018063 beqz gp,8000066c - 80000670: 00119193 slli gp,gp,0x1 - 80000674: 0011e193 ori gp,gp,1 - 80000678: 00000073 ecall - -000000008000067c : - 8000067c: 0ff0000f fence - 80000680: 00100193 li gp,1 - 80000684: 00000073 ecall - 80000688: c0001073 unimp - 8000068c: 0000 unimp - 8000068e: 0000 unimp - 80000690: 0000 unimp - 80000692: 0000 unimp - 80000694: 0000 unimp - 80000696: 0000 unimp - 80000698: 0000 unimp - 8000069a: 0000 unimp - 8000069c: 0000 unimp - 8000069e: 0000 unimp - 800006a0: 0000 unimp - 800006a2: 0000 unimp - 800006a4: 0000 unimp - 800006a6: 0000 unimp - 800006a8: 0000 unimp - 800006aa: 0000 unimp - 800006ac: 0000 unimp - 800006ae: 0000 unimp - 800006b0: 0000 unimp - 800006b2: 0000 unimp - 800006b4: 0000 unimp - 800006b6: 0000 unimp - 800006b8: 0000 unimp - 800006ba: 0000 unimp - 800006bc: 0000 unimp - 800006be: 0000 unimp - 800006c0: 0000 unimp - 800006c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-sllw.elf b/test/riscv/tests/rv64ui-p-sllw.elf deleted file mode 100644 index 4a1c421d..00000000 Binary files a/test/riscv/tests/rv64ui-p-sllw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-slt.dump b/test/riscv/tests/rv64ui-p-slt.dump deleted file mode 100644 index 1d5f786e..00000000 --- a/test/riscv/tests/rv64ui-p-slt.dump +++ /dev/null @@ -1,485 +0,0 @@ - -rv64ui-p-slt: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00000093 li ra,0 - 80000100: 00000113 li sp,0 - 80000104: 0020af33 slt t5,ra,sp - 80000108: 00000e93 li t4,0 - 8000010c: 00200193 li gp,2 - 80000110: 4bdf1a63 bne t5,t4,800005c4 - -0000000080000114 : - 80000114: 00100093 li ra,1 - 80000118: 00100113 li sp,1 - 8000011c: 0020af33 slt t5,ra,sp - 80000120: 00000e93 li t4,0 - 80000124: 00300193 li gp,3 - 80000128: 49df1e63 bne t5,t4,800005c4 - -000000008000012c : - 8000012c: 00300093 li ra,3 - 80000130: 00700113 li sp,7 - 80000134: 0020af33 slt t5,ra,sp - 80000138: 00100e93 li t4,1 - 8000013c: 00400193 li gp,4 - 80000140: 49df1263 bne t5,t4,800005c4 - -0000000080000144 : - 80000144: 00700093 li ra,7 - 80000148: 00300113 li sp,3 - 8000014c: 0020af33 slt t5,ra,sp - 80000150: 00000e93 li t4,0 - 80000154: 00500193 li gp,5 - 80000158: 47df1663 bne t5,t4,800005c4 - -000000008000015c : - 8000015c: 00000093 li ra,0 - 80000160: ffff8137 lui sp,0xffff8 - 80000164: 0020af33 slt t5,ra,sp - 80000168: 00000e93 li t4,0 - 8000016c: 00600193 li gp,6 - 80000170: 45df1a63 bne t5,t4,800005c4 - -0000000080000174 : - 80000174: 800000b7 lui ra,0x80000 - 80000178: 00000113 li sp,0 - 8000017c: 0020af33 slt t5,ra,sp - 80000180: 00100e93 li t4,1 - 80000184: 00700193 li gp,7 - 80000188: 43df1e63 bne t5,t4,800005c4 - -000000008000018c : - 8000018c: 800000b7 lui ra,0x80000 - 80000190: ffff8137 lui sp,0xffff8 - 80000194: 0020af33 slt t5,ra,sp - 80000198: 00100e93 li t4,1 - 8000019c: 00800193 li gp,8 - 800001a0: 43df1263 bne t5,t4,800005c4 - -00000000800001a4 : - 800001a4: 00000093 li ra,0 - 800001a8: 00008137 lui sp,0x8 - 800001ac: fff1011b addiw sp,sp,-1 - 800001b0: 0020af33 slt t5,ra,sp - 800001b4: 00100e93 li t4,1 - 800001b8: 00900193 li gp,9 - 800001bc: 41df1463 bne t5,t4,800005c4 - -00000000800001c0 : - 800001c0: 800000b7 lui ra,0x80000 - 800001c4: fff0809b addiw ra,ra,-1 - 800001c8: 00000113 li sp,0 - 800001cc: 0020af33 slt t5,ra,sp - 800001d0: 00000e93 li t4,0 - 800001d4: 00a00193 li gp,10 - 800001d8: 3fdf1663 bne t5,t4,800005c4 - -00000000800001dc : - 800001dc: 800000b7 lui ra,0x80000 - 800001e0: fff0809b addiw ra,ra,-1 - 800001e4: 00008137 lui sp,0x8 - 800001e8: fff1011b addiw sp,sp,-1 - 800001ec: 0020af33 slt t5,ra,sp - 800001f0: 00000e93 li t4,0 - 800001f4: 00b00193 li gp,11 - 800001f8: 3ddf1663 bne t5,t4,800005c4 - -00000000800001fc : - 800001fc: 800000b7 lui ra,0x80000 - 80000200: 00008137 lui sp,0x8 - 80000204: fff1011b addiw sp,sp,-1 - 80000208: 0020af33 slt t5,ra,sp - 8000020c: 00100e93 li t4,1 - 80000210: 00c00193 li gp,12 - 80000214: 3bdf1863 bne t5,t4,800005c4 - -0000000080000218 : - 80000218: 800000b7 lui ra,0x80000 - 8000021c: fff0809b addiw ra,ra,-1 - 80000220: ffff8137 lui sp,0xffff8 - 80000224: 0020af33 slt t5,ra,sp - 80000228: 00000e93 li t4,0 - 8000022c: 00d00193 li gp,13 - 80000230: 39df1a63 bne t5,t4,800005c4 - -0000000080000234 : - 80000234: 00000093 li ra,0 - 80000238: fff00113 li sp,-1 - 8000023c: 0020af33 slt t5,ra,sp - 80000240: 00000e93 li t4,0 - 80000244: 00e00193 li gp,14 - 80000248: 37df1e63 bne t5,t4,800005c4 - -000000008000024c : - 8000024c: fff00093 li ra,-1 - 80000250: 00100113 li sp,1 - 80000254: 0020af33 slt t5,ra,sp - 80000258: 00100e93 li t4,1 - 8000025c: 00f00193 li gp,15 - 80000260: 37df1263 bne t5,t4,800005c4 - -0000000080000264 : - 80000264: fff00093 li ra,-1 - 80000268: fff00113 li sp,-1 - 8000026c: 0020af33 slt t5,ra,sp - 80000270: 00000e93 li t4,0 - 80000274: 01000193 li gp,16 - 80000278: 35df1663 bne t5,t4,800005c4 - -000000008000027c : - 8000027c: 00e00093 li ra,14 - 80000280: 00d00113 li sp,13 - 80000284: 0020a0b3 slt ra,ra,sp - 80000288: 00000e93 li t4,0 - 8000028c: 01100193 li gp,17 - 80000290: 33d09a63 bne ra,t4,800005c4 - -0000000080000294 : - 80000294: 00b00093 li ra,11 - 80000298: 00d00113 li sp,13 - 8000029c: 0020a133 slt sp,ra,sp - 800002a0: 00100e93 li t4,1 - 800002a4: 01200193 li gp,18 - 800002a8: 31d11e63 bne sp,t4,800005c4 - -00000000800002ac : - 800002ac: 00d00093 li ra,13 - 800002b0: 0010a0b3 slt ra,ra,ra - 800002b4: 00000e93 li t4,0 - 800002b8: 01300193 li gp,19 - 800002bc: 31d09463 bne ra,t4,800005c4 - -00000000800002c0 : - 800002c0: 00000213 li tp,0 - 800002c4: 00b00093 li ra,11 - 800002c8: 00d00113 li sp,13 - 800002cc: 0020af33 slt t5,ra,sp - 800002d0: 000f0313 mv t1,t5 - 800002d4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002d8: 00200293 li t0,2 - 800002dc: fe5214e3 bne tp,t0,800002c4 - 800002e0: 00100e93 li t4,1 - 800002e4: 01400193 li gp,20 - 800002e8: 2dd31e63 bne t1,t4,800005c4 - -00000000800002ec : - 800002ec: 00000213 li tp,0 - 800002f0: 00e00093 li ra,14 - 800002f4: 00d00113 li sp,13 - 800002f8: 0020af33 slt t5,ra,sp - 800002fc: 00000013 nop - 80000300: 000f0313 mv t1,t5 - 80000304: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000308: 00200293 li t0,2 - 8000030c: fe5212e3 bne tp,t0,800002f0 - 80000310: 00000e93 li t4,0 - 80000314: 01500193 li gp,21 - 80000318: 2bd31663 bne t1,t4,800005c4 - -000000008000031c : - 8000031c: 00000213 li tp,0 - 80000320: 00c00093 li ra,12 - 80000324: 00d00113 li sp,13 - 80000328: 0020af33 slt t5,ra,sp - 8000032c: 00000013 nop - 80000330: 00000013 nop - 80000334: 000f0313 mv t1,t5 - 80000338: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000033c: 00200293 li t0,2 - 80000340: fe5210e3 bne tp,t0,80000320 - 80000344: 00100e93 li t4,1 - 80000348: 01600193 li gp,22 - 8000034c: 27d31c63 bne t1,t4,800005c4 - -0000000080000350 : - 80000350: 00000213 li tp,0 - 80000354: 00e00093 li ra,14 - 80000358: 00d00113 li sp,13 - 8000035c: 0020af33 slt t5,ra,sp - 80000360: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000364: 00200293 li t0,2 - 80000368: fe5216e3 bne tp,t0,80000354 - 8000036c: 00000e93 li t4,0 - 80000370: 01700193 li gp,23 - 80000374: 25df1863 bne t5,t4,800005c4 - -0000000080000378 : - 80000378: 00000213 li tp,0 - 8000037c: 00b00093 li ra,11 - 80000380: 00d00113 li sp,13 - 80000384: 00000013 nop - 80000388: 0020af33 slt t5,ra,sp - 8000038c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000390: 00200293 li t0,2 - 80000394: fe5214e3 bne tp,t0,8000037c - 80000398: 00100e93 li t4,1 - 8000039c: 01800193 li gp,24 - 800003a0: 23df1263 bne t5,t4,800005c4 - -00000000800003a4 : - 800003a4: 00000213 li tp,0 - 800003a8: 00f00093 li ra,15 - 800003ac: 00d00113 li sp,13 - 800003b0: 00000013 nop - 800003b4: 00000013 nop - 800003b8: 0020af33 slt t5,ra,sp - 800003bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003c0: 00200293 li t0,2 - 800003c4: fe5212e3 bne tp,t0,800003a8 - 800003c8: 00000e93 li t4,0 - 800003cc: 01900193 li gp,25 - 800003d0: 1fdf1a63 bne t5,t4,800005c4 - -00000000800003d4 : - 800003d4: 00000213 li tp,0 - 800003d8: 00a00093 li ra,10 - 800003dc: 00000013 nop - 800003e0: 00d00113 li sp,13 - 800003e4: 0020af33 slt t5,ra,sp - 800003e8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003ec: 00200293 li t0,2 - 800003f0: fe5214e3 bne tp,t0,800003d8 - 800003f4: 00100e93 li t4,1 - 800003f8: 01a00193 li gp,26 - 800003fc: 1ddf1463 bne t5,t4,800005c4 - -0000000080000400 : - 80000400: 00000213 li tp,0 - 80000404: 01000093 li ra,16 - 80000408: 00000013 nop - 8000040c: 00d00113 li sp,13 - 80000410: 00000013 nop - 80000414: 0020af33 slt t5,ra,sp - 80000418: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000041c: 00200293 li t0,2 - 80000420: fe5212e3 bne tp,t0,80000404 - 80000424: 00000e93 li t4,0 - 80000428: 01b00193 li gp,27 - 8000042c: 19df1c63 bne t5,t4,800005c4 - -0000000080000430 : - 80000430: 00000213 li tp,0 - 80000434: 00900093 li ra,9 - 80000438: 00000013 nop - 8000043c: 00000013 nop - 80000440: 00d00113 li sp,13 - 80000444: 0020af33 slt t5,ra,sp - 80000448: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000044c: 00200293 li t0,2 - 80000450: fe5212e3 bne tp,t0,80000434 - 80000454: 00100e93 li t4,1 - 80000458: 01c00193 li gp,28 - 8000045c: 17df1463 bne t5,t4,800005c4 - -0000000080000460 : - 80000460: 00000213 li tp,0 - 80000464: 00d00113 li sp,13 - 80000468: 01100093 li ra,17 - 8000046c: 0020af33 slt t5,ra,sp - 80000470: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000474: 00200293 li t0,2 - 80000478: fe5216e3 bne tp,t0,80000464 - 8000047c: 00000e93 li t4,0 - 80000480: 01d00193 li gp,29 - 80000484: 15df1063 bne t5,t4,800005c4 - -0000000080000488 : - 80000488: 00000213 li tp,0 - 8000048c: 00d00113 li sp,13 - 80000490: 00800093 li ra,8 - 80000494: 00000013 nop - 80000498: 0020af33 slt t5,ra,sp - 8000049c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004a0: 00200293 li t0,2 - 800004a4: fe5214e3 bne tp,t0,8000048c - 800004a8: 00100e93 li t4,1 - 800004ac: 01e00193 li gp,30 - 800004b0: 11df1a63 bne t5,t4,800005c4 - -00000000800004b4 : - 800004b4: 00000213 li tp,0 - 800004b8: 00d00113 li sp,13 - 800004bc: 01200093 li ra,18 - 800004c0: 00000013 nop - 800004c4: 00000013 nop - 800004c8: 0020af33 slt t5,ra,sp - 800004cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004d0: 00200293 li t0,2 - 800004d4: fe5212e3 bne tp,t0,800004b8 - 800004d8: 00000e93 li t4,0 - 800004dc: 01f00193 li gp,31 - 800004e0: 0fdf1263 bne t5,t4,800005c4 - -00000000800004e4 : - 800004e4: 00000213 li tp,0 - 800004e8: 00d00113 li sp,13 - 800004ec: 00000013 nop - 800004f0: 00700093 li ra,7 - 800004f4: 0020af33 slt t5,ra,sp - 800004f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004fc: 00200293 li t0,2 - 80000500: fe5214e3 bne tp,t0,800004e8 - 80000504: 00100e93 li t4,1 - 80000508: 02000193 li gp,32 - 8000050c: 0bdf1c63 bne t5,t4,800005c4 - -0000000080000510 : - 80000510: 00000213 li tp,0 - 80000514: 00d00113 li sp,13 - 80000518: 00000013 nop - 8000051c: 01300093 li ra,19 - 80000520: 00000013 nop - 80000524: 0020af33 slt t5,ra,sp - 80000528: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000052c: 00200293 li t0,2 - 80000530: fe5212e3 bne tp,t0,80000514 - 80000534: 00000e93 li t4,0 - 80000538: 02100193 li gp,33 - 8000053c: 09df1463 bne t5,t4,800005c4 - -0000000080000540 : - 80000540: 00000213 li tp,0 - 80000544: 00d00113 li sp,13 - 80000548: 00000013 nop - 8000054c: 00000013 nop - 80000550: 00600093 li ra,6 - 80000554: 0020af33 slt t5,ra,sp - 80000558: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000055c: 00200293 li t0,2 - 80000560: fe5212e3 bne tp,t0,80000544 - 80000564: 00100e93 li t4,1 - 80000568: 02200193 li gp,34 - 8000056c: 05df1c63 bne t5,t4,800005c4 - -0000000080000570 : - 80000570: fff00093 li ra,-1 - 80000574: 00102133 sgtz sp,ra - 80000578: 00000e93 li t4,0 - 8000057c: 02300193 li gp,35 - 80000580: 05d11263 bne sp,t4,800005c4 - -0000000080000584 : - 80000584: fff00093 li ra,-1 - 80000588: 0000a133 sltz sp,ra - 8000058c: 00100e93 li t4,1 - 80000590: 02400193 li gp,36 - 80000594: 03d11863 bne sp,t4,800005c4 - -0000000080000598 : - 80000598: 000020b3 sltz ra,zero - 8000059c: 00000e93 li t4,0 - 800005a0: 02500193 li gp,37 - 800005a4: 03d09063 bne ra,t4,800005c4 - -00000000800005a8 : - 800005a8: 01000093 li ra,16 - 800005ac: 01e00113 li sp,30 - 800005b0: 0020a033 slt zero,ra,sp - 800005b4: 00000e93 li t4,0 - 800005b8: 02600193 li gp,38 - 800005bc: 01d01463 bne zero,t4,800005c4 - 800005c0: 00301c63 bne zero,gp,800005d8 - -00000000800005c4 : - 800005c4: 0ff0000f fence - 800005c8: 00018063 beqz gp,800005c8 - 800005cc: 00119193 slli gp,gp,0x1 - 800005d0: 0011e193 ori gp,gp,1 - 800005d4: 00000073 ecall - -00000000800005d8 : - 800005d8: 0ff0000f fence - 800005dc: 00100193 li gp,1 - 800005e0: 00000073 ecall - 800005e4: c0001073 unimp - 800005e8: 0000 unimp - 800005ea: 0000 unimp - 800005ec: 0000 unimp - 800005ee: 0000 unimp - 800005f0: 0000 unimp - 800005f2: 0000 unimp - 800005f4: 0000 unimp - 800005f6: 0000 unimp - 800005f8: 0000 unimp - 800005fa: 0000 unimp - 800005fc: 0000 unimp - 800005fe: 0000 unimp - 80000600: 0000 unimp - 80000602: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-slt.elf b/test/riscv/tests/rv64ui-p-slt.elf deleted file mode 100644 index eef5e47c..00000000 Binary files a/test/riscv/tests/rv64ui-p-slt.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-slti.dump b/test/riscv/tests/rv64ui-p-slti.dump deleted file mode 100644 index c9ca449a..00000000 --- a/test/riscv/tests/rv64ui-p-slti.dump +++ /dev/null @@ -1,320 +0,0 @@ - -rv64ui-p-slti: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00000093 li ra,0 - 80000100: 0000af13 slti t5,ra,0 - 80000104: 00000e93 li t4,0 - 80000108: 00200193 li gp,2 - 8000010c: 27df1263 bne t5,t4,80000370 - -0000000080000110 : - 80000110: 00100093 li ra,1 - 80000114: 0010af13 slti t5,ra,1 - 80000118: 00000e93 li t4,0 - 8000011c: 00300193 li gp,3 - 80000120: 25df1863 bne t5,t4,80000370 - -0000000080000124 : - 80000124: 00300093 li ra,3 - 80000128: 0070af13 slti t5,ra,7 - 8000012c: 00100e93 li t4,1 - 80000130: 00400193 li gp,4 - 80000134: 23df1e63 bne t5,t4,80000370 - -0000000080000138 : - 80000138: 00700093 li ra,7 - 8000013c: 0030af13 slti t5,ra,3 - 80000140: 00000e93 li t4,0 - 80000144: 00500193 li gp,5 - 80000148: 23df1463 bne t5,t4,80000370 - -000000008000014c : - 8000014c: 00000093 li ra,0 - 80000150: 8000af13 slti t5,ra,-2048 - 80000154: 00000e93 li t4,0 - 80000158: 00600193 li gp,6 - 8000015c: 21df1a63 bne t5,t4,80000370 - -0000000080000160 : - 80000160: 800000b7 lui ra,0x80000 - 80000164: 0000af13 slti t5,ra,0 - 80000168: 00100e93 li t4,1 - 8000016c: 00700193 li gp,7 - 80000170: 21df1063 bne t5,t4,80000370 - -0000000080000174 : - 80000174: 800000b7 lui ra,0x80000 - 80000178: 8000af13 slti t5,ra,-2048 - 8000017c: 00100e93 li t4,1 - 80000180: 00800193 li gp,8 - 80000184: 1fdf1663 bne t5,t4,80000370 - -0000000080000188 : - 80000188: 00000093 li ra,0 - 8000018c: 7ff0af13 slti t5,ra,2047 - 80000190: 00100e93 li t4,1 - 80000194: 00900193 li gp,9 - 80000198: 1ddf1c63 bne t5,t4,80000370 - -000000008000019c : - 8000019c: 800000b7 lui ra,0x80000 - 800001a0: fff0809b addiw ra,ra,-1 - 800001a4: 0000af13 slti t5,ra,0 - 800001a8: 00000e93 li t4,0 - 800001ac: 00a00193 li gp,10 - 800001b0: 1ddf1063 bne t5,t4,80000370 - -00000000800001b4 : - 800001b4: 800000b7 lui ra,0x80000 - 800001b8: fff0809b addiw ra,ra,-1 - 800001bc: 7ff0af13 slti t5,ra,2047 - 800001c0: 00000e93 li t4,0 - 800001c4: 00b00193 li gp,11 - 800001c8: 1bdf1463 bne t5,t4,80000370 - -00000000800001cc : - 800001cc: 800000b7 lui ra,0x80000 - 800001d0: 7ff0af13 slti t5,ra,2047 - 800001d4: 00100e93 li t4,1 - 800001d8: 00c00193 li gp,12 - 800001dc: 19df1a63 bne t5,t4,80000370 - -00000000800001e0 : - 800001e0: 800000b7 lui ra,0x80000 - 800001e4: fff0809b addiw ra,ra,-1 - 800001e8: 8000af13 slti t5,ra,-2048 - 800001ec: 00000e93 li t4,0 - 800001f0: 00d00193 li gp,13 - 800001f4: 17df1e63 bne t5,t4,80000370 - -00000000800001f8 : - 800001f8: 00000093 li ra,0 - 800001fc: fff0af13 slti t5,ra,-1 - 80000200: 00000e93 li t4,0 - 80000204: 00e00193 li gp,14 - 80000208: 17df1463 bne t5,t4,80000370 - -000000008000020c : - 8000020c: fff00093 li ra,-1 - 80000210: 0010af13 slti t5,ra,1 - 80000214: 00100e93 li t4,1 - 80000218: 00f00193 li gp,15 - 8000021c: 15df1a63 bne t5,t4,80000370 - -0000000080000220 : - 80000220: fff00093 li ra,-1 - 80000224: fff0af13 slti t5,ra,-1 - 80000228: 00000e93 li t4,0 - 8000022c: 01000193 li gp,16 - 80000230: 15df1063 bne t5,t4,80000370 - -0000000080000234 : - 80000234: 00b00093 li ra,11 - 80000238: 00d0a093 slti ra,ra,13 - 8000023c: 00100e93 li t4,1 - 80000240: 01100193 li gp,17 - 80000244: 13d09663 bne ra,t4,80000370 - -0000000080000248 : - 80000248: 00000213 li tp,0 - 8000024c: 00f00093 li ra,15 - 80000250: 00a0af13 slti t5,ra,10 - 80000254: 000f0313 mv t1,t5 - 80000258: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000025c: 00200293 li t0,2 - 80000260: fe5216e3 bne tp,t0,8000024c - 80000264: 00000e93 li t4,0 - 80000268: 01200193 li gp,18 - 8000026c: 11d31263 bne t1,t4,80000370 - -0000000080000270 : - 80000270: 00000213 li tp,0 - 80000274: 00a00093 li ra,10 - 80000278: 0100af13 slti t5,ra,16 - 8000027c: 00000013 nop - 80000280: 000f0313 mv t1,t5 - 80000284: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000288: 00200293 li t0,2 - 8000028c: fe5214e3 bne tp,t0,80000274 - 80000290: 00100e93 li t4,1 - 80000294: 01300193 li gp,19 - 80000298: 0dd31c63 bne t1,t4,80000370 - -000000008000029c : - 8000029c: 00000213 li tp,0 - 800002a0: 01000093 li ra,16 - 800002a4: 0090af13 slti t5,ra,9 - 800002a8: 00000013 nop - 800002ac: 00000013 nop - 800002b0: 000f0313 mv t1,t5 - 800002b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002b8: 00200293 li t0,2 - 800002bc: fe5212e3 bne tp,t0,800002a0 - 800002c0: 00000e93 li t4,0 - 800002c4: 01400193 li gp,20 - 800002c8: 0bd31463 bne t1,t4,80000370 - -00000000800002cc : - 800002cc: 00000213 li tp,0 - 800002d0: 00b00093 li ra,11 - 800002d4: 00f0af13 slti t5,ra,15 - 800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002dc: 00200293 li t0,2 - 800002e0: fe5218e3 bne tp,t0,800002d0 - 800002e4: 00100e93 li t4,1 - 800002e8: 01500193 li gp,21 - 800002ec: 09df1263 bne t5,t4,80000370 - -00000000800002f0 : - 800002f0: 00000213 li tp,0 - 800002f4: 01100093 li ra,17 - 800002f8: 00000013 nop - 800002fc: 0080af13 slti t5,ra,8 - 80000300: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000304: 00200293 li t0,2 - 80000308: fe5216e3 bne tp,t0,800002f4 - 8000030c: 00000e93 li t4,0 - 80000310: 01600193 li gp,22 - 80000314: 05df1e63 bne t5,t4,80000370 - -0000000080000318 : - 80000318: 00000213 li tp,0 - 8000031c: 00c00093 li ra,12 - 80000320: 00000013 nop - 80000324: 00000013 nop - 80000328: 00e0af13 slti t5,ra,14 - 8000032c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000330: 00200293 li t0,2 - 80000334: fe5214e3 bne tp,t0,8000031c - 80000338: 00100e93 li t4,1 - 8000033c: 01700193 li gp,23 - 80000340: 03df1863 bne t5,t4,80000370 - -0000000080000344 : - 80000344: fff02093 slti ra,zero,-1 - 80000348: 00000e93 li t4,0 - 8000034c: 01800193 li gp,24 - 80000350: 03d09063 bne ra,t4,80000370 - -0000000080000354 : - 80000354: 00ff00b7 lui ra,0xff0 - 80000358: 0ff0809b addiw ra,ra,255 - 8000035c: fff0a013 slti zero,ra,-1 - 80000360: 00000e93 li t4,0 - 80000364: 01900193 li gp,25 - 80000368: 01d01463 bne zero,t4,80000370 - 8000036c: 00301c63 bne zero,gp,80000384 - -0000000080000370 : - 80000370: 0ff0000f fence - 80000374: 00018063 beqz gp,80000374 - 80000378: 00119193 slli gp,gp,0x1 - 8000037c: 0011e193 ori gp,gp,1 - 80000380: 00000073 ecall - -0000000080000384 : - 80000384: 0ff0000f fence - 80000388: 00100193 li gp,1 - 8000038c: 00000073 ecall - 80000390: c0001073 unimp - 80000394: 0000 unimp - 80000396: 0000 unimp - 80000398: 0000 unimp - 8000039a: 0000 unimp - 8000039c: 0000 unimp - 8000039e: 0000 unimp - 800003a0: 0000 unimp - 800003a2: 0000 unimp - 800003a4: 0000 unimp - 800003a6: 0000 unimp - 800003a8: 0000 unimp - 800003aa: 0000 unimp - 800003ac: 0000 unimp - 800003ae: 0000 unimp - 800003b0: 0000 unimp - 800003b2: 0000 unimp - 800003b4: 0000 unimp - 800003b6: 0000 unimp - 800003b8: 0000 unimp - 800003ba: 0000 unimp - 800003bc: 0000 unimp - 800003be: 0000 unimp - 800003c0: 0000 unimp - 800003c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-slti.elf b/test/riscv/tests/rv64ui-p-slti.elf deleted file mode 100644 index 190f81fd..00000000 Binary files a/test/riscv/tests/rv64ui-p-slti.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-sltiu.dump b/test/riscv/tests/rv64ui-p-sltiu.dump deleted file mode 100644 index 45fe6ab3..00000000 --- a/test/riscv/tests/rv64ui-p-sltiu.dump +++ /dev/null @@ -1,320 +0,0 @@ - -rv64ui-p-sltiu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00000093 li ra,0 - 80000100: 0000bf13 sltiu t5,ra,0 - 80000104: 00000e93 li t4,0 - 80000108: 00200193 li gp,2 - 8000010c: 27df1263 bne t5,t4,80000370 - -0000000080000110 : - 80000110: 00100093 li ra,1 - 80000114: 0010bf13 seqz t5,ra - 80000118: 00000e93 li t4,0 - 8000011c: 00300193 li gp,3 - 80000120: 25df1863 bne t5,t4,80000370 - -0000000080000124 : - 80000124: 00300093 li ra,3 - 80000128: 0070bf13 sltiu t5,ra,7 - 8000012c: 00100e93 li t4,1 - 80000130: 00400193 li gp,4 - 80000134: 23df1e63 bne t5,t4,80000370 - -0000000080000138 : - 80000138: 00700093 li ra,7 - 8000013c: 0030bf13 sltiu t5,ra,3 - 80000140: 00000e93 li t4,0 - 80000144: 00500193 li gp,5 - 80000148: 23df1463 bne t5,t4,80000370 - -000000008000014c : - 8000014c: 00000093 li ra,0 - 80000150: 8000bf13 sltiu t5,ra,-2048 - 80000154: 00100e93 li t4,1 - 80000158: 00600193 li gp,6 - 8000015c: 21df1a63 bne t5,t4,80000370 - -0000000080000160 : - 80000160: 800000b7 lui ra,0x80000 - 80000164: 0000bf13 sltiu t5,ra,0 - 80000168: 00000e93 li t4,0 - 8000016c: 00700193 li gp,7 - 80000170: 21df1063 bne t5,t4,80000370 - -0000000080000174 : - 80000174: 800000b7 lui ra,0x80000 - 80000178: 8000bf13 sltiu t5,ra,-2048 - 8000017c: 00100e93 li t4,1 - 80000180: 00800193 li gp,8 - 80000184: 1fdf1663 bne t5,t4,80000370 - -0000000080000188 : - 80000188: 00000093 li ra,0 - 8000018c: 7ff0bf13 sltiu t5,ra,2047 - 80000190: 00100e93 li t4,1 - 80000194: 00900193 li gp,9 - 80000198: 1ddf1c63 bne t5,t4,80000370 - -000000008000019c : - 8000019c: 800000b7 lui ra,0x80000 - 800001a0: fff0809b addiw ra,ra,-1 - 800001a4: 0000bf13 sltiu t5,ra,0 - 800001a8: 00000e93 li t4,0 - 800001ac: 00a00193 li gp,10 - 800001b0: 1ddf1063 bne t5,t4,80000370 - -00000000800001b4 : - 800001b4: 800000b7 lui ra,0x80000 - 800001b8: fff0809b addiw ra,ra,-1 - 800001bc: 7ff0bf13 sltiu t5,ra,2047 - 800001c0: 00000e93 li t4,0 - 800001c4: 00b00193 li gp,11 - 800001c8: 1bdf1463 bne t5,t4,80000370 - -00000000800001cc : - 800001cc: 800000b7 lui ra,0x80000 - 800001d0: 7ff0bf13 sltiu t5,ra,2047 - 800001d4: 00000e93 li t4,0 - 800001d8: 00c00193 li gp,12 - 800001dc: 19df1a63 bne t5,t4,80000370 - -00000000800001e0 : - 800001e0: 800000b7 lui ra,0x80000 - 800001e4: fff0809b addiw ra,ra,-1 - 800001e8: 8000bf13 sltiu t5,ra,-2048 - 800001ec: 00100e93 li t4,1 - 800001f0: 00d00193 li gp,13 - 800001f4: 17df1e63 bne t5,t4,80000370 - -00000000800001f8 : - 800001f8: 00000093 li ra,0 - 800001fc: fff0bf13 sltiu t5,ra,-1 - 80000200: 00100e93 li t4,1 - 80000204: 00e00193 li gp,14 - 80000208: 17df1463 bne t5,t4,80000370 - -000000008000020c : - 8000020c: fff00093 li ra,-1 - 80000210: 0010bf13 seqz t5,ra - 80000214: 00000e93 li t4,0 - 80000218: 00f00193 li gp,15 - 8000021c: 15df1a63 bne t5,t4,80000370 - -0000000080000220 : - 80000220: fff00093 li ra,-1 - 80000224: fff0bf13 sltiu t5,ra,-1 - 80000228: 00000e93 li t4,0 - 8000022c: 01000193 li gp,16 - 80000230: 15df1063 bne t5,t4,80000370 - -0000000080000234 : - 80000234: 00b00093 li ra,11 - 80000238: 00d0b093 sltiu ra,ra,13 - 8000023c: 00100e93 li t4,1 - 80000240: 01100193 li gp,17 - 80000244: 13d09663 bne ra,t4,80000370 - -0000000080000248 : - 80000248: 00000213 li tp,0 - 8000024c: 00f00093 li ra,15 - 80000250: 00a0bf13 sltiu t5,ra,10 - 80000254: 000f0313 mv t1,t5 - 80000258: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000025c: 00200293 li t0,2 - 80000260: fe5216e3 bne tp,t0,8000024c - 80000264: 00000e93 li t4,0 - 80000268: 01200193 li gp,18 - 8000026c: 11d31263 bne t1,t4,80000370 - -0000000080000270 : - 80000270: 00000213 li tp,0 - 80000274: 00a00093 li ra,10 - 80000278: 0100bf13 sltiu t5,ra,16 - 8000027c: 00000013 nop - 80000280: 000f0313 mv t1,t5 - 80000284: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000288: 00200293 li t0,2 - 8000028c: fe5214e3 bne tp,t0,80000274 - 80000290: 00100e93 li t4,1 - 80000294: 01300193 li gp,19 - 80000298: 0dd31c63 bne t1,t4,80000370 - -000000008000029c : - 8000029c: 00000213 li tp,0 - 800002a0: 01000093 li ra,16 - 800002a4: 0090bf13 sltiu t5,ra,9 - 800002a8: 00000013 nop - 800002ac: 00000013 nop - 800002b0: 000f0313 mv t1,t5 - 800002b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002b8: 00200293 li t0,2 - 800002bc: fe5212e3 bne tp,t0,800002a0 - 800002c0: 00000e93 li t4,0 - 800002c4: 01400193 li gp,20 - 800002c8: 0bd31463 bne t1,t4,80000370 - -00000000800002cc : - 800002cc: 00000213 li tp,0 - 800002d0: 00b00093 li ra,11 - 800002d4: 00f0bf13 sltiu t5,ra,15 - 800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002dc: 00200293 li t0,2 - 800002e0: fe5218e3 bne tp,t0,800002d0 - 800002e4: 00100e93 li t4,1 - 800002e8: 01500193 li gp,21 - 800002ec: 09df1263 bne t5,t4,80000370 - -00000000800002f0 : - 800002f0: 00000213 li tp,0 - 800002f4: 01100093 li ra,17 - 800002f8: 00000013 nop - 800002fc: 0080bf13 sltiu t5,ra,8 - 80000300: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000304: 00200293 li t0,2 - 80000308: fe5216e3 bne tp,t0,800002f4 - 8000030c: 00000e93 li t4,0 - 80000310: 01600193 li gp,22 - 80000314: 05df1e63 bne t5,t4,80000370 - -0000000080000318 : - 80000318: 00000213 li tp,0 - 8000031c: 00c00093 li ra,12 - 80000320: 00000013 nop - 80000324: 00000013 nop - 80000328: 00e0bf13 sltiu t5,ra,14 - 8000032c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000330: 00200293 li t0,2 - 80000334: fe5214e3 bne tp,t0,8000031c - 80000338: 00100e93 li t4,1 - 8000033c: 01700193 li gp,23 - 80000340: 03df1863 bne t5,t4,80000370 - -0000000080000344 : - 80000344: fff03093 sltiu ra,zero,-1 - 80000348: 00100e93 li t4,1 - 8000034c: 01800193 li gp,24 - 80000350: 03d09063 bne ra,t4,80000370 - -0000000080000354 : - 80000354: 00ff00b7 lui ra,0xff0 - 80000358: 0ff0809b addiw ra,ra,255 - 8000035c: fff0b013 sltiu zero,ra,-1 - 80000360: 00000e93 li t4,0 - 80000364: 01900193 li gp,25 - 80000368: 01d01463 bne zero,t4,80000370 - 8000036c: 00301c63 bne zero,gp,80000384 - -0000000080000370 : - 80000370: 0ff0000f fence - 80000374: 00018063 beqz gp,80000374 - 80000378: 00119193 slli gp,gp,0x1 - 8000037c: 0011e193 ori gp,gp,1 - 80000380: 00000073 ecall - -0000000080000384 : - 80000384: 0ff0000f fence - 80000388: 00100193 li gp,1 - 8000038c: 00000073 ecall - 80000390: c0001073 unimp - 80000394: 0000 unimp - 80000396: 0000 unimp - 80000398: 0000 unimp - 8000039a: 0000 unimp - 8000039c: 0000 unimp - 8000039e: 0000 unimp - 800003a0: 0000 unimp - 800003a2: 0000 unimp - 800003a4: 0000 unimp - 800003a6: 0000 unimp - 800003a8: 0000 unimp - 800003aa: 0000 unimp - 800003ac: 0000 unimp - 800003ae: 0000 unimp - 800003b0: 0000 unimp - 800003b2: 0000 unimp - 800003b4: 0000 unimp - 800003b6: 0000 unimp - 800003b8: 0000 unimp - 800003ba: 0000 unimp - 800003bc: 0000 unimp - 800003be: 0000 unimp - 800003c0: 0000 unimp - 800003c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-sltiu.elf b/test/riscv/tests/rv64ui-p-sltiu.elf deleted file mode 100644 index 8347ab89..00000000 Binary files a/test/riscv/tests/rv64ui-p-sltiu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-sltu.dump b/test/riscv/tests/rv64ui-p-sltu.dump deleted file mode 100644 index 4b1cd23e..00000000 --- a/test/riscv/tests/rv64ui-p-sltu.dump +++ /dev/null @@ -1,500 +0,0 @@ - -rv64ui-p-sltu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00000093 li ra,0 - 80000100: 00000113 li sp,0 - 80000104: 0020bf33 sltu t5,ra,sp - 80000108: 00000e93 li t4,0 - 8000010c: 00200193 li gp,2 - 80000110: 4fdf1c63 bne t5,t4,80000608 - -0000000080000114 : - 80000114: 00100093 li ra,1 - 80000118: 00100113 li sp,1 - 8000011c: 0020bf33 sltu t5,ra,sp - 80000120: 00000e93 li t4,0 - 80000124: 00300193 li gp,3 - 80000128: 4fdf1063 bne t5,t4,80000608 - -000000008000012c : - 8000012c: 00300093 li ra,3 - 80000130: 00700113 li sp,7 - 80000134: 0020bf33 sltu t5,ra,sp - 80000138: 00100e93 li t4,1 - 8000013c: 00400193 li gp,4 - 80000140: 4ddf1463 bne t5,t4,80000608 - -0000000080000144 : - 80000144: 00700093 li ra,7 - 80000148: 00300113 li sp,3 - 8000014c: 0020bf33 sltu t5,ra,sp - 80000150: 00000e93 li t4,0 - 80000154: 00500193 li gp,5 - 80000158: 4bdf1863 bne t5,t4,80000608 - -000000008000015c : - 8000015c: 00000093 li ra,0 - 80000160: 00020137 lui sp,0x20 - 80000164: fff1011b addiw sp,sp,-1 - 80000168: 00f11113 slli sp,sp,0xf - 8000016c: 0020bf33 sltu t5,ra,sp - 80000170: 00100e93 li t4,1 - 80000174: 00600193 li gp,6 - 80000178: 49df1863 bne t5,t4,80000608 - -000000008000017c : - 8000017c: 0010009b addiw ra,zero,1 - 80000180: 01f09093 slli ra,ra,0x1f - 80000184: 00000113 li sp,0 - 80000188: 0020bf33 sltu t5,ra,sp - 8000018c: 00000e93 li t4,0 - 80000190: 00700193 li gp,7 - 80000194: 47df1a63 bne t5,t4,80000608 - -0000000080000198 : - 80000198: 0010009b addiw ra,zero,1 - 8000019c: 01f09093 slli ra,ra,0x1f - 800001a0: 00020137 lui sp,0x20 - 800001a4: fff1011b addiw sp,sp,-1 - 800001a8: 00f11113 slli sp,sp,0xf - 800001ac: 0020bf33 sltu t5,ra,sp - 800001b0: 00100e93 li t4,1 - 800001b4: 00800193 li gp,8 - 800001b8: 45df1863 bne t5,t4,80000608 - -00000000800001bc : - 800001bc: 00000093 li ra,0 - 800001c0: 00008137 lui sp,0x8 - 800001c4: fff1011b addiw sp,sp,-1 - 800001c8: 0020bf33 sltu t5,ra,sp - 800001cc: 00100e93 li t4,1 - 800001d0: 00900193 li gp,9 - 800001d4: 43df1a63 bne t5,t4,80000608 - -00000000800001d8 : - 800001d8: 800000b7 lui ra,0x80000 - 800001dc: fff0809b addiw ra,ra,-1 - 800001e0: 00000113 li sp,0 - 800001e4: 0020bf33 sltu t5,ra,sp - 800001e8: 00000e93 li t4,0 - 800001ec: 00a00193 li gp,10 - 800001f0: 41df1c63 bne t5,t4,80000608 - -00000000800001f4 : - 800001f4: 800000b7 lui ra,0x80000 - 800001f8: fff0809b addiw ra,ra,-1 - 800001fc: 00008137 lui sp,0x8 - 80000200: fff1011b addiw sp,sp,-1 - 80000204: 0020bf33 sltu t5,ra,sp - 80000208: 00000e93 li t4,0 - 8000020c: 00b00193 li gp,11 - 80000210: 3fdf1c63 bne t5,t4,80000608 - -0000000080000214 : - 80000214: 0010009b addiw ra,zero,1 - 80000218: 01f09093 slli ra,ra,0x1f - 8000021c: 00008137 lui sp,0x8 - 80000220: fff1011b addiw sp,sp,-1 - 80000224: 0020bf33 sltu t5,ra,sp - 80000228: 00000e93 li t4,0 - 8000022c: 00c00193 li gp,12 - 80000230: 3ddf1c63 bne t5,t4,80000608 - -0000000080000234 : - 80000234: 800000b7 lui ra,0x80000 - 80000238: fff0809b addiw ra,ra,-1 - 8000023c: 00020137 lui sp,0x20 - 80000240: fff1011b addiw sp,sp,-1 - 80000244: 00f11113 slli sp,sp,0xf - 80000248: 0020bf33 sltu t5,ra,sp - 8000024c: 00100e93 li t4,1 - 80000250: 00d00193 li gp,13 - 80000254: 3bdf1a63 bne t5,t4,80000608 - -0000000080000258 : - 80000258: 00000093 li ra,0 - 8000025c: 0010011b addiw sp,zero,1 - 80000260: 02011113 slli sp,sp,0x20 - 80000264: fff10113 addi sp,sp,-1 # 1ffff <_start-0x7ffe0001> - 80000268: 0020bf33 sltu t5,ra,sp - 8000026c: 00100e93 li t4,1 - 80000270: 00e00193 li gp,14 - 80000274: 39df1a63 bne t5,t4,80000608 - -0000000080000278 : - 80000278: 0010009b addiw ra,zero,1 - 8000027c: 02009093 slli ra,ra,0x20 - 80000280: fff08093 addi ra,ra,-1 # ffffffff7fffffff <_end+0xfffffffeffffdfff> - 80000284: 00100113 li sp,1 - 80000288: 0020bf33 sltu t5,ra,sp - 8000028c: 00000e93 li t4,0 - 80000290: 00f00193 li gp,15 - 80000294: 37df1a63 bne t5,t4,80000608 - -0000000080000298 : - 80000298: 0010009b addiw ra,zero,1 - 8000029c: 02009093 slli ra,ra,0x20 - 800002a0: fff08093 addi ra,ra,-1 - 800002a4: 0010011b addiw sp,zero,1 - 800002a8: 02011113 slli sp,sp,0x20 - 800002ac: fff10113 addi sp,sp,-1 - 800002b0: 0020bf33 sltu t5,ra,sp - 800002b4: 00000e93 li t4,0 - 800002b8: 01000193 li gp,16 - 800002bc: 35df1663 bne t5,t4,80000608 - -00000000800002c0 : - 800002c0: 00e00093 li ra,14 - 800002c4: 00d00113 li sp,13 - 800002c8: 0020b0b3 sltu ra,ra,sp - 800002cc: 00000e93 li t4,0 - 800002d0: 01100193 li gp,17 - 800002d4: 33d09a63 bne ra,t4,80000608 - -00000000800002d8 : - 800002d8: 00b00093 li ra,11 - 800002dc: 00d00113 li sp,13 - 800002e0: 0020b133 sltu sp,ra,sp - 800002e4: 00100e93 li t4,1 - 800002e8: 01200193 li gp,18 - 800002ec: 31d11e63 bne sp,t4,80000608 - -00000000800002f0 : - 800002f0: 00d00093 li ra,13 - 800002f4: 0010b0b3 sltu ra,ra,ra - 800002f8: 00000e93 li t4,0 - 800002fc: 01300193 li gp,19 - 80000300: 31d09463 bne ra,t4,80000608 - -0000000080000304 : - 80000304: 00000213 li tp,0 - 80000308: 00b00093 li ra,11 - 8000030c: 00d00113 li sp,13 - 80000310: 0020bf33 sltu t5,ra,sp - 80000314: 000f0313 mv t1,t5 - 80000318: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000031c: 00200293 li t0,2 - 80000320: fe5214e3 bne tp,t0,80000308 - 80000324: 00100e93 li t4,1 - 80000328: 01400193 li gp,20 - 8000032c: 2dd31e63 bne t1,t4,80000608 - -0000000080000330 : - 80000330: 00000213 li tp,0 - 80000334: 00e00093 li ra,14 - 80000338: 00d00113 li sp,13 - 8000033c: 0020bf33 sltu t5,ra,sp - 80000340: 00000013 nop - 80000344: 000f0313 mv t1,t5 - 80000348: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000034c: 00200293 li t0,2 - 80000350: fe5212e3 bne tp,t0,80000334 - 80000354: 00000e93 li t4,0 - 80000358: 01500193 li gp,21 - 8000035c: 2bd31663 bne t1,t4,80000608 - -0000000080000360 : - 80000360: 00000213 li tp,0 - 80000364: 00c00093 li ra,12 - 80000368: 00d00113 li sp,13 - 8000036c: 0020bf33 sltu t5,ra,sp - 80000370: 00000013 nop - 80000374: 00000013 nop - 80000378: 000f0313 mv t1,t5 - 8000037c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000380: 00200293 li t0,2 - 80000384: fe5210e3 bne tp,t0,80000364 - 80000388: 00100e93 li t4,1 - 8000038c: 01600193 li gp,22 - 80000390: 27d31c63 bne t1,t4,80000608 - -0000000080000394 : - 80000394: 00000213 li tp,0 - 80000398: 00e00093 li ra,14 - 8000039c: 00d00113 li sp,13 - 800003a0: 0020bf33 sltu t5,ra,sp - 800003a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003a8: 00200293 li t0,2 - 800003ac: fe5216e3 bne tp,t0,80000398 - 800003b0: 00000e93 li t4,0 - 800003b4: 01700193 li gp,23 - 800003b8: 25df1863 bne t5,t4,80000608 - -00000000800003bc : - 800003bc: 00000213 li tp,0 - 800003c0: 00b00093 li ra,11 - 800003c4: 00d00113 li sp,13 - 800003c8: 00000013 nop - 800003cc: 0020bf33 sltu t5,ra,sp - 800003d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003d4: 00200293 li t0,2 - 800003d8: fe5214e3 bne tp,t0,800003c0 - 800003dc: 00100e93 li t4,1 - 800003e0: 01800193 li gp,24 - 800003e4: 23df1263 bne t5,t4,80000608 - -00000000800003e8 : - 800003e8: 00000213 li tp,0 - 800003ec: 00f00093 li ra,15 - 800003f0: 00d00113 li sp,13 - 800003f4: 00000013 nop - 800003f8: 00000013 nop - 800003fc: 0020bf33 sltu t5,ra,sp - 80000400: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000404: 00200293 li t0,2 - 80000408: fe5212e3 bne tp,t0,800003ec - 8000040c: 00000e93 li t4,0 - 80000410: 01900193 li gp,25 - 80000414: 1fdf1a63 bne t5,t4,80000608 - -0000000080000418 : - 80000418: 00000213 li tp,0 - 8000041c: 00a00093 li ra,10 - 80000420: 00000013 nop - 80000424: 00d00113 li sp,13 - 80000428: 0020bf33 sltu t5,ra,sp - 8000042c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000430: 00200293 li t0,2 - 80000434: fe5214e3 bne tp,t0,8000041c - 80000438: 00100e93 li t4,1 - 8000043c: 01a00193 li gp,26 - 80000440: 1ddf1463 bne t5,t4,80000608 - -0000000080000444 : - 80000444: 00000213 li tp,0 - 80000448: 01000093 li ra,16 - 8000044c: 00000013 nop - 80000450: 00d00113 li sp,13 - 80000454: 00000013 nop - 80000458: 0020bf33 sltu t5,ra,sp - 8000045c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000460: 00200293 li t0,2 - 80000464: fe5212e3 bne tp,t0,80000448 - 80000468: 00000e93 li t4,0 - 8000046c: 01b00193 li gp,27 - 80000470: 19df1c63 bne t5,t4,80000608 - -0000000080000474 : - 80000474: 00000213 li tp,0 - 80000478: 00900093 li ra,9 - 8000047c: 00000013 nop - 80000480: 00000013 nop - 80000484: 00d00113 li sp,13 - 80000488: 0020bf33 sltu t5,ra,sp - 8000048c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000490: 00200293 li t0,2 - 80000494: fe5212e3 bne tp,t0,80000478 - 80000498: 00100e93 li t4,1 - 8000049c: 01c00193 li gp,28 - 800004a0: 17df1463 bne t5,t4,80000608 - -00000000800004a4 : - 800004a4: 00000213 li tp,0 - 800004a8: 00d00113 li sp,13 - 800004ac: 01100093 li ra,17 - 800004b0: 0020bf33 sltu t5,ra,sp - 800004b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004b8: 00200293 li t0,2 - 800004bc: fe5216e3 bne tp,t0,800004a8 - 800004c0: 00000e93 li t4,0 - 800004c4: 01d00193 li gp,29 - 800004c8: 15df1063 bne t5,t4,80000608 - -00000000800004cc : - 800004cc: 00000213 li tp,0 - 800004d0: 00d00113 li sp,13 - 800004d4: 00800093 li ra,8 - 800004d8: 00000013 nop - 800004dc: 0020bf33 sltu t5,ra,sp - 800004e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004e4: 00200293 li t0,2 - 800004e8: fe5214e3 bne tp,t0,800004d0 - 800004ec: 00100e93 li t4,1 - 800004f0: 01e00193 li gp,30 - 800004f4: 11df1a63 bne t5,t4,80000608 - -00000000800004f8 : - 800004f8: 00000213 li tp,0 - 800004fc: 00d00113 li sp,13 - 80000500: 01200093 li ra,18 - 80000504: 00000013 nop - 80000508: 00000013 nop - 8000050c: 0020bf33 sltu t5,ra,sp - 80000510: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000514: 00200293 li t0,2 - 80000518: fe5212e3 bne tp,t0,800004fc - 8000051c: 00000e93 li t4,0 - 80000520: 01f00193 li gp,31 - 80000524: 0fdf1263 bne t5,t4,80000608 - -0000000080000528 : - 80000528: 00000213 li tp,0 - 8000052c: 00d00113 li sp,13 - 80000530: 00000013 nop - 80000534: 00700093 li ra,7 - 80000538: 0020bf33 sltu t5,ra,sp - 8000053c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000540: 00200293 li t0,2 - 80000544: fe5214e3 bne tp,t0,8000052c - 80000548: 00100e93 li t4,1 - 8000054c: 02000193 li gp,32 - 80000550: 0bdf1c63 bne t5,t4,80000608 - -0000000080000554 : - 80000554: 00000213 li tp,0 - 80000558: 00d00113 li sp,13 - 8000055c: 00000013 nop - 80000560: 01300093 li ra,19 - 80000564: 00000013 nop - 80000568: 0020bf33 sltu t5,ra,sp - 8000056c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000570: 00200293 li t0,2 - 80000574: fe5212e3 bne tp,t0,80000558 - 80000578: 00000e93 li t4,0 - 8000057c: 02100193 li gp,33 - 80000580: 09df1463 bne t5,t4,80000608 - -0000000080000584 : - 80000584: 00000213 li tp,0 - 80000588: 00d00113 li sp,13 - 8000058c: 00000013 nop - 80000590: 00000013 nop - 80000594: 00600093 li ra,6 - 80000598: 0020bf33 sltu t5,ra,sp - 8000059c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800005a0: 00200293 li t0,2 - 800005a4: fe5212e3 bne tp,t0,80000588 - 800005a8: 00100e93 li t4,1 - 800005ac: 02200193 li gp,34 - 800005b0: 05df1c63 bne t5,t4,80000608 - -00000000800005b4 : - 800005b4: fff00093 li ra,-1 - 800005b8: 00103133 snez sp,ra - 800005bc: 00100e93 li t4,1 - 800005c0: 02300193 li gp,35 - 800005c4: 05d11263 bne sp,t4,80000608 - -00000000800005c8 : - 800005c8: fff00093 li ra,-1 - 800005cc: 0000b133 sltu sp,ra,zero - 800005d0: 00000e93 li t4,0 - 800005d4: 02400193 li gp,36 - 800005d8: 03d11863 bne sp,t4,80000608 - -00000000800005dc : - 800005dc: 000030b3 snez ra,zero - 800005e0: 00000e93 li t4,0 - 800005e4: 02500193 li gp,37 - 800005e8: 03d09063 bne ra,t4,80000608 - -00000000800005ec : - 800005ec: 01000093 li ra,16 - 800005f0: 01e00113 li sp,30 - 800005f4: 0020b033 sltu zero,ra,sp - 800005f8: 00000e93 li t4,0 - 800005fc: 02600193 li gp,38 - 80000600: 01d01463 bne zero,t4,80000608 - 80000604: 00301c63 bne zero,gp,8000061c - -0000000080000608 : - 80000608: 0ff0000f fence - 8000060c: 00018063 beqz gp,8000060c - 80000610: 00119193 slli gp,gp,0x1 - 80000614: 0011e193 ori gp,gp,1 - 80000618: 00000073 ecall - -000000008000061c : - 8000061c: 0ff0000f fence - 80000620: 00100193 li gp,1 - 80000624: 00000073 ecall - 80000628: c0001073 unimp - 8000062c: 0000 unimp - 8000062e: 0000 unimp - 80000630: 0000 unimp - 80000632: 0000 unimp - 80000634: 0000 unimp - 80000636: 0000 unimp - 80000638: 0000 unimp - 8000063a: 0000 unimp - 8000063c: 0000 unimp - 8000063e: 0000 unimp - 80000640: 0000 unimp - 80000642: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-sltu.elf b/test/riscv/tests/rv64ui-p-sltu.elf deleted file mode 100644 index a1ef113c..00000000 Binary files a/test/riscv/tests/rv64ui-p-sltu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-sra.dump b/test/riscv/tests/rv64ui-p-sra.dump deleted file mode 100644 index 4b5e4ed5..00000000 --- a/test/riscv/tests/rv64ui-p-sra.dump +++ /dev/null @@ -1,538 +0,0 @@ - -rv64ui-p-sra: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 800000b7 lui ra,0x80000 - 80000100: 00000113 li sp,0 - 80000104: 4020df33 sra t5,ra,sp - 80000108: 80000eb7 lui t4,0x80000 - 8000010c: 00200193 li gp,2 - 80000110: 59df1463 bne t5,t4,80000698 - -0000000080000114 : - 80000114: 800000b7 lui ra,0x80000 - 80000118: 00100113 li sp,1 - 8000011c: 4020df33 sra t5,ra,sp - 80000120: c0000eb7 lui t4,0xc0000 - 80000124: 00300193 li gp,3 - 80000128: 57df1863 bne t5,t4,80000698 - -000000008000012c : - 8000012c: 800000b7 lui ra,0x80000 - 80000130: 00700113 li sp,7 - 80000134: 4020df33 sra t5,ra,sp - 80000138: ff000eb7 lui t4,0xff000 - 8000013c: 00400193 li gp,4 - 80000140: 55df1c63 bne t5,t4,80000698 - -0000000080000144 : - 80000144: 800000b7 lui ra,0x80000 - 80000148: 00e00113 li sp,14 - 8000014c: 4020df33 sra t5,ra,sp - 80000150: fffe0eb7 lui t4,0xfffe0 - 80000154: 00500193 li gp,5 - 80000158: 55df1063 bne t5,t4,80000698 - -000000008000015c : - 8000015c: 800000b7 lui ra,0x80000 - 80000160: 0010809b addiw ra,ra,1 - 80000164: 01f00113 li sp,31 - 80000168: 4020df33 sra t5,ra,sp - 8000016c: fff00e93 li t4,-1 - 80000170: 00600193 li gp,6 - 80000174: 53df1263 bne t5,t4,80000698 - -0000000080000178 : - 80000178: 800000b7 lui ra,0x80000 - 8000017c: fff0809b addiw ra,ra,-1 - 80000180: 00000113 li sp,0 - 80000184: 4020df33 sra t5,ra,sp - 80000188: 80000eb7 lui t4,0x80000 - 8000018c: fffe8e9b addiw t4,t4,-1 - 80000190: 00700193 li gp,7 - 80000194: 51df1263 bne t5,t4,80000698 - -0000000080000198 : - 80000198: 800000b7 lui ra,0x80000 - 8000019c: fff0809b addiw ra,ra,-1 - 800001a0: 00100113 li sp,1 - 800001a4: 4020df33 sra t5,ra,sp - 800001a8: 40000eb7 lui t4,0x40000 - 800001ac: fffe8e9b addiw t4,t4,-1 - 800001b0: 00800193 li gp,8 - 800001b4: 4fdf1263 bne t5,t4,80000698 - -00000000800001b8 : - 800001b8: 800000b7 lui ra,0x80000 - 800001bc: fff0809b addiw ra,ra,-1 - 800001c0: 00700113 li sp,7 - 800001c4: 4020df33 sra t5,ra,sp - 800001c8: 01000eb7 lui t4,0x1000 - 800001cc: fffe8e9b addiw t4,t4,-1 - 800001d0: 00900193 li gp,9 - 800001d4: 4ddf1263 bne t5,t4,80000698 - -00000000800001d8 : - 800001d8: 800000b7 lui ra,0x80000 - 800001dc: fff0809b addiw ra,ra,-1 - 800001e0: 00e00113 li sp,14 - 800001e4: 4020df33 sra t5,ra,sp - 800001e8: 00020eb7 lui t4,0x20 - 800001ec: fffe8e9b addiw t4,t4,-1 - 800001f0: 00a00193 li gp,10 - 800001f4: 4bdf1263 bne t5,t4,80000698 - -00000000800001f8 : - 800001f8: 800000b7 lui ra,0x80000 - 800001fc: fff0809b addiw ra,ra,-1 - 80000200: 01f00113 li sp,31 - 80000204: 4020df33 sra t5,ra,sp - 80000208: 00000e93 li t4,0 - 8000020c: 00b00193 li gp,11 - 80000210: 49df1463 bne t5,t4,80000698 - -0000000080000214 : - 80000214: 818180b7 lui ra,0x81818 - 80000218: 1810809b addiw ra,ra,385 - 8000021c: 00000113 li sp,0 - 80000220: 4020df33 sra t5,ra,sp - 80000224: 81818eb7 lui t4,0x81818 - 80000228: 181e8e9b addiw t4,t4,385 - 8000022c: 00c00193 li gp,12 - 80000230: 47df1463 bne t5,t4,80000698 - -0000000080000234 : - 80000234: 818180b7 lui ra,0x81818 - 80000238: 1810809b addiw ra,ra,385 - 8000023c: 00100113 li sp,1 - 80000240: 4020df33 sra t5,ra,sp - 80000244: c0c0ceb7 lui t4,0xc0c0c - 80000248: 0c0e8e9b addiw t4,t4,192 - 8000024c: 00d00193 li gp,13 - 80000250: 45df1463 bne t5,t4,80000698 - -0000000080000254 : - 80000254: 818180b7 lui ra,0x81818 - 80000258: 1810809b addiw ra,ra,385 - 8000025c: 00700113 li sp,7 - 80000260: 4020df33 sra t5,ra,sp - 80000264: ff030eb7 lui t4,0xff030 - 80000268: 303e8e9b addiw t4,t4,771 - 8000026c: 00e00193 li gp,14 - 80000270: 43df1463 bne t5,t4,80000698 - -0000000080000274 : - 80000274: 818180b7 lui ra,0x81818 - 80000278: 1810809b addiw ra,ra,385 - 8000027c: 00e00113 li sp,14 - 80000280: 4020df33 sra t5,ra,sp - 80000284: fffe0eb7 lui t4,0xfffe0 - 80000288: 606e8e9b addiw t4,t4,1542 - 8000028c: 00f00193 li gp,15 - 80000290: 41df1463 bne t5,t4,80000698 - -0000000080000294 : - 80000294: 818180b7 lui ra,0x81818 - 80000298: 1810809b addiw ra,ra,385 - 8000029c: 01f00113 li sp,31 - 800002a0: 4020df33 sra t5,ra,sp - 800002a4: fff00e93 li t4,-1 - 800002a8: 01000193 li gp,16 - 800002ac: 3fdf1663 bne t5,t4,80000698 - -00000000800002b0 : - 800002b0: 818180b7 lui ra,0x81818 - 800002b4: 1810809b addiw ra,ra,385 - 800002b8: fc000113 li sp,-64 - 800002bc: 4020df33 sra t5,ra,sp - 800002c0: 81818eb7 lui t4,0x81818 - 800002c4: 181e8e9b addiw t4,t4,385 - 800002c8: 01100193 li gp,17 - 800002cc: 3ddf1663 bne t5,t4,80000698 - -00000000800002d0 : - 800002d0: 818180b7 lui ra,0x81818 - 800002d4: 1810809b addiw ra,ra,385 - 800002d8: fc100113 li sp,-63 - 800002dc: 4020df33 sra t5,ra,sp - 800002e0: c0c0ceb7 lui t4,0xc0c0c - 800002e4: 0c0e8e9b addiw t4,t4,192 - 800002e8: 01200193 li gp,18 - 800002ec: 3bdf1663 bne t5,t4,80000698 - -00000000800002f0 : - 800002f0: 818180b7 lui ra,0x81818 - 800002f4: 1810809b addiw ra,ra,385 - 800002f8: fc700113 li sp,-57 - 800002fc: 4020df33 sra t5,ra,sp - 80000300: ff030eb7 lui t4,0xff030 - 80000304: 303e8e9b addiw t4,t4,771 - 80000308: 01300193 li gp,19 - 8000030c: 39df1663 bne t5,t4,80000698 - -0000000080000310 : - 80000310: 818180b7 lui ra,0x81818 - 80000314: 1810809b addiw ra,ra,385 - 80000318: fce00113 li sp,-50 - 8000031c: 4020df33 sra t5,ra,sp - 80000320: fffe0eb7 lui t4,0xfffe0 - 80000324: 606e8e9b addiw t4,t4,1542 - 80000328: 01400193 li gp,20 - 8000032c: 37df1663 bne t5,t4,80000698 - -0000000080000330 : - 80000330: 818180b7 lui ra,0x81818 - 80000334: 1810809b addiw ra,ra,385 - 80000338: fff00113 li sp,-1 - 8000033c: 4020df33 sra t5,ra,sp - 80000340: fff00e93 li t4,-1 - 80000344: 01500193 li gp,21 - 80000348: 35df1863 bne t5,t4,80000698 - -000000008000034c : - 8000034c: 800000b7 lui ra,0x80000 - 80000350: 00700113 li sp,7 - 80000354: 4020d0b3 sra ra,ra,sp - 80000358: ff000eb7 lui t4,0xff000 - 8000035c: 01600193 li gp,22 - 80000360: 33d09c63 bne ra,t4,80000698 - -0000000080000364 : - 80000364: 800000b7 lui ra,0x80000 - 80000368: 00e00113 li sp,14 - 8000036c: 4020d133 sra sp,ra,sp - 80000370: fffe0eb7 lui t4,0xfffe0 - 80000374: 01700193 li gp,23 - 80000378: 33d11063 bne sp,t4,80000698 - -000000008000037c : - 8000037c: 00700093 li ra,7 - 80000380: 4010d0b3 sra ra,ra,ra - 80000384: 00000e93 li t4,0 - 80000388: 01800193 li gp,24 - 8000038c: 31d09663 bne ra,t4,80000698 - -0000000080000390 : - 80000390: 00000213 li tp,0 - 80000394: 800000b7 lui ra,0x80000 - 80000398: 00700113 li sp,7 - 8000039c: 4020df33 sra t5,ra,sp - 800003a0: 000f0313 mv t1,t5 - 800003a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003a8: 00200293 li t0,2 - 800003ac: fe5214e3 bne tp,t0,80000394 - 800003b0: ff000eb7 lui t4,0xff000 - 800003b4: 01900193 li gp,25 - 800003b8: 2fd31063 bne t1,t4,80000698 - -00000000800003bc : - 800003bc: 00000213 li tp,0 - 800003c0: 800000b7 lui ra,0x80000 - 800003c4: 00e00113 li sp,14 - 800003c8: 4020df33 sra t5,ra,sp - 800003cc: 00000013 nop - 800003d0: 000f0313 mv t1,t5 - 800003d4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003d8: 00200293 li t0,2 - 800003dc: fe5212e3 bne tp,t0,800003c0 - 800003e0: fffe0eb7 lui t4,0xfffe0 - 800003e4: 01a00193 li gp,26 - 800003e8: 2bd31863 bne t1,t4,80000698 - -00000000800003ec : - 800003ec: 00000213 li tp,0 - 800003f0: 800000b7 lui ra,0x80000 - 800003f4: 01f00113 li sp,31 - 800003f8: 4020df33 sra t5,ra,sp - 800003fc: 00000013 nop - 80000400: 00000013 nop - 80000404: 000f0313 mv t1,t5 - 80000408: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000040c: 00200293 li t0,2 - 80000410: fe5210e3 bne tp,t0,800003f0 - 80000414: fff00e93 li t4,-1 - 80000418: 01b00193 li gp,27 - 8000041c: 27d31e63 bne t1,t4,80000698 - -0000000080000420 : - 80000420: 00000213 li tp,0 - 80000424: 800000b7 lui ra,0x80000 - 80000428: 00700113 li sp,7 - 8000042c: 4020df33 sra t5,ra,sp - 80000430: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000434: 00200293 li t0,2 - 80000438: fe5216e3 bne tp,t0,80000424 - 8000043c: ff000eb7 lui t4,0xff000 - 80000440: 01c00193 li gp,28 - 80000444: 25df1a63 bne t5,t4,80000698 - -0000000080000448 : - 80000448: 00000213 li tp,0 - 8000044c: 800000b7 lui ra,0x80000 - 80000450: 00e00113 li sp,14 - 80000454: 00000013 nop - 80000458: 4020df33 sra t5,ra,sp - 8000045c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000460: 00200293 li t0,2 - 80000464: fe5214e3 bne tp,t0,8000044c - 80000468: fffe0eb7 lui t4,0xfffe0 - 8000046c: 01d00193 li gp,29 - 80000470: 23df1463 bne t5,t4,80000698 - -0000000080000474 : - 80000474: 00000213 li tp,0 - 80000478: 800000b7 lui ra,0x80000 - 8000047c: 01f00113 li sp,31 - 80000480: 00000013 nop - 80000484: 00000013 nop - 80000488: 4020df33 sra t5,ra,sp - 8000048c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000490: 00200293 li t0,2 - 80000494: fe5212e3 bne tp,t0,80000478 - 80000498: fff00e93 li t4,-1 - 8000049c: 01e00193 li gp,30 - 800004a0: 1fdf1c63 bne t5,t4,80000698 - -00000000800004a4 : - 800004a4: 00000213 li tp,0 - 800004a8: 800000b7 lui ra,0x80000 - 800004ac: 00000013 nop - 800004b0: 00700113 li sp,7 - 800004b4: 4020df33 sra t5,ra,sp - 800004b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004bc: 00200293 li t0,2 - 800004c0: fe5214e3 bne tp,t0,800004a8 - 800004c4: ff000eb7 lui t4,0xff000 - 800004c8: 01f00193 li gp,31 - 800004cc: 1ddf1663 bne t5,t4,80000698 - -00000000800004d0 : - 800004d0: 00000213 li tp,0 - 800004d4: 800000b7 lui ra,0x80000 - 800004d8: 00000013 nop - 800004dc: 00e00113 li sp,14 - 800004e0: 00000013 nop - 800004e4: 4020df33 sra t5,ra,sp - 800004e8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004ec: 00200293 li t0,2 - 800004f0: fe5212e3 bne tp,t0,800004d4 - 800004f4: fffe0eb7 lui t4,0xfffe0 - 800004f8: 02000193 li gp,32 - 800004fc: 19df1e63 bne t5,t4,80000698 - -0000000080000500 : - 80000500: 00000213 li tp,0 - 80000504: 800000b7 lui ra,0x80000 - 80000508: 00000013 nop - 8000050c: 00000013 nop - 80000510: 01f00113 li sp,31 - 80000514: 4020df33 sra t5,ra,sp - 80000518: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000051c: 00200293 li t0,2 - 80000520: fe5212e3 bne tp,t0,80000504 - 80000524: fff00e93 li t4,-1 - 80000528: 02100193 li gp,33 - 8000052c: 17df1663 bne t5,t4,80000698 - -0000000080000530 : - 80000530: 00000213 li tp,0 - 80000534: 00700113 li sp,7 - 80000538: 800000b7 lui ra,0x80000 - 8000053c: 4020df33 sra t5,ra,sp - 80000540: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000544: 00200293 li t0,2 - 80000548: fe5216e3 bne tp,t0,80000534 - 8000054c: ff000eb7 lui t4,0xff000 - 80000550: 02200193 li gp,34 - 80000554: 15df1263 bne t5,t4,80000698 - -0000000080000558 : - 80000558: 00000213 li tp,0 - 8000055c: 00e00113 li sp,14 - 80000560: 800000b7 lui ra,0x80000 - 80000564: 00000013 nop - 80000568: 4020df33 sra t5,ra,sp - 8000056c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000570: 00200293 li t0,2 - 80000574: fe5214e3 bne tp,t0,8000055c - 80000578: fffe0eb7 lui t4,0xfffe0 - 8000057c: 02300193 li gp,35 - 80000580: 11df1c63 bne t5,t4,80000698 - -0000000080000584 : - 80000584: 00000213 li tp,0 - 80000588: 01f00113 li sp,31 - 8000058c: 800000b7 lui ra,0x80000 - 80000590: 00000013 nop - 80000594: 00000013 nop - 80000598: 4020df33 sra t5,ra,sp - 8000059c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800005a0: 00200293 li t0,2 - 800005a4: fe5212e3 bne tp,t0,80000588 - 800005a8: fff00e93 li t4,-1 - 800005ac: 02400193 li gp,36 - 800005b0: 0fdf1463 bne t5,t4,80000698 - -00000000800005b4 : - 800005b4: 00000213 li tp,0 - 800005b8: 00700113 li sp,7 - 800005bc: 00000013 nop - 800005c0: 800000b7 lui ra,0x80000 - 800005c4: 4020df33 sra t5,ra,sp - 800005c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800005cc: 00200293 li t0,2 - 800005d0: fe5214e3 bne tp,t0,800005b8 - 800005d4: ff000eb7 lui t4,0xff000 - 800005d8: 02500193 li gp,37 - 800005dc: 0bdf1e63 bne t5,t4,80000698 - -00000000800005e0 : - 800005e0: 00000213 li tp,0 - 800005e4: 00e00113 li sp,14 - 800005e8: 00000013 nop - 800005ec: 800000b7 lui ra,0x80000 - 800005f0: 00000013 nop - 800005f4: 4020df33 sra t5,ra,sp - 800005f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800005fc: 00200293 li t0,2 - 80000600: fe5212e3 bne tp,t0,800005e4 - 80000604: fffe0eb7 lui t4,0xfffe0 - 80000608: 02600193 li gp,38 - 8000060c: 09df1663 bne t5,t4,80000698 - -0000000080000610 : - 80000610: 00000213 li tp,0 - 80000614: 01f00113 li sp,31 - 80000618: 00000013 nop - 8000061c: 00000013 nop - 80000620: 800000b7 lui ra,0x80000 - 80000624: 4020df33 sra t5,ra,sp - 80000628: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000062c: 00200293 li t0,2 - 80000630: fe5212e3 bne tp,t0,80000614 - 80000634: fff00e93 li t4,-1 - 80000638: 02700193 li gp,39 - 8000063c: 05df1e63 bne t5,t4,80000698 - -0000000080000640 : - 80000640: 00f00093 li ra,15 - 80000644: 40105133 sra sp,zero,ra - 80000648: 00000e93 li t4,0 - 8000064c: 02800193 li gp,40 - 80000650: 05d11463 bne sp,t4,80000698 - -0000000080000654 : - 80000654: 02000093 li ra,32 - 80000658: 4000d133 sra sp,ra,zero - 8000065c: 02000e93 li t4,32 - 80000660: 02900193 li gp,41 - 80000664: 03d11a63 bne sp,t4,80000698 - -0000000080000668 : - 80000668: 400050b3 sra ra,zero,zero - 8000066c: 00000e93 li t4,0 - 80000670: 02a00193 li gp,42 - 80000674: 03d09263 bne ra,t4,80000698 - -0000000080000678 : - 80000678: 40000093 li ra,1024 - 8000067c: 00001137 lui sp,0x1 - 80000680: 8001011b addiw sp,sp,-2048 - 80000684: 4020d033 sra zero,ra,sp - 80000688: 00000e93 li t4,0 - 8000068c: 02b00193 li gp,43 - 80000690: 01d01463 bne zero,t4,80000698 - 80000694: 00301c63 bne zero,gp,800006ac - -0000000080000698 : - 80000698: 0ff0000f fence - 8000069c: 00018063 beqz gp,8000069c - 800006a0: 00119193 slli gp,gp,0x1 - 800006a4: 0011e193 ori gp,gp,1 - 800006a8: 00000073 ecall - -00000000800006ac : - 800006ac: 0ff0000f fence - 800006b0: 00100193 li gp,1 - 800006b4: 00000073 ecall - 800006b8: c0001073 unimp - 800006bc: 0000 unimp - 800006be: 0000 unimp - 800006c0: 0000 unimp - 800006c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-sra.elf b/test/riscv/tests/rv64ui-p-sra.elf deleted file mode 100644 index f03501d4..00000000 Binary files a/test/riscv/tests/rv64ui-p-sra.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-srai.dump b/test/riscv/tests/rv64ui-p-srai.dump deleted file mode 100644 index e86b0510..00000000 --- a/test/riscv/tests/rv64ui-p-srai.dump +++ /dev/null @@ -1,333 +0,0 @@ - -rv64ui-p-srai: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: fff0009b addiw ra,zero,-1 - 80000100: 02709093 slli ra,ra,0x27 - 80000104: 4000df13 srai t5,ra,0x0 - 80000108: fff00e9b addiw t4,zero,-1 - 8000010c: 027e9e93 slli t4,t4,0x27 - 80000110: 00200193 li gp,2 - 80000114: 2bdf1463 bne t5,t4,800003bc - -0000000080000118 : - 80000118: 800000b7 lui ra,0x80000 - 8000011c: 4010df13 srai t5,ra,0x1 - 80000120: c0000eb7 lui t4,0xc0000 - 80000124: 00300193 li gp,3 - 80000128: 29df1a63 bne t5,t4,800003bc - -000000008000012c : - 8000012c: 800000b7 lui ra,0x80000 - 80000130: 4070df13 srai t5,ra,0x7 - 80000134: ff000eb7 lui t4,0xff000 - 80000138: 00400193 li gp,4 - 8000013c: 29df1063 bne t5,t4,800003bc - -0000000080000140 : - 80000140: 800000b7 lui ra,0x80000 - 80000144: 40e0df13 srai t5,ra,0xe - 80000148: fffe0eb7 lui t4,0xfffe0 - 8000014c: 00500193 li gp,5 - 80000150: 27df1663 bne t5,t4,800003bc - -0000000080000154 : - 80000154: 800000b7 lui ra,0x80000 - 80000158: 0010809b addiw ra,ra,1 - 8000015c: 41f0df13 srai t5,ra,0x1f - 80000160: fff00e93 li t4,-1 - 80000164: 00600193 li gp,6 - 80000168: 25df1a63 bne t5,t4,800003bc - -000000008000016c : - 8000016c: 800000b7 lui ra,0x80000 - 80000170: fff0809b addiw ra,ra,-1 - 80000174: 4000df13 srai t5,ra,0x0 - 80000178: 80000eb7 lui t4,0x80000 - 8000017c: fffe8e9b addiw t4,t4,-1 - 80000180: 00700193 li gp,7 - 80000184: 23df1c63 bne t5,t4,800003bc - -0000000080000188 : - 80000188: 800000b7 lui ra,0x80000 - 8000018c: fff0809b addiw ra,ra,-1 - 80000190: 4010df13 srai t5,ra,0x1 - 80000194: 40000eb7 lui t4,0x40000 - 80000198: fffe8e9b addiw t4,t4,-1 - 8000019c: 00800193 li gp,8 - 800001a0: 21df1e63 bne t5,t4,800003bc - -00000000800001a4 : - 800001a4: 800000b7 lui ra,0x80000 - 800001a8: fff0809b addiw ra,ra,-1 - 800001ac: 4070df13 srai t5,ra,0x7 - 800001b0: 01000eb7 lui t4,0x1000 - 800001b4: fffe8e9b addiw t4,t4,-1 - 800001b8: 00900193 li gp,9 - 800001bc: 21df1063 bne t5,t4,800003bc - -00000000800001c0 : - 800001c0: 800000b7 lui ra,0x80000 - 800001c4: fff0809b addiw ra,ra,-1 - 800001c8: 40e0df13 srai t5,ra,0xe - 800001cc: 00020eb7 lui t4,0x20 - 800001d0: fffe8e9b addiw t4,t4,-1 - 800001d4: 00a00193 li gp,10 - 800001d8: 1fdf1263 bne t5,t4,800003bc - -00000000800001dc : - 800001dc: 800000b7 lui ra,0x80000 - 800001e0: fff0809b addiw ra,ra,-1 - 800001e4: 41f0df13 srai t5,ra,0x1f - 800001e8: 00000e93 li t4,0 - 800001ec: 00b00193 li gp,11 - 800001f0: 1ddf1663 bne t5,t4,800003bc - -00000000800001f4 : - 800001f4: 818180b7 lui ra,0x81818 - 800001f8: 1810809b addiw ra,ra,385 - 800001fc: 4000df13 srai t5,ra,0x0 - 80000200: 81818eb7 lui t4,0x81818 - 80000204: 181e8e9b addiw t4,t4,385 - 80000208: 00c00193 li gp,12 - 8000020c: 1bdf1863 bne t5,t4,800003bc - -0000000080000210 : - 80000210: 818180b7 lui ra,0x81818 - 80000214: 1810809b addiw ra,ra,385 - 80000218: 4010df13 srai t5,ra,0x1 - 8000021c: c0c0ceb7 lui t4,0xc0c0c - 80000220: 0c0e8e9b addiw t4,t4,192 - 80000224: 00d00193 li gp,13 - 80000228: 19df1a63 bne t5,t4,800003bc - -000000008000022c : - 8000022c: 818180b7 lui ra,0x81818 - 80000230: 1810809b addiw ra,ra,385 - 80000234: 4070df13 srai t5,ra,0x7 - 80000238: ff030eb7 lui t4,0xff030 - 8000023c: 303e8e9b addiw t4,t4,771 - 80000240: 00e00193 li gp,14 - 80000244: 17df1c63 bne t5,t4,800003bc - -0000000080000248 : - 80000248: 818180b7 lui ra,0x81818 - 8000024c: 1810809b addiw ra,ra,385 - 80000250: 40e0df13 srai t5,ra,0xe - 80000254: fffe0eb7 lui t4,0xfffe0 - 80000258: 606e8e9b addiw t4,t4,1542 - 8000025c: 00f00193 li gp,15 - 80000260: 15df1e63 bne t5,t4,800003bc - -0000000080000264 : - 80000264: 818180b7 lui ra,0x81818 - 80000268: 1810809b addiw ra,ra,385 - 8000026c: 41f0df13 srai t5,ra,0x1f - 80000270: fff00e93 li t4,-1 - 80000274: 01000193 li gp,16 - 80000278: 15df1263 bne t5,t4,800003bc - -000000008000027c : - 8000027c: 800000b7 lui ra,0x80000 - 80000280: 4070d093 srai ra,ra,0x7 - 80000284: ff000eb7 lui t4,0xff000 - 80000288: 01100193 li gp,17 - 8000028c: 13d09863 bne ra,t4,800003bc - -0000000080000290 : - 80000290: 00000213 li tp,0 - 80000294: 800000b7 lui ra,0x80000 - 80000298: 4070df13 srai t5,ra,0x7 - 8000029c: 000f0313 mv t1,t5 - 800002a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002a4: 00200293 li t0,2 - 800002a8: fe5216e3 bne tp,t0,80000294 - 800002ac: ff000eb7 lui t4,0xff000 - 800002b0: 01200193 li gp,18 - 800002b4: 11d31463 bne t1,t4,800003bc - -00000000800002b8 : - 800002b8: 00000213 li tp,0 - 800002bc: 800000b7 lui ra,0x80000 - 800002c0: 40e0df13 srai t5,ra,0xe - 800002c4: 00000013 nop - 800002c8: 000f0313 mv t1,t5 - 800002cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002d0: 00200293 li t0,2 - 800002d4: fe5214e3 bne tp,t0,800002bc - 800002d8: fffe0eb7 lui t4,0xfffe0 - 800002dc: 01300193 li gp,19 - 800002e0: 0dd31e63 bne t1,t4,800003bc - -00000000800002e4 : - 800002e4: 00000213 li tp,0 - 800002e8: 800000b7 lui ra,0x80000 - 800002ec: 0010809b addiw ra,ra,1 - 800002f0: 41f0df13 srai t5,ra,0x1f - 800002f4: 00000013 nop - 800002f8: 00000013 nop - 800002fc: 000f0313 mv t1,t5 - 80000300: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000304: 00200293 li t0,2 - 80000308: fe5210e3 bne tp,t0,800002e8 - 8000030c: fff00e93 li t4,-1 - 80000310: 01400193 li gp,20 - 80000314: 0bd31463 bne t1,t4,800003bc - -0000000080000318 : - 80000318: 00000213 li tp,0 - 8000031c: 800000b7 lui ra,0x80000 - 80000320: 4070df13 srai t5,ra,0x7 - 80000324: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000328: 00200293 li t0,2 - 8000032c: fe5218e3 bne tp,t0,8000031c - 80000330: ff000eb7 lui t4,0xff000 - 80000334: 01500193 li gp,21 - 80000338: 09df1263 bne t5,t4,800003bc - -000000008000033c : - 8000033c: 00000213 li tp,0 - 80000340: 800000b7 lui ra,0x80000 - 80000344: 00000013 nop - 80000348: 40e0df13 srai t5,ra,0xe - 8000034c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000350: 00200293 li t0,2 - 80000354: fe5216e3 bne tp,t0,80000340 - 80000358: fffe0eb7 lui t4,0xfffe0 - 8000035c: 01600193 li gp,22 - 80000360: 05df1e63 bne t5,t4,800003bc - -0000000080000364 : - 80000364: 00000213 li tp,0 - 80000368: 800000b7 lui ra,0x80000 - 8000036c: 0010809b addiw ra,ra,1 - 80000370: 00000013 nop - 80000374: 00000013 nop - 80000378: 41f0df13 srai t5,ra,0x1f - 8000037c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000380: 00200293 li t0,2 - 80000384: fe5212e3 bne tp,t0,80000368 - 80000388: fff00e93 li t4,-1 - 8000038c: 01700193 li gp,23 - 80000390: 03df1663 bne t5,t4,800003bc - -0000000080000394 : - 80000394: 40405093 srai ra,zero,0x4 - 80000398: 00000e93 li t4,0 - 8000039c: 01800193 li gp,24 - 800003a0: 01d09e63 bne ra,t4,800003bc - -00000000800003a4 : - 800003a4: 02100093 li ra,33 - 800003a8: 40a0d013 srai zero,ra,0xa - 800003ac: 00000e93 li t4,0 - 800003b0: 01900193 li gp,25 - 800003b4: 01d01463 bne zero,t4,800003bc - 800003b8: 00301c63 bne zero,gp,800003d0 - -00000000800003bc : - 800003bc: 0ff0000f fence - 800003c0: 00018063 beqz gp,800003c0 - 800003c4: 00119193 slli gp,gp,0x1 - 800003c8: 0011e193 ori gp,gp,1 - 800003cc: 00000073 ecall - -00000000800003d0 : - 800003d0: 0ff0000f fence - 800003d4: 00100193 li gp,1 - 800003d8: 00000073 ecall - 800003dc: c0001073 unimp - 800003e0: 0000 unimp - 800003e2: 0000 unimp - 800003e4: 0000 unimp - 800003e6: 0000 unimp - 800003e8: 0000 unimp - 800003ea: 0000 unimp - 800003ec: 0000 unimp - 800003ee: 0000 unimp - 800003f0: 0000 unimp - 800003f2: 0000 unimp - 800003f4: 0000 unimp - 800003f6: 0000 unimp - 800003f8: 0000 unimp - 800003fa: 0000 unimp - 800003fc: 0000 unimp - 800003fe: 0000 unimp - 80000400: 0000 unimp - 80000402: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-srai.elf b/test/riscv/tests/rv64ui-p-srai.elf deleted file mode 100644 index c670ee92..00000000 Binary files a/test/riscv/tests/rv64ui-p-srai.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-sraiw.dump b/test/riscv/tests/rv64ui-p-sraiw.dump deleted file mode 100644 index c45179f8..00000000 --- a/test/riscv/tests/rv64ui-p-sraiw.dump +++ /dev/null @@ -1,359 +0,0 @@ - -rv64ui-p-sraiw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 800000b7 lui ra,0x80000 - 80000100: 4000df1b sraiw t5,ra,0x0 - 80000104: 80000eb7 lui t4,0x80000 - 80000108: 00200193 li gp,2 - 8000010c: 2ddf1c63 bne t5,t4,800003e4 - -0000000080000110 : - 80000110: 800000b7 lui ra,0x80000 - 80000114: 4010df1b sraiw t5,ra,0x1 - 80000118: c0000eb7 lui t4,0xc0000 - 8000011c: 00300193 li gp,3 - 80000120: 2ddf1263 bne t5,t4,800003e4 - -0000000080000124 : - 80000124: 800000b7 lui ra,0x80000 - 80000128: 4070df1b sraiw t5,ra,0x7 - 8000012c: ff000eb7 lui t4,0xff000 - 80000130: 00400193 li gp,4 - 80000134: 2bdf1863 bne t5,t4,800003e4 - -0000000080000138 : - 80000138: 800000b7 lui ra,0x80000 - 8000013c: 40e0df1b sraiw t5,ra,0xe - 80000140: fffe0eb7 lui t4,0xfffe0 - 80000144: 00500193 li gp,5 - 80000148: 29df1e63 bne t5,t4,800003e4 - -000000008000014c : - 8000014c: 800000b7 lui ra,0x80000 - 80000150: 0010809b addiw ra,ra,1 - 80000154: 41f0df1b sraiw t5,ra,0x1f - 80000158: fff00e93 li t4,-1 - 8000015c: 00600193 li gp,6 - 80000160: 29df1263 bne t5,t4,800003e4 - -0000000080000164 : - 80000164: 800000b7 lui ra,0x80000 - 80000168: fff0809b addiw ra,ra,-1 - 8000016c: 4000df1b sraiw t5,ra,0x0 - 80000170: 80000eb7 lui t4,0x80000 - 80000174: fffe8e9b addiw t4,t4,-1 - 80000178: 00700193 li gp,7 - 8000017c: 27df1463 bne t5,t4,800003e4 - -0000000080000180 : - 80000180: 800000b7 lui ra,0x80000 - 80000184: fff0809b addiw ra,ra,-1 - 80000188: 4010df1b sraiw t5,ra,0x1 - 8000018c: 40000eb7 lui t4,0x40000 - 80000190: fffe8e9b addiw t4,t4,-1 - 80000194: 00800193 li gp,8 - 80000198: 25df1663 bne t5,t4,800003e4 - -000000008000019c : - 8000019c: 800000b7 lui ra,0x80000 - 800001a0: fff0809b addiw ra,ra,-1 - 800001a4: 4070df1b sraiw t5,ra,0x7 - 800001a8: 01000eb7 lui t4,0x1000 - 800001ac: fffe8e9b addiw t4,t4,-1 - 800001b0: 00900193 li gp,9 - 800001b4: 23df1863 bne t5,t4,800003e4 - -00000000800001b8 : - 800001b8: 800000b7 lui ra,0x80000 - 800001bc: fff0809b addiw ra,ra,-1 - 800001c0: 40e0df1b sraiw t5,ra,0xe - 800001c4: 00020eb7 lui t4,0x20 - 800001c8: fffe8e9b addiw t4,t4,-1 - 800001cc: 00a00193 li gp,10 - 800001d0: 21df1a63 bne t5,t4,800003e4 - -00000000800001d4 : - 800001d4: 800000b7 lui ra,0x80000 - 800001d8: fff0809b addiw ra,ra,-1 - 800001dc: 41f0df1b sraiw t5,ra,0x1f - 800001e0: 00000e93 li t4,0 - 800001e4: 00b00193 li gp,11 - 800001e8: 1fdf1e63 bne t5,t4,800003e4 - -00000000800001ec : - 800001ec: 818180b7 lui ra,0x81818 - 800001f0: 1810809b addiw ra,ra,385 - 800001f4: 4000df1b sraiw t5,ra,0x0 - 800001f8: 81818eb7 lui t4,0x81818 - 800001fc: 181e8e9b addiw t4,t4,385 - 80000200: 00c00193 li gp,12 - 80000204: 1fdf1063 bne t5,t4,800003e4 - -0000000080000208 : - 80000208: 818180b7 lui ra,0x81818 - 8000020c: 1810809b addiw ra,ra,385 - 80000210: 4010df1b sraiw t5,ra,0x1 - 80000214: c0c0ceb7 lui t4,0xc0c0c - 80000218: 0c0e8e9b addiw t4,t4,192 - 8000021c: 00d00193 li gp,13 - 80000220: 1ddf1263 bne t5,t4,800003e4 - -0000000080000224 : - 80000224: 818180b7 lui ra,0x81818 - 80000228: 1810809b addiw ra,ra,385 - 8000022c: 4070df1b sraiw t5,ra,0x7 - 80000230: ff030eb7 lui t4,0xff030 - 80000234: 303e8e9b addiw t4,t4,771 - 80000238: 00e00193 li gp,14 - 8000023c: 1bdf1463 bne t5,t4,800003e4 - -0000000080000240 : - 80000240: 818180b7 lui ra,0x81818 - 80000244: 1810809b addiw ra,ra,385 - 80000248: 40e0df1b sraiw t5,ra,0xe - 8000024c: fffe0eb7 lui t4,0xfffe0 - 80000250: 606e8e9b addiw t4,t4,1542 - 80000254: 00f00193 li gp,15 - 80000258: 19df1663 bne t5,t4,800003e4 - -000000008000025c : - 8000025c: 818180b7 lui ra,0x81818 - 80000260: 1810809b addiw ra,ra,385 - 80000264: 41f0df1b sraiw t5,ra,0x1f - 80000268: fff00e93 li t4,-1 - 8000026c: 01000193 li gp,16 - 80000270: 17df1a63 bne t5,t4,800003e4 - -0000000080000274 : - 80000274: 800000b7 lui ra,0x80000 - 80000278: 4070d09b sraiw ra,ra,0x7 - 8000027c: ff000eb7 lui t4,0xff000 - 80000280: 01100193 li gp,17 - 80000284: 17d09063 bne ra,t4,800003e4 - -0000000080000288 : - 80000288: 00000213 li tp,0 - 8000028c: 800000b7 lui ra,0x80000 - 80000290: 4070df1b sraiw t5,ra,0x7 - 80000294: 000f0313 mv t1,t5 - 80000298: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000029c: 00200293 li t0,2 - 800002a0: fe5216e3 bne tp,t0,8000028c - 800002a4: ff000eb7 lui t4,0xff000 - 800002a8: 01200193 li gp,18 - 800002ac: 13d31c63 bne t1,t4,800003e4 - -00000000800002b0 : - 800002b0: 00000213 li tp,0 - 800002b4: 800000b7 lui ra,0x80000 - 800002b8: 40e0df1b sraiw t5,ra,0xe - 800002bc: 00000013 nop - 800002c0: 000f0313 mv t1,t5 - 800002c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002c8: 00200293 li t0,2 - 800002cc: fe5214e3 bne tp,t0,800002b4 - 800002d0: fffe0eb7 lui t4,0xfffe0 - 800002d4: 01300193 li gp,19 - 800002d8: 11d31663 bne t1,t4,800003e4 - -00000000800002dc : - 800002dc: 00000213 li tp,0 - 800002e0: 800000b7 lui ra,0x80000 - 800002e4: 0010809b addiw ra,ra,1 - 800002e8: 41f0df1b sraiw t5,ra,0x1f - 800002ec: 00000013 nop - 800002f0: 00000013 nop - 800002f4: 000f0313 mv t1,t5 - 800002f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002fc: 00200293 li t0,2 - 80000300: fe5210e3 bne tp,t0,800002e0 - 80000304: fff00e93 li t4,-1 - 80000308: 01400193 li gp,20 - 8000030c: 0dd31c63 bne t1,t4,800003e4 - -0000000080000310 : - 80000310: 00000213 li tp,0 - 80000314: 800000b7 lui ra,0x80000 - 80000318: 4070df1b sraiw t5,ra,0x7 - 8000031c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000320: 00200293 li t0,2 - 80000324: fe5218e3 bne tp,t0,80000314 - 80000328: ff000eb7 lui t4,0xff000 - 8000032c: 01500193 li gp,21 - 80000330: 0bdf1a63 bne t5,t4,800003e4 - -0000000080000334 : - 80000334: 00000213 li tp,0 - 80000338: 800000b7 lui ra,0x80000 - 8000033c: 00000013 nop - 80000340: 40e0df1b sraiw t5,ra,0xe - 80000344: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000348: 00200293 li t0,2 - 8000034c: fe5216e3 bne tp,t0,80000338 - 80000350: fffe0eb7 lui t4,0xfffe0 - 80000354: 01600193 li gp,22 - 80000358: 09df1663 bne t5,t4,800003e4 - -000000008000035c : - 8000035c: 00000213 li tp,0 - 80000360: 800000b7 lui ra,0x80000 - 80000364: 0010809b addiw ra,ra,1 - 80000368: 00000013 nop - 8000036c: 00000013 nop - 80000370: 41f0df1b sraiw t5,ra,0x1f - 80000374: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000378: 00200293 li t0,2 - 8000037c: fe5212e3 bne tp,t0,80000360 - 80000380: fff00e93 li t4,-1 - 80000384: 01700193 li gp,23 - 80000388: 05df1e63 bne t5,t4,800003e4 - -000000008000038c : - 8000038c: 41f0509b sraiw ra,zero,0x1f - 80000390: 00000e93 li t4,0 - 80000394: 01800193 li gp,24 - 80000398: 05d09663 bne ra,t4,800003e4 - -000000008000039c : - 8000039c: 01f00093 li ra,31 - 800003a0: 41c0d01b sraiw zero,ra,0x1c - 800003a4: 00000e93 li t4,0 - 800003a8: 01900193 li gp,25 - 800003ac: 03d01c63 bne zero,t4,800003e4 - -00000000800003b0 : - 800003b0: 0070009b addiw ra,zero,7 - 800003b4: 03509093 slli ra,ra,0x35 - 800003b8: 41c0df1b sraiw t5,ra,0x1c - 800003bc: 00000e93 li t4,0 - 800003c0: 01a00193 li gp,26 - 800003c4: 03df1063 bne t5,t4,800003e4 - -00000000800003c8 : - 800003c8: 00f0009b addiw ra,zero,15 - 800003cc: 01c09093 slli ra,ra,0x1c - 800003d0: 4040df1b sraiw t5,ra,0x4 - 800003d4: ff000eb7 lui t4,0xff000 - 800003d8: 01b00193 li gp,27 - 800003dc: 01df1463 bne t5,t4,800003e4 - 800003e0: 00301c63 bne zero,gp,800003f8 - -00000000800003e4 : - 800003e4: 0ff0000f fence - 800003e8: 00018063 beqz gp,800003e8 - 800003ec: 00119193 slli gp,gp,0x1 - 800003f0: 0011e193 ori gp,gp,1 - 800003f4: 00000073 ecall - -00000000800003f8 : - 800003f8: 0ff0000f fence - 800003fc: 00100193 li gp,1 - 80000400: 00000073 ecall - 80000404: c0001073 unimp - 80000408: 0000 unimp - 8000040a: 0000 unimp - 8000040c: 0000 unimp - 8000040e: 0000 unimp - 80000410: 0000 unimp - 80000412: 0000 unimp - 80000414: 0000 unimp - 80000416: 0000 unimp - 80000418: 0000 unimp - 8000041a: 0000 unimp - 8000041c: 0000 unimp - 8000041e: 0000 unimp - 80000420: 0000 unimp - 80000422: 0000 unimp - 80000424: 0000 unimp - 80000426: 0000 unimp - 80000428: 0000 unimp - 8000042a: 0000 unimp - 8000042c: 0000 unimp - 8000042e: 0000 unimp - 80000430: 0000 unimp - 80000432: 0000 unimp - 80000434: 0000 unimp - 80000436: 0000 unimp - 80000438: 0000 unimp - 8000043a: 0000 unimp - 8000043c: 0000 unimp - 8000043e: 0000 unimp - 80000440: 0000 unimp - 80000442: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-sraiw.elf b/test/riscv/tests/rv64ui-p-sraiw.elf deleted file mode 100644 index e4cab284..00000000 Binary files a/test/riscv/tests/rv64ui-p-sraiw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-sraw.dump b/test/riscv/tests/rv64ui-p-sraw.dump deleted file mode 100644 index dc65ff46..00000000 --- a/test/riscv/tests/rv64ui-p-sraw.dump +++ /dev/null @@ -1,538 +0,0 @@ - -rv64ui-p-sraw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 800000b7 lui ra,0x80000 - 80000100: 00000113 li sp,0 - 80000104: 4020df3b sraw t5,ra,sp - 80000108: 80000eb7 lui t4,0x80000 - 8000010c: 00200193 li gp,2 - 80000110: 59df1463 bne t5,t4,80000698 - -0000000080000114 : - 80000114: 800000b7 lui ra,0x80000 - 80000118: 00100113 li sp,1 - 8000011c: 4020df3b sraw t5,ra,sp - 80000120: c0000eb7 lui t4,0xc0000 - 80000124: 00300193 li gp,3 - 80000128: 57df1863 bne t5,t4,80000698 - -000000008000012c : - 8000012c: 800000b7 lui ra,0x80000 - 80000130: 00700113 li sp,7 - 80000134: 4020df3b sraw t5,ra,sp - 80000138: ff000eb7 lui t4,0xff000 - 8000013c: 00400193 li gp,4 - 80000140: 55df1c63 bne t5,t4,80000698 - -0000000080000144 : - 80000144: 800000b7 lui ra,0x80000 - 80000148: 00e00113 li sp,14 - 8000014c: 4020df3b sraw t5,ra,sp - 80000150: fffe0eb7 lui t4,0xfffe0 - 80000154: 00500193 li gp,5 - 80000158: 55df1063 bne t5,t4,80000698 - -000000008000015c : - 8000015c: 800000b7 lui ra,0x80000 - 80000160: 0010809b addiw ra,ra,1 - 80000164: 01f00113 li sp,31 - 80000168: 4020df3b sraw t5,ra,sp - 8000016c: fff00e93 li t4,-1 - 80000170: 00600193 li gp,6 - 80000174: 53df1263 bne t5,t4,80000698 - -0000000080000178 : - 80000178: 800000b7 lui ra,0x80000 - 8000017c: fff0809b addiw ra,ra,-1 - 80000180: 00000113 li sp,0 - 80000184: 4020df3b sraw t5,ra,sp - 80000188: 80000eb7 lui t4,0x80000 - 8000018c: fffe8e9b addiw t4,t4,-1 - 80000190: 00700193 li gp,7 - 80000194: 51df1263 bne t5,t4,80000698 - -0000000080000198 : - 80000198: 800000b7 lui ra,0x80000 - 8000019c: fff0809b addiw ra,ra,-1 - 800001a0: 00100113 li sp,1 - 800001a4: 4020df3b sraw t5,ra,sp - 800001a8: 40000eb7 lui t4,0x40000 - 800001ac: fffe8e9b addiw t4,t4,-1 - 800001b0: 00800193 li gp,8 - 800001b4: 4fdf1263 bne t5,t4,80000698 - -00000000800001b8 : - 800001b8: 800000b7 lui ra,0x80000 - 800001bc: fff0809b addiw ra,ra,-1 - 800001c0: 00700113 li sp,7 - 800001c4: 4020df3b sraw t5,ra,sp - 800001c8: 01000eb7 lui t4,0x1000 - 800001cc: fffe8e9b addiw t4,t4,-1 - 800001d0: 00900193 li gp,9 - 800001d4: 4ddf1263 bne t5,t4,80000698 - -00000000800001d8 : - 800001d8: 800000b7 lui ra,0x80000 - 800001dc: fff0809b addiw ra,ra,-1 - 800001e0: 00e00113 li sp,14 - 800001e4: 4020df3b sraw t5,ra,sp - 800001e8: 00020eb7 lui t4,0x20 - 800001ec: fffe8e9b addiw t4,t4,-1 - 800001f0: 00a00193 li gp,10 - 800001f4: 4bdf1263 bne t5,t4,80000698 - -00000000800001f8 : - 800001f8: 800000b7 lui ra,0x80000 - 800001fc: fff0809b addiw ra,ra,-1 - 80000200: 01f00113 li sp,31 - 80000204: 4020df3b sraw t5,ra,sp - 80000208: 00000e93 li t4,0 - 8000020c: 00b00193 li gp,11 - 80000210: 49df1463 bne t5,t4,80000698 - -0000000080000214 : - 80000214: 818180b7 lui ra,0x81818 - 80000218: 1810809b addiw ra,ra,385 - 8000021c: 00000113 li sp,0 - 80000220: 4020df3b sraw t5,ra,sp - 80000224: 81818eb7 lui t4,0x81818 - 80000228: 181e8e9b addiw t4,t4,385 - 8000022c: 00c00193 li gp,12 - 80000230: 47df1463 bne t5,t4,80000698 - -0000000080000234 : - 80000234: 818180b7 lui ra,0x81818 - 80000238: 1810809b addiw ra,ra,385 - 8000023c: 00100113 li sp,1 - 80000240: 4020df3b sraw t5,ra,sp - 80000244: c0c0ceb7 lui t4,0xc0c0c - 80000248: 0c0e8e9b addiw t4,t4,192 - 8000024c: 00d00193 li gp,13 - 80000250: 45df1463 bne t5,t4,80000698 - -0000000080000254 : - 80000254: 818180b7 lui ra,0x81818 - 80000258: 1810809b addiw ra,ra,385 - 8000025c: 00700113 li sp,7 - 80000260: 4020df3b sraw t5,ra,sp - 80000264: ff030eb7 lui t4,0xff030 - 80000268: 303e8e9b addiw t4,t4,771 - 8000026c: 00e00193 li gp,14 - 80000270: 43df1463 bne t5,t4,80000698 - -0000000080000274 : - 80000274: 818180b7 lui ra,0x81818 - 80000278: 1810809b addiw ra,ra,385 - 8000027c: 00e00113 li sp,14 - 80000280: 4020df3b sraw t5,ra,sp - 80000284: fffe0eb7 lui t4,0xfffe0 - 80000288: 606e8e9b addiw t4,t4,1542 - 8000028c: 00f00193 li gp,15 - 80000290: 41df1463 bne t5,t4,80000698 - -0000000080000294 : - 80000294: 818180b7 lui ra,0x81818 - 80000298: 1810809b addiw ra,ra,385 - 8000029c: 01f00113 li sp,31 - 800002a0: 4020df3b sraw t5,ra,sp - 800002a4: fff00e93 li t4,-1 - 800002a8: 01000193 li gp,16 - 800002ac: 3fdf1663 bne t5,t4,80000698 - -00000000800002b0 : - 800002b0: 818180b7 lui ra,0x81818 - 800002b4: 1810809b addiw ra,ra,385 - 800002b8: fe000113 li sp,-32 - 800002bc: 4020df3b sraw t5,ra,sp - 800002c0: 81818eb7 lui t4,0x81818 - 800002c4: 181e8e9b addiw t4,t4,385 - 800002c8: 01100193 li gp,17 - 800002cc: 3ddf1663 bne t5,t4,80000698 - -00000000800002d0 : - 800002d0: 818180b7 lui ra,0x81818 - 800002d4: 1810809b addiw ra,ra,385 - 800002d8: fe100113 li sp,-31 - 800002dc: 4020df3b sraw t5,ra,sp - 800002e0: c0c0ceb7 lui t4,0xc0c0c - 800002e4: 0c0e8e9b addiw t4,t4,192 - 800002e8: 01200193 li gp,18 - 800002ec: 3bdf1663 bne t5,t4,80000698 - -00000000800002f0 : - 800002f0: 818180b7 lui ra,0x81818 - 800002f4: 1810809b addiw ra,ra,385 - 800002f8: fe700113 li sp,-25 - 800002fc: 4020df3b sraw t5,ra,sp - 80000300: ff030eb7 lui t4,0xff030 - 80000304: 303e8e9b addiw t4,t4,771 - 80000308: 01300193 li gp,19 - 8000030c: 39df1663 bne t5,t4,80000698 - -0000000080000310 : - 80000310: 818180b7 lui ra,0x81818 - 80000314: 1810809b addiw ra,ra,385 - 80000318: fee00113 li sp,-18 - 8000031c: 4020df3b sraw t5,ra,sp - 80000320: fffe0eb7 lui t4,0xfffe0 - 80000324: 606e8e9b addiw t4,t4,1542 - 80000328: 01400193 li gp,20 - 8000032c: 37df1663 bne t5,t4,80000698 - -0000000080000330 : - 80000330: 818180b7 lui ra,0x81818 - 80000334: 1810809b addiw ra,ra,385 - 80000338: fff00113 li sp,-1 - 8000033c: 4020df3b sraw t5,ra,sp - 80000340: fff00e93 li t4,-1 - 80000344: 01500193 li gp,21 - 80000348: 35df1863 bne t5,t4,80000698 - -000000008000034c : - 8000034c: 800000b7 lui ra,0x80000 - 80000350: 00700113 li sp,7 - 80000354: 4020d0bb sraw ra,ra,sp - 80000358: ff000eb7 lui t4,0xff000 - 8000035c: 01600193 li gp,22 - 80000360: 33d09c63 bne ra,t4,80000698 - -0000000080000364 : - 80000364: 800000b7 lui ra,0x80000 - 80000368: 00e00113 li sp,14 - 8000036c: 4020d13b sraw sp,ra,sp - 80000370: fffe0eb7 lui t4,0xfffe0 - 80000374: 01700193 li gp,23 - 80000378: 33d11063 bne sp,t4,80000698 - -000000008000037c : - 8000037c: 00700093 li ra,7 - 80000380: 4010d0bb sraw ra,ra,ra - 80000384: 00000e93 li t4,0 - 80000388: 01800193 li gp,24 - 8000038c: 31d09663 bne ra,t4,80000698 - -0000000080000390 : - 80000390: 00000213 li tp,0 - 80000394: 800000b7 lui ra,0x80000 - 80000398: 00700113 li sp,7 - 8000039c: 4020df3b sraw t5,ra,sp - 800003a0: 000f0313 mv t1,t5 - 800003a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003a8: 00200293 li t0,2 - 800003ac: fe5214e3 bne tp,t0,80000394 - 800003b0: ff000eb7 lui t4,0xff000 - 800003b4: 01900193 li gp,25 - 800003b8: 2fd31063 bne t1,t4,80000698 - -00000000800003bc : - 800003bc: 00000213 li tp,0 - 800003c0: 800000b7 lui ra,0x80000 - 800003c4: 00e00113 li sp,14 - 800003c8: 4020df3b sraw t5,ra,sp - 800003cc: 00000013 nop - 800003d0: 000f0313 mv t1,t5 - 800003d4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003d8: 00200293 li t0,2 - 800003dc: fe5212e3 bne tp,t0,800003c0 - 800003e0: fffe0eb7 lui t4,0xfffe0 - 800003e4: 01a00193 li gp,26 - 800003e8: 2bd31863 bne t1,t4,80000698 - -00000000800003ec : - 800003ec: 00000213 li tp,0 - 800003f0: 800000b7 lui ra,0x80000 - 800003f4: 01f00113 li sp,31 - 800003f8: 4020df3b sraw t5,ra,sp - 800003fc: 00000013 nop - 80000400: 00000013 nop - 80000404: 000f0313 mv t1,t5 - 80000408: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000040c: 00200293 li t0,2 - 80000410: fe5210e3 bne tp,t0,800003f0 - 80000414: fff00e93 li t4,-1 - 80000418: 01b00193 li gp,27 - 8000041c: 27d31e63 bne t1,t4,80000698 - -0000000080000420 : - 80000420: 00000213 li tp,0 - 80000424: 800000b7 lui ra,0x80000 - 80000428: 00700113 li sp,7 - 8000042c: 4020df3b sraw t5,ra,sp - 80000430: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000434: 00200293 li t0,2 - 80000438: fe5216e3 bne tp,t0,80000424 - 8000043c: ff000eb7 lui t4,0xff000 - 80000440: 01c00193 li gp,28 - 80000444: 25df1a63 bne t5,t4,80000698 - -0000000080000448 : - 80000448: 00000213 li tp,0 - 8000044c: 800000b7 lui ra,0x80000 - 80000450: 00e00113 li sp,14 - 80000454: 00000013 nop - 80000458: 4020df3b sraw t5,ra,sp - 8000045c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000460: 00200293 li t0,2 - 80000464: fe5214e3 bne tp,t0,8000044c - 80000468: fffe0eb7 lui t4,0xfffe0 - 8000046c: 01d00193 li gp,29 - 80000470: 23df1463 bne t5,t4,80000698 - -0000000080000474 : - 80000474: 00000213 li tp,0 - 80000478: 800000b7 lui ra,0x80000 - 8000047c: 01f00113 li sp,31 - 80000480: 00000013 nop - 80000484: 00000013 nop - 80000488: 4020df3b sraw t5,ra,sp - 8000048c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000490: 00200293 li t0,2 - 80000494: fe5212e3 bne tp,t0,80000478 - 80000498: fff00e93 li t4,-1 - 8000049c: 01e00193 li gp,30 - 800004a0: 1fdf1c63 bne t5,t4,80000698 - -00000000800004a4 : - 800004a4: 00000213 li tp,0 - 800004a8: 800000b7 lui ra,0x80000 - 800004ac: 00000013 nop - 800004b0: 00700113 li sp,7 - 800004b4: 4020df3b sraw t5,ra,sp - 800004b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004bc: 00200293 li t0,2 - 800004c0: fe5214e3 bne tp,t0,800004a8 - 800004c4: ff000eb7 lui t4,0xff000 - 800004c8: 01f00193 li gp,31 - 800004cc: 1ddf1663 bne t5,t4,80000698 - -00000000800004d0 : - 800004d0: 00000213 li tp,0 - 800004d4: 800000b7 lui ra,0x80000 - 800004d8: 00000013 nop - 800004dc: 00e00113 li sp,14 - 800004e0: 00000013 nop - 800004e4: 4020df3b sraw t5,ra,sp - 800004e8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004ec: 00200293 li t0,2 - 800004f0: fe5212e3 bne tp,t0,800004d4 - 800004f4: fffe0eb7 lui t4,0xfffe0 - 800004f8: 02000193 li gp,32 - 800004fc: 19df1e63 bne t5,t4,80000698 - -0000000080000500 : - 80000500: 00000213 li tp,0 - 80000504: 800000b7 lui ra,0x80000 - 80000508: 00000013 nop - 8000050c: 00000013 nop - 80000510: 01f00113 li sp,31 - 80000514: 4020df3b sraw t5,ra,sp - 80000518: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000051c: 00200293 li t0,2 - 80000520: fe5212e3 bne tp,t0,80000504 - 80000524: fff00e93 li t4,-1 - 80000528: 02100193 li gp,33 - 8000052c: 17df1663 bne t5,t4,80000698 - -0000000080000530 : - 80000530: 00000213 li tp,0 - 80000534: 00700113 li sp,7 - 80000538: 800000b7 lui ra,0x80000 - 8000053c: 4020df3b sraw t5,ra,sp - 80000540: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000544: 00200293 li t0,2 - 80000548: fe5216e3 bne tp,t0,80000534 - 8000054c: ff000eb7 lui t4,0xff000 - 80000550: 02200193 li gp,34 - 80000554: 15df1263 bne t5,t4,80000698 - -0000000080000558 : - 80000558: 00000213 li tp,0 - 8000055c: 00e00113 li sp,14 - 80000560: 800000b7 lui ra,0x80000 - 80000564: 00000013 nop - 80000568: 4020df3b sraw t5,ra,sp - 8000056c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000570: 00200293 li t0,2 - 80000574: fe5214e3 bne tp,t0,8000055c - 80000578: fffe0eb7 lui t4,0xfffe0 - 8000057c: 02300193 li gp,35 - 80000580: 11df1c63 bne t5,t4,80000698 - -0000000080000584 : - 80000584: 00000213 li tp,0 - 80000588: 01f00113 li sp,31 - 8000058c: 800000b7 lui ra,0x80000 - 80000590: 00000013 nop - 80000594: 00000013 nop - 80000598: 4020df3b sraw t5,ra,sp - 8000059c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800005a0: 00200293 li t0,2 - 800005a4: fe5212e3 bne tp,t0,80000588 - 800005a8: fff00e93 li t4,-1 - 800005ac: 02400193 li gp,36 - 800005b0: 0fdf1463 bne t5,t4,80000698 - -00000000800005b4 : - 800005b4: 00000213 li tp,0 - 800005b8: 00700113 li sp,7 - 800005bc: 00000013 nop - 800005c0: 800000b7 lui ra,0x80000 - 800005c4: 4020df3b sraw t5,ra,sp - 800005c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800005cc: 00200293 li t0,2 - 800005d0: fe5214e3 bne tp,t0,800005b8 - 800005d4: ff000eb7 lui t4,0xff000 - 800005d8: 02500193 li gp,37 - 800005dc: 0bdf1e63 bne t5,t4,80000698 - -00000000800005e0 : - 800005e0: 00000213 li tp,0 - 800005e4: 00e00113 li sp,14 - 800005e8: 00000013 nop - 800005ec: 800000b7 lui ra,0x80000 - 800005f0: 00000013 nop - 800005f4: 4020df3b sraw t5,ra,sp - 800005f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800005fc: 00200293 li t0,2 - 80000600: fe5212e3 bne tp,t0,800005e4 - 80000604: fffe0eb7 lui t4,0xfffe0 - 80000608: 02600193 li gp,38 - 8000060c: 09df1663 bne t5,t4,80000698 - -0000000080000610 : - 80000610: 00000213 li tp,0 - 80000614: 01f00113 li sp,31 - 80000618: 00000013 nop - 8000061c: 00000013 nop - 80000620: 800000b7 lui ra,0x80000 - 80000624: 4020df3b sraw t5,ra,sp - 80000628: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000062c: 00200293 li t0,2 - 80000630: fe5212e3 bne tp,t0,80000614 - 80000634: fff00e93 li t4,-1 - 80000638: 02700193 li gp,39 - 8000063c: 05df1e63 bne t5,t4,80000698 - -0000000080000640 : - 80000640: 00f00093 li ra,15 - 80000644: 4010513b sraw sp,zero,ra - 80000648: 00000e93 li t4,0 - 8000064c: 02800193 li gp,40 - 80000650: 05d11463 bne sp,t4,80000698 - -0000000080000654 : - 80000654: 02000093 li ra,32 - 80000658: 4000d13b sraw sp,ra,zero - 8000065c: 02000e93 li t4,32 - 80000660: 02900193 li gp,41 - 80000664: 03d11a63 bne sp,t4,80000698 - -0000000080000668 : - 80000668: 400050bb sraw ra,zero,zero - 8000066c: 00000e93 li t4,0 - 80000670: 02a00193 li gp,42 - 80000674: 03d09263 bne ra,t4,80000698 - -0000000080000678 : - 80000678: 40000093 li ra,1024 - 8000067c: 00001137 lui sp,0x1 - 80000680: 8001011b addiw sp,sp,-2048 - 80000684: 4020d03b sraw zero,ra,sp - 80000688: 00000e93 li t4,0 - 8000068c: 02b00193 li gp,43 - 80000690: 01d01463 bne zero,t4,80000698 - 80000694: 00301c63 bne zero,gp,800006ac - -0000000080000698 : - 80000698: 0ff0000f fence - 8000069c: 00018063 beqz gp,8000069c - 800006a0: 00119193 slli gp,gp,0x1 - 800006a4: 0011e193 ori gp,gp,1 - 800006a8: 00000073 ecall - -00000000800006ac : - 800006ac: 0ff0000f fence - 800006b0: 00100193 li gp,1 - 800006b4: 00000073 ecall - 800006b8: c0001073 unimp - 800006bc: 0000 unimp - 800006be: 0000 unimp - 800006c0: 0000 unimp - 800006c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-sraw.elf b/test/riscv/tests/rv64ui-p-sraw.elf deleted file mode 100644 index 40d2f2c4..00000000 Binary files a/test/riscv/tests/rv64ui-p-sraw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-srl.dump b/test/riscv/tests/rv64ui-p-srl.dump deleted file mode 100644 index 314069ff..00000000 --- a/test/riscv/tests/rv64ui-p-srl.dump +++ /dev/null @@ -1,575 +0,0 @@ - -rv64ui-p-srl: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 800000b7 lui ra,0x80000 - 80000100: 00000113 li sp,0 - 80000104: 0020df33 srl t5,ra,sp - 80000108: 80000eb7 lui t4,0x80000 - 8000010c: 00200193 li gp,2 - 80000110: 5fdf1a63 bne t5,t4,80000704 - -0000000080000114 : - 80000114: 800000b7 lui ra,0x80000 - 80000118: 00100113 li sp,1 - 8000011c: 0020df33 srl t5,ra,sp - 80000120: 00100e9b addiw t4,zero,1 - 80000124: 021e9e93 slli t4,t4,0x21 - 80000128: fffe8e93 addi t4,t4,-1 # ffffffff7fffffff <_end+0xfffffffeffffdfff> - 8000012c: 01ee9e93 slli t4,t4,0x1e - 80000130: 00300193 li gp,3 - 80000134: 5ddf1863 bne t5,t4,80000704 - -0000000080000138 : - 80000138: 800000b7 lui ra,0x80000 - 8000013c: 00700113 li sp,7 - 80000140: 0020df33 srl t5,ra,sp - 80000144: 00100e9b addiw t4,zero,1 - 80000148: 021e9e93 slli t4,t4,0x21 - 8000014c: fffe8e93 addi t4,t4,-1 - 80000150: 018e9e93 slli t4,t4,0x18 - 80000154: 00400193 li gp,4 - 80000158: 5bdf1663 bne t5,t4,80000704 - -000000008000015c : - 8000015c: 800000b7 lui ra,0x80000 - 80000160: 00e00113 li sp,14 - 80000164: 0020df33 srl t5,ra,sp - 80000168: 00100e9b addiw t4,zero,1 - 8000016c: 021e9e93 slli t4,t4,0x21 - 80000170: fffe8e93 addi t4,t4,-1 - 80000174: 011e9e93 slli t4,t4,0x11 - 80000178: 00500193 li gp,5 - 8000017c: 59df1463 bne t5,t4,80000704 - -0000000080000180 : - 80000180: 800000b7 lui ra,0x80000 - 80000184: 0010809b addiw ra,ra,1 - 80000188: 01f00113 li sp,31 - 8000018c: 0020df33 srl t5,ra,sp - 80000190: 00100e9b addiw t4,zero,1 - 80000194: 021e9e93 slli t4,t4,0x21 - 80000198: fffe8e93 addi t4,t4,-1 - 8000019c: 00600193 li gp,6 - 800001a0: 57df1263 bne t5,t4,80000704 - -00000000800001a4 : - 800001a4: fff00093 li ra,-1 - 800001a8: 00000113 li sp,0 - 800001ac: 0020df33 srl t5,ra,sp - 800001b0: fff00e93 li t4,-1 - 800001b4: 00700193 li gp,7 - 800001b8: 55df1663 bne t5,t4,80000704 - -00000000800001bc : - 800001bc: fff00093 li ra,-1 - 800001c0: 00100113 li sp,1 - 800001c4: 0020df33 srl t5,ra,sp - 800001c8: fff00e9b addiw t4,zero,-1 - 800001cc: 03fe9e93 slli t4,t4,0x3f - 800001d0: fffe8e93 addi t4,t4,-1 - 800001d4: 00800193 li gp,8 - 800001d8: 53df1663 bne t5,t4,80000704 - -00000000800001dc : - 800001dc: fff00093 li ra,-1 - 800001e0: 00700113 li sp,7 - 800001e4: 0020df33 srl t5,ra,sp - 800001e8: 00100e9b addiw t4,zero,1 - 800001ec: 039e9e93 slli t4,t4,0x39 - 800001f0: fffe8e93 addi t4,t4,-1 - 800001f4: 00900193 li gp,9 - 800001f8: 51df1663 bne t5,t4,80000704 - -00000000800001fc : - 800001fc: fff00093 li ra,-1 - 80000200: 00e00113 li sp,14 - 80000204: 0020df33 srl t5,ra,sp - 80000208: 00100e9b addiw t4,zero,1 - 8000020c: 032e9e93 slli t4,t4,0x32 - 80000210: fffe8e93 addi t4,t4,-1 - 80000214: 00a00193 li gp,10 - 80000218: 4fdf1663 bne t5,t4,80000704 - -000000008000021c : - 8000021c: fff00093 li ra,-1 - 80000220: 01f00113 li sp,31 - 80000224: 0020df33 srl t5,ra,sp - 80000228: 00100e9b addiw t4,zero,1 - 8000022c: 021e9e93 slli t4,t4,0x21 - 80000230: fffe8e93 addi t4,t4,-1 - 80000234: 00b00193 li gp,11 - 80000238: 4ddf1663 bne t5,t4,80000704 - -000000008000023c : - 8000023c: 212120b7 lui ra,0x21212 - 80000240: 1210809b addiw ra,ra,289 - 80000244: 00000113 li sp,0 - 80000248: 0020df33 srl t5,ra,sp - 8000024c: 21212eb7 lui t4,0x21212 - 80000250: 121e8e9b addiw t4,t4,289 - 80000254: 00c00193 li gp,12 - 80000258: 4bdf1663 bne t5,t4,80000704 - -000000008000025c : - 8000025c: 212120b7 lui ra,0x21212 - 80000260: 1210809b addiw ra,ra,289 - 80000264: 00100113 li sp,1 - 80000268: 0020df33 srl t5,ra,sp - 8000026c: 10909eb7 lui t4,0x10909 - 80000270: 090e8e9b addiw t4,t4,144 - 80000274: 00d00193 li gp,13 - 80000278: 49df1663 bne t5,t4,80000704 - -000000008000027c : - 8000027c: 212120b7 lui ra,0x21212 - 80000280: 1210809b addiw ra,ra,289 - 80000284: 00700113 li sp,7 - 80000288: 0020df33 srl t5,ra,sp - 8000028c: 00424eb7 lui t4,0x424 - 80000290: 242e8e9b addiw t4,t4,578 - 80000294: 00e00193 li gp,14 - 80000298: 47df1663 bne t5,t4,80000704 - -000000008000029c : - 8000029c: 212120b7 lui ra,0x21212 - 800002a0: 1210809b addiw ra,ra,289 - 800002a4: 00e00113 li sp,14 - 800002a8: 0020df33 srl t5,ra,sp - 800002ac: 00008eb7 lui t4,0x8 - 800002b0: 484e8e9b addiw t4,t4,1156 - 800002b4: 00f00193 li gp,15 - 800002b8: 45df1663 bne t5,t4,80000704 - -00000000800002bc : - 800002bc: 212120b7 lui ra,0x21212 - 800002c0: 1210809b addiw ra,ra,289 - 800002c4: 01f00113 li sp,31 - 800002c8: 0020df33 srl t5,ra,sp - 800002cc: 00000e93 li t4,0 - 800002d0: 01000193 li gp,16 - 800002d4: 43df1863 bne t5,t4,80000704 - -00000000800002d8 : - 800002d8: 212120b7 lui ra,0x21212 - 800002dc: 1210809b addiw ra,ra,289 - 800002e0: fc000113 li sp,-64 - 800002e4: 0020df33 srl t5,ra,sp - 800002e8: 21212eb7 lui t4,0x21212 - 800002ec: 121e8e9b addiw t4,t4,289 - 800002f0: 01100193 li gp,17 - 800002f4: 41df1863 bne t5,t4,80000704 - -00000000800002f8 : - 800002f8: 212120b7 lui ra,0x21212 - 800002fc: 1210809b addiw ra,ra,289 - 80000300: fc100113 li sp,-63 - 80000304: 0020df33 srl t5,ra,sp - 80000308: 10909eb7 lui t4,0x10909 - 8000030c: 090e8e9b addiw t4,t4,144 - 80000310: 01200193 li gp,18 - 80000314: 3fdf1863 bne t5,t4,80000704 - -0000000080000318 : - 80000318: 212120b7 lui ra,0x21212 - 8000031c: 1210809b addiw ra,ra,289 - 80000320: fc700113 li sp,-57 - 80000324: 0020df33 srl t5,ra,sp - 80000328: 00424eb7 lui t4,0x424 - 8000032c: 242e8e9b addiw t4,t4,578 - 80000330: 01300193 li gp,19 - 80000334: 3ddf1863 bne t5,t4,80000704 - -0000000080000338 : - 80000338: 212120b7 lui ra,0x21212 - 8000033c: 1210809b addiw ra,ra,289 - 80000340: fce00113 li sp,-50 - 80000344: 0020df33 srl t5,ra,sp - 80000348: 00008eb7 lui t4,0x8 - 8000034c: 484e8e9b addiw t4,t4,1156 - 80000350: 01400193 li gp,20 - 80000354: 3bdf1863 bne t5,t4,80000704 - -0000000080000358 : - 80000358: 212120b7 lui ra,0x21212 - 8000035c: 1210809b addiw ra,ra,289 - 80000360: fff00113 li sp,-1 - 80000364: 0020df33 srl t5,ra,sp - 80000368: 00000e93 li t4,0 - 8000036c: 01500193 li gp,21 - 80000370: 39df1a63 bne t5,t4,80000704 - -0000000080000374 : - 80000374: 0010009b addiw ra,zero,1 - 80000378: 01f09093 slli ra,ra,0x1f - 8000037c: 00700113 li sp,7 - 80000380: 0020d0b3 srl ra,ra,sp - 80000384: 01000eb7 lui t4,0x1000 - 80000388: 01600193 li gp,22 - 8000038c: 37d09c63 bne ra,t4,80000704 - -0000000080000390 : - 80000390: 0010009b addiw ra,zero,1 - 80000394: 01f09093 slli ra,ra,0x1f - 80000398: 00e00113 li sp,14 - 8000039c: 0020d133 srl sp,ra,sp - 800003a0: 00020eb7 lui t4,0x20 - 800003a4: 01700193 li gp,23 - 800003a8: 35d11e63 bne sp,t4,80000704 - -00000000800003ac : - 800003ac: 00700093 li ra,7 - 800003b0: 0010d0b3 srl ra,ra,ra - 800003b4: 00000e93 li t4,0 - 800003b8: 01800193 li gp,24 - 800003bc: 35d09463 bne ra,t4,80000704 - -00000000800003c0 : - 800003c0: 00000213 li tp,0 - 800003c4: 0010009b addiw ra,zero,1 - 800003c8: 01f09093 slli ra,ra,0x1f - 800003cc: 00700113 li sp,7 - 800003d0: 0020df33 srl t5,ra,sp - 800003d4: 000f0313 mv t1,t5 - 800003d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003dc: 00200293 li t0,2 - 800003e0: fe5212e3 bne tp,t0,800003c4 - 800003e4: 01000eb7 lui t4,0x1000 - 800003e8: 01900193 li gp,25 - 800003ec: 31d31c63 bne t1,t4,80000704 - -00000000800003f0 : - 800003f0: 00000213 li tp,0 - 800003f4: 0010009b addiw ra,zero,1 - 800003f8: 01f09093 slli ra,ra,0x1f - 800003fc: 00e00113 li sp,14 - 80000400: 0020df33 srl t5,ra,sp - 80000404: 00000013 nop - 80000408: 000f0313 mv t1,t5 - 8000040c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000410: 00200293 li t0,2 - 80000414: fe5210e3 bne tp,t0,800003f4 - 80000418: 00020eb7 lui t4,0x20 - 8000041c: 01a00193 li gp,26 - 80000420: 2fd31263 bne t1,t4,80000704 - -0000000080000424 : - 80000424: 00000213 li tp,0 - 80000428: 0010009b addiw ra,zero,1 - 8000042c: 01f09093 slli ra,ra,0x1f - 80000430: 01f00113 li sp,31 - 80000434: 0020df33 srl t5,ra,sp - 80000438: 00000013 nop - 8000043c: 00000013 nop - 80000440: 000f0313 mv t1,t5 - 80000444: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000448: 00200293 li t0,2 - 8000044c: fc521ee3 bne tp,t0,80000428 - 80000450: 00100e93 li t4,1 - 80000454: 01b00193 li gp,27 - 80000458: 2bd31663 bne t1,t4,80000704 - -000000008000045c : - 8000045c: 00000213 li tp,0 - 80000460: 0010009b addiw ra,zero,1 - 80000464: 01f09093 slli ra,ra,0x1f - 80000468: 00700113 li sp,7 - 8000046c: 0020df33 srl t5,ra,sp - 80000470: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000474: 00200293 li t0,2 - 80000478: fe5214e3 bne tp,t0,80000460 - 8000047c: 01000eb7 lui t4,0x1000 - 80000480: 01c00193 li gp,28 - 80000484: 29df1063 bne t5,t4,80000704 - -0000000080000488 : - 80000488: 00000213 li tp,0 - 8000048c: 0010009b addiw ra,zero,1 - 80000490: 01f09093 slli ra,ra,0x1f - 80000494: 00e00113 li sp,14 - 80000498: 00000013 nop - 8000049c: 0020df33 srl t5,ra,sp - 800004a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004a4: 00200293 li t0,2 - 800004a8: fe5212e3 bne tp,t0,8000048c - 800004ac: 00020eb7 lui t4,0x20 - 800004b0: 01d00193 li gp,29 - 800004b4: 25df1863 bne t5,t4,80000704 - -00000000800004b8 : - 800004b8: 00000213 li tp,0 - 800004bc: 0010009b addiw ra,zero,1 - 800004c0: 01f09093 slli ra,ra,0x1f - 800004c4: 01f00113 li sp,31 - 800004c8: 00000013 nop - 800004cc: 00000013 nop - 800004d0: 0020df33 srl t5,ra,sp - 800004d4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004d8: 00200293 li t0,2 - 800004dc: fe5210e3 bne tp,t0,800004bc - 800004e0: 00100e93 li t4,1 - 800004e4: 01e00193 li gp,30 - 800004e8: 21df1e63 bne t5,t4,80000704 - -00000000800004ec : - 800004ec: 00000213 li tp,0 - 800004f0: 0010009b addiw ra,zero,1 - 800004f4: 01f09093 slli ra,ra,0x1f - 800004f8: 00000013 nop - 800004fc: 00700113 li sp,7 - 80000500: 0020df33 srl t5,ra,sp - 80000504: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000508: 00200293 li t0,2 - 8000050c: fe5212e3 bne tp,t0,800004f0 - 80000510: 01000eb7 lui t4,0x1000 - 80000514: 01f00193 li gp,31 - 80000518: 1fdf1663 bne t5,t4,80000704 - -000000008000051c : - 8000051c: 00000213 li tp,0 - 80000520: 0010009b addiw ra,zero,1 - 80000524: 01f09093 slli ra,ra,0x1f - 80000528: 00000013 nop - 8000052c: 00e00113 li sp,14 - 80000530: 00000013 nop - 80000534: 0020df33 srl t5,ra,sp - 80000538: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000053c: 00200293 li t0,2 - 80000540: fe5210e3 bne tp,t0,80000520 - 80000544: 00020eb7 lui t4,0x20 - 80000548: 02000193 li gp,32 - 8000054c: 1bdf1c63 bne t5,t4,80000704 - -0000000080000550 : - 80000550: 00000213 li tp,0 - 80000554: 0010009b addiw ra,zero,1 - 80000558: 01f09093 slli ra,ra,0x1f - 8000055c: 00000013 nop - 80000560: 00000013 nop - 80000564: 01f00113 li sp,31 - 80000568: 0020df33 srl t5,ra,sp - 8000056c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000570: 00200293 li t0,2 - 80000574: fe5210e3 bne tp,t0,80000554 - 80000578: 00100e93 li t4,1 - 8000057c: 02100193 li gp,33 - 80000580: 19df1263 bne t5,t4,80000704 - -0000000080000584 : - 80000584: 00000213 li tp,0 - 80000588: 00700113 li sp,7 - 8000058c: 0010009b addiw ra,zero,1 - 80000590: 01f09093 slli ra,ra,0x1f - 80000594: 0020df33 srl t5,ra,sp - 80000598: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000059c: 00200293 li t0,2 - 800005a0: fe5214e3 bne tp,t0,80000588 - 800005a4: 01000eb7 lui t4,0x1000 - 800005a8: 02200193 li gp,34 - 800005ac: 15df1c63 bne t5,t4,80000704 - -00000000800005b0 : - 800005b0: 00000213 li tp,0 - 800005b4: 00e00113 li sp,14 - 800005b8: 0010009b addiw ra,zero,1 - 800005bc: 01f09093 slli ra,ra,0x1f - 800005c0: 00000013 nop - 800005c4: 0020df33 srl t5,ra,sp - 800005c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800005cc: 00200293 li t0,2 - 800005d0: fe5212e3 bne tp,t0,800005b4 - 800005d4: 00020eb7 lui t4,0x20 - 800005d8: 02300193 li gp,35 - 800005dc: 13df1463 bne t5,t4,80000704 - -00000000800005e0 : - 800005e0: 00000213 li tp,0 - 800005e4: 01f00113 li sp,31 - 800005e8: 0010009b addiw ra,zero,1 - 800005ec: 01f09093 slli ra,ra,0x1f - 800005f0: 00000013 nop - 800005f4: 00000013 nop - 800005f8: 0020df33 srl t5,ra,sp - 800005fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000600: 00200293 li t0,2 - 80000604: fe5210e3 bne tp,t0,800005e4 - 80000608: 00100e93 li t4,1 - 8000060c: 02400193 li gp,36 - 80000610: 0fdf1a63 bne t5,t4,80000704 - -0000000080000614 : - 80000614: 00000213 li tp,0 - 80000618: 00700113 li sp,7 - 8000061c: 00000013 nop - 80000620: 0010009b addiw ra,zero,1 - 80000624: 01f09093 slli ra,ra,0x1f - 80000628: 0020df33 srl t5,ra,sp - 8000062c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000630: 00200293 li t0,2 - 80000634: fe5212e3 bne tp,t0,80000618 - 80000638: 01000eb7 lui t4,0x1000 - 8000063c: 02500193 li gp,37 - 80000640: 0ddf1263 bne t5,t4,80000704 - -0000000080000644 : - 80000644: 00000213 li tp,0 - 80000648: 00e00113 li sp,14 - 8000064c: 00000013 nop - 80000650: 0010009b addiw ra,zero,1 - 80000654: 01f09093 slli ra,ra,0x1f - 80000658: 00000013 nop - 8000065c: 0020df33 srl t5,ra,sp - 80000660: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000664: 00200293 li t0,2 - 80000668: fe5210e3 bne tp,t0,80000648 - 8000066c: 00020eb7 lui t4,0x20 - 80000670: 02600193 li gp,38 - 80000674: 09df1863 bne t5,t4,80000704 - -0000000080000678 : - 80000678: 00000213 li tp,0 - 8000067c: 01f00113 li sp,31 - 80000680: 00000013 nop - 80000684: 00000013 nop - 80000688: 0010009b addiw ra,zero,1 - 8000068c: 01f09093 slli ra,ra,0x1f - 80000690: 0020df33 srl t5,ra,sp - 80000694: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000698: 00200293 li t0,2 - 8000069c: fe5210e3 bne tp,t0,8000067c - 800006a0: 00100e93 li t4,1 - 800006a4: 02700193 li gp,39 - 800006a8: 05df1e63 bne t5,t4,80000704 - -00000000800006ac : - 800006ac: 00f00093 li ra,15 - 800006b0: 00105133 srl sp,zero,ra - 800006b4: 00000e93 li t4,0 - 800006b8: 02800193 li gp,40 - 800006bc: 05d11463 bne sp,t4,80000704 - -00000000800006c0 : - 800006c0: 02000093 li ra,32 - 800006c4: 0000d133 srl sp,ra,zero - 800006c8: 02000e93 li t4,32 - 800006cc: 02900193 li gp,41 - 800006d0: 03d11a63 bne sp,t4,80000704 - -00000000800006d4 : - 800006d4: 000050b3 srl ra,zero,zero - 800006d8: 00000e93 li t4,0 - 800006dc: 02a00193 li gp,42 - 800006e0: 03d09263 bne ra,t4,80000704 - -00000000800006e4 : - 800006e4: 40000093 li ra,1024 - 800006e8: 00001137 lui sp,0x1 - 800006ec: 8001011b addiw sp,sp,-2048 - 800006f0: 0020d033 srl zero,ra,sp - 800006f4: 00000e93 li t4,0 - 800006f8: 02b00193 li gp,43 - 800006fc: 01d01463 bne zero,t4,80000704 - 80000700: 00301c63 bne zero,gp,80000718 - -0000000080000704 : - 80000704: 0ff0000f fence - 80000708: 00018063 beqz gp,80000708 - 8000070c: 00119193 slli gp,gp,0x1 - 80000710: 0011e193 ori gp,gp,1 - 80000714: 00000073 ecall - -0000000080000718 : - 80000718: 0ff0000f fence - 8000071c: 00100193 li gp,1 - 80000720: 00000073 ecall - 80000724: c0001073 unimp - 80000728: 0000 unimp - 8000072a: 0000 unimp - 8000072c: 0000 unimp - 8000072e: 0000 unimp - 80000730: 0000 unimp - 80000732: 0000 unimp - 80000734: 0000 unimp - 80000736: 0000 unimp - 80000738: 0000 unimp - 8000073a: 0000 unimp - 8000073c: 0000 unimp - 8000073e: 0000 unimp - 80000740: 0000 unimp - 80000742: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-srl.elf b/test/riscv/tests/rv64ui-p-srl.elf deleted file mode 100644 index 5abd6a01..00000000 Binary files a/test/riscv/tests/rv64ui-p-srl.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-srli.dump b/test/riscv/tests/rv64ui-p-srli.dump deleted file mode 100644 index bcb2df7a..00000000 --- a/test/riscv/tests/rv64ui-p-srli.dump +++ /dev/null @@ -1,350 +0,0 @@ - -rv64ui-p-srli: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 800000b7 lui ra,0x80000 - 80000100: 0000df13 srli t5,ra,0x0 - 80000104: 80000eb7 lui t4,0x80000 - 80000108: 00200193 li gp,2 - 8000010c: 2fdf1663 bne t5,t4,800003f8 - -0000000080000110 : - 80000110: 800000b7 lui ra,0x80000 - 80000114: 0010df13 srli t5,ra,0x1 - 80000118: 00100e9b addiw t4,zero,1 - 8000011c: 021e9e93 slli t4,t4,0x21 - 80000120: fffe8e93 addi t4,t4,-1 # ffffffff7fffffff <_end+0xfffffffeffffdfff> - 80000124: 01ee9e93 slli t4,t4,0x1e - 80000128: 00300193 li gp,3 - 8000012c: 2ddf1663 bne t5,t4,800003f8 - -0000000080000130 : - 80000130: 800000b7 lui ra,0x80000 - 80000134: 0070df13 srli t5,ra,0x7 - 80000138: 00100e9b addiw t4,zero,1 - 8000013c: 021e9e93 slli t4,t4,0x21 - 80000140: fffe8e93 addi t4,t4,-1 - 80000144: 018e9e93 slli t4,t4,0x18 - 80000148: 00400193 li gp,4 - 8000014c: 2bdf1663 bne t5,t4,800003f8 - -0000000080000150 : - 80000150: 800000b7 lui ra,0x80000 - 80000154: 00e0df13 srli t5,ra,0xe - 80000158: 00100e9b addiw t4,zero,1 - 8000015c: 021e9e93 slli t4,t4,0x21 - 80000160: fffe8e93 addi t4,t4,-1 - 80000164: 011e9e93 slli t4,t4,0x11 - 80000168: 00500193 li gp,5 - 8000016c: 29df1663 bne t5,t4,800003f8 - -0000000080000170 : - 80000170: 800000b7 lui ra,0x80000 - 80000174: 0010809b addiw ra,ra,1 - 80000178: 01f0df13 srli t5,ra,0x1f - 8000017c: 00100e9b addiw t4,zero,1 - 80000180: 021e9e93 slli t4,t4,0x21 - 80000184: fffe8e93 addi t4,t4,-1 - 80000188: 00600193 li gp,6 - 8000018c: 27df1663 bne t5,t4,800003f8 - -0000000080000190 : - 80000190: fff00093 li ra,-1 - 80000194: 0000df13 srli t5,ra,0x0 - 80000198: fff00e93 li t4,-1 - 8000019c: 00700193 li gp,7 - 800001a0: 25df1c63 bne t5,t4,800003f8 - -00000000800001a4 : - 800001a4: fff00093 li ra,-1 - 800001a8: 0010df13 srli t5,ra,0x1 - 800001ac: fff00e9b addiw t4,zero,-1 - 800001b0: 03fe9e93 slli t4,t4,0x3f - 800001b4: fffe8e93 addi t4,t4,-1 - 800001b8: 00800193 li gp,8 - 800001bc: 23df1e63 bne t5,t4,800003f8 - -00000000800001c0 : - 800001c0: fff00093 li ra,-1 - 800001c4: 0070df13 srli t5,ra,0x7 - 800001c8: 00100e9b addiw t4,zero,1 - 800001cc: 039e9e93 slli t4,t4,0x39 - 800001d0: fffe8e93 addi t4,t4,-1 - 800001d4: 00900193 li gp,9 - 800001d8: 23df1063 bne t5,t4,800003f8 - -00000000800001dc : - 800001dc: fff00093 li ra,-1 - 800001e0: 00e0df13 srli t5,ra,0xe - 800001e4: 00100e9b addiw t4,zero,1 - 800001e8: 032e9e93 slli t4,t4,0x32 - 800001ec: fffe8e93 addi t4,t4,-1 - 800001f0: 00a00193 li gp,10 - 800001f4: 21df1263 bne t5,t4,800003f8 - -00000000800001f8 : - 800001f8: fff00093 li ra,-1 - 800001fc: 01f0df13 srli t5,ra,0x1f - 80000200: 00100e9b addiw t4,zero,1 - 80000204: 021e9e93 slli t4,t4,0x21 - 80000208: fffe8e93 addi t4,t4,-1 - 8000020c: 00b00193 li gp,11 - 80000210: 1fdf1463 bne t5,t4,800003f8 - -0000000080000214 : - 80000214: 212120b7 lui ra,0x21212 - 80000218: 1210809b addiw ra,ra,289 - 8000021c: 0000df13 srli t5,ra,0x0 - 80000220: 21212eb7 lui t4,0x21212 - 80000224: 121e8e9b addiw t4,t4,289 - 80000228: 00c00193 li gp,12 - 8000022c: 1ddf1663 bne t5,t4,800003f8 - -0000000080000230 : - 80000230: 212120b7 lui ra,0x21212 - 80000234: 1210809b addiw ra,ra,289 - 80000238: 0010df13 srli t5,ra,0x1 - 8000023c: 10909eb7 lui t4,0x10909 - 80000240: 090e8e9b addiw t4,t4,144 - 80000244: 00d00193 li gp,13 - 80000248: 1bdf1863 bne t5,t4,800003f8 - -000000008000024c : - 8000024c: 212120b7 lui ra,0x21212 - 80000250: 1210809b addiw ra,ra,289 - 80000254: 0070df13 srli t5,ra,0x7 - 80000258: 00424eb7 lui t4,0x424 - 8000025c: 242e8e9b addiw t4,t4,578 - 80000260: 00e00193 li gp,14 - 80000264: 19df1a63 bne t5,t4,800003f8 - -0000000080000268 : - 80000268: 212120b7 lui ra,0x21212 - 8000026c: 1210809b addiw ra,ra,289 - 80000270: 00e0df13 srli t5,ra,0xe - 80000274: 00008eb7 lui t4,0x8 - 80000278: 484e8e9b addiw t4,t4,1156 - 8000027c: 00f00193 li gp,15 - 80000280: 17df1c63 bne t5,t4,800003f8 - -0000000080000284 : - 80000284: 212120b7 lui ra,0x21212 - 80000288: 1210809b addiw ra,ra,289 - 8000028c: 01f0df13 srli t5,ra,0x1f - 80000290: 00000e93 li t4,0 - 80000294: 01000193 li gp,16 - 80000298: 17df1063 bne t5,t4,800003f8 - -000000008000029c : - 8000029c: 0010009b addiw ra,zero,1 - 800002a0: 01f09093 slli ra,ra,0x1f - 800002a4: 0070d093 srli ra,ra,0x7 - 800002a8: 01000eb7 lui t4,0x1000 - 800002ac: 01100193 li gp,17 - 800002b0: 15d09463 bne ra,t4,800003f8 - -00000000800002b4 : - 800002b4: 00000213 li tp,0 - 800002b8: 0010009b addiw ra,zero,1 - 800002bc: 01f09093 slli ra,ra,0x1f - 800002c0: 0070df13 srli t5,ra,0x7 - 800002c4: 000f0313 mv t1,t5 - 800002c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002cc: 00200293 li t0,2 - 800002d0: fe5214e3 bne tp,t0,800002b8 - 800002d4: 01000eb7 lui t4,0x1000 - 800002d8: 01200193 li gp,18 - 800002dc: 11d31e63 bne t1,t4,800003f8 - -00000000800002e0 : - 800002e0: 00000213 li tp,0 - 800002e4: 0010009b addiw ra,zero,1 - 800002e8: 01f09093 slli ra,ra,0x1f - 800002ec: 00e0df13 srli t5,ra,0xe - 800002f0: 00000013 nop - 800002f4: 000f0313 mv t1,t5 - 800002f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002fc: 00200293 li t0,2 - 80000300: fe5212e3 bne tp,t0,800002e4 - 80000304: 00020eb7 lui t4,0x20 - 80000308: 01300193 li gp,19 - 8000030c: 0fd31663 bne t1,t4,800003f8 - -0000000080000310 : - 80000310: 00000213 li tp,0 - 80000314: 0010009b addiw ra,zero,1 - 80000318: 01f09093 slli ra,ra,0x1f - 8000031c: 00108093 addi ra,ra,1 # 21212001 <_start-0x5ededfff> - 80000320: 01f0df13 srli t5,ra,0x1f - 80000324: 00000013 nop - 80000328: 00000013 nop - 8000032c: 000f0313 mv t1,t5 - 80000330: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000334: 00200293 li t0,2 - 80000338: fc521ee3 bne tp,t0,80000314 - 8000033c: 00100e93 li t4,1 - 80000340: 01400193 li gp,20 - 80000344: 0bd31a63 bne t1,t4,800003f8 - -0000000080000348 : - 80000348: 00000213 li tp,0 - 8000034c: 0010009b addiw ra,zero,1 - 80000350: 01f09093 slli ra,ra,0x1f - 80000354: 0070df13 srli t5,ra,0x7 - 80000358: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000035c: 00200293 li t0,2 - 80000360: fe5216e3 bne tp,t0,8000034c - 80000364: 01000eb7 lui t4,0x1000 - 80000368: 01500193 li gp,21 - 8000036c: 09df1663 bne t5,t4,800003f8 - -0000000080000370 : - 80000370: 00000213 li tp,0 - 80000374: 0010009b addiw ra,zero,1 - 80000378: 01f09093 slli ra,ra,0x1f - 8000037c: 00000013 nop - 80000380: 00e0df13 srli t5,ra,0xe - 80000384: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000388: 00200293 li t0,2 - 8000038c: fe5214e3 bne tp,t0,80000374 - 80000390: 00020eb7 lui t4,0x20 - 80000394: 01600193 li gp,22 - 80000398: 07df1063 bne t5,t4,800003f8 - -000000008000039c : - 8000039c: 00000213 li tp,0 - 800003a0: 0010009b addiw ra,zero,1 - 800003a4: 01f09093 slli ra,ra,0x1f - 800003a8: 00108093 addi ra,ra,1 - 800003ac: 00000013 nop - 800003b0: 00000013 nop - 800003b4: 01f0df13 srli t5,ra,0x1f - 800003b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003bc: 00200293 li t0,2 - 800003c0: fe5210e3 bne tp,t0,800003a0 - 800003c4: 00100e93 li t4,1 - 800003c8: 01700193 li gp,23 - 800003cc: 03df1663 bne t5,t4,800003f8 - -00000000800003d0 : - 800003d0: 00405093 srli ra,zero,0x4 - 800003d4: 00000e93 li t4,0 - 800003d8: 01800193 li gp,24 - 800003dc: 01d09e63 bne ra,t4,800003f8 - -00000000800003e0 : - 800003e0: 02100093 li ra,33 - 800003e4: 00a0d013 srli zero,ra,0xa - 800003e8: 00000e93 li t4,0 - 800003ec: 01900193 li gp,25 - 800003f0: 01d01463 bne zero,t4,800003f8 - 800003f4: 00301c63 bne zero,gp,8000040c - -00000000800003f8 : - 800003f8: 0ff0000f fence - 800003fc: 00018063 beqz gp,800003fc - 80000400: 00119193 slli gp,gp,0x1 - 80000404: 0011e193 ori gp,gp,1 - 80000408: 00000073 ecall - -000000008000040c : - 8000040c: 0ff0000f fence - 80000410: 00100193 li gp,1 - 80000414: 00000073 ecall - 80000418: c0001073 unimp - 8000041c: 0000 unimp - 8000041e: 0000 unimp - 80000420: 0000 unimp - 80000422: 0000 unimp - 80000424: 0000 unimp - 80000426: 0000 unimp - 80000428: 0000 unimp - 8000042a: 0000 unimp - 8000042c: 0000 unimp - 8000042e: 0000 unimp - 80000430: 0000 unimp - 80000432: 0000 unimp - 80000434: 0000 unimp - 80000436: 0000 unimp - 80000438: 0000 unimp - 8000043a: 0000 unimp - 8000043c: 0000 unimp - 8000043e: 0000 unimp - 80000440: 0000 unimp - 80000442: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-srli.elf b/test/riscv/tests/rv64ui-p-srli.elf deleted file mode 100644 index 6e2f7948..00000000 Binary files a/test/riscv/tests/rv64ui-p-srli.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-srliw.dump b/test/riscv/tests/rv64ui-p-srliw.dump deleted file mode 100644 index 99581fb6..00000000 --- a/test/riscv/tests/rv64ui-p-srliw.dump +++ /dev/null @@ -1,309 +0,0 @@ - -rv64ui-p-srliw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 800000b7 lui ra,0x80000 - 80000100: 0000df1b srliw t5,ra,0x0 - 80000104: 80000eb7 lui t4,0x80000 - 80000108: 00200193 li gp,2 - 8000010c: 29df1863 bne t5,t4,8000039c - -0000000080000110 : - 80000110: 800000b7 lui ra,0x80000 - 80000114: 0010df1b srliw t5,ra,0x1 - 80000118: 40000eb7 lui t4,0x40000 - 8000011c: 00300193 li gp,3 - 80000120: 27df1e63 bne t5,t4,8000039c - -0000000080000124 : - 80000124: 800000b7 lui ra,0x80000 - 80000128: 0070df1b srliw t5,ra,0x7 - 8000012c: 01000eb7 lui t4,0x1000 - 80000130: 00400193 li gp,4 - 80000134: 27df1463 bne t5,t4,8000039c - -0000000080000138 : - 80000138: 800000b7 lui ra,0x80000 - 8000013c: 00e0df1b srliw t5,ra,0xe - 80000140: 00020eb7 lui t4,0x20 - 80000144: 00500193 li gp,5 - 80000148: 25df1a63 bne t5,t4,8000039c - -000000008000014c : - 8000014c: 800000b7 lui ra,0x80000 - 80000150: 0010809b addiw ra,ra,1 - 80000154: 01f0df1b srliw t5,ra,0x1f - 80000158: 00100e93 li t4,1 - 8000015c: 00600193 li gp,6 - 80000160: 23df1e63 bne t5,t4,8000039c - -0000000080000164 : - 80000164: fff00093 li ra,-1 - 80000168: 0000df1b srliw t5,ra,0x0 - 8000016c: fff00e93 li t4,-1 - 80000170: 00700193 li gp,7 - 80000174: 23df1463 bne t5,t4,8000039c - -0000000080000178 : - 80000178: fff00093 li ra,-1 - 8000017c: 0010df1b srliw t5,ra,0x1 - 80000180: 80000eb7 lui t4,0x80000 - 80000184: fffe8e9b addiw t4,t4,-1 - 80000188: 00800193 li gp,8 - 8000018c: 21df1863 bne t5,t4,8000039c - -0000000080000190 : - 80000190: fff00093 li ra,-1 - 80000194: 0070df1b srliw t5,ra,0x7 - 80000198: 02000eb7 lui t4,0x2000 - 8000019c: fffe8e9b addiw t4,t4,-1 - 800001a0: 00900193 li gp,9 - 800001a4: 1fdf1c63 bne t5,t4,8000039c - -00000000800001a8 : - 800001a8: fff00093 li ra,-1 - 800001ac: 00e0df1b srliw t5,ra,0xe - 800001b0: 00040eb7 lui t4,0x40 - 800001b4: fffe8e9b addiw t4,t4,-1 - 800001b8: 00a00193 li gp,10 - 800001bc: 1fdf1063 bne t5,t4,8000039c - -00000000800001c0 : - 800001c0: fff00093 li ra,-1 - 800001c4: 01f0df1b srliw t5,ra,0x1f - 800001c8: 00100e93 li t4,1 - 800001cc: 00b00193 li gp,11 - 800001d0: 1ddf1663 bne t5,t4,8000039c - -00000000800001d4 : - 800001d4: 212120b7 lui ra,0x21212 - 800001d8: 1210809b addiw ra,ra,289 - 800001dc: 0000df1b srliw t5,ra,0x0 - 800001e0: 21212eb7 lui t4,0x21212 - 800001e4: 121e8e9b addiw t4,t4,289 - 800001e8: 00c00193 li gp,12 - 800001ec: 1bdf1863 bne t5,t4,8000039c - -00000000800001f0 : - 800001f0: 212120b7 lui ra,0x21212 - 800001f4: 1210809b addiw ra,ra,289 - 800001f8: 0010df1b srliw t5,ra,0x1 - 800001fc: 10909eb7 lui t4,0x10909 - 80000200: 090e8e9b addiw t4,t4,144 - 80000204: 00d00193 li gp,13 - 80000208: 19df1a63 bne t5,t4,8000039c - -000000008000020c : - 8000020c: 212120b7 lui ra,0x21212 - 80000210: 1210809b addiw ra,ra,289 - 80000214: 0070df1b srliw t5,ra,0x7 - 80000218: 00424eb7 lui t4,0x424 - 8000021c: 242e8e9b addiw t4,t4,578 - 80000220: 00e00193 li gp,14 - 80000224: 17df1c63 bne t5,t4,8000039c - -0000000080000228 : - 80000228: 212120b7 lui ra,0x21212 - 8000022c: 1210809b addiw ra,ra,289 - 80000230: 00e0df1b srliw t5,ra,0xe - 80000234: 00008eb7 lui t4,0x8 - 80000238: 484e8e9b addiw t4,t4,1156 - 8000023c: 00f00193 li gp,15 - 80000240: 15df1e63 bne t5,t4,8000039c - -0000000080000244 : - 80000244: 212120b7 lui ra,0x21212 - 80000248: 1210809b addiw ra,ra,289 - 8000024c: 01f0df1b srliw t5,ra,0x1f - 80000250: 00000e93 li t4,0 - 80000254: 01000193 li gp,16 - 80000258: 15df1263 bne t5,t4,8000039c - -000000008000025c : - 8000025c: 800000b7 lui ra,0x80000 - 80000260: 0070d09b srliw ra,ra,0x7 - 80000264: 01000eb7 lui t4,0x1000 - 80000268: 01100193 li gp,17 - 8000026c: 13d09863 bne ra,t4,8000039c - -0000000080000270 : - 80000270: 00000213 li tp,0 - 80000274: 800000b7 lui ra,0x80000 - 80000278: 0070df1b srliw t5,ra,0x7 - 8000027c: 000f0313 mv t1,t5 - 80000280: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000284: 00200293 li t0,2 - 80000288: fe5216e3 bne tp,t0,80000274 - 8000028c: 01000eb7 lui t4,0x1000 - 80000290: 01200193 li gp,18 - 80000294: 11d31463 bne t1,t4,8000039c - -0000000080000298 : - 80000298: 00000213 li tp,0 - 8000029c: 800000b7 lui ra,0x80000 - 800002a0: 00e0df1b srliw t5,ra,0xe - 800002a4: 00000013 nop - 800002a8: 000f0313 mv t1,t5 - 800002ac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002b0: 00200293 li t0,2 - 800002b4: fe5214e3 bne tp,t0,8000029c - 800002b8: 00020eb7 lui t4,0x20 - 800002bc: 01300193 li gp,19 - 800002c0: 0dd31e63 bne t1,t4,8000039c - -00000000800002c4 : - 800002c4: 00000213 li tp,0 - 800002c8: 800000b7 lui ra,0x80000 - 800002cc: 0010809b addiw ra,ra,1 - 800002d0: 01f0df1b srliw t5,ra,0x1f - 800002d4: 00000013 nop - 800002d8: 00000013 nop - 800002dc: 000f0313 mv t1,t5 - 800002e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002e4: 00200293 li t0,2 - 800002e8: fe5210e3 bne tp,t0,800002c8 - 800002ec: 00100e93 li t4,1 - 800002f0: 01400193 li gp,20 - 800002f4: 0bd31463 bne t1,t4,8000039c - -00000000800002f8 : - 800002f8: 00000213 li tp,0 - 800002fc: 800000b7 lui ra,0x80000 - 80000300: 0070df1b srliw t5,ra,0x7 - 80000304: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000308: 00200293 li t0,2 - 8000030c: fe5218e3 bne tp,t0,800002fc - 80000310: 01000eb7 lui t4,0x1000 - 80000314: 01500193 li gp,21 - 80000318: 09df1263 bne t5,t4,8000039c - -000000008000031c : - 8000031c: 00000213 li tp,0 - 80000320: 800000b7 lui ra,0x80000 - 80000324: 00000013 nop - 80000328: 00e0df1b srliw t5,ra,0xe - 8000032c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000330: 00200293 li t0,2 - 80000334: fe5216e3 bne tp,t0,80000320 - 80000338: 00020eb7 lui t4,0x20 - 8000033c: 01600193 li gp,22 - 80000340: 05df1e63 bne t5,t4,8000039c - -0000000080000344 : - 80000344: 00000213 li tp,0 - 80000348: 800000b7 lui ra,0x80000 - 8000034c: 0010809b addiw ra,ra,1 - 80000350: 00000013 nop - 80000354: 00000013 nop - 80000358: 01f0df1b srliw t5,ra,0x1f - 8000035c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000360: 00200293 li t0,2 - 80000364: fe5212e3 bne tp,t0,80000348 - 80000368: 00100e93 li t4,1 - 8000036c: 01700193 li gp,23 - 80000370: 03df1663 bne t5,t4,8000039c - -0000000080000374 : - 80000374: 01f0509b srliw ra,zero,0x1f - 80000378: 00000e93 li t4,0 - 8000037c: 01800193 li gp,24 - 80000380: 01d09e63 bne ra,t4,8000039c - -0000000080000384 : - 80000384: 01f00093 li ra,31 - 80000388: 01c0d01b srliw zero,ra,0x1c - 8000038c: 00000e93 li t4,0 - 80000390: 01900193 li gp,25 - 80000394: 01d01463 bne zero,t4,8000039c - 80000398: 00301c63 bne zero,gp,800003b0 - -000000008000039c : - 8000039c: 0ff0000f fence - 800003a0: 00018063 beqz gp,800003a0 - 800003a4: 00119193 slli gp,gp,0x1 - 800003a8: 0011e193 ori gp,gp,1 - 800003ac: 00000073 ecall - -00000000800003b0 : - 800003b0: 0ff0000f fence - 800003b4: 00100193 li gp,1 - 800003b8: 00000073 ecall - 800003bc: c0001073 unimp - 800003c0: 0000 unimp - 800003c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-srliw.elf b/test/riscv/tests/rv64ui-p-srliw.elf deleted file mode 100644 index 70758a3c..00000000 Binary files a/test/riscv/tests/rv64ui-p-srliw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-srlw.dump b/test/riscv/tests/rv64ui-p-srlw.dump deleted file mode 100644 index cf3f8377..00000000 --- a/test/riscv/tests/rv64ui-p-srlw.dump +++ /dev/null @@ -1,544 +0,0 @@ - -rv64ui-p-srlw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 800000b7 lui ra,0x80000 - 80000100: 00000113 li sp,0 - 80000104: 0020df3b srlw t5,ra,sp - 80000108: 80000eb7 lui t4,0x80000 - 8000010c: 00200193 li gp,2 - 80000110: 57df1863 bne t5,t4,80000680 - -0000000080000114 : - 80000114: 800000b7 lui ra,0x80000 - 80000118: 00100113 li sp,1 - 8000011c: 0020df3b srlw t5,ra,sp - 80000120: 40000eb7 lui t4,0x40000 - 80000124: 00300193 li gp,3 - 80000128: 55df1c63 bne t5,t4,80000680 - -000000008000012c : - 8000012c: 800000b7 lui ra,0x80000 - 80000130: 00700113 li sp,7 - 80000134: 0020df3b srlw t5,ra,sp - 80000138: 01000eb7 lui t4,0x1000 - 8000013c: 00400193 li gp,4 - 80000140: 55df1063 bne t5,t4,80000680 - -0000000080000144 : - 80000144: 800000b7 lui ra,0x80000 - 80000148: 00e00113 li sp,14 - 8000014c: 0020df3b srlw t5,ra,sp - 80000150: 00020eb7 lui t4,0x20 - 80000154: 00500193 li gp,5 - 80000158: 53df1463 bne t5,t4,80000680 - -000000008000015c : - 8000015c: 800000b7 lui ra,0x80000 - 80000160: 0010809b addiw ra,ra,1 - 80000164: 01f00113 li sp,31 - 80000168: 0020df3b srlw t5,ra,sp - 8000016c: 00100e93 li t4,1 - 80000170: 00600193 li gp,6 - 80000174: 51df1663 bne t5,t4,80000680 - -0000000080000178 : - 80000178: fff00093 li ra,-1 - 8000017c: 00000113 li sp,0 - 80000180: 0020df3b srlw t5,ra,sp - 80000184: fff00e93 li t4,-1 - 80000188: 00700193 li gp,7 - 8000018c: 4fdf1a63 bne t5,t4,80000680 - -0000000080000190 : - 80000190: fff00093 li ra,-1 - 80000194: 00100113 li sp,1 - 80000198: 0020df3b srlw t5,ra,sp - 8000019c: 80000eb7 lui t4,0x80000 - 800001a0: fffe8e9b addiw t4,t4,-1 - 800001a4: 00800193 li gp,8 - 800001a8: 4ddf1c63 bne t5,t4,80000680 - -00000000800001ac : - 800001ac: fff00093 li ra,-1 - 800001b0: 00700113 li sp,7 - 800001b4: 0020df3b srlw t5,ra,sp - 800001b8: 02000eb7 lui t4,0x2000 - 800001bc: fffe8e9b addiw t4,t4,-1 - 800001c0: 00900193 li gp,9 - 800001c4: 4bdf1e63 bne t5,t4,80000680 - -00000000800001c8 : - 800001c8: fff00093 li ra,-1 - 800001cc: 00e00113 li sp,14 - 800001d0: 0020df3b srlw t5,ra,sp - 800001d4: 00040eb7 lui t4,0x40 - 800001d8: fffe8e9b addiw t4,t4,-1 - 800001dc: 00a00193 li gp,10 - 800001e0: 4bdf1063 bne t5,t4,80000680 - -00000000800001e4 : - 800001e4: fff00093 li ra,-1 - 800001e8: 01f00113 li sp,31 - 800001ec: 0020df3b srlw t5,ra,sp - 800001f0: 00100e93 li t4,1 - 800001f4: 00b00193 li gp,11 - 800001f8: 49df1463 bne t5,t4,80000680 - -00000000800001fc : - 800001fc: 212120b7 lui ra,0x21212 - 80000200: 1210809b addiw ra,ra,289 - 80000204: 00000113 li sp,0 - 80000208: 0020df3b srlw t5,ra,sp - 8000020c: 21212eb7 lui t4,0x21212 - 80000210: 121e8e9b addiw t4,t4,289 - 80000214: 00c00193 li gp,12 - 80000218: 47df1463 bne t5,t4,80000680 - -000000008000021c : - 8000021c: 212120b7 lui ra,0x21212 - 80000220: 1210809b addiw ra,ra,289 - 80000224: 00100113 li sp,1 - 80000228: 0020df3b srlw t5,ra,sp - 8000022c: 10909eb7 lui t4,0x10909 - 80000230: 090e8e9b addiw t4,t4,144 - 80000234: 00d00193 li gp,13 - 80000238: 45df1463 bne t5,t4,80000680 - -000000008000023c : - 8000023c: 212120b7 lui ra,0x21212 - 80000240: 1210809b addiw ra,ra,289 - 80000244: 00700113 li sp,7 - 80000248: 0020df3b srlw t5,ra,sp - 8000024c: 00424eb7 lui t4,0x424 - 80000250: 242e8e9b addiw t4,t4,578 - 80000254: 00e00193 li gp,14 - 80000258: 43df1463 bne t5,t4,80000680 - -000000008000025c : - 8000025c: 212120b7 lui ra,0x21212 - 80000260: 1210809b addiw ra,ra,289 - 80000264: 00e00113 li sp,14 - 80000268: 0020df3b srlw t5,ra,sp - 8000026c: 00008eb7 lui t4,0x8 - 80000270: 484e8e9b addiw t4,t4,1156 - 80000274: 00f00193 li gp,15 - 80000278: 41df1463 bne t5,t4,80000680 - -000000008000027c : - 8000027c: 212120b7 lui ra,0x21212 - 80000280: 1210809b addiw ra,ra,289 - 80000284: 01f00113 li sp,31 - 80000288: 0020df3b srlw t5,ra,sp - 8000028c: 00000e93 li t4,0 - 80000290: 01000193 li gp,16 - 80000294: 3fdf1663 bne t5,t4,80000680 - -0000000080000298 : - 80000298: 212120b7 lui ra,0x21212 - 8000029c: 1210809b addiw ra,ra,289 - 800002a0: fe000113 li sp,-32 - 800002a4: 0020df3b srlw t5,ra,sp - 800002a8: 21212eb7 lui t4,0x21212 - 800002ac: 121e8e9b addiw t4,t4,289 - 800002b0: 01100193 li gp,17 - 800002b4: 3ddf1663 bne t5,t4,80000680 - -00000000800002b8 : - 800002b8: 212120b7 lui ra,0x21212 - 800002bc: 1210809b addiw ra,ra,289 - 800002c0: fe100113 li sp,-31 - 800002c4: 0020df3b srlw t5,ra,sp - 800002c8: 10909eb7 lui t4,0x10909 - 800002cc: 090e8e9b addiw t4,t4,144 - 800002d0: 01200193 li gp,18 - 800002d4: 3bdf1663 bne t5,t4,80000680 - -00000000800002d8 : - 800002d8: 212120b7 lui ra,0x21212 - 800002dc: 1210809b addiw ra,ra,289 - 800002e0: fe700113 li sp,-25 - 800002e4: 0020df3b srlw t5,ra,sp - 800002e8: 00424eb7 lui t4,0x424 - 800002ec: 242e8e9b addiw t4,t4,578 - 800002f0: 01300193 li gp,19 - 800002f4: 39df1663 bne t5,t4,80000680 - -00000000800002f8 : - 800002f8: 212120b7 lui ra,0x21212 - 800002fc: 1210809b addiw ra,ra,289 - 80000300: fee00113 li sp,-18 - 80000304: 0020df3b srlw t5,ra,sp - 80000308: 00008eb7 lui t4,0x8 - 8000030c: 484e8e9b addiw t4,t4,1156 - 80000310: 01400193 li gp,20 - 80000314: 37df1663 bne t5,t4,80000680 - -0000000080000318 : - 80000318: 212120b7 lui ra,0x21212 - 8000031c: 1210809b addiw ra,ra,289 - 80000320: fff00113 li sp,-1 - 80000324: 0020df3b srlw t5,ra,sp - 80000328: 00000e93 li t4,0 - 8000032c: 01500193 li gp,21 - 80000330: 35df1863 bne t5,t4,80000680 - -0000000080000334 : - 80000334: 800000b7 lui ra,0x80000 - 80000338: 00700113 li sp,7 - 8000033c: 0020d0bb srlw ra,ra,sp - 80000340: 01000eb7 lui t4,0x1000 - 80000344: 01600193 li gp,22 - 80000348: 33d09c63 bne ra,t4,80000680 - -000000008000034c : - 8000034c: 800000b7 lui ra,0x80000 - 80000350: 00e00113 li sp,14 - 80000354: 0020d13b srlw sp,ra,sp - 80000358: 00020eb7 lui t4,0x20 - 8000035c: 01700193 li gp,23 - 80000360: 33d11063 bne sp,t4,80000680 - -0000000080000364 : - 80000364: 00700093 li ra,7 - 80000368: 0010d0bb srlw ra,ra,ra - 8000036c: 00000e93 li t4,0 - 80000370: 01800193 li gp,24 - 80000374: 31d09663 bne ra,t4,80000680 - -0000000080000378 : - 80000378: 00000213 li tp,0 - 8000037c: 800000b7 lui ra,0x80000 - 80000380: 00700113 li sp,7 - 80000384: 0020df3b srlw t5,ra,sp - 80000388: 000f0313 mv t1,t5 - 8000038c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000390: 00200293 li t0,2 - 80000394: fe5214e3 bne tp,t0,8000037c - 80000398: 01000eb7 lui t4,0x1000 - 8000039c: 01900193 li gp,25 - 800003a0: 2fd31063 bne t1,t4,80000680 - -00000000800003a4 : - 800003a4: 00000213 li tp,0 - 800003a8: 800000b7 lui ra,0x80000 - 800003ac: 00e00113 li sp,14 - 800003b0: 0020df3b srlw t5,ra,sp - 800003b4: 00000013 nop - 800003b8: 000f0313 mv t1,t5 - 800003bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003c0: 00200293 li t0,2 - 800003c4: fe5212e3 bne tp,t0,800003a8 - 800003c8: 00020eb7 lui t4,0x20 - 800003cc: 01a00193 li gp,26 - 800003d0: 2bd31863 bne t1,t4,80000680 - -00000000800003d4 : - 800003d4: 00000213 li tp,0 - 800003d8: 800000b7 lui ra,0x80000 - 800003dc: 01f00113 li sp,31 - 800003e0: 0020df3b srlw t5,ra,sp - 800003e4: 00000013 nop - 800003e8: 00000013 nop - 800003ec: 000f0313 mv t1,t5 - 800003f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003f4: 00200293 li t0,2 - 800003f8: fe5210e3 bne tp,t0,800003d8 - 800003fc: 00100e93 li t4,1 - 80000400: 01b00193 li gp,27 - 80000404: 27d31e63 bne t1,t4,80000680 - -0000000080000408 : - 80000408: 00000213 li tp,0 - 8000040c: 800000b7 lui ra,0x80000 - 80000410: 00700113 li sp,7 - 80000414: 0020df3b srlw t5,ra,sp - 80000418: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000041c: 00200293 li t0,2 - 80000420: fe5216e3 bne tp,t0,8000040c - 80000424: 01000eb7 lui t4,0x1000 - 80000428: 01c00193 li gp,28 - 8000042c: 25df1a63 bne t5,t4,80000680 - -0000000080000430 : - 80000430: 00000213 li tp,0 - 80000434: 800000b7 lui ra,0x80000 - 80000438: 00e00113 li sp,14 - 8000043c: 00000013 nop - 80000440: 0020df3b srlw t5,ra,sp - 80000444: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000448: 00200293 li t0,2 - 8000044c: fe5214e3 bne tp,t0,80000434 - 80000450: 00020eb7 lui t4,0x20 - 80000454: 01d00193 li gp,29 - 80000458: 23df1463 bne t5,t4,80000680 - -000000008000045c : - 8000045c: 00000213 li tp,0 - 80000460: 800000b7 lui ra,0x80000 - 80000464: 01f00113 li sp,31 - 80000468: 00000013 nop - 8000046c: 00000013 nop - 80000470: 0020df3b srlw t5,ra,sp - 80000474: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000478: 00200293 li t0,2 - 8000047c: fe5212e3 bne tp,t0,80000460 - 80000480: 00100e93 li t4,1 - 80000484: 01e00193 li gp,30 - 80000488: 1fdf1c63 bne t5,t4,80000680 - -000000008000048c : - 8000048c: 00000213 li tp,0 - 80000490: 800000b7 lui ra,0x80000 - 80000494: 00000013 nop - 80000498: 00700113 li sp,7 - 8000049c: 0020df3b srlw t5,ra,sp - 800004a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004a4: 00200293 li t0,2 - 800004a8: fe5214e3 bne tp,t0,80000490 - 800004ac: 01000eb7 lui t4,0x1000 - 800004b0: 01f00193 li gp,31 - 800004b4: 1ddf1663 bne t5,t4,80000680 - -00000000800004b8 : - 800004b8: 00000213 li tp,0 - 800004bc: 800000b7 lui ra,0x80000 - 800004c0: 00000013 nop - 800004c4: 00e00113 li sp,14 - 800004c8: 00000013 nop - 800004cc: 0020df3b srlw t5,ra,sp - 800004d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004d4: 00200293 li t0,2 - 800004d8: fe5212e3 bne tp,t0,800004bc - 800004dc: 00020eb7 lui t4,0x20 - 800004e0: 02000193 li gp,32 - 800004e4: 19df1e63 bne t5,t4,80000680 - -00000000800004e8 : - 800004e8: 00000213 li tp,0 - 800004ec: 800000b7 lui ra,0x80000 - 800004f0: 00000013 nop - 800004f4: 00000013 nop - 800004f8: 01f00113 li sp,31 - 800004fc: 0020df3b srlw t5,ra,sp - 80000500: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000504: 00200293 li t0,2 - 80000508: fe5212e3 bne tp,t0,800004ec - 8000050c: 00100e93 li t4,1 - 80000510: 02100193 li gp,33 - 80000514: 17df1663 bne t5,t4,80000680 - -0000000080000518 : - 80000518: 00000213 li tp,0 - 8000051c: 00700113 li sp,7 - 80000520: 800000b7 lui ra,0x80000 - 80000524: 0020df3b srlw t5,ra,sp - 80000528: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000052c: 00200293 li t0,2 - 80000530: fe5216e3 bne tp,t0,8000051c - 80000534: 01000eb7 lui t4,0x1000 - 80000538: 02200193 li gp,34 - 8000053c: 15df1263 bne t5,t4,80000680 - -0000000080000540 : - 80000540: 00000213 li tp,0 - 80000544: 00e00113 li sp,14 - 80000548: 800000b7 lui ra,0x80000 - 8000054c: 00000013 nop - 80000550: 0020df3b srlw t5,ra,sp - 80000554: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000558: 00200293 li t0,2 - 8000055c: fe5214e3 bne tp,t0,80000544 - 80000560: 00020eb7 lui t4,0x20 - 80000564: 02300193 li gp,35 - 80000568: 11df1c63 bne t5,t4,80000680 - -000000008000056c : - 8000056c: 00000213 li tp,0 - 80000570: 01f00113 li sp,31 - 80000574: 800000b7 lui ra,0x80000 - 80000578: 00000013 nop - 8000057c: 00000013 nop - 80000580: 0020df3b srlw t5,ra,sp - 80000584: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000588: 00200293 li t0,2 - 8000058c: fe5212e3 bne tp,t0,80000570 - 80000590: 00100e93 li t4,1 - 80000594: 02400193 li gp,36 - 80000598: 0fdf1463 bne t5,t4,80000680 - -000000008000059c : - 8000059c: 00000213 li tp,0 - 800005a0: 00700113 li sp,7 - 800005a4: 00000013 nop - 800005a8: 800000b7 lui ra,0x80000 - 800005ac: 0020df3b srlw t5,ra,sp - 800005b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800005b4: 00200293 li t0,2 - 800005b8: fe5214e3 bne tp,t0,800005a0 - 800005bc: 01000eb7 lui t4,0x1000 - 800005c0: 02500193 li gp,37 - 800005c4: 0bdf1e63 bne t5,t4,80000680 - -00000000800005c8 : - 800005c8: 00000213 li tp,0 - 800005cc: 00e00113 li sp,14 - 800005d0: 00000013 nop - 800005d4: 800000b7 lui ra,0x80000 - 800005d8: 00000013 nop - 800005dc: 0020df3b srlw t5,ra,sp - 800005e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800005e4: 00200293 li t0,2 - 800005e8: fe5212e3 bne tp,t0,800005cc - 800005ec: 00020eb7 lui t4,0x20 - 800005f0: 02600193 li gp,38 - 800005f4: 09df1663 bne t5,t4,80000680 - -00000000800005f8 : - 800005f8: 00000213 li tp,0 - 800005fc: 01f00113 li sp,31 - 80000600: 00000013 nop - 80000604: 00000013 nop - 80000608: 800000b7 lui ra,0x80000 - 8000060c: 0020df3b srlw t5,ra,sp - 80000610: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000614: 00200293 li t0,2 - 80000618: fe5212e3 bne tp,t0,800005fc - 8000061c: 00100e93 li t4,1 - 80000620: 02700193 li gp,39 - 80000624: 05df1e63 bne t5,t4,80000680 - -0000000080000628 : - 80000628: 00f00093 li ra,15 - 8000062c: 0010513b srlw sp,zero,ra - 80000630: 00000e93 li t4,0 - 80000634: 02800193 li gp,40 - 80000638: 05d11463 bne sp,t4,80000680 - -000000008000063c : - 8000063c: 02000093 li ra,32 - 80000640: 0000d13b srlw sp,ra,zero - 80000644: 02000e93 li t4,32 - 80000648: 02900193 li gp,41 - 8000064c: 03d11a63 bne sp,t4,80000680 - -0000000080000650 : - 80000650: 000050bb srlw ra,zero,zero - 80000654: 00000e93 li t4,0 - 80000658: 02a00193 li gp,42 - 8000065c: 03d09263 bne ra,t4,80000680 - -0000000080000660 : - 80000660: 40000093 li ra,1024 - 80000664: 00001137 lui sp,0x1 - 80000668: 8001011b addiw sp,sp,-2048 - 8000066c: 0020d03b srlw zero,ra,sp - 80000670: 00000e93 li t4,0 - 80000674: 02b00193 li gp,43 - 80000678: 01d01463 bne zero,t4,80000680 - 8000067c: 00301c63 bne zero,gp,80000694 - -0000000080000680 : - 80000680: 0ff0000f fence - 80000684: 00018063 beqz gp,80000684 - 80000688: 00119193 slli gp,gp,0x1 - 8000068c: 0011e193 ori gp,gp,1 - 80000690: 00000073 ecall - -0000000080000694 : - 80000694: 0ff0000f fence - 80000698: 00100193 li gp,1 - 8000069c: 00000073 ecall - 800006a0: c0001073 unimp - 800006a4: 0000 unimp - 800006a6: 0000 unimp - 800006a8: 0000 unimp - 800006aa: 0000 unimp - 800006ac: 0000 unimp - 800006ae: 0000 unimp - 800006b0: 0000 unimp - 800006b2: 0000 unimp - 800006b4: 0000 unimp - 800006b6: 0000 unimp - 800006b8: 0000 unimp - 800006ba: 0000 unimp - 800006bc: 0000 unimp - 800006be: 0000 unimp - 800006c0: 0000 unimp - 800006c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-srlw.elf b/test/riscv/tests/rv64ui-p-srlw.elf deleted file mode 100644 index d1758021..00000000 Binary files a/test/riscv/tests/rv64ui-p-srlw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-sub.dump b/test/riscv/tests/rv64ui-p-sub.dump deleted file mode 100644 index 34bda7b8..00000000 --- a/test/riscv/tests/rv64ui-p-sub.dump +++ /dev/null @@ -1,481 +0,0 @@ - -rv64ui-p-sub: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00000093 li ra,0 - 80000100: 00000113 li sp,0 - 80000104: 40208f33 sub t5,ra,sp - 80000108: 00000e93 li t4,0 - 8000010c: 00200193 li gp,2 - 80000110: 4bdf1e63 bne t5,t4,800005cc - -0000000080000114 : - 80000114: 00100093 li ra,1 - 80000118: 00100113 li sp,1 - 8000011c: 40208f33 sub t5,ra,sp - 80000120: 00000e93 li t4,0 - 80000124: 00300193 li gp,3 - 80000128: 4bdf1263 bne t5,t4,800005cc - -000000008000012c : - 8000012c: 00300093 li ra,3 - 80000130: 00700113 li sp,7 - 80000134: 40208f33 sub t5,ra,sp - 80000138: ffc00e93 li t4,-4 - 8000013c: 00400193 li gp,4 - 80000140: 49df1663 bne t5,t4,800005cc - -0000000080000144 : - 80000144: 00000093 li ra,0 - 80000148: ffff8137 lui sp,0xffff8 - 8000014c: 40208f33 sub t5,ra,sp - 80000150: 00008eb7 lui t4,0x8 - 80000154: 00500193 li gp,5 - 80000158: 47df1a63 bne t5,t4,800005cc - -000000008000015c : - 8000015c: 800000b7 lui ra,0x80000 - 80000160: 00000113 li sp,0 - 80000164: 40208f33 sub t5,ra,sp - 80000168: 80000eb7 lui t4,0x80000 - 8000016c: 00600193 li gp,6 - 80000170: 45df1e63 bne t5,t4,800005cc - -0000000080000174 : - 80000174: 800000b7 lui ra,0x80000 - 80000178: ffff8137 lui sp,0xffff8 - 8000017c: 40208f33 sub t5,ra,sp - 80000180: 80008eb7 lui t4,0x80008 - 80000184: 00700193 li gp,7 - 80000188: 45df1263 bne t5,t4,800005cc - -000000008000018c : - 8000018c: 00000093 li ra,0 - 80000190: 00008137 lui sp,0x8 - 80000194: fff1011b addiw sp,sp,-1 - 80000198: 40208f33 sub t5,ra,sp - 8000019c: ffff8eb7 lui t4,0xffff8 - 800001a0: 001e8e9b addiw t4,t4,1 - 800001a4: 00800193 li gp,8 - 800001a8: 43df1263 bne t5,t4,800005cc - -00000000800001ac : - 800001ac: 800000b7 lui ra,0x80000 - 800001b0: fff0809b addiw ra,ra,-1 - 800001b4: 00000113 li sp,0 - 800001b8: 40208f33 sub t5,ra,sp - 800001bc: 80000eb7 lui t4,0x80000 - 800001c0: fffe8e9b addiw t4,t4,-1 - 800001c4: 00900193 li gp,9 - 800001c8: 41df1263 bne t5,t4,800005cc - -00000000800001cc : - 800001cc: 800000b7 lui ra,0x80000 - 800001d0: fff0809b addiw ra,ra,-1 - 800001d4: 00008137 lui sp,0x8 - 800001d8: fff1011b addiw sp,sp,-1 - 800001dc: 40208f33 sub t5,ra,sp - 800001e0: 7fff8eb7 lui t4,0x7fff8 - 800001e4: 00a00193 li gp,10 - 800001e8: 3fdf1263 bne t5,t4,800005cc - -00000000800001ec : - 800001ec: 800000b7 lui ra,0x80000 - 800001f0: 00008137 lui sp,0x8 - 800001f4: fff1011b addiw sp,sp,-1 - 800001f8: 40208f33 sub t5,ra,sp - 800001fc: ffff0eb7 lui t4,0xffff0 - 80000200: fffe8e9b addiw t4,t4,-1 - 80000204: 00fe9e93 slli t4,t4,0xf - 80000208: 001e8e93 addi t4,t4,1 # ffffffffffff0001 <_end+0xffffffff7ffee001> - 8000020c: 00b00193 li gp,11 - 80000210: 3bdf1e63 bne t5,t4,800005cc - -0000000080000214 : - 80000214: 800000b7 lui ra,0x80000 - 80000218: fff0809b addiw ra,ra,-1 - 8000021c: ffff8137 lui sp,0xffff8 - 80000220: 40208f33 sub t5,ra,sp - 80000224: 00010eb7 lui t4,0x10 - 80000228: 001e8e9b addiw t4,t4,1 - 8000022c: 00fe9e93 slli t4,t4,0xf - 80000230: fffe8e93 addi t4,t4,-1 # ffff <_start-0x7fff0001> - 80000234: 00c00193 li gp,12 - 80000238: 39df1a63 bne t5,t4,800005cc - -000000008000023c : - 8000023c: 00000093 li ra,0 - 80000240: fff00113 li sp,-1 - 80000244: 40208f33 sub t5,ra,sp - 80000248: 00100e93 li t4,1 - 8000024c: 00d00193 li gp,13 - 80000250: 37df1e63 bne t5,t4,800005cc - -0000000080000254 : - 80000254: fff00093 li ra,-1 - 80000258: 00100113 li sp,1 - 8000025c: 40208f33 sub t5,ra,sp - 80000260: ffe00e93 li t4,-2 - 80000264: 00e00193 li gp,14 - 80000268: 37df1263 bne t5,t4,800005cc - -000000008000026c : - 8000026c: fff00093 li ra,-1 - 80000270: fff00113 li sp,-1 - 80000274: 40208f33 sub t5,ra,sp - 80000278: 00000e93 li t4,0 - 8000027c: 00f00193 li gp,15 - 80000280: 35df1663 bne t5,t4,800005cc - -0000000080000284 : - 80000284: 00d00093 li ra,13 - 80000288: 00b00113 li sp,11 - 8000028c: 402080b3 sub ra,ra,sp - 80000290: 00200e93 li t4,2 - 80000294: 01000193 li gp,16 - 80000298: 33d09a63 bne ra,t4,800005cc - -000000008000029c : - 8000029c: 00e00093 li ra,14 - 800002a0: 00b00113 li sp,11 - 800002a4: 40208133 sub sp,ra,sp - 800002a8: 00300e93 li t4,3 - 800002ac: 01100193 li gp,17 - 800002b0: 31d11e63 bne sp,t4,800005cc - -00000000800002b4 : - 800002b4: 00d00093 li ra,13 - 800002b8: 401080b3 sub ra,ra,ra - 800002bc: 00000e93 li t4,0 - 800002c0: 01200193 li gp,18 - 800002c4: 31d09463 bne ra,t4,800005cc - -00000000800002c8 : - 800002c8: 00000213 li tp,0 - 800002cc: 00d00093 li ra,13 - 800002d0: 00b00113 li sp,11 - 800002d4: 40208f33 sub t5,ra,sp - 800002d8: 000f0313 mv t1,t5 - 800002dc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002e0: 00200293 li t0,2 - 800002e4: fe5214e3 bne tp,t0,800002cc - 800002e8: 00200e93 li t4,2 - 800002ec: 01300193 li gp,19 - 800002f0: 2dd31e63 bne t1,t4,800005cc - -00000000800002f4 : - 800002f4: 00000213 li tp,0 - 800002f8: 00e00093 li ra,14 - 800002fc: 00b00113 li sp,11 - 80000300: 40208f33 sub t5,ra,sp - 80000304: 00000013 nop - 80000308: 000f0313 mv t1,t5 - 8000030c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000310: 00200293 li t0,2 - 80000314: fe5212e3 bne tp,t0,800002f8 - 80000318: 00300e93 li t4,3 - 8000031c: 01400193 li gp,20 - 80000320: 2bd31663 bne t1,t4,800005cc - -0000000080000324 : - 80000324: 00000213 li tp,0 - 80000328: 00f00093 li ra,15 - 8000032c: 00b00113 li sp,11 - 80000330: 40208f33 sub t5,ra,sp - 80000334: 00000013 nop - 80000338: 00000013 nop - 8000033c: 000f0313 mv t1,t5 - 80000340: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000344: 00200293 li t0,2 - 80000348: fe5210e3 bne tp,t0,80000328 - 8000034c: 00400e93 li t4,4 - 80000350: 01500193 li gp,21 - 80000354: 27d31c63 bne t1,t4,800005cc - -0000000080000358 : - 80000358: 00000213 li tp,0 - 8000035c: 00d00093 li ra,13 - 80000360: 00b00113 li sp,11 - 80000364: 40208f33 sub t5,ra,sp - 80000368: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000036c: 00200293 li t0,2 - 80000370: fe5216e3 bne tp,t0,8000035c - 80000374: 00200e93 li t4,2 - 80000378: 01600193 li gp,22 - 8000037c: 25df1863 bne t5,t4,800005cc - -0000000080000380 : - 80000380: 00000213 li tp,0 - 80000384: 00e00093 li ra,14 - 80000388: 00b00113 li sp,11 - 8000038c: 00000013 nop - 80000390: 40208f33 sub t5,ra,sp - 80000394: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000398: 00200293 li t0,2 - 8000039c: fe5214e3 bne tp,t0,80000384 - 800003a0: 00300e93 li t4,3 - 800003a4: 01700193 li gp,23 - 800003a8: 23df1263 bne t5,t4,800005cc - -00000000800003ac : - 800003ac: 00000213 li tp,0 - 800003b0: 00f00093 li ra,15 - 800003b4: 00b00113 li sp,11 - 800003b8: 00000013 nop - 800003bc: 00000013 nop - 800003c0: 40208f33 sub t5,ra,sp - 800003c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003c8: 00200293 li t0,2 - 800003cc: fe5212e3 bne tp,t0,800003b0 - 800003d0: 00400e93 li t4,4 - 800003d4: 01800193 li gp,24 - 800003d8: 1fdf1a63 bne t5,t4,800005cc - -00000000800003dc : - 800003dc: 00000213 li tp,0 - 800003e0: 00d00093 li ra,13 - 800003e4: 00000013 nop - 800003e8: 00b00113 li sp,11 - 800003ec: 40208f33 sub t5,ra,sp - 800003f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003f4: 00200293 li t0,2 - 800003f8: fe5214e3 bne tp,t0,800003e0 - 800003fc: 00200e93 li t4,2 - 80000400: 01900193 li gp,25 - 80000404: 1ddf1463 bne t5,t4,800005cc - -0000000080000408 : - 80000408: 00000213 li tp,0 - 8000040c: 00e00093 li ra,14 - 80000410: 00000013 nop - 80000414: 00b00113 li sp,11 - 80000418: 00000013 nop - 8000041c: 40208f33 sub t5,ra,sp - 80000420: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000424: 00200293 li t0,2 - 80000428: fe5212e3 bne tp,t0,8000040c - 8000042c: 00300e93 li t4,3 - 80000430: 01a00193 li gp,26 - 80000434: 19df1c63 bne t5,t4,800005cc - -0000000080000438 : - 80000438: 00000213 li tp,0 - 8000043c: 00f00093 li ra,15 - 80000440: 00000013 nop - 80000444: 00000013 nop - 80000448: 00b00113 li sp,11 - 8000044c: 40208f33 sub t5,ra,sp - 80000450: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000454: 00200293 li t0,2 - 80000458: fe5212e3 bne tp,t0,8000043c - 8000045c: 00400e93 li t4,4 - 80000460: 01b00193 li gp,27 - 80000464: 17df1463 bne t5,t4,800005cc - -0000000080000468 : - 80000468: 00000213 li tp,0 - 8000046c: 00b00113 li sp,11 - 80000470: 00d00093 li ra,13 - 80000474: 40208f33 sub t5,ra,sp - 80000478: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000047c: 00200293 li t0,2 - 80000480: fe5216e3 bne tp,t0,8000046c - 80000484: 00200e93 li t4,2 - 80000488: 01c00193 li gp,28 - 8000048c: 15df1063 bne t5,t4,800005cc - -0000000080000490 : - 80000490: 00000213 li tp,0 - 80000494: 00b00113 li sp,11 - 80000498: 00e00093 li ra,14 - 8000049c: 00000013 nop - 800004a0: 40208f33 sub t5,ra,sp - 800004a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004a8: 00200293 li t0,2 - 800004ac: fe5214e3 bne tp,t0,80000494 - 800004b0: 00300e93 li t4,3 - 800004b4: 01d00193 li gp,29 - 800004b8: 11df1a63 bne t5,t4,800005cc - -00000000800004bc : - 800004bc: 00000213 li tp,0 - 800004c0: 00b00113 li sp,11 - 800004c4: 00f00093 li ra,15 - 800004c8: 00000013 nop - 800004cc: 00000013 nop - 800004d0: 40208f33 sub t5,ra,sp - 800004d4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004d8: 00200293 li t0,2 - 800004dc: fe5212e3 bne tp,t0,800004c0 - 800004e0: 00400e93 li t4,4 - 800004e4: 01e00193 li gp,30 - 800004e8: 0fdf1263 bne t5,t4,800005cc - -00000000800004ec : - 800004ec: 00000213 li tp,0 - 800004f0: 00b00113 li sp,11 - 800004f4: 00000013 nop - 800004f8: 00d00093 li ra,13 - 800004fc: 40208f33 sub t5,ra,sp - 80000500: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000504: 00200293 li t0,2 - 80000508: fe5214e3 bne tp,t0,800004f0 - 8000050c: 00200e93 li t4,2 - 80000510: 01f00193 li gp,31 - 80000514: 0bdf1c63 bne t5,t4,800005cc - -0000000080000518 : - 80000518: 00000213 li tp,0 - 8000051c: 00b00113 li sp,11 - 80000520: 00000013 nop - 80000524: 00e00093 li ra,14 - 80000528: 00000013 nop - 8000052c: 40208f33 sub t5,ra,sp - 80000530: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000534: 00200293 li t0,2 - 80000538: fe5212e3 bne tp,t0,8000051c - 8000053c: 00300e93 li t4,3 - 80000540: 02000193 li gp,32 - 80000544: 09df1463 bne t5,t4,800005cc - -0000000080000548 : - 80000548: 00000213 li tp,0 - 8000054c: 00b00113 li sp,11 - 80000550: 00000013 nop - 80000554: 00000013 nop - 80000558: 00f00093 li ra,15 - 8000055c: 40208f33 sub t5,ra,sp - 80000560: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000564: 00200293 li t0,2 - 80000568: fe5212e3 bne tp,t0,8000054c - 8000056c: 00400e93 li t4,4 - 80000570: 02100193 li gp,33 - 80000574: 05df1c63 bne t5,t4,800005cc - -0000000080000578 : - 80000578: ff100093 li ra,-15 - 8000057c: 40100133 neg sp,ra - 80000580: 00f00e93 li t4,15 - 80000584: 02200193 li gp,34 - 80000588: 05d11263 bne sp,t4,800005cc - -000000008000058c : - 8000058c: 02000093 li ra,32 - 80000590: 40008133 sub sp,ra,zero - 80000594: 02000e93 li t4,32 - 80000598: 02300193 li gp,35 - 8000059c: 03d11863 bne sp,t4,800005cc - -00000000800005a0 : - 800005a0: 400000b3 neg ra,zero - 800005a4: 00000e93 li t4,0 - 800005a8: 02400193 li gp,36 - 800005ac: 03d09063 bne ra,t4,800005cc - -00000000800005b0 : - 800005b0: 01000093 li ra,16 - 800005b4: 01e00113 li sp,30 - 800005b8: 40208033 sub zero,ra,sp - 800005bc: 00000e93 li t4,0 - 800005c0: 02500193 li gp,37 - 800005c4: 01d01463 bne zero,t4,800005cc - 800005c8: 00301c63 bne zero,gp,800005e0 - -00000000800005cc : - 800005cc: 0ff0000f fence - 800005d0: 00018063 beqz gp,800005d0 - 800005d4: 00119193 slli gp,gp,0x1 - 800005d8: 0011e193 ori gp,gp,1 - 800005dc: 00000073 ecall - -00000000800005e0 : - 800005e0: 0ff0000f fence - 800005e4: 00100193 li gp,1 - 800005e8: 00000073 ecall - 800005ec: c0001073 unimp - 800005f0: 0000 unimp - 800005f2: 0000 unimp - 800005f4: 0000 unimp - 800005f6: 0000 unimp - 800005f8: 0000 unimp - 800005fa: 0000 unimp - 800005fc: 0000 unimp - 800005fe: 0000 unimp - 80000600: 0000 unimp - 80000602: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-sub.elf b/test/riscv/tests/rv64ui-p-sub.elf deleted file mode 100644 index ea64efd5..00000000 Binary files a/test/riscv/tests/rv64ui-p-sub.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-subw.dump b/test/riscv/tests/rv64ui-p-subw.dump deleted file mode 100644 index 0a29bbfb..00000000 --- a/test/riscv/tests/rv64ui-p-subw.dump +++ /dev/null @@ -1,485 +0,0 @@ - -rv64ui-p-subw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00000093 li ra,0 - 80000100: 00000113 li sp,0 - 80000104: 40208f3b subw t5,ra,sp - 80000108: 00000e93 li t4,0 - 8000010c: 00200193 li gp,2 - 80000110: 4bdf1663 bne t5,t4,800005bc - -0000000080000114 : - 80000114: 00100093 li ra,1 - 80000118: 00100113 li sp,1 - 8000011c: 40208f3b subw t5,ra,sp - 80000120: 00000e93 li t4,0 - 80000124: 00300193 li gp,3 - 80000128: 49df1a63 bne t5,t4,800005bc - -000000008000012c : - 8000012c: 00300093 li ra,3 - 80000130: 00700113 li sp,7 - 80000134: 40208f3b subw t5,ra,sp - 80000138: ffc00e93 li t4,-4 - 8000013c: 00400193 li gp,4 - 80000140: 47df1e63 bne t5,t4,800005bc - -0000000080000144 : - 80000144: 00000093 li ra,0 - 80000148: ffff8137 lui sp,0xffff8 - 8000014c: 40208f3b subw t5,ra,sp - 80000150: 00008eb7 lui t4,0x8 - 80000154: 00500193 li gp,5 - 80000158: 47df1263 bne t5,t4,800005bc - -000000008000015c : - 8000015c: 800000b7 lui ra,0x80000 - 80000160: 00000113 li sp,0 - 80000164: 40208f3b subw t5,ra,sp - 80000168: 80000eb7 lui t4,0x80000 - 8000016c: 00600193 li gp,6 - 80000170: 45df1663 bne t5,t4,800005bc - -0000000080000174 : - 80000174: 800000b7 lui ra,0x80000 - 80000178: ffff8137 lui sp,0xffff8 - 8000017c: 40208f3b subw t5,ra,sp - 80000180: 80008eb7 lui t4,0x80008 - 80000184: 00700193 li gp,7 - 80000188: 43df1a63 bne t5,t4,800005bc - -000000008000018c : - 8000018c: 00000093 li ra,0 - 80000190: 00008137 lui sp,0x8 - 80000194: fff1011b addiw sp,sp,-1 - 80000198: 40208f3b subw t5,ra,sp - 8000019c: ffff8eb7 lui t4,0xffff8 - 800001a0: 001e8e9b addiw t4,t4,1 - 800001a4: 00800193 li gp,8 - 800001a8: 41df1a63 bne t5,t4,800005bc - -00000000800001ac : - 800001ac: 800000b7 lui ra,0x80000 - 800001b0: fff0809b addiw ra,ra,-1 - 800001b4: 00000113 li sp,0 - 800001b8: 40208f3b subw t5,ra,sp - 800001bc: 80000eb7 lui t4,0x80000 - 800001c0: fffe8e9b addiw t4,t4,-1 - 800001c4: 00900193 li gp,9 - 800001c8: 3fdf1a63 bne t5,t4,800005bc - -00000000800001cc : - 800001cc: 800000b7 lui ra,0x80000 - 800001d0: fff0809b addiw ra,ra,-1 - 800001d4: 00008137 lui sp,0x8 - 800001d8: fff1011b addiw sp,sp,-1 - 800001dc: 40208f3b subw t5,ra,sp - 800001e0: 7fff8eb7 lui t4,0x7fff8 - 800001e4: 00a00193 li gp,10 - 800001e8: 3ddf1a63 bne t5,t4,800005bc - -00000000800001ec : - 800001ec: 800000b7 lui ra,0x80000 - 800001f0: 00008137 lui sp,0x8 - 800001f4: fff1011b addiw sp,sp,-1 - 800001f8: 40208f3b subw t5,ra,sp - 800001fc: 7fff8eb7 lui t4,0x7fff8 - 80000200: 001e8e9b addiw t4,t4,1 - 80000204: 00b00193 li gp,11 - 80000208: 3bdf1a63 bne t5,t4,800005bc - -000000008000020c : - 8000020c: 800000b7 lui ra,0x80000 - 80000210: fff0809b addiw ra,ra,-1 - 80000214: ffff8137 lui sp,0xffff8 - 80000218: 40208f3b subw t5,ra,sp - 8000021c: 80008eb7 lui t4,0x80008 - 80000220: fffe8e9b addiw t4,t4,-1 - 80000224: 00c00193 li gp,12 - 80000228: 39df1a63 bne t5,t4,800005bc - -000000008000022c : - 8000022c: 00000093 li ra,0 - 80000230: fff00113 li sp,-1 - 80000234: 40208f3b subw t5,ra,sp - 80000238: 00100e93 li t4,1 - 8000023c: 00d00193 li gp,13 - 80000240: 37df1e63 bne t5,t4,800005bc - -0000000080000244 : - 80000244: fff00093 li ra,-1 - 80000248: 00100113 li sp,1 - 8000024c: 40208f3b subw t5,ra,sp - 80000250: ffe00e93 li t4,-2 - 80000254: 00e00193 li gp,14 - 80000258: 37df1263 bne t5,t4,800005bc - -000000008000025c : - 8000025c: fff00093 li ra,-1 - 80000260: fff00113 li sp,-1 - 80000264: 40208f3b subw t5,ra,sp - 80000268: 00000e93 li t4,0 - 8000026c: 00f00193 li gp,15 - 80000270: 35df1663 bne t5,t4,800005bc - -0000000080000274 : - 80000274: 00d00093 li ra,13 - 80000278: 00b00113 li sp,11 - 8000027c: 402080bb subw ra,ra,sp - 80000280: 00200e93 li t4,2 - 80000284: 01000193 li gp,16 - 80000288: 33d09a63 bne ra,t4,800005bc - -000000008000028c : - 8000028c: 00e00093 li ra,14 - 80000290: 00b00113 li sp,11 - 80000294: 4020813b subw sp,ra,sp - 80000298: 00300e93 li t4,3 - 8000029c: 01100193 li gp,17 - 800002a0: 31d11e63 bne sp,t4,800005bc - -00000000800002a4 : - 800002a4: 00d00093 li ra,13 - 800002a8: 401080bb subw ra,ra,ra - 800002ac: 00000e93 li t4,0 - 800002b0: 01200193 li gp,18 - 800002b4: 31d09463 bne ra,t4,800005bc - -00000000800002b8 : - 800002b8: 00000213 li tp,0 - 800002bc: 00d00093 li ra,13 - 800002c0: 00b00113 li sp,11 - 800002c4: 40208f3b subw t5,ra,sp - 800002c8: 000f0313 mv t1,t5 - 800002cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002d0: 00200293 li t0,2 - 800002d4: fe5214e3 bne tp,t0,800002bc - 800002d8: 00200e93 li t4,2 - 800002dc: 01300193 li gp,19 - 800002e0: 2dd31e63 bne t1,t4,800005bc - -00000000800002e4 : - 800002e4: 00000213 li tp,0 - 800002e8: 00e00093 li ra,14 - 800002ec: 00b00113 li sp,11 - 800002f0: 40208f3b subw t5,ra,sp - 800002f4: 00000013 nop - 800002f8: 000f0313 mv t1,t5 - 800002fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000300: 00200293 li t0,2 - 80000304: fe5212e3 bne tp,t0,800002e8 - 80000308: 00300e93 li t4,3 - 8000030c: 01400193 li gp,20 - 80000310: 2bd31663 bne t1,t4,800005bc - -0000000080000314 : - 80000314: 00000213 li tp,0 - 80000318: 00f00093 li ra,15 - 8000031c: 00b00113 li sp,11 - 80000320: 40208f3b subw t5,ra,sp - 80000324: 00000013 nop - 80000328: 00000013 nop - 8000032c: 000f0313 mv t1,t5 - 80000330: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000334: 00200293 li t0,2 - 80000338: fe5210e3 bne tp,t0,80000318 - 8000033c: 00400e93 li t4,4 - 80000340: 01500193 li gp,21 - 80000344: 27d31c63 bne t1,t4,800005bc - -0000000080000348 : - 80000348: 00000213 li tp,0 - 8000034c: 00d00093 li ra,13 - 80000350: 00b00113 li sp,11 - 80000354: 40208f3b subw t5,ra,sp - 80000358: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000035c: 00200293 li t0,2 - 80000360: fe5216e3 bne tp,t0,8000034c - 80000364: 00200e93 li t4,2 - 80000368: 01600193 li gp,22 - 8000036c: 25df1863 bne t5,t4,800005bc - -0000000080000370 : - 80000370: 00000213 li tp,0 - 80000374: 00e00093 li ra,14 - 80000378: 00b00113 li sp,11 - 8000037c: 00000013 nop - 80000380: 40208f3b subw t5,ra,sp - 80000384: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000388: 00200293 li t0,2 - 8000038c: fe5214e3 bne tp,t0,80000374 - 80000390: 00300e93 li t4,3 - 80000394: 01700193 li gp,23 - 80000398: 23df1263 bne t5,t4,800005bc - -000000008000039c : - 8000039c: 00000213 li tp,0 - 800003a0: 00f00093 li ra,15 - 800003a4: 00b00113 li sp,11 - 800003a8: 00000013 nop - 800003ac: 00000013 nop - 800003b0: 40208f3b subw t5,ra,sp - 800003b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003b8: 00200293 li t0,2 - 800003bc: fe5212e3 bne tp,t0,800003a0 - 800003c0: 00400e93 li t4,4 - 800003c4: 01800193 li gp,24 - 800003c8: 1fdf1a63 bne t5,t4,800005bc - -00000000800003cc : - 800003cc: 00000213 li tp,0 - 800003d0: 00d00093 li ra,13 - 800003d4: 00000013 nop - 800003d8: 00b00113 li sp,11 - 800003dc: 40208f3b subw t5,ra,sp - 800003e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003e4: 00200293 li t0,2 - 800003e8: fe5214e3 bne tp,t0,800003d0 - 800003ec: 00200e93 li t4,2 - 800003f0: 01900193 li gp,25 - 800003f4: 1ddf1463 bne t5,t4,800005bc - -00000000800003f8 : - 800003f8: 00000213 li tp,0 - 800003fc: 00e00093 li ra,14 - 80000400: 00000013 nop - 80000404: 00b00113 li sp,11 - 80000408: 00000013 nop - 8000040c: 40208f3b subw t5,ra,sp - 80000410: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000414: 00200293 li t0,2 - 80000418: fe5212e3 bne tp,t0,800003fc - 8000041c: 00300e93 li t4,3 - 80000420: 01a00193 li gp,26 - 80000424: 19df1c63 bne t5,t4,800005bc - -0000000080000428 : - 80000428: 00000213 li tp,0 - 8000042c: 00f00093 li ra,15 - 80000430: 00000013 nop - 80000434: 00000013 nop - 80000438: 00b00113 li sp,11 - 8000043c: 40208f3b subw t5,ra,sp - 80000440: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000444: 00200293 li t0,2 - 80000448: fe5212e3 bne tp,t0,8000042c - 8000044c: 00400e93 li t4,4 - 80000450: 01b00193 li gp,27 - 80000454: 17df1463 bne t5,t4,800005bc - -0000000080000458 : - 80000458: 00000213 li tp,0 - 8000045c: 00b00113 li sp,11 - 80000460: 00d00093 li ra,13 - 80000464: 40208f3b subw t5,ra,sp - 80000468: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000046c: 00200293 li t0,2 - 80000470: fe5216e3 bne tp,t0,8000045c - 80000474: 00200e93 li t4,2 - 80000478: 01c00193 li gp,28 - 8000047c: 15df1063 bne t5,t4,800005bc - -0000000080000480 : - 80000480: 00000213 li tp,0 - 80000484: 00b00113 li sp,11 - 80000488: 00e00093 li ra,14 - 8000048c: 00000013 nop - 80000490: 40208f3b subw t5,ra,sp - 80000494: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000498: 00200293 li t0,2 - 8000049c: fe5214e3 bne tp,t0,80000484 - 800004a0: 00300e93 li t4,3 - 800004a4: 01d00193 li gp,29 - 800004a8: 11df1a63 bne t5,t4,800005bc - -00000000800004ac : - 800004ac: 00000213 li tp,0 - 800004b0: 00b00113 li sp,11 - 800004b4: 00f00093 li ra,15 - 800004b8: 00000013 nop - 800004bc: 00000013 nop - 800004c0: 40208f3b subw t5,ra,sp - 800004c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004c8: 00200293 li t0,2 - 800004cc: fe5212e3 bne tp,t0,800004b0 - 800004d0: 00400e93 li t4,4 - 800004d4: 01e00193 li gp,30 - 800004d8: 0fdf1263 bne t5,t4,800005bc - -00000000800004dc : - 800004dc: 00000213 li tp,0 - 800004e0: 00b00113 li sp,11 - 800004e4: 00000013 nop - 800004e8: 00d00093 li ra,13 - 800004ec: 40208f3b subw t5,ra,sp - 800004f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004f4: 00200293 li t0,2 - 800004f8: fe5214e3 bne tp,t0,800004e0 - 800004fc: 00200e93 li t4,2 - 80000500: 01f00193 li gp,31 - 80000504: 0bdf1c63 bne t5,t4,800005bc - -0000000080000508 : - 80000508: 00000213 li tp,0 - 8000050c: 00b00113 li sp,11 - 80000510: 00000013 nop - 80000514: 00e00093 li ra,14 - 80000518: 00000013 nop - 8000051c: 40208f3b subw t5,ra,sp - 80000520: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000524: 00200293 li t0,2 - 80000528: fe5212e3 bne tp,t0,8000050c - 8000052c: 00300e93 li t4,3 - 80000530: 02000193 li gp,32 - 80000534: 09df1463 bne t5,t4,800005bc - -0000000080000538 : - 80000538: 00000213 li tp,0 - 8000053c: 00b00113 li sp,11 - 80000540: 00000013 nop - 80000544: 00000013 nop - 80000548: 00f00093 li ra,15 - 8000054c: 40208f3b subw t5,ra,sp - 80000550: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000554: 00200293 li t0,2 - 80000558: fe5212e3 bne tp,t0,8000053c - 8000055c: 00400e93 li t4,4 - 80000560: 02100193 li gp,33 - 80000564: 05df1c63 bne t5,t4,800005bc - -0000000080000568 : - 80000568: ff100093 li ra,-15 - 8000056c: 4010013b negw sp,ra - 80000570: 00f00e93 li t4,15 - 80000574: 02200193 li gp,34 - 80000578: 05d11263 bne sp,t4,800005bc - -000000008000057c : - 8000057c: 02000093 li ra,32 - 80000580: 4000813b subw sp,ra,zero - 80000584: 02000e93 li t4,32 - 80000588: 02300193 li gp,35 - 8000058c: 03d11863 bne sp,t4,800005bc - -0000000080000590 : - 80000590: 400000bb negw ra,zero - 80000594: 00000e93 li t4,0 - 80000598: 02400193 li gp,36 - 8000059c: 03d09063 bne ra,t4,800005bc - -00000000800005a0 : - 800005a0: 01000093 li ra,16 - 800005a4: 01e00113 li sp,30 - 800005a8: 4020803b subw zero,ra,sp - 800005ac: 00000e93 li t4,0 - 800005b0: 02500193 li gp,37 - 800005b4: 01d01463 bne zero,t4,800005bc - 800005b8: 00301c63 bne zero,gp,800005d0 - -00000000800005bc : - 800005bc: 0ff0000f fence - 800005c0: 00018063 beqz gp,800005c0 - 800005c4: 00119193 slli gp,gp,0x1 - 800005c8: 0011e193 ori gp,gp,1 - 800005cc: 00000073 ecall - -00000000800005d0 : - 800005d0: 0ff0000f fence - 800005d4: 00100193 li gp,1 - 800005d8: 00000073 ecall - 800005dc: c0001073 unimp - 800005e0: 0000 unimp - 800005e2: 0000 unimp - 800005e4: 0000 unimp - 800005e6: 0000 unimp - 800005e8: 0000 unimp - 800005ea: 0000 unimp - 800005ec: 0000 unimp - 800005ee: 0000 unimp - 800005f0: 0000 unimp - 800005f2: 0000 unimp - 800005f4: 0000 unimp - 800005f6: 0000 unimp - 800005f8: 0000 unimp - 800005fa: 0000 unimp - 800005fc: 0000 unimp - 800005fe: 0000 unimp - 80000600: 0000 unimp - 80000602: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-subw.elf b/test/riscv/tests/rv64ui-p-subw.elf deleted file mode 100644 index fd876f50..00000000 Binary files a/test/riscv/tests/rv64ui-p-subw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-sw.dump b/test/riscv/tests/rv64ui-p-sw.dump deleted file mode 100644 index a80b9958..00000000 --- a/test/riscv/tests/rv64ui-p-sw.dump +++ /dev/null @@ -1,476 +0,0 @@ - -rv64ui-p-sw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00002097 auipc ra,0x2 - 80000100: f0408093 addi ra,ra,-252 # 80002000 - 80000104: 00aa0137 lui sp,0xaa0 - 80000108: 0aa1011b addiw sp,sp,170 - 8000010c: 0020a023 sw sp,0(ra) - 80000110: 0000af03 lw t5,0(ra) - 80000114: 00aa0eb7 lui t4,0xaa0 - 80000118: 0aae8e9b addiw t4,t4,170 - 8000011c: 00200193 li gp,2 - 80000120: 47df1063 bne t5,t4,80000580 - -0000000080000124 : - 80000124: 00002097 auipc ra,0x2 - 80000128: edc08093 addi ra,ra,-292 # 80002000 - 8000012c: aa00b137 lui sp,0xaa00b - 80000130: a001011b addiw sp,sp,-1536 - 80000134: 0020a223 sw sp,4(ra) - 80000138: 0040af03 lw t5,4(ra) - 8000013c: aa00beb7 lui t4,0xaa00b - 80000140: a00e8e9b addiw t4,t4,-1536 - 80000144: 00300193 li gp,3 - 80000148: 43df1c63 bne t5,t4,80000580 - -000000008000014c : - 8000014c: 00002097 auipc ra,0x2 - 80000150: eb408093 addi ra,ra,-332 # 80002000 - 80000154: 0aa01137 lui sp,0xaa01 - 80000158: aa01011b addiw sp,sp,-1376 - 8000015c: 0020a423 sw sp,8(ra) - 80000160: 0080af03 lw t5,8(ra) - 80000164: 0aa01eb7 lui t4,0xaa01 - 80000168: aa0e8e9b addiw t4,t4,-1376 - 8000016c: 00400193 li gp,4 - 80000170: 41df1863 bne t5,t4,80000580 - -0000000080000174 : - 80000174: 00002097 auipc ra,0x2 - 80000178: e8c08093 addi ra,ra,-372 # 80002000 - 8000017c: a00aa137 lui sp,0xa00aa - 80000180: 00a1011b addiw sp,sp,10 - 80000184: 0020a623 sw sp,12(ra) - 80000188: 00c0af03 lw t5,12(ra) - 8000018c: a00aaeb7 lui t4,0xa00aa - 80000190: 00ae8e9b addiw t4,t4,10 - 80000194: 00500193 li gp,5 - 80000198: 3fdf1463 bne t5,t4,80000580 - -000000008000019c : - 8000019c: 00002097 auipc ra,0x2 - 800001a0: e8008093 addi ra,ra,-384 # 8000201c - 800001a4: 00aa0137 lui sp,0xaa0 - 800001a8: 0aa1011b addiw sp,sp,170 - 800001ac: fe20aa23 sw sp,-12(ra) - 800001b0: ff40af03 lw t5,-12(ra) - 800001b4: 00aa0eb7 lui t4,0xaa0 - 800001b8: 0aae8e9b addiw t4,t4,170 - 800001bc: 00600193 li gp,6 - 800001c0: 3ddf1063 bne t5,t4,80000580 - -00000000800001c4 : - 800001c4: 00002097 auipc ra,0x2 - 800001c8: e5808093 addi ra,ra,-424 # 8000201c - 800001cc: aa00b137 lui sp,0xaa00b - 800001d0: a001011b addiw sp,sp,-1536 - 800001d4: fe20ac23 sw sp,-8(ra) - 800001d8: ff80af03 lw t5,-8(ra) - 800001dc: aa00beb7 lui t4,0xaa00b - 800001e0: a00e8e9b addiw t4,t4,-1536 - 800001e4: 00700193 li gp,7 - 800001e8: 39df1c63 bne t5,t4,80000580 - -00000000800001ec : - 800001ec: 00002097 auipc ra,0x2 - 800001f0: e3008093 addi ra,ra,-464 # 8000201c - 800001f4: 0aa01137 lui sp,0xaa01 - 800001f8: aa01011b addiw sp,sp,-1376 - 800001fc: fe20ae23 sw sp,-4(ra) - 80000200: ffc0af03 lw t5,-4(ra) - 80000204: 0aa01eb7 lui t4,0xaa01 - 80000208: aa0e8e9b addiw t4,t4,-1376 - 8000020c: 00800193 li gp,8 - 80000210: 37df1863 bne t5,t4,80000580 - -0000000080000214 : - 80000214: 00002097 auipc ra,0x2 - 80000218: e0808093 addi ra,ra,-504 # 8000201c - 8000021c: a00aa137 lui sp,0xa00aa - 80000220: 00a1011b addiw sp,sp,10 - 80000224: 0020a023 sw sp,0(ra) - 80000228: 0000af03 lw t5,0(ra) - 8000022c: a00aaeb7 lui t4,0xa00aa - 80000230: 00ae8e9b addiw t4,t4,10 - 80000234: 00900193 li gp,9 - 80000238: 35df1463 bne t5,t4,80000580 - -000000008000023c : - 8000023c: 00002097 auipc ra,0x2 - 80000240: de408093 addi ra,ra,-540 # 80002020 - 80000244: 12345137 lui sp,0x12345 - 80000248: 6781011b addiw sp,sp,1656 - 8000024c: fe008213 addi tp,ra,-32 - 80000250: 02222023 sw sp,32(tp) # 20 <_start-0x7fffffe0> - 80000254: 0000a283 lw t0,0(ra) - 80000258: 12345eb7 lui t4,0x12345 - 8000025c: 678e8e9b addiw t4,t4,1656 - 80000260: 00a00193 li gp,10 - 80000264: 31d29e63 bne t0,t4,80000580 - -0000000080000268 : - 80000268: 00002097 auipc ra,0x2 - 8000026c: db808093 addi ra,ra,-584 # 80002020 - 80000270: 58213137 lui sp,0x58213 - 80000274: 0981011b addiw sp,sp,152 - 80000278: ffd08093 addi ra,ra,-3 - 8000027c: 0020a3a3 sw sp,7(ra) - 80000280: 00002217 auipc tp,0x2 - 80000284: da420213 addi tp,tp,-604 # 80002024 - 80000288: 00022283 lw t0,0(tp) # 0 <_start-0x80000000> - 8000028c: 58213eb7 lui t4,0x58213 - 80000290: 098e8e9b addiw t4,t4,152 - 80000294: 00b00193 li gp,11 - 80000298: 2fd29463 bne t0,t4,80000580 - -000000008000029c : - 8000029c: 00c00193 li gp,12 - 800002a0: 00000213 li tp,0 - 800002a4: aabbd0b7 lui ra,0xaabbd - 800002a8: cdd0809b addiw ra,ra,-803 - 800002ac: 00002117 auipc sp,0x2 - 800002b0: d5410113 addi sp,sp,-684 # 80002000 - 800002b4: 00112023 sw ra,0(sp) - 800002b8: 00012f03 lw t5,0(sp) - 800002bc: aabbdeb7 lui t4,0xaabbd - 800002c0: cdde8e9b addiw t4,t4,-803 - 800002c4: 2bdf1e63 bne t5,t4,80000580 - 800002c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002cc: 00200293 li t0,2 - 800002d0: fc521ae3 bne tp,t0,800002a4 - -00000000800002d4 : - 800002d4: 00d00193 li gp,13 - 800002d8: 00000213 li tp,0 - 800002dc: daabc0b7 lui ra,0xdaabc - 800002e0: ccd0809b addiw ra,ra,-819 - 800002e4: 00002117 auipc sp,0x2 - 800002e8: d1c10113 addi sp,sp,-740 # 80002000 - 800002ec: 00000013 nop - 800002f0: 00112223 sw ra,4(sp) - 800002f4: 00412f03 lw t5,4(sp) - 800002f8: daabceb7 lui t4,0xdaabc - 800002fc: ccde8e9b addiw t4,t4,-819 - 80000300: 29df1063 bne t5,t4,80000580 - 80000304: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000308: 00200293 li t0,2 - 8000030c: fc5218e3 bne tp,t0,800002dc - -0000000080000310 : - 80000310: 00e00193 li gp,14 - 80000314: 00000213 li tp,0 - 80000318: ddaac0b7 lui ra,0xddaac - 8000031c: bcc0809b addiw ra,ra,-1076 - 80000320: 00002117 auipc sp,0x2 - 80000324: ce010113 addi sp,sp,-800 # 80002000 - 80000328: 00000013 nop - 8000032c: 00000013 nop - 80000330: 00112423 sw ra,8(sp) - 80000334: 00812f03 lw t5,8(sp) - 80000338: ddaaceb7 lui t4,0xddaac - 8000033c: bcce8e9b addiw t4,t4,-1076 - 80000340: 25df1063 bne t5,t4,80000580 - 80000344: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000348: 00200293 li t0,2 - 8000034c: fc5216e3 bne tp,t0,80000318 - -0000000080000350 : - 80000350: 00f00193 li gp,15 - 80000354: 00000213 li tp,0 - 80000358: cddab0b7 lui ra,0xcddab - 8000035c: bbc0809b addiw ra,ra,-1092 - 80000360: 00000013 nop - 80000364: 00002117 auipc sp,0x2 - 80000368: c9c10113 addi sp,sp,-868 # 80002000 - 8000036c: 00112623 sw ra,12(sp) - 80000370: 00c12f03 lw t5,12(sp) - 80000374: cddabeb7 lui t4,0xcddab - 80000378: bbce8e9b addiw t4,t4,-1092 - 8000037c: 21df1263 bne t5,t4,80000580 - 80000380: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000384: 00200293 li t0,2 - 80000388: fc5218e3 bne tp,t0,80000358 - -000000008000038c : - 8000038c: 01000193 li gp,16 - 80000390: 00000213 li tp,0 - 80000394: ccddb0b7 lui ra,0xccddb - 80000398: abb0809b addiw ra,ra,-1349 - 8000039c: 00000013 nop - 800003a0: 00002117 auipc sp,0x2 - 800003a4: c6010113 addi sp,sp,-928 # 80002000 - 800003a8: 00000013 nop - 800003ac: 00112823 sw ra,16(sp) - 800003b0: 01012f03 lw t5,16(sp) - 800003b4: ccddbeb7 lui t4,0xccddb - 800003b8: abbe8e9b addiw t4,t4,-1349 - 800003bc: 1ddf1263 bne t5,t4,80000580 - 800003c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003c4: 00200293 li t0,2 - 800003c8: fc5216e3 bne tp,t0,80000394 - -00000000800003cc : - 800003cc: 01100193 li gp,17 - 800003d0: 00000213 li tp,0 - 800003d4: bccde0b7 lui ra,0xbccde - 800003d8: aab0809b addiw ra,ra,-1365 - 800003dc: 00000013 nop - 800003e0: 00000013 nop - 800003e4: 00002117 auipc sp,0x2 - 800003e8: c1c10113 addi sp,sp,-996 # 80002000 - 800003ec: 00112a23 sw ra,20(sp) - 800003f0: 01412f03 lw t5,20(sp) - 800003f4: bccdeeb7 lui t4,0xbccde - 800003f8: aabe8e9b addiw t4,t4,-1365 - 800003fc: 19df1263 bne t5,t4,80000580 - 80000400: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000404: 00200293 li t0,2 - 80000408: fc5216e3 bne tp,t0,800003d4 - -000000008000040c : - 8000040c: 01200193 li gp,18 - 80000410: 00000213 li tp,0 - 80000414: 00002117 auipc sp,0x2 - 80000418: bec10113 addi sp,sp,-1044 # 80002000 - 8000041c: 001120b7 lui ra,0x112 - 80000420: 2330809b addiw ra,ra,563 - 80000424: 00112023 sw ra,0(sp) - 80000428: 00012f03 lw t5,0(sp) - 8000042c: 00112eb7 lui t4,0x112 - 80000430: 233e8e9b addiw t4,t4,563 - 80000434: 15df1663 bne t5,t4,80000580 - 80000438: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000043c: 00200293 li t0,2 - 80000440: fc521ae3 bne tp,t0,80000414 - -0000000080000444 : - 80000444: 01300193 li gp,19 - 80000448: 00000213 li tp,0 - 8000044c: 00002117 auipc sp,0x2 - 80000450: bb410113 addi sp,sp,-1100 # 80002000 - 80000454: 300110b7 lui ra,0x30011 - 80000458: 2230809b addiw ra,ra,547 - 8000045c: 00000013 nop - 80000460: 00112223 sw ra,4(sp) - 80000464: 00412f03 lw t5,4(sp) - 80000468: 30011eb7 lui t4,0x30011 - 8000046c: 223e8e9b addiw t4,t4,547 - 80000470: 11df1863 bne t5,t4,80000580 - 80000474: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000478: 00200293 li t0,2 - 8000047c: fc5218e3 bne tp,t0,8000044c - -0000000080000480 : - 80000480: 01400193 li gp,20 - 80000484: 00000213 li tp,0 - 80000488: 00002117 auipc sp,0x2 - 8000048c: b7810113 addi sp,sp,-1160 # 80002000 - 80000490: 330010b7 lui ra,0x33001 - 80000494: 1220809b addiw ra,ra,290 - 80000498: 00000013 nop - 8000049c: 00000013 nop - 800004a0: 00112423 sw ra,8(sp) - 800004a4: 00812f03 lw t5,8(sp) - 800004a8: 33001eb7 lui t4,0x33001 - 800004ac: 122e8e9b addiw t4,t4,290 - 800004b0: 0ddf1863 bne t5,t4,80000580 - 800004b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004b8: 00200293 li t0,2 - 800004bc: fc5216e3 bne tp,t0,80000488 - -00000000800004c0 : - 800004c0: 01500193 li gp,21 - 800004c4: 00000213 li tp,0 - 800004c8: 00002117 auipc sp,0x2 - 800004cc: b3810113 addi sp,sp,-1224 # 80002000 - 800004d0: 00000013 nop - 800004d4: 233000b7 lui ra,0x23300 - 800004d8: 1120809b addiw ra,ra,274 - 800004dc: 00112623 sw ra,12(sp) - 800004e0: 00c12f03 lw t5,12(sp) - 800004e4: 23300eb7 lui t4,0x23300 - 800004e8: 112e8e9b addiw t4,t4,274 - 800004ec: 09df1a63 bne t5,t4,80000580 - 800004f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004f4: 00200293 li t0,2 - 800004f8: fc5218e3 bne tp,t0,800004c8 - -00000000800004fc : - 800004fc: 01600193 li gp,22 - 80000500: 00000213 li tp,0 - 80000504: 00002117 auipc sp,0x2 - 80000508: afc10113 addi sp,sp,-1284 # 80002000 - 8000050c: 00000013 nop - 80000510: 223300b7 lui ra,0x22330 - 80000514: 0110809b addiw ra,ra,17 - 80000518: 00000013 nop - 8000051c: 00112823 sw ra,16(sp) - 80000520: 01012f03 lw t5,16(sp) - 80000524: 22330eb7 lui t4,0x22330 - 80000528: 011e8e9b addiw t4,t4,17 - 8000052c: 05df1a63 bne t5,t4,80000580 - 80000530: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000534: 00200293 li t0,2 - 80000538: fc5216e3 bne tp,t0,80000504 - -000000008000053c : - 8000053c: 01700193 li gp,23 - 80000540: 00000213 li tp,0 - 80000544: 00002117 auipc sp,0x2 - 80000548: abc10113 addi sp,sp,-1348 # 80002000 - 8000054c: 00000013 nop - 80000550: 00000013 nop - 80000554: 122330b7 lui ra,0x12233 - 80000558: 0010809b addiw ra,ra,1 - 8000055c: 00112a23 sw ra,20(sp) - 80000560: 01412f03 lw t5,20(sp) - 80000564: 12233eb7 lui t4,0x12233 - 80000568: 001e8e9b addiw t4,t4,1 - 8000056c: 01df1a63 bne t5,t4,80000580 - 80000570: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000574: 00200293 li t0,2 - 80000578: fc5216e3 bne tp,t0,80000544 - 8000057c: 00301c63 bne zero,gp,80000594 - -0000000080000580 : - 80000580: 0ff0000f fence - 80000584: 00018063 beqz gp,80000584 - 80000588: 00119193 slli gp,gp,0x1 - 8000058c: 0011e193 ori gp,gp,1 - 80000590: 00000073 ecall - -0000000080000594 : - 80000594: 0ff0000f fence - 80000598: 00100193 li gp,1 - 8000059c: 00000073 ecall - 800005a0: c0001073 unimp - 800005a4: 0000 unimp - 800005a6: 0000 unimp - 800005a8: 0000 unimp - 800005aa: 0000 unimp - 800005ac: 0000 unimp - 800005ae: 0000 unimp - 800005b0: 0000 unimp - 800005b2: 0000 unimp - 800005b4: 0000 unimp - 800005b6: 0000 unimp - 800005b8: 0000 unimp - 800005ba: 0000 unimp - 800005bc: 0000 unimp - 800005be: 0000 unimp - 800005c0: 0000 unimp - 800005c2: 0000 unimp - -Disassembly of section .data: - -0000000080002000 : - 80002000: deadbeef jal t4,7ffdd5ea <_start-0x22a16> - -0000000080002004 : - 80002004: deadbeef jal t4,7ffdd5ee <_start-0x22a12> - -0000000080002008 : - 80002008: deadbeef jal t4,7ffdd5f2 <_start-0x22a0e> - -000000008000200c : - 8000200c: deadbeef jal t4,7ffdd5f6 <_start-0x22a0a> - -0000000080002010 : - 80002010: deadbeef jal t4,7ffdd5fa <_start-0x22a06> - -0000000080002014 : - 80002014: deadbeef jal t4,7ffdd5fe <_start-0x22a02> - -0000000080002018 : - 80002018: deadbeef jal t4,7ffdd602 <_start-0x229fe> - -000000008000201c : - 8000201c: deadbeef jal t4,7ffdd606 <_start-0x229fa> - -0000000080002020 : - 80002020: deadbeef jal t4,7ffdd60a <_start-0x229f6> - -0000000080002024 : - 80002024: deadbeef jal t4,7ffdd60e <_start-0x229f2> - 80002028: 0000 unimp - 8000202a: 0000 unimp - 8000202c: 0000 unimp - 8000202e: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-sw.elf b/test/riscv/tests/rv64ui-p-sw.elf deleted file mode 100644 index fa60dda4..00000000 Binary files a/test/riscv/tests/rv64ui-p-sw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-xor.dump b/test/riscv/tests/rv64ui-p-xor.dump deleted file mode 100644 index 2f6d21b3..00000000 --- a/test/riscv/tests/rv64ui-p-xor.dump +++ /dev/null @@ -1,527 +0,0 @@ - -rv64ui-p-xor: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 000100b7 lui ra,0x10 - 80000100: f010809b addiw ra,ra,-255 - 80000104: 01009093 slli ra,ra,0x10 - 80000108: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 8000010c: 0f0f1137 lui sp,0xf0f1 - 80000110: f0f1011b addiw sp,sp,-241 - 80000114: 0020cf33 xor t5,ra,sp - 80000118: 000f0eb7 lui t4,0xf0 - 8000011c: 0ffe8e9b addiw t4,t4,255 - 80000120: 00ce9e93 slli t4,t4,0xc - 80000124: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 80000128: 00200193 li gp,2 - 8000012c: 59df1c63 bne t5,t4,800006c4 - -0000000080000130 : - 80000130: 0ff010b7 lui ra,0xff01 - 80000134: ff00809b addiw ra,ra,-16 - 80000138: 000f1137 lui sp,0xf1 - 8000013c: f0f1011b addiw sp,sp,-241 - 80000140: 00c11113 slli sp,sp,0xc - 80000144: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80000148: 0020cf33 xor t5,ra,sp - 8000014c: 00010eb7 lui t4,0x10 - 80000150: f01e8e9b addiw t4,t4,-255 - 80000154: 010e9e93 slli t4,t4,0x10 - 80000158: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 8000015c: 00300193 li gp,3 - 80000160: 57df1263 bne t5,t4,800006c4 - -0000000080000164 : - 80000164: 00ff00b7 lui ra,0xff0 - 80000168: 0ff0809b addiw ra,ra,255 - 8000016c: 0f0f1137 lui sp,0xf0f1 - 80000170: f0f1011b addiw sp,sp,-241 - 80000174: 0020cf33 xor t5,ra,sp - 80000178: 0ff01eb7 lui t4,0xff01 - 8000017c: ff0e8e9b addiw t4,t4,-16 - 80000180: 00400193 li gp,4 - 80000184: 55df1063 bne t5,t4,800006c4 - -0000000080000188 : - 80000188: 000f00b7 lui ra,0xf0 - 8000018c: 0ff0809b addiw ra,ra,255 - 80000190: 00c09093 slli ra,ra,0xc - 80000194: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> - 80000198: 000f1137 lui sp,0xf1 - 8000019c: f0f1011b addiw sp,sp,-241 - 800001a0: 00c11113 slli sp,sp,0xc - 800001a4: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 800001a8: 0020cf33 xor t5,ra,sp - 800001ac: 00ff0eb7 lui t4,0xff0 - 800001b0: 0ffe8e9b addiw t4,t4,255 - 800001b4: 00500193 li gp,5 - 800001b8: 51df1663 bne t5,t4,800006c4 - -00000000800001bc : - 800001bc: 000100b7 lui ra,0x10 - 800001c0: f010809b addiw ra,ra,-255 - 800001c4: 01009093 slli ra,ra,0x10 - 800001c8: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 800001cc: 0f0f1137 lui sp,0xf0f1 - 800001d0: f0f1011b addiw sp,sp,-241 - 800001d4: 0020c0b3 xor ra,ra,sp - 800001d8: 000f0eb7 lui t4,0xf0 - 800001dc: 0ffe8e9b addiw t4,t4,255 - 800001e0: 00ce9e93 slli t4,t4,0xc - 800001e4: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 800001e8: 00600193 li gp,6 - 800001ec: 4dd09c63 bne ra,t4,800006c4 - -00000000800001f0 : - 800001f0: 000100b7 lui ra,0x10 - 800001f4: f010809b addiw ra,ra,-255 - 800001f8: 01009093 slli ra,ra,0x10 - 800001fc: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80000200: 0f0f1137 lui sp,0xf0f1 - 80000204: f0f1011b addiw sp,sp,-241 - 80000208: 0020c133 xor sp,ra,sp - 8000020c: 000f0eb7 lui t4,0xf0 - 80000210: 0ffe8e9b addiw t4,t4,255 - 80000214: 00ce9e93 slli t4,t4,0xc - 80000218: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 8000021c: 00700193 li gp,7 - 80000220: 4bd11263 bne sp,t4,800006c4 - -0000000080000224 : - 80000224: 000100b7 lui ra,0x10 - 80000228: f010809b addiw ra,ra,-255 - 8000022c: 01009093 slli ra,ra,0x10 - 80000230: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80000234: 0010c0b3 xor ra,ra,ra - 80000238: 00000e93 li t4,0 - 8000023c: 00800193 li gp,8 - 80000240: 49d09263 bne ra,t4,800006c4 - -0000000080000244 : - 80000244: 00000213 li tp,0 - 80000248: 000100b7 lui ra,0x10 - 8000024c: f010809b addiw ra,ra,-255 - 80000250: 01009093 slli ra,ra,0x10 - 80000254: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80000258: 0f0f1137 lui sp,0xf0f1 - 8000025c: f0f1011b addiw sp,sp,-241 - 80000260: 0020cf33 xor t5,ra,sp - 80000264: 000f0313 mv t1,t5 - 80000268: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000026c: 00200293 li t0,2 - 80000270: fc521ce3 bne tp,t0,80000248 - 80000274: 000f0eb7 lui t4,0xf0 - 80000278: 0ffe8e9b addiw t4,t4,255 - 8000027c: 00ce9e93 slli t4,t4,0xc - 80000280: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 80000284: 00900193 li gp,9 - 80000288: 43d31e63 bne t1,t4,800006c4 - -000000008000028c : - 8000028c: 00000213 li tp,0 - 80000290: 0ff010b7 lui ra,0xff01 - 80000294: ff00809b addiw ra,ra,-16 - 80000298: 000f1137 lui sp,0xf1 - 8000029c: f0f1011b addiw sp,sp,-241 - 800002a0: 00c11113 slli sp,sp,0xc - 800002a4: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 800002a8: 0020cf33 xor t5,ra,sp - 800002ac: 00000013 nop - 800002b0: 000f0313 mv t1,t5 - 800002b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002b8: 00200293 li t0,2 - 800002bc: fc521ae3 bne tp,t0,80000290 - 800002c0: 00010eb7 lui t4,0x10 - 800002c4: f01e8e9b addiw t4,t4,-255 - 800002c8: 010e9e93 slli t4,t4,0x10 - 800002cc: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 800002d0: 00a00193 li gp,10 - 800002d4: 3fd31863 bne t1,t4,800006c4 - -00000000800002d8 : - 800002d8: 00000213 li tp,0 - 800002dc: 00ff00b7 lui ra,0xff0 - 800002e0: 0ff0809b addiw ra,ra,255 - 800002e4: 0f0f1137 lui sp,0xf0f1 - 800002e8: f0f1011b addiw sp,sp,-241 - 800002ec: 0020cf33 xor t5,ra,sp - 800002f0: 00000013 nop - 800002f4: 00000013 nop - 800002f8: 000f0313 mv t1,t5 - 800002fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000300: 00200293 li t0,2 - 80000304: fc521ce3 bne tp,t0,800002dc - 80000308: 0ff01eb7 lui t4,0xff01 - 8000030c: ff0e8e9b addiw t4,t4,-16 - 80000310: 00b00193 li gp,11 - 80000314: 3bd31863 bne t1,t4,800006c4 - -0000000080000318 : - 80000318: 00000213 li tp,0 - 8000031c: 000100b7 lui ra,0x10 - 80000320: f010809b addiw ra,ra,-255 - 80000324: 01009093 slli ra,ra,0x10 - 80000328: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 8000032c: 0f0f1137 lui sp,0xf0f1 - 80000330: f0f1011b addiw sp,sp,-241 - 80000334: 0020cf33 xor t5,ra,sp - 80000338: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000033c: 00200293 li t0,2 - 80000340: fc521ee3 bne tp,t0,8000031c - 80000344: 000f0eb7 lui t4,0xf0 - 80000348: 0ffe8e9b addiw t4,t4,255 - 8000034c: 00ce9e93 slli t4,t4,0xc - 80000350: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 80000354: 00c00193 li gp,12 - 80000358: 37df1663 bne t5,t4,800006c4 - -000000008000035c : - 8000035c: 00000213 li tp,0 - 80000360: 0ff010b7 lui ra,0xff01 - 80000364: ff00809b addiw ra,ra,-16 - 80000368: 000f1137 lui sp,0xf1 - 8000036c: f0f1011b addiw sp,sp,-241 - 80000370: 00c11113 slli sp,sp,0xc - 80000374: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80000378: 00000013 nop - 8000037c: 0020cf33 xor t5,ra,sp - 80000380: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000384: 00200293 li t0,2 - 80000388: fc521ce3 bne tp,t0,80000360 - 8000038c: 00010eb7 lui t4,0x10 - 80000390: f01e8e9b addiw t4,t4,-255 - 80000394: 010e9e93 slli t4,t4,0x10 - 80000398: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 8000039c: 00d00193 li gp,13 - 800003a0: 33df1263 bne t5,t4,800006c4 - -00000000800003a4 : - 800003a4: 00000213 li tp,0 - 800003a8: 00ff00b7 lui ra,0xff0 - 800003ac: 0ff0809b addiw ra,ra,255 - 800003b0: 0f0f1137 lui sp,0xf0f1 - 800003b4: f0f1011b addiw sp,sp,-241 - 800003b8: 00000013 nop - 800003bc: 00000013 nop - 800003c0: 0020cf33 xor t5,ra,sp - 800003c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003c8: 00200293 li t0,2 - 800003cc: fc521ee3 bne tp,t0,800003a8 - 800003d0: 0ff01eb7 lui t4,0xff01 - 800003d4: ff0e8e9b addiw t4,t4,-16 - 800003d8: 00e00193 li gp,14 - 800003dc: 2fdf1463 bne t5,t4,800006c4 - -00000000800003e0 : - 800003e0: 00000213 li tp,0 - 800003e4: 000100b7 lui ra,0x10 - 800003e8: f010809b addiw ra,ra,-255 - 800003ec: 01009093 slli ra,ra,0x10 - 800003f0: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 800003f4: 00000013 nop - 800003f8: 0f0f1137 lui sp,0xf0f1 - 800003fc: f0f1011b addiw sp,sp,-241 - 80000400: 0020cf33 xor t5,ra,sp - 80000404: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000408: 00200293 li t0,2 - 8000040c: fc521ce3 bne tp,t0,800003e4 - 80000410: 000f0eb7 lui t4,0xf0 - 80000414: 0ffe8e9b addiw t4,t4,255 - 80000418: 00ce9e93 slli t4,t4,0xc - 8000041c: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 80000420: 00f00193 li gp,15 - 80000424: 2bdf1063 bne t5,t4,800006c4 - -0000000080000428 : - 80000428: 00000213 li tp,0 - 8000042c: 0ff010b7 lui ra,0xff01 - 80000430: ff00809b addiw ra,ra,-16 - 80000434: 00000013 nop - 80000438: 000f1137 lui sp,0xf1 - 8000043c: f0f1011b addiw sp,sp,-241 - 80000440: 00c11113 slli sp,sp,0xc - 80000444: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80000448: 00000013 nop - 8000044c: 0020cf33 xor t5,ra,sp - 80000450: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000454: 00200293 li t0,2 - 80000458: fc521ae3 bne tp,t0,8000042c - 8000045c: 00010eb7 lui t4,0x10 - 80000460: f01e8e9b addiw t4,t4,-255 - 80000464: 010e9e93 slli t4,t4,0x10 - 80000468: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 8000046c: 01000193 li gp,16 - 80000470: 25df1a63 bne t5,t4,800006c4 - -0000000080000474 : - 80000474: 00000213 li tp,0 - 80000478: 00ff00b7 lui ra,0xff0 - 8000047c: 0ff0809b addiw ra,ra,255 - 80000480: 00000013 nop - 80000484: 00000013 nop - 80000488: 0f0f1137 lui sp,0xf0f1 - 8000048c: f0f1011b addiw sp,sp,-241 - 80000490: 0020cf33 xor t5,ra,sp - 80000494: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000498: 00200293 li t0,2 - 8000049c: fc521ee3 bne tp,t0,80000478 - 800004a0: 0ff01eb7 lui t4,0xff01 - 800004a4: ff0e8e9b addiw t4,t4,-16 - 800004a8: 01100193 li gp,17 - 800004ac: 21df1c63 bne t5,t4,800006c4 - -00000000800004b0 : - 800004b0: 00000213 li tp,0 - 800004b4: 0f0f1137 lui sp,0xf0f1 - 800004b8: f0f1011b addiw sp,sp,-241 - 800004bc: 000100b7 lui ra,0x10 - 800004c0: f010809b addiw ra,ra,-255 - 800004c4: 01009093 slli ra,ra,0x10 - 800004c8: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 800004cc: 0020cf33 xor t5,ra,sp - 800004d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004d4: 00200293 li t0,2 - 800004d8: fc521ee3 bne tp,t0,800004b4 - 800004dc: 000f0eb7 lui t4,0xf0 - 800004e0: 0ffe8e9b addiw t4,t4,255 - 800004e4: 00ce9e93 slli t4,t4,0xc - 800004e8: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 800004ec: 01200193 li gp,18 - 800004f0: 1ddf1a63 bne t5,t4,800006c4 - -00000000800004f4 : - 800004f4: 00000213 li tp,0 - 800004f8: 000f1137 lui sp,0xf1 - 800004fc: f0f1011b addiw sp,sp,-241 - 80000500: 00c11113 slli sp,sp,0xc - 80000504: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80000508: 0ff010b7 lui ra,0xff01 - 8000050c: ff00809b addiw ra,ra,-16 - 80000510: 00000013 nop - 80000514: 0020cf33 xor t5,ra,sp - 80000518: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000051c: 00200293 li t0,2 - 80000520: fc521ce3 bne tp,t0,800004f8 - 80000524: 00010eb7 lui t4,0x10 - 80000528: f01e8e9b addiw t4,t4,-255 - 8000052c: 010e9e93 slli t4,t4,0x10 - 80000530: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80000534: 01300193 li gp,19 - 80000538: 19df1663 bne t5,t4,800006c4 - -000000008000053c : - 8000053c: 00000213 li tp,0 - 80000540: 0f0f1137 lui sp,0xf0f1 - 80000544: f0f1011b addiw sp,sp,-241 - 80000548: 00ff00b7 lui ra,0xff0 - 8000054c: 0ff0809b addiw ra,ra,255 - 80000550: 00000013 nop - 80000554: 00000013 nop - 80000558: 0020cf33 xor t5,ra,sp - 8000055c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000560: 00200293 li t0,2 - 80000564: fc521ee3 bne tp,t0,80000540 - 80000568: 0ff01eb7 lui t4,0xff01 - 8000056c: ff0e8e9b addiw t4,t4,-16 - 80000570: 01400193 li gp,20 - 80000574: 15df1863 bne t5,t4,800006c4 - -0000000080000578 : - 80000578: 00000213 li tp,0 - 8000057c: 0f0f1137 lui sp,0xf0f1 - 80000580: f0f1011b addiw sp,sp,-241 - 80000584: 00000013 nop - 80000588: 000100b7 lui ra,0x10 - 8000058c: f010809b addiw ra,ra,-255 - 80000590: 01009093 slli ra,ra,0x10 - 80000594: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80000598: 0020cf33 xor t5,ra,sp - 8000059c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800005a0: 00200293 li t0,2 - 800005a4: fc521ce3 bne tp,t0,8000057c - 800005a8: 000f0eb7 lui t4,0xf0 - 800005ac: 0ffe8e9b addiw t4,t4,255 - 800005b0: 00ce9e93 slli t4,t4,0xc - 800005b4: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 800005b8: 01500193 li gp,21 - 800005bc: 11df1463 bne t5,t4,800006c4 - -00000000800005c0 : - 800005c0: 00000213 li tp,0 - 800005c4: 000f1137 lui sp,0xf1 - 800005c8: f0f1011b addiw sp,sp,-241 - 800005cc: 00c11113 slli sp,sp,0xc - 800005d0: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 800005d4: 00000013 nop - 800005d8: 0ff010b7 lui ra,0xff01 - 800005dc: ff00809b addiw ra,ra,-16 - 800005e0: 00000013 nop - 800005e4: 0020cf33 xor t5,ra,sp - 800005e8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800005ec: 00200293 li t0,2 - 800005f0: fc521ae3 bne tp,t0,800005c4 - 800005f4: 00010eb7 lui t4,0x10 - 800005f8: f01e8e9b addiw t4,t4,-255 - 800005fc: 010e9e93 slli t4,t4,0x10 - 80000600: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80000604: 01600193 li gp,22 - 80000608: 0bdf1e63 bne t5,t4,800006c4 - -000000008000060c : - 8000060c: 00000213 li tp,0 - 80000610: 0f0f1137 lui sp,0xf0f1 - 80000614: f0f1011b addiw sp,sp,-241 - 80000618: 00000013 nop - 8000061c: 00000013 nop - 80000620: 00ff00b7 lui ra,0xff0 - 80000624: 0ff0809b addiw ra,ra,255 - 80000628: 0020cf33 xor t5,ra,sp - 8000062c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000630: 00200293 li t0,2 - 80000634: fc521ee3 bne tp,t0,80000610 - 80000638: 0ff01eb7 lui t4,0xff01 - 8000063c: ff0e8e9b addiw t4,t4,-16 - 80000640: 01700193 li gp,23 - 80000644: 09df1063 bne t5,t4,800006c4 - -0000000080000648 : - 80000648: 000100b7 lui ra,0x10 - 8000064c: f010809b addiw ra,ra,-255 - 80000650: 01009093 slli ra,ra,0x10 - 80000654: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80000658: 00104133 xor sp,zero,ra - 8000065c: 00010eb7 lui t4,0x10 - 80000660: f01e8e9b addiw t4,t4,-255 - 80000664: 010e9e93 slli t4,t4,0x10 - 80000668: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 8000066c: 01800193 li gp,24 - 80000670: 05d11a63 bne sp,t4,800006c4 - -0000000080000674 : - 80000674: 00ff00b7 lui ra,0xff0 - 80000678: 0ff0809b addiw ra,ra,255 - 8000067c: 0000c133 xor sp,ra,zero - 80000680: 00ff0eb7 lui t4,0xff0 - 80000684: 0ffe8e9b addiw t4,t4,255 - 80000688: 01900193 li gp,25 - 8000068c: 03d11c63 bne sp,t4,800006c4 - -0000000080000690 : - 80000690: 000040b3 xor ra,zero,zero - 80000694: 00000e93 li t4,0 - 80000698: 01a00193 li gp,26 - 8000069c: 03d09463 bne ra,t4,800006c4 - -00000000800006a0 : - 800006a0: 111110b7 lui ra,0x11111 - 800006a4: 1110809b addiw ra,ra,273 - 800006a8: 22222137 lui sp,0x22222 - 800006ac: 2221011b addiw sp,sp,546 - 800006b0: 0020c033 xor zero,ra,sp - 800006b4: 00000e93 li t4,0 - 800006b8: 01b00193 li gp,27 - 800006bc: 01d01463 bne zero,t4,800006c4 - 800006c0: 00301c63 bne zero,gp,800006d8 - -00000000800006c4 : - 800006c4: 0ff0000f fence - 800006c8: 00018063 beqz gp,800006c8 - 800006cc: 00119193 slli gp,gp,0x1 - 800006d0: 0011e193 ori gp,gp,1 - 800006d4: 00000073 ecall - -00000000800006d8 : - 800006d8: 0ff0000f fence - 800006dc: 00100193 li gp,1 - 800006e0: 00000073 ecall - 800006e4: c0001073 unimp - 800006e8: 0000 unimp - 800006ea: 0000 unimp - 800006ec: 0000 unimp - 800006ee: 0000 unimp - 800006f0: 0000 unimp - 800006f2: 0000 unimp - 800006f4: 0000 unimp - 800006f6: 0000 unimp - 800006f8: 0000 unimp - 800006fa: 0000 unimp - 800006fc: 0000 unimp - 800006fe: 0000 unimp - 80000700: 0000 unimp - 80000702: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-xor.elf b/test/riscv/tests/rv64ui-p-xor.elf deleted file mode 100644 index 0466245a..00000000 Binary files a/test/riscv/tests/rv64ui-p-xor.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-p-xori.dump b/test/riscv/tests/rv64ui-p-xori.dump deleted file mode 100644 index 12f6997d..00000000 --- a/test/riscv/tests/rv64ui-p-xori.dump +++ /dev/null @@ -1,238 +0,0 @@ - -rv64ui-p-xori: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00ff10b7 lui ra,0xff1 - 80000100: f000809b addiw ra,ra,-256 - 80000104: f0f0cf13 xori t5,ra,-241 - 80000108: ff00feb7 lui t4,0xff00f - 8000010c: 00fe8e9b addiw t4,t4,15 - 80000110: 00200193 li gp,2 - 80000114: 1ddf1663 bne t5,t4,800002e0 - -0000000080000118 : - 80000118: 0ff010b7 lui ra,0xff01 - 8000011c: ff00809b addiw ra,ra,-16 - 80000120: 0f00cf13 xori t5,ra,240 - 80000124: 0ff01eb7 lui t4,0xff01 - 80000128: f00e8e9b addiw t4,t4,-256 - 8000012c: 00300193 li gp,3 - 80000130: 1bdf1863 bne t5,t4,800002e0 - -0000000080000134 : - 80000134: 00ff10b7 lui ra,0xff1 - 80000138: 8ff0809b addiw ra,ra,-1793 - 8000013c: 70f0cf13 xori t5,ra,1807 - 80000140: 00ff1eb7 lui t4,0xff1 - 80000144: ff0e8e9b addiw t4,t4,-16 - 80000148: 00400193 li gp,4 - 8000014c: 19df1a63 bne t5,t4,800002e0 - -0000000080000150 : - 80000150: f00ff0b7 lui ra,0xf00ff - 80000154: 00f0809b addiw ra,ra,15 - 80000158: 0f00cf13 xori t5,ra,240 - 8000015c: f00ffeb7 lui t4,0xf00ff - 80000160: 0ffe8e9b addiw t4,t4,255 - 80000164: 00500193 li gp,5 - 80000168: 17df1c63 bne t5,t4,800002e0 - -000000008000016c : - 8000016c: ff00f0b7 lui ra,0xff00f - 80000170: 7000809b addiw ra,ra,1792 - 80000174: 70f0c093 xori ra,ra,1807 - 80000178: ff00feb7 lui t4,0xff00f - 8000017c: 00fe8e9b addiw t4,t4,15 - 80000180: 00600193 li gp,6 - 80000184: 15d09e63 bne ra,t4,800002e0 - -0000000080000188 : - 80000188: 00000213 li tp,0 - 8000018c: 0ff010b7 lui ra,0xff01 - 80000190: ff00809b addiw ra,ra,-16 - 80000194: 0f00cf13 xori t5,ra,240 - 80000198: 000f0313 mv t1,t5 - 8000019c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800001a0: 00200293 li t0,2 - 800001a4: fe5214e3 bne tp,t0,8000018c - 800001a8: 0ff01eb7 lui t4,0xff01 - 800001ac: f00e8e9b addiw t4,t4,-256 - 800001b0: 00700193 li gp,7 - 800001b4: 13d31663 bne t1,t4,800002e0 - -00000000800001b8 : - 800001b8: 00000213 li tp,0 - 800001bc: 00ff10b7 lui ra,0xff1 - 800001c0: 8ff0809b addiw ra,ra,-1793 - 800001c4: 70f0cf13 xori t5,ra,1807 - 800001c8: 00000013 nop - 800001cc: 000f0313 mv t1,t5 - 800001d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800001d4: 00200293 li t0,2 - 800001d8: fe5212e3 bne tp,t0,800001bc - 800001dc: 00ff1eb7 lui t4,0xff1 - 800001e0: ff0e8e9b addiw t4,t4,-16 - 800001e4: 00800193 li gp,8 - 800001e8: 0fd31c63 bne t1,t4,800002e0 - -00000000800001ec : - 800001ec: 00000213 li tp,0 - 800001f0: f00ff0b7 lui ra,0xf00ff - 800001f4: 00f0809b addiw ra,ra,15 - 800001f8: 0f00cf13 xori t5,ra,240 - 800001fc: 00000013 nop - 80000200: 00000013 nop - 80000204: 000f0313 mv t1,t5 - 80000208: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000020c: 00200293 li t0,2 - 80000210: fe5210e3 bne tp,t0,800001f0 - 80000214: f00ffeb7 lui t4,0xf00ff - 80000218: 0ffe8e9b addiw t4,t4,255 - 8000021c: 00900193 li gp,9 - 80000220: 0dd31063 bne t1,t4,800002e0 - -0000000080000224 : - 80000224: 00000213 li tp,0 - 80000228: 0ff010b7 lui ra,0xff01 - 8000022c: ff00809b addiw ra,ra,-16 - 80000230: 0f00cf13 xori t5,ra,240 - 80000234: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000238: 00200293 li t0,2 - 8000023c: fe5216e3 bne tp,t0,80000228 - 80000240: 0ff01eb7 lui t4,0xff01 - 80000244: f00e8e9b addiw t4,t4,-256 - 80000248: 00a00193 li gp,10 - 8000024c: 09df1a63 bne t5,t4,800002e0 - -0000000080000250 : - 80000250: 00000213 li tp,0 - 80000254: 00ff10b7 lui ra,0xff1 - 80000258: fff0809b addiw ra,ra,-1 - 8000025c: 00000013 nop - 80000260: 00f0cf13 xori t5,ra,15 - 80000264: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000268: 00200293 li t0,2 - 8000026c: fe5214e3 bne tp,t0,80000254 - 80000270: 00ff1eb7 lui t4,0xff1 - 80000274: ff0e8e9b addiw t4,t4,-16 - 80000278: 00b00193 li gp,11 - 8000027c: 07df1263 bne t5,t4,800002e0 - -0000000080000280 : - 80000280: 00000213 li tp,0 - 80000284: f00ff0b7 lui ra,0xf00ff - 80000288: 00f0809b addiw ra,ra,15 - 8000028c: 00000013 nop - 80000290: 00000013 nop - 80000294: 0f00cf13 xori t5,ra,240 - 80000298: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000029c: 00200293 li t0,2 - 800002a0: fe5212e3 bne tp,t0,80000284 - 800002a4: f00ffeb7 lui t4,0xf00ff - 800002a8: 0ffe8e9b addiw t4,t4,255 - 800002ac: 00c00193 li gp,12 - 800002b0: 03df1863 bne t5,t4,800002e0 - -00000000800002b4 : - 800002b4: 0f004093 xori ra,zero,240 - 800002b8: 0f000e93 li t4,240 - 800002bc: 00d00193 li gp,13 - 800002c0: 03d09063 bne ra,t4,800002e0 - -00000000800002c4 : - 800002c4: 00ff00b7 lui ra,0xff0 - 800002c8: 0ff0809b addiw ra,ra,255 - 800002cc: 70f0c013 xori zero,ra,1807 - 800002d0: 00000e93 li t4,0 - 800002d4: 00e00193 li gp,14 - 800002d8: 01d01463 bne zero,t4,800002e0 - 800002dc: 00301c63 bne zero,gp,800002f4 - -00000000800002e0 : - 800002e0: 0ff0000f fence - 800002e4: 00018063 beqz gp,800002e4 - 800002e8: 00119193 slli gp,gp,0x1 - 800002ec: 0011e193 ori gp,gp,1 - 800002f0: 00000073 ecall - -00000000800002f4 : - 800002f4: 0ff0000f fence - 800002f8: 00100193 li gp,1 - 800002fc: 00000073 ecall - 80000300: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-p-xori.elf b/test/riscv/tests/rv64ui-p-xori.elf deleted file mode 100644 index fe522aff..00000000 Binary files a/test/riscv/tests/rv64ui-p-xori.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-add.dump b/test/riscv/tests/rv64ui-v-add.dump deleted file mode 100644 index 8598d2b6..00000000 --- a/test/riscv/tests/rv64ui-v-add.dump +++ /dev/null @@ -1,1229 +0,0 @@ - -rv64ui-v-add: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: b8068693 addi a3,a3,-1152 # 80002fd8 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: bb460613 addi a2,a2,-1100 # 80003068 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: b7c60613 addi a2,a2,-1156 # 80003080 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: acc68693 addi a3,a3,-1332 # 80003020 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: ae868693 addi a3,a3,-1304 # 80003158 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: a6860613 addi a2,a2,-1432 # 80003130 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: 99c68693 addi a3,a3,-1636 # 80003188 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 8bc68693 addi a3,a3,-1860 # 800030f8 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00001697 auipc a3,0x1 - 80002878: 84c68693 addi a3,a3,-1972 # 800030c0 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 02100793 li a5,33 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0f1557b7 lui a5,0xf155 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 1b078793 addi a5,a5,432 # f1551b0 <_start-0x70eaae50> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000093 li ra,0 - 80002acc: 00000113 li sp,0 - 80002ad0: 00208f33 add t5,ra,sp - 80002ad4: 00000e93 li t4,0 - 80002ad8: 00200193 li gp,2 - 80002adc: 4fdf1063 bne t5,t4,80002fbc - -0000000080002ae0 : - 80002ae0: 00100093 li ra,1 - 80002ae4: 00100113 li sp,1 - 80002ae8: 00208f33 add t5,ra,sp - 80002aec: 00200e93 li t4,2 - 80002af0: 00300193 li gp,3 - 80002af4: 4ddf1463 bne t5,t4,80002fbc - -0000000080002af8 : - 80002af8: 00300093 li ra,3 - 80002afc: 00700113 li sp,7 - 80002b00: 00208f33 add t5,ra,sp - 80002b04: 00a00e93 li t4,10 - 80002b08: 00400193 li gp,4 - 80002b0c: 4bdf1863 bne t5,t4,80002fbc - -0000000080002b10 : - 80002b10: 00000093 li ra,0 - 80002b14: ffff8137 lui sp,0xffff8 - 80002b18: 00208f33 add t5,ra,sp - 80002b1c: ffff8eb7 lui t4,0xffff8 - 80002b20: 00500193 li gp,5 - 80002b24: 49df1c63 bne t5,t4,80002fbc - -0000000080002b28 : - 80002b28: 800000b7 lui ra,0x80000 - 80002b2c: 00000113 li sp,0 - 80002b30: 00208f33 add t5,ra,sp - 80002b34: 80000eb7 lui t4,0x80000 - 80002b38: 00600193 li gp,6 - 80002b3c: 49df1063 bne t5,t4,80002fbc - -0000000080002b40 : - 80002b40: 800000b7 lui ra,0x80000 - 80002b44: ffff8137 lui sp,0xffff8 - 80002b48: 00208f33 add t5,ra,sp - 80002b4c: ffff0eb7 lui t4,0xffff0 - 80002b50: fffe8e9b addiw t4,t4,-1 - 80002b54: 00fe9e93 slli t4,t4,0xf - 80002b58: 00700193 li gp,7 - 80002b5c: 47df1063 bne t5,t4,80002fbc - -0000000080002b60 : - 80002b60: 00000093 li ra,0 - 80002b64: 00008137 lui sp,0x8 - 80002b68: fff1011b addiw sp,sp,-1 - 80002b6c: 00208f33 add t5,ra,sp - 80002b70: 00008eb7 lui t4,0x8 - 80002b74: fffe8e9b addiw t4,t4,-1 - 80002b78: 00800193 li gp,8 - 80002b7c: 45df1063 bne t5,t4,80002fbc - -0000000080002b80 : - 80002b80: 800000b7 lui ra,0x80000 - 80002b84: fff0809b addiw ra,ra,-1 - 80002b88: 00000113 li sp,0 - 80002b8c: 00208f33 add t5,ra,sp - 80002b90: 80000eb7 lui t4,0x80000 - 80002b94: fffe8e9b addiw t4,t4,-1 - 80002b98: 00900193 li gp,9 - 80002b9c: 43df1063 bne t5,t4,80002fbc - -0000000080002ba0 : - 80002ba0: 800000b7 lui ra,0x80000 - 80002ba4: fff0809b addiw ra,ra,-1 - 80002ba8: 00008137 lui sp,0x8 - 80002bac: fff1011b addiw sp,sp,-1 - 80002bb0: 00208f33 add t5,ra,sp - 80002bb4: 00010eb7 lui t4,0x10 - 80002bb8: 001e8e9b addiw t4,t4,1 - 80002bbc: 00fe9e93 slli t4,t4,0xf - 80002bc0: ffee8e93 addi t4,t4,-2 # fffe <_start-0x7fff0002> - 80002bc4: 00a00193 li gp,10 - 80002bc8: 3fdf1a63 bne t5,t4,80002fbc - -0000000080002bcc : - 80002bcc: 800000b7 lui ra,0x80000 - 80002bd0: 00008137 lui sp,0x8 - 80002bd4: fff1011b addiw sp,sp,-1 - 80002bd8: 00208f33 add t5,ra,sp - 80002bdc: 80008eb7 lui t4,0x80008 - 80002be0: fffe8e9b addiw t4,t4,-1 - 80002be4: 00b00193 li gp,11 - 80002be8: 3ddf1a63 bne t5,t4,80002fbc - -0000000080002bec : - 80002bec: 800000b7 lui ra,0x80000 - 80002bf0: fff0809b addiw ra,ra,-1 - 80002bf4: ffff8137 lui sp,0xffff8 - 80002bf8: 00208f33 add t5,ra,sp - 80002bfc: 7fff8eb7 lui t4,0x7fff8 - 80002c00: fffe8e9b addiw t4,t4,-1 - 80002c04: 00c00193 li gp,12 - 80002c08: 3bdf1a63 bne t5,t4,80002fbc - -0000000080002c0c : - 80002c0c: 00000093 li ra,0 - 80002c10: fff00113 li sp,-1 - 80002c14: 00208f33 add t5,ra,sp - 80002c18: fff00e93 li t4,-1 - 80002c1c: 00d00193 li gp,13 - 80002c20: 39df1e63 bne t5,t4,80002fbc - -0000000080002c24 : - 80002c24: fff00093 li ra,-1 - 80002c28: 00100113 li sp,1 - 80002c2c: 00208f33 add t5,ra,sp - 80002c30: 00000e93 li t4,0 - 80002c34: 00e00193 li gp,14 - 80002c38: 39df1263 bne t5,t4,80002fbc - -0000000080002c3c : - 80002c3c: fff00093 li ra,-1 - 80002c40: fff00113 li sp,-1 - 80002c44: 00208f33 add t5,ra,sp - 80002c48: ffe00e93 li t4,-2 - 80002c4c: 00f00193 li gp,15 - 80002c50: 37df1663 bne t5,t4,80002fbc - -0000000080002c54 : - 80002c54: 00100093 li ra,1 - 80002c58: 80000137 lui sp,0x80000 - 80002c5c: fff1011b addiw sp,sp,-1 - 80002c60: 00208f33 add t5,ra,sp - 80002c64: 00100e9b addiw t4,zero,1 - 80002c68: 01fe9e93 slli t4,t4,0x1f - 80002c6c: 01000193 li gp,16 - 80002c70: 35df1663 bne t5,t4,80002fbc - -0000000080002c74 : - 80002c74: 00d00093 li ra,13 - 80002c78: 00b00113 li sp,11 - 80002c7c: 002080b3 add ra,ra,sp - 80002c80: 01800e93 li t4,24 - 80002c84: 01100193 li gp,17 - 80002c88: 33d09a63 bne ra,t4,80002fbc - -0000000080002c8c : - 80002c8c: 00e00093 li ra,14 - 80002c90: 00b00113 li sp,11 - 80002c94: 00208133 add sp,ra,sp - 80002c98: 01900e93 li t4,25 - 80002c9c: 01200193 li gp,18 - 80002ca0: 31d11e63 bne sp,t4,80002fbc - -0000000080002ca4 : - 80002ca4: 00d00093 li ra,13 - 80002ca8: 001080b3 add ra,ra,ra - 80002cac: 01a00e93 li t4,26 - 80002cb0: 01300193 li gp,19 - 80002cb4: 31d09463 bne ra,t4,80002fbc - -0000000080002cb8 : - 80002cb8: 00000213 li tp,0 - 80002cbc: 00d00093 li ra,13 - 80002cc0: 00b00113 li sp,11 - 80002cc4: 00208f33 add t5,ra,sp - 80002cc8: 000f0313 mv t1,t5 - 80002ccc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cd0: 00200293 li t0,2 - 80002cd4: fe5214e3 bne tp,t0,80002cbc - 80002cd8: 01800e93 li t4,24 - 80002cdc: 01400193 li gp,20 - 80002ce0: 2dd31e63 bne t1,t4,80002fbc - -0000000080002ce4 : - 80002ce4: 00000213 li tp,0 - 80002ce8: 00e00093 li ra,14 - 80002cec: 00b00113 li sp,11 - 80002cf0: 00208f33 add t5,ra,sp - 80002cf4: 00000013 nop - 80002cf8: 000f0313 mv t1,t5 - 80002cfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d00: 00200293 li t0,2 - 80002d04: fe5212e3 bne tp,t0,80002ce8 - 80002d08: 01900e93 li t4,25 - 80002d0c: 01500193 li gp,21 - 80002d10: 2bd31663 bne t1,t4,80002fbc - -0000000080002d14 : - 80002d14: 00000213 li tp,0 - 80002d18: 00f00093 li ra,15 - 80002d1c: 00b00113 li sp,11 - 80002d20: 00208f33 add t5,ra,sp - 80002d24: 00000013 nop - 80002d28: 00000013 nop - 80002d2c: 000f0313 mv t1,t5 - 80002d30: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d34: 00200293 li t0,2 - 80002d38: fe5210e3 bne tp,t0,80002d18 - 80002d3c: 01a00e93 li t4,26 - 80002d40: 01600193 li gp,22 - 80002d44: 27d31c63 bne t1,t4,80002fbc - -0000000080002d48 : - 80002d48: 00000213 li tp,0 - 80002d4c: 00d00093 li ra,13 - 80002d50: 00b00113 li sp,11 - 80002d54: 00208f33 add t5,ra,sp - 80002d58: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d5c: 00200293 li t0,2 - 80002d60: fe5216e3 bne tp,t0,80002d4c - 80002d64: 01800e93 li t4,24 - 80002d68: 01700193 li gp,23 - 80002d6c: 25df1863 bne t5,t4,80002fbc - -0000000080002d70 : - 80002d70: 00000213 li tp,0 - 80002d74: 00e00093 li ra,14 - 80002d78: 00b00113 li sp,11 - 80002d7c: 00000013 nop - 80002d80: 00208f33 add t5,ra,sp - 80002d84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d88: 00200293 li t0,2 - 80002d8c: fe5214e3 bne tp,t0,80002d74 - 80002d90: 01900e93 li t4,25 - 80002d94: 01800193 li gp,24 - 80002d98: 23df1263 bne t5,t4,80002fbc - -0000000080002d9c : - 80002d9c: 00000213 li tp,0 - 80002da0: 00f00093 li ra,15 - 80002da4: 00b00113 li sp,11 - 80002da8: 00000013 nop - 80002dac: 00000013 nop - 80002db0: 00208f33 add t5,ra,sp - 80002db4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002db8: 00200293 li t0,2 - 80002dbc: fe5212e3 bne tp,t0,80002da0 - 80002dc0: 01a00e93 li t4,26 - 80002dc4: 01900193 li gp,25 - 80002dc8: 1fdf1a63 bne t5,t4,80002fbc - -0000000080002dcc : - 80002dcc: 00000213 li tp,0 - 80002dd0: 00d00093 li ra,13 - 80002dd4: 00000013 nop - 80002dd8: 00b00113 li sp,11 - 80002ddc: 00208f33 add t5,ra,sp - 80002de0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002de4: 00200293 li t0,2 - 80002de8: fe5214e3 bne tp,t0,80002dd0 - 80002dec: 01800e93 li t4,24 - 80002df0: 01a00193 li gp,26 - 80002df4: 1ddf1463 bne t5,t4,80002fbc - -0000000080002df8 : - 80002df8: 00000213 li tp,0 - 80002dfc: 00e00093 li ra,14 - 80002e00: 00000013 nop - 80002e04: 00b00113 li sp,11 - 80002e08: 00000013 nop - 80002e0c: 00208f33 add t5,ra,sp - 80002e10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e14: 00200293 li t0,2 - 80002e18: fe5212e3 bne tp,t0,80002dfc - 80002e1c: 01900e93 li t4,25 - 80002e20: 01b00193 li gp,27 - 80002e24: 19df1c63 bne t5,t4,80002fbc - -0000000080002e28 : - 80002e28: 00000213 li tp,0 - 80002e2c: 00f00093 li ra,15 - 80002e30: 00000013 nop - 80002e34: 00000013 nop - 80002e38: 00b00113 li sp,11 - 80002e3c: 00208f33 add t5,ra,sp - 80002e40: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e44: 00200293 li t0,2 - 80002e48: fe5212e3 bne tp,t0,80002e2c - 80002e4c: 01a00e93 li t4,26 - 80002e50: 01c00193 li gp,28 - 80002e54: 17df1463 bne t5,t4,80002fbc - -0000000080002e58 : - 80002e58: 00000213 li tp,0 - 80002e5c: 00b00113 li sp,11 - 80002e60: 00d00093 li ra,13 - 80002e64: 00208f33 add t5,ra,sp - 80002e68: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e6c: 00200293 li t0,2 - 80002e70: fe5216e3 bne tp,t0,80002e5c - 80002e74: 01800e93 li t4,24 - 80002e78: 01d00193 li gp,29 - 80002e7c: 15df1063 bne t5,t4,80002fbc - -0000000080002e80 : - 80002e80: 00000213 li tp,0 - 80002e84: 00b00113 li sp,11 - 80002e88: 00e00093 li ra,14 - 80002e8c: 00000013 nop - 80002e90: 00208f33 add t5,ra,sp - 80002e94: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e98: 00200293 li t0,2 - 80002e9c: fe5214e3 bne tp,t0,80002e84 - 80002ea0: 01900e93 li t4,25 - 80002ea4: 01e00193 li gp,30 - 80002ea8: 11df1a63 bne t5,t4,80002fbc - -0000000080002eac : - 80002eac: 00000213 li tp,0 - 80002eb0: 00b00113 li sp,11 - 80002eb4: 00f00093 li ra,15 - 80002eb8: 00000013 nop - 80002ebc: 00000013 nop - 80002ec0: 00208f33 add t5,ra,sp - 80002ec4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ec8: 00200293 li t0,2 - 80002ecc: fe5212e3 bne tp,t0,80002eb0 - 80002ed0: 01a00e93 li t4,26 - 80002ed4: 01f00193 li gp,31 - 80002ed8: 0fdf1263 bne t5,t4,80002fbc - -0000000080002edc : - 80002edc: 00000213 li tp,0 - 80002ee0: 00b00113 li sp,11 - 80002ee4: 00000013 nop - 80002ee8: 00d00093 li ra,13 - 80002eec: 00208f33 add t5,ra,sp - 80002ef0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ef4: 00200293 li t0,2 - 80002ef8: fe5214e3 bne tp,t0,80002ee0 - 80002efc: 01800e93 li t4,24 - 80002f00: 02000193 li gp,32 - 80002f04: 0bdf1c63 bne t5,t4,80002fbc - -0000000080002f08 : - 80002f08: 00000213 li tp,0 - 80002f0c: 00b00113 li sp,11 - 80002f10: 00000013 nop - 80002f14: 00e00093 li ra,14 - 80002f18: 00000013 nop - 80002f1c: 00208f33 add t5,ra,sp - 80002f20: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f24: 00200293 li t0,2 - 80002f28: fe5212e3 bne tp,t0,80002f0c - 80002f2c: 01900e93 li t4,25 - 80002f30: 02100193 li gp,33 - 80002f34: 09df1463 bne t5,t4,80002fbc - -0000000080002f38 : - 80002f38: 00000213 li tp,0 - 80002f3c: 00b00113 li sp,11 - 80002f40: 00000013 nop - 80002f44: 00000013 nop - 80002f48: 00f00093 li ra,15 - 80002f4c: 00208f33 add t5,ra,sp - 80002f50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f54: 00200293 li t0,2 - 80002f58: fe5212e3 bne tp,t0,80002f3c - 80002f5c: 01a00e93 li t4,26 - 80002f60: 02200193 li gp,34 - 80002f64: 05df1c63 bne t5,t4,80002fbc - -0000000080002f68 : - 80002f68: 00f00093 li ra,15 - 80002f6c: 00100133 add sp,zero,ra - 80002f70: 00f00e93 li t4,15 - 80002f74: 02300193 li gp,35 - 80002f78: 05d11263 bne sp,t4,80002fbc - -0000000080002f7c : - 80002f7c: 02000093 li ra,32 - 80002f80: 00008133 add sp,ra,zero - 80002f84: 02000e93 li t4,32 - 80002f88: 02400193 li gp,36 - 80002f8c: 03d11863 bne sp,t4,80002fbc - -0000000080002f90 : - 80002f90: 000000b3 add ra,zero,zero - 80002f94: 00000e93 li t4,0 - 80002f98: 02500193 li gp,37 - 80002f9c: 03d09063 bne ra,t4,80002fbc - -0000000080002fa0 : - 80002fa0: 01000093 li ra,16 - 80002fa4: 01e00113 li sp,30 - 80002fa8: 00208033 add zero,ra,sp - 80002fac: 00000e93 li t4,0 - 80002fb0: 02600193 li gp,38 - 80002fb4: 01d01463 bne zero,t4,80002fbc - 80002fb8: 00301a63 bne zero,gp,80002fcc - -0000000080002fbc : - 80002fbc: 00119513 slli a0,gp,0x1 - 80002fc0: 00050063 beqz a0,80002fc0 - 80002fc4: 00156513 ori a0,a0,1 - 80002fc8: 00000073 ecall - -0000000080002fcc : - 80002fcc: 00100513 li a0,1 - 80002fd0: 00000073 ecall - 80002fd4: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-add.elf b/test/riscv/tests/rv64ui-v-add.elf deleted file mode 100644 index d60d87a8..00000000 Binary files a/test/riscv/tests/rv64ui-v-add.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-addi.dump b/test/riscv/tests/rv64ui-v-addi.dump deleted file mode 100644 index 6c453f70..00000000 --- a/test/riscv/tests/rv64ui-v-addi.dump +++ /dev/null @@ -1,1051 +0,0 @@ - -rv64ui-v-addi: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 92068693 addi a3,a3,-1760 # 80002d78 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 95460613 addi a2,a2,-1708 # 80002e08 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 91c60613 addi a2,a2,-1764 # 80002e20 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 86c68693 addi a3,a3,-1940 # 80002dc0 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 88868693 addi a3,a3,-1912 # 80002ef8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 80860613 addi a2,a2,-2040 # 80002ed0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 73c68693 addi a3,a3,1852 # 80002f28 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 65c68693 addi a3,a3,1628 # 80002e98 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 5ec68693 addi a3,a3,1516 # 80002e60 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 01000793 li a5,16 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 04f557b7 lui a5,0x4f55 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 5a178793 addi a5,a5,1441 # 4f555a1 <_start-0x7b0aaa5f> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000093 li ra,0 - 80002acc: 00008f13 mv t5,ra - 80002ad0: 00000e93 li t4,0 - 80002ad4: 00200193 li gp,2 - 80002ad8: 29df1263 bne t5,t4,80002d5c - -0000000080002adc : - 80002adc: 00100093 li ra,1 - 80002ae0: 00108f13 addi t5,ra,1 - 80002ae4: 00200e93 li t4,2 - 80002ae8: 00300193 li gp,3 - 80002aec: 27df1863 bne t5,t4,80002d5c - -0000000080002af0 : - 80002af0: 00300093 li ra,3 - 80002af4: 00708f13 addi t5,ra,7 - 80002af8: 00a00e93 li t4,10 - 80002afc: 00400193 li gp,4 - 80002b00: 25df1e63 bne t5,t4,80002d5c - -0000000080002b04 : - 80002b04: 00000093 li ra,0 - 80002b08: 80008f13 addi t5,ra,-2048 - 80002b0c: 80000e93 li t4,-2048 - 80002b10: 00500193 li gp,5 - 80002b14: 25df1463 bne t5,t4,80002d5c - -0000000080002b18 : - 80002b18: 800000b7 lui ra,0x80000 - 80002b1c: 00008f13 mv t5,ra - 80002b20: 80000eb7 lui t4,0x80000 - 80002b24: 00600193 li gp,6 - 80002b28: 23df1a63 bne t5,t4,80002d5c - -0000000080002b2c : - 80002b2c: 800000b7 lui ra,0x80000 - 80002b30: 80008f13 addi t5,ra,-2048 # ffffffff7ffff800 <_end+0xfffffffeffff8010> - 80002b34: fff00e9b addiw t4,zero,-1 - 80002b38: 01fe9e93 slli t4,t4,0x1f - 80002b3c: 800e8e93 addi t4,t4,-2048 # ffffffff7ffff800 <_end+0xfffffffeffff8010> - 80002b40: 00700193 li gp,7 - 80002b44: 21df1c63 bne t5,t4,80002d5c - -0000000080002b48 : - 80002b48: 00000093 li ra,0 - 80002b4c: 7ff08f13 addi t5,ra,2047 - 80002b50: 7ff00e93 li t4,2047 - 80002b54: 00800193 li gp,8 - 80002b58: 21df1263 bne t5,t4,80002d5c - -0000000080002b5c : - 80002b5c: 800000b7 lui ra,0x80000 - 80002b60: fff0809b addiw ra,ra,-1 - 80002b64: 00008f13 mv t5,ra - 80002b68: 80000eb7 lui t4,0x80000 - 80002b6c: fffe8e9b addiw t4,t4,-1 - 80002b70: 00900193 li gp,9 - 80002b74: 1fdf1463 bne t5,t4,80002d5c - -0000000080002b78 : - 80002b78: 800000b7 lui ra,0x80000 - 80002b7c: fff0809b addiw ra,ra,-1 - 80002b80: 7ff08f13 addi t5,ra,2047 # ffffffff800007ff <_end+0xfffffffeffff900f> - 80002b84: 00100e9b addiw t4,zero,1 - 80002b88: 01fe9e93 slli t4,t4,0x1f - 80002b8c: 7fee8e93 addi t4,t4,2046 # ffffffff800007fe <_end+0xfffffffeffff900e> - 80002b90: 00a00193 li gp,10 - 80002b94: 1ddf1463 bne t5,t4,80002d5c - -0000000080002b98 : - 80002b98: 800000b7 lui ra,0x80000 - 80002b9c: 7ff08f13 addi t5,ra,2047 # ffffffff800007ff <_end+0xfffffffeffff900f> - 80002ba0: 80000eb7 lui t4,0x80000 - 80002ba4: 7ffe8e9b addiw t4,t4,2047 - 80002ba8: 00b00193 li gp,11 - 80002bac: 1bdf1863 bne t5,t4,80002d5c - -0000000080002bb0 : - 80002bb0: 800000b7 lui ra,0x80000 - 80002bb4: fff0809b addiw ra,ra,-1 - 80002bb8: 80008f13 addi t5,ra,-2048 # ffffffff7ffff800 <_end+0xfffffffeffff8010> - 80002bbc: 7ffffeb7 lui t4,0x7ffff - 80002bc0: 7ffe8e9b addiw t4,t4,2047 - 80002bc4: 00c00193 li gp,12 - 80002bc8: 19df1a63 bne t5,t4,80002d5c - -0000000080002bcc : - 80002bcc: 00000093 li ra,0 - 80002bd0: fff08f13 addi t5,ra,-1 - 80002bd4: fff00e93 li t4,-1 - 80002bd8: 00d00193 li gp,13 - 80002bdc: 19df1063 bne t5,t4,80002d5c - -0000000080002be0 : - 80002be0: fff00093 li ra,-1 - 80002be4: 00108f13 addi t5,ra,1 - 80002be8: 00000e93 li t4,0 - 80002bec: 00e00193 li gp,14 - 80002bf0: 17df1663 bne t5,t4,80002d5c - -0000000080002bf4 : - 80002bf4: fff00093 li ra,-1 - 80002bf8: fff08f13 addi t5,ra,-1 - 80002bfc: ffe00e93 li t4,-2 - 80002c00: 00f00193 li gp,15 - 80002c04: 15df1c63 bne t5,t4,80002d5c - -0000000080002c08 : - 80002c08: 800000b7 lui ra,0x80000 - 80002c0c: fff0809b addiw ra,ra,-1 - 80002c10: 00108f13 addi t5,ra,1 # ffffffff80000001 <_end+0xfffffffeffff8811> - 80002c14: 00100e9b addiw t4,zero,1 - 80002c18: 01fe9e93 slli t4,t4,0x1f - 80002c1c: 01000193 li gp,16 - 80002c20: 13df1e63 bne t5,t4,80002d5c - -0000000080002c24 : - 80002c24: 00d00093 li ra,13 - 80002c28: 00b08093 addi ra,ra,11 - 80002c2c: 01800e93 li t4,24 - 80002c30: 01100193 li gp,17 - 80002c34: 13d09463 bne ra,t4,80002d5c - -0000000080002c38 : - 80002c38: 00000213 li tp,0 - 80002c3c: 00d00093 li ra,13 - 80002c40: 00b08f13 addi t5,ra,11 - 80002c44: 000f0313 mv t1,t5 - 80002c48: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c4c: 00200293 li t0,2 - 80002c50: fe5216e3 bne tp,t0,80002c3c - 80002c54: 01800e93 li t4,24 - 80002c58: 01200193 li gp,18 - 80002c5c: 11d31063 bne t1,t4,80002d5c - -0000000080002c60 : - 80002c60: 00000213 li tp,0 - 80002c64: 00d00093 li ra,13 - 80002c68: 00a08f13 addi t5,ra,10 - 80002c6c: 00000013 nop - 80002c70: 000f0313 mv t1,t5 - 80002c74: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c78: 00200293 li t0,2 - 80002c7c: fe5214e3 bne tp,t0,80002c64 - 80002c80: 01700e93 li t4,23 - 80002c84: 01300193 li gp,19 - 80002c88: 0dd31a63 bne t1,t4,80002d5c - -0000000080002c8c : - 80002c8c: 00000213 li tp,0 - 80002c90: 00d00093 li ra,13 - 80002c94: 00908f13 addi t5,ra,9 - 80002c98: 00000013 nop - 80002c9c: 00000013 nop - 80002ca0: 000f0313 mv t1,t5 - 80002ca4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ca8: 00200293 li t0,2 - 80002cac: fe5212e3 bne tp,t0,80002c90 - 80002cb0: 01600e93 li t4,22 - 80002cb4: 01400193 li gp,20 - 80002cb8: 0bd31263 bne t1,t4,80002d5c - -0000000080002cbc : - 80002cbc: 00000213 li tp,0 - 80002cc0: 00d00093 li ra,13 - 80002cc4: 00b08f13 addi t5,ra,11 - 80002cc8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ccc: 00200293 li t0,2 - 80002cd0: fe5218e3 bne tp,t0,80002cc0 - 80002cd4: 01800e93 li t4,24 - 80002cd8: 01500193 li gp,21 - 80002cdc: 09df1063 bne t5,t4,80002d5c - -0000000080002ce0 : - 80002ce0: 00000213 li tp,0 - 80002ce4: 00d00093 li ra,13 - 80002ce8: 00000013 nop - 80002cec: 00a08f13 addi t5,ra,10 - 80002cf0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cf4: 00200293 li t0,2 - 80002cf8: fe5216e3 bne tp,t0,80002ce4 - 80002cfc: 01700e93 li t4,23 - 80002d00: 01600193 li gp,22 - 80002d04: 05df1c63 bne t5,t4,80002d5c - -0000000080002d08 : - 80002d08: 00000213 li tp,0 - 80002d0c: 00d00093 li ra,13 - 80002d10: 00000013 nop - 80002d14: 00000013 nop - 80002d18: 00908f13 addi t5,ra,9 - 80002d1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d20: 00200293 li t0,2 - 80002d24: fe5214e3 bne tp,t0,80002d0c - 80002d28: 01600e93 li t4,22 - 80002d2c: 01700193 li gp,23 - 80002d30: 03df1663 bne t5,t4,80002d5c - -0000000080002d34 : - 80002d34: 02000093 li ra,32 - 80002d38: 02000e93 li t4,32 - 80002d3c: 01800193 li gp,24 - 80002d40: 01d09e63 bne ra,t4,80002d5c - -0000000080002d44 : - 80002d44: 02100093 li ra,33 - 80002d48: 03208013 addi zero,ra,50 - 80002d4c: 00000e93 li t4,0 - 80002d50: 01900193 li gp,25 - 80002d54: 01d01463 bne zero,t4,80002d5c - 80002d58: 00301a63 bne zero,gp,80002d6c - -0000000080002d5c : - 80002d5c: 00119513 slli a0,gp,0x1 - 80002d60: 00050063 beqz a0,80002d60 - 80002d64: 00156513 ori a0,a0,1 - 80002d68: 00000073 ecall - -0000000080002d6c : - 80002d6c: 00100513 li a0,1 - 80002d70: 00000073 ecall - 80002d74: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-addi.elf b/test/riscv/tests/rv64ui-v-addi.elf deleted file mode 100644 index 28d8b889..00000000 Binary files a/test/riscv/tests/rv64ui-v-addi.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-addiw.dump b/test/riscv/tests/rv64ui-v-addiw.dump deleted file mode 100644 index d152915b..00000000 --- a/test/riscv/tests/rv64ui-v-addiw.dump +++ /dev/null @@ -1,1048 +0,0 @@ - -rv64ui-v-addiw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 91868693 addi a3,a3,-1768 # 80002d70 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 94c60613 addi a2,a2,-1716 # 80002e00 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 91460613 addi a2,a2,-1772 # 80002e18 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 86468693 addi a3,a3,-1948 # 80002db8 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 88068693 addi a3,a3,-1920 # 80002ef0 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 80060613 addi a2,a2,-2048 # 80002ec8 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 73468693 addi a3,a3,1844 # 80002f20 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 65468693 addi a3,a3,1620 # 80002e90 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 5e468693 addi a3,a3,1508 # 80002e58 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 00d00793 li a5,13 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 04c6e7b7 lui a5,0x4c6e - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 45678793 addi a5,a5,1110 # 4c6e456 <_start-0x7b391baa> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000093 li ra,0 - 80002acc: 00008f1b sext.w t5,ra - 80002ad0: 00000e93 li t4,0 - 80002ad4: 00200193 li gp,2 - 80002ad8: 27df1c63 bne t5,t4,80002d50 - -0000000080002adc : - 80002adc: 00100093 li ra,1 - 80002ae0: 00108f1b addiw t5,ra,1 - 80002ae4: 00200e93 li t4,2 - 80002ae8: 00300193 li gp,3 - 80002aec: 27df1263 bne t5,t4,80002d50 - -0000000080002af0 : - 80002af0: 00300093 li ra,3 - 80002af4: 00708f1b addiw t5,ra,7 - 80002af8: 00a00e93 li t4,10 - 80002afc: 00400193 li gp,4 - 80002b00: 25df1863 bne t5,t4,80002d50 - -0000000080002b04 : - 80002b04: 00000093 li ra,0 - 80002b08: 80008f1b addiw t5,ra,-2048 - 80002b0c: 80000e93 li t4,-2048 - 80002b10: 00500193 li gp,5 - 80002b14: 23df1e63 bne t5,t4,80002d50 - -0000000080002b18 : - 80002b18: 800000b7 lui ra,0x80000 - 80002b1c: 00008f1b sext.w t5,ra - 80002b20: 80000eb7 lui t4,0x80000 - 80002b24: 00600193 li gp,6 - 80002b28: 23df1463 bne t5,t4,80002d50 - -0000000080002b2c : - 80002b2c: 800000b7 lui ra,0x80000 - 80002b30: 80008f1b addiw t5,ra,-2048 - 80002b34: 80000eb7 lui t4,0x80000 - 80002b38: 800e8e9b addiw t4,t4,-2048 - 80002b3c: 00700193 li gp,7 - 80002b40: 21df1863 bne t5,t4,80002d50 - -0000000080002b44 : - 80002b44: 00000093 li ra,0 - 80002b48: 7ff08f1b addiw t5,ra,2047 - 80002b4c: 7ff00e93 li t4,2047 - 80002b50: 00800193 li gp,8 - 80002b54: 1fdf1e63 bne t5,t4,80002d50 - -0000000080002b58 : - 80002b58: 800000b7 lui ra,0x80000 - 80002b5c: fff0809b addiw ra,ra,-1 - 80002b60: 00008f1b sext.w t5,ra - 80002b64: 80000eb7 lui t4,0x80000 - 80002b68: fffe8e9b addiw t4,t4,-1 - 80002b6c: 00900193 li gp,9 - 80002b70: 1fdf1063 bne t5,t4,80002d50 - -0000000080002b74 : - 80002b74: 800000b7 lui ra,0x80000 - 80002b78: fff0809b addiw ra,ra,-1 - 80002b7c: 7ff08f1b addiw t5,ra,2047 - 80002b80: 80000eb7 lui t4,0x80000 - 80002b84: 7fee8e9b addiw t4,t4,2046 - 80002b88: 00a00193 li gp,10 - 80002b8c: 1ddf1263 bne t5,t4,80002d50 - -0000000080002b90 : - 80002b90: 800000b7 lui ra,0x80000 - 80002b94: 7ff08f1b addiw t5,ra,2047 - 80002b98: 80000eb7 lui t4,0x80000 - 80002b9c: 7ffe8e9b addiw t4,t4,2047 - 80002ba0: 00b00193 li gp,11 - 80002ba4: 1bdf1663 bne t5,t4,80002d50 - -0000000080002ba8 : - 80002ba8: 800000b7 lui ra,0x80000 - 80002bac: fff0809b addiw ra,ra,-1 - 80002bb0: 80008f1b addiw t5,ra,-2048 - 80002bb4: 7ffffeb7 lui t4,0x7ffff - 80002bb8: 7ffe8e9b addiw t4,t4,2047 - 80002bbc: 00c00193 li gp,12 - 80002bc0: 19df1863 bne t5,t4,80002d50 - -0000000080002bc4 : - 80002bc4: 00000093 li ra,0 - 80002bc8: fff08f1b addiw t5,ra,-1 - 80002bcc: fff00e93 li t4,-1 - 80002bd0: 00d00193 li gp,13 - 80002bd4: 17df1e63 bne t5,t4,80002d50 - -0000000080002bd8 : - 80002bd8: fff00093 li ra,-1 - 80002bdc: 00108f1b addiw t5,ra,1 - 80002be0: 00000e93 li t4,0 - 80002be4: 00e00193 li gp,14 - 80002be8: 17df1463 bne t5,t4,80002d50 - -0000000080002bec : - 80002bec: fff00093 li ra,-1 - 80002bf0: fff08f1b addiw t5,ra,-1 - 80002bf4: ffe00e93 li t4,-2 - 80002bf8: 00f00193 li gp,15 - 80002bfc: 15df1a63 bne t5,t4,80002d50 - -0000000080002c00 : - 80002c00: 800000b7 lui ra,0x80000 - 80002c04: fff0809b addiw ra,ra,-1 - 80002c08: 00108f1b addiw t5,ra,1 - 80002c0c: 80000eb7 lui t4,0x80000 - 80002c10: 01000193 li gp,16 - 80002c14: 13df1e63 bne t5,t4,80002d50 - -0000000080002c18 : - 80002c18: 00d00093 li ra,13 - 80002c1c: 00b0809b addiw ra,ra,11 - 80002c20: 01800e93 li t4,24 - 80002c24: 01100193 li gp,17 - 80002c28: 13d09463 bne ra,t4,80002d50 - -0000000080002c2c : - 80002c2c: 00000213 li tp,0 - 80002c30: 00d00093 li ra,13 - 80002c34: 00b08f1b addiw t5,ra,11 - 80002c38: 000f0313 mv t1,t5 - 80002c3c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c40: 00200293 li t0,2 - 80002c44: fe5216e3 bne tp,t0,80002c30 - 80002c48: 01800e93 li t4,24 - 80002c4c: 01200193 li gp,18 - 80002c50: 11d31063 bne t1,t4,80002d50 - -0000000080002c54 : - 80002c54: 00000213 li tp,0 - 80002c58: 00d00093 li ra,13 - 80002c5c: 00a08f1b addiw t5,ra,10 - 80002c60: 00000013 nop - 80002c64: 000f0313 mv t1,t5 - 80002c68: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c6c: 00200293 li t0,2 - 80002c70: fe5214e3 bne tp,t0,80002c58 - 80002c74: 01700e93 li t4,23 - 80002c78: 01300193 li gp,19 - 80002c7c: 0dd31a63 bne t1,t4,80002d50 - -0000000080002c80 : - 80002c80: 00000213 li tp,0 - 80002c84: 00d00093 li ra,13 - 80002c88: 00908f1b addiw t5,ra,9 - 80002c8c: 00000013 nop - 80002c90: 00000013 nop - 80002c94: 000f0313 mv t1,t5 - 80002c98: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c9c: 00200293 li t0,2 - 80002ca0: fe5212e3 bne tp,t0,80002c84 - 80002ca4: 01600e93 li t4,22 - 80002ca8: 01400193 li gp,20 - 80002cac: 0bd31263 bne t1,t4,80002d50 - -0000000080002cb0 : - 80002cb0: 00000213 li tp,0 - 80002cb4: 00d00093 li ra,13 - 80002cb8: 00b08f1b addiw t5,ra,11 - 80002cbc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cc0: 00200293 li t0,2 - 80002cc4: fe5218e3 bne tp,t0,80002cb4 - 80002cc8: 01800e93 li t4,24 - 80002ccc: 01500193 li gp,21 - 80002cd0: 09df1063 bne t5,t4,80002d50 - -0000000080002cd4 : - 80002cd4: 00000213 li tp,0 - 80002cd8: 00d00093 li ra,13 - 80002cdc: 00000013 nop - 80002ce0: 00a08f1b addiw t5,ra,10 - 80002ce4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ce8: 00200293 li t0,2 - 80002cec: fe5216e3 bne tp,t0,80002cd8 - 80002cf0: 01700e93 li t4,23 - 80002cf4: 01600193 li gp,22 - 80002cf8: 05df1c63 bne t5,t4,80002d50 - -0000000080002cfc : - 80002cfc: 00000213 li tp,0 - 80002d00: 00d00093 li ra,13 - 80002d04: 00000013 nop - 80002d08: 00000013 nop - 80002d0c: 00908f1b addiw t5,ra,9 - 80002d10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d14: 00200293 li t0,2 - 80002d18: fe5214e3 bne tp,t0,80002d00 - 80002d1c: 01600e93 li t4,22 - 80002d20: 01700193 li gp,23 - 80002d24: 03df1663 bne t5,t4,80002d50 - -0000000080002d28 : - 80002d28: 0200009b addiw ra,zero,32 - 80002d2c: 02000e93 li t4,32 - 80002d30: 01800193 li gp,24 - 80002d34: 01d09e63 bne ra,t4,80002d50 - -0000000080002d38 : - 80002d38: 02100093 li ra,33 - 80002d3c: 0320801b addiw zero,ra,50 - 80002d40: 00000e93 li t4,0 - 80002d44: 01900193 li gp,25 - 80002d48: 01d01463 bne zero,t4,80002d50 - 80002d4c: 00301a63 bne zero,gp,80002d60 - -0000000080002d50 : - 80002d50: 00119513 slli a0,gp,0x1 - 80002d54: 00050063 beqz a0,80002d54 - 80002d58: 00156513 ori a0,a0,1 - 80002d5c: 00000073 ecall - -0000000080002d60 : - 80002d60: 00100513 li a0,1 - 80002d64: 00000073 ecall - 80002d68: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-addiw.elf b/test/riscv/tests/rv64ui-v-addiw.elf deleted file mode 100644 index ddbea563..00000000 Binary files a/test/riscv/tests/rv64ui-v-addiw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-addw.dump b/test/riscv/tests/rv64ui-v-addw.dump deleted file mode 100644 index 838371b6..00000000 --- a/test/riscv/tests/rv64ui-v-addw.dump +++ /dev/null @@ -1,1224 +0,0 @@ - -rv64ui-v-addw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: b7068693 addi a3,a3,-1168 # 80002fc8 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: ba460613 addi a2,a2,-1116 # 80003058 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: b6c60613 addi a2,a2,-1172 # 80003070 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: abc68693 addi a3,a3,-1348 # 80003010 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: ad868693 addi a3,a3,-1320 # 80003148 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: a5860613 addi a2,a2,-1448 # 80003120 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: 98c68693 addi a3,a3,-1652 # 80003178 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 8ac68693 addi a3,a3,-1876 # 800030e8 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00001697 auipc a3,0x1 - 80002878: 83c68693 addi a3,a3,-1988 # 800030b0 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 00800793 li a5,8 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 04c367b7 lui a5,0x4c36 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 29178793 addi a5,a5,657 # 4c36291 <_start-0x7b3c9d6f> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000093 li ra,0 - 80002acc: 00000113 li sp,0 - 80002ad0: 00208f3b addw t5,ra,sp - 80002ad4: 00000e93 li t4,0 - 80002ad8: 00200193 li gp,2 - 80002adc: 4ddf1663 bne t5,t4,80002fa8 - -0000000080002ae0 : - 80002ae0: 00100093 li ra,1 - 80002ae4: 00100113 li sp,1 - 80002ae8: 00208f3b addw t5,ra,sp - 80002aec: 00200e93 li t4,2 - 80002af0: 00300193 li gp,3 - 80002af4: 4bdf1a63 bne t5,t4,80002fa8 - -0000000080002af8 : - 80002af8: 00300093 li ra,3 - 80002afc: 00700113 li sp,7 - 80002b00: 00208f3b addw t5,ra,sp - 80002b04: 00a00e93 li t4,10 - 80002b08: 00400193 li gp,4 - 80002b0c: 49df1e63 bne t5,t4,80002fa8 - -0000000080002b10 : - 80002b10: 00000093 li ra,0 - 80002b14: ffff8137 lui sp,0xffff8 - 80002b18: 00208f3b addw t5,ra,sp - 80002b1c: ffff8eb7 lui t4,0xffff8 - 80002b20: 00500193 li gp,5 - 80002b24: 49df1263 bne t5,t4,80002fa8 - -0000000080002b28 : - 80002b28: 800000b7 lui ra,0x80000 - 80002b2c: 00000113 li sp,0 - 80002b30: 00208f3b addw t5,ra,sp - 80002b34: 80000eb7 lui t4,0x80000 - 80002b38: 00600193 li gp,6 - 80002b3c: 47df1663 bne t5,t4,80002fa8 - -0000000080002b40 : - 80002b40: 800000b7 lui ra,0x80000 - 80002b44: ffff8137 lui sp,0xffff8 - 80002b48: 00208f3b addw t5,ra,sp - 80002b4c: 7fff8eb7 lui t4,0x7fff8 - 80002b50: 00700193 li gp,7 - 80002b54: 45df1a63 bne t5,t4,80002fa8 - -0000000080002b58 : - 80002b58: 00000093 li ra,0 - 80002b5c: 00008137 lui sp,0x8 - 80002b60: fff1011b addiw sp,sp,-1 - 80002b64: 00208f3b addw t5,ra,sp - 80002b68: 00008eb7 lui t4,0x8 - 80002b6c: fffe8e9b addiw t4,t4,-1 - 80002b70: 00800193 li gp,8 - 80002b74: 43df1a63 bne t5,t4,80002fa8 - -0000000080002b78 : - 80002b78: 800000b7 lui ra,0x80000 - 80002b7c: fff0809b addiw ra,ra,-1 - 80002b80: 00000113 li sp,0 - 80002b84: 00208f3b addw t5,ra,sp - 80002b88: 80000eb7 lui t4,0x80000 - 80002b8c: fffe8e9b addiw t4,t4,-1 - 80002b90: 00900193 li gp,9 - 80002b94: 41df1a63 bne t5,t4,80002fa8 - -0000000080002b98 : - 80002b98: 800000b7 lui ra,0x80000 - 80002b9c: fff0809b addiw ra,ra,-1 - 80002ba0: 00008137 lui sp,0x8 - 80002ba4: fff1011b addiw sp,sp,-1 - 80002ba8: 00208f3b addw t5,ra,sp - 80002bac: 80008eb7 lui t4,0x80008 - 80002bb0: ffee8e9b addiw t4,t4,-2 - 80002bb4: 00a00193 li gp,10 - 80002bb8: 3fdf1863 bne t5,t4,80002fa8 - -0000000080002bbc : - 80002bbc: 800000b7 lui ra,0x80000 - 80002bc0: 00008137 lui sp,0x8 - 80002bc4: fff1011b addiw sp,sp,-1 - 80002bc8: 00208f3b addw t5,ra,sp - 80002bcc: 80008eb7 lui t4,0x80008 - 80002bd0: fffe8e9b addiw t4,t4,-1 - 80002bd4: 00b00193 li gp,11 - 80002bd8: 3ddf1863 bne t5,t4,80002fa8 - -0000000080002bdc : - 80002bdc: 800000b7 lui ra,0x80000 - 80002be0: fff0809b addiw ra,ra,-1 - 80002be4: ffff8137 lui sp,0xffff8 - 80002be8: 00208f3b addw t5,ra,sp - 80002bec: 7fff8eb7 lui t4,0x7fff8 - 80002bf0: fffe8e9b addiw t4,t4,-1 - 80002bf4: 00c00193 li gp,12 - 80002bf8: 3bdf1863 bne t5,t4,80002fa8 - -0000000080002bfc : - 80002bfc: 00000093 li ra,0 - 80002c00: fff00113 li sp,-1 - 80002c04: 00208f3b addw t5,ra,sp - 80002c08: fff00e93 li t4,-1 - 80002c0c: 00d00193 li gp,13 - 80002c10: 39df1c63 bne t5,t4,80002fa8 - -0000000080002c14 : - 80002c14: fff00093 li ra,-1 - 80002c18: 00100113 li sp,1 - 80002c1c: 00208f3b addw t5,ra,sp - 80002c20: 00000e93 li t4,0 - 80002c24: 00e00193 li gp,14 - 80002c28: 39df1063 bne t5,t4,80002fa8 - -0000000080002c2c : - 80002c2c: fff00093 li ra,-1 - 80002c30: fff00113 li sp,-1 - 80002c34: 00208f3b addw t5,ra,sp - 80002c38: ffe00e93 li t4,-2 - 80002c3c: 00f00193 li gp,15 - 80002c40: 37df1463 bne t5,t4,80002fa8 - -0000000080002c44 : - 80002c44: 00100093 li ra,1 - 80002c48: 80000137 lui sp,0x80000 - 80002c4c: fff1011b addiw sp,sp,-1 - 80002c50: 00208f3b addw t5,ra,sp - 80002c54: 80000eb7 lui t4,0x80000 - 80002c58: 01000193 li gp,16 - 80002c5c: 35df1663 bne t5,t4,80002fa8 - -0000000080002c60 : - 80002c60: 00d00093 li ra,13 - 80002c64: 00b00113 li sp,11 - 80002c68: 002080bb addw ra,ra,sp - 80002c6c: 01800e93 li t4,24 - 80002c70: 01100193 li gp,17 - 80002c74: 33d09a63 bne ra,t4,80002fa8 - -0000000080002c78 : - 80002c78: 00e00093 li ra,14 - 80002c7c: 00b00113 li sp,11 - 80002c80: 0020813b addw sp,ra,sp - 80002c84: 01900e93 li t4,25 - 80002c88: 01200193 li gp,18 - 80002c8c: 31d11e63 bne sp,t4,80002fa8 - -0000000080002c90 : - 80002c90: 00d00093 li ra,13 - 80002c94: 001080bb addw ra,ra,ra - 80002c98: 01a00e93 li t4,26 - 80002c9c: 01300193 li gp,19 - 80002ca0: 31d09463 bne ra,t4,80002fa8 - -0000000080002ca4 : - 80002ca4: 00000213 li tp,0 - 80002ca8: 00d00093 li ra,13 - 80002cac: 00b00113 li sp,11 - 80002cb0: 00208f3b addw t5,ra,sp - 80002cb4: 000f0313 mv t1,t5 - 80002cb8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cbc: 00200293 li t0,2 - 80002cc0: fe5214e3 bne tp,t0,80002ca8 - 80002cc4: 01800e93 li t4,24 - 80002cc8: 01400193 li gp,20 - 80002ccc: 2dd31e63 bne t1,t4,80002fa8 - -0000000080002cd0 : - 80002cd0: 00000213 li tp,0 - 80002cd4: 00e00093 li ra,14 - 80002cd8: 00b00113 li sp,11 - 80002cdc: 00208f3b addw t5,ra,sp - 80002ce0: 00000013 nop - 80002ce4: 000f0313 mv t1,t5 - 80002ce8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cec: 00200293 li t0,2 - 80002cf0: fe5212e3 bne tp,t0,80002cd4 - 80002cf4: 01900e93 li t4,25 - 80002cf8: 01500193 li gp,21 - 80002cfc: 2bd31663 bne t1,t4,80002fa8 - -0000000080002d00 : - 80002d00: 00000213 li tp,0 - 80002d04: 00f00093 li ra,15 - 80002d08: 00b00113 li sp,11 - 80002d0c: 00208f3b addw t5,ra,sp - 80002d10: 00000013 nop - 80002d14: 00000013 nop - 80002d18: 000f0313 mv t1,t5 - 80002d1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d20: 00200293 li t0,2 - 80002d24: fe5210e3 bne tp,t0,80002d04 - 80002d28: 01a00e93 li t4,26 - 80002d2c: 01600193 li gp,22 - 80002d30: 27d31c63 bne t1,t4,80002fa8 - -0000000080002d34 : - 80002d34: 00000213 li tp,0 - 80002d38: 00d00093 li ra,13 - 80002d3c: 00b00113 li sp,11 - 80002d40: 00208f3b addw t5,ra,sp - 80002d44: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d48: 00200293 li t0,2 - 80002d4c: fe5216e3 bne tp,t0,80002d38 - 80002d50: 01800e93 li t4,24 - 80002d54: 01700193 li gp,23 - 80002d58: 25df1863 bne t5,t4,80002fa8 - -0000000080002d5c : - 80002d5c: 00000213 li tp,0 - 80002d60: 00e00093 li ra,14 - 80002d64: 00b00113 li sp,11 - 80002d68: 00000013 nop - 80002d6c: 00208f3b addw t5,ra,sp - 80002d70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d74: 00200293 li t0,2 - 80002d78: fe5214e3 bne tp,t0,80002d60 - 80002d7c: 01900e93 li t4,25 - 80002d80: 01800193 li gp,24 - 80002d84: 23df1263 bne t5,t4,80002fa8 - -0000000080002d88 : - 80002d88: 00000213 li tp,0 - 80002d8c: 00f00093 li ra,15 - 80002d90: 00b00113 li sp,11 - 80002d94: 00000013 nop - 80002d98: 00000013 nop - 80002d9c: 00208f3b addw t5,ra,sp - 80002da0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002da4: 00200293 li t0,2 - 80002da8: fe5212e3 bne tp,t0,80002d8c - 80002dac: 01a00e93 li t4,26 - 80002db0: 01900193 li gp,25 - 80002db4: 1fdf1a63 bne t5,t4,80002fa8 - -0000000080002db8 : - 80002db8: 00000213 li tp,0 - 80002dbc: 00d00093 li ra,13 - 80002dc0: 00000013 nop - 80002dc4: 00b00113 li sp,11 - 80002dc8: 00208f3b addw t5,ra,sp - 80002dcc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dd0: 00200293 li t0,2 - 80002dd4: fe5214e3 bne tp,t0,80002dbc - 80002dd8: 01800e93 li t4,24 - 80002ddc: 01a00193 li gp,26 - 80002de0: 1ddf1463 bne t5,t4,80002fa8 - -0000000080002de4 : - 80002de4: 00000213 li tp,0 - 80002de8: 00e00093 li ra,14 - 80002dec: 00000013 nop - 80002df0: 00b00113 li sp,11 - 80002df4: 00000013 nop - 80002df8: 00208f3b addw t5,ra,sp - 80002dfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e00: 00200293 li t0,2 - 80002e04: fe5212e3 bne tp,t0,80002de8 - 80002e08: 01900e93 li t4,25 - 80002e0c: 01b00193 li gp,27 - 80002e10: 19df1c63 bne t5,t4,80002fa8 - -0000000080002e14 : - 80002e14: 00000213 li tp,0 - 80002e18: 00f00093 li ra,15 - 80002e1c: 00000013 nop - 80002e20: 00000013 nop - 80002e24: 00b00113 li sp,11 - 80002e28: 00208f3b addw t5,ra,sp - 80002e2c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e30: 00200293 li t0,2 - 80002e34: fe5212e3 bne tp,t0,80002e18 - 80002e38: 01a00e93 li t4,26 - 80002e3c: 01c00193 li gp,28 - 80002e40: 17df1463 bne t5,t4,80002fa8 - -0000000080002e44 : - 80002e44: 00000213 li tp,0 - 80002e48: 00b00113 li sp,11 - 80002e4c: 00d00093 li ra,13 - 80002e50: 00208f3b addw t5,ra,sp - 80002e54: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e58: 00200293 li t0,2 - 80002e5c: fe5216e3 bne tp,t0,80002e48 - 80002e60: 01800e93 li t4,24 - 80002e64: 01d00193 li gp,29 - 80002e68: 15df1063 bne t5,t4,80002fa8 - -0000000080002e6c : - 80002e6c: 00000213 li tp,0 - 80002e70: 00b00113 li sp,11 - 80002e74: 00e00093 li ra,14 - 80002e78: 00000013 nop - 80002e7c: 00208f3b addw t5,ra,sp - 80002e80: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e84: 00200293 li t0,2 - 80002e88: fe5214e3 bne tp,t0,80002e70 - 80002e8c: 01900e93 li t4,25 - 80002e90: 01e00193 li gp,30 - 80002e94: 11df1a63 bne t5,t4,80002fa8 - -0000000080002e98 : - 80002e98: 00000213 li tp,0 - 80002e9c: 00b00113 li sp,11 - 80002ea0: 00f00093 li ra,15 - 80002ea4: 00000013 nop - 80002ea8: 00000013 nop - 80002eac: 00208f3b addw t5,ra,sp - 80002eb0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002eb4: 00200293 li t0,2 - 80002eb8: fe5212e3 bne tp,t0,80002e9c - 80002ebc: 01a00e93 li t4,26 - 80002ec0: 01f00193 li gp,31 - 80002ec4: 0fdf1263 bne t5,t4,80002fa8 - -0000000080002ec8 : - 80002ec8: 00000213 li tp,0 - 80002ecc: 00b00113 li sp,11 - 80002ed0: 00000013 nop - 80002ed4: 00d00093 li ra,13 - 80002ed8: 00208f3b addw t5,ra,sp - 80002edc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ee0: 00200293 li t0,2 - 80002ee4: fe5214e3 bne tp,t0,80002ecc - 80002ee8: 01800e93 li t4,24 - 80002eec: 02000193 li gp,32 - 80002ef0: 0bdf1c63 bne t5,t4,80002fa8 - -0000000080002ef4 : - 80002ef4: 00000213 li tp,0 - 80002ef8: 00b00113 li sp,11 - 80002efc: 00000013 nop - 80002f00: 00e00093 li ra,14 - 80002f04: 00000013 nop - 80002f08: 00208f3b addw t5,ra,sp - 80002f0c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f10: 00200293 li t0,2 - 80002f14: fe5212e3 bne tp,t0,80002ef8 - 80002f18: 01900e93 li t4,25 - 80002f1c: 02100193 li gp,33 - 80002f20: 09df1463 bne t5,t4,80002fa8 - -0000000080002f24 : - 80002f24: 00000213 li tp,0 - 80002f28: 00b00113 li sp,11 - 80002f2c: 00000013 nop - 80002f30: 00000013 nop - 80002f34: 00f00093 li ra,15 - 80002f38: 00208f3b addw t5,ra,sp - 80002f3c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f40: 00200293 li t0,2 - 80002f44: fe5212e3 bne tp,t0,80002f28 - 80002f48: 01a00e93 li t4,26 - 80002f4c: 02200193 li gp,34 - 80002f50: 05df1c63 bne t5,t4,80002fa8 - -0000000080002f54 : - 80002f54: 00f00093 li ra,15 - 80002f58: 0010013b addw sp,zero,ra - 80002f5c: 00f00e93 li t4,15 - 80002f60: 02300193 li gp,35 - 80002f64: 05d11263 bne sp,t4,80002fa8 - -0000000080002f68 : - 80002f68: 02000093 li ra,32 - 80002f6c: 0000813b addw sp,ra,zero - 80002f70: 02000e93 li t4,32 - 80002f74: 02400193 li gp,36 - 80002f78: 03d11863 bne sp,t4,80002fa8 - -0000000080002f7c : - 80002f7c: 000000bb addw ra,zero,zero - 80002f80: 00000e93 li t4,0 - 80002f84: 02500193 li gp,37 - 80002f88: 03d09063 bne ra,t4,80002fa8 - -0000000080002f8c : - 80002f8c: 01000093 li ra,16 - 80002f90: 01e00113 li sp,30 - 80002f94: 0020803b addw zero,ra,sp - 80002f98: 00000e93 li t4,0 - 80002f9c: 02600193 li gp,38 - 80002fa0: 01d01463 bne zero,t4,80002fa8 - 80002fa4: 00301a63 bne zero,gp,80002fb8 - -0000000080002fa8 : - 80002fa8: 00119513 slli a0,gp,0x1 - 80002fac: 00050063 beqz a0,80002fac - 80002fb0: 00156513 ori a0,a0,1 - 80002fb4: 00000073 ecall - -0000000080002fb8 : - 80002fb8: 00100513 li a0,1 - 80002fbc: 00000073 ecall - 80002fc0: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-addw.elf b/test/riscv/tests/rv64ui-v-addw.elf deleted file mode 100644 index e78ff7a7..00000000 Binary files a/test/riscv/tests/rv64ui-v-addw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-and.dump b/test/riscv/tests/rv64ui-v-and.dump deleted file mode 100644 index 063fbeb1..00000000 --- a/test/riscv/tests/rv64ui-v-and.dump +++ /dev/null @@ -1,1232 +0,0 @@ - -rv64ui-v-and: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: be868693 addi a3,a3,-1048 # 80003040 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: c1c60613 addi a2,a2,-996 # 800030d0 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: be460613 addi a2,a2,-1052 # 800030e8 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: b3468693 addi a3,a3,-1228 # 80003088 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: b5068693 addi a3,a3,-1200 # 800031c0 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: ad060613 addi a2,a2,-1328 # 80003198 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: a0468693 addi a3,a3,-1532 # 800031f0 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 92468693 addi a3,a3,-1756 # 80003160 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00001697 auipc a3,0x1 - 80002878: 8b468693 addi a3,a3,-1868 # 80003128 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 01200793 li a5,18 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0a1787b7 lui a5,0xa178 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 4b678793 addi a5,a5,1206 # a1784b6 <_start-0x75e87b4a> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 000100b7 lui ra,0x10 - 80002acc: f010809b addiw ra,ra,-255 - 80002ad0: 01009093 slli ra,ra,0x10 - 80002ad4: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002ad8: 0f0f1137 lui sp,0xf0f1 - 80002adc: f0f1011b addiw sp,sp,-241 - 80002ae0: 0020ff33 and t5,ra,sp - 80002ae4: 0f001eb7 lui t4,0xf001 - 80002ae8: f00e8e9b addiw t4,t4,-256 - 80002aec: 00200193 li gp,2 - 80002af0: 53df1863 bne t5,t4,80003020 - -0000000080002af4 : - 80002af4: 0ff010b7 lui ra,0xff01 - 80002af8: ff00809b addiw ra,ra,-16 - 80002afc: 000f1137 lui sp,0xf1 - 80002b00: f0f1011b addiw sp,sp,-241 - 80002b04: 00c11113 slli sp,sp,0xc - 80002b08: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002b0c: 0020ff33 and t5,ra,sp - 80002b10: 00f00eb7 lui t4,0xf00 - 80002b14: 0f0e8e9b addiw t4,t4,240 - 80002b18: 00300193 li gp,3 - 80002b1c: 51df1263 bne t5,t4,80003020 - -0000000080002b20 : - 80002b20: 00ff00b7 lui ra,0xff0 - 80002b24: 0ff0809b addiw ra,ra,255 - 80002b28: 0f0f1137 lui sp,0xf0f1 - 80002b2c: f0f1011b addiw sp,sp,-241 - 80002b30: 0020ff33 and t5,ra,sp - 80002b34: 000f0eb7 lui t4,0xf0 - 80002b38: 00fe8e9b addiw t4,t4,15 - 80002b3c: 00400193 li gp,4 - 80002b40: 4fdf1063 bne t5,t4,80003020 - -0000000080002b44 : - 80002b44: 000f00b7 lui ra,0xf0 - 80002b48: 0ff0809b addiw ra,ra,255 - 80002b4c: 00c09093 slli ra,ra,0xc - 80002b50: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> - 80002b54: 000f1137 lui sp,0xf1 - 80002b58: f0f1011b addiw sp,sp,-241 - 80002b5c: 00c11113 slli sp,sp,0xc - 80002b60: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002b64: 0020ff33 and t5,ra,sp - 80002b68: 000f0eb7 lui t4,0xf0 - 80002b6c: 00fe8e9b addiw t4,t4,15 - 80002b70: 00ce9e93 slli t4,t4,0xc - 80002b74: 00500193 li gp,5 - 80002b78: 4bdf1463 bne t5,t4,80003020 - -0000000080002b7c : - 80002b7c: 000100b7 lui ra,0x10 - 80002b80: f010809b addiw ra,ra,-255 - 80002b84: 01009093 slli ra,ra,0x10 - 80002b88: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002b8c: 0f0f1137 lui sp,0xf0f1 - 80002b90: f0f1011b addiw sp,sp,-241 - 80002b94: 0020f0b3 and ra,ra,sp - 80002b98: 0f001eb7 lui t4,0xf001 - 80002b9c: f00e8e9b addiw t4,t4,-256 - 80002ba0: 00600193 li gp,6 - 80002ba4: 47d09e63 bne ra,t4,80003020 - -0000000080002ba8 : - 80002ba8: 0ff010b7 lui ra,0xff01 - 80002bac: ff00809b addiw ra,ra,-16 - 80002bb0: 000f1137 lui sp,0xf1 - 80002bb4: f0f1011b addiw sp,sp,-241 - 80002bb8: 00c11113 slli sp,sp,0xc - 80002bbc: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002bc0: 0020f133 and sp,ra,sp - 80002bc4: 00f00eb7 lui t4,0xf00 - 80002bc8: 0f0e8e9b addiw t4,t4,240 - 80002bcc: 00700193 li gp,7 - 80002bd0: 45d11863 bne sp,t4,80003020 - -0000000080002bd4 : - 80002bd4: 000100b7 lui ra,0x10 - 80002bd8: f010809b addiw ra,ra,-255 - 80002bdc: 01009093 slli ra,ra,0x10 - 80002be0: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002be4: 0010f0b3 and ra,ra,ra - 80002be8: 00010eb7 lui t4,0x10 - 80002bec: f01e8e9b addiw t4,t4,-255 - 80002bf0: 010e9e93 slli t4,t4,0x10 - 80002bf4: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80002bf8: 00800193 li gp,8 - 80002bfc: 43d09263 bne ra,t4,80003020 - -0000000080002c00 : - 80002c00: 00000213 li tp,0 - 80002c04: 000100b7 lui ra,0x10 - 80002c08: f010809b addiw ra,ra,-255 - 80002c0c: 01009093 slli ra,ra,0x10 - 80002c10: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002c14: 0f0f1137 lui sp,0xf0f1 - 80002c18: f0f1011b addiw sp,sp,-241 - 80002c1c: 0020ff33 and t5,ra,sp - 80002c20: 000f0313 mv t1,t5 - 80002c24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c28: 00200293 li t0,2 - 80002c2c: fc521ce3 bne tp,t0,80002c04 - 80002c30: 0f001eb7 lui t4,0xf001 - 80002c34: f00e8e9b addiw t4,t4,-256 - 80002c38: 00900193 li gp,9 - 80002c3c: 3fd31263 bne t1,t4,80003020 - -0000000080002c40 : - 80002c40: 00000213 li tp,0 - 80002c44: 0ff010b7 lui ra,0xff01 - 80002c48: ff00809b addiw ra,ra,-16 - 80002c4c: 000f1137 lui sp,0xf1 - 80002c50: f0f1011b addiw sp,sp,-241 - 80002c54: 00c11113 slli sp,sp,0xc - 80002c58: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002c5c: 0020ff33 and t5,ra,sp - 80002c60: 00000013 nop - 80002c64: 000f0313 mv t1,t5 - 80002c68: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c6c: 00200293 li t0,2 - 80002c70: fc521ae3 bne tp,t0,80002c44 - 80002c74: 00f00eb7 lui t4,0xf00 - 80002c78: 0f0e8e9b addiw t4,t4,240 - 80002c7c: 00a00193 li gp,10 - 80002c80: 3bd31063 bne t1,t4,80003020 - -0000000080002c84 : - 80002c84: 00000213 li tp,0 - 80002c88: 00ff00b7 lui ra,0xff0 - 80002c8c: 0ff0809b addiw ra,ra,255 - 80002c90: 0f0f1137 lui sp,0xf0f1 - 80002c94: f0f1011b addiw sp,sp,-241 - 80002c98: 0020ff33 and t5,ra,sp - 80002c9c: 00000013 nop - 80002ca0: 00000013 nop - 80002ca4: 000f0313 mv t1,t5 - 80002ca8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cac: 00200293 li t0,2 - 80002cb0: fc521ce3 bne tp,t0,80002c88 - 80002cb4: 000f0eb7 lui t4,0xf0 - 80002cb8: 00fe8e9b addiw t4,t4,15 - 80002cbc: 00b00193 li gp,11 - 80002cc0: 37d31063 bne t1,t4,80003020 - -0000000080002cc4 : - 80002cc4: 00000213 li tp,0 - 80002cc8: 000100b7 lui ra,0x10 - 80002ccc: f010809b addiw ra,ra,-255 - 80002cd0: 01009093 slli ra,ra,0x10 - 80002cd4: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002cd8: 0f0f1137 lui sp,0xf0f1 - 80002cdc: f0f1011b addiw sp,sp,-241 - 80002ce0: 0020ff33 and t5,ra,sp - 80002ce4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ce8: 00200293 li t0,2 - 80002cec: fc521ee3 bne tp,t0,80002cc8 - 80002cf0: 0f001eb7 lui t4,0xf001 - 80002cf4: f00e8e9b addiw t4,t4,-256 - 80002cf8: 00c00193 li gp,12 - 80002cfc: 33df1263 bne t5,t4,80003020 - -0000000080002d00 : - 80002d00: 00000213 li tp,0 - 80002d04: 0ff010b7 lui ra,0xff01 - 80002d08: ff00809b addiw ra,ra,-16 - 80002d0c: 000f1137 lui sp,0xf1 - 80002d10: f0f1011b addiw sp,sp,-241 - 80002d14: 00c11113 slli sp,sp,0xc - 80002d18: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002d1c: 00000013 nop - 80002d20: 0020ff33 and t5,ra,sp - 80002d24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d28: 00200293 li t0,2 - 80002d2c: fc521ce3 bne tp,t0,80002d04 - 80002d30: 00f00eb7 lui t4,0xf00 - 80002d34: 0f0e8e9b addiw t4,t4,240 - 80002d38: 00d00193 li gp,13 - 80002d3c: 2fdf1263 bne t5,t4,80003020 - -0000000080002d40 : - 80002d40: 00000213 li tp,0 - 80002d44: 00ff00b7 lui ra,0xff0 - 80002d48: 0ff0809b addiw ra,ra,255 - 80002d4c: 0f0f1137 lui sp,0xf0f1 - 80002d50: f0f1011b addiw sp,sp,-241 - 80002d54: 00000013 nop - 80002d58: 00000013 nop - 80002d5c: 0020ff33 and t5,ra,sp - 80002d60: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d64: 00200293 li t0,2 - 80002d68: fc521ee3 bne tp,t0,80002d44 - 80002d6c: 000f0eb7 lui t4,0xf0 - 80002d70: 00fe8e9b addiw t4,t4,15 - 80002d74: 00e00193 li gp,14 - 80002d78: 2bdf1463 bne t5,t4,80003020 - -0000000080002d7c : - 80002d7c: 00000213 li tp,0 - 80002d80: 000100b7 lui ra,0x10 - 80002d84: f010809b addiw ra,ra,-255 - 80002d88: 01009093 slli ra,ra,0x10 - 80002d8c: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002d90: 00000013 nop - 80002d94: 0f0f1137 lui sp,0xf0f1 - 80002d98: f0f1011b addiw sp,sp,-241 - 80002d9c: 0020ff33 and t5,ra,sp - 80002da0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002da4: 00200293 li t0,2 - 80002da8: fc521ce3 bne tp,t0,80002d80 - 80002dac: 0f001eb7 lui t4,0xf001 - 80002db0: f00e8e9b addiw t4,t4,-256 - 80002db4: 00f00193 li gp,15 - 80002db8: 27df1463 bne t5,t4,80003020 - -0000000080002dbc : - 80002dbc: 00000213 li tp,0 - 80002dc0: 0ff010b7 lui ra,0xff01 - 80002dc4: ff00809b addiw ra,ra,-16 - 80002dc8: 00000013 nop - 80002dcc: 000f1137 lui sp,0xf1 - 80002dd0: f0f1011b addiw sp,sp,-241 - 80002dd4: 00c11113 slli sp,sp,0xc - 80002dd8: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002ddc: 00000013 nop - 80002de0: 0020ff33 and t5,ra,sp - 80002de4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002de8: 00200293 li t0,2 - 80002dec: fc521ae3 bne tp,t0,80002dc0 - 80002df0: 00f00eb7 lui t4,0xf00 - 80002df4: 0f0e8e9b addiw t4,t4,240 - 80002df8: 01000193 li gp,16 - 80002dfc: 23df1263 bne t5,t4,80003020 - -0000000080002e00 : - 80002e00: 00000213 li tp,0 - 80002e04: 00ff00b7 lui ra,0xff0 - 80002e08: 0ff0809b addiw ra,ra,255 - 80002e0c: 00000013 nop - 80002e10: 00000013 nop - 80002e14: 0f0f1137 lui sp,0xf0f1 - 80002e18: f0f1011b addiw sp,sp,-241 - 80002e1c: 0020ff33 and t5,ra,sp - 80002e20: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e24: 00200293 li t0,2 - 80002e28: fc521ee3 bne tp,t0,80002e04 - 80002e2c: 000f0eb7 lui t4,0xf0 - 80002e30: 00fe8e9b addiw t4,t4,15 - 80002e34: 01100193 li gp,17 - 80002e38: 1fdf1463 bne t5,t4,80003020 - -0000000080002e3c : - 80002e3c: 00000213 li tp,0 - 80002e40: 0f0f1137 lui sp,0xf0f1 - 80002e44: f0f1011b addiw sp,sp,-241 - 80002e48: 000100b7 lui ra,0x10 - 80002e4c: f010809b addiw ra,ra,-255 - 80002e50: 01009093 slli ra,ra,0x10 - 80002e54: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002e58: 0020ff33 and t5,ra,sp - 80002e5c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e60: 00200293 li t0,2 - 80002e64: fc521ee3 bne tp,t0,80002e40 - 80002e68: 0f001eb7 lui t4,0xf001 - 80002e6c: f00e8e9b addiw t4,t4,-256 - 80002e70: 01200193 li gp,18 - 80002e74: 1bdf1663 bne t5,t4,80003020 - -0000000080002e78 : - 80002e78: 00000213 li tp,0 - 80002e7c: 000f1137 lui sp,0xf1 - 80002e80: f0f1011b addiw sp,sp,-241 - 80002e84: 00c11113 slli sp,sp,0xc - 80002e88: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002e8c: 0ff010b7 lui ra,0xff01 - 80002e90: ff00809b addiw ra,ra,-16 - 80002e94: 00000013 nop - 80002e98: 0020ff33 and t5,ra,sp - 80002e9c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ea0: 00200293 li t0,2 - 80002ea4: fc521ce3 bne tp,t0,80002e7c - 80002ea8: 00f00eb7 lui t4,0xf00 - 80002eac: 0f0e8e9b addiw t4,t4,240 - 80002eb0: 01300193 li gp,19 - 80002eb4: 17df1663 bne t5,t4,80003020 - -0000000080002eb8 : - 80002eb8: 00000213 li tp,0 - 80002ebc: 0f0f1137 lui sp,0xf0f1 - 80002ec0: f0f1011b addiw sp,sp,-241 - 80002ec4: 00ff00b7 lui ra,0xff0 - 80002ec8: 0ff0809b addiw ra,ra,255 - 80002ecc: 00000013 nop - 80002ed0: 00000013 nop - 80002ed4: 0020ff33 and t5,ra,sp - 80002ed8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002edc: 00200293 li t0,2 - 80002ee0: fc521ee3 bne tp,t0,80002ebc - 80002ee4: 000f0eb7 lui t4,0xf0 - 80002ee8: 00fe8e9b addiw t4,t4,15 - 80002eec: 01400193 li gp,20 - 80002ef0: 13df1863 bne t5,t4,80003020 - -0000000080002ef4 : - 80002ef4: 00000213 li tp,0 - 80002ef8: 0f0f1137 lui sp,0xf0f1 - 80002efc: f0f1011b addiw sp,sp,-241 - 80002f00: 00000013 nop - 80002f04: 000100b7 lui ra,0x10 - 80002f08: f010809b addiw ra,ra,-255 - 80002f0c: 01009093 slli ra,ra,0x10 - 80002f10: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002f14: 0020ff33 and t5,ra,sp - 80002f18: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f1c: 00200293 li t0,2 - 80002f20: fc521ce3 bne tp,t0,80002ef8 - 80002f24: 0f001eb7 lui t4,0xf001 - 80002f28: f00e8e9b addiw t4,t4,-256 - 80002f2c: 01500193 li gp,21 - 80002f30: 0fdf1863 bne t5,t4,80003020 - -0000000080002f34 : - 80002f34: 00000213 li tp,0 - 80002f38: 000f1137 lui sp,0xf1 - 80002f3c: f0f1011b addiw sp,sp,-241 - 80002f40: 00c11113 slli sp,sp,0xc - 80002f44: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002f48: 00000013 nop - 80002f4c: 0ff010b7 lui ra,0xff01 - 80002f50: ff00809b addiw ra,ra,-16 - 80002f54: 00000013 nop - 80002f58: 0020ff33 and t5,ra,sp - 80002f5c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f60: 00200293 li t0,2 - 80002f64: fc521ae3 bne tp,t0,80002f38 - 80002f68: 00f00eb7 lui t4,0xf00 - 80002f6c: 0f0e8e9b addiw t4,t4,240 - 80002f70: 01600193 li gp,22 - 80002f74: 0bdf1663 bne t5,t4,80003020 - -0000000080002f78 : - 80002f78: 00000213 li tp,0 - 80002f7c: 0f0f1137 lui sp,0xf0f1 - 80002f80: f0f1011b addiw sp,sp,-241 - 80002f84: 00000013 nop - 80002f88: 00000013 nop - 80002f8c: 00ff00b7 lui ra,0xff0 - 80002f90: 0ff0809b addiw ra,ra,255 - 80002f94: 0020ff33 and t5,ra,sp - 80002f98: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f9c: 00200293 li t0,2 - 80002fa0: fc521ee3 bne tp,t0,80002f7c - 80002fa4: 000f0eb7 lui t4,0xf0 - 80002fa8: 00fe8e9b addiw t4,t4,15 - 80002fac: 01700193 li gp,23 - 80002fb0: 07df1863 bne t5,t4,80003020 - -0000000080002fb4 : - 80002fb4: 000100b7 lui ra,0x10 - 80002fb8: f010809b addiw ra,ra,-255 - 80002fbc: 01009093 slli ra,ra,0x10 - 80002fc0: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002fc4: 00107133 and sp,zero,ra - 80002fc8: 00000e93 li t4,0 - 80002fcc: 01800193 li gp,24 - 80002fd0: 05d11863 bne sp,t4,80003020 - -0000000080002fd4 : - 80002fd4: 00ff00b7 lui ra,0xff0 - 80002fd8: 0ff0809b addiw ra,ra,255 - 80002fdc: 0000f133 and sp,ra,zero - 80002fe0: 00000e93 li t4,0 - 80002fe4: 01900193 li gp,25 - 80002fe8: 03d11c63 bne sp,t4,80003020 - -0000000080002fec : - 80002fec: 000070b3 and ra,zero,zero - 80002ff0: 00000e93 li t4,0 - 80002ff4: 01a00193 li gp,26 - 80002ff8: 03d09463 bne ra,t4,80003020 - -0000000080002ffc : - 80002ffc: 111110b7 lui ra,0x11111 - 80003000: 1110809b addiw ra,ra,273 - 80003004: 22222137 lui sp,0x22222 - 80003008: 2221011b addiw sp,sp,546 - 8000300c: 0020f033 and zero,ra,sp - 80003010: 00000e93 li t4,0 - 80003014: 01b00193 li gp,27 - 80003018: 01d01463 bne zero,t4,80003020 - 8000301c: 00301a63 bne zero,gp,80003030 - -0000000080003020 : - 80003020: 00119513 slli a0,gp,0x1 - 80003024: 00050063 beqz a0,80003024 - 80003028: 00156513 ori a0,a0,1 - 8000302c: 00000073 ecall - -0000000080003030 : - 80003030: 00100513 li a0,1 - 80003034: 00000073 ecall - 80003038: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-and.elf b/test/riscv/tests/rv64ui-v-and.elf deleted file mode 100644 index 2cf4f37d..00000000 Binary files a/test/riscv/tests/rv64ui-v-and.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-andi.dump b/test/riscv/tests/rv64ui-v-andi.dump deleted file mode 100644 index 6503a378..00000000 --- a/test/riscv/tests/rv64ui-v-andi.dump +++ /dev/null @@ -1,990 +0,0 @@ - -rv64ui-v-andi: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 88868693 addi a3,a3,-1912 # 80002ce0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 8bc60613 addi a2,a2,-1860 # 80002d70 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 88460613 addi a2,a2,-1916 # 80002d88 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 7d468693 addi a3,a3,2004 # 80002d28 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 7f068693 addi a3,a3,2032 # 80002e60 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 77060613 addi a2,a2,1904 # 80002e38 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 6a468693 addi a3,a3,1700 # 80002e90 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 5c468693 addi a3,a3,1476 # 80002e00 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 55468693 addi a3,a3,1364 # 80002dc8 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 01a00793 li a5,26 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 069897b7 lui a5,0x6989 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 68978793 addi a5,a5,1673 # 6989689 <_start-0x79676977> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 000100b7 lui ra,0x10 - 80002acc: f010809b addiw ra,ra,-255 - 80002ad0: 01009093 slli ra,ra,0x10 - 80002ad4: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002ad8: f0f0ff13 andi t5,ra,-241 - 80002adc: 00010eb7 lui t4,0x10 - 80002ae0: f01e8e9b addiw t4,t4,-255 - 80002ae4: 010e9e93 slli t4,t4,0x10 - 80002ae8: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80002aec: 00200193 li gp,2 - 80002af0: 1ddf1863 bne t5,t4,80002cc0 - -0000000080002af4 : - 80002af4: 0ff010b7 lui ra,0xff01 - 80002af8: ff00809b addiw ra,ra,-16 - 80002afc: 0f00ff13 andi t5,ra,240 - 80002b00: 0f000e93 li t4,240 - 80002b04: 00300193 li gp,3 - 80002b08: 1bdf1c63 bne t5,t4,80002cc0 - -0000000080002b0c : - 80002b0c: 00ff00b7 lui ra,0xff0 - 80002b10: 0ff0809b addiw ra,ra,255 - 80002b14: 70f0ff13 andi t5,ra,1807 - 80002b18: 00f00e93 li t4,15 - 80002b1c: 00400193 li gp,4 - 80002b20: 1bdf1063 bne t5,t4,80002cc0 - -0000000080002b24 : - 80002b24: 000f00b7 lui ra,0xf0 - 80002b28: 0ff0809b addiw ra,ra,255 - 80002b2c: 00c09093 slli ra,ra,0xc - 80002b30: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> - 80002b34: 0f00ff13 andi t5,ra,240 - 80002b38: 00000e93 li t4,0 - 80002b3c: 00500193 li gp,5 - 80002b40: 19df1063 bne t5,t4,80002cc0 - -0000000080002b44 : - 80002b44: 000100b7 lui ra,0x10 - 80002b48: f010809b addiw ra,ra,-255 - 80002b4c: 01009093 slli ra,ra,0x10 - 80002b50: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002b54: 0f00f093 andi ra,ra,240 - 80002b58: 00000e93 li t4,0 - 80002b5c: 00600193 li gp,6 - 80002b60: 17d09063 bne ra,t4,80002cc0 - -0000000080002b64 : - 80002b64: 00000213 li tp,0 - 80002b68: 0ff010b7 lui ra,0xff01 - 80002b6c: ff00809b addiw ra,ra,-16 - 80002b70: 70f0ff13 andi t5,ra,1807 - 80002b74: 000f0313 mv t1,t5 - 80002b78: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002b7c: 00200293 li t0,2 - 80002b80: fe5214e3 bne tp,t0,80002b68 - 80002b84: 70000e93 li t4,1792 - 80002b88: 00700193 li gp,7 - 80002b8c: 13d31a63 bne t1,t4,80002cc0 - -0000000080002b90 : - 80002b90: 00000213 li tp,0 - 80002b94: 00ff00b7 lui ra,0xff0 - 80002b98: 0ff0809b addiw ra,ra,255 - 80002b9c: 0f00ff13 andi t5,ra,240 - 80002ba0: 00000013 nop - 80002ba4: 000f0313 mv t1,t5 - 80002ba8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002bac: 00200293 li t0,2 - 80002bb0: fe5212e3 bne tp,t0,80002b94 - 80002bb4: 0f000e93 li t4,240 - 80002bb8: 00800193 li gp,8 - 80002bbc: 11d31263 bne t1,t4,80002cc0 - -0000000080002bc0 : - 80002bc0: 00000213 li tp,0 - 80002bc4: 000f00b7 lui ra,0xf0 - 80002bc8: 0ff0809b addiw ra,ra,255 - 80002bcc: 00c09093 slli ra,ra,0xc - 80002bd0: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> - 80002bd4: f0f0ff13 andi t5,ra,-241 - 80002bd8: 00000013 nop - 80002bdc: 00000013 nop - 80002be0: 000f0313 mv t1,t5 - 80002be4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002be8: 00200293 li t0,2 - 80002bec: fc521ce3 bne tp,t0,80002bc4 - 80002bf0: 000f0eb7 lui t4,0xf0 - 80002bf4: 0ffe8e9b addiw t4,t4,255 - 80002bf8: 00ce9e93 slli t4,t4,0xc - 80002bfc: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 80002c00: 00900193 li gp,9 - 80002c04: 0bd31e63 bne t1,t4,80002cc0 - -0000000080002c08 : - 80002c08: 00000213 li tp,0 - 80002c0c: 0ff010b7 lui ra,0xff01 - 80002c10: ff00809b addiw ra,ra,-16 - 80002c14: 70f0ff13 andi t5,ra,1807 - 80002c18: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c1c: 00200293 li t0,2 - 80002c20: fe5216e3 bne tp,t0,80002c0c - 80002c24: 70000e93 li t4,1792 - 80002c28: 00a00193 li gp,10 - 80002c2c: 09df1a63 bne t5,t4,80002cc0 - -0000000080002c30 : - 80002c30: 00000213 li tp,0 - 80002c34: 00ff00b7 lui ra,0xff0 - 80002c38: 0ff0809b addiw ra,ra,255 - 80002c3c: 00000013 nop - 80002c40: 0f00ff13 andi t5,ra,240 - 80002c44: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c48: 00200293 li t0,2 - 80002c4c: fe5214e3 bne tp,t0,80002c34 - 80002c50: 0f000e93 li t4,240 - 80002c54: 00b00193 li gp,11 - 80002c58: 07df1463 bne t5,t4,80002cc0 - -0000000080002c5c : - 80002c5c: 00000213 li tp,0 - 80002c60: 000f00b7 lui ra,0xf0 - 80002c64: 0ff0809b addiw ra,ra,255 - 80002c68: 00c09093 slli ra,ra,0xc - 80002c6c: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> - 80002c70: 00000013 nop - 80002c74: 00000013 nop - 80002c78: 70f0ff13 andi t5,ra,1807 - 80002c7c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c80: 00200293 li t0,2 - 80002c84: fc521ee3 bne tp,t0,80002c60 - 80002c88: 00f00e93 li t4,15 - 80002c8c: 00c00193 li gp,12 - 80002c90: 03df1863 bne t5,t4,80002cc0 - -0000000080002c94 : - 80002c94: 0f007093 andi ra,zero,240 - 80002c98: 00000e93 li t4,0 - 80002c9c: 00d00193 li gp,13 - 80002ca0: 03d09063 bne ra,t4,80002cc0 - -0000000080002ca4 : - 80002ca4: 00ff00b7 lui ra,0xff0 - 80002ca8: 0ff0809b addiw ra,ra,255 - 80002cac: 70f0f013 andi zero,ra,1807 - 80002cb0: 00000e93 li t4,0 - 80002cb4: 00e00193 li gp,14 - 80002cb8: 01d01463 bne zero,t4,80002cc0 - 80002cbc: 00301a63 bne zero,gp,80002cd0 - -0000000080002cc0 : - 80002cc0: 00119513 slli a0,gp,0x1 - 80002cc4: 00050063 beqz a0,80002cc4 - 80002cc8: 00156513 ori a0,a0,1 - 80002ccc: 00000073 ecall - -0000000080002cd0 : - 80002cd0: 00100513 li a0,1 - 80002cd4: 00000073 ecall - 80002cd8: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-andi.elf b/test/riscv/tests/rv64ui-v-andi.elf deleted file mode 100644 index 02ec3d50..00000000 Binary files a/test/riscv/tests/rv64ui-v-andi.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-auipc.dump b/test/riscv/tests/rv64ui-v-auipc.dump deleted file mode 100644 index bfa19dda..00000000 --- a/test/riscv/tests/rv64ui-v-auipc.dump +++ /dev/null @@ -1,859 +0,0 @@ - -rv64ui-v-auipc: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 6d068693 addi a3,a3,1744 # 80002b28 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 70460613 addi a2,a2,1796 # 80002bb8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6cc60613 addi a2,a2,1740 # 80002bd0 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 61c68693 addi a3,a3,1564 # 80002b70 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 63868693 addi a3,a3,1592 # 80002ca8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5b860613 addi a2,a2,1464 # 80002c80 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 4ec68693 addi a3,a3,1260 # 80002cd8 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 40c68693 addi a3,a3,1036 # 80002c48 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 39c68693 addi a3,a3,924 # 80002c10 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 02a00793 li a5,42 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0962a7b7 lui a5,0x962a - 80002a70: 000805b7 lui a1,0x80 - 80002a74: af278793 addi a5,a5,-1294 # 9629af2 <_start-0x769d650e> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00002517 auipc a0,0x2 - 80002acc: 71c50513 addi a0,a0,1820 # 800051e4 - 80002ad0: 004005ef jal a1,80002ad4 - 80002ad4: 40b50533 sub a0,a0,a1 - 80002ad8: 00002eb7 lui t4,0x2 - 80002adc: 710e8e9b addiw t4,t4,1808 - 80002ae0: 00200193 li gp,2 - 80002ae4: 03d51463 bne a0,t4,80002b0c - -0000000080002ae8 : - 80002ae8: ffffe517 auipc a0,0xffffe - 80002aec: 8fc50513 addi a0,a0,-1796 # 800003e4 - 80002af0: 004005ef jal a1,80002af4 - 80002af4: 40b50533 sub a0,a0,a1 - 80002af8: ffffeeb7 lui t4,0xffffe - 80002afc: 8f0e8e9b addiw t4,t4,-1808 - 80002b00: 00300193 li gp,3 - 80002b04: 01d51463 bne a0,t4,80002b0c - 80002b08: 00301a63 bne zero,gp,80002b1c - -0000000080002b0c : - 80002b0c: 00119513 slli a0,gp,0x1 - 80002b10: 00050063 beqz a0,80002b10 - 80002b14: 00156513 ori a0,a0,1 - 80002b18: 00000073 ecall - -0000000080002b1c : - 80002b1c: 00100513 li a0,1 - 80002b20: 00000073 ecall - 80002b24: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-auipc.elf b/test/riscv/tests/rv64ui-v-auipc.elf deleted file mode 100644 index e0fc7d11..00000000 Binary files a/test/riscv/tests/rv64ui-v-auipc.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-beq.dump b/test/riscv/tests/rv64ui-v-beq.dump deleted file mode 100644 index 18ece1e2..00000000 --- a/test/riscv/tests/rv64ui-v-beq.dump +++ /dev/null @@ -1,1054 +0,0 @@ - -rv64ui-v-beq: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 95068693 addi a3,a3,-1712 # 80002da8 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 98460613 addi a2,a2,-1660 # 80002e38 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 94c60613 addi a2,a2,-1716 # 80002e50 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 89c68693 addi a3,a3,-1892 # 80002df0 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 8b868693 addi a3,a3,-1864 # 80002f28 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 83860613 addi a2,a2,-1992 # 80002f00 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 76c68693 addi a3,a3,1900 # 80002f58 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 68c68693 addi a3,a3,1676 # 80002ec8 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 61c68693 addi a3,a3,1564 # 80002e90 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 03400793 li a5,52 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 029747b7 lui a5,0x2974 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 93378793 addi a5,a5,-1741 # 2973933 <_start-0x7d68c6cd> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00200193 li gp,2 - 80002acc: 00000093 li ra,0 - 80002ad0: 00000113 li sp,0 - 80002ad4: 00208663 beq ra,sp,80002ae0 - 80002ad8: 2a301863 bne zero,gp,80002d88 - 80002adc: 00301663 bne zero,gp,80002ae8 - 80002ae0: fe208ee3 beq ra,sp,80002adc - 80002ae4: 2a301263 bne zero,gp,80002d88 - -0000000080002ae8 : - 80002ae8: 00300193 li gp,3 - 80002aec: 00100093 li ra,1 - 80002af0: 00100113 li sp,1 - 80002af4: 00208663 beq ra,sp,80002b00 - 80002af8: 28301863 bne zero,gp,80002d88 - 80002afc: 00301663 bne zero,gp,80002b08 - 80002b00: fe208ee3 beq ra,sp,80002afc - 80002b04: 28301263 bne zero,gp,80002d88 - -0000000080002b08 : - 80002b08: 00400193 li gp,4 - 80002b0c: fff00093 li ra,-1 - 80002b10: fff00113 li sp,-1 - 80002b14: 00208663 beq ra,sp,80002b20 - 80002b18: 26301863 bne zero,gp,80002d88 - 80002b1c: 00301663 bne zero,gp,80002b28 - 80002b20: fe208ee3 beq ra,sp,80002b1c - 80002b24: 26301263 bne zero,gp,80002d88 - -0000000080002b28 : - 80002b28: 00500193 li gp,5 - 80002b2c: 00000093 li ra,0 - 80002b30: 00100113 li sp,1 - 80002b34: 00208463 beq ra,sp,80002b3c - 80002b38: 00301463 bne zero,gp,80002b40 - 80002b3c: 24301663 bne zero,gp,80002d88 - 80002b40: fe208ee3 beq ra,sp,80002b3c - -0000000080002b44 : - 80002b44: 00600193 li gp,6 - 80002b48: 00100093 li ra,1 - 80002b4c: 00000113 li sp,0 - 80002b50: 00208463 beq ra,sp,80002b58 - 80002b54: 00301463 bne zero,gp,80002b5c - 80002b58: 22301863 bne zero,gp,80002d88 - 80002b5c: fe208ee3 beq ra,sp,80002b58 - -0000000080002b60 : - 80002b60: 00700193 li gp,7 - 80002b64: fff00093 li ra,-1 - 80002b68: 00100113 li sp,1 - 80002b6c: 00208463 beq ra,sp,80002b74 - 80002b70: 00301463 bne zero,gp,80002b78 - 80002b74: 20301a63 bne zero,gp,80002d88 - 80002b78: fe208ee3 beq ra,sp,80002b74 - -0000000080002b7c : - 80002b7c: 00800193 li gp,8 - 80002b80: 00100093 li ra,1 - 80002b84: fff00113 li sp,-1 - 80002b88: 00208463 beq ra,sp,80002b90 - 80002b8c: 00301463 bne zero,gp,80002b94 - 80002b90: 1e301c63 bne zero,gp,80002d88 - 80002b94: fe208ee3 beq ra,sp,80002b90 - -0000000080002b98 : - 80002b98: 00900193 li gp,9 - 80002b9c: 00000213 li tp,0 - 80002ba0: 00000093 li ra,0 - 80002ba4: fff00113 li sp,-1 - 80002ba8: 1e208063 beq ra,sp,80002d88 - 80002bac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002bb0: 00200293 li t0,2 - 80002bb4: fe5216e3 bne tp,t0,80002ba0 - -0000000080002bb8 : - 80002bb8: 00a00193 li gp,10 - 80002bbc: 00000213 li tp,0 - 80002bc0: 00000093 li ra,0 - 80002bc4: fff00113 li sp,-1 - 80002bc8: 00000013 nop - 80002bcc: 1a208e63 beq ra,sp,80002d88 - 80002bd0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002bd4: 00200293 li t0,2 - 80002bd8: fe5214e3 bne tp,t0,80002bc0 - -0000000080002bdc : - 80002bdc: 00b00193 li gp,11 - 80002be0: 00000213 li tp,0 - 80002be4: 00000093 li ra,0 - 80002be8: fff00113 li sp,-1 - 80002bec: 00000013 nop - 80002bf0: 00000013 nop - 80002bf4: 18208a63 beq ra,sp,80002d88 - 80002bf8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002bfc: 00200293 li t0,2 - 80002c00: fe5212e3 bne tp,t0,80002be4 - -0000000080002c04 : - 80002c04: 00c00193 li gp,12 - 80002c08: 00000213 li tp,0 - 80002c0c: 00000093 li ra,0 - 80002c10: 00000013 nop - 80002c14: fff00113 li sp,-1 - 80002c18: 16208863 beq ra,sp,80002d88 - 80002c1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c20: 00200293 li t0,2 - 80002c24: fe5214e3 bne tp,t0,80002c0c - -0000000080002c28 : - 80002c28: 00d00193 li gp,13 - 80002c2c: 00000213 li tp,0 - 80002c30: 00000093 li ra,0 - 80002c34: 00000013 nop - 80002c38: fff00113 li sp,-1 - 80002c3c: 00000013 nop - 80002c40: 14208463 beq ra,sp,80002d88 - 80002c44: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c48: 00200293 li t0,2 - 80002c4c: fe5212e3 bne tp,t0,80002c30 - -0000000080002c50 : - 80002c50: 00e00193 li gp,14 - 80002c54: 00000213 li tp,0 - 80002c58: 00000093 li ra,0 - 80002c5c: 00000013 nop - 80002c60: 00000013 nop - 80002c64: fff00113 li sp,-1 - 80002c68: 12208063 beq ra,sp,80002d88 - 80002c6c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c70: 00200293 li t0,2 - 80002c74: fe5212e3 bne tp,t0,80002c58 - -0000000080002c78 : - 80002c78: 00f00193 li gp,15 - 80002c7c: 00000213 li tp,0 - 80002c80: 00000093 li ra,0 - 80002c84: fff00113 li sp,-1 - 80002c88: 10208063 beq ra,sp,80002d88 - 80002c8c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c90: 00200293 li t0,2 - 80002c94: fe5216e3 bne tp,t0,80002c80 - -0000000080002c98 : - 80002c98: 01000193 li gp,16 - 80002c9c: 00000213 li tp,0 - 80002ca0: 00000093 li ra,0 - 80002ca4: fff00113 li sp,-1 - 80002ca8: 00000013 nop - 80002cac: 0c208e63 beq ra,sp,80002d88 - 80002cb0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cb4: 00200293 li t0,2 - 80002cb8: fe5214e3 bne tp,t0,80002ca0 - -0000000080002cbc : - 80002cbc: 01100193 li gp,17 - 80002cc0: 00000213 li tp,0 - 80002cc4: 00000093 li ra,0 - 80002cc8: fff00113 li sp,-1 - 80002ccc: 00000013 nop - 80002cd0: 00000013 nop - 80002cd4: 0a208a63 beq ra,sp,80002d88 - 80002cd8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cdc: 00200293 li t0,2 - 80002ce0: fe5212e3 bne tp,t0,80002cc4 - -0000000080002ce4 : - 80002ce4: 01200193 li gp,18 - 80002ce8: 00000213 li tp,0 - 80002cec: 00000093 li ra,0 - 80002cf0: 00000013 nop - 80002cf4: fff00113 li sp,-1 - 80002cf8: 08208863 beq ra,sp,80002d88 - 80002cfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d00: 00200293 li t0,2 - 80002d04: fe5214e3 bne tp,t0,80002cec - -0000000080002d08 : - 80002d08: 01300193 li gp,19 - 80002d0c: 00000213 li tp,0 - 80002d10: 00000093 li ra,0 - 80002d14: 00000013 nop - 80002d18: fff00113 li sp,-1 - 80002d1c: 00000013 nop - 80002d20: 06208463 beq ra,sp,80002d88 - 80002d24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d28: 00200293 li t0,2 - 80002d2c: fe5212e3 bne tp,t0,80002d10 - -0000000080002d30 : - 80002d30: 01400193 li gp,20 - 80002d34: 00000213 li tp,0 - 80002d38: 00000093 li ra,0 - 80002d3c: 00000013 nop - 80002d40: 00000013 nop - 80002d44: fff00113 li sp,-1 - 80002d48: 04208063 beq ra,sp,80002d88 - 80002d4c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d50: 00200293 li t0,2 - 80002d54: fe5212e3 bne tp,t0,80002d38 - -0000000080002d58 : - 80002d58: 00100093 li ra,1 - 80002d5c: 00000a63 beqz zero,80002d70 - 80002d60: 00108093 addi ra,ra,1 - 80002d64: 00108093 addi ra,ra,1 - 80002d68: 00108093 addi ra,ra,1 - 80002d6c: 00108093 addi ra,ra,1 - 80002d70: 00108093 addi ra,ra,1 - 80002d74: 00108093 addi ra,ra,1 - 80002d78: 00300e93 li t4,3 - 80002d7c: 01500193 li gp,21 - 80002d80: 01d09463 bne ra,t4,80002d88 - 80002d84: 00301a63 bne zero,gp,80002d98 - -0000000080002d88 : - 80002d88: 00119513 slli a0,gp,0x1 - 80002d8c: 00050063 beqz a0,80002d8c - 80002d90: 00156513 ori a0,a0,1 - 80002d94: 00000073 ecall - -0000000080002d98 : - 80002d98: 00100513 li a0,1 - 80002d9c: 00000073 ecall - 80002da0: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-beq.elf b/test/riscv/tests/rv64ui-v-beq.elf deleted file mode 100644 index a64100b1..00000000 Binary files a/test/riscv/tests/rv64ui-v-beq.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-bge.dump b/test/riscv/tests/rv64ui-v-bge.dump deleted file mode 100644 index 58215260..00000000 --- a/test/riscv/tests/rv64ui-v-bge.dump +++ /dev/null @@ -1,1084 +0,0 @@ - -rv64ui-v-bge: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 9b068693 addi a3,a3,-1616 # 80002e08 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 9e460613 addi a2,a2,-1564 # 80002e98 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 9ac60613 addi a2,a2,-1620 # 80002eb0 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 8fc68693 addi a3,a3,-1796 # 80002e50 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 91868693 addi a3,a3,-1768 # 80002f88 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 89860613 addi a2,a2,-1896 # 80002f60 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 7cc68693 addi a3,a3,1996 # 80002fb8 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 6ec68693 addi a3,a3,1772 # 80002f28 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 67c68693 addi a3,a3,1660 # 80002ef0 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 01f00793 li a5,31 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 05e177b7 lui a5,0x5e17 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 4f578793 addi a5,a5,1269 # 5e174f5 <_start-0x7a1e8b0b> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00200193 li gp,2 - 80002acc: 00000093 li ra,0 - 80002ad0: 00000113 li sp,0 - 80002ad4: 0020d663 ble sp,ra,80002ae0 - 80002ad8: 30301863 bne zero,gp,80002de8 - 80002adc: 00301663 bne zero,gp,80002ae8 - 80002ae0: fe20dee3 ble sp,ra,80002adc - 80002ae4: 30301263 bne zero,gp,80002de8 - -0000000080002ae8 : - 80002ae8: 00300193 li gp,3 - 80002aec: 00100093 li ra,1 - 80002af0: 00100113 li sp,1 - 80002af4: 0020d663 ble sp,ra,80002b00 - 80002af8: 2e301863 bne zero,gp,80002de8 - 80002afc: 00301663 bne zero,gp,80002b08 - 80002b00: fe20dee3 ble sp,ra,80002afc - 80002b04: 2e301263 bne zero,gp,80002de8 - -0000000080002b08 : - 80002b08: 00400193 li gp,4 - 80002b0c: fff00093 li ra,-1 - 80002b10: fff00113 li sp,-1 - 80002b14: 0020d663 ble sp,ra,80002b20 - 80002b18: 2c301863 bne zero,gp,80002de8 - 80002b1c: 00301663 bne zero,gp,80002b28 - 80002b20: fe20dee3 ble sp,ra,80002b1c - 80002b24: 2c301263 bne zero,gp,80002de8 - -0000000080002b28 : - 80002b28: 00500193 li gp,5 - 80002b2c: 00100093 li ra,1 - 80002b30: 00000113 li sp,0 - 80002b34: 0020d663 ble sp,ra,80002b40 - 80002b38: 2a301863 bne zero,gp,80002de8 - 80002b3c: 00301663 bne zero,gp,80002b48 - 80002b40: fe20dee3 ble sp,ra,80002b3c - 80002b44: 2a301263 bne zero,gp,80002de8 - -0000000080002b48 : - 80002b48: 00600193 li gp,6 - 80002b4c: 00100093 li ra,1 - 80002b50: fff00113 li sp,-1 - 80002b54: 0020d663 ble sp,ra,80002b60 - 80002b58: 28301863 bne zero,gp,80002de8 - 80002b5c: 00301663 bne zero,gp,80002b68 - 80002b60: fe20dee3 ble sp,ra,80002b5c - 80002b64: 28301263 bne zero,gp,80002de8 - -0000000080002b68 : - 80002b68: 00700193 li gp,7 - 80002b6c: fff00093 li ra,-1 - 80002b70: ffe00113 li sp,-2 - 80002b74: 0020d663 ble sp,ra,80002b80 - 80002b78: 26301863 bne zero,gp,80002de8 - 80002b7c: 00301663 bne zero,gp,80002b88 - 80002b80: fe20dee3 ble sp,ra,80002b7c - 80002b84: 26301263 bne zero,gp,80002de8 - -0000000080002b88 : - 80002b88: 00800193 li gp,8 - 80002b8c: 00000093 li ra,0 - 80002b90: 00100113 li sp,1 - 80002b94: 0020d463 ble sp,ra,80002b9c - 80002b98: 00301463 bne zero,gp,80002ba0 - 80002b9c: 24301663 bne zero,gp,80002de8 - 80002ba0: fe20dee3 ble sp,ra,80002b9c - -0000000080002ba4 : - 80002ba4: 00900193 li gp,9 - 80002ba8: fff00093 li ra,-1 - 80002bac: 00100113 li sp,1 - 80002bb0: 0020d463 ble sp,ra,80002bb8 - 80002bb4: 00301463 bne zero,gp,80002bbc - 80002bb8: 22301863 bne zero,gp,80002de8 - 80002bbc: fe20dee3 ble sp,ra,80002bb8 - -0000000080002bc0 : - 80002bc0: 00a00193 li gp,10 - 80002bc4: ffe00093 li ra,-2 - 80002bc8: fff00113 li sp,-1 - 80002bcc: 0020d463 ble sp,ra,80002bd4 - 80002bd0: 00301463 bne zero,gp,80002bd8 - 80002bd4: 20301a63 bne zero,gp,80002de8 - 80002bd8: fe20dee3 ble sp,ra,80002bd4 - -0000000080002bdc : - 80002bdc: 00b00193 li gp,11 - 80002be0: ffe00093 li ra,-2 - 80002be4: 00100113 li sp,1 - 80002be8: 0020d463 ble sp,ra,80002bf0 - 80002bec: 00301463 bne zero,gp,80002bf4 - 80002bf0: 1e301c63 bne zero,gp,80002de8 - 80002bf4: fe20dee3 ble sp,ra,80002bf0 - -0000000080002bf8 : - 80002bf8: 00c00193 li gp,12 - 80002bfc: 00000213 li tp,0 - 80002c00: fff00093 li ra,-1 - 80002c04: 00000113 li sp,0 - 80002c08: 1e20d063 ble sp,ra,80002de8 - 80002c0c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c10: 00200293 li t0,2 - 80002c14: fe5216e3 bne tp,t0,80002c00 - -0000000080002c18 : - 80002c18: 00d00193 li gp,13 - 80002c1c: 00000213 li tp,0 - 80002c20: fff00093 li ra,-1 - 80002c24: 00000113 li sp,0 - 80002c28: 00000013 nop - 80002c2c: 1a20de63 ble sp,ra,80002de8 - 80002c30: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c34: 00200293 li t0,2 - 80002c38: fe5214e3 bne tp,t0,80002c20 - -0000000080002c3c : - 80002c3c: 00e00193 li gp,14 - 80002c40: 00000213 li tp,0 - 80002c44: fff00093 li ra,-1 - 80002c48: 00000113 li sp,0 - 80002c4c: 00000013 nop - 80002c50: 00000013 nop - 80002c54: 1820da63 ble sp,ra,80002de8 - 80002c58: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c5c: 00200293 li t0,2 - 80002c60: fe5212e3 bne tp,t0,80002c44 - -0000000080002c64 : - 80002c64: 00f00193 li gp,15 - 80002c68: 00000213 li tp,0 - 80002c6c: fff00093 li ra,-1 - 80002c70: 00000013 nop - 80002c74: 00000113 li sp,0 - 80002c78: 1620d863 ble sp,ra,80002de8 - 80002c7c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c80: 00200293 li t0,2 - 80002c84: fe5214e3 bne tp,t0,80002c6c - -0000000080002c88 : - 80002c88: 01000193 li gp,16 - 80002c8c: 00000213 li tp,0 - 80002c90: fff00093 li ra,-1 - 80002c94: 00000013 nop - 80002c98: 00000113 li sp,0 - 80002c9c: 00000013 nop - 80002ca0: 1420d463 ble sp,ra,80002de8 - 80002ca4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ca8: 00200293 li t0,2 - 80002cac: fe5212e3 bne tp,t0,80002c90 - -0000000080002cb0 : - 80002cb0: 01100193 li gp,17 - 80002cb4: 00000213 li tp,0 - 80002cb8: fff00093 li ra,-1 - 80002cbc: 00000013 nop - 80002cc0: 00000013 nop - 80002cc4: 00000113 li sp,0 - 80002cc8: 1220d063 ble sp,ra,80002de8 - 80002ccc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cd0: 00200293 li t0,2 - 80002cd4: fe5212e3 bne tp,t0,80002cb8 - -0000000080002cd8 : - 80002cd8: 01200193 li gp,18 - 80002cdc: 00000213 li tp,0 - 80002ce0: fff00093 li ra,-1 - 80002ce4: 00000113 li sp,0 - 80002ce8: 1020d063 ble sp,ra,80002de8 - 80002cec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cf0: 00200293 li t0,2 - 80002cf4: fe5216e3 bne tp,t0,80002ce0 - -0000000080002cf8 : - 80002cf8: 01300193 li gp,19 - 80002cfc: 00000213 li tp,0 - 80002d00: fff00093 li ra,-1 - 80002d04: 00000113 li sp,0 - 80002d08: 00000013 nop - 80002d0c: 0c20de63 ble sp,ra,80002de8 - 80002d10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d14: 00200293 li t0,2 - 80002d18: fe5214e3 bne tp,t0,80002d00 - -0000000080002d1c : - 80002d1c: 01400193 li gp,20 - 80002d20: 00000213 li tp,0 - 80002d24: fff00093 li ra,-1 - 80002d28: 00000113 li sp,0 - 80002d2c: 00000013 nop - 80002d30: 00000013 nop - 80002d34: 0a20da63 ble sp,ra,80002de8 - 80002d38: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d3c: 00200293 li t0,2 - 80002d40: fe5212e3 bne tp,t0,80002d24 - -0000000080002d44 : - 80002d44: 01500193 li gp,21 - 80002d48: 00000213 li tp,0 - 80002d4c: fff00093 li ra,-1 - 80002d50: 00000013 nop - 80002d54: 00000113 li sp,0 - 80002d58: 0820d863 ble sp,ra,80002de8 - 80002d5c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d60: 00200293 li t0,2 - 80002d64: fe5214e3 bne tp,t0,80002d4c - -0000000080002d68 : - 80002d68: 01600193 li gp,22 - 80002d6c: 00000213 li tp,0 - 80002d70: fff00093 li ra,-1 - 80002d74: 00000013 nop - 80002d78: 00000113 li sp,0 - 80002d7c: 00000013 nop - 80002d80: 0620d463 ble sp,ra,80002de8 - 80002d84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d88: 00200293 li t0,2 - 80002d8c: fe5212e3 bne tp,t0,80002d70 - -0000000080002d90 : - 80002d90: 01700193 li gp,23 - 80002d94: 00000213 li tp,0 - 80002d98: fff00093 li ra,-1 - 80002d9c: 00000013 nop - 80002da0: 00000013 nop - 80002da4: 00000113 li sp,0 - 80002da8: 0420d063 ble sp,ra,80002de8 - 80002dac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002db0: 00200293 li t0,2 - 80002db4: fe5212e3 bne tp,t0,80002d98 - -0000000080002db8 : - 80002db8: 00100093 li ra,1 - 80002dbc: 0000da63 bgez ra,80002dd0 - 80002dc0: 00108093 addi ra,ra,1 - 80002dc4: 00108093 addi ra,ra,1 - 80002dc8: 00108093 addi ra,ra,1 - 80002dcc: 00108093 addi ra,ra,1 - 80002dd0: 00108093 addi ra,ra,1 - 80002dd4: 00108093 addi ra,ra,1 - 80002dd8: 00300e93 li t4,3 - 80002ddc: 01800193 li gp,24 - 80002de0: 01d09463 bne ra,t4,80002de8 - 80002de4: 00301a63 bne zero,gp,80002df8 - -0000000080002de8 : - 80002de8: 00119513 slli a0,gp,0x1 - 80002dec: 00050063 beqz a0,80002dec - 80002df0: 00156513 ori a0,a0,1 - 80002df4: 00000073 ecall - -0000000080002df8 : - 80002df8: 00100513 li a0,1 - 80002dfc: 00000073 ecall - 80002e00: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-bge.elf b/test/riscv/tests/rv64ui-v-bge.elf deleted file mode 100644 index 74af9d1f..00000000 Binary files a/test/riscv/tests/rv64ui-v-bge.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-bgeu.dump b/test/riscv/tests/rv64ui-v-bgeu.dump deleted file mode 100644 index 9544e42f..00000000 --- a/test/riscv/tests/rv64ui-v-bgeu.dump +++ /dev/null @@ -1,1138 +0,0 @@ - -rv64ui-v-bgeu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: a8868693 addi a3,a3,-1400 # 80002ee0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: abc60613 addi a2,a2,-1348 # 80002f70 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: a8460613 addi a2,a2,-1404 # 80002f88 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 9d468693 addi a3,a3,-1580 # 80002f28 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 9f068693 addi a3,a3,-1552 # 80003060 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 97060613 addi a2,a2,-1680 # 80003038 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: 8a468693 addi a3,a3,-1884 # 80003090 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 7c468693 addi a3,a3,1988 # 80003000 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 75468693 addi a3,a3,1876 # 80002fc8 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 03d00793 li a5,61 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 02e567b7 lui a5,0x2e56 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: eb078793 addi a5,a5,-336 # 2e55eb0 <_start-0x7d1aa150> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00200193 li gp,2 - 80002acc: 00000093 li ra,0 - 80002ad0: 00000113 li sp,0 - 80002ad4: 0020f663 bleu sp,ra,80002ae0 - 80002ad8: 3e301463 bne zero,gp,80002ec0 - 80002adc: 00301663 bne zero,gp,80002ae8 - 80002ae0: fe20fee3 bleu sp,ra,80002adc - 80002ae4: 3c301e63 bne zero,gp,80002ec0 - -0000000080002ae8 : - 80002ae8: 00300193 li gp,3 - 80002aec: 00100093 li ra,1 - 80002af0: 00100113 li sp,1 - 80002af4: 0020f663 bleu sp,ra,80002b00 - 80002af8: 3c301463 bne zero,gp,80002ec0 - 80002afc: 00301663 bne zero,gp,80002b08 - 80002b00: fe20fee3 bleu sp,ra,80002afc - 80002b04: 3a301e63 bne zero,gp,80002ec0 - -0000000080002b08 : - 80002b08: 00400193 li gp,4 - 80002b0c: 0010009b addiw ra,zero,1 - 80002b10: 02009093 slli ra,ra,0x20 - 80002b14: fff08093 addi ra,ra,-1 - 80002b18: 0010011b addiw sp,zero,1 - 80002b1c: 02011113 slli sp,sp,0x20 - 80002b20: fff10113 addi sp,sp,-1 - 80002b24: 0020f663 bleu sp,ra,80002b30 - 80002b28: 38301c63 bne zero,gp,80002ec0 - 80002b2c: 00301663 bne zero,gp,80002b38 - 80002b30: fe20fee3 bleu sp,ra,80002b2c - 80002b34: 38301663 bne zero,gp,80002ec0 - -0000000080002b38 : - 80002b38: 00500193 li gp,5 - 80002b3c: 00100093 li ra,1 - 80002b40: 00000113 li sp,0 - 80002b44: 0020f663 bleu sp,ra,80002b50 - 80002b48: 36301c63 bne zero,gp,80002ec0 - 80002b4c: 00301663 bne zero,gp,80002b58 - 80002b50: fe20fee3 bleu sp,ra,80002b4c - 80002b54: 36301663 bne zero,gp,80002ec0 - -0000000080002b58 : - 80002b58: 00600193 li gp,6 - 80002b5c: 0010009b addiw ra,zero,1 - 80002b60: 02009093 slli ra,ra,0x20 - 80002b64: fff08093 addi ra,ra,-1 - 80002b68: 0010011b addiw sp,zero,1 - 80002b6c: 02011113 slli sp,sp,0x20 - 80002b70: ffe10113 addi sp,sp,-2 - 80002b74: 0020f663 bleu sp,ra,80002b80 - 80002b78: 34301463 bne zero,gp,80002ec0 - 80002b7c: 00301663 bne zero,gp,80002b88 - 80002b80: fe20fee3 bleu sp,ra,80002b7c - 80002b84: 32301e63 bne zero,gp,80002ec0 - -0000000080002b88 : - 80002b88: 00700193 li gp,7 - 80002b8c: 0010009b addiw ra,zero,1 - 80002b90: 02009093 slli ra,ra,0x20 - 80002b94: fff08093 addi ra,ra,-1 - 80002b98: 00000113 li sp,0 - 80002b9c: 0020f663 bleu sp,ra,80002ba8 - 80002ba0: 32301063 bne zero,gp,80002ec0 - 80002ba4: 00301663 bne zero,gp,80002bb0 - 80002ba8: fe20fee3 bleu sp,ra,80002ba4 - 80002bac: 30301a63 bne zero,gp,80002ec0 - -0000000080002bb0 : - 80002bb0: 00800193 li gp,8 - 80002bb4: 00000093 li ra,0 - 80002bb8: 00100113 li sp,1 - 80002bbc: 0020f463 bleu sp,ra,80002bc4 - 80002bc0: 00301463 bne zero,gp,80002bc8 - 80002bc4: 2e301e63 bne zero,gp,80002ec0 - 80002bc8: fe20fee3 bleu sp,ra,80002bc4 - -0000000080002bcc : - 80002bcc: 00900193 li gp,9 - 80002bd0: 0010009b addiw ra,zero,1 - 80002bd4: 02009093 slli ra,ra,0x20 - 80002bd8: ffe08093 addi ra,ra,-2 - 80002bdc: 0010011b addiw sp,zero,1 - 80002be0: 02011113 slli sp,sp,0x20 - 80002be4: fff10113 addi sp,sp,-1 - 80002be8: 0020f463 bleu sp,ra,80002bf0 - 80002bec: 00301463 bne zero,gp,80002bf4 - 80002bf0: 2c301863 bne zero,gp,80002ec0 - 80002bf4: fe20fee3 bleu sp,ra,80002bf0 - -0000000080002bf8 : - 80002bf8: 00a00193 li gp,10 - 80002bfc: 00000093 li ra,0 - 80002c00: 0010011b addiw sp,zero,1 - 80002c04: 02011113 slli sp,sp,0x20 - 80002c08: fff10113 addi sp,sp,-1 - 80002c0c: 0020f463 bleu sp,ra,80002c14 - 80002c10: 00301463 bne zero,gp,80002c18 - 80002c14: 2a301663 bne zero,gp,80002ec0 - 80002c18: fe20fee3 bleu sp,ra,80002c14 - -0000000080002c1c : - 80002c1c: 00b00193 li gp,11 - 80002c20: 800000b7 lui ra,0x80000 - 80002c24: fff0809b addiw ra,ra,-1 - 80002c28: 0010011b addiw sp,zero,1 - 80002c2c: 01f11113 slli sp,sp,0x1f - 80002c30: 0020f463 bleu sp,ra,80002c38 - 80002c34: 00301463 bne zero,gp,80002c3c - 80002c38: 28301463 bne zero,gp,80002ec0 - 80002c3c: fe20fee3 bleu sp,ra,80002c38 - -0000000080002c40 : - 80002c40: 00c00193 li gp,12 - 80002c44: 00000213 li tp,0 - 80002c48: 00f0009b addiw ra,zero,15 - 80002c4c: 01c09093 slli ra,ra,0x1c - 80002c50: fff08093 addi ra,ra,-1 # ffffffff7fffffff <_end+0xfffffffeffff780f> - 80002c54: 00f0011b addiw sp,zero,15 - 80002c58: 01c11113 slli sp,sp,0x1c - 80002c5c: 2620f263 bleu sp,ra,80002ec0 - 80002c60: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c64: 00200293 li t0,2 - 80002c68: fe5210e3 bne tp,t0,80002c48 - -0000000080002c6c : - 80002c6c: 00d00193 li gp,13 - 80002c70: 00000213 li tp,0 - 80002c74: 00f0009b addiw ra,zero,15 - 80002c78: 01c09093 slli ra,ra,0x1c - 80002c7c: fff08093 addi ra,ra,-1 - 80002c80: 00f0011b addiw sp,zero,15 - 80002c84: 01c11113 slli sp,sp,0x1c - 80002c88: 00000013 nop - 80002c8c: 2220fa63 bleu sp,ra,80002ec0 - 80002c90: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c94: 00200293 li t0,2 - 80002c98: fc521ee3 bne tp,t0,80002c74 - -0000000080002c9c : - 80002c9c: 00e00193 li gp,14 - 80002ca0: 00000213 li tp,0 - 80002ca4: 00f0009b addiw ra,zero,15 - 80002ca8: 01c09093 slli ra,ra,0x1c - 80002cac: fff08093 addi ra,ra,-1 - 80002cb0: 00f0011b addiw sp,zero,15 - 80002cb4: 01c11113 slli sp,sp,0x1c - 80002cb8: 00000013 nop - 80002cbc: 00000013 nop - 80002cc0: 2020f063 bleu sp,ra,80002ec0 - 80002cc4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cc8: 00200293 li t0,2 - 80002ccc: fc521ce3 bne tp,t0,80002ca4 - -0000000080002cd0 : - 80002cd0: 00f00193 li gp,15 - 80002cd4: 00000213 li tp,0 - 80002cd8: 00f0009b addiw ra,zero,15 - 80002cdc: 01c09093 slli ra,ra,0x1c - 80002ce0: fff08093 addi ra,ra,-1 - 80002ce4: 00000013 nop - 80002ce8: 00f0011b addiw sp,zero,15 - 80002cec: 01c11113 slli sp,sp,0x1c - 80002cf0: 1c20f863 bleu sp,ra,80002ec0 - 80002cf4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cf8: 00200293 li t0,2 - 80002cfc: fc521ee3 bne tp,t0,80002cd8 - -0000000080002d00 : - 80002d00: 01000193 li gp,16 - 80002d04: 00000213 li tp,0 - 80002d08: 00f0009b addiw ra,zero,15 - 80002d0c: 01c09093 slli ra,ra,0x1c - 80002d10: fff08093 addi ra,ra,-1 - 80002d14: 00000013 nop - 80002d18: 00f0011b addiw sp,zero,15 - 80002d1c: 01c11113 slli sp,sp,0x1c - 80002d20: 00000013 nop - 80002d24: 1820fe63 bleu sp,ra,80002ec0 - 80002d28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d2c: 00200293 li t0,2 - 80002d30: fc521ce3 bne tp,t0,80002d08 - -0000000080002d34 : - 80002d34: 01100193 li gp,17 - 80002d38: 00000213 li tp,0 - 80002d3c: 00f0009b addiw ra,zero,15 - 80002d40: 01c09093 slli ra,ra,0x1c - 80002d44: fff08093 addi ra,ra,-1 - 80002d48: 00000013 nop - 80002d4c: 00000013 nop - 80002d50: 00f0011b addiw sp,zero,15 - 80002d54: 01c11113 slli sp,sp,0x1c - 80002d58: 1620f463 bleu sp,ra,80002ec0 - 80002d5c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d60: 00200293 li t0,2 - 80002d64: fc521ce3 bne tp,t0,80002d3c - -0000000080002d68 : - 80002d68: 01200193 li gp,18 - 80002d6c: 00000213 li tp,0 - 80002d70: 00f0009b addiw ra,zero,15 - 80002d74: 01c09093 slli ra,ra,0x1c - 80002d78: fff08093 addi ra,ra,-1 - 80002d7c: 00f0011b addiw sp,zero,15 - 80002d80: 01c11113 slli sp,sp,0x1c - 80002d84: 1220fe63 bleu sp,ra,80002ec0 - 80002d88: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d8c: 00200293 li t0,2 - 80002d90: fe5210e3 bne tp,t0,80002d70 - -0000000080002d94 : - 80002d94: 01300193 li gp,19 - 80002d98: 00000213 li tp,0 - 80002d9c: 00f0009b addiw ra,zero,15 - 80002da0: 01c09093 slli ra,ra,0x1c - 80002da4: fff08093 addi ra,ra,-1 - 80002da8: 00f0011b addiw sp,zero,15 - 80002dac: 01c11113 slli sp,sp,0x1c - 80002db0: 00000013 nop - 80002db4: 1020f663 bleu sp,ra,80002ec0 - 80002db8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dbc: 00200293 li t0,2 - 80002dc0: fc521ee3 bne tp,t0,80002d9c - -0000000080002dc4 : - 80002dc4: 01400193 li gp,20 - 80002dc8: 00000213 li tp,0 - 80002dcc: 00f0009b addiw ra,zero,15 - 80002dd0: 01c09093 slli ra,ra,0x1c - 80002dd4: fff08093 addi ra,ra,-1 - 80002dd8: 00f0011b addiw sp,zero,15 - 80002ddc: 01c11113 slli sp,sp,0x1c - 80002de0: 00000013 nop - 80002de4: 00000013 nop - 80002de8: 0c20fc63 bleu sp,ra,80002ec0 - 80002dec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002df0: 00200293 li t0,2 - 80002df4: fc521ce3 bne tp,t0,80002dcc - -0000000080002df8 : - 80002df8: 01500193 li gp,21 - 80002dfc: 00000213 li tp,0 - 80002e00: 00f0009b addiw ra,zero,15 - 80002e04: 01c09093 slli ra,ra,0x1c - 80002e08: fff08093 addi ra,ra,-1 - 80002e0c: 00000013 nop - 80002e10: 00f0011b addiw sp,zero,15 - 80002e14: 01c11113 slli sp,sp,0x1c - 80002e18: 0a20f463 bleu sp,ra,80002ec0 - 80002e1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e20: 00200293 li t0,2 - 80002e24: fc521ee3 bne tp,t0,80002e00 - -0000000080002e28 : - 80002e28: 01600193 li gp,22 - 80002e2c: 00000213 li tp,0 - 80002e30: 00f0009b addiw ra,zero,15 - 80002e34: 01c09093 slli ra,ra,0x1c - 80002e38: fff08093 addi ra,ra,-1 - 80002e3c: 00000013 nop - 80002e40: 00f0011b addiw sp,zero,15 - 80002e44: 01c11113 slli sp,sp,0x1c - 80002e48: 00000013 nop - 80002e4c: 0620fa63 bleu sp,ra,80002ec0 - 80002e50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e54: 00200293 li t0,2 - 80002e58: fc521ce3 bne tp,t0,80002e30 - -0000000080002e5c : - 80002e5c: 01700193 li gp,23 - 80002e60: 00000213 li tp,0 - 80002e64: 00f0009b addiw ra,zero,15 - 80002e68: 01c09093 slli ra,ra,0x1c - 80002e6c: fff08093 addi ra,ra,-1 - 80002e70: 00000013 nop - 80002e74: 00000013 nop - 80002e78: 00f0011b addiw sp,zero,15 - 80002e7c: 01c11113 slli sp,sp,0x1c - 80002e80: 0420f063 bleu sp,ra,80002ec0 - 80002e84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e88: 00200293 li t0,2 - 80002e8c: fc521ce3 bne tp,t0,80002e64 - -0000000080002e90 : - 80002e90: 00100093 li ra,1 - 80002e94: 0000fa63 bleu zero,ra,80002ea8 - 80002e98: 00108093 addi ra,ra,1 - 80002e9c: 00108093 addi ra,ra,1 - 80002ea0: 00108093 addi ra,ra,1 - 80002ea4: 00108093 addi ra,ra,1 - 80002ea8: 00108093 addi ra,ra,1 - 80002eac: 00108093 addi ra,ra,1 - 80002eb0: 00300e93 li t4,3 - 80002eb4: 01800193 li gp,24 - 80002eb8: 01d09463 bne ra,t4,80002ec0 - 80002ebc: 00301a63 bne zero,gp,80002ed0 - -0000000080002ec0 : - 80002ec0: 00119513 slli a0,gp,0x1 - 80002ec4: 00050063 beqz a0,80002ec4 - 80002ec8: 00156513 ori a0,a0,1 - 80002ecc: 00000073 ecall - -0000000080002ed0 : - 80002ed0: 00100513 li a0,1 - 80002ed4: 00000073 ecall - 80002ed8: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-bgeu.elf b/test/riscv/tests/rv64ui-v-bgeu.elf deleted file mode 100644 index 469b8175..00000000 Binary files a/test/riscv/tests/rv64ui-v-bgeu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-blt.dump b/test/riscv/tests/rv64ui-v-blt.dump deleted file mode 100644 index c0eaae64..00000000 --- a/test/riscv/tests/rv64ui-v-blt.dump +++ /dev/null @@ -1,1054 +0,0 @@ - -rv64ui-v-blt: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 95068693 addi a3,a3,-1712 # 80002da8 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 98460613 addi a2,a2,-1660 # 80002e38 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 94c60613 addi a2,a2,-1716 # 80002e50 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 89c68693 addi a3,a3,-1892 # 80002df0 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 8b868693 addi a3,a3,-1864 # 80002f28 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 83860613 addi a2,a2,-1992 # 80002f00 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 76c68693 addi a3,a3,1900 # 80002f58 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 68c68693 addi a3,a3,1676 # 80002ec8 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 61c68693 addi a3,a3,1564 # 80002e90 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 01300793 li a5,19 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 01a3a7b7 lui a5,0x1a3a - 80002a70: 000805b7 lui a1,0x80 - 80002a74: b4178793 addi a5,a5,-1215 # 1a39b41 <_start-0x7e5c64bf> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00200193 li gp,2 - 80002acc: 00000093 li ra,0 - 80002ad0: 00100113 li sp,1 - 80002ad4: 0020c663 blt ra,sp,80002ae0 - 80002ad8: 2a301863 bne zero,gp,80002d88 - 80002adc: 00301663 bne zero,gp,80002ae8 - 80002ae0: fe20cee3 blt ra,sp,80002adc - 80002ae4: 2a301263 bne zero,gp,80002d88 - -0000000080002ae8 : - 80002ae8: 00300193 li gp,3 - 80002aec: fff00093 li ra,-1 - 80002af0: 00100113 li sp,1 - 80002af4: 0020c663 blt ra,sp,80002b00 - 80002af8: 28301863 bne zero,gp,80002d88 - 80002afc: 00301663 bne zero,gp,80002b08 - 80002b00: fe20cee3 blt ra,sp,80002afc - 80002b04: 28301263 bne zero,gp,80002d88 - -0000000080002b08 : - 80002b08: 00400193 li gp,4 - 80002b0c: ffe00093 li ra,-2 - 80002b10: fff00113 li sp,-1 - 80002b14: 0020c663 blt ra,sp,80002b20 - 80002b18: 26301863 bne zero,gp,80002d88 - 80002b1c: 00301663 bne zero,gp,80002b28 - 80002b20: fe20cee3 blt ra,sp,80002b1c - 80002b24: 26301263 bne zero,gp,80002d88 - -0000000080002b28 : - 80002b28: 00500193 li gp,5 - 80002b2c: 00100093 li ra,1 - 80002b30: 00000113 li sp,0 - 80002b34: 0020c463 blt ra,sp,80002b3c - 80002b38: 00301463 bne zero,gp,80002b40 - 80002b3c: 24301663 bne zero,gp,80002d88 - 80002b40: fe20cee3 blt ra,sp,80002b3c - -0000000080002b44 : - 80002b44: 00600193 li gp,6 - 80002b48: 00100093 li ra,1 - 80002b4c: fff00113 li sp,-1 - 80002b50: 0020c463 blt ra,sp,80002b58 - 80002b54: 00301463 bne zero,gp,80002b5c - 80002b58: 22301863 bne zero,gp,80002d88 - 80002b5c: fe20cee3 blt ra,sp,80002b58 - -0000000080002b60 : - 80002b60: 00700193 li gp,7 - 80002b64: fff00093 li ra,-1 - 80002b68: ffe00113 li sp,-2 - 80002b6c: 0020c463 blt ra,sp,80002b74 - 80002b70: 00301463 bne zero,gp,80002b78 - 80002b74: 20301a63 bne zero,gp,80002d88 - 80002b78: fe20cee3 blt ra,sp,80002b74 - -0000000080002b7c : - 80002b7c: 00800193 li gp,8 - 80002b80: 00100093 li ra,1 - 80002b84: ffe00113 li sp,-2 - 80002b88: 0020c463 blt ra,sp,80002b90 - 80002b8c: 00301463 bne zero,gp,80002b94 - 80002b90: 1e301c63 bne zero,gp,80002d88 - 80002b94: fe20cee3 blt ra,sp,80002b90 - -0000000080002b98 : - 80002b98: 00900193 li gp,9 - 80002b9c: 00000213 li tp,0 - 80002ba0: 00000093 li ra,0 - 80002ba4: fff00113 li sp,-1 - 80002ba8: 1e20c063 blt ra,sp,80002d88 - 80002bac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002bb0: 00200293 li t0,2 - 80002bb4: fe5216e3 bne tp,t0,80002ba0 - -0000000080002bb8 : - 80002bb8: 00a00193 li gp,10 - 80002bbc: 00000213 li tp,0 - 80002bc0: 00000093 li ra,0 - 80002bc4: fff00113 li sp,-1 - 80002bc8: 00000013 nop - 80002bcc: 1a20ce63 blt ra,sp,80002d88 - 80002bd0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002bd4: 00200293 li t0,2 - 80002bd8: fe5214e3 bne tp,t0,80002bc0 - -0000000080002bdc : - 80002bdc: 00b00193 li gp,11 - 80002be0: 00000213 li tp,0 - 80002be4: 00000093 li ra,0 - 80002be8: fff00113 li sp,-1 - 80002bec: 00000013 nop - 80002bf0: 00000013 nop - 80002bf4: 1820ca63 blt ra,sp,80002d88 - 80002bf8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002bfc: 00200293 li t0,2 - 80002c00: fe5212e3 bne tp,t0,80002be4 - -0000000080002c04 : - 80002c04: 00c00193 li gp,12 - 80002c08: 00000213 li tp,0 - 80002c0c: 00000093 li ra,0 - 80002c10: 00000013 nop - 80002c14: fff00113 li sp,-1 - 80002c18: 1620c863 blt ra,sp,80002d88 - 80002c1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c20: 00200293 li t0,2 - 80002c24: fe5214e3 bne tp,t0,80002c0c - -0000000080002c28 : - 80002c28: 00d00193 li gp,13 - 80002c2c: 00000213 li tp,0 - 80002c30: 00000093 li ra,0 - 80002c34: 00000013 nop - 80002c38: fff00113 li sp,-1 - 80002c3c: 00000013 nop - 80002c40: 1420c463 blt ra,sp,80002d88 - 80002c44: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c48: 00200293 li t0,2 - 80002c4c: fe5212e3 bne tp,t0,80002c30 - -0000000080002c50 : - 80002c50: 00e00193 li gp,14 - 80002c54: 00000213 li tp,0 - 80002c58: 00000093 li ra,0 - 80002c5c: 00000013 nop - 80002c60: 00000013 nop - 80002c64: fff00113 li sp,-1 - 80002c68: 1220c063 blt ra,sp,80002d88 - 80002c6c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c70: 00200293 li t0,2 - 80002c74: fe5212e3 bne tp,t0,80002c58 - -0000000080002c78 : - 80002c78: 00f00193 li gp,15 - 80002c7c: 00000213 li tp,0 - 80002c80: 00000093 li ra,0 - 80002c84: fff00113 li sp,-1 - 80002c88: 1020c063 blt ra,sp,80002d88 - 80002c8c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c90: 00200293 li t0,2 - 80002c94: fe5216e3 bne tp,t0,80002c80 - -0000000080002c98 : - 80002c98: 01000193 li gp,16 - 80002c9c: 00000213 li tp,0 - 80002ca0: 00000093 li ra,0 - 80002ca4: fff00113 li sp,-1 - 80002ca8: 00000013 nop - 80002cac: 0c20ce63 blt ra,sp,80002d88 - 80002cb0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cb4: 00200293 li t0,2 - 80002cb8: fe5214e3 bne tp,t0,80002ca0 - -0000000080002cbc : - 80002cbc: 01100193 li gp,17 - 80002cc0: 00000213 li tp,0 - 80002cc4: 00000093 li ra,0 - 80002cc8: fff00113 li sp,-1 - 80002ccc: 00000013 nop - 80002cd0: 00000013 nop - 80002cd4: 0a20ca63 blt ra,sp,80002d88 - 80002cd8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cdc: 00200293 li t0,2 - 80002ce0: fe5212e3 bne tp,t0,80002cc4 - -0000000080002ce4 : - 80002ce4: 01200193 li gp,18 - 80002ce8: 00000213 li tp,0 - 80002cec: 00000093 li ra,0 - 80002cf0: 00000013 nop - 80002cf4: fff00113 li sp,-1 - 80002cf8: 0820c863 blt ra,sp,80002d88 - 80002cfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d00: 00200293 li t0,2 - 80002d04: fe5214e3 bne tp,t0,80002cec - -0000000080002d08 : - 80002d08: 01300193 li gp,19 - 80002d0c: 00000213 li tp,0 - 80002d10: 00000093 li ra,0 - 80002d14: 00000013 nop - 80002d18: fff00113 li sp,-1 - 80002d1c: 00000013 nop - 80002d20: 0620c463 blt ra,sp,80002d88 - 80002d24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d28: 00200293 li t0,2 - 80002d2c: fe5212e3 bne tp,t0,80002d10 - -0000000080002d30 : - 80002d30: 01400193 li gp,20 - 80002d34: 00000213 li tp,0 - 80002d38: 00000093 li ra,0 - 80002d3c: 00000013 nop - 80002d40: 00000013 nop - 80002d44: fff00113 li sp,-1 - 80002d48: 0420c063 blt ra,sp,80002d88 - 80002d4c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d50: 00200293 li t0,2 - 80002d54: fe5212e3 bne tp,t0,80002d38 - -0000000080002d58 : - 80002d58: 00100093 li ra,1 - 80002d5c: 00104a63 bgtz ra,80002d70 - 80002d60: 00108093 addi ra,ra,1 - 80002d64: 00108093 addi ra,ra,1 - 80002d68: 00108093 addi ra,ra,1 - 80002d6c: 00108093 addi ra,ra,1 - 80002d70: 00108093 addi ra,ra,1 - 80002d74: 00108093 addi ra,ra,1 - 80002d78: 00300e93 li t4,3 - 80002d7c: 01500193 li gp,21 - 80002d80: 01d09463 bne ra,t4,80002d88 - 80002d84: 00301a63 bne zero,gp,80002d98 - -0000000080002d88 : - 80002d88: 00119513 slli a0,gp,0x1 - 80002d8c: 00050063 beqz a0,80002d8c - 80002d90: 00156513 ori a0,a0,1 - 80002d94: 00000073 ecall - -0000000080002d98 : - 80002d98: 00100513 li a0,1 - 80002d9c: 00000073 ecall - 80002da0: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-blt.elf b/test/riscv/tests/rv64ui-v-blt.elf deleted file mode 100644 index 1232ebb1..00000000 Binary files a/test/riscv/tests/rv64ui-v-blt.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-bltu.dump b/test/riscv/tests/rv64ui-v-bltu.dump deleted file mode 100644 index bf46506a..00000000 --- a/test/riscv/tests/rv64ui-v-bltu.dump +++ /dev/null @@ -1,1104 +0,0 @@ - -rv64ui-v-bltu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: a1868693 addi a3,a3,-1512 # 80002e70 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: a4c60613 addi a2,a2,-1460 # 80002f00 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: a1460613 addi a2,a2,-1516 # 80002f18 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 96468693 addi a3,a3,-1692 # 80002eb8 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 98068693 addi a3,a3,-1664 # 80002ff0 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 90060613 addi a2,a2,-1792 # 80002fc8 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: 83468693 addi a3,a3,-1996 # 80003020 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 75468693 addi a3,a3,1876 # 80002f90 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 6e468693 addi a3,a3,1764 # 80002f58 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 03800793 li a5,56 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 09c3b7b7 lui a5,0x9c3b - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 9db78793 addi a5,a5,-1573 # 9c3a9db <_start-0x763c5625> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00200193 li gp,2 - 80002acc: 00000093 li ra,0 - 80002ad0: 00100113 li sp,1 - 80002ad4: 0020e663 bltu ra,sp,80002ae0 - 80002ad8: 36301c63 bne zero,gp,80002e50 - 80002adc: 00301663 bne zero,gp,80002ae8 - 80002ae0: fe20eee3 bltu ra,sp,80002adc - 80002ae4: 36301663 bne zero,gp,80002e50 - -0000000080002ae8 : - 80002ae8: 00300193 li gp,3 - 80002aec: 0010009b addiw ra,zero,1 - 80002af0: 02009093 slli ra,ra,0x20 - 80002af4: ffe08093 addi ra,ra,-2 - 80002af8: 0010011b addiw sp,zero,1 - 80002afc: 02011113 slli sp,sp,0x20 - 80002b00: fff10113 addi sp,sp,-1 - 80002b04: 0020e663 bltu ra,sp,80002b10 - 80002b08: 34301463 bne zero,gp,80002e50 - 80002b0c: 00301663 bne zero,gp,80002b18 - 80002b10: fe20eee3 bltu ra,sp,80002b0c - 80002b14: 32301e63 bne zero,gp,80002e50 - -0000000080002b18 : - 80002b18: 00400193 li gp,4 - 80002b1c: 00000093 li ra,0 - 80002b20: 0010011b addiw sp,zero,1 - 80002b24: 02011113 slli sp,sp,0x20 - 80002b28: fff10113 addi sp,sp,-1 - 80002b2c: 0020e663 bltu ra,sp,80002b38 - 80002b30: 32301063 bne zero,gp,80002e50 - 80002b34: 00301663 bne zero,gp,80002b40 - 80002b38: fe20eee3 bltu ra,sp,80002b34 - 80002b3c: 30301a63 bne zero,gp,80002e50 - -0000000080002b40 : - 80002b40: 00500193 li gp,5 - 80002b44: 00100093 li ra,1 - 80002b48: 00000113 li sp,0 - 80002b4c: 0020e463 bltu ra,sp,80002b54 - 80002b50: 00301463 bne zero,gp,80002b58 - 80002b54: 2e301e63 bne zero,gp,80002e50 - 80002b58: fe20eee3 bltu ra,sp,80002b54 - -0000000080002b5c : - 80002b5c: 00600193 li gp,6 - 80002b60: 0010009b addiw ra,zero,1 - 80002b64: 02009093 slli ra,ra,0x20 - 80002b68: fff08093 addi ra,ra,-1 - 80002b6c: 0010011b addiw sp,zero,1 - 80002b70: 02011113 slli sp,sp,0x20 - 80002b74: ffe10113 addi sp,sp,-2 - 80002b78: 0020e463 bltu ra,sp,80002b80 - 80002b7c: 00301463 bne zero,gp,80002b84 - 80002b80: 2c301863 bne zero,gp,80002e50 - 80002b84: fe20eee3 bltu ra,sp,80002b80 - -0000000080002b88 : - 80002b88: 00700193 li gp,7 - 80002b8c: 0010009b addiw ra,zero,1 - 80002b90: 02009093 slli ra,ra,0x20 - 80002b94: fff08093 addi ra,ra,-1 - 80002b98: 00000113 li sp,0 - 80002b9c: 0020e463 bltu ra,sp,80002ba4 - 80002ba0: 00301463 bne zero,gp,80002ba8 - 80002ba4: 2a301663 bne zero,gp,80002e50 - 80002ba8: fe20eee3 bltu ra,sp,80002ba4 - -0000000080002bac : - 80002bac: 00800193 li gp,8 - 80002bb0: 0010009b addiw ra,zero,1 - 80002bb4: 01f09093 slli ra,ra,0x1f - 80002bb8: 80000137 lui sp,0x80000 - 80002bbc: fff1011b addiw sp,sp,-1 - 80002bc0: 0020e463 bltu ra,sp,80002bc8 - 80002bc4: 00301463 bne zero,gp,80002bcc - 80002bc8: 28301463 bne zero,gp,80002e50 - 80002bcc: fe20eee3 bltu ra,sp,80002bc8 - -0000000080002bd0 : - 80002bd0: 00900193 li gp,9 - 80002bd4: 00000213 li tp,0 - 80002bd8: 00f0009b addiw ra,zero,15 - 80002bdc: 01c09093 slli ra,ra,0x1c - 80002be0: 00f0011b addiw sp,zero,15 - 80002be4: 01c11113 slli sp,sp,0x1c - 80002be8: fff10113 addi sp,sp,-1 # ffffffff7fffffff <_end+0xfffffffeffff780f> - 80002bec: 2620e263 bltu ra,sp,80002e50 - 80002bf0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002bf4: 00200293 li t0,2 - 80002bf8: fe5210e3 bne tp,t0,80002bd8 - -0000000080002bfc : - 80002bfc: 00a00193 li gp,10 - 80002c00: 00000213 li tp,0 - 80002c04: 00f0009b addiw ra,zero,15 - 80002c08: 01c09093 slli ra,ra,0x1c - 80002c0c: 00f0011b addiw sp,zero,15 - 80002c10: 01c11113 slli sp,sp,0x1c - 80002c14: fff10113 addi sp,sp,-1 - 80002c18: 00000013 nop - 80002c1c: 2220ea63 bltu ra,sp,80002e50 - 80002c20: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c24: 00200293 li t0,2 - 80002c28: fc521ee3 bne tp,t0,80002c04 - -0000000080002c2c : - 80002c2c: 00b00193 li gp,11 - 80002c30: 00000213 li tp,0 - 80002c34: 00f0009b addiw ra,zero,15 - 80002c38: 01c09093 slli ra,ra,0x1c - 80002c3c: 00f0011b addiw sp,zero,15 - 80002c40: 01c11113 slli sp,sp,0x1c - 80002c44: fff10113 addi sp,sp,-1 - 80002c48: 00000013 nop - 80002c4c: 00000013 nop - 80002c50: 2020e063 bltu ra,sp,80002e50 - 80002c54: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c58: 00200293 li t0,2 - 80002c5c: fc521ce3 bne tp,t0,80002c34 - -0000000080002c60 : - 80002c60: 00c00193 li gp,12 - 80002c64: 00000213 li tp,0 - 80002c68: 00f0009b addiw ra,zero,15 - 80002c6c: 01c09093 slli ra,ra,0x1c - 80002c70: 00000013 nop - 80002c74: 00f0011b addiw sp,zero,15 - 80002c78: 01c11113 slli sp,sp,0x1c - 80002c7c: fff10113 addi sp,sp,-1 - 80002c80: 1c20e863 bltu ra,sp,80002e50 - 80002c84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c88: 00200293 li t0,2 - 80002c8c: fc521ee3 bne tp,t0,80002c68 - -0000000080002c90 : - 80002c90: 00d00193 li gp,13 - 80002c94: 00000213 li tp,0 - 80002c98: 00f0009b addiw ra,zero,15 - 80002c9c: 01c09093 slli ra,ra,0x1c - 80002ca0: 00000013 nop - 80002ca4: 00f0011b addiw sp,zero,15 - 80002ca8: 01c11113 slli sp,sp,0x1c - 80002cac: fff10113 addi sp,sp,-1 - 80002cb0: 00000013 nop - 80002cb4: 1820ee63 bltu ra,sp,80002e50 - 80002cb8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cbc: 00200293 li t0,2 - 80002cc0: fc521ce3 bne tp,t0,80002c98 - -0000000080002cc4 : - 80002cc4: 00e00193 li gp,14 - 80002cc8: 00000213 li tp,0 - 80002ccc: 00f0009b addiw ra,zero,15 - 80002cd0: 01c09093 slli ra,ra,0x1c - 80002cd4: 00000013 nop - 80002cd8: 00000013 nop - 80002cdc: 00f0011b addiw sp,zero,15 - 80002ce0: 01c11113 slli sp,sp,0x1c - 80002ce4: fff10113 addi sp,sp,-1 - 80002ce8: 1620e463 bltu ra,sp,80002e50 - 80002cec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cf0: 00200293 li t0,2 - 80002cf4: fc521ce3 bne tp,t0,80002ccc - -0000000080002cf8 : - 80002cf8: 00f00193 li gp,15 - 80002cfc: 00000213 li tp,0 - 80002d00: 00f0009b addiw ra,zero,15 - 80002d04: 01c09093 slli ra,ra,0x1c - 80002d08: 00f0011b addiw sp,zero,15 - 80002d0c: 01c11113 slli sp,sp,0x1c - 80002d10: fff10113 addi sp,sp,-1 - 80002d14: 1220ee63 bltu ra,sp,80002e50 - 80002d18: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d1c: 00200293 li t0,2 - 80002d20: fe5210e3 bne tp,t0,80002d00 - -0000000080002d24 : - 80002d24: 01000193 li gp,16 - 80002d28: 00000213 li tp,0 - 80002d2c: 00f0009b addiw ra,zero,15 - 80002d30: 01c09093 slli ra,ra,0x1c - 80002d34: 00f0011b addiw sp,zero,15 - 80002d38: 01c11113 slli sp,sp,0x1c - 80002d3c: fff10113 addi sp,sp,-1 - 80002d40: 00000013 nop - 80002d44: 1020e663 bltu ra,sp,80002e50 - 80002d48: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d4c: 00200293 li t0,2 - 80002d50: fc521ee3 bne tp,t0,80002d2c - -0000000080002d54 : - 80002d54: 01100193 li gp,17 - 80002d58: 00000213 li tp,0 - 80002d5c: 00f0009b addiw ra,zero,15 - 80002d60: 01c09093 slli ra,ra,0x1c - 80002d64: 00f0011b addiw sp,zero,15 - 80002d68: 01c11113 slli sp,sp,0x1c - 80002d6c: fff10113 addi sp,sp,-1 - 80002d70: 00000013 nop - 80002d74: 00000013 nop - 80002d78: 0c20ec63 bltu ra,sp,80002e50 - 80002d7c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d80: 00200293 li t0,2 - 80002d84: fc521ce3 bne tp,t0,80002d5c - -0000000080002d88 : - 80002d88: 01200193 li gp,18 - 80002d8c: 00000213 li tp,0 - 80002d90: 00f0009b addiw ra,zero,15 - 80002d94: 01c09093 slli ra,ra,0x1c - 80002d98: 00000013 nop - 80002d9c: 00f0011b addiw sp,zero,15 - 80002da0: 01c11113 slli sp,sp,0x1c - 80002da4: fff10113 addi sp,sp,-1 - 80002da8: 0a20e463 bltu ra,sp,80002e50 - 80002dac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002db0: 00200293 li t0,2 - 80002db4: fc521ee3 bne tp,t0,80002d90 - -0000000080002db8 : - 80002db8: 01300193 li gp,19 - 80002dbc: 00000213 li tp,0 - 80002dc0: 00f0009b addiw ra,zero,15 - 80002dc4: 01c09093 slli ra,ra,0x1c - 80002dc8: 00000013 nop - 80002dcc: 00f0011b addiw sp,zero,15 - 80002dd0: 01c11113 slli sp,sp,0x1c - 80002dd4: fff10113 addi sp,sp,-1 - 80002dd8: 00000013 nop - 80002ddc: 0620ea63 bltu ra,sp,80002e50 - 80002de0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002de4: 00200293 li t0,2 - 80002de8: fc521ce3 bne tp,t0,80002dc0 - -0000000080002dec : - 80002dec: 01400193 li gp,20 - 80002df0: 00000213 li tp,0 - 80002df4: 00f0009b addiw ra,zero,15 - 80002df8: 01c09093 slli ra,ra,0x1c - 80002dfc: 00000013 nop - 80002e00: 00000013 nop - 80002e04: 00f0011b addiw sp,zero,15 - 80002e08: 01c11113 slli sp,sp,0x1c - 80002e0c: fff10113 addi sp,sp,-1 - 80002e10: 0420e063 bltu ra,sp,80002e50 - 80002e14: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e18: 00200293 li t0,2 - 80002e1c: fc521ce3 bne tp,t0,80002df4 - -0000000080002e20 : - 80002e20: 00100093 li ra,1 - 80002e24: 00106a63 bltu zero,ra,80002e38 - 80002e28: 00108093 addi ra,ra,1 - 80002e2c: 00108093 addi ra,ra,1 - 80002e30: 00108093 addi ra,ra,1 - 80002e34: 00108093 addi ra,ra,1 - 80002e38: 00108093 addi ra,ra,1 - 80002e3c: 00108093 addi ra,ra,1 - 80002e40: 00300e93 li t4,3 - 80002e44: 01500193 li gp,21 - 80002e48: 01d09463 bne ra,t4,80002e50 - 80002e4c: 00301a63 bne zero,gp,80002e60 - -0000000080002e50 : - 80002e50: 00119513 slli a0,gp,0x1 - 80002e54: 00050063 beqz a0,80002e54 - 80002e58: 00156513 ori a0,a0,1 - 80002e5c: 00000073 ecall - -0000000080002e60 : - 80002e60: 00100513 li a0,1 - 80002e64: 00000073 ecall - 80002e68: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-bltu.elf b/test/riscv/tests/rv64ui-v-bltu.elf deleted file mode 100644 index 4109accb..00000000 Binary files a/test/riscv/tests/rv64ui-v-bltu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-bne.dump b/test/riscv/tests/rv64ui-v-bne.dump deleted file mode 100644 index 63ec2886..00000000 --- a/test/riscv/tests/rv64ui-v-bne.dump +++ /dev/null @@ -1,1055 +0,0 @@ - -rv64ui-v-bne: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 95068693 addi a3,a3,-1712 # 80002da8 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 98460613 addi a2,a2,-1660 # 80002e38 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 94c60613 addi a2,a2,-1716 # 80002e50 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 89c68693 addi a3,a3,-1892 # 80002df0 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 8b868693 addi a3,a3,-1864 # 80002f28 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 83860613 addi a2,a2,-1992 # 80002f00 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 76c68693 addi a3,a3,1900 # 80002f58 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 68c68693 addi a3,a3,1676 # 80002ec8 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 61c68693 addi a3,a3,1564 # 80002e90 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 02600793 li a5,38 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0802e7b7 lui a5,0x802e - 80002a70: 000805b7 lui a1,0x80 - 80002a74: d7978793 addi a5,a5,-647 # 802dd79 <_start-0x77fd2287> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00200193 li gp,2 - 80002acc: 00000093 li ra,0 - 80002ad0: 00100113 li sp,1 - 80002ad4: 00209663 bne ra,sp,80002ae0 - 80002ad8: 2a301a63 bne zero,gp,80002d8c - 80002adc: 00301663 bne zero,gp,80002ae8 - 80002ae0: fe209ee3 bne ra,sp,80002adc - 80002ae4: 2a301463 bne zero,gp,80002d8c - -0000000080002ae8 : - 80002ae8: 00300193 li gp,3 - 80002aec: 00100093 li ra,1 - 80002af0: 00000113 li sp,0 - 80002af4: 00209663 bne ra,sp,80002b00 - 80002af8: 28301a63 bne zero,gp,80002d8c - 80002afc: 00301663 bne zero,gp,80002b08 - 80002b00: fe209ee3 bne ra,sp,80002afc - 80002b04: 28301463 bne zero,gp,80002d8c - -0000000080002b08 : - 80002b08: 00400193 li gp,4 - 80002b0c: fff00093 li ra,-1 - 80002b10: 00100113 li sp,1 - 80002b14: 00209663 bne ra,sp,80002b20 - 80002b18: 26301a63 bne zero,gp,80002d8c - 80002b1c: 00301663 bne zero,gp,80002b28 - 80002b20: fe209ee3 bne ra,sp,80002b1c - 80002b24: 26301463 bne zero,gp,80002d8c - -0000000080002b28 : - 80002b28: 00500193 li gp,5 - 80002b2c: 00100093 li ra,1 - 80002b30: fff00113 li sp,-1 - 80002b34: 00209663 bne ra,sp,80002b40 - 80002b38: 24301a63 bne zero,gp,80002d8c - 80002b3c: 00301663 bne zero,gp,80002b48 - 80002b40: fe209ee3 bne ra,sp,80002b3c - 80002b44: 24301463 bne zero,gp,80002d8c - -0000000080002b48 : - 80002b48: 00600193 li gp,6 - 80002b4c: 00000093 li ra,0 - 80002b50: 00000113 li sp,0 - 80002b54: 00209463 bne ra,sp,80002b5c - 80002b58: 00301463 bne zero,gp,80002b60 - 80002b5c: 22301863 bne zero,gp,80002d8c - 80002b60: fe209ee3 bne ra,sp,80002b5c - -0000000080002b64 : - 80002b64: 00700193 li gp,7 - 80002b68: 00100093 li ra,1 - 80002b6c: 00100113 li sp,1 - 80002b70: 00209463 bne ra,sp,80002b78 - 80002b74: 00301463 bne zero,gp,80002b7c - 80002b78: 20301a63 bne zero,gp,80002d8c - 80002b7c: fe209ee3 bne ra,sp,80002b78 - -0000000080002b80 : - 80002b80: 00800193 li gp,8 - 80002b84: fff00093 li ra,-1 - 80002b88: fff00113 li sp,-1 - 80002b8c: 00209463 bne ra,sp,80002b94 - 80002b90: 00301463 bne zero,gp,80002b98 - 80002b94: 1e301c63 bne zero,gp,80002d8c - 80002b98: fe209ee3 bne ra,sp,80002b94 - -0000000080002b9c : - 80002b9c: 00900193 li gp,9 - 80002ba0: 00000213 li tp,0 - 80002ba4: 00000093 li ra,0 - 80002ba8: 00000113 li sp,0 - 80002bac: 1e209063 bne ra,sp,80002d8c - 80002bb0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002bb4: 00200293 li t0,2 - 80002bb8: fe5216e3 bne tp,t0,80002ba4 - -0000000080002bbc : - 80002bbc: 00a00193 li gp,10 - 80002bc0: 00000213 li tp,0 - 80002bc4: 00000093 li ra,0 - 80002bc8: 00000113 li sp,0 - 80002bcc: 00000013 nop - 80002bd0: 1a209e63 bne ra,sp,80002d8c - 80002bd4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002bd8: 00200293 li t0,2 - 80002bdc: fe5214e3 bne tp,t0,80002bc4 - -0000000080002be0 : - 80002be0: 00b00193 li gp,11 - 80002be4: 00000213 li tp,0 - 80002be8: 00000093 li ra,0 - 80002bec: 00000113 li sp,0 - 80002bf0: 00000013 nop - 80002bf4: 00000013 nop - 80002bf8: 18209a63 bne ra,sp,80002d8c - 80002bfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c00: 00200293 li t0,2 - 80002c04: fe5212e3 bne tp,t0,80002be8 - -0000000080002c08 : - 80002c08: 00c00193 li gp,12 - 80002c0c: 00000213 li tp,0 - 80002c10: 00000093 li ra,0 - 80002c14: 00000013 nop - 80002c18: 00000113 li sp,0 - 80002c1c: 16209863 bne ra,sp,80002d8c - 80002c20: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c24: 00200293 li t0,2 - 80002c28: fe5214e3 bne tp,t0,80002c10 - -0000000080002c2c : - 80002c2c: 00d00193 li gp,13 - 80002c30: 00000213 li tp,0 - 80002c34: 00000093 li ra,0 - 80002c38: 00000013 nop - 80002c3c: 00000113 li sp,0 - 80002c40: 00000013 nop - 80002c44: 14209463 bne ra,sp,80002d8c - 80002c48: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c4c: 00200293 li t0,2 - 80002c50: fe5212e3 bne tp,t0,80002c34 - -0000000080002c54 : - 80002c54: 00e00193 li gp,14 - 80002c58: 00000213 li tp,0 - 80002c5c: 00000093 li ra,0 - 80002c60: 00000013 nop - 80002c64: 00000013 nop - 80002c68: 00000113 li sp,0 - 80002c6c: 12209063 bne ra,sp,80002d8c - 80002c70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c74: 00200293 li t0,2 - 80002c78: fe5212e3 bne tp,t0,80002c5c - -0000000080002c7c : - 80002c7c: 00f00193 li gp,15 - 80002c80: 00000213 li tp,0 - 80002c84: 00000093 li ra,0 - 80002c88: 00000113 li sp,0 - 80002c8c: 10209063 bne ra,sp,80002d8c - 80002c90: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c94: 00200293 li t0,2 - 80002c98: fe5216e3 bne tp,t0,80002c84 - -0000000080002c9c : - 80002c9c: 01000193 li gp,16 - 80002ca0: 00000213 li tp,0 - 80002ca4: 00000093 li ra,0 - 80002ca8: 00000113 li sp,0 - 80002cac: 00000013 nop - 80002cb0: 0c209e63 bne ra,sp,80002d8c - 80002cb4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cb8: 00200293 li t0,2 - 80002cbc: fe5214e3 bne tp,t0,80002ca4 - -0000000080002cc0 : - 80002cc0: 01100193 li gp,17 - 80002cc4: 00000213 li tp,0 - 80002cc8: 00000093 li ra,0 - 80002ccc: 00000113 li sp,0 - 80002cd0: 00000013 nop - 80002cd4: 00000013 nop - 80002cd8: 0a209a63 bne ra,sp,80002d8c - 80002cdc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ce0: 00200293 li t0,2 - 80002ce4: fe5212e3 bne tp,t0,80002cc8 - -0000000080002ce8 : - 80002ce8: 01200193 li gp,18 - 80002cec: 00000213 li tp,0 - 80002cf0: 00000093 li ra,0 - 80002cf4: 00000013 nop - 80002cf8: 00000113 li sp,0 - 80002cfc: 08209863 bne ra,sp,80002d8c - 80002d00: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d04: 00200293 li t0,2 - 80002d08: fe5214e3 bne tp,t0,80002cf0 - -0000000080002d0c : - 80002d0c: 01300193 li gp,19 - 80002d10: 00000213 li tp,0 - 80002d14: 00000093 li ra,0 - 80002d18: 00000013 nop - 80002d1c: 00000113 li sp,0 - 80002d20: 00000013 nop - 80002d24: 06209463 bne ra,sp,80002d8c - 80002d28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d2c: 00200293 li t0,2 - 80002d30: fe5212e3 bne tp,t0,80002d14 - -0000000080002d34 : - 80002d34: 01400193 li gp,20 - 80002d38: 00000213 li tp,0 - 80002d3c: 00000093 li ra,0 - 80002d40: 00000013 nop - 80002d44: 00000013 nop - 80002d48: 00000113 li sp,0 - 80002d4c: 04209063 bne ra,sp,80002d8c - 80002d50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d54: 00200293 li t0,2 - 80002d58: fe5212e3 bne tp,t0,80002d3c - -0000000080002d5c : - 80002d5c: 00100093 li ra,1 - 80002d60: 00009a63 bnez ra,80002d74 - 80002d64: 00108093 addi ra,ra,1 - 80002d68: 00108093 addi ra,ra,1 - 80002d6c: 00108093 addi ra,ra,1 - 80002d70: 00108093 addi ra,ra,1 - 80002d74: 00108093 addi ra,ra,1 - 80002d78: 00108093 addi ra,ra,1 - 80002d7c: 00300e93 li t4,3 - 80002d80: 01500193 li gp,21 - 80002d84: 01d09463 bne ra,t4,80002d8c - 80002d88: 00301a63 bne zero,gp,80002d9c - -0000000080002d8c : - 80002d8c: 00119513 slli a0,gp,0x1 - 80002d90: 00050063 beqz a0,80002d90 - 80002d94: 00156513 ori a0,a0,1 - 80002d98: 00000073 ecall - -0000000080002d9c : - 80002d9c: 00100513 li a0,1 - 80002da0: 00000073 ecall - 80002da4: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-bne.elf b/test/riscv/tests/rv64ui-v-bne.elf deleted file mode 100644 index fa480bf2..00000000 Binary files a/test/riscv/tests/rv64ui-v-bne.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-fence_i.dump b/test/riscv/tests/rv64ui-v-fence_i.dump deleted file mode 100644 index b559930c..00000000 --- a/test/riscv/tests/rv64ui-v-fence_i.dump +++ /dev/null @@ -1,959 +0,0 @@ - -rv64ui-v-fence_i: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: ad050513 addi a0,a0,-1328 # 80002b00 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 7d868693 addi a3,a3,2008 # 80002c30 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 80c60613 addi a2,a2,-2036 # 80002cc0 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 7d460613 addi a2,a2,2004 # 80002cd8 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 72468693 addi a3,a3,1828 # 80002c78 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 74068693 addi a3,a3,1856 # 80002db0 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 6c060613 addi a2,a2,1728 # 80002d88 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 5f468693 addi a3,a3,1524 # 80002de0 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 51468693 addi a3,a3,1300 # 80002d50 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 4a468693 addi a3,a3,1188 # 80002d18 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 03300793 li a5,51 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 032fe7b7 lui a5,0x32fe - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 19f78793 addi a5,a5,415 # 32fe19f <_start-0x7cd01e61> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - 80002ac8: 0000 unimp - 80002aca: 0000 unimp - 80002acc: 0000 unimp - 80002ace: 0000 unimp - 80002ad0: 0000 unimp - 80002ad2: 0000 unimp - 80002ad4: 0000 unimp - 80002ad6: 0000 unimp - 80002ad8: 0000 unimp - 80002ada: 0000 unimp - 80002adc: 0000 unimp - 80002ade: 0000 unimp - 80002ae0: 0000 unimp - 80002ae2: 0000 unimp - 80002ae4: 0000 unimp - 80002ae6: 0000 unimp - 80002ae8: 0000 unimp - 80002aea: 0000 unimp - 80002aec: 0000 unimp - 80002aee: 0000 unimp - 80002af0: 0000 unimp - 80002af2: 0000 unimp - 80002af4: 0000 unimp - 80002af6: 0000 unimp - 80002af8: 0000 unimp - 80002afa: 0000 unimp - 80002afc: 0000 unimp - 80002afe: 0000 unimp - -0000000080002b00 : - 80002b00: 06f00693 li a3,111 - 80002b04: 00000517 auipc a0,0x0 - 80002b08: 4fc51503 lh a0,1276(a0) # 80003000 - 80002b0c: 00000597 auipc a1,0x0 - 80002b10: 4f659583 lh a1,1270(a1) # 80003002 - 80002b14: 00000013 nop - 80002b18: 00000013 nop - 80002b1c: 00000013 nop - 80002b20: 00000013 nop - 80002b24: 00000013 nop - 80002b28: 00000013 nop - 80002b2c: 00000013 nop - 80002b30: 00000013 nop - 80002b34: 00000013 nop - 80002b38: 00000013 nop - 80002b3c: 00000013 nop - 80002b40: 00000297 auipc t0,0x0 - 80002b44: 00a29a23 sh a0,20(t0) # 80002b54 - 80002b48: 00000297 auipc t0,0x0 - 80002b4c: 00b29723 sh a1,14(t0) # 80002b56 - 80002b50: 0000100f fence.i - 80002b54: 0de68693 addi a3,a3,222 - -0000000080002b58 : - 80002b58: 00000013 nop - 80002b5c: 1bc00e93 li t4,444 - 80002b60: 00200193 li gp,2 - 80002b64: 07d69a63 bne a3,t4,80002bd8 - 80002b68: 06400713 li a4,100 - 80002b6c: fff70713 addi a4,a4,-1 - 80002b70: fe071ee3 bnez a4,80002b6c - 80002b74: 00000297 auipc t0,0x0 - 80002b78: 04a29623 sh a0,76(t0) # 80002bc0 - 80002b7c: 00000297 auipc t0,0x0 - 80002b80: 04b29323 sh a1,70(t0) # 80002bc2 - 80002b84: 0000100f fence.i - 80002b88: 00000013 nop - 80002b8c: 00000013 nop - 80002b90: 00000013 nop - 80002b94: 00000013 nop - 80002b98: 00000013 nop - 80002b9c: 00000013 nop - 80002ba0: 00000013 nop - 80002ba4: 00000013 nop - 80002ba8: 00000013 nop - 80002bac: 00000013 nop - 80002bb0: 00000013 nop - 80002bb4: 00000013 nop - 80002bb8: 00000013 nop - 80002bbc: 00000013 nop - 80002bc0: 22b68693 addi a3,a3,555 - -0000000080002bc4 : - 80002bc4: 00000013 nop - 80002bc8: 30900e93 li t4,777 - 80002bcc: 00300193 li gp,3 - 80002bd0: 01d69463 bne a3,t4,80002bd8 - 80002bd4: 00301a63 bne zero,gp,80002be8 - -0000000080002bd8 : - 80002bd8: 00119513 slli a0,gp,0x1 - 80002bdc: 00050063 beqz a0,80002bdc - 80002be0: 00156513 ori a0,a0,1 - 80002be4: 00000073 ecall - -0000000080002be8 : - 80002be8: 00100513 li a0,1 - 80002bec: 00000073 ecall - 80002bf0: c0001073 unimp - 80002bf4: 0000 unimp - 80002bf6: 0000 unimp - 80002bf8: 0000 unimp - 80002bfa: 0000 unimp - 80002bfc: 0000 unimp - 80002bfe: 0000 unimp - 80002c00: 0000 unimp - 80002c02: 0000 unimp - 80002c04: 0000 unimp - 80002c06: 0000 unimp - 80002c08: 0000 unimp - 80002c0a: 0000 unimp - 80002c0c: 0000 unimp - 80002c0e: 0000 unimp - 80002c10: 0000 unimp - 80002c12: 0000 unimp - 80002c14: 0000 unimp - 80002c16: 0000 unimp - 80002c18: 0000 unimp - 80002c1a: 0000 unimp - 80002c1c: 0000 unimp - 80002c1e: 0000 unimp - 80002c20: 0000 unimp - 80002c22: 0000 unimp - 80002c24: 0000 unimp - 80002c26: 0000 unimp - 80002c28: 0000 unimp - 80002c2a: 0000 unimp - -Disassembly of section .data: - -0000000080003000 : - 80003000: 14d68693 addi a3,a3,333 diff --git a/test/riscv/tests/rv64ui-v-fence_i.elf b/test/riscv/tests/rv64ui-v-fence_i.elf deleted file mode 100644 index 5ab09908..00000000 Binary files a/test/riscv/tests/rv64ui-v-fence_i.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-jal.dump b/test/riscv/tests/rv64ui-v-jal.dump deleted file mode 100644 index a22031d1..00000000 --- a/test/riscv/tests/rv64ui-v-jal.dump +++ /dev/null @@ -1,867 +0,0 @@ - -rv64ui-v-jal: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 6e068693 addi a3,a3,1760 # 80002b38 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 71460613 addi a2,a2,1812 # 80002bc8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6dc60613 addi a2,a2,1756 # 80002be0 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 62c68693 addi a3,a3,1580 # 80002b80 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 64868693 addi a3,a3,1608 # 80002cb8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5c860613 addi a2,a2,1480 # 80002c90 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 4fc68693 addi a3,a3,1276 # 80002ce8 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 41c68693 addi a3,a3,1052 # 80002c58 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 3ac68693 addi a3,a3,940 # 80002c20 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 02d00793 li a5,45 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0e1d97b7 lui a5,0xe1d9 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: ad378793 addi a5,a5,-1325 # e1d8ad3 <_start-0x71e2752d> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00200193 li gp,2 - 80002acc: 00000093 li ra,0 - 80002ad0: 0100026f jal tp,80002ae0 - -0000000080002ad4 : - 80002ad4: 00000013 nop - 80002ad8: 00000013 nop - 80002adc: 0400006f j 80002b1c - -0000000080002ae0 : - 80002ae0: 00000117 auipc sp,0x0 - 80002ae4: ff410113 addi sp,sp,-12 # 80002ad4 - 80002ae8: 02411a63 bne sp,tp,80002b1c - -0000000080002aec : - 80002aec: 00100093 li ra,1 - 80002af0: 0140006f j 80002b04 - 80002af4: 00108093 addi ra,ra,1 - 80002af8: 00108093 addi ra,ra,1 - 80002afc: 00108093 addi ra,ra,1 - 80002b00: 00108093 addi ra,ra,1 - 80002b04: 00108093 addi ra,ra,1 - 80002b08: 00108093 addi ra,ra,1 - 80002b0c: 00300e93 li t4,3 - 80002b10: 00300193 li gp,3 - 80002b14: 01d09463 bne ra,t4,80002b1c - 80002b18: 00301a63 bne zero,gp,80002b2c - -0000000080002b1c : - 80002b1c: 00119513 slli a0,gp,0x1 - 80002b20: 00050063 beqz a0,80002b20 - 80002b24: 00156513 ori a0,a0,1 - 80002b28: 00000073 ecall - -0000000080002b2c : - 80002b2c: 00100513 li a0,1 - 80002b30: 00000073 ecall - 80002b34: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-jal.elf b/test/riscv/tests/rv64ui-v-jal.elf deleted file mode 100644 index 82efaa89..00000000 Binary files a/test/riscv/tests/rv64ui-v-jal.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-jalr.dump b/test/riscv/tests/rv64ui-v-jalr.dump deleted file mode 100644 index 4b43b163..00000000 --- a/test/riscv/tests/rv64ui-v-jalr.dump +++ /dev/null @@ -1,905 +0,0 @@ - -rv64ui-v-jalr: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 76068693 addi a3,a3,1888 # 80002bb8 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 79460613 addi a2,a2,1940 # 80002c48 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 75c60613 addi a2,a2,1884 # 80002c60 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 6ac68693 addi a3,a3,1708 # 80002c00 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 6c868693 addi a3,a3,1736 # 80002d38 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 64860613 addi a2,a2,1608 # 80002d10 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 57c68693 addi a3,a3,1404 # 80002d68 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 49c68693 addi a3,a3,1180 # 80002cd8 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 42c68693 addi a3,a3,1068 # 80002ca0 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 01600793 li a5,22 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 044267b7 lui a5,0x4426 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 9b478793 addi a5,a5,-1612 # 44259b4 <_start-0x7bbda64c> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00200193 li gp,2 - 80002acc: 00000293 li t0,0 - 80002ad0: 00000317 auipc t1,0x0 - 80002ad4: 01030313 addi t1,t1,16 # 80002ae0 - 80002ad8: 000302e7 jalr t0,t1 - -0000000080002adc : - 80002adc: 0c00006f j 80002b9c - -0000000080002ae0 : - 80002ae0: 00000317 auipc t1,0x0 - 80002ae4: ffc30313 addi t1,t1,-4 # 80002adc - 80002ae8: 0a629a63 bne t0,t1,80002b9c - -0000000080002aec : - 80002aec: 00400193 li gp,4 - 80002af0: 00000213 li tp,0 - 80002af4: 00000317 auipc t1,0x0 - 80002af8: 01030313 addi t1,t1,16 # 80002b04 - 80002afc: 000309e7 jalr s3,t1 - 80002b00: 08301e63 bne zero,gp,80002b9c - 80002b04: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002b08: 00200293 li t0,2 - 80002b0c: fe5214e3 bne tp,t0,80002af4 - -0000000080002b10 : - 80002b10: 00500193 li gp,5 - 80002b14: 00000213 li tp,0 - 80002b18: 00000317 auipc t1,0x0 - 80002b1c: 01430313 addi t1,t1,20 # 80002b2c - 80002b20: 00000013 nop - 80002b24: 000309e7 jalr s3,t1 - 80002b28: 06301a63 bne zero,gp,80002b9c - 80002b2c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002b30: 00200293 li t0,2 - 80002b34: fe5212e3 bne tp,t0,80002b18 - -0000000080002b38 : - 80002b38: 00600193 li gp,6 - 80002b3c: 00000213 li tp,0 - 80002b40: 00000317 auipc t1,0x0 - 80002b44: 01830313 addi t1,t1,24 # 80002b58 - 80002b48: 00000013 nop - 80002b4c: 00000013 nop - 80002b50: 000309e7 jalr s3,t1 - 80002b54: 04301463 bne zero,gp,80002b9c - 80002b58: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002b5c: 00200293 li t0,2 - 80002b60: fe5210e3 bne tp,t0,80002b40 - -0000000080002b64 : - 80002b64: 00100293 li t0,1 - 80002b68: 00000317 auipc t1,0x0 - 80002b6c: 01c30313 addi t1,t1,28 # 80002b84 - 80002b70: ffc30067 jr -4(t1) - 80002b74: 00128293 addi t0,t0,1 - 80002b78: 00128293 addi t0,t0,1 - 80002b7c: 00128293 addi t0,t0,1 - 80002b80: 00128293 addi t0,t0,1 - 80002b84: 00128293 addi t0,t0,1 - 80002b88: 00128293 addi t0,t0,1 - 80002b8c: 00400e93 li t4,4 - 80002b90: 00700193 li gp,7 - 80002b94: 01d29463 bne t0,t4,80002b9c - 80002b98: 00301a63 bne zero,gp,80002bac - -0000000080002b9c : - 80002b9c: 00119513 slli a0,gp,0x1 - 80002ba0: 00050063 beqz a0,80002ba0 - 80002ba4: 00156513 ori a0,a0,1 - 80002ba8: 00000073 ecall - -0000000080002bac : - 80002bac: 00100513 li a0,1 - 80002bb0: 00000073 ecall - 80002bb4: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-jalr.elf b/test/riscv/tests/rv64ui-v-jalr.elf deleted file mode 100644 index 80442747..00000000 Binary files a/test/riscv/tests/rv64ui-v-jalr.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-lb.dump b/test/riscv/tests/rv64ui-v-lb.dump deleted file mode 100644 index fc9d680e..00000000 --- a/test/riscv/tests/rv64ui-v-lb.dump +++ /dev/null @@ -1,1037 +0,0 @@ - -rv64ui-v-lb: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 8d868693 addi a3,a3,-1832 # 80002d30 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 90c60613 addi a2,a2,-1780 # 80002dc0 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 8d460613 addi a2,a2,-1836 # 80002dd8 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 82468693 addi a3,a3,-2012 # 80002d78 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 84068693 addi a3,a3,-1984 # 80002eb0 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 7c060613 addi a2,a2,1984 # 80002e88 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 6f468693 addi a3,a3,1780 # 80002ee0 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 61468693 addi a3,a3,1556 # 80002e50 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 5a468693 addi a3,a3,1444 # 80002e18 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 00600793 li a5,6 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0c1067b7 lui a5,0xc106 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 32278793 addi a5,a5,802 # c106322 <_start-0x73ef9cde> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000097 auipc ra,0x0 - 80002acc: 53808093 addi ra,ra,1336 # 80003000 - 80002ad0: 00008f03 lb t5,0(ra) - 80002ad4: fff00e93 li t4,-1 - 80002ad8: 00200193 li gp,2 - 80002adc: 23df1c63 bne t5,t4,80002d14 - -0000000080002ae0 : - 80002ae0: 00000097 auipc ra,0x0 - 80002ae4: 52008093 addi ra,ra,1312 # 80003000 - 80002ae8: 00108f03 lb t5,1(ra) - 80002aec: 00000e93 li t4,0 - 80002af0: 00300193 li gp,3 - 80002af4: 23df1063 bne t5,t4,80002d14 - -0000000080002af8 : - 80002af8: 00000097 auipc ra,0x0 - 80002afc: 50808093 addi ra,ra,1288 # 80003000 - 80002b00: 00208f03 lb t5,2(ra) - 80002b04: ff000e93 li t4,-16 - 80002b08: 00400193 li gp,4 - 80002b0c: 21df1463 bne t5,t4,80002d14 - -0000000080002b10 : - 80002b10: 00000097 auipc ra,0x0 - 80002b14: 4f008093 addi ra,ra,1264 # 80003000 - 80002b18: 00308f03 lb t5,3(ra) - 80002b1c: 00f00e93 li t4,15 - 80002b20: 00500193 li gp,5 - 80002b24: 1fdf1863 bne t5,t4,80002d14 - -0000000080002b28 : - 80002b28: 00000097 auipc ra,0x0 - 80002b2c: 4db08093 addi ra,ra,1243 # 80003003 - 80002b30: ffd08f03 lb t5,-3(ra) - 80002b34: fff00e93 li t4,-1 - 80002b38: 00600193 li gp,6 - 80002b3c: 1ddf1c63 bne t5,t4,80002d14 - -0000000080002b40 : - 80002b40: 00000097 auipc ra,0x0 - 80002b44: 4c308093 addi ra,ra,1219 # 80003003 - 80002b48: ffe08f03 lb t5,-2(ra) - 80002b4c: 00000e93 li t4,0 - 80002b50: 00700193 li gp,7 - 80002b54: 1ddf1063 bne t5,t4,80002d14 - -0000000080002b58 : - 80002b58: 00000097 auipc ra,0x0 - 80002b5c: 4ab08093 addi ra,ra,1195 # 80003003 - 80002b60: fff08f03 lb t5,-1(ra) - 80002b64: ff000e93 li t4,-16 - 80002b68: 00800193 li gp,8 - 80002b6c: 1bdf1463 bne t5,t4,80002d14 - -0000000080002b70 : - 80002b70: 00000097 auipc ra,0x0 - 80002b74: 49308093 addi ra,ra,1171 # 80003003 - 80002b78: 00008f03 lb t5,0(ra) - 80002b7c: 00f00e93 li t4,15 - 80002b80: 00900193 li gp,9 - 80002b84: 19df1863 bne t5,t4,80002d14 - -0000000080002b88 : - 80002b88: 00000097 auipc ra,0x0 - 80002b8c: 47808093 addi ra,ra,1144 # 80003000 - 80002b90: fe008093 addi ra,ra,-32 - 80002b94: 02008283 lb t0,32(ra) - 80002b98: fff00e93 li t4,-1 - 80002b9c: 00a00193 li gp,10 - 80002ba0: 17d29a63 bne t0,t4,80002d14 - -0000000080002ba4 : - 80002ba4: 00000097 auipc ra,0x0 - 80002ba8: 45c08093 addi ra,ra,1116 # 80003000 - 80002bac: ffa08093 addi ra,ra,-6 - 80002bb0: 00708283 lb t0,7(ra) - 80002bb4: 00000e93 li t4,0 - 80002bb8: 00b00193 li gp,11 - 80002bbc: 15d29c63 bne t0,t4,80002d14 - -0000000080002bc0 : - 80002bc0: 00c00193 li gp,12 - 80002bc4: 00000213 li tp,0 - 80002bc8: 00000097 auipc ra,0x0 - 80002bcc: 43908093 addi ra,ra,1081 # 80003001 - 80002bd0: 00108f03 lb t5,1(ra) - 80002bd4: 000f0313 mv t1,t5 - 80002bd8: ff000e93 li t4,-16 - 80002bdc: 13d31c63 bne t1,t4,80002d14 - 80002be0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002be4: 00200293 li t0,2 - 80002be8: fe5210e3 bne tp,t0,80002bc8 - -0000000080002bec : - 80002bec: 00d00193 li gp,13 - 80002bf0: 00000213 li tp,0 - 80002bf4: 00000097 auipc ra,0x0 - 80002bf8: 40e08093 addi ra,ra,1038 # 80003002 - 80002bfc: 00108f03 lb t5,1(ra) - 80002c00: 00000013 nop - 80002c04: 000f0313 mv t1,t5 - 80002c08: 00f00e93 li t4,15 - 80002c0c: 11d31463 bne t1,t4,80002d14 - 80002c10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c14: 00200293 li t0,2 - 80002c18: fc521ee3 bne tp,t0,80002bf4 - -0000000080002c1c : - 80002c1c: 00e00193 li gp,14 - 80002c20: 00000213 li tp,0 - 80002c24: 00000097 auipc ra,0x0 - 80002c28: 3dc08093 addi ra,ra,988 # 80003000 - 80002c2c: 00108f03 lb t5,1(ra) - 80002c30: 00000013 nop - 80002c34: 00000013 nop - 80002c38: 000f0313 mv t1,t5 - 80002c3c: 00000e93 li t4,0 - 80002c40: 0dd31a63 bne t1,t4,80002d14 - 80002c44: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c48: 00200293 li t0,2 - 80002c4c: fc521ce3 bne tp,t0,80002c24 - -0000000080002c50 : - 80002c50: 00f00193 li gp,15 - 80002c54: 00000213 li tp,0 - 80002c58: 00000097 auipc ra,0x0 - 80002c5c: 3a908093 addi ra,ra,937 # 80003001 - 80002c60: 00108f03 lb t5,1(ra) - 80002c64: ff000e93 li t4,-16 - 80002c68: 0bdf1663 bne t5,t4,80002d14 - 80002c6c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c70: 00200293 li t0,2 - 80002c74: fe5212e3 bne tp,t0,80002c58 - -0000000080002c78 : - 80002c78: 01000193 li gp,16 - 80002c7c: 00000213 li tp,0 - 80002c80: 00000097 auipc ra,0x0 - 80002c84: 38208093 addi ra,ra,898 # 80003002 - 80002c88: 00000013 nop - 80002c8c: 00108f03 lb t5,1(ra) - 80002c90: 00f00e93 li t4,15 - 80002c94: 09df1063 bne t5,t4,80002d14 - 80002c98: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c9c: 00200293 li t0,2 - 80002ca0: fe5210e3 bne tp,t0,80002c80 - -0000000080002ca4 : - 80002ca4: 01100193 li gp,17 - 80002ca8: 00000213 li tp,0 - 80002cac: 00000097 auipc ra,0x0 - 80002cb0: 35408093 addi ra,ra,852 # 80003000 - 80002cb4: 00000013 nop - 80002cb8: 00000013 nop - 80002cbc: 00108f03 lb t5,1(ra) - 80002cc0: 00000e93 li t4,0 - 80002cc4: 05df1863 bne t5,t4,80002d14 - 80002cc8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ccc: 00200293 li t0,2 - 80002cd0: fc521ee3 bne tp,t0,80002cac - -0000000080002cd4 : - 80002cd4: 00000297 auipc t0,0x0 - 80002cd8: 32c28293 addi t0,t0,812 # 80003000 - 80002cdc: 00028103 lb sp,0(t0) - 80002ce0: 00200113 li sp,2 - 80002ce4: 00200e93 li t4,2 - 80002ce8: 01200193 li gp,18 - 80002cec: 03d11463 bne sp,t4,80002d14 - -0000000080002cf0 : - 80002cf0: 00000297 auipc t0,0x0 - 80002cf4: 31028293 addi t0,t0,784 # 80003000 - 80002cf8: 00028103 lb sp,0(t0) - 80002cfc: 00000013 nop - 80002d00: 00200113 li sp,2 - 80002d04: 00200e93 li t4,2 - 80002d08: 01300193 li gp,19 - 80002d0c: 01d11463 bne sp,t4,80002d14 - 80002d10: 00301a63 bne zero,gp,80002d24 - -0000000080002d14 : - 80002d14: 00119513 slli a0,gp,0x1 - 80002d18: 00050063 beqz a0,80002d18 - 80002d1c: 00156513 ori a0,a0,1 - 80002d20: 00000073 ecall - -0000000080002d24 : - 80002d24: 00100513 li a0,1 - 80002d28: 00000073 ecall - 80002d2c: c0001073 unimp - -Disassembly of section .data: - -0000000080003000 : - 80003000: 0xff - -0000000080003001 : - 80003001: sd s0,32(s0) - -0000000080003002 : - 80003002: addi a2,sp,988 - -0000000080003003 : - 80003003: 0f Address 0x0000000080003003 is out of bounds. - - 80003007: diff --git a/test/riscv/tests/rv64ui-v-lb.elf b/test/riscv/tests/rv64ui-v-lb.elf deleted file mode 100644 index 438c0905..00000000 Binary files a/test/riscv/tests/rv64ui-v-lb.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-lbu.dump b/test/riscv/tests/rv64ui-v-lbu.dump deleted file mode 100644 index 8de55fb8..00000000 --- a/test/riscv/tests/rv64ui-v-lbu.dump +++ /dev/null @@ -1,1037 +0,0 @@ - -rv64ui-v-lbu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 8d868693 addi a3,a3,-1832 # 80002d30 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 90c60613 addi a2,a2,-1780 # 80002dc0 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 8d460613 addi a2,a2,-1836 # 80002dd8 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 82468693 addi a3,a3,-2012 # 80002d78 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 84068693 addi a3,a3,-1984 # 80002eb0 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 7c060613 addi a2,a2,1984 # 80002e88 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 6f468693 addi a3,a3,1780 # 80002ee0 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 61468693 addi a3,a3,1556 # 80002e50 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 5a468693 addi a3,a3,1444 # 80002e18 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 00d00793 li a5,13 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 04c8f7b7 lui a5,0x4c8f - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 8a478793 addi a5,a5,-1884 # 4c8e8a4 <_start-0x7b37175c> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000097 auipc ra,0x0 - 80002acc: 53808093 addi ra,ra,1336 # 80003000 - 80002ad0: 0000cf03 lbu t5,0(ra) - 80002ad4: 0ff00e93 li t4,255 - 80002ad8: 00200193 li gp,2 - 80002adc: 23df1c63 bne t5,t4,80002d14 - -0000000080002ae0 : - 80002ae0: 00000097 auipc ra,0x0 - 80002ae4: 52008093 addi ra,ra,1312 # 80003000 - 80002ae8: 0010cf03 lbu t5,1(ra) - 80002aec: 00000e93 li t4,0 - 80002af0: 00300193 li gp,3 - 80002af4: 23df1063 bne t5,t4,80002d14 - -0000000080002af8 : - 80002af8: 00000097 auipc ra,0x0 - 80002afc: 50808093 addi ra,ra,1288 # 80003000 - 80002b00: 0020cf03 lbu t5,2(ra) - 80002b04: 0f000e93 li t4,240 - 80002b08: 00400193 li gp,4 - 80002b0c: 21df1463 bne t5,t4,80002d14 - -0000000080002b10 : - 80002b10: 00000097 auipc ra,0x0 - 80002b14: 4f008093 addi ra,ra,1264 # 80003000 - 80002b18: 0030cf03 lbu t5,3(ra) - 80002b1c: 00f00e93 li t4,15 - 80002b20: 00500193 li gp,5 - 80002b24: 1fdf1863 bne t5,t4,80002d14 - -0000000080002b28 : - 80002b28: 00000097 auipc ra,0x0 - 80002b2c: 4db08093 addi ra,ra,1243 # 80003003 - 80002b30: ffd0cf03 lbu t5,-3(ra) - 80002b34: 0ff00e93 li t4,255 - 80002b38: 00600193 li gp,6 - 80002b3c: 1ddf1c63 bne t5,t4,80002d14 - -0000000080002b40 : - 80002b40: 00000097 auipc ra,0x0 - 80002b44: 4c308093 addi ra,ra,1219 # 80003003 - 80002b48: ffe0cf03 lbu t5,-2(ra) - 80002b4c: 00000e93 li t4,0 - 80002b50: 00700193 li gp,7 - 80002b54: 1ddf1063 bne t5,t4,80002d14 - -0000000080002b58 : - 80002b58: 00000097 auipc ra,0x0 - 80002b5c: 4ab08093 addi ra,ra,1195 # 80003003 - 80002b60: fff0cf03 lbu t5,-1(ra) - 80002b64: 0f000e93 li t4,240 - 80002b68: 00800193 li gp,8 - 80002b6c: 1bdf1463 bne t5,t4,80002d14 - -0000000080002b70 : - 80002b70: 00000097 auipc ra,0x0 - 80002b74: 49308093 addi ra,ra,1171 # 80003003 - 80002b78: 0000cf03 lbu t5,0(ra) - 80002b7c: 00f00e93 li t4,15 - 80002b80: 00900193 li gp,9 - 80002b84: 19df1863 bne t5,t4,80002d14 - -0000000080002b88 : - 80002b88: 00000097 auipc ra,0x0 - 80002b8c: 47808093 addi ra,ra,1144 # 80003000 - 80002b90: fe008093 addi ra,ra,-32 - 80002b94: 0200c283 lbu t0,32(ra) - 80002b98: 0ff00e93 li t4,255 - 80002b9c: 00a00193 li gp,10 - 80002ba0: 17d29a63 bne t0,t4,80002d14 - -0000000080002ba4 : - 80002ba4: 00000097 auipc ra,0x0 - 80002ba8: 45c08093 addi ra,ra,1116 # 80003000 - 80002bac: ffa08093 addi ra,ra,-6 - 80002bb0: 0070c283 lbu t0,7(ra) - 80002bb4: 00000e93 li t4,0 - 80002bb8: 00b00193 li gp,11 - 80002bbc: 15d29c63 bne t0,t4,80002d14 - -0000000080002bc0 : - 80002bc0: 00c00193 li gp,12 - 80002bc4: 00000213 li tp,0 - 80002bc8: 00000097 auipc ra,0x0 - 80002bcc: 43908093 addi ra,ra,1081 # 80003001 - 80002bd0: 0010cf03 lbu t5,1(ra) - 80002bd4: 000f0313 mv t1,t5 - 80002bd8: 0f000e93 li t4,240 - 80002bdc: 13d31c63 bne t1,t4,80002d14 - 80002be0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002be4: 00200293 li t0,2 - 80002be8: fe5210e3 bne tp,t0,80002bc8 - -0000000080002bec : - 80002bec: 00d00193 li gp,13 - 80002bf0: 00000213 li tp,0 - 80002bf4: 00000097 auipc ra,0x0 - 80002bf8: 40e08093 addi ra,ra,1038 # 80003002 - 80002bfc: 0010cf03 lbu t5,1(ra) - 80002c00: 00000013 nop - 80002c04: 000f0313 mv t1,t5 - 80002c08: 00f00e93 li t4,15 - 80002c0c: 11d31463 bne t1,t4,80002d14 - 80002c10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c14: 00200293 li t0,2 - 80002c18: fc521ee3 bne tp,t0,80002bf4 - -0000000080002c1c : - 80002c1c: 00e00193 li gp,14 - 80002c20: 00000213 li tp,0 - 80002c24: 00000097 auipc ra,0x0 - 80002c28: 3dc08093 addi ra,ra,988 # 80003000 - 80002c2c: 0010cf03 lbu t5,1(ra) - 80002c30: 00000013 nop - 80002c34: 00000013 nop - 80002c38: 000f0313 mv t1,t5 - 80002c3c: 00000e93 li t4,0 - 80002c40: 0dd31a63 bne t1,t4,80002d14 - 80002c44: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c48: 00200293 li t0,2 - 80002c4c: fc521ce3 bne tp,t0,80002c24 - -0000000080002c50 : - 80002c50: 00f00193 li gp,15 - 80002c54: 00000213 li tp,0 - 80002c58: 00000097 auipc ra,0x0 - 80002c5c: 3a908093 addi ra,ra,937 # 80003001 - 80002c60: 0010cf03 lbu t5,1(ra) - 80002c64: 0f000e93 li t4,240 - 80002c68: 0bdf1663 bne t5,t4,80002d14 - 80002c6c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c70: 00200293 li t0,2 - 80002c74: fe5212e3 bne tp,t0,80002c58 - -0000000080002c78 : - 80002c78: 01000193 li gp,16 - 80002c7c: 00000213 li tp,0 - 80002c80: 00000097 auipc ra,0x0 - 80002c84: 38208093 addi ra,ra,898 # 80003002 - 80002c88: 00000013 nop - 80002c8c: 0010cf03 lbu t5,1(ra) - 80002c90: 00f00e93 li t4,15 - 80002c94: 09df1063 bne t5,t4,80002d14 - 80002c98: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c9c: 00200293 li t0,2 - 80002ca0: fe5210e3 bne tp,t0,80002c80 - -0000000080002ca4 : - 80002ca4: 01100193 li gp,17 - 80002ca8: 00000213 li tp,0 - 80002cac: 00000097 auipc ra,0x0 - 80002cb0: 35408093 addi ra,ra,852 # 80003000 - 80002cb4: 00000013 nop - 80002cb8: 00000013 nop - 80002cbc: 0010cf03 lbu t5,1(ra) - 80002cc0: 00000e93 li t4,0 - 80002cc4: 05df1863 bne t5,t4,80002d14 - 80002cc8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ccc: 00200293 li t0,2 - 80002cd0: fc521ee3 bne tp,t0,80002cac - -0000000080002cd4 : - 80002cd4: 00000297 auipc t0,0x0 - 80002cd8: 32c28293 addi t0,t0,812 # 80003000 - 80002cdc: 0002c103 lbu sp,0(t0) - 80002ce0: 00200113 li sp,2 - 80002ce4: 00200e93 li t4,2 - 80002ce8: 01200193 li gp,18 - 80002cec: 03d11463 bne sp,t4,80002d14 - -0000000080002cf0 : - 80002cf0: 00000297 auipc t0,0x0 - 80002cf4: 31028293 addi t0,t0,784 # 80003000 - 80002cf8: 0002c103 lbu sp,0(t0) - 80002cfc: 00000013 nop - 80002d00: 00200113 li sp,2 - 80002d04: 00200e93 li t4,2 - 80002d08: 01300193 li gp,19 - 80002d0c: 01d11463 bne sp,t4,80002d14 - 80002d10: 00301a63 bne zero,gp,80002d24 - -0000000080002d14 : - 80002d14: 00119513 slli a0,gp,0x1 - 80002d18: 00050063 beqz a0,80002d18 - 80002d1c: 00156513 ori a0,a0,1 - 80002d20: 00000073 ecall - -0000000080002d24 : - 80002d24: 00100513 li a0,1 - 80002d28: 00000073 ecall - 80002d2c: c0001073 unimp - -Disassembly of section .data: - -0000000080003000 : - 80003000: 0xff - -0000000080003001 : - 80003001: sd s0,32(s0) - -0000000080003002 : - 80003002: addi a2,sp,988 - -0000000080003003 : - 80003003: 0f Address 0x0000000080003003 is out of bounds. - - 80003007: diff --git a/test/riscv/tests/rv64ui-v-lbu.elf b/test/riscv/tests/rv64ui-v-lbu.elf deleted file mode 100644 index 2f2023bb..00000000 Binary files a/test/riscv/tests/rv64ui-v-lbu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-ld.dump b/test/riscv/tests/rv64ui-v-ld.dump deleted file mode 100644 index 3d8b640c..00000000 --- a/test/riscv/tests/rv64ui-v-ld.dump +++ /dev/null @@ -1,1141 +0,0 @@ - -rv64ui-v-ld: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 0000a117 auipc sp,0xa - 8000001c: 6b810113 addi sp,sp,1720 # 8000a6d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00003617 auipc a2,0x3 - 80002318: cec60613 addi a2,a2,-788 # 80005000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00007797 auipc a5,0x7 - 80002334: 4b878793 addi a5,a5,1208 # 800097e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00007717 auipc a4,0x7 - 80002348: 49c70713 addi a4,a4,1180 # 800097e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00007897 auipc a7,0x7 - 80002354: 48f8bc23 sd a5,1176(a7) # 800097e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00007797 auipc a5,0x7 - 80002384: 07078793 addi a5,a5,112 # 800093f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf6810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00007797 auipc a5,0x7 - 80002448: 3807be23 sd zero,924(a5) # 800097e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: a5868693 addi a3,a3,-1448 # 80002eb0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: a8c60613 addi a2,a2,-1396 # 80002f40 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: a5460613 addi a2,a2,-1452 # 80002f58 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 9a468693 addi a3,a3,-1628 # 80002ef8 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 9c068693 addi a3,a3,-1600 # 80003030 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 94060613 addi a2,a2,-1728 # 80003008 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00007d17 auipc s10,0x7 - 80002720: cd4d0d13 addi s10,s10,-812 # 800093f0 - 80002724: 00003b97 auipc s7,0x3 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80005000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00007a17 auipc s4,0x7 - 80002738: 0aca0a13 addi s4,s4,172 # 800097e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00007717 auipc a4,0x7 - 8000274c: 08f73c23 sd a5,152(a4) # 800097e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00007717 auipc a4,0x7 - 800027d4: 00f73823 sd a5,16(a4) # 800097e0 - 800027d8: 00007717 auipc a4,0x7 - 800027dc: 00f73823 sd a5,16(a4) # 800097e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: 87468693 addi a3,a3,-1932 # 80003060 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 79468693 addi a3,a3,1940 # 80002fd0 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 72468693 addi a3,a3,1828 # 80002f98 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00003697 auipc a3,0x3 - 800028e0: 72468693 addi a3,a3,1828 # 80006000 - 800028e4: 00004717 auipc a4,0x4 - 800028e8: 71c70713 addi a4,a4,1820 # 80007000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00005797 auipc a5,0x5 - 800028f8: 70c78793 addi a5,a5,1804 # 80008000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00002897 auipc a7,0x2 - 80002914: 6ed8b823 sd a3,1776(a7) # 80005000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00003697 auipc a3,0x3 - 80002920: 6ce6be23 sd a4,1756(a3) # 80005ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00002617 auipc a2,0x2 - 80002938: 6cc60613 addi a2,a2,1740 # 80005000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00005697 auipc a3,0x5 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80007ff8 - 8000294c: 00003717 auipc a4,0x3 - 80002950: 6af73a23 sd a5,1716(a4) # 80006000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00006697 auipc a3,0x6 - 800029c0: 64468693 addi a3,a3,1604 # 80009000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00007617 auipc a2,0x7 - 800029d0: e0f63e23 sd a5,-484(a2) # 800097e8 - 800029d4: 00007797 auipc a5,0x7 - 800029d8: e0e7b623 sd a4,-500(a5) # 800097e0 - 800029dc: 00007317 auipc t1,0x7 - 800029e0: a1430313 addi t1,t1,-1516 # 800093f0 - 800029e4: 02d00793 li a5,45 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00007797 auipc a5,0x7 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800093e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 055417b7 lui a5,0x5541 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: b2578793 addi a5,a5,-1243 # 5540b25 <_start-0x7aabf4db> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00001097 auipc ra,0x1 - 80002acc: 53808093 addi ra,ra,1336 # 80004000 - 80002ad0: 0000bf03 ld t5,0(ra) - 80002ad4: 00ff0eb7 lui t4,0xff0 - 80002ad8: 0ffe8e9b addiw t4,t4,255 - 80002adc: 010e9e93 slli t4,t4,0x10 - 80002ae0: 0ffe8e93 addi t4,t4,255 # ff00ff <_start-0x7f00ff01> - 80002ae4: 010e9e93 slli t4,t4,0x10 - 80002ae8: 0ffe8e93 addi t4,t4,255 - 80002aec: 00200193 li gp,2 - 80002af0: 3bdf1263 bne t5,t4,80002e94 - -0000000080002af4 : - 80002af4: 00001097 auipc ra,0x1 - 80002af8: 50c08093 addi ra,ra,1292 # 80004000 - 80002afc: 0080bf03 ld t5,8(ra) - 80002b00: ff010eb7 lui t4,0xff010 - 80002b04: f01e8e9b addiw t4,t4,-255 - 80002b08: 010e9e93 slli t4,t4,0x10 - 80002b0c: f01e8e93 addi t4,t4,-255 # ffffffffff00ff01 <_end+0xffffffff7f006711> - 80002b10: 010e9e93 slli t4,t4,0x10 - 80002b14: f00e8e93 addi t4,t4,-256 - 80002b18: 00300193 li gp,3 - 80002b1c: 37df1c63 bne t5,t4,80002e94 - -0000000080002b20 : - 80002b20: 00001097 auipc ra,0x1 - 80002b24: 4e008093 addi ra,ra,1248 # 80004000 - 80002b28: 0100bf03 ld t5,16(ra) - 80002b2c: 00010eb7 lui t4,0x10 - 80002b30: f01e8e9b addiw t4,t4,-255 - 80002b34: 010e9e93 slli t4,t4,0x10 - 80002b38: f01e8e93 addi t4,t4,-255 # ff01 <_start-0x7fff00ff> - 80002b3c: 010e9e93 slli t4,t4,0x10 - 80002b40: f01e8e93 addi t4,t4,-255 - 80002b44: 00ce9e93 slli t4,t4,0xc - 80002b48: ff0e8e93 addi t4,t4,-16 - 80002b4c: 00400193 li gp,4 - 80002b50: 35df1263 bne t5,t4,80002e94 - -0000000080002b54 : - 80002b54: 00001097 auipc ra,0x1 - 80002b58: 4ac08093 addi ra,ra,1196 # 80004000 - 80002b5c: 0180bf03 ld t5,24(ra) - 80002b60: ffff0eb7 lui t4,0xffff0 - 80002b64: 0ffe8e9b addiw t4,t4,255 - 80002b68: 010e9e93 slli t4,t4,0x10 - 80002b6c: 0ffe8e93 addi t4,t4,255 # ffffffffffff00ff <_end+0xffffffff7ffe690f> - 80002b70: 010e9e93 slli t4,t4,0x10 - 80002b74: 0ffe8e93 addi t4,t4,255 - 80002b78: 00ce9e93 slli t4,t4,0xc - 80002b7c: 00fe8e93 addi t4,t4,15 - 80002b80: 00500193 li gp,5 - 80002b84: 31df1863 bne t5,t4,80002e94 - -0000000080002b88 : - 80002b88: 00001097 auipc ra,0x1 - 80002b8c: 49008093 addi ra,ra,1168 # 80004018 - 80002b90: fe80bf03 ld t5,-24(ra) - 80002b94: 00ff0eb7 lui t4,0xff0 - 80002b98: 0ffe8e9b addiw t4,t4,255 - 80002b9c: 010e9e93 slli t4,t4,0x10 - 80002ba0: 0ffe8e93 addi t4,t4,255 # ff00ff <_start-0x7f00ff01> - 80002ba4: 010e9e93 slli t4,t4,0x10 - 80002ba8: 0ffe8e93 addi t4,t4,255 - 80002bac: 00600193 li gp,6 - 80002bb0: 2fdf1263 bne t5,t4,80002e94 - -0000000080002bb4 : - 80002bb4: 00001097 auipc ra,0x1 - 80002bb8: 46408093 addi ra,ra,1124 # 80004018 - 80002bbc: ff00bf03 ld t5,-16(ra) - 80002bc0: ff010eb7 lui t4,0xff010 - 80002bc4: f01e8e9b addiw t4,t4,-255 - 80002bc8: 010e9e93 slli t4,t4,0x10 - 80002bcc: f01e8e93 addi t4,t4,-255 # ffffffffff00ff01 <_end+0xffffffff7f006711> - 80002bd0: 010e9e93 slli t4,t4,0x10 - 80002bd4: f00e8e93 addi t4,t4,-256 - 80002bd8: 00700193 li gp,7 - 80002bdc: 2bdf1c63 bne t5,t4,80002e94 - -0000000080002be0 : - 80002be0: 00001097 auipc ra,0x1 - 80002be4: 43808093 addi ra,ra,1080 # 80004018 - 80002be8: ff80bf03 ld t5,-8(ra) - 80002bec: 00010eb7 lui t4,0x10 - 80002bf0: f01e8e9b addiw t4,t4,-255 - 80002bf4: 010e9e93 slli t4,t4,0x10 - 80002bf8: f01e8e93 addi t4,t4,-255 # ff01 <_start-0x7fff00ff> - 80002bfc: 010e9e93 slli t4,t4,0x10 - 80002c00: f01e8e93 addi t4,t4,-255 - 80002c04: 00ce9e93 slli t4,t4,0xc - 80002c08: ff0e8e93 addi t4,t4,-16 - 80002c0c: 00800193 li gp,8 - 80002c10: 29df1263 bne t5,t4,80002e94 - -0000000080002c14 : - 80002c14: 00001097 auipc ra,0x1 - 80002c18: 40408093 addi ra,ra,1028 # 80004018 - 80002c1c: 0000bf03 ld t5,0(ra) - 80002c20: ffff0eb7 lui t4,0xffff0 - 80002c24: 0ffe8e9b addiw t4,t4,255 - 80002c28: 010e9e93 slli t4,t4,0x10 - 80002c2c: 0ffe8e93 addi t4,t4,255 # ffffffffffff00ff <_end+0xffffffff7ffe690f> - 80002c30: 010e9e93 slli t4,t4,0x10 - 80002c34: 0ffe8e93 addi t4,t4,255 - 80002c38: 00ce9e93 slli t4,t4,0xc - 80002c3c: 00fe8e93 addi t4,t4,15 - 80002c40: 00900193 li gp,9 - 80002c44: 25df1863 bne t5,t4,80002e94 - -0000000080002c48 : - 80002c48: 00001097 auipc ra,0x1 - 80002c4c: 3b808093 addi ra,ra,952 # 80004000 - 80002c50: fe008093 addi ra,ra,-32 - 80002c54: 0200b283 ld t0,32(ra) - 80002c58: 00ff0eb7 lui t4,0xff0 - 80002c5c: 0ffe8e9b addiw t4,t4,255 - 80002c60: 010e9e93 slli t4,t4,0x10 - 80002c64: 0ffe8e93 addi t4,t4,255 # ff00ff <_start-0x7f00ff01> - 80002c68: 010e9e93 slli t4,t4,0x10 - 80002c6c: 0ffe8e93 addi t4,t4,255 - 80002c70: 00a00193 li gp,10 - 80002c74: 23d29063 bne t0,t4,80002e94 - -0000000080002c78 : - 80002c78: 00001097 auipc ra,0x1 - 80002c7c: 38808093 addi ra,ra,904 # 80004000 - 80002c80: ffd08093 addi ra,ra,-3 - 80002c84: 00b0b283 ld t0,11(ra) - 80002c88: ff010eb7 lui t4,0xff010 - 80002c8c: f01e8e9b addiw t4,t4,-255 - 80002c90: 010e9e93 slli t4,t4,0x10 - 80002c94: f01e8e93 addi t4,t4,-255 # ffffffffff00ff01 <_end+0xffffffff7f006711> - 80002c98: 010e9e93 slli t4,t4,0x10 - 80002c9c: f00e8e93 addi t4,t4,-256 - 80002ca0: 00b00193 li gp,11 - 80002ca4: 1fd29863 bne t0,t4,80002e94 - -0000000080002ca8 : - 80002ca8: 00c00193 li gp,12 - 80002cac: 00000213 li tp,0 - 80002cb0: 00001097 auipc ra,0x1 - 80002cb4: 35808093 addi ra,ra,856 # 80004008 - 80002cb8: 0080bf03 ld t5,8(ra) - 80002cbc: 000f0313 mv t1,t5 - 80002cc0: 00010eb7 lui t4,0x10 - 80002cc4: f01e8e9b addiw t4,t4,-255 - 80002cc8: 010e9e93 slli t4,t4,0x10 - 80002ccc: f01e8e93 addi t4,t4,-255 # ff01 <_start-0x7fff00ff> - 80002cd0: 010e9e93 slli t4,t4,0x10 - 80002cd4: f01e8e93 addi t4,t4,-255 - 80002cd8: 00ce9e93 slli t4,t4,0xc - 80002cdc: ff0e8e93 addi t4,t4,-16 - 80002ce0: 1bd31a63 bne t1,t4,80002e94 - 80002ce4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ce8: 00200293 li t0,2 - 80002cec: fc5212e3 bne tp,t0,80002cb0 - -0000000080002cf0 : - 80002cf0: 00d00193 li gp,13 - 80002cf4: 00000213 li tp,0 - 80002cf8: 00001097 auipc ra,0x1 - 80002cfc: 31808093 addi ra,ra,792 # 80004010 - 80002d00: 0080bf03 ld t5,8(ra) - 80002d04: 00000013 nop - 80002d08: 000f0313 mv t1,t5 - 80002d0c: ffff0eb7 lui t4,0xffff0 - 80002d10: 0ffe8e9b addiw t4,t4,255 - 80002d14: 010e9e93 slli t4,t4,0x10 - 80002d18: 0ffe8e93 addi t4,t4,255 # ffffffffffff00ff <_end+0xffffffff7ffe690f> - 80002d1c: 010e9e93 slli t4,t4,0x10 - 80002d20: 0ffe8e93 addi t4,t4,255 - 80002d24: 00ce9e93 slli t4,t4,0xc - 80002d28: 00fe8e93 addi t4,t4,15 - 80002d2c: 17d31463 bne t1,t4,80002e94 - 80002d30: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d34: 00200293 li t0,2 - 80002d38: fc5210e3 bne tp,t0,80002cf8 - -0000000080002d3c : - 80002d3c: 00e00193 li gp,14 - 80002d40: 00000213 li tp,0 - 80002d44: 00001097 auipc ra,0x1 - 80002d48: 2bc08093 addi ra,ra,700 # 80004000 - 80002d4c: 0080bf03 ld t5,8(ra) - 80002d50: 00000013 nop - 80002d54: 00000013 nop - 80002d58: 000f0313 mv t1,t5 - 80002d5c: ff010eb7 lui t4,0xff010 - 80002d60: f01e8e9b addiw t4,t4,-255 - 80002d64: 010e9e93 slli t4,t4,0x10 - 80002d68: f01e8e93 addi t4,t4,-255 # ffffffffff00ff01 <_end+0xffffffff7f006711> - 80002d6c: 010e9e93 slli t4,t4,0x10 - 80002d70: f00e8e93 addi t4,t4,-256 - 80002d74: 13d31063 bne t1,t4,80002e94 - 80002d78: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d7c: 00200293 li t0,2 - 80002d80: fc5212e3 bne tp,t0,80002d44 - -0000000080002d84 : - 80002d84: 00f00193 li gp,15 - 80002d88: 00000213 li tp,0 - 80002d8c: 00001097 auipc ra,0x1 - 80002d90: 27c08093 addi ra,ra,636 # 80004008 - 80002d94: 0080bf03 ld t5,8(ra) - 80002d98: 00010eb7 lui t4,0x10 - 80002d9c: f01e8e9b addiw t4,t4,-255 - 80002da0: 010e9e93 slli t4,t4,0x10 - 80002da4: f01e8e93 addi t4,t4,-255 # ff01 <_start-0x7fff00ff> - 80002da8: 010e9e93 slli t4,t4,0x10 - 80002dac: f01e8e93 addi t4,t4,-255 - 80002db0: 00ce9e93 slli t4,t4,0xc - 80002db4: ff0e8e93 addi t4,t4,-16 - 80002db8: 0ddf1e63 bne t5,t4,80002e94 - 80002dbc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dc0: 00200293 li t0,2 - 80002dc4: fc5214e3 bne tp,t0,80002d8c - -0000000080002dc8 : - 80002dc8: 01000193 li gp,16 - 80002dcc: 00000213 li tp,0 - 80002dd0: 00001097 auipc ra,0x1 - 80002dd4: 24008093 addi ra,ra,576 # 80004010 - 80002dd8: 00000013 nop - 80002ddc: 0080bf03 ld t5,8(ra) - 80002de0: ffff0eb7 lui t4,0xffff0 - 80002de4: 0ffe8e9b addiw t4,t4,255 - 80002de8: 010e9e93 slli t4,t4,0x10 - 80002dec: 0ffe8e93 addi t4,t4,255 # ffffffffffff00ff <_end+0xffffffff7ffe690f> - 80002df0: 010e9e93 slli t4,t4,0x10 - 80002df4: 0ffe8e93 addi t4,t4,255 - 80002df8: 00ce9e93 slli t4,t4,0xc - 80002dfc: 00fe8e93 addi t4,t4,15 - 80002e00: 09df1a63 bne t5,t4,80002e94 - 80002e04: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e08: 00200293 li t0,2 - 80002e0c: fc5212e3 bne tp,t0,80002dd0 - -0000000080002e10 : - 80002e10: 01100193 li gp,17 - 80002e14: 00000213 li tp,0 - 80002e18: 00001097 auipc ra,0x1 - 80002e1c: 1e808093 addi ra,ra,488 # 80004000 - 80002e20: 00000013 nop - 80002e24: 00000013 nop - 80002e28: 0080bf03 ld t5,8(ra) - 80002e2c: ff010eb7 lui t4,0xff010 - 80002e30: f01e8e9b addiw t4,t4,-255 - 80002e34: 010e9e93 slli t4,t4,0x10 - 80002e38: f01e8e93 addi t4,t4,-255 # ffffffffff00ff01 <_end+0xffffffff7f006711> - 80002e3c: 010e9e93 slli t4,t4,0x10 - 80002e40: f00e8e93 addi t4,t4,-256 - 80002e44: 05df1863 bne t5,t4,80002e94 - 80002e48: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e4c: 00200293 li t0,2 - 80002e50: fc5214e3 bne tp,t0,80002e18 - -0000000080002e54 : - 80002e54: 00001297 auipc t0,0x1 - 80002e58: 1ac28293 addi t0,t0,428 # 80004000 - 80002e5c: 0002b103 ld sp,0(t0) - 80002e60: 00200113 li sp,2 - 80002e64: 00200e93 li t4,2 - 80002e68: 01200193 li gp,18 - 80002e6c: 03d11463 bne sp,t4,80002e94 - -0000000080002e70 : - 80002e70: 00001297 auipc t0,0x1 - 80002e74: 19028293 addi t0,t0,400 # 80004000 - 80002e78: 0002b103 ld sp,0(t0) - 80002e7c: 00000013 nop - 80002e80: 00200113 li sp,2 - 80002e84: 00200e93 li t4,2 - 80002e88: 01300193 li gp,19 - 80002e8c: 01d11463 bne sp,t4,80002e94 - 80002e90: 00301a63 bne zero,gp,80002ea4 - -0000000080002e94 : - 80002e94: 00119513 slli a0,gp,0x1 - 80002e98: 00050063 beqz a0,80002e98 - 80002e9c: 00156513 ori a0,a0,1 - 80002ea0: 00000073 ecall - -0000000080002ea4 : - 80002ea4: 00100513 li a0,1 - 80002ea8: 00000073 ecall - 80002eac: c0001073 unimp - -Disassembly of section .data: - -0000000080004000 : - 80004000: 00ff 0xff - 80004002: 00ff 0xff - 80004004: 00ff 0xff - 80004006: 00ff 0xff - -0000000080004008 : - 80004008: ff00 sd s0,56(a4) - 8000400a: ff00 sd s0,56(a4) - 8000400c: ff00 sd s0,56(a4) - 8000400e: ff00 sd s0,56(a4) - -0000000080004010 : - 80004010: 0ff0 addi a2,sp,988 - 80004012: 0ff0 addi a2,sp,988 - 80004014: 0ff0 addi a2,sp,988 - 80004016: 0ff0 addi a2,sp,988 - -0000000080004018 : - 80004018: f00ff00f 0xf00ff00f - 8000401c: f00ff00f 0xf00ff00f diff --git a/test/riscv/tests/rv64ui-v-ld.elf b/test/riscv/tests/rv64ui-v-ld.elf deleted file mode 100644 index 29406988..00000000 Binary files a/test/riscv/tests/rv64ui-v-ld.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-lh.dump b/test/riscv/tests/rv64ui-v-lh.dump deleted file mode 100644 index 50f2fddc..00000000 --- a/test/riscv/tests/rv64ui-v-lh.dump +++ /dev/null @@ -1,1043 +0,0 @@ - -rv64ui-v-lh: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 8f868693 addi a3,a3,-1800 # 80002d50 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 92c60613 addi a2,a2,-1748 # 80002de0 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 8f460613 addi a2,a2,-1804 # 80002df8 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 84468693 addi a3,a3,-1980 # 80002d98 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 86068693 addi a3,a3,-1952 # 80002ed0 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 7e060613 addi a2,a2,2016 # 80002ea8 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 71468693 addi a3,a3,1812 # 80002f00 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 63468693 addi a3,a3,1588 # 80002e70 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 5c468693 addi a3,a3,1476 # 80002e38 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 00700793 li a5,7 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 039687b7 lui a5,0x3968 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: c8378793 addi a5,a5,-893 # 3967c83 <_start-0x7c69837d> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000097 auipc ra,0x0 - 80002acc: 53808093 addi ra,ra,1336 # 80003000 - 80002ad0: 00009f03 lh t5,0(ra) - 80002ad4: 0ff00e93 li t4,255 - 80002ad8: 00200193 li gp,2 - 80002adc: 25df1c63 bne t5,t4,80002d34 - -0000000080002ae0 : - 80002ae0: 00000097 auipc ra,0x0 - 80002ae4: 52008093 addi ra,ra,1312 # 80003000 - 80002ae8: 00209f03 lh t5,2(ra) - 80002aec: f0000e93 li t4,-256 - 80002af0: 00300193 li gp,3 - 80002af4: 25df1063 bne t5,t4,80002d34 - -0000000080002af8 : - 80002af8: 00000097 auipc ra,0x0 - 80002afc: 50808093 addi ra,ra,1288 # 80003000 - 80002b00: 00409f03 lh t5,4(ra) - 80002b04: 00001eb7 lui t4,0x1 - 80002b08: ff0e8e9b addiw t4,t4,-16 - 80002b0c: 00400193 li gp,4 - 80002b10: 23df1263 bne t5,t4,80002d34 - -0000000080002b14 : - 80002b14: 00000097 auipc ra,0x0 - 80002b18: 4ec08093 addi ra,ra,1260 # 80003000 - 80002b1c: 00609f03 lh t5,6(ra) - 80002b20: fffffeb7 lui t4,0xfffff - 80002b24: 00fe8e9b addiw t4,t4,15 - 80002b28: 00500193 li gp,5 - 80002b2c: 21df1463 bne t5,t4,80002d34 - -0000000080002b30 : - 80002b30: 00000097 auipc ra,0x0 - 80002b34: 4d608093 addi ra,ra,1238 # 80003006 - 80002b38: ffa09f03 lh t5,-6(ra) - 80002b3c: 0ff00e93 li t4,255 - 80002b40: 00600193 li gp,6 - 80002b44: 1fdf1863 bne t5,t4,80002d34 - -0000000080002b48 : - 80002b48: 00000097 auipc ra,0x0 - 80002b4c: 4be08093 addi ra,ra,1214 # 80003006 - 80002b50: ffc09f03 lh t5,-4(ra) - 80002b54: f0000e93 li t4,-256 - 80002b58: 00700193 li gp,7 - 80002b5c: 1ddf1c63 bne t5,t4,80002d34 - -0000000080002b60 : - 80002b60: 00000097 auipc ra,0x0 - 80002b64: 4a608093 addi ra,ra,1190 # 80003006 - 80002b68: ffe09f03 lh t5,-2(ra) - 80002b6c: 00001eb7 lui t4,0x1 - 80002b70: ff0e8e9b addiw t4,t4,-16 - 80002b74: 00800193 li gp,8 - 80002b78: 1bdf1e63 bne t5,t4,80002d34 - -0000000080002b7c : - 80002b7c: 00000097 auipc ra,0x0 - 80002b80: 48a08093 addi ra,ra,1162 # 80003006 - 80002b84: 00009f03 lh t5,0(ra) - 80002b88: fffffeb7 lui t4,0xfffff - 80002b8c: 00fe8e9b addiw t4,t4,15 - 80002b90: 00900193 li gp,9 - 80002b94: 1bdf1063 bne t5,t4,80002d34 - -0000000080002b98 : - 80002b98: 00000097 auipc ra,0x0 - 80002b9c: 46808093 addi ra,ra,1128 # 80003000 - 80002ba0: fe008093 addi ra,ra,-32 - 80002ba4: 02009283 lh t0,32(ra) - 80002ba8: 0ff00e93 li t4,255 - 80002bac: 00a00193 li gp,10 - 80002bb0: 19d29263 bne t0,t4,80002d34 - -0000000080002bb4 : - 80002bb4: 00000097 auipc ra,0x0 - 80002bb8: 44c08093 addi ra,ra,1100 # 80003000 - 80002bbc: ffb08093 addi ra,ra,-5 - 80002bc0: 00709283 lh t0,7(ra) - 80002bc4: f0000e93 li t4,-256 - 80002bc8: 00b00193 li gp,11 - 80002bcc: 17d29463 bne t0,t4,80002d34 - -0000000080002bd0 : - 80002bd0: 00c00193 li gp,12 - 80002bd4: 00000213 li tp,0 - 80002bd8: 00000097 auipc ra,0x0 - 80002bdc: 42a08093 addi ra,ra,1066 # 80003002 - 80002be0: 00209f03 lh t5,2(ra) - 80002be4: 000f0313 mv t1,t5 - 80002be8: 00001eb7 lui t4,0x1 - 80002bec: ff0e8e9b addiw t4,t4,-16 - 80002bf0: 15d31263 bne t1,t4,80002d34 - 80002bf4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002bf8: 00200293 li t0,2 - 80002bfc: fc521ee3 bne tp,t0,80002bd8 - -0000000080002c00 : - 80002c00: 00d00193 li gp,13 - 80002c04: 00000213 li tp,0 - 80002c08: 00000097 auipc ra,0x0 - 80002c0c: 3fc08093 addi ra,ra,1020 # 80003004 - 80002c10: 00209f03 lh t5,2(ra) - 80002c14: 00000013 nop - 80002c18: 000f0313 mv t1,t5 - 80002c1c: fffffeb7 lui t4,0xfffff - 80002c20: 00fe8e9b addiw t4,t4,15 - 80002c24: 11d31863 bne t1,t4,80002d34 - 80002c28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c2c: 00200293 li t0,2 - 80002c30: fc521ce3 bne tp,t0,80002c08 - -0000000080002c34 : - 80002c34: 00e00193 li gp,14 - 80002c38: 00000213 li tp,0 - 80002c3c: 00000097 auipc ra,0x0 - 80002c40: 3c408093 addi ra,ra,964 # 80003000 - 80002c44: 00209f03 lh t5,2(ra) - 80002c48: 00000013 nop - 80002c4c: 00000013 nop - 80002c50: 000f0313 mv t1,t5 - 80002c54: f0000e93 li t4,-256 - 80002c58: 0dd31e63 bne t1,t4,80002d34 - 80002c5c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c60: 00200293 li t0,2 - 80002c64: fc521ce3 bne tp,t0,80002c3c - -0000000080002c68 : - 80002c68: 00f00193 li gp,15 - 80002c6c: 00000213 li tp,0 - 80002c70: 00000097 auipc ra,0x0 - 80002c74: 39208093 addi ra,ra,914 # 80003002 - 80002c78: 00209f03 lh t5,2(ra) - 80002c7c: 00001eb7 lui t4,0x1 - 80002c80: ff0e8e9b addiw t4,t4,-16 - 80002c84: 0bdf1863 bne t5,t4,80002d34 - 80002c88: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c8c: 00200293 li t0,2 - 80002c90: fe5210e3 bne tp,t0,80002c70 - -0000000080002c94 : - 80002c94: 01000193 li gp,16 - 80002c98: 00000213 li tp,0 - 80002c9c: 00000097 auipc ra,0x0 - 80002ca0: 36808093 addi ra,ra,872 # 80003004 - 80002ca4: 00000013 nop - 80002ca8: 00209f03 lh t5,2(ra) - 80002cac: fffffeb7 lui t4,0xfffff - 80002cb0: 00fe8e9b addiw t4,t4,15 - 80002cb4: 09df1063 bne t5,t4,80002d34 - 80002cb8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cbc: 00200293 li t0,2 - 80002cc0: fc521ee3 bne tp,t0,80002c9c - -0000000080002cc4 : - 80002cc4: 01100193 li gp,17 - 80002cc8: 00000213 li tp,0 - 80002ccc: 00000097 auipc ra,0x0 - 80002cd0: 33408093 addi ra,ra,820 # 80003000 - 80002cd4: 00000013 nop - 80002cd8: 00000013 nop - 80002cdc: 00209f03 lh t5,2(ra) - 80002ce0: f0000e93 li t4,-256 - 80002ce4: 05df1863 bne t5,t4,80002d34 - 80002ce8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cec: 00200293 li t0,2 - 80002cf0: fc521ee3 bne tp,t0,80002ccc - -0000000080002cf4 : - 80002cf4: 00000297 auipc t0,0x0 - 80002cf8: 30c28293 addi t0,t0,780 # 80003000 - 80002cfc: 00029103 lh sp,0(t0) - 80002d00: 00200113 li sp,2 - 80002d04: 00200e93 li t4,2 - 80002d08: 01200193 li gp,18 - 80002d0c: 03d11463 bne sp,t4,80002d34 - -0000000080002d10 : - 80002d10: 00000297 auipc t0,0x0 - 80002d14: 2f028293 addi t0,t0,752 # 80003000 - 80002d18: 00029103 lh sp,0(t0) - 80002d1c: 00000013 nop - 80002d20: 00200113 li sp,2 - 80002d24: 00200e93 li t4,2 - 80002d28: 01300193 li gp,19 - 80002d2c: 01d11463 bne sp,t4,80002d34 - 80002d30: 00301a63 bne zero,gp,80002d44 - -0000000080002d34 : - 80002d34: 00119513 slli a0,gp,0x1 - 80002d38: 00050063 beqz a0,80002d38 - 80002d3c: 00156513 ori a0,a0,1 - 80002d40: 00000073 ecall - -0000000080002d44 : - 80002d44: 00100513 li a0,1 - 80002d48: 00000073 ecall - 80002d4c: c0001073 unimp - -Disassembly of section .data: - -0000000080003000 : - 80003000: 00ff 0xff - -0000000080003002 : - 80003002: ff00 sd s0,56(a4) - -0000000080003004 : - 80003004: 0ff0 addi a2,sp,988 - -0000000080003006 : - 80003006: 0xf00f diff --git a/test/riscv/tests/rv64ui-v-lh.elf b/test/riscv/tests/rv64ui-v-lh.elf deleted file mode 100644 index 7d91368b..00000000 Binary files a/test/riscv/tests/rv64ui-v-lh.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-lhu.dump b/test/riscv/tests/rv64ui-v-lhu.dump deleted file mode 100644 index 45585fe4..00000000 --- a/test/riscv/tests/rv64ui-v-lhu.dump +++ /dev/null @@ -1,1048 +0,0 @@ - -rv64ui-v-lhu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 91068693 addi a3,a3,-1776 # 80002d68 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 94460613 addi a2,a2,-1724 # 80002df8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 90c60613 addi a2,a2,-1780 # 80002e10 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 85c68693 addi a3,a3,-1956 # 80002db0 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 87868693 addi a3,a3,-1928 # 80002ee8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 7f860613 addi a2,a2,2040 # 80002ec0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 72c68693 addi a3,a3,1836 # 80002f18 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 64c68693 addi a3,a3,1612 # 80002e88 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 5dc68693 addi a3,a3,1500 # 80002e50 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 03b00793 li a5,59 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 007667b7 lui a5,0x766 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: efb78793 addi a5,a5,-261 # 765efb <_start-0x7f89a105> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000097 auipc ra,0x0 - 80002acc: 53808093 addi ra,ra,1336 # 80003000 - 80002ad0: 0000df03 lhu t5,0(ra) - 80002ad4: 0ff00e93 li t4,255 - 80002ad8: 00200193 li gp,2 - 80002adc: 27df1663 bne t5,t4,80002d48 - -0000000080002ae0 : - 80002ae0: 00000097 auipc ra,0x0 - 80002ae4: 52008093 addi ra,ra,1312 # 80003000 - 80002ae8: 0020df03 lhu t5,2(ra) - 80002aec: 00010eb7 lui t4,0x10 - 80002af0: f00e8e9b addiw t4,t4,-256 - 80002af4: 00300193 li gp,3 - 80002af8: 25df1863 bne t5,t4,80002d48 - -0000000080002afc : - 80002afc: 00000097 auipc ra,0x0 - 80002b00: 50408093 addi ra,ra,1284 # 80003000 - 80002b04: 0040df03 lhu t5,4(ra) - 80002b08: 00001eb7 lui t4,0x1 - 80002b0c: ff0e8e9b addiw t4,t4,-16 - 80002b10: 00400193 li gp,4 - 80002b14: 23df1a63 bne t5,t4,80002d48 - -0000000080002b18 : - 80002b18: 00000097 auipc ra,0x0 - 80002b1c: 4e808093 addi ra,ra,1256 # 80003000 - 80002b20: 0060df03 lhu t5,6(ra) - 80002b24: 0000feb7 lui t4,0xf - 80002b28: 00fe8e9b addiw t4,t4,15 - 80002b2c: 00500193 li gp,5 - 80002b30: 21df1c63 bne t5,t4,80002d48 - -0000000080002b34 : - 80002b34: 00000097 auipc ra,0x0 - 80002b38: 4d208093 addi ra,ra,1234 # 80003006 - 80002b3c: ffa0df03 lhu t5,-6(ra) - 80002b40: 0ff00e93 li t4,255 - 80002b44: 00600193 li gp,6 - 80002b48: 21df1063 bne t5,t4,80002d48 - -0000000080002b4c : - 80002b4c: 00000097 auipc ra,0x0 - 80002b50: 4ba08093 addi ra,ra,1210 # 80003006 - 80002b54: ffc0df03 lhu t5,-4(ra) - 80002b58: 00010eb7 lui t4,0x10 - 80002b5c: f00e8e9b addiw t4,t4,-256 - 80002b60: 00700193 li gp,7 - 80002b64: 1fdf1263 bne t5,t4,80002d48 - -0000000080002b68 : - 80002b68: 00000097 auipc ra,0x0 - 80002b6c: 49e08093 addi ra,ra,1182 # 80003006 - 80002b70: ffe0df03 lhu t5,-2(ra) - 80002b74: 00001eb7 lui t4,0x1 - 80002b78: ff0e8e9b addiw t4,t4,-16 - 80002b7c: 00800193 li gp,8 - 80002b80: 1ddf1463 bne t5,t4,80002d48 - -0000000080002b84 : - 80002b84: 00000097 auipc ra,0x0 - 80002b88: 48208093 addi ra,ra,1154 # 80003006 - 80002b8c: 0000df03 lhu t5,0(ra) - 80002b90: 0000feb7 lui t4,0xf - 80002b94: 00fe8e9b addiw t4,t4,15 - 80002b98: 00900193 li gp,9 - 80002b9c: 1bdf1663 bne t5,t4,80002d48 - -0000000080002ba0 : - 80002ba0: 00000097 auipc ra,0x0 - 80002ba4: 46008093 addi ra,ra,1120 # 80003000 - 80002ba8: fe008093 addi ra,ra,-32 - 80002bac: 0200d283 lhu t0,32(ra) - 80002bb0: 0ff00e93 li t4,255 - 80002bb4: 00a00193 li gp,10 - 80002bb8: 19d29863 bne t0,t4,80002d48 - -0000000080002bbc : - 80002bbc: 00000097 auipc ra,0x0 - 80002bc0: 44408093 addi ra,ra,1092 # 80003000 - 80002bc4: ffb08093 addi ra,ra,-5 - 80002bc8: 0070d283 lhu t0,7(ra) - 80002bcc: 00010eb7 lui t4,0x10 - 80002bd0: f00e8e9b addiw t4,t4,-256 - 80002bd4: 00b00193 li gp,11 - 80002bd8: 17d29863 bne t0,t4,80002d48 - -0000000080002bdc : - 80002bdc: 00c00193 li gp,12 - 80002be0: 00000213 li tp,0 - 80002be4: 00000097 auipc ra,0x0 - 80002be8: 41e08093 addi ra,ra,1054 # 80003002 - 80002bec: 0020df03 lhu t5,2(ra) - 80002bf0: 000f0313 mv t1,t5 - 80002bf4: 00001eb7 lui t4,0x1 - 80002bf8: ff0e8e9b addiw t4,t4,-16 - 80002bfc: 15d31663 bne t1,t4,80002d48 - 80002c00: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c04: 00200293 li t0,2 - 80002c08: fc521ee3 bne tp,t0,80002be4 - -0000000080002c0c : - 80002c0c: 00d00193 li gp,13 - 80002c10: 00000213 li tp,0 - 80002c14: 00000097 auipc ra,0x0 - 80002c18: 3f008093 addi ra,ra,1008 # 80003004 - 80002c1c: 0020df03 lhu t5,2(ra) - 80002c20: 00000013 nop - 80002c24: 000f0313 mv t1,t5 - 80002c28: 0000feb7 lui t4,0xf - 80002c2c: 00fe8e9b addiw t4,t4,15 - 80002c30: 11d31c63 bne t1,t4,80002d48 - 80002c34: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c38: 00200293 li t0,2 - 80002c3c: fc521ce3 bne tp,t0,80002c14 - -0000000080002c40 : - 80002c40: 00e00193 li gp,14 - 80002c44: 00000213 li tp,0 - 80002c48: 00000097 auipc ra,0x0 - 80002c4c: 3b808093 addi ra,ra,952 # 80003000 - 80002c50: 0020df03 lhu t5,2(ra) - 80002c54: 00000013 nop - 80002c58: 00000013 nop - 80002c5c: 000f0313 mv t1,t5 - 80002c60: 00010eb7 lui t4,0x10 - 80002c64: f00e8e9b addiw t4,t4,-256 - 80002c68: 0fd31063 bne t1,t4,80002d48 - 80002c6c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c70: 00200293 li t0,2 - 80002c74: fc521ae3 bne tp,t0,80002c48 - -0000000080002c78 : - 80002c78: 00f00193 li gp,15 - 80002c7c: 00000213 li tp,0 - 80002c80: 00000097 auipc ra,0x0 - 80002c84: 38208093 addi ra,ra,898 # 80003002 - 80002c88: 0020df03 lhu t5,2(ra) - 80002c8c: 00001eb7 lui t4,0x1 - 80002c90: ff0e8e9b addiw t4,t4,-16 - 80002c94: 0bdf1a63 bne t5,t4,80002d48 - 80002c98: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c9c: 00200293 li t0,2 - 80002ca0: fe5210e3 bne tp,t0,80002c80 - -0000000080002ca4 : - 80002ca4: 01000193 li gp,16 - 80002ca8: 00000213 li tp,0 - 80002cac: 00000097 auipc ra,0x0 - 80002cb0: 35808093 addi ra,ra,856 # 80003004 - 80002cb4: 00000013 nop - 80002cb8: 0020df03 lhu t5,2(ra) - 80002cbc: 0000feb7 lui t4,0xf - 80002cc0: 00fe8e9b addiw t4,t4,15 - 80002cc4: 09df1263 bne t5,t4,80002d48 - 80002cc8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ccc: 00200293 li t0,2 - 80002cd0: fc521ee3 bne tp,t0,80002cac - -0000000080002cd4 : - 80002cd4: 01100193 li gp,17 - 80002cd8: 00000213 li tp,0 - 80002cdc: 00000097 auipc ra,0x0 - 80002ce0: 32408093 addi ra,ra,804 # 80003000 - 80002ce4: 00000013 nop - 80002ce8: 00000013 nop - 80002cec: 0020df03 lhu t5,2(ra) - 80002cf0: 00010eb7 lui t4,0x10 - 80002cf4: f00e8e9b addiw t4,t4,-256 - 80002cf8: 05df1863 bne t5,t4,80002d48 - 80002cfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d00: 00200293 li t0,2 - 80002d04: fc521ce3 bne tp,t0,80002cdc - -0000000080002d08 : - 80002d08: 00000297 auipc t0,0x0 - 80002d0c: 2f828293 addi t0,t0,760 # 80003000 - 80002d10: 0002d103 lhu sp,0(t0) - 80002d14: 00200113 li sp,2 - 80002d18: 00200e93 li t4,2 - 80002d1c: 01200193 li gp,18 - 80002d20: 03d11463 bne sp,t4,80002d48 - -0000000080002d24 : - 80002d24: 00000297 auipc t0,0x0 - 80002d28: 2dc28293 addi t0,t0,732 # 80003000 - 80002d2c: 0002d103 lhu sp,0(t0) - 80002d30: 00000013 nop - 80002d34: 00200113 li sp,2 - 80002d38: 00200e93 li t4,2 - 80002d3c: 01300193 li gp,19 - 80002d40: 01d11463 bne sp,t4,80002d48 - 80002d44: 00301a63 bne zero,gp,80002d58 - -0000000080002d48 : - 80002d48: 00119513 slli a0,gp,0x1 - 80002d4c: 00050063 beqz a0,80002d4c - 80002d50: 00156513 ori a0,a0,1 - 80002d54: 00000073 ecall - -0000000080002d58 : - 80002d58: 00100513 li a0,1 - 80002d5c: 00000073 ecall - 80002d60: c0001073 unimp - -Disassembly of section .data: - -0000000080003000 : - 80003000: 00ff 0xff - -0000000080003002 : - 80003002: ff00 sd s0,56(a4) - -0000000080003004 : - 80003004: 0ff0 addi a2,sp,988 - -0000000080003006 : - 80003006: 0xf00f diff --git a/test/riscv/tests/rv64ui-v-lhu.elf b/test/riscv/tests/rv64ui-v-lhu.elf deleted file mode 100644 index af1ebeec..00000000 Binary files a/test/riscv/tests/rv64ui-v-lhu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-lui.dump b/test/riscv/tests/rv64ui-v-lui.dump deleted file mode 100644 index 6de22b61..00000000 --- a/test/riscv/tests/rv64ui-v-lui.dump +++ /dev/null @@ -1,872 +0,0 @@ - -rv64ui-v-lui: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 6f068693 addi a3,a3,1776 # 80002b48 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 72460613 addi a2,a2,1828 # 80002bd8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 6ec60613 addi a2,a2,1772 # 80002bf0 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 63c68693 addi a3,a3,1596 # 80002b90 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 65868693 addi a3,a3,1624 # 80002cc8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 5d860613 addi a2,a2,1496 # 80002ca0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 50c68693 addi a3,a3,1292 # 80002cf8 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 42c68693 addi a3,a3,1068 # 80002c68 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 3bc68693 addi a3,a3,956 # 80002c30 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 00e00793 li a5,14 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0caa87b7 lui a5,0xcaa8 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 51978793 addi a5,a5,1305 # caa8519 <_start-0x73557ae7> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 000000b7 lui ra,0x0 - 80002acc: 00000e93 li t4,0 - 80002ad0: 00200193 li gp,2 - 80002ad4: 05d09a63 bne ra,t4,80002b28 - -0000000080002ad8 : - 80002ad8: fffff0b7 lui ra,0xfffff - 80002adc: 4010d093 srai ra,ra,0x1 - 80002ae0: 80000e93 li t4,-2048 - 80002ae4: 00300193 li gp,3 - 80002ae8: 05d09063 bne ra,t4,80002b28 - -0000000080002aec : - 80002aec: 7ffff0b7 lui ra,0x7ffff - 80002af0: 4140d093 srai ra,ra,0x14 - 80002af4: 7ff00e93 li t4,2047 - 80002af8: 00400193 li gp,4 - 80002afc: 03d09663 bne ra,t4,80002b28 - -0000000080002b00 : - 80002b00: 800000b7 lui ra,0x80000 - 80002b04: 4140d093 srai ra,ra,0x14 - 80002b08: 80000e93 li t4,-2048 - 80002b0c: 00500193 li gp,5 - 80002b10: 01d09c63 bne ra,t4,80002b28 - -0000000080002b14 : - 80002b14: 80000037 lui zero,0x80000 - 80002b18: 00000e93 li t4,0 - 80002b1c: 00600193 li gp,6 - 80002b20: 01d01463 bne zero,t4,80002b28 - 80002b24: 00301a63 bne zero,gp,80002b38 - -0000000080002b28 : - 80002b28: 00119513 slli a0,gp,0x1 - 80002b2c: 00050063 beqz a0,80002b2c - 80002b30: 00156513 ori a0,a0,1 - 80002b34: 00000073 ecall - -0000000080002b38 : - 80002b38: 00100513 li a0,1 - 80002b3c: 00000073 ecall - 80002b40: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-lui.elf b/test/riscv/tests/rv64ui-v-lui.elf deleted file mode 100644 index 3cab9504..00000000 Binary files a/test/riscv/tests/rv64ui-v-lui.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-lw.dump b/test/riscv/tests/rv64ui-v-lw.dump deleted file mode 100644 index 4208d276..00000000 --- a/test/riscv/tests/rv64ui-v-lw.dump +++ /dev/null @@ -1,1054 +0,0 @@ - -rv64ui-v-lw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 91868693 addi a3,a3,-1768 # 80002d70 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 94c60613 addi a2,a2,-1716 # 80002e00 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 91460613 addi a2,a2,-1772 # 80002e18 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 86468693 addi a3,a3,-1948 # 80002db8 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 88068693 addi a3,a3,-1920 # 80002ef0 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 80060613 addi a2,a2,-2048 # 80002ec8 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 73468693 addi a3,a3,1844 # 80002f20 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 65468693 addi a3,a3,1620 # 80002e90 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 5e468693 addi a3,a3,1508 # 80002e58 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 00800793 li a5,8 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 03dd47b7 lui a5,0x3dd4 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: ebd78793 addi a5,a5,-323 # 3dd3ebd <_start-0x7c22c143> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000097 auipc ra,0x0 - 80002acc: 53808093 addi ra,ra,1336 # 80003000 - 80002ad0: 0000af03 lw t5,0(ra) - 80002ad4: 00ff0eb7 lui t4,0xff0 - 80002ad8: 0ffe8e9b addiw t4,t4,255 - 80002adc: 00200193 li gp,2 - 80002ae0: 27df1a63 bne t5,t4,80002d54 - -0000000080002ae4 : - 80002ae4: 00000097 auipc ra,0x0 - 80002ae8: 51c08093 addi ra,ra,1308 # 80003000 - 80002aec: 0040af03 lw t5,4(ra) - 80002af0: ff010eb7 lui t4,0xff010 - 80002af4: f00e8e9b addiw t4,t4,-256 - 80002af8: 00300193 li gp,3 - 80002afc: 25df1c63 bne t5,t4,80002d54 - -0000000080002b00 : - 80002b00: 00000097 auipc ra,0x0 - 80002b04: 50008093 addi ra,ra,1280 # 80003000 - 80002b08: 0080af03 lw t5,8(ra) - 80002b0c: 0ff01eb7 lui t4,0xff01 - 80002b10: ff0e8e9b addiw t4,t4,-16 - 80002b14: 00400193 li gp,4 - 80002b18: 23df1e63 bne t5,t4,80002d54 - -0000000080002b1c : - 80002b1c: 00000097 auipc ra,0x0 - 80002b20: 4e408093 addi ra,ra,1252 # 80003000 - 80002b24: 00c0af03 lw t5,12(ra) - 80002b28: f00ffeb7 lui t4,0xf00ff - 80002b2c: 00fe8e9b addiw t4,t4,15 - 80002b30: 00500193 li gp,5 - 80002b34: 23df1063 bne t5,t4,80002d54 - -0000000080002b38 : - 80002b38: 00000097 auipc ra,0x0 - 80002b3c: 4d408093 addi ra,ra,1236 # 8000300c - 80002b40: ff40af03 lw t5,-12(ra) - 80002b44: 00ff0eb7 lui t4,0xff0 - 80002b48: 0ffe8e9b addiw t4,t4,255 - 80002b4c: 00600193 li gp,6 - 80002b50: 21df1263 bne t5,t4,80002d54 - -0000000080002b54 : - 80002b54: 00000097 auipc ra,0x0 - 80002b58: 4b808093 addi ra,ra,1208 # 8000300c - 80002b5c: ff80af03 lw t5,-8(ra) - 80002b60: ff010eb7 lui t4,0xff010 - 80002b64: f00e8e9b addiw t4,t4,-256 - 80002b68: 00700193 li gp,7 - 80002b6c: 1fdf1463 bne t5,t4,80002d54 - -0000000080002b70 : - 80002b70: 00000097 auipc ra,0x0 - 80002b74: 49c08093 addi ra,ra,1180 # 8000300c - 80002b78: ffc0af03 lw t5,-4(ra) - 80002b7c: 0ff01eb7 lui t4,0xff01 - 80002b80: ff0e8e9b addiw t4,t4,-16 - 80002b84: 00800193 li gp,8 - 80002b88: 1ddf1663 bne t5,t4,80002d54 - -0000000080002b8c : - 80002b8c: 00000097 auipc ra,0x0 - 80002b90: 48008093 addi ra,ra,1152 # 8000300c - 80002b94: 0000af03 lw t5,0(ra) - 80002b98: f00ffeb7 lui t4,0xf00ff - 80002b9c: 00fe8e9b addiw t4,t4,15 - 80002ba0: 00900193 li gp,9 - 80002ba4: 1bdf1863 bne t5,t4,80002d54 - -0000000080002ba8 : - 80002ba8: 00000097 auipc ra,0x0 - 80002bac: 45808093 addi ra,ra,1112 # 80003000 - 80002bb0: fe008093 addi ra,ra,-32 - 80002bb4: 0200a283 lw t0,32(ra) - 80002bb8: 00ff0eb7 lui t4,0xff0 - 80002bbc: 0ffe8e9b addiw t4,t4,255 - 80002bc0: 00a00193 li gp,10 - 80002bc4: 19d29863 bne t0,t4,80002d54 - -0000000080002bc8 : - 80002bc8: 00000097 auipc ra,0x0 - 80002bcc: 43808093 addi ra,ra,1080 # 80003000 - 80002bd0: ffd08093 addi ra,ra,-3 - 80002bd4: 0070a283 lw t0,7(ra) - 80002bd8: ff010eb7 lui t4,0xff010 - 80002bdc: f00e8e9b addiw t4,t4,-256 - 80002be0: 00b00193 li gp,11 - 80002be4: 17d29863 bne t0,t4,80002d54 - -0000000080002be8 : - 80002be8: 00c00193 li gp,12 - 80002bec: 00000213 li tp,0 - 80002bf0: 00000097 auipc ra,0x0 - 80002bf4: 41408093 addi ra,ra,1044 # 80003004 - 80002bf8: 0040af03 lw t5,4(ra) - 80002bfc: 000f0313 mv t1,t5 - 80002c00: 0ff01eb7 lui t4,0xff01 - 80002c04: ff0e8e9b addiw t4,t4,-16 - 80002c08: 15d31663 bne t1,t4,80002d54 - 80002c0c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c10: 00200293 li t0,2 - 80002c14: fc521ee3 bne tp,t0,80002bf0 - -0000000080002c18 : - 80002c18: 00d00193 li gp,13 - 80002c1c: 00000213 li tp,0 - 80002c20: 00000097 auipc ra,0x0 - 80002c24: 3e808093 addi ra,ra,1000 # 80003008 - 80002c28: 0040af03 lw t5,4(ra) - 80002c2c: 00000013 nop - 80002c30: 000f0313 mv t1,t5 - 80002c34: f00ffeb7 lui t4,0xf00ff - 80002c38: 00fe8e9b addiw t4,t4,15 - 80002c3c: 11d31c63 bne t1,t4,80002d54 - 80002c40: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c44: 00200293 li t0,2 - 80002c48: fc521ce3 bne tp,t0,80002c20 - -0000000080002c4c : - 80002c4c: 00e00193 li gp,14 - 80002c50: 00000213 li tp,0 - 80002c54: 00000097 auipc ra,0x0 - 80002c58: 3ac08093 addi ra,ra,940 # 80003000 - 80002c5c: 0040af03 lw t5,4(ra) - 80002c60: 00000013 nop - 80002c64: 00000013 nop - 80002c68: 000f0313 mv t1,t5 - 80002c6c: ff010eb7 lui t4,0xff010 - 80002c70: f00e8e9b addiw t4,t4,-256 - 80002c74: 0fd31063 bne t1,t4,80002d54 - 80002c78: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c7c: 00200293 li t0,2 - 80002c80: fc521ae3 bne tp,t0,80002c54 - -0000000080002c84 : - 80002c84: 00f00193 li gp,15 - 80002c88: 00000213 li tp,0 - 80002c8c: 00000097 auipc ra,0x0 - 80002c90: 37808093 addi ra,ra,888 # 80003004 - 80002c94: 0040af03 lw t5,4(ra) - 80002c98: 0ff01eb7 lui t4,0xff01 - 80002c9c: ff0e8e9b addiw t4,t4,-16 - 80002ca0: 0bdf1a63 bne t5,t4,80002d54 - 80002ca4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ca8: 00200293 li t0,2 - 80002cac: fe5210e3 bne tp,t0,80002c8c - -0000000080002cb0 : - 80002cb0: 01000193 li gp,16 - 80002cb4: 00000213 li tp,0 - 80002cb8: 00000097 auipc ra,0x0 - 80002cbc: 35008093 addi ra,ra,848 # 80003008 - 80002cc0: 00000013 nop - 80002cc4: 0040af03 lw t5,4(ra) - 80002cc8: f00ffeb7 lui t4,0xf00ff - 80002ccc: 00fe8e9b addiw t4,t4,15 - 80002cd0: 09df1263 bne t5,t4,80002d54 - 80002cd4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cd8: 00200293 li t0,2 - 80002cdc: fc521ee3 bne tp,t0,80002cb8 - -0000000080002ce0 : - 80002ce0: 01100193 li gp,17 - 80002ce4: 00000213 li tp,0 - 80002ce8: 00000097 auipc ra,0x0 - 80002cec: 31808093 addi ra,ra,792 # 80003000 - 80002cf0: 00000013 nop - 80002cf4: 00000013 nop - 80002cf8: 0040af03 lw t5,4(ra) - 80002cfc: ff010eb7 lui t4,0xff010 - 80002d00: f00e8e9b addiw t4,t4,-256 - 80002d04: 05df1863 bne t5,t4,80002d54 - 80002d08: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d0c: 00200293 li t0,2 - 80002d10: fc521ce3 bne tp,t0,80002ce8 - -0000000080002d14 : - 80002d14: 00000297 auipc t0,0x0 - 80002d18: 2ec28293 addi t0,t0,748 # 80003000 - 80002d1c: 0002a103 lw sp,0(t0) - 80002d20: 00200113 li sp,2 - 80002d24: 00200e93 li t4,2 - 80002d28: 01200193 li gp,18 - 80002d2c: 03d11463 bne sp,t4,80002d54 - -0000000080002d30 : - 80002d30: 00000297 auipc t0,0x0 - 80002d34: 2d028293 addi t0,t0,720 # 80003000 - 80002d38: 0002a103 lw sp,0(t0) - 80002d3c: 00000013 nop - 80002d40: 00200113 li sp,2 - 80002d44: 00200e93 li t4,2 - 80002d48: 01300193 li gp,19 - 80002d4c: 01d11463 bne sp,t4,80002d54 - 80002d50: 00301a63 bne zero,gp,80002d64 - -0000000080002d54 : - 80002d54: 00119513 slli a0,gp,0x1 - 80002d58: 00050063 beqz a0,80002d58 - 80002d5c: 00156513 ori a0,a0,1 - 80002d60: 00000073 ecall - -0000000080002d64 : - 80002d64: 00100513 li a0,1 - 80002d68: 00000073 ecall - 80002d6c: c0001073 unimp - -Disassembly of section .data: - -0000000080003000 : - 80003000: 00ff 0xff - 80003002: 00ff 0xff - -0000000080003004 : - 80003004: ff00 sd s0,56(a4) - 80003006: ff00 sd s0,56(a4) - -0000000080003008 : - 80003008: 0ff0 addi a2,sp,988 - 8000300a: 0ff0 addi a2,sp,988 - -000000008000300c : - 8000300c: f00ff00f 0xf00ff00f diff --git a/test/riscv/tests/rv64ui-v-lw.elf b/test/riscv/tests/rv64ui-v-lw.elf deleted file mode 100644 index d73403be..00000000 Binary files a/test/riscv/tests/rv64ui-v-lw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-lwu.dump b/test/riscv/tests/rv64ui-v-lwu.dump deleted file mode 100644 index aa0fb7d0..00000000 --- a/test/riscv/tests/rv64ui-v-lwu.dump +++ /dev/null @@ -1,1072 +0,0 @@ - -rv64ui-v-lwu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 96068693 addi a3,a3,-1696 # 80002db8 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 99460613 addi a2,a2,-1644 # 80002e48 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 95c60613 addi a2,a2,-1700 # 80002e60 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 8ac68693 addi a3,a3,-1876 # 80002e00 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 8c868693 addi a3,a3,-1848 # 80002f38 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 84860613 addi a2,a2,-1976 # 80002f10 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 77c68693 addi a3,a3,1916 # 80002f68 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 69c68693 addi a3,a3,1692 # 80002ed8 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 62c68693 addi a3,a3,1580 # 80002ea0 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 00200793 li a5,2 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 046f07b7 lui a5,0x46f0 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: b8378793 addi a5,a5,-1149 # 46efb83 <_start-0x7b91047d> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000097 auipc ra,0x0 - 80002acc: 53808093 addi ra,ra,1336 # 80003000 - 80002ad0: 0000ef03 lwu t5,0(ra) - 80002ad4: 00ff0eb7 lui t4,0xff0 - 80002ad8: 0ffe8e9b addiw t4,t4,255 - 80002adc: 00200193 li gp,2 - 80002ae0: 2bdf1e63 bne t5,t4,80002d9c - -0000000080002ae4 : - 80002ae4: 00000097 auipc ra,0x0 - 80002ae8: 51c08093 addi ra,ra,1308 # 80003000 - 80002aec: 0040ef03 lwu t5,4(ra) - 80002af0: 00010eb7 lui t4,0x10 - 80002af4: f01e8e9b addiw t4,t4,-255 - 80002af8: 010e9e93 slli t4,t4,0x10 - 80002afc: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80002b00: 00300193 li gp,3 - 80002b04: 29df1c63 bne t5,t4,80002d9c - -0000000080002b08 : - 80002b08: 00000097 auipc ra,0x0 - 80002b0c: 4f808093 addi ra,ra,1272 # 80003000 - 80002b10: 0080ef03 lwu t5,8(ra) - 80002b14: 0ff01eb7 lui t4,0xff01 - 80002b18: ff0e8e9b addiw t4,t4,-16 - 80002b1c: 00400193 li gp,4 - 80002b20: 27df1e63 bne t5,t4,80002d9c - -0000000080002b24 : - 80002b24: 00000097 auipc ra,0x0 - 80002b28: 4dc08093 addi ra,ra,1244 # 80003000 - 80002b2c: 00c0ef03 lwu t5,12(ra) - 80002b30: 000f0eb7 lui t4,0xf0 - 80002b34: 0ffe8e9b addiw t4,t4,255 - 80002b38: 00ce9e93 slli t4,t4,0xc - 80002b3c: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 80002b40: 00500193 li gp,5 - 80002b44: 25df1c63 bne t5,t4,80002d9c - -0000000080002b48 : - 80002b48: 00000097 auipc ra,0x0 - 80002b4c: 4c408093 addi ra,ra,1220 # 8000300c - 80002b50: ff40ef03 lwu t5,-12(ra) - 80002b54: 00ff0eb7 lui t4,0xff0 - 80002b58: 0ffe8e9b addiw t4,t4,255 - 80002b5c: 00600193 li gp,6 - 80002b60: 23df1e63 bne t5,t4,80002d9c - -0000000080002b64 : - 80002b64: 00000097 auipc ra,0x0 - 80002b68: 4a808093 addi ra,ra,1192 # 8000300c - 80002b6c: ff80ef03 lwu t5,-8(ra) - 80002b70: 00010eb7 lui t4,0x10 - 80002b74: f01e8e9b addiw t4,t4,-255 - 80002b78: 010e9e93 slli t4,t4,0x10 - 80002b7c: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80002b80: 00700193 li gp,7 - 80002b84: 21df1c63 bne t5,t4,80002d9c - -0000000080002b88 : - 80002b88: 00000097 auipc ra,0x0 - 80002b8c: 48408093 addi ra,ra,1156 # 8000300c - 80002b90: ffc0ef03 lwu t5,-4(ra) - 80002b94: 0ff01eb7 lui t4,0xff01 - 80002b98: ff0e8e9b addiw t4,t4,-16 - 80002b9c: 00800193 li gp,8 - 80002ba0: 1fdf1e63 bne t5,t4,80002d9c - -0000000080002ba4 : - 80002ba4: 00000097 auipc ra,0x0 - 80002ba8: 46808093 addi ra,ra,1128 # 8000300c - 80002bac: 0000ef03 lwu t5,0(ra) - 80002bb0: 000f0eb7 lui t4,0xf0 - 80002bb4: 0ffe8e9b addiw t4,t4,255 - 80002bb8: 00ce9e93 slli t4,t4,0xc - 80002bbc: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 80002bc0: 00900193 li gp,9 - 80002bc4: 1ddf1c63 bne t5,t4,80002d9c - -0000000080002bc8 : - 80002bc8: 00000097 auipc ra,0x0 - 80002bcc: 43808093 addi ra,ra,1080 # 80003000 - 80002bd0: fe008093 addi ra,ra,-32 - 80002bd4: 0200e283 lwu t0,32(ra) - 80002bd8: 00ff0eb7 lui t4,0xff0 - 80002bdc: 0ffe8e9b addiw t4,t4,255 - 80002be0: 00a00193 li gp,10 - 80002be4: 1bd29c63 bne t0,t4,80002d9c - -0000000080002be8 : - 80002be8: 00000097 auipc ra,0x0 - 80002bec: 41808093 addi ra,ra,1048 # 80003000 - 80002bf0: ffd08093 addi ra,ra,-3 - 80002bf4: 0070e283 lwu t0,7(ra) - 80002bf8: 00010eb7 lui t4,0x10 - 80002bfc: f01e8e9b addiw t4,t4,-255 - 80002c00: 010e9e93 slli t4,t4,0x10 - 80002c04: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80002c08: 00b00193 li gp,11 - 80002c0c: 19d29863 bne t0,t4,80002d9c - -0000000080002c10 : - 80002c10: 00c00193 li gp,12 - 80002c14: 00000213 li tp,0 - 80002c18: 00000097 auipc ra,0x0 - 80002c1c: 3ec08093 addi ra,ra,1004 # 80003004 - 80002c20: 0040ef03 lwu t5,4(ra) - 80002c24: 000f0313 mv t1,t5 - 80002c28: 0ff01eb7 lui t4,0xff01 - 80002c2c: ff0e8e9b addiw t4,t4,-16 - 80002c30: 17d31663 bne t1,t4,80002d9c - 80002c34: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c38: 00200293 li t0,2 - 80002c3c: fc521ee3 bne tp,t0,80002c18 - -0000000080002c40 : - 80002c40: 00d00193 li gp,13 - 80002c44: 00000213 li tp,0 - 80002c48: 00000097 auipc ra,0x0 - 80002c4c: 3c008093 addi ra,ra,960 # 80003008 - 80002c50: 0040ef03 lwu t5,4(ra) - 80002c54: 00000013 nop - 80002c58: 000f0313 mv t1,t5 - 80002c5c: 000f0eb7 lui t4,0xf0 - 80002c60: 0ffe8e9b addiw t4,t4,255 - 80002c64: 00ce9e93 slli t4,t4,0xc - 80002c68: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 80002c6c: 13d31863 bne t1,t4,80002d9c - 80002c70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c74: 00200293 li t0,2 - 80002c78: fc5218e3 bne tp,t0,80002c48 - -0000000080002c7c : - 80002c7c: 00e00193 li gp,14 - 80002c80: 00000213 li tp,0 - 80002c84: 00000097 auipc ra,0x0 - 80002c88: 37c08093 addi ra,ra,892 # 80003000 - 80002c8c: 0040ef03 lwu t5,4(ra) - 80002c90: 00000013 nop - 80002c94: 00000013 nop - 80002c98: 000f0313 mv t1,t5 - 80002c9c: 00010eb7 lui t4,0x10 - 80002ca0: f01e8e9b addiw t4,t4,-255 - 80002ca4: 010e9e93 slli t4,t4,0x10 - 80002ca8: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80002cac: 0fd31863 bne t1,t4,80002d9c - 80002cb0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cb4: 00200293 li t0,2 - 80002cb8: fc5216e3 bne tp,t0,80002c84 - -0000000080002cbc : - 80002cbc: 00f00193 li gp,15 - 80002cc0: 00000213 li tp,0 - 80002cc4: 00000097 auipc ra,0x0 - 80002cc8: 34008093 addi ra,ra,832 # 80003004 - 80002ccc: 0040ef03 lwu t5,4(ra) - 80002cd0: 0ff01eb7 lui t4,0xff01 - 80002cd4: ff0e8e9b addiw t4,t4,-16 - 80002cd8: 0ddf1263 bne t5,t4,80002d9c - 80002cdc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ce0: 00200293 li t0,2 - 80002ce4: fe5210e3 bne tp,t0,80002cc4 - -0000000080002ce8 : - 80002ce8: 01000193 li gp,16 - 80002cec: 00000213 li tp,0 - 80002cf0: 00000097 auipc ra,0x0 - 80002cf4: 31808093 addi ra,ra,792 # 80003008 - 80002cf8: 00000013 nop - 80002cfc: 0040ef03 lwu t5,4(ra) - 80002d00: 000f0eb7 lui t4,0xf0 - 80002d04: 0ffe8e9b addiw t4,t4,255 - 80002d08: 00ce9e93 slli t4,t4,0xc - 80002d0c: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 80002d10: 09df1663 bne t5,t4,80002d9c - 80002d14: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d18: 00200293 li t0,2 - 80002d1c: fc521ae3 bne tp,t0,80002cf0 - -0000000080002d20 : - 80002d20: 01100193 li gp,17 - 80002d24: 00000213 li tp,0 - 80002d28: 00000097 auipc ra,0x0 - 80002d2c: 2d808093 addi ra,ra,728 # 80003000 - 80002d30: 00000013 nop - 80002d34: 00000013 nop - 80002d38: 0040ef03 lwu t5,4(ra) - 80002d3c: 00010eb7 lui t4,0x10 - 80002d40: f01e8e9b addiw t4,t4,-255 - 80002d44: 010e9e93 slli t4,t4,0x10 - 80002d48: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80002d4c: 05df1863 bne t5,t4,80002d9c - 80002d50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d54: 00200293 li t0,2 - 80002d58: fc5218e3 bne tp,t0,80002d28 - -0000000080002d5c : - 80002d5c: 00000297 auipc t0,0x0 - 80002d60: 2a428293 addi t0,t0,676 # 80003000 - 80002d64: 0002e103 lwu sp,0(t0) - 80002d68: 00200113 li sp,2 - 80002d6c: 00200e93 li t4,2 - 80002d70: 01200193 li gp,18 - 80002d74: 03d11463 bne sp,t4,80002d9c - -0000000080002d78 : - 80002d78: 00000297 auipc t0,0x0 - 80002d7c: 28828293 addi t0,t0,648 # 80003000 - 80002d80: 0002e103 lwu sp,0(t0) - 80002d84: 00000013 nop - 80002d88: 00200113 li sp,2 - 80002d8c: 00200e93 li t4,2 - 80002d90: 01300193 li gp,19 - 80002d94: 01d11463 bne sp,t4,80002d9c - 80002d98: 00301a63 bne zero,gp,80002dac - -0000000080002d9c : - 80002d9c: 00119513 slli a0,gp,0x1 - 80002da0: 00050063 beqz a0,80002da0 - 80002da4: 00156513 ori a0,a0,1 - 80002da8: 00000073 ecall - -0000000080002dac : - 80002dac: 00100513 li a0,1 - 80002db0: 00000073 ecall - 80002db4: c0001073 unimp - -Disassembly of section .data: - -0000000080003000 : - 80003000: 00ff 0xff - 80003002: 00ff 0xff - -0000000080003004 : - 80003004: ff00 sd s0,56(a4) - 80003006: ff00 sd s0,56(a4) - -0000000080003008 : - 80003008: 0ff0 addi a2,sp,988 - 8000300a: 0ff0 addi a2,sp,988 - -000000008000300c : - 8000300c: f00ff00f 0xf00ff00f diff --git a/test/riscv/tests/rv64ui-v-lwu.elf b/test/riscv/tests/rv64ui-v-lwu.elf deleted file mode 100644 index 2cd5e0bd..00000000 Binary files a/test/riscv/tests/rv64ui-v-lwu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-or.dump b/test/riscv/tests/rv64ui-v-or.dump deleted file mode 100644 index c5e0940a..00000000 --- a/test/riscv/tests/rv64ui-v-or.dump +++ /dev/null @@ -1,1265 +0,0 @@ - -rv64ui-v-or: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: c6868693 addi a3,a3,-920 # 800030c0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: c9c60613 addi a2,a2,-868 # 80003150 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: c6460613 addi a2,a2,-924 # 80003168 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: bb468693 addi a3,a3,-1100 # 80003108 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: bd068693 addi a3,a3,-1072 # 80003240 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: b5060613 addi a2,a2,-1200 # 80003218 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: a8468693 addi a3,a3,-1404 # 80003270 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 9a468693 addi a3,a3,-1628 # 800031e0 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00001697 auipc a3,0x1 - 80002878: 93468693 addi a3,a3,-1740 # 800031a8 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 03800793 li a5,56 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 039357b7 lui a5,0x3935 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: f5d78793 addi a5,a5,-163 # 3934f5d <_start-0x7c6cb0a3> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 000100b7 lui ra,0x10 - 80002acc: f010809b addiw ra,ra,-255 - 80002ad0: 01009093 slli ra,ra,0x10 - 80002ad4: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002ad8: 0f0f1137 lui sp,0xf0f1 - 80002adc: f0f1011b addiw sp,sp,-241 - 80002ae0: 0020ef33 or t5,ra,sp - 80002ae4: 00001eb7 lui t4,0x1 - 80002ae8: ff1e8e9b addiw t4,t4,-15 - 80002aec: 014e9e93 slli t4,t4,0x14 - 80002af0: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> - 80002af4: 00200193 li gp,2 - 80002af8: 5bdf1663 bne t5,t4,800030a4 - -0000000080002afc : - 80002afc: 0ff010b7 lui ra,0xff01 - 80002b00: ff00809b addiw ra,ra,-16 - 80002b04: 000f1137 lui sp,0xf1 - 80002b08: f0f1011b addiw sp,sp,-241 - 80002b0c: 00c11113 slli sp,sp,0xc - 80002b10: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002b14: 0020ef33 or t5,ra,sp - 80002b18: 00010eb7 lui t4,0x10 - 80002b1c: ff1e8e9b addiw t4,t4,-15 - 80002b20: 010e9e93 slli t4,t4,0x10 - 80002b24: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> - 80002b28: 00300193 li gp,3 - 80002b2c: 57df1c63 bne t5,t4,800030a4 - -0000000080002b30 : - 80002b30: 00ff00b7 lui ra,0xff0 - 80002b34: 0ff0809b addiw ra,ra,255 - 80002b38: 0f0f1137 lui sp,0xf0f1 - 80002b3c: f0f1011b addiw sp,sp,-241 - 80002b40: 0020ef33 or t5,ra,sp - 80002b44: 0fff1eb7 lui t4,0xfff1 - 80002b48: fffe8e9b addiw t4,t4,-1 - 80002b4c: 00400193 li gp,4 - 80002b50: 55df1a63 bne t5,t4,800030a4 - -0000000080002b54 : - 80002b54: 000f00b7 lui ra,0xf0 - 80002b58: 0ff0809b addiw ra,ra,255 - 80002b5c: 00c09093 slli ra,ra,0xc - 80002b60: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> - 80002b64: 000f1137 lui sp,0xf1 - 80002b68: f0f1011b addiw sp,sp,-241 - 80002b6c: 00c11113 slli sp,sp,0xc - 80002b70: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002b74: 0020ef33 or t5,ra,sp - 80002b78: 000f1eb7 lui t4,0xf1 - 80002b7c: fffe8e9b addiw t4,t4,-1 - 80002b80: 00ce9e93 slli t4,t4,0xc - 80002b84: 0ffe8e93 addi t4,t4,255 # f10ff <_start-0x7ff0ef01> - 80002b88: 00500193 li gp,5 - 80002b8c: 51df1c63 bne t5,t4,800030a4 - -0000000080002b90 : - 80002b90: 000100b7 lui ra,0x10 - 80002b94: f010809b addiw ra,ra,-255 - 80002b98: 01009093 slli ra,ra,0x10 - 80002b9c: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002ba0: 0f0f1137 lui sp,0xf0f1 - 80002ba4: f0f1011b addiw sp,sp,-241 - 80002ba8: 0020e0b3 or ra,ra,sp - 80002bac: 00001eb7 lui t4,0x1 - 80002bb0: ff1e8e9b addiw t4,t4,-15 - 80002bb4: 014e9e93 slli t4,t4,0x14 - 80002bb8: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> - 80002bbc: 00600193 li gp,6 - 80002bc0: 4fd09263 bne ra,t4,800030a4 - -0000000080002bc4 : - 80002bc4: 000100b7 lui ra,0x10 - 80002bc8: f010809b addiw ra,ra,-255 - 80002bcc: 01009093 slli ra,ra,0x10 - 80002bd0: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002bd4: 0f0f1137 lui sp,0xf0f1 - 80002bd8: f0f1011b addiw sp,sp,-241 - 80002bdc: 0020e133 or sp,ra,sp - 80002be0: 00001eb7 lui t4,0x1 - 80002be4: ff1e8e9b addiw t4,t4,-15 - 80002be8: 014e9e93 slli t4,t4,0x14 - 80002bec: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> - 80002bf0: 00700193 li gp,7 - 80002bf4: 4bd11863 bne sp,t4,800030a4 - -0000000080002bf8 : - 80002bf8: 000100b7 lui ra,0x10 - 80002bfc: f010809b addiw ra,ra,-255 - 80002c00: 01009093 slli ra,ra,0x10 - 80002c04: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002c08: 0010e0b3 or ra,ra,ra - 80002c0c: 00010eb7 lui t4,0x10 - 80002c10: f01e8e9b addiw t4,t4,-255 - 80002c14: 010e9e93 slli t4,t4,0x10 - 80002c18: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80002c1c: 00800193 li gp,8 - 80002c20: 49d09263 bne ra,t4,800030a4 - -0000000080002c24 : - 80002c24: 00000213 li tp,0 - 80002c28: 000100b7 lui ra,0x10 - 80002c2c: f010809b addiw ra,ra,-255 - 80002c30: 01009093 slli ra,ra,0x10 - 80002c34: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002c38: 0f0f1137 lui sp,0xf0f1 - 80002c3c: f0f1011b addiw sp,sp,-241 - 80002c40: 0020ef33 or t5,ra,sp - 80002c44: 000f0313 mv t1,t5 - 80002c48: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c4c: 00200293 li t0,2 - 80002c50: fc521ce3 bne tp,t0,80002c28 - 80002c54: 00001eb7 lui t4,0x1 - 80002c58: ff1e8e9b addiw t4,t4,-15 - 80002c5c: 014e9e93 slli t4,t4,0x14 - 80002c60: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> - 80002c64: 00900193 li gp,9 - 80002c68: 43d31e63 bne t1,t4,800030a4 - -0000000080002c6c : - 80002c6c: 00000213 li tp,0 - 80002c70: 0ff010b7 lui ra,0xff01 - 80002c74: ff00809b addiw ra,ra,-16 - 80002c78: 000f1137 lui sp,0xf1 - 80002c7c: f0f1011b addiw sp,sp,-241 - 80002c80: 00c11113 slli sp,sp,0xc - 80002c84: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002c88: 0020ef33 or t5,ra,sp - 80002c8c: 00000013 nop - 80002c90: 000f0313 mv t1,t5 - 80002c94: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c98: 00200293 li t0,2 - 80002c9c: fc521ae3 bne tp,t0,80002c70 - 80002ca0: 00010eb7 lui t4,0x10 - 80002ca4: ff1e8e9b addiw t4,t4,-15 - 80002ca8: 010e9e93 slli t4,t4,0x10 - 80002cac: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> - 80002cb0: 00a00193 li gp,10 - 80002cb4: 3fd31863 bne t1,t4,800030a4 - -0000000080002cb8 : - 80002cb8: 00000213 li tp,0 - 80002cbc: 00ff00b7 lui ra,0xff0 - 80002cc0: 0ff0809b addiw ra,ra,255 - 80002cc4: 0f0f1137 lui sp,0xf0f1 - 80002cc8: f0f1011b addiw sp,sp,-241 - 80002ccc: 0020ef33 or t5,ra,sp - 80002cd0: 00000013 nop - 80002cd4: 00000013 nop - 80002cd8: 000f0313 mv t1,t5 - 80002cdc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ce0: 00200293 li t0,2 - 80002ce4: fc521ce3 bne tp,t0,80002cbc - 80002ce8: 0fff1eb7 lui t4,0xfff1 - 80002cec: fffe8e9b addiw t4,t4,-1 - 80002cf0: 00b00193 li gp,11 - 80002cf4: 3bd31863 bne t1,t4,800030a4 - -0000000080002cf8 : - 80002cf8: 00000213 li tp,0 - 80002cfc: 000100b7 lui ra,0x10 - 80002d00: f010809b addiw ra,ra,-255 - 80002d04: 01009093 slli ra,ra,0x10 - 80002d08: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002d0c: 0f0f1137 lui sp,0xf0f1 - 80002d10: f0f1011b addiw sp,sp,-241 - 80002d14: 0020ef33 or t5,ra,sp - 80002d18: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d1c: 00200293 li t0,2 - 80002d20: fc521ee3 bne tp,t0,80002cfc - 80002d24: 00001eb7 lui t4,0x1 - 80002d28: ff1e8e9b addiw t4,t4,-15 - 80002d2c: 014e9e93 slli t4,t4,0x14 - 80002d30: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> - 80002d34: 00c00193 li gp,12 - 80002d38: 37df1663 bne t5,t4,800030a4 - -0000000080002d3c : - 80002d3c: 00000213 li tp,0 - 80002d40: 0ff010b7 lui ra,0xff01 - 80002d44: ff00809b addiw ra,ra,-16 - 80002d48: 000f1137 lui sp,0xf1 - 80002d4c: f0f1011b addiw sp,sp,-241 - 80002d50: 00c11113 slli sp,sp,0xc - 80002d54: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002d58: 00000013 nop - 80002d5c: 0020ef33 or t5,ra,sp - 80002d60: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d64: 00200293 li t0,2 - 80002d68: fc521ce3 bne tp,t0,80002d40 - 80002d6c: 00010eb7 lui t4,0x10 - 80002d70: ff1e8e9b addiw t4,t4,-15 - 80002d74: 010e9e93 slli t4,t4,0x10 - 80002d78: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> - 80002d7c: 00d00193 li gp,13 - 80002d80: 33df1263 bne t5,t4,800030a4 - -0000000080002d84 : - 80002d84: 00000213 li tp,0 - 80002d88: 00ff00b7 lui ra,0xff0 - 80002d8c: 0ff0809b addiw ra,ra,255 - 80002d90: 0f0f1137 lui sp,0xf0f1 - 80002d94: f0f1011b addiw sp,sp,-241 - 80002d98: 00000013 nop - 80002d9c: 00000013 nop - 80002da0: 0020ef33 or t5,ra,sp - 80002da4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002da8: 00200293 li t0,2 - 80002dac: fc521ee3 bne tp,t0,80002d88 - 80002db0: 0fff1eb7 lui t4,0xfff1 - 80002db4: fffe8e9b addiw t4,t4,-1 - 80002db8: 00e00193 li gp,14 - 80002dbc: 2fdf1463 bne t5,t4,800030a4 - -0000000080002dc0 : - 80002dc0: 00000213 li tp,0 - 80002dc4: 000100b7 lui ra,0x10 - 80002dc8: f010809b addiw ra,ra,-255 - 80002dcc: 01009093 slli ra,ra,0x10 - 80002dd0: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002dd4: 00000013 nop - 80002dd8: 0f0f1137 lui sp,0xf0f1 - 80002ddc: f0f1011b addiw sp,sp,-241 - 80002de0: 0020ef33 or t5,ra,sp - 80002de4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002de8: 00200293 li t0,2 - 80002dec: fc521ce3 bne tp,t0,80002dc4 - 80002df0: 00001eb7 lui t4,0x1 - 80002df4: ff1e8e9b addiw t4,t4,-15 - 80002df8: 014e9e93 slli t4,t4,0x14 - 80002dfc: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> - 80002e00: 00f00193 li gp,15 - 80002e04: 2bdf1063 bne t5,t4,800030a4 - -0000000080002e08 : - 80002e08: 00000213 li tp,0 - 80002e0c: 0ff010b7 lui ra,0xff01 - 80002e10: ff00809b addiw ra,ra,-16 - 80002e14: 00000013 nop - 80002e18: 000f1137 lui sp,0xf1 - 80002e1c: f0f1011b addiw sp,sp,-241 - 80002e20: 00c11113 slli sp,sp,0xc - 80002e24: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002e28: 00000013 nop - 80002e2c: 0020ef33 or t5,ra,sp - 80002e30: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e34: 00200293 li t0,2 - 80002e38: fc521ae3 bne tp,t0,80002e0c - 80002e3c: 00010eb7 lui t4,0x10 - 80002e40: ff1e8e9b addiw t4,t4,-15 - 80002e44: 010e9e93 slli t4,t4,0x10 - 80002e48: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> - 80002e4c: 01000193 li gp,16 - 80002e50: 25df1a63 bne t5,t4,800030a4 - -0000000080002e54 : - 80002e54: 00000213 li tp,0 - 80002e58: 00ff00b7 lui ra,0xff0 - 80002e5c: 0ff0809b addiw ra,ra,255 - 80002e60: 00000013 nop - 80002e64: 00000013 nop - 80002e68: 0f0f1137 lui sp,0xf0f1 - 80002e6c: f0f1011b addiw sp,sp,-241 - 80002e70: 0020ef33 or t5,ra,sp - 80002e74: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e78: 00200293 li t0,2 - 80002e7c: fc521ee3 bne tp,t0,80002e58 - 80002e80: 0fff1eb7 lui t4,0xfff1 - 80002e84: fffe8e9b addiw t4,t4,-1 - 80002e88: 01100193 li gp,17 - 80002e8c: 21df1c63 bne t5,t4,800030a4 - -0000000080002e90 : - 80002e90: 00000213 li tp,0 - 80002e94: 0f0f1137 lui sp,0xf0f1 - 80002e98: f0f1011b addiw sp,sp,-241 - 80002e9c: 000100b7 lui ra,0x10 - 80002ea0: f010809b addiw ra,ra,-255 - 80002ea4: 01009093 slli ra,ra,0x10 - 80002ea8: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002eac: 0020ef33 or t5,ra,sp - 80002eb0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002eb4: 00200293 li t0,2 - 80002eb8: fc521ee3 bne tp,t0,80002e94 - 80002ebc: 00001eb7 lui t4,0x1 - 80002ec0: ff1e8e9b addiw t4,t4,-15 - 80002ec4: 014e9e93 slli t4,t4,0x14 - 80002ec8: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> - 80002ecc: 01200193 li gp,18 - 80002ed0: 1ddf1a63 bne t5,t4,800030a4 - -0000000080002ed4 : - 80002ed4: 00000213 li tp,0 - 80002ed8: 000f1137 lui sp,0xf1 - 80002edc: f0f1011b addiw sp,sp,-241 - 80002ee0: 00c11113 slli sp,sp,0xc - 80002ee4: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002ee8: 0ff010b7 lui ra,0xff01 - 80002eec: ff00809b addiw ra,ra,-16 - 80002ef0: 00000013 nop - 80002ef4: 0020ef33 or t5,ra,sp - 80002ef8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002efc: 00200293 li t0,2 - 80002f00: fc521ce3 bne tp,t0,80002ed8 - 80002f04: 00010eb7 lui t4,0x10 - 80002f08: ff1e8e9b addiw t4,t4,-15 - 80002f0c: 010e9e93 slli t4,t4,0x10 - 80002f10: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> - 80002f14: 01300193 li gp,19 - 80002f18: 19df1663 bne t5,t4,800030a4 - -0000000080002f1c : - 80002f1c: 00000213 li tp,0 - 80002f20: 0f0f1137 lui sp,0xf0f1 - 80002f24: f0f1011b addiw sp,sp,-241 - 80002f28: 00ff00b7 lui ra,0xff0 - 80002f2c: 0ff0809b addiw ra,ra,255 - 80002f30: 00000013 nop - 80002f34: 00000013 nop - 80002f38: 0020ef33 or t5,ra,sp - 80002f3c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f40: 00200293 li t0,2 - 80002f44: fc521ee3 bne tp,t0,80002f20 - 80002f48: 0fff1eb7 lui t4,0xfff1 - 80002f4c: fffe8e9b addiw t4,t4,-1 - 80002f50: 01400193 li gp,20 - 80002f54: 15df1863 bne t5,t4,800030a4 - -0000000080002f58 : - 80002f58: 00000213 li tp,0 - 80002f5c: 0f0f1137 lui sp,0xf0f1 - 80002f60: f0f1011b addiw sp,sp,-241 - 80002f64: 00000013 nop - 80002f68: 000100b7 lui ra,0x10 - 80002f6c: f010809b addiw ra,ra,-255 - 80002f70: 01009093 slli ra,ra,0x10 - 80002f74: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002f78: 0020ef33 or t5,ra,sp - 80002f7c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f80: 00200293 li t0,2 - 80002f84: fc521ce3 bne tp,t0,80002f5c - 80002f88: 00001eb7 lui t4,0x1 - 80002f8c: ff1e8e9b addiw t4,t4,-15 - 80002f90: 014e9e93 slli t4,t4,0x14 - 80002f94: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> - 80002f98: 01500193 li gp,21 - 80002f9c: 11df1463 bne t5,t4,800030a4 - -0000000080002fa0 : - 80002fa0: 00000213 li tp,0 - 80002fa4: 000f1137 lui sp,0xf1 - 80002fa8: f0f1011b addiw sp,sp,-241 - 80002fac: 00c11113 slli sp,sp,0xc - 80002fb0: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002fb4: 00000013 nop - 80002fb8: 0ff010b7 lui ra,0xff01 - 80002fbc: ff00809b addiw ra,ra,-16 - 80002fc0: 00000013 nop - 80002fc4: 0020ef33 or t5,ra,sp - 80002fc8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002fcc: 00200293 li t0,2 - 80002fd0: fc521ae3 bne tp,t0,80002fa4 - 80002fd4: 00010eb7 lui t4,0x10 - 80002fd8: ff1e8e9b addiw t4,t4,-15 - 80002fdc: 010e9e93 slli t4,t4,0x10 - 80002fe0: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> - 80002fe4: 01600193 li gp,22 - 80002fe8: 0bdf1e63 bne t5,t4,800030a4 - -0000000080002fec : - 80002fec: 00000213 li tp,0 - 80002ff0: 0f0f1137 lui sp,0xf0f1 - 80002ff4: f0f1011b addiw sp,sp,-241 - 80002ff8: 00000013 nop - 80002ffc: 00000013 nop - 80003000: 00ff00b7 lui ra,0xff0 - 80003004: 0ff0809b addiw ra,ra,255 - 80003008: 0020ef33 or t5,ra,sp - 8000300c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80003010: 00200293 li t0,2 - 80003014: fc521ee3 bne tp,t0,80002ff0 - 80003018: 0fff1eb7 lui t4,0xfff1 - 8000301c: fffe8e9b addiw t4,t4,-1 - 80003020: 01700193 li gp,23 - 80003024: 09df1063 bne t5,t4,800030a4 - -0000000080003028 : - 80003028: 000100b7 lui ra,0x10 - 8000302c: f010809b addiw ra,ra,-255 - 80003030: 01009093 slli ra,ra,0x10 - 80003034: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80003038: 00106133 or sp,zero,ra - 8000303c: 00010eb7 lui t4,0x10 - 80003040: f01e8e9b addiw t4,t4,-255 - 80003044: 010e9e93 slli t4,t4,0x10 - 80003048: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 8000304c: 01800193 li gp,24 - 80003050: 05d11a63 bne sp,t4,800030a4 - -0000000080003054 : - 80003054: 00ff00b7 lui ra,0xff0 - 80003058: 0ff0809b addiw ra,ra,255 - 8000305c: 0000e133 or sp,ra,zero - 80003060: 00ff0eb7 lui t4,0xff0 - 80003064: 0ffe8e9b addiw t4,t4,255 - 80003068: 01900193 li gp,25 - 8000306c: 03d11c63 bne sp,t4,800030a4 - -0000000080003070 : - 80003070: 000060b3 or ra,zero,zero - 80003074: 00000e93 li t4,0 - 80003078: 01a00193 li gp,26 - 8000307c: 03d09463 bne ra,t4,800030a4 - -0000000080003080 : - 80003080: 111110b7 lui ra,0x11111 - 80003084: 1110809b addiw ra,ra,273 - 80003088: 22222137 lui sp,0x22222 - 8000308c: 2221011b addiw sp,sp,546 - 80003090: 0020e033 or zero,ra,sp - 80003094: 00000e93 li t4,0 - 80003098: 01b00193 li gp,27 - 8000309c: 01d01463 bne zero,t4,800030a4 - 800030a0: 00301a63 bne zero,gp,800030b4 - -00000000800030a4 : - 800030a4: 00119513 slli a0,gp,0x1 - 800030a8: 00050063 beqz a0,800030a8 - 800030ac: 00156513 ori a0,a0,1 - 800030b0: 00000073 ecall - -00000000800030b4 : - 800030b4: 00100513 li a0,1 - 800030b8: 00000073 ecall - 800030bc: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-or.elf b/test/riscv/tests/rv64ui-v-or.elf deleted file mode 100644 index cf601403..00000000 Binary files a/test/riscv/tests/rv64ui-v-or.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-ori.dump b/test/riscv/tests/rv64ui-v-ori.dump deleted file mode 100644 index 9b536c5f..00000000 --- a/test/riscv/tests/rv64ui-v-ori.dump +++ /dev/null @@ -1,987 +0,0 @@ - -rv64ui-v-ori: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 87868693 addi a3,a3,-1928 # 80002cd0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 8ac60613 addi a2,a2,-1876 # 80002d60 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 87460613 addi a2,a2,-1932 # 80002d78 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 7c468693 addi a3,a3,1988 # 80002d18 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 7e068693 addi a3,a3,2016 # 80002e50 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 76060613 addi a2,a2,1888 # 80002e28 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 69468693 addi a3,a3,1684 # 80002e80 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 5b468693 addi a3,a3,1460 # 80002df0 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 54468693 addi a3,a3,1348 # 80002db8 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 00d00793 li a5,13 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0a6287b7 lui a5,0xa628 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: a5878793 addi a5,a5,-1448 # a627a58 <_start-0x759d85a8> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: ff0100b7 lui ra,0xff010 - 80002acc: f000809b addiw ra,ra,-256 - 80002ad0: f0f0ef13 ori t5,ra,-241 - 80002ad4: f0f00e93 li t4,-241 - 80002ad8: 00200193 li gp,2 - 80002adc: 1ddf1c63 bne t5,t4,80002cb4 - -0000000080002ae0 : - 80002ae0: 0ff010b7 lui ra,0xff01 - 80002ae4: ff00809b addiw ra,ra,-16 - 80002ae8: 0f00ef13 ori t5,ra,240 - 80002aec: 0ff01eb7 lui t4,0xff01 - 80002af0: ff0e8e9b addiw t4,t4,-16 - 80002af4: 00300193 li gp,3 - 80002af8: 1bdf1e63 bne t5,t4,80002cb4 - -0000000080002afc : - 80002afc: 00ff00b7 lui ra,0xff0 - 80002b00: 0ff0809b addiw ra,ra,255 - 80002b04: 70f0ef13 ori t5,ra,1807 - 80002b08: 00ff0eb7 lui t4,0xff0 - 80002b0c: 7ffe8e9b addiw t4,t4,2047 - 80002b10: 00400193 li gp,4 - 80002b14: 1bdf1063 bne t5,t4,80002cb4 - -0000000080002b18 : - 80002b18: f00ff0b7 lui ra,0xf00ff - 80002b1c: 00f0809b addiw ra,ra,15 - 80002b20: 0f00ef13 ori t5,ra,240 - 80002b24: f00ffeb7 lui t4,0xf00ff - 80002b28: 0ffe8e9b addiw t4,t4,255 - 80002b2c: 00500193 li gp,5 - 80002b30: 19df1263 bne t5,t4,80002cb4 - -0000000080002b34 : - 80002b34: 000100b7 lui ra,0x10 - 80002b38: f010809b addiw ra,ra,-255 - 80002b3c: 01009093 slli ra,ra,0x10 - 80002b40: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002b44: 0f00e093 ori ra,ra,240 - 80002b48: 00010eb7 lui t4,0x10 - 80002b4c: f01e8e9b addiw t4,t4,-255 - 80002b50: 010e9e93 slli t4,t4,0x10 - 80002b54: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> - 80002b58: 00600193 li gp,6 - 80002b5c: 15d09c63 bne ra,t4,80002cb4 - -0000000080002b60 : - 80002b60: 00000213 li tp,0 - 80002b64: 0ff010b7 lui ra,0xff01 - 80002b68: ff00809b addiw ra,ra,-16 - 80002b6c: 0f00ef13 ori t5,ra,240 - 80002b70: 000f0313 mv t1,t5 - 80002b74: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002b78: 00200293 li t0,2 - 80002b7c: fe5214e3 bne tp,t0,80002b64 - 80002b80: 0ff01eb7 lui t4,0xff01 - 80002b84: ff0e8e9b addiw t4,t4,-16 - 80002b88: 00700193 li gp,7 - 80002b8c: 13d31463 bne t1,t4,80002cb4 - -0000000080002b90 : - 80002b90: 00000213 li tp,0 - 80002b94: 00ff00b7 lui ra,0xff0 - 80002b98: 0ff0809b addiw ra,ra,255 - 80002b9c: 70f0ef13 ori t5,ra,1807 - 80002ba0: 00000013 nop - 80002ba4: 000f0313 mv t1,t5 - 80002ba8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002bac: 00200293 li t0,2 - 80002bb0: fe5212e3 bne tp,t0,80002b94 - 80002bb4: 00ff0eb7 lui t4,0xff0 - 80002bb8: 7ffe8e9b addiw t4,t4,2047 - 80002bbc: 00800193 li gp,8 - 80002bc0: 0fd31a63 bne t1,t4,80002cb4 - -0000000080002bc4 : - 80002bc4: 00000213 li tp,0 - 80002bc8: f00ff0b7 lui ra,0xf00ff - 80002bcc: 00f0809b addiw ra,ra,15 - 80002bd0: 0f00ef13 ori t5,ra,240 - 80002bd4: 00000013 nop - 80002bd8: 00000013 nop - 80002bdc: 000f0313 mv t1,t5 - 80002be0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002be4: 00200293 li t0,2 - 80002be8: fe5210e3 bne tp,t0,80002bc8 - 80002bec: f00ffeb7 lui t4,0xf00ff - 80002bf0: 0ffe8e9b addiw t4,t4,255 - 80002bf4: 00900193 li gp,9 - 80002bf8: 0bd31e63 bne t1,t4,80002cb4 - -0000000080002bfc : - 80002bfc: 00000213 li tp,0 - 80002c00: 0ff010b7 lui ra,0xff01 - 80002c04: ff00809b addiw ra,ra,-16 - 80002c08: 0f00ef13 ori t5,ra,240 - 80002c0c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c10: 00200293 li t0,2 - 80002c14: fe5216e3 bne tp,t0,80002c00 - 80002c18: 0ff01eb7 lui t4,0xff01 - 80002c1c: ff0e8e9b addiw t4,t4,-16 - 80002c20: 00a00193 li gp,10 - 80002c24: 09df1863 bne t5,t4,80002cb4 - -0000000080002c28 : - 80002c28: 00000213 li tp,0 - 80002c2c: 00ff00b7 lui ra,0xff0 - 80002c30: 0ff0809b addiw ra,ra,255 - 80002c34: 00000013 nop - 80002c38: f0f0ef13 ori t5,ra,-241 - 80002c3c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c40: 00200293 li t0,2 - 80002c44: fe5214e3 bne tp,t0,80002c2c - 80002c48: fff00e93 li t4,-1 - 80002c4c: 00b00193 li gp,11 - 80002c50: 07df1263 bne t5,t4,80002cb4 - -0000000080002c54 : - 80002c54: 00000213 li tp,0 - 80002c58: f00ff0b7 lui ra,0xf00ff - 80002c5c: 00f0809b addiw ra,ra,15 - 80002c60: 00000013 nop - 80002c64: 00000013 nop - 80002c68: 0f00ef13 ori t5,ra,240 - 80002c6c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c70: 00200293 li t0,2 - 80002c74: fe5212e3 bne tp,t0,80002c58 - 80002c78: f00ffeb7 lui t4,0xf00ff - 80002c7c: 0ffe8e9b addiw t4,t4,255 - 80002c80: 00c00193 li gp,12 - 80002c84: 03df1863 bne t5,t4,80002cb4 - -0000000080002c88 : - 80002c88: 0f006093 ori ra,zero,240 - 80002c8c: 0f000e93 li t4,240 - 80002c90: 00d00193 li gp,13 - 80002c94: 03d09063 bne ra,t4,80002cb4 - -0000000080002c98 : - 80002c98: 00ff00b7 lui ra,0xff0 - 80002c9c: 0ff0809b addiw ra,ra,255 - 80002ca0: 70f0e013 ori zero,ra,1807 - 80002ca4: 00000e93 li t4,0 - 80002ca8: 00e00193 li gp,14 - 80002cac: 01d01463 bne zero,t4,80002cb4 - 80002cb0: 00301a63 bne zero,gp,80002cc4 - -0000000080002cb4 : - 80002cb4: 00119513 slli a0,gp,0x1 - 80002cb8: 00050063 beqz a0,80002cb8 - 80002cbc: 00156513 ori a0,a0,1 - 80002cc0: 00000073 ecall - -0000000080002cc4 : - 80002cc4: 00100513 li a0,1 - 80002cc8: 00000073 ecall - 80002ccc: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-ori.elf b/test/riscv/tests/rv64ui-v-ori.elf deleted file mode 100644 index db589c1d..00000000 Binary files a/test/riscv/tests/rv64ui-v-ori.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-sb.dump b/test/riscv/tests/rv64ui-v-sb.dump deleted file mode 100644 index 52b1645b..00000000 --- a/test/riscv/tests/rv64ui-v-sb.dump +++ /dev/null @@ -1,1169 +0,0 @@ - -rv64ui-v-sb: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 0000a117 auipc sp,0xa - 8000001c: 6b810113 addi sp,sp,1720 # 8000a6d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00003617 auipc a2,0x3 - 80002318: cec60613 addi a2,a2,-788 # 80005000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00007797 auipc a5,0x7 - 80002334: 4b878793 addi a5,a5,1208 # 800097e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00007717 auipc a4,0x7 - 80002348: 49c70713 addi a4,a4,1180 # 800097e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00007897 auipc a7,0x7 - 80002354: 48f8bc23 sd a5,1176(a7) # 800097e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00007797 auipc a5,0x7 - 80002384: 07078793 addi a5,a5,112 # 800093f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf6810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00007797 auipc a5,0x7 - 80002448: 3807be23 sd zero,924(a5) # 800097e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: a8068693 addi a3,a3,-1408 # 80002ed8 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: ab460613 addi a2,a2,-1356 # 80002f68 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: a7c60613 addi a2,a2,-1412 # 80002f80 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 9cc68693 addi a3,a3,-1588 # 80002f20 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 9e868693 addi a3,a3,-1560 # 80003058 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 96860613 addi a2,a2,-1688 # 80003030 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00007d17 auipc s10,0x7 - 80002720: cd4d0d13 addi s10,s10,-812 # 800093f0 - 80002724: 00003b97 auipc s7,0x3 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80005000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00007a17 auipc s4,0x7 - 80002738: 0aca0a13 addi s4,s4,172 # 800097e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00007717 auipc a4,0x7 - 8000274c: 08f73c23 sd a5,152(a4) # 800097e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00007717 auipc a4,0x7 - 800027d4: 00f73823 sd a5,16(a4) # 800097e0 - 800027d8: 00007717 auipc a4,0x7 - 800027dc: 00f73823 sd a5,16(a4) # 800097e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: 89c68693 addi a3,a3,-1892 # 80003088 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 7bc68693 addi a3,a3,1980 # 80002ff8 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 74c68693 addi a3,a3,1868 # 80002fc0 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00003697 auipc a3,0x3 - 800028e0: 72468693 addi a3,a3,1828 # 80006000 - 800028e4: 00004717 auipc a4,0x4 - 800028e8: 71c70713 addi a4,a4,1820 # 80007000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00005797 auipc a5,0x5 - 800028f8: 70c78793 addi a5,a5,1804 # 80008000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00002897 auipc a7,0x2 - 80002914: 6ed8b823 sd a3,1776(a7) # 80005000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00003697 auipc a3,0x3 - 80002920: 6ce6be23 sd a4,1756(a3) # 80005ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00002617 auipc a2,0x2 - 80002938: 6cc60613 addi a2,a2,1740 # 80005000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00005697 auipc a3,0x5 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80007ff8 - 8000294c: 00003717 auipc a4,0x3 - 80002950: 6af73a23 sd a5,1716(a4) # 80006000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00006697 auipc a3,0x6 - 800029c0: 64468693 addi a3,a3,1604 # 80009000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00007617 auipc a2,0x7 - 800029d0: e0f63e23 sd a5,-484(a2) # 800097e8 - 800029d4: 00007797 auipc a5,0x7 - 800029d8: e0e7b623 sd a4,-500(a5) # 800097e0 - 800029dc: 00007317 auipc t1,0x7 - 800029e0: a1430313 addi t1,t1,-1516 # 800093f0 - 800029e4: 01300793 li a5,19 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00007797 auipc a5,0x7 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800093e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 061a97b7 lui a5,0x61a9 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 7fc78793 addi a5,a5,2044 # 61a97fc <_start-0x79e56804> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00001097 auipc ra,0x1 - 80002acc: 53808093 addi ra,ra,1336 # 80004000 - 80002ad0: faa00113 li sp,-86 - 80002ad4: 00208023 sb sp,0(ra) - 80002ad8: 00008f03 lb t5,0(ra) - 80002adc: faa00e93 li t4,-86 - 80002ae0: 00200193 li gp,2 - 80002ae4: 3ddf1c63 bne t5,t4,80002ebc - -0000000080002ae8 : - 80002ae8: 00001097 auipc ra,0x1 - 80002aec: 51808093 addi ra,ra,1304 # 80004000 - 80002af0: 00000113 li sp,0 - 80002af4: 002080a3 sb sp,1(ra) - 80002af8: 00108f03 lb t5,1(ra) - 80002afc: 00000e93 li t4,0 - 80002b00: 00300193 li gp,3 - 80002b04: 3bdf1c63 bne t5,t4,80002ebc - -0000000080002b08 : - 80002b08: 00001097 auipc ra,0x1 - 80002b0c: 4f808093 addi ra,ra,1272 # 80004000 - 80002b10: fffff137 lui sp,0xfffff - 80002b14: fa01011b addiw sp,sp,-96 - 80002b18: 00208123 sb sp,2(ra) - 80002b1c: 00209f03 lh t5,2(ra) - 80002b20: fffffeb7 lui t4,0xfffff - 80002b24: fa0e8e9b addiw t4,t4,-96 - 80002b28: 00400193 li gp,4 - 80002b2c: 39df1863 bne t5,t4,80002ebc - -0000000080002b30 : - 80002b30: 00001097 auipc ra,0x1 - 80002b34: 4d008093 addi ra,ra,1232 # 80004000 - 80002b38: 00a00113 li sp,10 - 80002b3c: 002081a3 sb sp,3(ra) - 80002b40: 00308f03 lb t5,3(ra) - 80002b44: 00a00e93 li t4,10 - 80002b48: 00500193 li gp,5 - 80002b4c: 37df1863 bne t5,t4,80002ebc - -0000000080002b50 : - 80002b50: 00001097 auipc ra,0x1 - 80002b54: 4b708093 addi ra,ra,1207 # 80004007 - 80002b58: faa00113 li sp,-86 - 80002b5c: fe208ea3 sb sp,-3(ra) - 80002b60: ffd08f03 lb t5,-3(ra) - 80002b64: faa00e93 li t4,-86 - 80002b68: 00600193 li gp,6 - 80002b6c: 35df1863 bne t5,t4,80002ebc - -0000000080002b70 : - 80002b70: 00001097 auipc ra,0x1 - 80002b74: 49708093 addi ra,ra,1175 # 80004007 - 80002b78: 00000113 li sp,0 - 80002b7c: fe208f23 sb sp,-2(ra) - 80002b80: ffe08f03 lb t5,-2(ra) - 80002b84: 00000e93 li t4,0 - 80002b88: 00700193 li gp,7 - 80002b8c: 33df1863 bne t5,t4,80002ebc - -0000000080002b90 : - 80002b90: 00001097 auipc ra,0x1 - 80002b94: 47708093 addi ra,ra,1143 # 80004007 - 80002b98: fa000113 li sp,-96 - 80002b9c: fe208fa3 sb sp,-1(ra) - 80002ba0: fff08f03 lb t5,-1(ra) - 80002ba4: fa000e93 li t4,-96 - 80002ba8: 00800193 li gp,8 - 80002bac: 31df1863 bne t5,t4,80002ebc - -0000000080002bb0 : - 80002bb0: 00001097 auipc ra,0x1 - 80002bb4: 45708093 addi ra,ra,1111 # 80004007 - 80002bb8: 00a00113 li sp,10 - 80002bbc: 00208023 sb sp,0(ra) - 80002bc0: 00008f03 lb t5,0(ra) - 80002bc4: 00a00e93 li t4,10 - 80002bc8: 00900193 li gp,9 - 80002bcc: 2fdf1863 bne t5,t4,80002ebc - -0000000080002bd0 : - 80002bd0: 00001097 auipc ra,0x1 - 80002bd4: 43808093 addi ra,ra,1080 # 80004008 - 80002bd8: 12345137 lui sp,0x12345 - 80002bdc: 6781011b addiw sp,sp,1656 - 80002be0: fe008213 addi tp,ra,-32 - 80002be4: 02220023 sb sp,32(tp) # 20 <_start-0x7fffffe0> - 80002be8: 00008283 lb t0,0(ra) - 80002bec: 07800e93 li t4,120 - 80002bf0: 00a00193 li gp,10 - 80002bf4: 2dd29463 bne t0,t4,80002ebc - -0000000080002bf8 : - 80002bf8: 00001097 auipc ra,0x1 - 80002bfc: 41008093 addi ra,ra,1040 # 80004008 - 80002c00: 00003137 lui sp,0x3 - 80002c04: 0981011b addiw sp,sp,152 - 80002c08: ffa08093 addi ra,ra,-6 - 80002c0c: 002083a3 sb sp,7(ra) - 80002c10: 00001217 auipc tp,0x1 - 80002c14: 3f920213 addi tp,tp,1017 # 80004009 - 80002c18: 00020283 lb t0,0(tp) # 0 <_start-0x80000000> - 80002c1c: f9800e93 li t4,-104 - 80002c20: 00b00193 li gp,11 - 80002c24: 29d29c63 bne t0,t4,80002ebc - -0000000080002c28 : - 80002c28: 00c00193 li gp,12 - 80002c2c: 00000213 li tp,0 - 80002c30: fdd00093 li ra,-35 - 80002c34: 00001117 auipc sp,0x1 - 80002c38: 3cc10113 addi sp,sp,972 # 80004000 - 80002c3c: 00110023 sb ra,0(sp) - 80002c40: 00010f03 lb t5,0(sp) - 80002c44: fdd00e93 li t4,-35 - 80002c48: 27df1a63 bne t5,t4,80002ebc - 80002c4c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c50: 00200293 li t0,2 - 80002c54: fc521ee3 bne tp,t0,80002c30 - -0000000080002c58 : - 80002c58: 00d00193 li gp,13 - 80002c5c: 00000213 li tp,0 - 80002c60: fcd00093 li ra,-51 - 80002c64: 00001117 auipc sp,0x1 - 80002c68: 39c10113 addi sp,sp,924 # 80004000 - 80002c6c: 00000013 nop - 80002c70: 001100a3 sb ra,1(sp) - 80002c74: 00110f03 lb t5,1(sp) - 80002c78: fcd00e93 li t4,-51 - 80002c7c: 25df1063 bne t5,t4,80002ebc - 80002c80: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c84: 00200293 li t0,2 - 80002c88: fc521ce3 bne tp,t0,80002c60 - -0000000080002c8c : - 80002c8c: 00e00193 li gp,14 - 80002c90: 00000213 li tp,0 - 80002c94: fcc00093 li ra,-52 - 80002c98: 00001117 auipc sp,0x1 - 80002c9c: 36810113 addi sp,sp,872 # 80004000 - 80002ca0: 00000013 nop - 80002ca4: 00000013 nop - 80002ca8: 00110123 sb ra,2(sp) - 80002cac: 00210f03 lb t5,2(sp) - 80002cb0: fcc00e93 li t4,-52 - 80002cb4: 21df1463 bne t5,t4,80002ebc - 80002cb8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cbc: 00200293 li t0,2 - 80002cc0: fc521ae3 bne tp,t0,80002c94 - -0000000080002cc4 : - 80002cc4: 00f00193 li gp,15 - 80002cc8: 00000213 li tp,0 - 80002ccc: fbc00093 li ra,-68 - 80002cd0: 00000013 nop - 80002cd4: 00001117 auipc sp,0x1 - 80002cd8: 32c10113 addi sp,sp,812 # 80004000 - 80002cdc: 001101a3 sb ra,3(sp) - 80002ce0: 00310f03 lb t5,3(sp) - 80002ce4: fbc00e93 li t4,-68 - 80002ce8: 1ddf1a63 bne t5,t4,80002ebc - 80002cec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cf0: 00200293 li t0,2 - 80002cf4: fc521ce3 bne tp,t0,80002ccc - -0000000080002cf8 : - 80002cf8: 01000193 li gp,16 - 80002cfc: 00000213 li tp,0 - 80002d00: fbb00093 li ra,-69 - 80002d04: 00000013 nop - 80002d08: 00001117 auipc sp,0x1 - 80002d0c: 2f810113 addi sp,sp,760 # 80004000 - 80002d10: 00000013 nop - 80002d14: 00110223 sb ra,4(sp) - 80002d18: 00410f03 lb t5,4(sp) - 80002d1c: fbb00e93 li t4,-69 - 80002d20: 19df1e63 bne t5,t4,80002ebc - 80002d24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d28: 00200293 li t0,2 - 80002d2c: fc521ae3 bne tp,t0,80002d00 - -0000000080002d30 : - 80002d30: 01100193 li gp,17 - 80002d34: 00000213 li tp,0 - 80002d38: fab00093 li ra,-85 - 80002d3c: 00000013 nop - 80002d40: 00000013 nop - 80002d44: 00001117 auipc sp,0x1 - 80002d48: 2bc10113 addi sp,sp,700 # 80004000 - 80002d4c: 001102a3 sb ra,5(sp) - 80002d50: 00510f03 lb t5,5(sp) - 80002d54: fab00e93 li t4,-85 - 80002d58: 17df1263 bne t5,t4,80002ebc - 80002d5c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d60: 00200293 li t0,2 - 80002d64: fc521ae3 bne tp,t0,80002d38 - -0000000080002d68 : - 80002d68: 01200193 li gp,18 - 80002d6c: 00000213 li tp,0 - 80002d70: 00001117 auipc sp,0x1 - 80002d74: 29010113 addi sp,sp,656 # 80004000 - 80002d78: 03300093 li ra,51 - 80002d7c: 00110023 sb ra,0(sp) - 80002d80: 00010f03 lb t5,0(sp) - 80002d84: 03300e93 li t4,51 - 80002d88: 13df1a63 bne t5,t4,80002ebc - 80002d8c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d90: 00200293 li t0,2 - 80002d94: fc521ee3 bne tp,t0,80002d70 - -0000000080002d98 : - 80002d98: 01300193 li gp,19 - 80002d9c: 00000213 li tp,0 - 80002da0: 00001117 auipc sp,0x1 - 80002da4: 26010113 addi sp,sp,608 # 80004000 - 80002da8: 02300093 li ra,35 - 80002dac: 00000013 nop - 80002db0: 001100a3 sb ra,1(sp) - 80002db4: 00110f03 lb t5,1(sp) - 80002db8: 02300e93 li t4,35 - 80002dbc: 11df1063 bne t5,t4,80002ebc - 80002dc0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dc4: 00200293 li t0,2 - 80002dc8: fc521ce3 bne tp,t0,80002da0 - -0000000080002dcc : - 80002dcc: 01400193 li gp,20 - 80002dd0: 00000213 li tp,0 - 80002dd4: 00001117 auipc sp,0x1 - 80002dd8: 22c10113 addi sp,sp,556 # 80004000 - 80002ddc: 02200093 li ra,34 - 80002de0: 00000013 nop - 80002de4: 00000013 nop - 80002de8: 00110123 sb ra,2(sp) - 80002dec: 00210f03 lb t5,2(sp) - 80002df0: 02200e93 li t4,34 - 80002df4: 0ddf1463 bne t5,t4,80002ebc - 80002df8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dfc: 00200293 li t0,2 - 80002e00: fc521ae3 bne tp,t0,80002dd4 - -0000000080002e04 : - 80002e04: 01500193 li gp,21 - 80002e08: 00000213 li tp,0 - 80002e0c: 00001117 auipc sp,0x1 - 80002e10: 1f410113 addi sp,sp,500 # 80004000 - 80002e14: 00000013 nop - 80002e18: 01200093 li ra,18 - 80002e1c: 001101a3 sb ra,3(sp) - 80002e20: 00310f03 lb t5,3(sp) - 80002e24: 01200e93 li t4,18 - 80002e28: 09df1a63 bne t5,t4,80002ebc - 80002e2c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e30: 00200293 li t0,2 - 80002e34: fc521ce3 bne tp,t0,80002e0c - -0000000080002e38 : - 80002e38: 01600193 li gp,22 - 80002e3c: 00000213 li tp,0 - 80002e40: 00001117 auipc sp,0x1 - 80002e44: 1c010113 addi sp,sp,448 # 80004000 - 80002e48: 00000013 nop - 80002e4c: 01100093 li ra,17 - 80002e50: 00000013 nop - 80002e54: 00110223 sb ra,4(sp) - 80002e58: 00410f03 lb t5,4(sp) - 80002e5c: 01100e93 li t4,17 - 80002e60: 05df1e63 bne t5,t4,80002ebc - 80002e64: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e68: 00200293 li t0,2 - 80002e6c: fc521ae3 bne tp,t0,80002e40 - -0000000080002e70 : - 80002e70: 01700193 li gp,23 - 80002e74: 00000213 li tp,0 - 80002e78: 00001117 auipc sp,0x1 - 80002e7c: 18810113 addi sp,sp,392 # 80004000 - 80002e80: 00000013 nop - 80002e84: 00000013 nop - 80002e88: 00100093 li ra,1 - 80002e8c: 001102a3 sb ra,5(sp) - 80002e90: 00510f03 lb t5,5(sp) - 80002e94: 00100e93 li t4,1 - 80002e98: 03df1263 bne t5,t4,80002ebc - 80002e9c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ea0: 00200293 li t0,2 - 80002ea4: fc521ae3 bne tp,t0,80002e78 - 80002ea8: 0ef00513 li a0,239 - 80002eac: 00001597 auipc a1,0x1 - 80002eb0: 15458593 addi a1,a1,340 # 80004000 - 80002eb4: 00a581a3 sb a0,3(a1) - 80002eb8: 00301a63 bne zero,gp,80002ecc - -0000000080002ebc : - 80002ebc: 00119513 slli a0,gp,0x1 - 80002ec0: 00050063 beqz a0,80002ec0 - 80002ec4: 00156513 ori a0,a0,1 - 80002ec8: 00000073 ecall - -0000000080002ecc : - 80002ecc: 00100513 li a0,1 - 80002ed0: 00000073 ecall - 80002ed4: c0001073 unimp - -Disassembly of section .data: - -0000000080004000 : - 80004000: jal t6,800026fe - -0000000080004001 : - 80004001: jal t6,800026ff - -0000000080004002 : - 80004002: jal t6,80002700 - -0000000080004003 : - 80004003: jal t6,80002701 - -0000000080004004 : - 80004004: jal t6,80002702 - -0000000080004005 : - 80004005: jal t6,80002703 - -0000000080004006 : - 80004006: jal t6,80002704 - -0000000080004007 : - 80004007: jal t6,80012007 <_end+0x8817> - -0000000080004008 : - 80004008: jal t6,80012008 <_end+0x8818> - -0000000080004009 : - 80004009: ef Address 0x0000000080004009 is out of bounds. - - 8000400d: diff --git a/test/riscv/tests/rv64ui-v-sb.elf b/test/riscv/tests/rv64ui-v-sb.elf deleted file mode 100644 index 72d0ab55..00000000 Binary files a/test/riscv/tests/rv64ui-v-sb.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-sd.dump b/test/riscv/tests/rv64ui-v-sd.dump deleted file mode 100644 index 3fc62989..00000000 --- a/test/riscv/tests/rv64ui-v-sd.dump +++ /dev/null @@ -1,1325 +0,0 @@ - -rv64ui-v-sd: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 0000a117 auipc sp,0xa - 8000001c: 6b810113 addi sp,sp,1720 # 8000a6d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00003617 auipc a2,0x3 - 80002318: cec60613 addi a2,a2,-788 # 80005000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00007797 auipc a5,0x7 - 80002334: 4b878793 addi a5,a5,1208 # 800097e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00007717 auipc a4,0x7 - 80002348: 49c70713 addi a4,a4,1180 # 800097e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00007897 auipc a7,0x7 - 80002354: 48f8bc23 sd a5,1176(a7) # 800097e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00007797 auipc a5,0x7 - 80002384: 07078793 addi a5,a5,112 # 800093f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf6810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00007797 auipc a5,0x7 - 80002448: 3807be23 sd zero,924(a5) # 800097e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: cd068693 addi a3,a3,-816 # 80003128 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: d0460613 addi a2,a2,-764 # 800031b8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: ccc60613 addi a2,a2,-820 # 800031d0 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: c1c68693 addi a3,a3,-996 # 80003170 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: c3868693 addi a3,a3,-968 # 800032a8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: bb860613 addi a2,a2,-1096 # 80003280 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00007d17 auipc s10,0x7 - 80002720: cd4d0d13 addi s10,s10,-812 # 800093f0 - 80002724: 00003b97 auipc s7,0x3 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80005000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00007a17 auipc s4,0x7 - 80002738: 0aca0a13 addi s4,s4,172 # 800097e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00007717 auipc a4,0x7 - 8000274c: 08f73c23 sd a5,152(a4) # 800097e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00007717 auipc a4,0x7 - 800027d4: 00f73823 sd a5,16(a4) # 800097e0 - 800027d8: 00007717 auipc a4,0x7 - 800027dc: 00f73823 sd a5,16(a4) # 800097e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: aec68693 addi a3,a3,-1300 # 800032d8 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: a0c68693 addi a3,a3,-1524 # 80003248 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00001697 auipc a3,0x1 - 80002878: 99c68693 addi a3,a3,-1636 # 80003210 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00003697 auipc a3,0x3 - 800028e0: 72468693 addi a3,a3,1828 # 80006000 - 800028e4: 00004717 auipc a4,0x4 - 800028e8: 71c70713 addi a4,a4,1820 # 80007000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00005797 auipc a5,0x5 - 800028f8: 70c78793 addi a5,a5,1804 # 80008000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00002897 auipc a7,0x2 - 80002914: 6ed8b823 sd a3,1776(a7) # 80005000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00003697 auipc a3,0x3 - 80002920: 6ce6be23 sd a4,1756(a3) # 80005ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00002617 auipc a2,0x2 - 80002938: 6cc60613 addi a2,a2,1740 # 80005000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00005697 auipc a3,0x5 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80007ff8 - 8000294c: 00003717 auipc a4,0x3 - 80002950: 6af73a23 sd a5,1716(a4) # 80006000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00006697 auipc a3,0x6 - 800029c0: 64468693 addi a3,a3,1604 # 80009000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00007617 auipc a2,0x7 - 800029d0: e0f63e23 sd a5,-484(a2) # 800097e8 - 800029d4: 00007797 auipc a5,0x7 - 800029d8: e0e7b623 sd a4,-500(a5) # 800097e0 - 800029dc: 00007317 auipc t1,0x7 - 800029e0: a1430313 addi t1,t1,-1516 # 800093f0 - 800029e4: 00a00793 li a5,10 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00007797 auipc a5,0x7 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800093e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 036b47b7 lui a5,0x36b4 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: c8578793 addi a5,a5,-891 # 36b3c85 <_start-0x7c94c37b> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00001097 auipc ra,0x1 - 80002acc: 53808093 addi ra,ra,1336 # 80004000 - 80002ad0: 00550137 lui sp,0x550 - 80002ad4: 0551011b addiw sp,sp,85 - 80002ad8: 01011113 slli sp,sp,0x10 - 80002adc: 05510113 addi sp,sp,85 # 550055 <_start-0x7faaffab> - 80002ae0: 01111113 slli sp,sp,0x11 - 80002ae4: 0aa10113 addi sp,sp,170 - 80002ae8: 0020b023 sd sp,0(ra) - 80002aec: 0000bf03 ld t5,0(ra) - 80002af0: 00550eb7 lui t4,0x550 - 80002af4: 055e8e9b addiw t4,t4,85 - 80002af8: 010e9e93 slli t4,t4,0x10 - 80002afc: 055e8e93 addi t4,t4,85 # 550055 <_start-0x7faaffab> - 80002b00: 011e9e93 slli t4,t4,0x11 - 80002b04: 0aae8e93 addi t4,t4,170 - 80002b08: 00200193 li gp,2 - 80002b0c: 61df1063 bne t5,t4,8000310c - -0000000080002b10 : - 80002b10: 00001097 auipc ra,0x1 - 80002b14: 4f008093 addi ra,ra,1264 # 80004000 - 80002b18: ffd50137 lui sp,0xffd50 - 80002b1c: 0551011b addiw sp,sp,85 - 80002b20: 01011113 slli sp,sp,0x10 - 80002b24: 05510113 addi sp,sp,85 # ffffffffffd50055 <_end+0xffffffff7fd46865> - 80002b28: 00d11113 slli sp,sp,0xd - 80002b2c: 00b10113 addi sp,sp,11 - 80002b30: 00c11113 slli sp,sp,0xc - 80002b34: a0010113 addi sp,sp,-1536 - 80002b38: 0020b423 sd sp,8(ra) - 80002b3c: 0080bf03 ld t5,8(ra) - 80002b40: ffd50eb7 lui t4,0xffd50 - 80002b44: 055e8e9b addiw t4,t4,85 - 80002b48: 010e9e93 slli t4,t4,0x10 - 80002b4c: 055e8e93 addi t4,t4,85 # ffffffffffd50055 <_end+0xffffffff7fd46865> - 80002b50: 00de9e93 slli t4,t4,0xd - 80002b54: 00be8e93 addi t4,t4,11 - 80002b58: 00ce9e93 slli t4,t4,0xc - 80002b5c: a00e8e93 addi t4,t4,-1536 - 80002b60: 00300193 li gp,3 - 80002b64: 5bdf1463 bne t5,t4,8000310c - -0000000080002b68 : - 80002b68: 00001097 auipc ra,0x1 - 80002b6c: 49808093 addi ra,ra,1176 # 80004000 - 80002b70: 00550137 lui sp,0x550 - 80002b74: 0551011b addiw sp,sp,85 - 80002b78: 00d11113 slli sp,sp,0xd - 80002b7c: 00b10113 addi sp,sp,11 # 55000b <_start-0x7faafff5> - 80002b80: 00c11113 slli sp,sp,0xc - 80002b84: a0110113 addi sp,sp,-1535 - 80002b88: 00c11113 slli sp,sp,0xc - 80002b8c: aa010113 addi sp,sp,-1376 - 80002b90: 0020b823 sd sp,16(ra) - 80002b94: 0100bf03 ld t5,16(ra) - 80002b98: 00550eb7 lui t4,0x550 - 80002b9c: 055e8e9b addiw t4,t4,85 - 80002ba0: 00de9e93 slli t4,t4,0xd - 80002ba4: 00be8e93 addi t4,t4,11 # 55000b <_start-0x7faafff5> - 80002ba8: 00ce9e93 slli t4,t4,0xc - 80002bac: a01e8e93 addi t4,t4,-1535 - 80002bb0: 00ce9e93 slli t4,t4,0xc - 80002bb4: aa0e8e93 addi t4,t4,-1376 - 80002bb8: 00400193 li gp,4 - 80002bbc: 55df1863 bne t5,t4,8000310c - -0000000080002bc0 : - 80002bc0: 00001097 auipc ra,0x1 - 80002bc4: 44008093 addi ra,ra,1088 # 80004000 - 80002bc8: fffd0137 lui sp,0xfffd0 - 80002bcc: 0551011b addiw sp,sp,85 - 80002bd0: 01011113 slli sp,sp,0x10 - 80002bd4: 05510113 addi sp,sp,85 # fffffffffffd0055 <_end+0xffffffff7ffc6865> - 80002bd8: 01011113 slli sp,sp,0x10 - 80002bdc: 05510113 addi sp,sp,85 - 80002be0: 00d11113 slli sp,sp,0xd - 80002be4: 00a10113 addi sp,sp,10 - 80002be8: 0020bc23 sd sp,24(ra) - 80002bec: 0180bf03 ld t5,24(ra) - 80002bf0: fffd0eb7 lui t4,0xfffd0 - 80002bf4: 055e8e9b addiw t4,t4,85 - 80002bf8: 010e9e93 slli t4,t4,0x10 - 80002bfc: 055e8e93 addi t4,t4,85 # fffffffffffd0055 <_end+0xffffffff7ffc6865> - 80002c00: 010e9e93 slli t4,t4,0x10 - 80002c04: 055e8e93 addi t4,t4,85 - 80002c08: 00de9e93 slli t4,t4,0xd - 80002c0c: 00ae8e93 addi t4,t4,10 - 80002c10: 00500193 li gp,5 - 80002c14: 4fdf1c63 bne t5,t4,8000310c - -0000000080002c18 : - 80002c18: 00001097 auipc ra,0x1 - 80002c1c: 42008093 addi ra,ra,1056 # 80004038 - 80002c20: 00550137 lui sp,0x550 - 80002c24: 0551011b addiw sp,sp,85 - 80002c28: 01011113 slli sp,sp,0x10 - 80002c2c: 05510113 addi sp,sp,85 # 550055 <_start-0x7faaffab> - 80002c30: 01111113 slli sp,sp,0x11 - 80002c34: 0aa10113 addi sp,sp,170 - 80002c38: fe20b423 sd sp,-24(ra) - 80002c3c: fe80bf03 ld t5,-24(ra) - 80002c40: 00550eb7 lui t4,0x550 - 80002c44: 055e8e9b addiw t4,t4,85 - 80002c48: 010e9e93 slli t4,t4,0x10 - 80002c4c: 055e8e93 addi t4,t4,85 # 550055 <_start-0x7faaffab> - 80002c50: 011e9e93 slli t4,t4,0x11 - 80002c54: 0aae8e93 addi t4,t4,170 - 80002c58: 00600193 li gp,6 - 80002c5c: 4bdf1863 bne t5,t4,8000310c - -0000000080002c60 : - 80002c60: 00001097 auipc ra,0x1 - 80002c64: 3d808093 addi ra,ra,984 # 80004038 - 80002c68: ffd50137 lui sp,0xffd50 - 80002c6c: 0551011b addiw sp,sp,85 - 80002c70: 01011113 slli sp,sp,0x10 - 80002c74: 05510113 addi sp,sp,85 # ffffffffffd50055 <_end+0xffffffff7fd46865> - 80002c78: 00d11113 slli sp,sp,0xd - 80002c7c: 00b10113 addi sp,sp,11 - 80002c80: 00c11113 slli sp,sp,0xc - 80002c84: a0010113 addi sp,sp,-1536 - 80002c88: fe20b823 sd sp,-16(ra) - 80002c8c: ff00bf03 ld t5,-16(ra) - 80002c90: ffd50eb7 lui t4,0xffd50 - 80002c94: 055e8e9b addiw t4,t4,85 - 80002c98: 010e9e93 slli t4,t4,0x10 - 80002c9c: 055e8e93 addi t4,t4,85 # ffffffffffd50055 <_end+0xffffffff7fd46865> - 80002ca0: 00de9e93 slli t4,t4,0xd - 80002ca4: 00be8e93 addi t4,t4,11 - 80002ca8: 00ce9e93 slli t4,t4,0xc - 80002cac: a00e8e93 addi t4,t4,-1536 - 80002cb0: 00700193 li gp,7 - 80002cb4: 45df1c63 bne t5,t4,8000310c - -0000000080002cb8 : - 80002cb8: 00001097 auipc ra,0x1 - 80002cbc: 38008093 addi ra,ra,896 # 80004038 - 80002cc0: 00550137 lui sp,0x550 - 80002cc4: 0551011b addiw sp,sp,85 - 80002cc8: 00d11113 slli sp,sp,0xd - 80002ccc: 00b10113 addi sp,sp,11 # 55000b <_start-0x7faafff5> - 80002cd0: 00c11113 slli sp,sp,0xc - 80002cd4: a0110113 addi sp,sp,-1535 - 80002cd8: 00c11113 slli sp,sp,0xc - 80002cdc: aa010113 addi sp,sp,-1376 - 80002ce0: fe20bc23 sd sp,-8(ra) - 80002ce4: ff80bf03 ld t5,-8(ra) - 80002ce8: 00550eb7 lui t4,0x550 - 80002cec: 055e8e9b addiw t4,t4,85 - 80002cf0: 00de9e93 slli t4,t4,0xd - 80002cf4: 00be8e93 addi t4,t4,11 # 55000b <_start-0x7faafff5> - 80002cf8: 00ce9e93 slli t4,t4,0xc - 80002cfc: a01e8e93 addi t4,t4,-1535 - 80002d00: 00ce9e93 slli t4,t4,0xc - 80002d04: aa0e8e93 addi t4,t4,-1376 - 80002d08: 00800193 li gp,8 - 80002d0c: 41df1063 bne t5,t4,8000310c - -0000000080002d10 : - 80002d10: 00001097 auipc ra,0x1 - 80002d14: 32808093 addi ra,ra,808 # 80004038 - 80002d18: fffd0137 lui sp,0xfffd0 - 80002d1c: 0551011b addiw sp,sp,85 - 80002d20: 01011113 slli sp,sp,0x10 - 80002d24: 05510113 addi sp,sp,85 # fffffffffffd0055 <_end+0xffffffff7ffc6865> - 80002d28: 01011113 slli sp,sp,0x10 - 80002d2c: 05510113 addi sp,sp,85 - 80002d30: 00d11113 slli sp,sp,0xd - 80002d34: 00a10113 addi sp,sp,10 - 80002d38: 0020b023 sd sp,0(ra) - 80002d3c: 0000bf03 ld t5,0(ra) - 80002d40: fffd0eb7 lui t4,0xfffd0 - 80002d44: 055e8e9b addiw t4,t4,85 - 80002d48: 010e9e93 slli t4,t4,0x10 - 80002d4c: 055e8e93 addi t4,t4,85 # fffffffffffd0055 <_end+0xffffffff7ffc6865> - 80002d50: 010e9e93 slli t4,t4,0x10 - 80002d54: 055e8e93 addi t4,t4,85 - 80002d58: 00de9e93 slli t4,t4,0xd - 80002d5c: 00ae8e93 addi t4,t4,10 - 80002d60: 00900193 li gp,9 - 80002d64: 3bdf1463 bne t5,t4,8000310c - -0000000080002d68 : - 80002d68: 00001097 auipc ra,0x1 - 80002d6c: 2d808093 addi ra,ra,728 # 80004040 - 80002d70: 00247137 lui sp,0x247 - 80002d74: 8ad1011b addiw sp,sp,-1875 - 80002d78: 00e11113 slli sp,sp,0xe - 80002d7c: c0910113 addi sp,sp,-1015 # 246c09 <_start-0x7fdb93f7> - 80002d80: 00d11113 slli sp,sp,0xd - 80002d84: 34510113 addi sp,sp,837 - 80002d88: 00c11113 slli sp,sp,0xc - 80002d8c: 67810113 addi sp,sp,1656 - 80002d90: fe008213 addi tp,ra,-32 - 80002d94: 02223023 sd sp,32(tp) # 20 <_start-0x7fffffe0> - 80002d98: 0000b283 ld t0,0(ra) - 80002d9c: 00247eb7 lui t4,0x247 - 80002da0: 8ade8e9b addiw t4,t4,-1875 - 80002da4: 00ee9e93 slli t4,t4,0xe - 80002da8: c09e8e93 addi t4,t4,-1015 # 246c09 <_start-0x7fdb93f7> - 80002dac: 00de9e93 slli t4,t4,0xd - 80002db0: 345e8e93 addi t4,t4,837 - 80002db4: 00ce9e93 slli t4,t4,0xc - 80002db8: 678e8e93 addi t4,t4,1656 - 80002dbc: 00a00193 li gp,10 - 80002dc0: 35d29663 bne t0,t4,8000310c - -0000000080002dc4 : - 80002dc4: 00001097 auipc ra,0x1 - 80002dc8: 27c08093 addi ra,ra,636 # 80004040 - 80002dcc: 00b04137 lui sp,0xb04 - 80002dd0: 2611011b addiw sp,sp,609 - 80002dd4: 00c11113 slli sp,sp,0xc - 80002dd8: 30b10113 addi sp,sp,779 # b0430b <_start-0x7f4fbcf5> - 80002ddc: 00f11113 slli sp,sp,0xf - 80002de0: 21310113 addi sp,sp,531 - 80002de4: 00c11113 slli sp,sp,0xc - 80002de8: 09810113 addi sp,sp,152 - 80002dec: ffd08093 addi ra,ra,-3 - 80002df0: 0020b5a3 sd sp,11(ra) - 80002df4: 00001217 auipc tp,0x1 - 80002df8: 25420213 addi tp,tp,596 # 80004048 - 80002dfc: 00023283 ld t0,0(tp) # 0 <_start-0x80000000> - 80002e00: 00b04eb7 lui t4,0xb04 - 80002e04: 261e8e9b addiw t4,t4,609 - 80002e08: 00ce9e93 slli t4,t4,0xc - 80002e0c: 30be8e93 addi t4,t4,779 # b0430b <_start-0x7f4fbcf5> - 80002e10: 00fe9e93 slli t4,t4,0xf - 80002e14: 213e8e93 addi t4,t4,531 - 80002e18: 00ce9e93 slli t4,t4,0xc - 80002e1c: 098e8e93 addi t4,t4,152 - 80002e20: 00b00193 li gp,11 - 80002e24: 2fd29463 bne t0,t4,8000310c - -0000000080002e28 : - 80002e28: 00c00193 li gp,12 - 80002e2c: 00000213 li tp,0 - 80002e30: 0abbd0b7 lui ra,0xabbd - 80002e34: cdd0809b addiw ra,ra,-803 - 80002e38: 00001117 auipc sp,0x1 - 80002e3c: 1c810113 addi sp,sp,456 # 80004000 - 80002e40: 00113023 sd ra,0(sp) - 80002e44: 00013f03 ld t5,0(sp) - 80002e48: 0abbdeb7 lui t4,0xabbd - 80002e4c: cdde8e9b addiw t4,t4,-803 - 80002e50: 2bdf1e63 bne t5,t4,8000310c - 80002e54: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e58: 00200293 li t0,2 - 80002e5c: fc521ae3 bne tp,t0,80002e30 - -0000000080002e60 : - 80002e60: 00d00193 li gp,13 - 80002e64: 00000213 li tp,0 - 80002e68: 0aabc0b7 lui ra,0xaabc - 80002e6c: ccd0809b addiw ra,ra,-819 - 80002e70: 00001117 auipc sp,0x1 - 80002e74: 19010113 addi sp,sp,400 # 80004000 - 80002e78: 00000013 nop - 80002e7c: 00113423 sd ra,8(sp) - 80002e80: 00813f03 ld t5,8(sp) - 80002e84: 0aabceb7 lui t4,0xaabc - 80002e88: ccde8e9b addiw t4,t4,-819 - 80002e8c: 29df1063 bne t5,t4,8000310c - 80002e90: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e94: 00200293 li t0,2 - 80002e98: fc5218e3 bne tp,t0,80002e68 - -0000000080002e9c : - 80002e9c: 00e00193 li gp,14 - 80002ea0: 00000213 li tp,0 - 80002ea4: 0daac0b7 lui ra,0xdaac - 80002ea8: bcc0809b addiw ra,ra,-1076 - 80002eac: 00001117 auipc sp,0x1 - 80002eb0: 15410113 addi sp,sp,340 # 80004000 - 80002eb4: 00000013 nop - 80002eb8: 00000013 nop - 80002ebc: 00113823 sd ra,16(sp) - 80002ec0: 01013f03 ld t5,16(sp) - 80002ec4: 0daaceb7 lui t4,0xdaac - 80002ec8: bcce8e9b addiw t4,t4,-1076 - 80002ecc: 25df1063 bne t5,t4,8000310c - 80002ed0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ed4: 00200293 li t0,2 - 80002ed8: fc5216e3 bne tp,t0,80002ea4 - -0000000080002edc : - 80002edc: 00f00193 li gp,15 - 80002ee0: 00000213 li tp,0 - 80002ee4: 0ddab0b7 lui ra,0xddab - 80002ee8: bbc0809b addiw ra,ra,-1092 - 80002eec: 00000013 nop - 80002ef0: 00001117 auipc sp,0x1 - 80002ef4: 11010113 addi sp,sp,272 # 80004000 - 80002ef8: 00113c23 sd ra,24(sp) - 80002efc: 01813f03 ld t5,24(sp) - 80002f00: 0ddabeb7 lui t4,0xddab - 80002f04: bbce8e9b addiw t4,t4,-1092 - 80002f08: 21df1263 bne t5,t4,8000310c - 80002f0c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f10: 00200293 li t0,2 - 80002f14: fc5218e3 bne tp,t0,80002ee4 - -0000000080002f18 : - 80002f18: 01000193 li gp,16 - 80002f1c: 00000213 li tp,0 - 80002f20: 0cddb0b7 lui ra,0xcddb - 80002f24: abb0809b addiw ra,ra,-1349 - 80002f28: 00000013 nop - 80002f2c: 00001117 auipc sp,0x1 - 80002f30: 0d410113 addi sp,sp,212 # 80004000 - 80002f34: 00000013 nop - 80002f38: 02113023 sd ra,32(sp) - 80002f3c: 02013f03 ld t5,32(sp) - 80002f40: 0cddbeb7 lui t4,0xcddb - 80002f44: abbe8e9b addiw t4,t4,-1349 - 80002f48: 1ddf1263 bne t5,t4,8000310c - 80002f4c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f50: 00200293 li t0,2 - 80002f54: fc5216e3 bne tp,t0,80002f20 - -0000000080002f58 : - 80002f58: 01100193 li gp,17 - 80002f5c: 00000213 li tp,0 - 80002f60: 0ccde0b7 lui ra,0xccde - 80002f64: aab0809b addiw ra,ra,-1365 - 80002f68: 00000013 nop - 80002f6c: 00000013 nop - 80002f70: 00001117 auipc sp,0x1 - 80002f74: 09010113 addi sp,sp,144 # 80004000 - 80002f78: 02113423 sd ra,40(sp) - 80002f7c: 02813f03 ld t5,40(sp) - 80002f80: 0ccdeeb7 lui t4,0xccde - 80002f84: aabe8e9b addiw t4,t4,-1365 - 80002f88: 19df1263 bne t5,t4,8000310c - 80002f8c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f90: 00200293 li t0,2 - 80002f94: fc5216e3 bne tp,t0,80002f60 - -0000000080002f98 : - 80002f98: 01200193 li gp,18 - 80002f9c: 00000213 li tp,0 - 80002fa0: 00001117 auipc sp,0x1 - 80002fa4: 06010113 addi sp,sp,96 # 80004000 - 80002fa8: 001120b7 lui ra,0x112 - 80002fac: 2330809b addiw ra,ra,563 - 80002fb0: 00113023 sd ra,0(sp) - 80002fb4: 00013f03 ld t5,0(sp) - 80002fb8: 00112eb7 lui t4,0x112 - 80002fbc: 233e8e9b addiw t4,t4,563 - 80002fc0: 15df1663 bne t5,t4,8000310c - 80002fc4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002fc8: 00200293 li t0,2 - 80002fcc: fc521ae3 bne tp,t0,80002fa0 - -0000000080002fd0 : - 80002fd0: 01300193 li gp,19 - 80002fd4: 00000213 li tp,0 - 80002fd8: 00001117 auipc sp,0x1 - 80002fdc: 02810113 addi sp,sp,40 # 80004000 - 80002fe0: 300110b7 lui ra,0x30011 - 80002fe4: 2230809b addiw ra,ra,547 - 80002fe8: 00000013 nop - 80002fec: 00113423 sd ra,8(sp) - 80002ff0: 00813f03 ld t5,8(sp) - 80002ff4: 30011eb7 lui t4,0x30011 - 80002ff8: 223e8e9b addiw t4,t4,547 - 80002ffc: 11df1863 bne t5,t4,8000310c - 80003000: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80003004: 00200293 li t0,2 - 80003008: fc5218e3 bne tp,t0,80002fd8 - -000000008000300c : - 8000300c: 01400193 li gp,20 - 80003010: 00000213 li tp,0 - 80003014: 00001117 auipc sp,0x1 - 80003018: fec10113 addi sp,sp,-20 # 80004000 - 8000301c: 330010b7 lui ra,0x33001 - 80003020: 1220809b addiw ra,ra,290 - 80003024: 00000013 nop - 80003028: 00000013 nop - 8000302c: 00113823 sd ra,16(sp) - 80003030: 01013f03 ld t5,16(sp) - 80003034: 33001eb7 lui t4,0x33001 - 80003038: 122e8e9b addiw t4,t4,290 - 8000303c: 0ddf1863 bne t5,t4,8000310c - 80003040: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80003044: 00200293 li t0,2 - 80003048: fc5216e3 bne tp,t0,80003014 - -000000008000304c : - 8000304c: 01500193 li gp,21 - 80003050: 00000213 li tp,0 - 80003054: 00001117 auipc sp,0x1 - 80003058: fac10113 addi sp,sp,-84 # 80004000 - 8000305c: 00000013 nop - 80003060: 233000b7 lui ra,0x23300 - 80003064: 1120809b addiw ra,ra,274 - 80003068: 00113c23 sd ra,24(sp) - 8000306c: 01813f03 ld t5,24(sp) - 80003070: 23300eb7 lui t4,0x23300 - 80003074: 112e8e9b addiw t4,t4,274 - 80003078: 09df1a63 bne t5,t4,8000310c - 8000307c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80003080: 00200293 li t0,2 - 80003084: fc5218e3 bne tp,t0,80003054 - -0000000080003088 : - 80003088: 01600193 li gp,22 - 8000308c: 00000213 li tp,0 - 80003090: 00001117 auipc sp,0x1 - 80003094: f7010113 addi sp,sp,-144 # 80004000 - 80003098: 00000013 nop - 8000309c: 223300b7 lui ra,0x22330 - 800030a0: 0110809b addiw ra,ra,17 - 800030a4: 00000013 nop - 800030a8: 02113023 sd ra,32(sp) - 800030ac: 02013f03 ld t5,32(sp) - 800030b0: 22330eb7 lui t4,0x22330 - 800030b4: 011e8e9b addiw t4,t4,17 - 800030b8: 05df1a63 bne t5,t4,8000310c - 800030bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800030c0: 00200293 li t0,2 - 800030c4: fc5216e3 bne tp,t0,80003090 - -00000000800030c8 : - 800030c8: 01700193 li gp,23 - 800030cc: 00000213 li tp,0 - 800030d0: 00001117 auipc sp,0x1 - 800030d4: f3010113 addi sp,sp,-208 # 80004000 - 800030d8: 00000013 nop - 800030dc: 00000013 nop - 800030e0: 122330b7 lui ra,0x12233 - 800030e4: 0010809b addiw ra,ra,1 - 800030e8: 02113423 sd ra,40(sp) - 800030ec: 02813f03 ld t5,40(sp) - 800030f0: 12233eb7 lui t4,0x12233 - 800030f4: 001e8e9b addiw t4,t4,1 - 800030f8: 01df1a63 bne t5,t4,8000310c - 800030fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80003100: 00200293 li t0,2 - 80003104: fc5216e3 bne tp,t0,800030d0 - 80003108: 00301a63 bne zero,gp,8000311c - -000000008000310c : - 8000310c: 00119513 slli a0,gp,0x1 - 80003110: 00050063 beqz a0,80003110 - 80003114: 00156513 ori a0,a0,1 - 80003118: 00000073 ecall - -000000008000311c : - 8000311c: 00100513 li a0,1 - 80003120: 00000073 ecall - 80003124: c0001073 unimp - -Disassembly of section .data: - -0000000080004000 : - 80004000: deadbeef jal t4,7ffdf5ea <_start-0x20a16> - 80004004: deadbeef jal t4,7ffdf5ee <_start-0x20a12> - -0000000080004008 : - 80004008: deadbeef jal t4,7ffdf5f2 <_start-0x20a0e> - 8000400c: deadbeef jal t4,7ffdf5f6 <_start-0x20a0a> - -0000000080004010 : - 80004010: deadbeef jal t4,7ffdf5fa <_start-0x20a06> - 80004014: deadbeef jal t4,7ffdf5fe <_start-0x20a02> - -0000000080004018 : - 80004018: deadbeef jal t4,7ffdf602 <_start-0x209fe> - 8000401c: deadbeef jal t4,7ffdf606 <_start-0x209fa> - -0000000080004020 : - 80004020: deadbeef jal t4,7ffdf60a <_start-0x209f6> - 80004024: deadbeef jal t4,7ffdf60e <_start-0x209f2> - -0000000080004028 : - 80004028: deadbeef jal t4,7ffdf612 <_start-0x209ee> - 8000402c: deadbeef jal t4,7ffdf616 <_start-0x209ea> - -0000000080004030 : - 80004030: deadbeef jal t4,7ffdf61a <_start-0x209e6> - 80004034: deadbeef jal t4,7ffdf61e <_start-0x209e2> - -0000000080004038 : - 80004038: deadbeef jal t4,7ffdf622 <_start-0x209de> - 8000403c: deadbeef jal t4,7ffdf626 <_start-0x209da> - -0000000080004040 : - 80004040: deadbeef jal t4,7ffdf62a <_start-0x209d6> - 80004044: deadbeef jal t4,7ffdf62e <_start-0x209d2> - -0000000080004048 : - 80004048: deadbeef jal t4,7ffdf632 <_start-0x209ce> - 8000404c: deadbeef jal t4,7ffdf636 <_start-0x209ca> diff --git a/test/riscv/tests/rv64ui-v-sd.elf b/test/riscv/tests/rv64ui-v-sd.elf deleted file mode 100644 index b1660db0..00000000 Binary files a/test/riscv/tests/rv64ui-v-sd.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-sh.dump b/test/riscv/tests/rv64ui-v-sh.dump deleted file mode 100644 index 62862d9e..00000000 --- a/test/riscv/tests/rv64ui-v-sh.dump +++ /dev/null @@ -1,1200 +0,0 @@ - -rv64ui-v-sh: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 0000a117 auipc sp,0xa - 8000001c: 6b810113 addi sp,sp,1720 # 8000a6d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00003617 auipc a2,0x3 - 80002318: cec60613 addi a2,a2,-788 # 80005000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00007797 auipc a5,0x7 - 80002334: 4b878793 addi a5,a5,1208 # 800097e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00007717 auipc a4,0x7 - 80002348: 49c70713 addi a4,a4,1180 # 800097e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00007897 auipc a7,0x7 - 80002354: 48f8bc23 sd a5,1176(a7) # 800097e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00007797 auipc a5,0x7 - 80002384: 07078793 addi a5,a5,112 # 800093f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf6810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00007797 auipc a5,0x7 - 80002448: 3807be23 sd zero,924(a5) # 800097e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: b0868693 addi a3,a3,-1272 # 80002f60 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: b3c60613 addi a2,a2,-1220 # 80002ff0 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: b0460613 addi a2,a2,-1276 # 80003008 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: a5468693 addi a3,a3,-1452 # 80002fa8 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: a7068693 addi a3,a3,-1424 # 800030e0 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 9f060613 addi a2,a2,-1552 # 800030b8 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00007d17 auipc s10,0x7 - 80002720: cd4d0d13 addi s10,s10,-812 # 800093f0 - 80002724: 00003b97 auipc s7,0x3 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80005000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00007a17 auipc s4,0x7 - 80002738: 0aca0a13 addi s4,s4,172 # 800097e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00007717 auipc a4,0x7 - 8000274c: 08f73c23 sd a5,152(a4) # 800097e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00007717 auipc a4,0x7 - 800027d4: 00f73823 sd a5,16(a4) # 800097e0 - 800027d8: 00007717 auipc a4,0x7 - 800027dc: 00f73823 sd a5,16(a4) # 800097e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: 92468693 addi a3,a3,-1756 # 80003110 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 84468693 addi a3,a3,-1980 # 80003080 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 7d468693 addi a3,a3,2004 # 80003048 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00003697 auipc a3,0x3 - 800028e0: 72468693 addi a3,a3,1828 # 80006000 - 800028e4: 00004717 auipc a4,0x4 - 800028e8: 71c70713 addi a4,a4,1820 # 80007000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00005797 auipc a5,0x5 - 800028f8: 70c78793 addi a5,a5,1804 # 80008000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00002897 auipc a7,0x2 - 80002914: 6ed8b823 sd a3,1776(a7) # 80005000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00003697 auipc a3,0x3 - 80002920: 6ce6be23 sd a4,1756(a3) # 80005ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00002617 auipc a2,0x2 - 80002938: 6cc60613 addi a2,a2,1740 # 80005000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00005697 auipc a3,0x5 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80007ff8 - 8000294c: 00003717 auipc a4,0x3 - 80002950: 6af73a23 sd a5,1716(a4) # 80006000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00006697 auipc a3,0x6 - 800029c0: 64468693 addi a3,a3,1604 # 80009000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00007617 auipc a2,0x7 - 800029d0: e0f63e23 sd a5,-484(a2) # 800097e8 - 800029d4: 00007797 auipc a5,0x7 - 800029d8: e0e7b623 sd a4,-500(a5) # 800097e0 - 800029dc: 00007317 auipc t1,0x7 - 800029e0: a1430313 addi t1,t1,-1516 # 800093f0 - 800029e4: 03300793 li a5,51 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00007797 auipc a5,0x7 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800093e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0adbd7b7 lui a5,0xadbd - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 91078793 addi a5,a5,-1776 # adbc910 <_start-0x752436f0> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00001097 auipc ra,0x1 - 80002acc: 53808093 addi ra,ra,1336 # 80004000 - 80002ad0: 0aa00113 li sp,170 - 80002ad4: 00209023 sh sp,0(ra) - 80002ad8: 00009f03 lh t5,0(ra) - 80002adc: 0aa00e93 li t4,170 - 80002ae0: 00200193 li gp,2 - 80002ae4: 45df1e63 bne t5,t4,80002f40 - -0000000080002ae8 : - 80002ae8: 00001097 auipc ra,0x1 - 80002aec: 51808093 addi ra,ra,1304 # 80004000 - 80002af0: ffffb137 lui sp,0xffffb - 80002af4: a001011b addiw sp,sp,-1536 - 80002af8: 00209123 sh sp,2(ra) - 80002afc: 00209f03 lh t5,2(ra) - 80002b00: ffffbeb7 lui t4,0xffffb - 80002b04: a00e8e9b addiw t4,t4,-1536 - 80002b08: 00300193 li gp,3 - 80002b0c: 43df1a63 bne t5,t4,80002f40 - -0000000080002b10 : - 80002b10: 00001097 auipc ra,0x1 - 80002b14: 4f008093 addi ra,ra,1264 # 80004000 - 80002b18: beef1137 lui sp,0xbeef1 - 80002b1c: aa01011b addiw sp,sp,-1376 - 80002b20: 00209223 sh sp,4(ra) - 80002b24: 0040af03 lw t5,4(ra) - 80002b28: beef1eb7 lui t4,0xbeef1 - 80002b2c: aa0e8e9b addiw t4,t4,-1376 - 80002b30: 00400193 li gp,4 - 80002b34: 41df1663 bne t5,t4,80002f40 - -0000000080002b38 : - 80002b38: 00001097 auipc ra,0x1 - 80002b3c: 4c808093 addi ra,ra,1224 # 80004000 - 80002b40: ffffa137 lui sp,0xffffa - 80002b44: 00a1011b addiw sp,sp,10 - 80002b48: 00209323 sh sp,6(ra) - 80002b4c: 00609f03 lh t5,6(ra) - 80002b50: ffffaeb7 lui t4,0xffffa - 80002b54: 00ae8e9b addiw t4,t4,10 - 80002b58: 00500193 li gp,5 - 80002b5c: 3fdf1263 bne t5,t4,80002f40 - -0000000080002b60 : - 80002b60: 00001097 auipc ra,0x1 - 80002b64: 4ae08093 addi ra,ra,1198 # 8000400e - 80002b68: 0aa00113 li sp,170 - 80002b6c: fe209d23 sh sp,-6(ra) - 80002b70: ffa09f03 lh t5,-6(ra) - 80002b74: 0aa00e93 li t4,170 - 80002b78: 00600193 li gp,6 - 80002b7c: 3ddf1263 bne t5,t4,80002f40 - -0000000080002b80 : - 80002b80: 00001097 auipc ra,0x1 - 80002b84: 48e08093 addi ra,ra,1166 # 8000400e - 80002b88: ffffb137 lui sp,0xffffb - 80002b8c: a001011b addiw sp,sp,-1536 - 80002b90: fe209e23 sh sp,-4(ra) - 80002b94: ffc09f03 lh t5,-4(ra) - 80002b98: ffffbeb7 lui t4,0xffffb - 80002b9c: a00e8e9b addiw t4,t4,-1536 - 80002ba0: 00700193 li gp,7 - 80002ba4: 39df1e63 bne t5,t4,80002f40 - -0000000080002ba8 : - 80002ba8: 00001097 auipc ra,0x1 - 80002bac: 46608093 addi ra,ra,1126 # 8000400e - 80002bb0: 00001137 lui sp,0x1 - 80002bb4: aa01011b addiw sp,sp,-1376 - 80002bb8: fe209f23 sh sp,-2(ra) - 80002bbc: ffe09f03 lh t5,-2(ra) - 80002bc0: 00001eb7 lui t4,0x1 - 80002bc4: aa0e8e9b addiw t4,t4,-1376 - 80002bc8: 00800193 li gp,8 - 80002bcc: 37df1a63 bne t5,t4,80002f40 - -0000000080002bd0 : - 80002bd0: 00001097 auipc ra,0x1 - 80002bd4: 43e08093 addi ra,ra,1086 # 8000400e - 80002bd8: ffffa137 lui sp,0xffffa - 80002bdc: 00a1011b addiw sp,sp,10 - 80002be0: 00209023 sh sp,0(ra) - 80002be4: 00009f03 lh t5,0(ra) - 80002be8: ffffaeb7 lui t4,0xffffa - 80002bec: 00ae8e9b addiw t4,t4,10 - 80002bf0: 00900193 li gp,9 - 80002bf4: 35df1663 bne t5,t4,80002f40 - -0000000080002bf8 : - 80002bf8: 00001097 auipc ra,0x1 - 80002bfc: 41808093 addi ra,ra,1048 # 80004010 - 80002c00: 12345137 lui sp,0x12345 - 80002c04: 6781011b addiw sp,sp,1656 - 80002c08: fe008213 addi tp,ra,-32 - 80002c0c: 02221023 sh sp,32(tp) # 20 <_start-0x7fffffe0> - 80002c10: 00009283 lh t0,0(ra) - 80002c14: 00005eb7 lui t4,0x5 - 80002c18: 678e8e9b addiw t4,t4,1656 - 80002c1c: 00a00193 li gp,10 - 80002c20: 33d29063 bne t0,t4,80002f40 - -0000000080002c24 : - 80002c24: 00001097 auipc ra,0x1 - 80002c28: 3ec08093 addi ra,ra,1004 # 80004010 - 80002c2c: 00003137 lui sp,0x3 - 80002c30: 0981011b addiw sp,sp,152 - 80002c34: ffb08093 addi ra,ra,-5 - 80002c38: 002093a3 sh sp,7(ra) - 80002c3c: 00001217 auipc tp,0x1 - 80002c40: 3d620213 addi tp,tp,982 # 80004012 - 80002c44: 00021283 lh t0,0(tp) # 0 <_start-0x80000000> - 80002c48: 00003eb7 lui t4,0x3 - 80002c4c: 098e8e9b addiw t4,t4,152 - 80002c50: 00b00193 li gp,11 - 80002c54: 2fd29663 bne t0,t4,80002f40 - -0000000080002c58 : - 80002c58: 00c00193 li gp,12 - 80002c5c: 00000213 li tp,0 - 80002c60: ffffd0b7 lui ra,0xffffd - 80002c64: cdd0809b addiw ra,ra,-803 - 80002c68: 00001117 auipc sp,0x1 - 80002c6c: 39810113 addi sp,sp,920 # 80004000 - 80002c70: 00111023 sh ra,0(sp) - 80002c74: 00011f03 lh t5,0(sp) - 80002c78: ffffdeb7 lui t4,0xffffd - 80002c7c: cdde8e9b addiw t4,t4,-803 - 80002c80: 2ddf1063 bne t5,t4,80002f40 - 80002c84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c88: 00200293 li t0,2 - 80002c8c: fc521ae3 bne tp,t0,80002c60 - -0000000080002c90 : - 80002c90: 00d00193 li gp,13 - 80002c94: 00000213 li tp,0 - 80002c98: ffffc0b7 lui ra,0xffffc - 80002c9c: ccd0809b addiw ra,ra,-819 - 80002ca0: 00001117 auipc sp,0x1 - 80002ca4: 36010113 addi sp,sp,864 # 80004000 - 80002ca8: 00000013 nop - 80002cac: 00111123 sh ra,2(sp) - 80002cb0: 00211f03 lh t5,2(sp) - 80002cb4: ffffceb7 lui t4,0xffffc - 80002cb8: ccde8e9b addiw t4,t4,-819 - 80002cbc: 29df1263 bne t5,t4,80002f40 - 80002cc0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cc4: 00200293 li t0,2 - 80002cc8: fc5218e3 bne tp,t0,80002c98 - -0000000080002ccc : - 80002ccc: 00e00193 li gp,14 - 80002cd0: 00000213 li tp,0 - 80002cd4: ffffc0b7 lui ra,0xffffc - 80002cd8: bcc0809b addiw ra,ra,-1076 - 80002cdc: 00001117 auipc sp,0x1 - 80002ce0: 32410113 addi sp,sp,804 # 80004000 - 80002ce4: 00000013 nop - 80002ce8: 00000013 nop - 80002cec: 00111223 sh ra,4(sp) - 80002cf0: 00411f03 lh t5,4(sp) - 80002cf4: ffffceb7 lui t4,0xffffc - 80002cf8: bcce8e9b addiw t4,t4,-1076 - 80002cfc: 25df1263 bne t5,t4,80002f40 - 80002d00: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d04: 00200293 li t0,2 - 80002d08: fc5216e3 bne tp,t0,80002cd4 - -0000000080002d0c : - 80002d0c: 00f00193 li gp,15 - 80002d10: 00000213 li tp,0 - 80002d14: ffffb0b7 lui ra,0xffffb - 80002d18: bbc0809b addiw ra,ra,-1092 - 80002d1c: 00000013 nop - 80002d20: 00001117 auipc sp,0x1 - 80002d24: 2e010113 addi sp,sp,736 # 80004000 - 80002d28: 00111323 sh ra,6(sp) - 80002d2c: 00611f03 lh t5,6(sp) - 80002d30: ffffbeb7 lui t4,0xffffb - 80002d34: bbce8e9b addiw t4,t4,-1092 - 80002d38: 21df1463 bne t5,t4,80002f40 - 80002d3c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d40: 00200293 li t0,2 - 80002d44: fc5218e3 bne tp,t0,80002d14 - -0000000080002d48 : - 80002d48: 01000193 li gp,16 - 80002d4c: 00000213 li tp,0 - 80002d50: ffffb0b7 lui ra,0xffffb - 80002d54: abb0809b addiw ra,ra,-1349 - 80002d58: 00000013 nop - 80002d5c: 00001117 auipc sp,0x1 - 80002d60: 2a410113 addi sp,sp,676 # 80004000 - 80002d64: 00000013 nop - 80002d68: 00111423 sh ra,8(sp) - 80002d6c: 00811f03 lh t5,8(sp) - 80002d70: ffffbeb7 lui t4,0xffffb - 80002d74: abbe8e9b addiw t4,t4,-1349 - 80002d78: 1ddf1463 bne t5,t4,80002f40 - 80002d7c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d80: 00200293 li t0,2 - 80002d84: fc5216e3 bne tp,t0,80002d50 - -0000000080002d88 : - 80002d88: 01100193 li gp,17 - 80002d8c: 00000213 li tp,0 - 80002d90: ffffe0b7 lui ra,0xffffe - 80002d94: aab0809b addiw ra,ra,-1365 - 80002d98: 00000013 nop - 80002d9c: 00000013 nop - 80002da0: 00001117 auipc sp,0x1 - 80002da4: 26010113 addi sp,sp,608 # 80004000 - 80002da8: 00111523 sh ra,10(sp) - 80002dac: 00a11f03 lh t5,10(sp) - 80002db0: ffffeeb7 lui t4,0xffffe - 80002db4: aabe8e9b addiw t4,t4,-1365 - 80002db8: 19df1463 bne t5,t4,80002f40 - 80002dbc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dc0: 00200293 li t0,2 - 80002dc4: fc5216e3 bne tp,t0,80002d90 - -0000000080002dc8 : - 80002dc8: 01200193 li gp,18 - 80002dcc: 00000213 li tp,0 - 80002dd0: 00001117 auipc sp,0x1 - 80002dd4: 23010113 addi sp,sp,560 # 80004000 - 80002dd8: 000020b7 lui ra,0x2 - 80002ddc: 2330809b addiw ra,ra,563 - 80002de0: 00111023 sh ra,0(sp) - 80002de4: 00011f03 lh t5,0(sp) - 80002de8: 00002eb7 lui t4,0x2 - 80002dec: 233e8e9b addiw t4,t4,563 - 80002df0: 15df1863 bne t5,t4,80002f40 - 80002df4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002df8: 00200293 li t0,2 - 80002dfc: fc521ae3 bne tp,t0,80002dd0 - -0000000080002e00 : - 80002e00: 01300193 li gp,19 - 80002e04: 00000213 li tp,0 - 80002e08: 00001117 auipc sp,0x1 - 80002e0c: 1f810113 addi sp,sp,504 # 80004000 - 80002e10: 000010b7 lui ra,0x1 - 80002e14: 2230809b addiw ra,ra,547 - 80002e18: 00000013 nop - 80002e1c: 00111123 sh ra,2(sp) - 80002e20: 00211f03 lh t5,2(sp) - 80002e24: 00001eb7 lui t4,0x1 - 80002e28: 223e8e9b addiw t4,t4,547 - 80002e2c: 11df1a63 bne t5,t4,80002f40 - 80002e30: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e34: 00200293 li t0,2 - 80002e38: fc5218e3 bne tp,t0,80002e08 - -0000000080002e3c : - 80002e3c: 01400193 li gp,20 - 80002e40: 00000213 li tp,0 - 80002e44: 00001117 auipc sp,0x1 - 80002e48: 1bc10113 addi sp,sp,444 # 80004000 - 80002e4c: 000010b7 lui ra,0x1 - 80002e50: 1220809b addiw ra,ra,290 - 80002e54: 00000013 nop - 80002e58: 00000013 nop - 80002e5c: 00111223 sh ra,4(sp) - 80002e60: 00411f03 lh t5,4(sp) - 80002e64: 00001eb7 lui t4,0x1 - 80002e68: 122e8e9b addiw t4,t4,290 - 80002e6c: 0ddf1a63 bne t5,t4,80002f40 - 80002e70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e74: 00200293 li t0,2 - 80002e78: fc5216e3 bne tp,t0,80002e44 - -0000000080002e7c : - 80002e7c: 01500193 li gp,21 - 80002e80: 00000213 li tp,0 - 80002e84: 00001117 auipc sp,0x1 - 80002e88: 17c10113 addi sp,sp,380 # 80004000 - 80002e8c: 00000013 nop - 80002e90: 11200093 li ra,274 - 80002e94: 00111323 sh ra,6(sp) - 80002e98: 00611f03 lh t5,6(sp) - 80002e9c: 11200e93 li t4,274 - 80002ea0: 0bdf1063 bne t5,t4,80002f40 - 80002ea4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ea8: 00200293 li t0,2 - 80002eac: fc521ce3 bne tp,t0,80002e84 - -0000000080002eb0 : - 80002eb0: 01600193 li gp,22 - 80002eb4: 00000213 li tp,0 - 80002eb8: 00001117 auipc sp,0x1 - 80002ebc: 14810113 addi sp,sp,328 # 80004000 - 80002ec0: 00000013 nop - 80002ec4: 01100093 li ra,17 - 80002ec8: 00000013 nop - 80002ecc: 00111423 sh ra,8(sp) - 80002ed0: 00811f03 lh t5,8(sp) - 80002ed4: 01100e93 li t4,17 - 80002ed8: 07df1463 bne t5,t4,80002f40 - 80002edc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ee0: 00200293 li t0,2 - 80002ee4: fc521ae3 bne tp,t0,80002eb8 - -0000000080002ee8 : - 80002ee8: 01700193 li gp,23 - 80002eec: 00000213 li tp,0 - 80002ef0: 00001117 auipc sp,0x1 - 80002ef4: 11010113 addi sp,sp,272 # 80004000 - 80002ef8: 00000013 nop - 80002efc: 00000013 nop - 80002f00: 000030b7 lui ra,0x3 - 80002f04: 0010809b addiw ra,ra,1 - 80002f08: 00111523 sh ra,10(sp) - 80002f0c: 00a11f03 lh t5,10(sp) - 80002f10: 00003eb7 lui t4,0x3 - 80002f14: 001e8e9b addiw t4,t4,1 - 80002f18: 03df1463 bne t5,t4,80002f40 - 80002f1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f20: 00200293 li t0,2 - 80002f24: fc5216e3 bne tp,t0,80002ef0 - 80002f28: 0000c537 lui a0,0xc - 80002f2c: eef5051b addiw a0,a0,-273 - 80002f30: 00001597 auipc a1,0x1 - 80002f34: 0d058593 addi a1,a1,208 # 80004000 - 80002f38: 00a59323 sh a0,6(a1) - 80002f3c: 00301a63 bne zero,gp,80002f50 - -0000000080002f40 : - 80002f40: 00119513 slli a0,gp,0x1 - 80002f44: 00050063 beqz a0,80002f44 - 80002f48: 00156513 ori a0,a0,1 - 80002f4c: 00000073 ecall - -0000000080002f50 : - 80002f50: 00100513 li a0,1 - 80002f54: 00000073 ecall - 80002f58: c0001073 unimp - -Disassembly of section .data: - -0000000080004000 : - 80004000: jal t4,7ffff3ee <_start-0xc12> - -0000000080004002 : - 80004002: jal t4,7ffff3f0 <_start-0xc10> - -0000000080004004 : - 80004004: jal t4,7ffff3f2 <_start-0xc0e> - -0000000080004006 : - 80004006: jal t4,7ffff3f4 <_start-0xc0c> - -0000000080004008 : - 80004008: jal t4,7ffff3f6 <_start-0xc0a> - -000000008000400a : - 8000400a: jal t4,7ffff3f8 <_start-0xc08> - -000000008000400c : - 8000400c: jal t4,7ffff3fa <_start-0xc06> - -000000008000400e : - 8000400e: jal t4,7ffff3fc <_start-0xc04> - -0000000080004010 : - 80004010: jal t4,7ffff3fe <_start-0xc02> - -0000000080004012 : - 80004012: jal t4,8000f012 <_end+0x5822> diff --git a/test/riscv/tests/rv64ui-v-sh.elf b/test/riscv/tests/rv64ui-v-sh.elf deleted file mode 100644 index a3a67da2..00000000 Binary files a/test/riscv/tests/rv64ui-v-sh.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-simple.dump b/test/riscv/tests/rv64ui-v-simple.dump deleted file mode 100644 index 0c3cc1cc..00000000 --- a/test/riscv/tests/rv64ui-v-simple.dump +++ /dev/null @@ -1,832 +0,0 @@ - -rv64ui-v-simple: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 68068693 addi a3,a3,1664 # 80002ad8 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 6b460613 addi a2,a2,1716 # 80002b68 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 67c60613 addi a2,a2,1660 # 80002b80 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 5cc68693 addi a3,a3,1484 # 80002b20 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 5e868693 addi a3,a3,1512 # 80002c58 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 56860613 addi a2,a2,1384 # 80002c30 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 49c68693 addi a3,a3,1180 # 80002c88 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 3bc68693 addi a3,a3,956 # 80002bf8 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 34c68693 addi a3,a3,844 # 80002bc0 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 03000793 li a5,48 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 07a657b7 lui a5,0x7a65 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: bab78793 addi a5,a5,-1109 # 7a64bab <_start-0x7859b455> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00100513 li a0,1 - 80002acc: 00000073 ecall - 80002ad0: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-simple.elf b/test/riscv/tests/rv64ui-v-simple.elf deleted file mode 100644 index 04140b00..00000000 Binary files a/test/riscv/tests/rv64ui-v-simple.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-sll.dump b/test/riscv/tests/rv64ui-v-sll.dump deleted file mode 100644 index 6b4b00b0..00000000 --- a/test/riscv/tests/rv64ui-v-sll.dump +++ /dev/null @@ -1,1315 +0,0 @@ - -rv64ui-v-sll: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: c9868693 addi a3,a3,-872 # 800030f0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: ccc60613 addi a2,a2,-820 # 80003180 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: c9460613 addi a2,a2,-876 # 80003198 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: be468693 addi a3,a3,-1052 # 80003138 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: c0068693 addi a3,a3,-1024 # 80003270 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: b8060613 addi a2,a2,-1152 # 80003248 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: ab468693 addi a3,a3,-1356 # 800032a0 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 9d468693 addi a3,a3,-1580 # 80003210 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00001697 auipc a3,0x1 - 80002878: 96468693 addi a3,a3,-1692 # 800031d8 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 02b00793 li a5,43 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 063c27b7 lui a5,0x63c2 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 9ad78793 addi a5,a5,-1619 # 63c19ad <_start-0x79c3e653> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00100093 li ra,1 - 80002acc: 00000113 li sp,0 - 80002ad0: 00209f33 sll t5,ra,sp - 80002ad4: 00100e93 li t4,1 - 80002ad8: 00200193 li gp,2 - 80002adc: 5fdf1c63 bne t5,t4,800030d4 - -0000000080002ae0 : - 80002ae0: 00100093 li ra,1 - 80002ae4: 00100113 li sp,1 - 80002ae8: 00209f33 sll t5,ra,sp - 80002aec: 00200e93 li t4,2 - 80002af0: 00300193 li gp,3 - 80002af4: 5fdf1063 bne t5,t4,800030d4 - -0000000080002af8 : - 80002af8: 00100093 li ra,1 - 80002afc: 00700113 li sp,7 - 80002b00: 00209f33 sll t5,ra,sp - 80002b04: 08000e93 li t4,128 - 80002b08: 00400193 li gp,4 - 80002b0c: 5ddf1463 bne t5,t4,800030d4 - -0000000080002b10 : - 80002b10: 00100093 li ra,1 - 80002b14: 00e00113 li sp,14 - 80002b18: 00209f33 sll t5,ra,sp - 80002b1c: 00004eb7 lui t4,0x4 - 80002b20: 00500193 li gp,5 - 80002b24: 5bdf1863 bne t5,t4,800030d4 - -0000000080002b28 : - 80002b28: 00100093 li ra,1 - 80002b2c: 01f00113 li sp,31 - 80002b30: 00209f33 sll t5,ra,sp - 80002b34: 00100e9b addiw t4,zero,1 - 80002b38: 01fe9e93 slli t4,t4,0x1f - 80002b3c: 00600193 li gp,6 - 80002b40: 59df1a63 bne t5,t4,800030d4 - -0000000080002b44 : - 80002b44: fff00093 li ra,-1 - 80002b48: 00000113 li sp,0 - 80002b4c: 00209f33 sll t5,ra,sp - 80002b50: fff00e93 li t4,-1 - 80002b54: 00700193 li gp,7 - 80002b58: 57df1e63 bne t5,t4,800030d4 - -0000000080002b5c : - 80002b5c: fff00093 li ra,-1 - 80002b60: 00100113 li sp,1 - 80002b64: 00209f33 sll t5,ra,sp - 80002b68: ffe00e93 li t4,-2 - 80002b6c: 00800193 li gp,8 - 80002b70: 57df1263 bne t5,t4,800030d4 - -0000000080002b74 : - 80002b74: fff00093 li ra,-1 - 80002b78: 00700113 li sp,7 - 80002b7c: 00209f33 sll t5,ra,sp - 80002b80: f8000e93 li t4,-128 - 80002b84: 00900193 li gp,9 - 80002b88: 55df1663 bne t5,t4,800030d4 - -0000000080002b8c : - 80002b8c: fff00093 li ra,-1 - 80002b90: 00e00113 li sp,14 - 80002b94: 00209f33 sll t5,ra,sp - 80002b98: ffffceb7 lui t4,0xffffc - 80002b9c: 00a00193 li gp,10 - 80002ba0: 53df1a63 bne t5,t4,800030d4 - -0000000080002ba4 : - 80002ba4: fff00093 li ra,-1 - 80002ba8: 01f00113 li sp,31 - 80002bac: 00209f33 sll t5,ra,sp - 80002bb0: 80000eb7 lui t4,0x80000 - 80002bb4: 00b00193 li gp,11 - 80002bb8: 51df1e63 bne t5,t4,800030d4 - -0000000080002bbc : - 80002bbc: 212120b7 lui ra,0x21212 - 80002bc0: 1210809b addiw ra,ra,289 - 80002bc4: 00000113 li sp,0 - 80002bc8: 00209f33 sll t5,ra,sp - 80002bcc: 21212eb7 lui t4,0x21212 - 80002bd0: 121e8e9b addiw t4,t4,289 - 80002bd4: 00c00193 li gp,12 - 80002bd8: 4fdf1e63 bne t5,t4,800030d4 - -0000000080002bdc : - 80002bdc: 212120b7 lui ra,0x21212 - 80002be0: 1210809b addiw ra,ra,289 - 80002be4: 00100113 li sp,1 - 80002be8: 00209f33 sll t5,ra,sp - 80002bec: 42424eb7 lui t4,0x42424 - 80002bf0: 242e8e9b addiw t4,t4,578 - 80002bf4: 00d00193 li gp,13 - 80002bf8: 4ddf1e63 bne t5,t4,800030d4 - -0000000080002bfc : - 80002bfc: 212120b7 lui ra,0x21212 - 80002c00: 1210809b addiw ra,ra,289 - 80002c04: 00700113 li sp,7 - 80002c08: 00209f33 sll t5,ra,sp - 80002c0c: 01091eb7 lui t4,0x1091 - 80002c10: 909e8e9b addiw t4,t4,-1783 - 80002c14: 00ce9e93 slli t4,t4,0xc - 80002c18: 080e8e93 addi t4,t4,128 # 1091080 <_start-0x7ef6ef80> - 80002c1c: 00e00193 li gp,14 - 80002c20: 4bdf1a63 bne t5,t4,800030d4 - -0000000080002c24 : - 80002c24: 212120b7 lui ra,0x21212 - 80002c28: 1210809b addiw ra,ra,289 - 80002c2c: 00e00113 li sp,14 - 80002c30: 00209f33 sll t5,ra,sp - 80002c34: 21212eb7 lui t4,0x21212 - 80002c38: 121e8e9b addiw t4,t4,289 - 80002c3c: 00ee9e93 slli t4,t4,0xe - 80002c40: 00f00193 li gp,15 - 80002c44: 49df1863 bne t5,t4,800030d4 - -0000000080002c48 : - 80002c48: 212120b7 lui ra,0x21212 - 80002c4c: 1210809b addiw ra,ra,289 - 80002c50: 01f00113 li sp,31 - 80002c54: 00209f33 sll t5,ra,sp - 80002c58: 21212eb7 lui t4,0x21212 - 80002c5c: 121e8e9b addiw t4,t4,289 - 80002c60: 01fe9e93 slli t4,t4,0x1f - 80002c64: 01000193 li gp,16 - 80002c68: 47df1663 bne t5,t4,800030d4 - -0000000080002c6c : - 80002c6c: 212120b7 lui ra,0x21212 - 80002c70: 1210809b addiw ra,ra,289 - 80002c74: fc000113 li sp,-64 - 80002c78: 00209f33 sll t5,ra,sp - 80002c7c: 21212eb7 lui t4,0x21212 - 80002c80: 121e8e9b addiw t4,t4,289 - 80002c84: 01100193 li gp,17 - 80002c88: 45df1663 bne t5,t4,800030d4 - -0000000080002c8c : - 80002c8c: 212120b7 lui ra,0x21212 - 80002c90: 1210809b addiw ra,ra,289 - 80002c94: fc100113 li sp,-63 - 80002c98: 00209f33 sll t5,ra,sp - 80002c9c: 42424eb7 lui t4,0x42424 - 80002ca0: 242e8e9b addiw t4,t4,578 - 80002ca4: 01200193 li gp,18 - 80002ca8: 43df1663 bne t5,t4,800030d4 - -0000000080002cac : - 80002cac: 212120b7 lui ra,0x21212 - 80002cb0: 1210809b addiw ra,ra,289 - 80002cb4: fc700113 li sp,-57 - 80002cb8: 00209f33 sll t5,ra,sp - 80002cbc: 01091eb7 lui t4,0x1091 - 80002cc0: 909e8e9b addiw t4,t4,-1783 - 80002cc4: 00ce9e93 slli t4,t4,0xc - 80002cc8: 080e8e93 addi t4,t4,128 # 1091080 <_start-0x7ef6ef80> - 80002ccc: 01300193 li gp,19 - 80002cd0: 41df1263 bne t5,t4,800030d4 - -0000000080002cd4 : - 80002cd4: 212120b7 lui ra,0x21212 - 80002cd8: 1210809b addiw ra,ra,289 - 80002cdc: fce00113 li sp,-50 - 80002ce0: 00209f33 sll t5,ra,sp - 80002ce4: 21212eb7 lui t4,0x21212 - 80002ce8: 121e8e9b addiw t4,t4,289 - 80002cec: 00ee9e93 slli t4,t4,0xe - 80002cf0: 01400193 li gp,20 - 80002cf4: 3fdf1063 bne t5,t4,800030d4 - -0000000080002cf8 : - 80002cf8: 212120b7 lui ra,0x21212 - 80002cfc: 1210809b addiw ra,ra,289 - 80002d00: fff00113 li sp,-1 - 80002d04: 00209f33 sll t5,ra,sp - 80002d08: fff00e9b addiw t4,zero,-1 - 80002d0c: 03fe9e93 slli t4,t4,0x3f - 80002d10: 01500193 li gp,21 - 80002d14: 3ddf1063 bne t5,t4,800030d4 - -0000000080002d18 : - 80002d18: 00100093 li ra,1 - 80002d1c: 03f00113 li sp,63 - 80002d20: 00209f33 sll t5,ra,sp - 80002d24: fff00e9b addiw t4,zero,-1 - 80002d28: 03fe9e93 slli t4,t4,0x3f - 80002d2c: 03200193 li gp,50 - 80002d30: 3bdf1263 bne t5,t4,800030d4 - -0000000080002d34 : - 80002d34: fff00093 li ra,-1 - 80002d38: 02700113 li sp,39 - 80002d3c: 00209f33 sll t5,ra,sp - 80002d40: fff00e9b addiw t4,zero,-1 - 80002d44: 027e9e93 slli t4,t4,0x27 - 80002d48: 03300193 li gp,51 - 80002d4c: 39df1463 bne t5,t4,800030d4 - -0000000080002d50 : - 80002d50: 212120b7 lui ra,0x21212 - 80002d54: 1210809b addiw ra,ra,289 - 80002d58: 02b00113 li sp,43 - 80002d5c: 00209f33 sll t5,ra,sp - 80002d60: 00012eb7 lui t4,0x12 - 80002d64: 121e8e9b addiw t4,t4,289 - 80002d68: 02be9e93 slli t4,t4,0x2b - 80002d6c: 03400193 li gp,52 - 80002d70: 37df1263 bne t5,t4,800030d4 - -0000000080002d74 : - 80002d74: 00100093 li ra,1 - 80002d78: 00700113 li sp,7 - 80002d7c: 002090b3 sll ra,ra,sp - 80002d80: 08000e93 li t4,128 - 80002d84: 01600193 li gp,22 - 80002d88: 35d09663 bne ra,t4,800030d4 - -0000000080002d8c : - 80002d8c: 00100093 li ra,1 - 80002d90: 00e00113 li sp,14 - 80002d94: 00209133 sll sp,ra,sp - 80002d98: 00004eb7 lui t4,0x4 - 80002d9c: 01700193 li gp,23 - 80002da0: 33d11a63 bne sp,t4,800030d4 - -0000000080002da4 : - 80002da4: 00300093 li ra,3 - 80002da8: 001090b3 sll ra,ra,ra - 80002dac: 01800e93 li t4,24 - 80002db0: 01800193 li gp,24 - 80002db4: 33d09063 bne ra,t4,800030d4 - -0000000080002db8 : - 80002db8: 00000213 li tp,0 - 80002dbc: 00100093 li ra,1 - 80002dc0: 00700113 li sp,7 - 80002dc4: 00209f33 sll t5,ra,sp - 80002dc8: 000f0313 mv t1,t5 - 80002dcc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dd0: 00200293 li t0,2 - 80002dd4: fe5214e3 bne tp,t0,80002dbc - 80002dd8: 08000e93 li t4,128 - 80002ddc: 01900193 li gp,25 - 80002de0: 2fd31a63 bne t1,t4,800030d4 - -0000000080002de4 : - 80002de4: 00000213 li tp,0 - 80002de8: 00100093 li ra,1 - 80002dec: 00e00113 li sp,14 - 80002df0: 00209f33 sll t5,ra,sp - 80002df4: 00000013 nop - 80002df8: 000f0313 mv t1,t5 - 80002dfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e00: 00200293 li t0,2 - 80002e04: fe5212e3 bne tp,t0,80002de8 - 80002e08: 00004eb7 lui t4,0x4 - 80002e0c: 01a00193 li gp,26 - 80002e10: 2dd31263 bne t1,t4,800030d4 - -0000000080002e14 : - 80002e14: 00000213 li tp,0 - 80002e18: 00100093 li ra,1 - 80002e1c: 01f00113 li sp,31 - 80002e20: 00209f33 sll t5,ra,sp - 80002e24: 00000013 nop - 80002e28: 00000013 nop - 80002e2c: 000f0313 mv t1,t5 - 80002e30: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e34: 00200293 li t0,2 - 80002e38: fe5210e3 bne tp,t0,80002e18 - 80002e3c: 00100e9b addiw t4,zero,1 - 80002e40: 01fe9e93 slli t4,t4,0x1f - 80002e44: 01b00193 li gp,27 - 80002e48: 29d31663 bne t1,t4,800030d4 - -0000000080002e4c : - 80002e4c: 00000213 li tp,0 - 80002e50: 00100093 li ra,1 - 80002e54: 00700113 li sp,7 - 80002e58: 00209f33 sll t5,ra,sp - 80002e5c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e60: 00200293 li t0,2 - 80002e64: fe5216e3 bne tp,t0,80002e50 - 80002e68: 08000e93 li t4,128 - 80002e6c: 01c00193 li gp,28 - 80002e70: 27df1263 bne t5,t4,800030d4 - -0000000080002e74 : - 80002e74: 00000213 li tp,0 - 80002e78: 00100093 li ra,1 - 80002e7c: 00e00113 li sp,14 - 80002e80: 00000013 nop - 80002e84: 00209f33 sll t5,ra,sp - 80002e88: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e8c: 00200293 li t0,2 - 80002e90: fe5214e3 bne tp,t0,80002e78 - 80002e94: 00004eb7 lui t4,0x4 - 80002e98: 01d00193 li gp,29 - 80002e9c: 23df1c63 bne t5,t4,800030d4 - -0000000080002ea0 : - 80002ea0: 00000213 li tp,0 - 80002ea4: 00100093 li ra,1 - 80002ea8: 01f00113 li sp,31 - 80002eac: 00000013 nop - 80002eb0: 00000013 nop - 80002eb4: 00209f33 sll t5,ra,sp - 80002eb8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ebc: 00200293 li t0,2 - 80002ec0: fe5212e3 bne tp,t0,80002ea4 - 80002ec4: 00100e9b addiw t4,zero,1 - 80002ec8: 01fe9e93 slli t4,t4,0x1f - 80002ecc: 01e00193 li gp,30 - 80002ed0: 21df1263 bne t5,t4,800030d4 - -0000000080002ed4 : - 80002ed4: 00000213 li tp,0 - 80002ed8: 00100093 li ra,1 - 80002edc: 00000013 nop - 80002ee0: 00700113 li sp,7 - 80002ee4: 00209f33 sll t5,ra,sp - 80002ee8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002eec: 00200293 li t0,2 - 80002ef0: fe5214e3 bne tp,t0,80002ed8 - 80002ef4: 08000e93 li t4,128 - 80002ef8: 01f00193 li gp,31 - 80002efc: 1ddf1c63 bne t5,t4,800030d4 - -0000000080002f00 : - 80002f00: 00000213 li tp,0 - 80002f04: 00100093 li ra,1 - 80002f08: 00000013 nop - 80002f0c: 00e00113 li sp,14 - 80002f10: 00000013 nop - 80002f14: 00209f33 sll t5,ra,sp - 80002f18: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f1c: 00200293 li t0,2 - 80002f20: fe5212e3 bne tp,t0,80002f04 - 80002f24: 00004eb7 lui t4,0x4 - 80002f28: 02000193 li gp,32 - 80002f2c: 1bdf1463 bne t5,t4,800030d4 - -0000000080002f30 : - 80002f30: 00000213 li tp,0 - 80002f34: 00100093 li ra,1 - 80002f38: 00000013 nop - 80002f3c: 00000013 nop - 80002f40: 01f00113 li sp,31 - 80002f44: 00209f33 sll t5,ra,sp - 80002f48: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f4c: 00200293 li t0,2 - 80002f50: fe5212e3 bne tp,t0,80002f34 - 80002f54: 00100e9b addiw t4,zero,1 - 80002f58: 01fe9e93 slli t4,t4,0x1f - 80002f5c: 02100193 li gp,33 - 80002f60: 17df1a63 bne t5,t4,800030d4 - -0000000080002f64 : - 80002f64: 00000213 li tp,0 - 80002f68: 00700113 li sp,7 - 80002f6c: 00100093 li ra,1 - 80002f70: 00209f33 sll t5,ra,sp - 80002f74: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f78: 00200293 li t0,2 - 80002f7c: fe5216e3 bne tp,t0,80002f68 - 80002f80: 08000e93 li t4,128 - 80002f84: 02200193 li gp,34 - 80002f88: 15df1663 bne t5,t4,800030d4 - -0000000080002f8c : - 80002f8c: 00000213 li tp,0 - 80002f90: 00e00113 li sp,14 - 80002f94: 00100093 li ra,1 - 80002f98: 00000013 nop - 80002f9c: 00209f33 sll t5,ra,sp - 80002fa0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002fa4: 00200293 li t0,2 - 80002fa8: fe5214e3 bne tp,t0,80002f90 - 80002fac: 00004eb7 lui t4,0x4 - 80002fb0: 02300193 li gp,35 - 80002fb4: 13df1063 bne t5,t4,800030d4 - -0000000080002fb8 : - 80002fb8: 00000213 li tp,0 - 80002fbc: 01f00113 li sp,31 - 80002fc0: 00100093 li ra,1 - 80002fc4: 00000013 nop - 80002fc8: 00000013 nop - 80002fcc: 00209f33 sll t5,ra,sp - 80002fd0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002fd4: 00200293 li t0,2 - 80002fd8: fe5212e3 bne tp,t0,80002fbc - 80002fdc: 00100e9b addiw t4,zero,1 - 80002fe0: 01fe9e93 slli t4,t4,0x1f - 80002fe4: 02400193 li gp,36 - 80002fe8: 0fdf1663 bne t5,t4,800030d4 - -0000000080002fec : - 80002fec: 00000213 li tp,0 - 80002ff0: 00700113 li sp,7 - 80002ff4: 00000013 nop - 80002ff8: 00100093 li ra,1 - 80002ffc: 00209f33 sll t5,ra,sp - 80003000: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80003004: 00200293 li t0,2 - 80003008: fe5214e3 bne tp,t0,80002ff0 - 8000300c: 08000e93 li t4,128 - 80003010: 02500193 li gp,37 - 80003014: 0ddf1063 bne t5,t4,800030d4 - -0000000080003018 : - 80003018: 00000213 li tp,0 - 8000301c: 00e00113 li sp,14 - 80003020: 00000013 nop - 80003024: 00100093 li ra,1 - 80003028: 00000013 nop - 8000302c: 00209f33 sll t5,ra,sp - 80003030: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80003034: 00200293 li t0,2 - 80003038: fe5212e3 bne tp,t0,8000301c - 8000303c: 00004eb7 lui t4,0x4 - 80003040: 02600193 li gp,38 - 80003044: 09df1863 bne t5,t4,800030d4 - -0000000080003048 : - 80003048: 00000213 li tp,0 - 8000304c: 01f00113 li sp,31 - 80003050: 00000013 nop - 80003054: 00000013 nop - 80003058: 00100093 li ra,1 - 8000305c: 00209f33 sll t5,ra,sp - 80003060: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80003064: 00200293 li t0,2 - 80003068: fe5212e3 bne tp,t0,8000304c - 8000306c: 00100e9b addiw t4,zero,1 - 80003070: 01fe9e93 slli t4,t4,0x1f - 80003074: 02700193 li gp,39 - 80003078: 05df1e63 bne t5,t4,800030d4 - -000000008000307c : - 8000307c: 00f00093 li ra,15 - 80003080: 00101133 sll sp,zero,ra - 80003084: 00000e93 li t4,0 - 80003088: 02800193 li gp,40 - 8000308c: 05d11463 bne sp,t4,800030d4 - -0000000080003090 : - 80003090: 02000093 li ra,32 - 80003094: 00009133 sll sp,ra,zero - 80003098: 02000e93 li t4,32 - 8000309c: 02900193 li gp,41 - 800030a0: 03d11a63 bne sp,t4,800030d4 - -00000000800030a4 : - 800030a4: 000010b3 sll ra,zero,zero - 800030a8: 00000e93 li t4,0 - 800030ac: 02a00193 li gp,42 - 800030b0: 03d09263 bne ra,t4,800030d4 - -00000000800030b4 : - 800030b4: 40000093 li ra,1024 - 800030b8: 00001137 lui sp,0x1 - 800030bc: 8001011b addiw sp,sp,-2048 - 800030c0: 00209033 sll zero,ra,sp - 800030c4: 00000e93 li t4,0 - 800030c8: 02b00193 li gp,43 - 800030cc: 01d01463 bne zero,t4,800030d4 - 800030d0: 00301a63 bne zero,gp,800030e4 - -00000000800030d4 : - 800030d4: 00119513 slli a0,gp,0x1 - 800030d8: 00050063 beqz a0,800030d8 - 800030dc: 00156513 ori a0,a0,1 - 800030e0: 00000073 ecall - -00000000800030e4 : - 800030e4: 00100513 li a0,1 - 800030e8: 00000073 ecall - 800030ec: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-sll.elf b/test/riscv/tests/rv64ui-v-sll.elf deleted file mode 100644 index a32b39ed..00000000 Binary files a/test/riscv/tests/rv64ui-v-sll.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-slli.dump b/test/riscv/tests/rv64ui-v-slli.dump deleted file mode 100644 index 2808442b..00000000 --- a/test/riscv/tests/rv64ui-v-slli.dump +++ /dev/null @@ -1,1082 +0,0 @@ - -rv64ui-v-slli: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 98868693 addi a3,a3,-1656 # 80002de0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 9bc60613 addi a2,a2,-1604 # 80002e70 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 98460613 addi a2,a2,-1660 # 80002e88 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 8d468693 addi a3,a3,-1836 # 80002e28 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 8f068693 addi a3,a3,-1808 # 80002f60 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 87060613 addi a2,a2,-1936 # 80002f38 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 7a468693 addi a3,a3,1956 # 80002f90 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 6c468693 addi a3,a3,1732 # 80002f00 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 65468693 addi a3,a3,1620 # 80002ec8 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 02100793 li a5,33 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0f9957b7 lui a5,0xf995 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 0d278793 addi a5,a5,210 # f9950d2 <_start-0x7066af2e> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00100093 li ra,1 - 80002acc: 00009f13 slli t5,ra,0x0 - 80002ad0: 00100e93 li t4,1 - 80002ad4: 00200193 li gp,2 - 80002ad8: 2fdf1463 bne t5,t4,80002dc0 - -0000000080002adc : - 80002adc: 00100093 li ra,1 - 80002ae0: 00109f13 slli t5,ra,0x1 - 80002ae4: 00200e93 li t4,2 - 80002ae8: 00300193 li gp,3 - 80002aec: 2ddf1a63 bne t5,t4,80002dc0 - -0000000080002af0 : - 80002af0: 00100093 li ra,1 - 80002af4: 00709f13 slli t5,ra,0x7 - 80002af8: 08000e93 li t4,128 - 80002afc: 00400193 li gp,4 - 80002b00: 2ddf1063 bne t5,t4,80002dc0 - -0000000080002b04 : - 80002b04: 00100093 li ra,1 - 80002b08: 00e09f13 slli t5,ra,0xe - 80002b0c: 00004eb7 lui t4,0x4 - 80002b10: 00500193 li gp,5 - 80002b14: 2bdf1663 bne t5,t4,80002dc0 - -0000000080002b18 : - 80002b18: 00100093 li ra,1 - 80002b1c: 01f09f13 slli t5,ra,0x1f - 80002b20: 00100e9b addiw t4,zero,1 - 80002b24: 01fe9e93 slli t4,t4,0x1f - 80002b28: 00600193 li gp,6 - 80002b2c: 29df1a63 bne t5,t4,80002dc0 - -0000000080002b30 : - 80002b30: fff00093 li ra,-1 - 80002b34: 00009f13 slli t5,ra,0x0 - 80002b38: fff00e93 li t4,-1 - 80002b3c: 00700193 li gp,7 - 80002b40: 29df1063 bne t5,t4,80002dc0 - -0000000080002b44 : - 80002b44: fff00093 li ra,-1 - 80002b48: 00109f13 slli t5,ra,0x1 - 80002b4c: ffe00e93 li t4,-2 - 80002b50: 00800193 li gp,8 - 80002b54: 27df1663 bne t5,t4,80002dc0 - -0000000080002b58 : - 80002b58: fff00093 li ra,-1 - 80002b5c: 00709f13 slli t5,ra,0x7 - 80002b60: f8000e93 li t4,-128 - 80002b64: 00900193 li gp,9 - 80002b68: 25df1c63 bne t5,t4,80002dc0 - -0000000080002b6c : - 80002b6c: fff00093 li ra,-1 - 80002b70: 00e09f13 slli t5,ra,0xe - 80002b74: ffffceb7 lui t4,0xffffc - 80002b78: 00a00193 li gp,10 - 80002b7c: 25df1263 bne t5,t4,80002dc0 - -0000000080002b80 : - 80002b80: fff00093 li ra,-1 - 80002b84: 01f09f13 slli t5,ra,0x1f - 80002b88: 80000eb7 lui t4,0x80000 - 80002b8c: 00b00193 li gp,11 - 80002b90: 23df1863 bne t5,t4,80002dc0 - -0000000080002b94 : - 80002b94: 212120b7 lui ra,0x21212 - 80002b98: 1210809b addiw ra,ra,289 - 80002b9c: 00009f13 slli t5,ra,0x0 - 80002ba0: 21212eb7 lui t4,0x21212 - 80002ba4: 121e8e9b addiw t4,t4,289 - 80002ba8: 00c00193 li gp,12 - 80002bac: 21df1a63 bne t5,t4,80002dc0 - -0000000080002bb0 : - 80002bb0: 212120b7 lui ra,0x21212 - 80002bb4: 1210809b addiw ra,ra,289 - 80002bb8: 00109f13 slli t5,ra,0x1 - 80002bbc: 42424eb7 lui t4,0x42424 - 80002bc0: 242e8e9b addiw t4,t4,578 - 80002bc4: 00d00193 li gp,13 - 80002bc8: 1fdf1c63 bne t5,t4,80002dc0 - -0000000080002bcc : - 80002bcc: 212120b7 lui ra,0x21212 - 80002bd0: 1210809b addiw ra,ra,289 - 80002bd4: 00709f13 slli t5,ra,0x7 - 80002bd8: 01091eb7 lui t4,0x1091 - 80002bdc: 909e8e9b addiw t4,t4,-1783 - 80002be0: 00ce9e93 slli t4,t4,0xc - 80002be4: 080e8e93 addi t4,t4,128 # 1091080 <_start-0x7ef6ef80> - 80002be8: 00e00193 li gp,14 - 80002bec: 1ddf1a63 bne t5,t4,80002dc0 - -0000000080002bf0 : - 80002bf0: 212120b7 lui ra,0x21212 - 80002bf4: 1210809b addiw ra,ra,289 - 80002bf8: 00e09f13 slli t5,ra,0xe - 80002bfc: 21212eb7 lui t4,0x21212 - 80002c00: 121e8e9b addiw t4,t4,289 - 80002c04: 00ee9e93 slli t4,t4,0xe - 80002c08: 00f00193 li gp,15 - 80002c0c: 1bdf1a63 bne t5,t4,80002dc0 - -0000000080002c10 : - 80002c10: 212120b7 lui ra,0x21212 - 80002c14: 1210809b addiw ra,ra,289 - 80002c18: 01f09f13 slli t5,ra,0x1f - 80002c1c: 21212eb7 lui t4,0x21212 - 80002c20: 121e8e9b addiw t4,t4,289 - 80002c24: 01fe9e93 slli t4,t4,0x1f - 80002c28: 01000193 li gp,16 - 80002c2c: 19df1a63 bne t5,t4,80002dc0 - -0000000080002c30 : - 80002c30: 00100093 li ra,1 - 80002c34: 03f09f13 slli t5,ra,0x3f - 80002c38: fff00e9b addiw t4,zero,-1 - 80002c3c: 03fe9e93 slli t4,t4,0x3f - 80002c40: 03200193 li gp,50 - 80002c44: 17df1e63 bne t5,t4,80002dc0 - -0000000080002c48 : - 80002c48: fff00093 li ra,-1 - 80002c4c: 02709f13 slli t5,ra,0x27 - 80002c50: fff00e9b addiw t4,zero,-1 - 80002c54: 027e9e93 slli t4,t4,0x27 - 80002c58: 03300193 li gp,51 - 80002c5c: 17df1263 bne t5,t4,80002dc0 - -0000000080002c60 : - 80002c60: 212120b7 lui ra,0x21212 - 80002c64: 1210809b addiw ra,ra,289 - 80002c68: 02b09f13 slli t5,ra,0x2b - 80002c6c: 00012eb7 lui t4,0x12 - 80002c70: 121e8e9b addiw t4,t4,289 - 80002c74: 02be9e93 slli t4,t4,0x2b - 80002c78: 03400193 li gp,52 - 80002c7c: 15df1263 bne t5,t4,80002dc0 - -0000000080002c80 : - 80002c80: 00100093 li ra,1 - 80002c84: 00709093 slli ra,ra,0x7 - 80002c88: 08000e93 li t4,128 - 80002c8c: 01100193 li gp,17 - 80002c90: 13d09863 bne ra,t4,80002dc0 - -0000000080002c94 : - 80002c94: 00000213 li tp,0 - 80002c98: 00100093 li ra,1 - 80002c9c: 00709f13 slli t5,ra,0x7 - 80002ca0: 000f0313 mv t1,t5 - 80002ca4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ca8: 00200293 li t0,2 - 80002cac: fe5216e3 bne tp,t0,80002c98 - 80002cb0: 08000e93 li t4,128 - 80002cb4: 01200193 li gp,18 - 80002cb8: 11d31463 bne t1,t4,80002dc0 - -0000000080002cbc : - 80002cbc: 00000213 li tp,0 - 80002cc0: 00100093 li ra,1 - 80002cc4: 00e09f13 slli t5,ra,0xe - 80002cc8: 00000013 nop - 80002ccc: 000f0313 mv t1,t5 - 80002cd0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cd4: 00200293 li t0,2 - 80002cd8: fe5214e3 bne tp,t0,80002cc0 - 80002cdc: 00004eb7 lui t4,0x4 - 80002ce0: 01300193 li gp,19 - 80002ce4: 0dd31e63 bne t1,t4,80002dc0 - -0000000080002ce8 : - 80002ce8: 00000213 li tp,0 - 80002cec: 00100093 li ra,1 - 80002cf0: 01f09f13 slli t5,ra,0x1f - 80002cf4: 00000013 nop - 80002cf8: 00000013 nop - 80002cfc: 000f0313 mv t1,t5 - 80002d00: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d04: 00200293 li t0,2 - 80002d08: fe5212e3 bne tp,t0,80002cec - 80002d0c: 00100e9b addiw t4,zero,1 - 80002d10: 01fe9e93 slli t4,t4,0x1f - 80002d14: 01400193 li gp,20 - 80002d18: 0bd31463 bne t1,t4,80002dc0 - -0000000080002d1c : - 80002d1c: 00000213 li tp,0 - 80002d20: 00100093 li ra,1 - 80002d24: 00709f13 slli t5,ra,0x7 - 80002d28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d2c: 00200293 li t0,2 - 80002d30: fe5218e3 bne tp,t0,80002d20 - 80002d34: 08000e93 li t4,128 - 80002d38: 01500193 li gp,21 - 80002d3c: 09df1263 bne t5,t4,80002dc0 - -0000000080002d40 : - 80002d40: 00000213 li tp,0 - 80002d44: 00100093 li ra,1 - 80002d48: 00000013 nop - 80002d4c: 00e09f13 slli t5,ra,0xe - 80002d50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d54: 00200293 li t0,2 - 80002d58: fe5216e3 bne tp,t0,80002d44 - 80002d5c: 00004eb7 lui t4,0x4 - 80002d60: 01600193 li gp,22 - 80002d64: 05df1e63 bne t5,t4,80002dc0 - -0000000080002d68 : - 80002d68: 00000213 li tp,0 - 80002d6c: 00100093 li ra,1 - 80002d70: 00000013 nop - 80002d74: 00000013 nop - 80002d78: 01f09f13 slli t5,ra,0x1f - 80002d7c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d80: 00200293 li t0,2 - 80002d84: fe5214e3 bne tp,t0,80002d6c - 80002d88: 00100e9b addiw t4,zero,1 - 80002d8c: 01fe9e93 slli t4,t4,0x1f - 80002d90: 01700193 li gp,23 - 80002d94: 03df1663 bne t5,t4,80002dc0 - -0000000080002d98 : - 80002d98: 01f01093 slli ra,zero,0x1f - 80002d9c: 00000e93 li t4,0 - 80002da0: 01800193 li gp,24 - 80002da4: 01d09e63 bne ra,t4,80002dc0 - -0000000080002da8 : - 80002da8: 02100093 li ra,33 - 80002dac: 01409013 slli zero,ra,0x14 - 80002db0: 00000e93 li t4,0 - 80002db4: 01900193 li gp,25 - 80002db8: 01d01463 bne zero,t4,80002dc0 - 80002dbc: 00301a63 bne zero,gp,80002dd0 - -0000000080002dc0 : - 80002dc0: 00119513 slli a0,gp,0x1 - 80002dc4: 00050063 beqz a0,80002dc4 - 80002dc8: 00156513 ori a0,a0,1 - 80002dcc: 00000073 ecall - -0000000080002dd0 : - 80002dd0: 00100513 li a0,1 - 80002dd4: 00000073 ecall - 80002dd8: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-slli.elf b/test/riscv/tests/rv64ui-v-slli.elf deleted file mode 100644 index 2b9e327a..00000000 Binary files a/test/riscv/tests/rv64ui-v-slli.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-slliw.dump b/test/riscv/tests/rv64ui-v-slliw.dump deleted file mode 100644 index 25efc0d9..00000000 --- a/test/riscv/tests/rv64ui-v-slliw.dump +++ /dev/null @@ -1,1047 +0,0 @@ - -rv64ui-v-slliw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 91068693 addi a3,a3,-1776 # 80002d68 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 94460613 addi a2,a2,-1724 # 80002df8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 90c60613 addi a2,a2,-1780 # 80002e10 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 85c68693 addi a3,a3,-1956 # 80002db0 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 87868693 addi a3,a3,-1928 # 80002ee8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 7f860613 addi a2,a2,2040 # 80002ec0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 72c68693 addi a3,a3,1836 # 80002f18 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 64c68693 addi a3,a3,1612 # 80002e88 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 5dc68693 addi a3,a3,1500 # 80002e50 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 01000793 li a5,16 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0a2947b7 lui a5,0xa294 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: def78793 addi a5,a5,-529 # a293def <_start-0x75d6c211> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00100093 li ra,1 - 80002acc: 00009f1b slliw t5,ra,0x0 - 80002ad0: 00100e93 li t4,1 - 80002ad4: 00200193 li gp,2 - 80002ad8: 27df1a63 bne t5,t4,80002d4c - -0000000080002adc : - 80002adc: 00100093 li ra,1 - 80002ae0: 00109f1b slliw t5,ra,0x1 - 80002ae4: 00200e93 li t4,2 - 80002ae8: 00300193 li gp,3 - 80002aec: 27df1063 bne t5,t4,80002d4c - -0000000080002af0 : - 80002af0: 00100093 li ra,1 - 80002af4: 00709f1b slliw t5,ra,0x7 - 80002af8: 08000e93 li t4,128 - 80002afc: 00400193 li gp,4 - 80002b00: 25df1663 bne t5,t4,80002d4c - -0000000080002b04 : - 80002b04: 00100093 li ra,1 - 80002b08: 00e09f1b slliw t5,ra,0xe - 80002b0c: 00004eb7 lui t4,0x4 - 80002b10: 00500193 li gp,5 - 80002b14: 23df1c63 bne t5,t4,80002d4c - -0000000080002b18 : - 80002b18: 00100093 li ra,1 - 80002b1c: 01f09f1b slliw t5,ra,0x1f - 80002b20: 80000eb7 lui t4,0x80000 - 80002b24: 00600193 li gp,6 - 80002b28: 23df1263 bne t5,t4,80002d4c - -0000000080002b2c : - 80002b2c: fff00093 li ra,-1 - 80002b30: 00009f1b slliw t5,ra,0x0 - 80002b34: fff00e93 li t4,-1 - 80002b38: 00700193 li gp,7 - 80002b3c: 21df1863 bne t5,t4,80002d4c - -0000000080002b40 : - 80002b40: fff00093 li ra,-1 - 80002b44: 00109f1b slliw t5,ra,0x1 - 80002b48: ffe00e93 li t4,-2 - 80002b4c: 00800193 li gp,8 - 80002b50: 1fdf1e63 bne t5,t4,80002d4c - -0000000080002b54 : - 80002b54: fff00093 li ra,-1 - 80002b58: 00709f1b slliw t5,ra,0x7 - 80002b5c: f8000e93 li t4,-128 - 80002b60: 00900193 li gp,9 - 80002b64: 1fdf1463 bne t5,t4,80002d4c - -0000000080002b68 : - 80002b68: fff00093 li ra,-1 - 80002b6c: 00e09f1b slliw t5,ra,0xe - 80002b70: ffffceb7 lui t4,0xffffc - 80002b74: 00a00193 li gp,10 - 80002b78: 1ddf1a63 bne t5,t4,80002d4c - -0000000080002b7c : - 80002b7c: fff00093 li ra,-1 - 80002b80: 01f09f1b slliw t5,ra,0x1f - 80002b84: 80000eb7 lui t4,0x80000 - 80002b88: 00b00193 li gp,11 - 80002b8c: 1ddf1063 bne t5,t4,80002d4c - -0000000080002b90 : - 80002b90: 212120b7 lui ra,0x21212 - 80002b94: 1210809b addiw ra,ra,289 - 80002b98: 00009f1b slliw t5,ra,0x0 - 80002b9c: 21212eb7 lui t4,0x21212 - 80002ba0: 121e8e9b addiw t4,t4,289 - 80002ba4: 00c00193 li gp,12 - 80002ba8: 1bdf1263 bne t5,t4,80002d4c - -0000000080002bac : - 80002bac: 212120b7 lui ra,0x21212 - 80002bb0: 1210809b addiw ra,ra,289 - 80002bb4: 00109f1b slliw t5,ra,0x1 - 80002bb8: 42424eb7 lui t4,0x42424 - 80002bbc: 242e8e9b addiw t4,t4,578 - 80002bc0: 00d00193 li gp,13 - 80002bc4: 19df1463 bne t5,t4,80002d4c - -0000000080002bc8 : - 80002bc8: 212120b7 lui ra,0x21212 - 80002bcc: 1210809b addiw ra,ra,289 - 80002bd0: 00709f1b slliw t5,ra,0x7 - 80002bd4: 90909eb7 lui t4,0x90909 - 80002bd8: 080e8e9b addiw t4,t4,128 - 80002bdc: 00e00193 li gp,14 - 80002be0: 17df1663 bne t5,t4,80002d4c - -0000000080002be4 : - 80002be4: 212120b7 lui ra,0x21212 - 80002be8: 1210809b addiw ra,ra,289 - 80002bec: 00e09f1b slliw t5,ra,0xe - 80002bf0: 48484eb7 lui t4,0x48484 - 80002bf4: 00f00193 li gp,15 - 80002bf8: 15df1a63 bne t5,t4,80002d4c - -0000000080002bfc : - 80002bfc: 212120b7 lui ra,0x21212 - 80002c00: 1210809b addiw ra,ra,289 - 80002c04: 01f09f1b slliw t5,ra,0x1f - 80002c08: 80000eb7 lui t4,0x80000 - 80002c0c: 01000193 li gp,16 - 80002c10: 13df1e63 bne t5,t4,80002d4c - -0000000080002c14 : - 80002c14: 00100093 li ra,1 - 80002c18: 0070909b slliw ra,ra,0x7 - 80002c1c: 08000e93 li t4,128 - 80002c20: 01100193 li gp,17 - 80002c24: 13d09463 bne ra,t4,80002d4c - -0000000080002c28 : - 80002c28: 00000213 li tp,0 - 80002c2c: 00100093 li ra,1 - 80002c30: 00709f1b slliw t5,ra,0x7 - 80002c34: 000f0313 mv t1,t5 - 80002c38: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c3c: 00200293 li t0,2 - 80002c40: fe5216e3 bne tp,t0,80002c2c - 80002c44: 08000e93 li t4,128 - 80002c48: 01200193 li gp,18 - 80002c4c: 11d31063 bne t1,t4,80002d4c - -0000000080002c50 : - 80002c50: 00000213 li tp,0 - 80002c54: 00100093 li ra,1 - 80002c58: 00e09f1b slliw t5,ra,0xe - 80002c5c: 00000013 nop - 80002c60: 000f0313 mv t1,t5 - 80002c64: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c68: 00200293 li t0,2 - 80002c6c: fe5214e3 bne tp,t0,80002c54 - 80002c70: 00004eb7 lui t4,0x4 - 80002c74: 01300193 li gp,19 - 80002c78: 0dd31a63 bne t1,t4,80002d4c - -0000000080002c7c : - 80002c7c: 00000213 li tp,0 - 80002c80: 00100093 li ra,1 - 80002c84: 01f09f1b slliw t5,ra,0x1f - 80002c88: 00000013 nop - 80002c8c: 00000013 nop - 80002c90: 000f0313 mv t1,t5 - 80002c94: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c98: 00200293 li t0,2 - 80002c9c: fe5212e3 bne tp,t0,80002c80 - 80002ca0: 80000eb7 lui t4,0x80000 - 80002ca4: 01400193 li gp,20 - 80002ca8: 0bd31263 bne t1,t4,80002d4c - -0000000080002cac : - 80002cac: 00000213 li tp,0 - 80002cb0: 00100093 li ra,1 - 80002cb4: 00709f1b slliw t5,ra,0x7 - 80002cb8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cbc: 00200293 li t0,2 - 80002cc0: fe5218e3 bne tp,t0,80002cb0 - 80002cc4: 08000e93 li t4,128 - 80002cc8: 01500193 li gp,21 - 80002ccc: 09df1063 bne t5,t4,80002d4c - -0000000080002cd0 : - 80002cd0: 00000213 li tp,0 - 80002cd4: 00100093 li ra,1 - 80002cd8: 00000013 nop - 80002cdc: 00e09f1b slliw t5,ra,0xe - 80002ce0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ce4: 00200293 li t0,2 - 80002ce8: fe5216e3 bne tp,t0,80002cd4 - 80002cec: 00004eb7 lui t4,0x4 - 80002cf0: 01600193 li gp,22 - 80002cf4: 05df1c63 bne t5,t4,80002d4c - -0000000080002cf8 : - 80002cf8: 00000213 li tp,0 - 80002cfc: 00100093 li ra,1 - 80002d00: 00000013 nop - 80002d04: 00000013 nop - 80002d08: 01f09f1b slliw t5,ra,0x1f - 80002d0c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d10: 00200293 li t0,2 - 80002d14: fe5214e3 bne tp,t0,80002cfc - 80002d18: 80000eb7 lui t4,0x80000 - 80002d1c: 01700193 li gp,23 - 80002d20: 03df1663 bne t5,t4,80002d4c - -0000000080002d24 : - 80002d24: 01f0109b slliw ra,zero,0x1f - 80002d28: 00000e93 li t4,0 - 80002d2c: 01800193 li gp,24 - 80002d30: 01d09e63 bne ra,t4,80002d4c - -0000000080002d34 : - 80002d34: 01f00093 li ra,31 - 80002d38: 01c0901b slliw zero,ra,0x1c - 80002d3c: 00000e93 li t4,0 - 80002d40: 01900193 li gp,25 - 80002d44: 01d01463 bne zero,t4,80002d4c - 80002d48: 00301a63 bne zero,gp,80002d5c - -0000000080002d4c : - 80002d4c: 00119513 slli a0,gp,0x1 - 80002d50: 00050063 beqz a0,80002d50 - 80002d54: 00156513 ori a0,a0,1 - 80002d58: 00000073 ecall - -0000000080002d5c : - 80002d5c: 00100513 li a0,1 - 80002d60: 00000073 ecall - 80002d64: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-slliw.elf b/test/riscv/tests/rv64ui-v-slliw.elf deleted file mode 100644 index dd80f11c..00000000 Binary files a/test/riscv/tests/rv64ui-v-slliw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-sllw.dump b/test/riscv/tests/rv64ui-v-sllw.dump deleted file mode 100644 index e44d86e7..00000000 --- a/test/riscv/tests/rv64ui-v-sllw.dump +++ /dev/null @@ -1,1269 +0,0 @@ - -rv64ui-v-sllw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: bf868693 addi a3,a3,-1032 # 80003050 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: c2c60613 addi a2,a2,-980 # 800030e0 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: bf460613 addi a2,a2,-1036 # 800030f8 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: b4468693 addi a3,a3,-1212 # 80003098 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: b6068693 addi a3,a3,-1184 # 800031d0 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: ae060613 addi a2,a2,-1312 # 800031a8 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: a1468693 addi a3,a3,-1516 # 80003200 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 93468693 addi a3,a3,-1740 # 80003170 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00001697 auipc a3,0x1 - 80002878: 8c468693 addi a3,a3,-1852 # 80003138 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 02f00793 li a5,47 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 09afd7b7 lui a5,0x9afd - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 1b578793 addi a5,a5,437 # 9afd1b5 <_start-0x76502e4b> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00100093 li ra,1 - 80002acc: 00000113 li sp,0 - 80002ad0: 00209f3b sllw t5,ra,sp - 80002ad4: 00100e93 li t4,1 - 80002ad8: 00200193 li gp,2 - 80002adc: 55df1c63 bne t5,t4,80003034 - -0000000080002ae0 : - 80002ae0: 00100093 li ra,1 - 80002ae4: 00100113 li sp,1 - 80002ae8: 00209f3b sllw t5,ra,sp - 80002aec: 00200e93 li t4,2 - 80002af0: 00300193 li gp,3 - 80002af4: 55df1063 bne t5,t4,80003034 - -0000000080002af8 : - 80002af8: 00100093 li ra,1 - 80002afc: 00700113 li sp,7 - 80002b00: 00209f3b sllw t5,ra,sp - 80002b04: 08000e93 li t4,128 - 80002b08: 00400193 li gp,4 - 80002b0c: 53df1463 bne t5,t4,80003034 - -0000000080002b10 : - 80002b10: 00100093 li ra,1 - 80002b14: 00e00113 li sp,14 - 80002b18: 00209f3b sllw t5,ra,sp - 80002b1c: 00004eb7 lui t4,0x4 - 80002b20: 00500193 li gp,5 - 80002b24: 51df1863 bne t5,t4,80003034 - -0000000080002b28 : - 80002b28: 00100093 li ra,1 - 80002b2c: 01f00113 li sp,31 - 80002b30: 00209f3b sllw t5,ra,sp - 80002b34: 80000eb7 lui t4,0x80000 - 80002b38: 00600193 li gp,6 - 80002b3c: 4fdf1c63 bne t5,t4,80003034 - -0000000080002b40 : - 80002b40: fff00093 li ra,-1 - 80002b44: 00000113 li sp,0 - 80002b48: 00209f3b sllw t5,ra,sp - 80002b4c: fff00e93 li t4,-1 - 80002b50: 00700193 li gp,7 - 80002b54: 4fdf1063 bne t5,t4,80003034 - -0000000080002b58 : - 80002b58: fff00093 li ra,-1 - 80002b5c: 00100113 li sp,1 - 80002b60: 00209f3b sllw t5,ra,sp - 80002b64: ffe00e93 li t4,-2 - 80002b68: 00800193 li gp,8 - 80002b6c: 4ddf1463 bne t5,t4,80003034 - -0000000080002b70 : - 80002b70: fff00093 li ra,-1 - 80002b74: 00700113 li sp,7 - 80002b78: 00209f3b sllw t5,ra,sp - 80002b7c: f8000e93 li t4,-128 - 80002b80: 00900193 li gp,9 - 80002b84: 4bdf1863 bne t5,t4,80003034 - -0000000080002b88 : - 80002b88: fff00093 li ra,-1 - 80002b8c: 00e00113 li sp,14 - 80002b90: 00209f3b sllw t5,ra,sp - 80002b94: ffffceb7 lui t4,0xffffc - 80002b98: 00a00193 li gp,10 - 80002b9c: 49df1c63 bne t5,t4,80003034 - -0000000080002ba0 : - 80002ba0: fff00093 li ra,-1 - 80002ba4: 01f00113 li sp,31 - 80002ba8: 00209f3b sllw t5,ra,sp - 80002bac: 80000eb7 lui t4,0x80000 - 80002bb0: 00b00193 li gp,11 - 80002bb4: 49df1063 bne t5,t4,80003034 - -0000000080002bb8 : - 80002bb8: 212120b7 lui ra,0x21212 - 80002bbc: 1210809b addiw ra,ra,289 - 80002bc0: 00000113 li sp,0 - 80002bc4: 00209f3b sllw t5,ra,sp - 80002bc8: 21212eb7 lui t4,0x21212 - 80002bcc: 121e8e9b addiw t4,t4,289 - 80002bd0: 00c00193 li gp,12 - 80002bd4: 47df1063 bne t5,t4,80003034 - -0000000080002bd8 : - 80002bd8: 212120b7 lui ra,0x21212 - 80002bdc: 1210809b addiw ra,ra,289 - 80002be0: 00100113 li sp,1 - 80002be4: 00209f3b sllw t5,ra,sp - 80002be8: 42424eb7 lui t4,0x42424 - 80002bec: 242e8e9b addiw t4,t4,578 - 80002bf0: 00d00193 li gp,13 - 80002bf4: 45df1063 bne t5,t4,80003034 - -0000000080002bf8 : - 80002bf8: 212120b7 lui ra,0x21212 - 80002bfc: 1210809b addiw ra,ra,289 - 80002c00: 00700113 li sp,7 - 80002c04: 00209f3b sllw t5,ra,sp - 80002c08: 90909eb7 lui t4,0x90909 - 80002c0c: 080e8e9b addiw t4,t4,128 - 80002c10: 00e00193 li gp,14 - 80002c14: 43df1063 bne t5,t4,80003034 - -0000000080002c18 : - 80002c18: 212120b7 lui ra,0x21212 - 80002c1c: 1210809b addiw ra,ra,289 - 80002c20: 00e00113 li sp,14 - 80002c24: 00209f3b sllw t5,ra,sp - 80002c28: 48484eb7 lui t4,0x48484 - 80002c2c: 00f00193 li gp,15 - 80002c30: 41df1263 bne t5,t4,80003034 - -0000000080002c34 : - 80002c34: 212120b7 lui ra,0x21212 - 80002c38: 1210809b addiw ra,ra,289 - 80002c3c: 01f00113 li sp,31 - 80002c40: 00209f3b sllw t5,ra,sp - 80002c44: 80000eb7 lui t4,0x80000 - 80002c48: 01000193 li gp,16 - 80002c4c: 3fdf1463 bne t5,t4,80003034 - -0000000080002c50 : - 80002c50: 212120b7 lui ra,0x21212 - 80002c54: 1210809b addiw ra,ra,289 - 80002c58: fe000113 li sp,-32 - 80002c5c: 00209f3b sllw t5,ra,sp - 80002c60: 21212eb7 lui t4,0x21212 - 80002c64: 121e8e9b addiw t4,t4,289 - 80002c68: 01100193 li gp,17 - 80002c6c: 3ddf1463 bne t5,t4,80003034 - -0000000080002c70 : - 80002c70: 212120b7 lui ra,0x21212 - 80002c74: 1210809b addiw ra,ra,289 - 80002c78: fe100113 li sp,-31 - 80002c7c: 00209f3b sllw t5,ra,sp - 80002c80: 42424eb7 lui t4,0x42424 - 80002c84: 242e8e9b addiw t4,t4,578 - 80002c88: 01200193 li gp,18 - 80002c8c: 3bdf1463 bne t5,t4,80003034 - -0000000080002c90 : - 80002c90: 212120b7 lui ra,0x21212 - 80002c94: 1210809b addiw ra,ra,289 - 80002c98: fe700113 li sp,-25 - 80002c9c: 00209f3b sllw t5,ra,sp - 80002ca0: 90909eb7 lui t4,0x90909 - 80002ca4: 080e8e9b addiw t4,t4,128 - 80002ca8: 01300193 li gp,19 - 80002cac: 39df1463 bne t5,t4,80003034 - -0000000080002cb0 : - 80002cb0: 212120b7 lui ra,0x21212 - 80002cb4: 1210809b addiw ra,ra,289 - 80002cb8: fee00113 li sp,-18 - 80002cbc: 00209f3b sllw t5,ra,sp - 80002cc0: 48484eb7 lui t4,0x48484 - 80002cc4: 01400193 li gp,20 - 80002cc8: 37df1663 bne t5,t4,80003034 - -0000000080002ccc : - 80002ccc: 212120b7 lui ra,0x21212 - 80002cd0: 1210809b addiw ra,ra,289 - 80002cd4: fff00113 li sp,-1 - 80002cd8: 00209f3b sllw t5,ra,sp - 80002cdc: 80000eb7 lui t4,0x80000 - 80002ce0: 01500193 li gp,21 - 80002ce4: 35df1863 bne t5,t4,80003034 - -0000000080002ce8 : - 80002ce8: 00100093 li ra,1 - 80002cec: 00700113 li sp,7 - 80002cf0: 002090bb sllw ra,ra,sp - 80002cf4: 08000e93 li t4,128 - 80002cf8: 01600193 li gp,22 - 80002cfc: 33d09c63 bne ra,t4,80003034 - -0000000080002d00 : - 80002d00: 00100093 li ra,1 - 80002d04: 00e00113 li sp,14 - 80002d08: 0020913b sllw sp,ra,sp - 80002d0c: 00004eb7 lui t4,0x4 - 80002d10: 01700193 li gp,23 - 80002d14: 33d11063 bne sp,t4,80003034 - -0000000080002d18 : - 80002d18: 00300093 li ra,3 - 80002d1c: 001090bb sllw ra,ra,ra - 80002d20: 01800e93 li t4,24 - 80002d24: 01800193 li gp,24 - 80002d28: 31d09663 bne ra,t4,80003034 - -0000000080002d2c : - 80002d2c: 00000213 li tp,0 - 80002d30: 00100093 li ra,1 - 80002d34: 00700113 li sp,7 - 80002d38: 00209f3b sllw t5,ra,sp - 80002d3c: 000f0313 mv t1,t5 - 80002d40: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d44: 00200293 li t0,2 - 80002d48: fe5214e3 bne tp,t0,80002d30 - 80002d4c: 08000e93 li t4,128 - 80002d50: 01900193 li gp,25 - 80002d54: 2fd31063 bne t1,t4,80003034 - -0000000080002d58 : - 80002d58: 00000213 li tp,0 - 80002d5c: 00100093 li ra,1 - 80002d60: 00e00113 li sp,14 - 80002d64: 00209f3b sllw t5,ra,sp - 80002d68: 00000013 nop - 80002d6c: 000f0313 mv t1,t5 - 80002d70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d74: 00200293 li t0,2 - 80002d78: fe5212e3 bne tp,t0,80002d5c - 80002d7c: 00004eb7 lui t4,0x4 - 80002d80: 01a00193 li gp,26 - 80002d84: 2bd31863 bne t1,t4,80003034 - -0000000080002d88 : - 80002d88: 00000213 li tp,0 - 80002d8c: 00100093 li ra,1 - 80002d90: 01f00113 li sp,31 - 80002d94: 00209f3b sllw t5,ra,sp - 80002d98: 00000013 nop - 80002d9c: 00000013 nop - 80002da0: 000f0313 mv t1,t5 - 80002da4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002da8: 00200293 li t0,2 - 80002dac: fe5210e3 bne tp,t0,80002d8c - 80002db0: 80000eb7 lui t4,0x80000 - 80002db4: 01b00193 li gp,27 - 80002db8: 27d31e63 bne t1,t4,80003034 - -0000000080002dbc : - 80002dbc: 00000213 li tp,0 - 80002dc0: 00100093 li ra,1 - 80002dc4: 00700113 li sp,7 - 80002dc8: 00209f3b sllw t5,ra,sp - 80002dcc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dd0: 00200293 li t0,2 - 80002dd4: fe5216e3 bne tp,t0,80002dc0 - 80002dd8: 08000e93 li t4,128 - 80002ddc: 01c00193 li gp,28 - 80002de0: 25df1a63 bne t5,t4,80003034 - -0000000080002de4 : - 80002de4: 00000213 li tp,0 - 80002de8: 00100093 li ra,1 - 80002dec: 00e00113 li sp,14 - 80002df0: 00000013 nop - 80002df4: 00209f3b sllw t5,ra,sp - 80002df8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dfc: 00200293 li t0,2 - 80002e00: fe5214e3 bne tp,t0,80002de8 - 80002e04: 00004eb7 lui t4,0x4 - 80002e08: 01d00193 li gp,29 - 80002e0c: 23df1463 bne t5,t4,80003034 - -0000000080002e10 : - 80002e10: 00000213 li tp,0 - 80002e14: 00100093 li ra,1 - 80002e18: 01f00113 li sp,31 - 80002e1c: 00000013 nop - 80002e20: 00000013 nop - 80002e24: 00209f3b sllw t5,ra,sp - 80002e28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e2c: 00200293 li t0,2 - 80002e30: fe5212e3 bne tp,t0,80002e14 - 80002e34: 80000eb7 lui t4,0x80000 - 80002e38: 01e00193 li gp,30 - 80002e3c: 1fdf1c63 bne t5,t4,80003034 - -0000000080002e40 : - 80002e40: 00000213 li tp,0 - 80002e44: 00100093 li ra,1 - 80002e48: 00000013 nop - 80002e4c: 00700113 li sp,7 - 80002e50: 00209f3b sllw t5,ra,sp - 80002e54: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e58: 00200293 li t0,2 - 80002e5c: fe5214e3 bne tp,t0,80002e44 - 80002e60: 08000e93 li t4,128 - 80002e64: 01f00193 li gp,31 - 80002e68: 1ddf1663 bne t5,t4,80003034 - -0000000080002e6c : - 80002e6c: 00000213 li tp,0 - 80002e70: 00100093 li ra,1 - 80002e74: 00000013 nop - 80002e78: 00e00113 li sp,14 - 80002e7c: 00000013 nop - 80002e80: 00209f3b sllw t5,ra,sp - 80002e84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e88: 00200293 li t0,2 - 80002e8c: fe5212e3 bne tp,t0,80002e70 - 80002e90: 00004eb7 lui t4,0x4 - 80002e94: 02000193 li gp,32 - 80002e98: 19df1e63 bne t5,t4,80003034 - -0000000080002e9c : - 80002e9c: 00000213 li tp,0 - 80002ea0: 00100093 li ra,1 - 80002ea4: 00000013 nop - 80002ea8: 00000013 nop - 80002eac: 01f00113 li sp,31 - 80002eb0: 00209f3b sllw t5,ra,sp - 80002eb4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002eb8: 00200293 li t0,2 - 80002ebc: fe5212e3 bne tp,t0,80002ea0 - 80002ec0: 80000eb7 lui t4,0x80000 - 80002ec4: 02100193 li gp,33 - 80002ec8: 17df1663 bne t5,t4,80003034 - -0000000080002ecc : - 80002ecc: 00000213 li tp,0 - 80002ed0: 00700113 li sp,7 - 80002ed4: 00100093 li ra,1 - 80002ed8: 00209f3b sllw t5,ra,sp - 80002edc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ee0: 00200293 li t0,2 - 80002ee4: fe5216e3 bne tp,t0,80002ed0 - 80002ee8: 08000e93 li t4,128 - 80002eec: 02200193 li gp,34 - 80002ef0: 15df1263 bne t5,t4,80003034 - -0000000080002ef4 : - 80002ef4: 00000213 li tp,0 - 80002ef8: 00e00113 li sp,14 - 80002efc: 00100093 li ra,1 - 80002f00: 00000013 nop - 80002f04: 00209f3b sllw t5,ra,sp - 80002f08: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f0c: 00200293 li t0,2 - 80002f10: fe5214e3 bne tp,t0,80002ef8 - 80002f14: 00004eb7 lui t4,0x4 - 80002f18: 02300193 li gp,35 - 80002f1c: 11df1c63 bne t5,t4,80003034 - -0000000080002f20 : - 80002f20: 00000213 li tp,0 - 80002f24: 01f00113 li sp,31 - 80002f28: 00100093 li ra,1 - 80002f2c: 00000013 nop - 80002f30: 00000013 nop - 80002f34: 00209f3b sllw t5,ra,sp - 80002f38: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f3c: 00200293 li t0,2 - 80002f40: fe5212e3 bne tp,t0,80002f24 - 80002f44: 80000eb7 lui t4,0x80000 - 80002f48: 02400193 li gp,36 - 80002f4c: 0fdf1463 bne t5,t4,80003034 - -0000000080002f50 : - 80002f50: 00000213 li tp,0 - 80002f54: 00700113 li sp,7 - 80002f58: 00000013 nop - 80002f5c: 00100093 li ra,1 - 80002f60: 00209f3b sllw t5,ra,sp - 80002f64: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f68: 00200293 li t0,2 - 80002f6c: fe5214e3 bne tp,t0,80002f54 - 80002f70: 08000e93 li t4,128 - 80002f74: 02500193 li gp,37 - 80002f78: 0bdf1e63 bne t5,t4,80003034 - -0000000080002f7c : - 80002f7c: 00000213 li tp,0 - 80002f80: 00e00113 li sp,14 - 80002f84: 00000013 nop - 80002f88: 00100093 li ra,1 - 80002f8c: 00000013 nop - 80002f90: 00209f3b sllw t5,ra,sp - 80002f94: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f98: 00200293 li t0,2 - 80002f9c: fe5212e3 bne tp,t0,80002f80 - 80002fa0: 00004eb7 lui t4,0x4 - 80002fa4: 02600193 li gp,38 - 80002fa8: 09df1663 bne t5,t4,80003034 - -0000000080002fac : - 80002fac: 00000213 li tp,0 - 80002fb0: 01f00113 li sp,31 - 80002fb4: 00000013 nop - 80002fb8: 00000013 nop - 80002fbc: 00100093 li ra,1 - 80002fc0: 00209f3b sllw t5,ra,sp - 80002fc4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002fc8: 00200293 li t0,2 - 80002fcc: fe5212e3 bne tp,t0,80002fb0 - 80002fd0: 80000eb7 lui t4,0x80000 - 80002fd4: 02700193 li gp,39 - 80002fd8: 05df1e63 bne t5,t4,80003034 - -0000000080002fdc : - 80002fdc: 00f00093 li ra,15 - 80002fe0: 0010113b sllw sp,zero,ra - 80002fe4: 00000e93 li t4,0 - 80002fe8: 02800193 li gp,40 - 80002fec: 05d11463 bne sp,t4,80003034 - -0000000080002ff0 : - 80002ff0: 02000093 li ra,32 - 80002ff4: 0000913b sllw sp,ra,zero - 80002ff8: 02000e93 li t4,32 - 80002ffc: 02900193 li gp,41 - 80003000: 03d11a63 bne sp,t4,80003034 - -0000000080003004 : - 80003004: 000010bb sllw ra,zero,zero - 80003008: 00000e93 li t4,0 - 8000300c: 02a00193 li gp,42 - 80003010: 03d09263 bne ra,t4,80003034 - -0000000080003014 : - 80003014: 40000093 li ra,1024 - 80003018: 00001137 lui sp,0x1 - 8000301c: 8001011b addiw sp,sp,-2048 - 80003020: 0020903b sllw zero,ra,sp - 80003024: 00000e93 li t4,0 - 80003028: 02b00193 li gp,43 - 8000302c: 01d01463 bne zero,t4,80003034 - 80003030: 00301a63 bne zero,gp,80003044 - -0000000080003034 : - 80003034: 00119513 slli a0,gp,0x1 - 80003038: 00050063 beqz a0,80003038 - 8000303c: 00156513 ori a0,a0,1 - 80003040: 00000073 ecall - -0000000080003044 : - 80003044: 00100513 li a0,1 - 80003048: 00000073 ecall - 8000304c: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-sllw.elf b/test/riscv/tests/rv64ui-v-sllw.elf deleted file mode 100644 index 9ae693bd..00000000 Binary files a/test/riscv/tests/rv64ui-v-sllw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-slt.dump b/test/riscv/tests/rv64ui-v-slt.dump deleted file mode 100644 index dd39ae72..00000000 --- a/test/riscv/tests/rv64ui-v-slt.dump +++ /dev/null @@ -1,1218 +0,0 @@ - -rv64ui-v-slt: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: b5868693 addi a3,a3,-1192 # 80002fb0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: b8c60613 addi a2,a2,-1140 # 80003040 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: b5460613 addi a2,a2,-1196 # 80003058 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: aa468693 addi a3,a3,-1372 # 80002ff8 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: ac068693 addi a3,a3,-1344 # 80003130 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: a4060613 addi a2,a2,-1472 # 80003108 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: 97468693 addi a3,a3,-1676 # 80003160 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 89468693 addi a3,a3,-1900 # 800030d0 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00001697 auipc a3,0x1 - 80002878: 82468693 addi a3,a3,-2012 # 80003098 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 00300793 li a5,3 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0c8c27b7 lui a5,0xc8c2 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: a2878793 addi a5,a5,-1496 # c8c1a28 <_start-0x7373e5d8> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000093 li ra,0 - 80002acc: 00000113 li sp,0 - 80002ad0: 0020af33 slt t5,ra,sp - 80002ad4: 00000e93 li t4,0 - 80002ad8: 00200193 li gp,2 - 80002adc: 4bdf1a63 bne t5,t4,80002f90 - -0000000080002ae0 : - 80002ae0: 00100093 li ra,1 - 80002ae4: 00100113 li sp,1 - 80002ae8: 0020af33 slt t5,ra,sp - 80002aec: 00000e93 li t4,0 - 80002af0: 00300193 li gp,3 - 80002af4: 49df1e63 bne t5,t4,80002f90 - -0000000080002af8 : - 80002af8: 00300093 li ra,3 - 80002afc: 00700113 li sp,7 - 80002b00: 0020af33 slt t5,ra,sp - 80002b04: 00100e93 li t4,1 - 80002b08: 00400193 li gp,4 - 80002b0c: 49df1263 bne t5,t4,80002f90 - -0000000080002b10 : - 80002b10: 00700093 li ra,7 - 80002b14: 00300113 li sp,3 - 80002b18: 0020af33 slt t5,ra,sp - 80002b1c: 00000e93 li t4,0 - 80002b20: 00500193 li gp,5 - 80002b24: 47df1663 bne t5,t4,80002f90 - -0000000080002b28 : - 80002b28: 00000093 li ra,0 - 80002b2c: ffff8137 lui sp,0xffff8 - 80002b30: 0020af33 slt t5,ra,sp - 80002b34: 00000e93 li t4,0 - 80002b38: 00600193 li gp,6 - 80002b3c: 45df1a63 bne t5,t4,80002f90 - -0000000080002b40 : - 80002b40: 800000b7 lui ra,0x80000 - 80002b44: 00000113 li sp,0 - 80002b48: 0020af33 slt t5,ra,sp - 80002b4c: 00100e93 li t4,1 - 80002b50: 00700193 li gp,7 - 80002b54: 43df1e63 bne t5,t4,80002f90 - -0000000080002b58 : - 80002b58: 800000b7 lui ra,0x80000 - 80002b5c: ffff8137 lui sp,0xffff8 - 80002b60: 0020af33 slt t5,ra,sp - 80002b64: 00100e93 li t4,1 - 80002b68: 00800193 li gp,8 - 80002b6c: 43df1263 bne t5,t4,80002f90 - -0000000080002b70 : - 80002b70: 00000093 li ra,0 - 80002b74: 00008137 lui sp,0x8 - 80002b78: fff1011b addiw sp,sp,-1 - 80002b7c: 0020af33 slt t5,ra,sp - 80002b80: 00100e93 li t4,1 - 80002b84: 00900193 li gp,9 - 80002b88: 41df1463 bne t5,t4,80002f90 - -0000000080002b8c : - 80002b8c: 800000b7 lui ra,0x80000 - 80002b90: fff0809b addiw ra,ra,-1 - 80002b94: 00000113 li sp,0 - 80002b98: 0020af33 slt t5,ra,sp - 80002b9c: 00000e93 li t4,0 - 80002ba0: 00a00193 li gp,10 - 80002ba4: 3fdf1663 bne t5,t4,80002f90 - -0000000080002ba8 : - 80002ba8: 800000b7 lui ra,0x80000 - 80002bac: fff0809b addiw ra,ra,-1 - 80002bb0: 00008137 lui sp,0x8 - 80002bb4: fff1011b addiw sp,sp,-1 - 80002bb8: 0020af33 slt t5,ra,sp - 80002bbc: 00000e93 li t4,0 - 80002bc0: 00b00193 li gp,11 - 80002bc4: 3ddf1663 bne t5,t4,80002f90 - -0000000080002bc8 : - 80002bc8: 800000b7 lui ra,0x80000 - 80002bcc: 00008137 lui sp,0x8 - 80002bd0: fff1011b addiw sp,sp,-1 - 80002bd4: 0020af33 slt t5,ra,sp - 80002bd8: 00100e93 li t4,1 - 80002bdc: 00c00193 li gp,12 - 80002be0: 3bdf1863 bne t5,t4,80002f90 - -0000000080002be4 : - 80002be4: 800000b7 lui ra,0x80000 - 80002be8: fff0809b addiw ra,ra,-1 - 80002bec: ffff8137 lui sp,0xffff8 - 80002bf0: 0020af33 slt t5,ra,sp - 80002bf4: 00000e93 li t4,0 - 80002bf8: 00d00193 li gp,13 - 80002bfc: 39df1a63 bne t5,t4,80002f90 - -0000000080002c00 : - 80002c00: 00000093 li ra,0 - 80002c04: fff00113 li sp,-1 - 80002c08: 0020af33 slt t5,ra,sp - 80002c0c: 00000e93 li t4,0 - 80002c10: 00e00193 li gp,14 - 80002c14: 37df1e63 bne t5,t4,80002f90 - -0000000080002c18 : - 80002c18: fff00093 li ra,-1 - 80002c1c: 00100113 li sp,1 - 80002c20: 0020af33 slt t5,ra,sp - 80002c24: 00100e93 li t4,1 - 80002c28: 00f00193 li gp,15 - 80002c2c: 37df1263 bne t5,t4,80002f90 - -0000000080002c30 : - 80002c30: fff00093 li ra,-1 - 80002c34: fff00113 li sp,-1 - 80002c38: 0020af33 slt t5,ra,sp - 80002c3c: 00000e93 li t4,0 - 80002c40: 01000193 li gp,16 - 80002c44: 35df1663 bne t5,t4,80002f90 - -0000000080002c48 : - 80002c48: 00e00093 li ra,14 - 80002c4c: 00d00113 li sp,13 - 80002c50: 0020a0b3 slt ra,ra,sp - 80002c54: 00000e93 li t4,0 - 80002c58: 01100193 li gp,17 - 80002c5c: 33d09a63 bne ra,t4,80002f90 - -0000000080002c60 : - 80002c60: 00b00093 li ra,11 - 80002c64: 00d00113 li sp,13 - 80002c68: 0020a133 slt sp,ra,sp - 80002c6c: 00100e93 li t4,1 - 80002c70: 01200193 li gp,18 - 80002c74: 31d11e63 bne sp,t4,80002f90 - -0000000080002c78 : - 80002c78: 00d00093 li ra,13 - 80002c7c: 0010a0b3 slt ra,ra,ra - 80002c80: 00000e93 li t4,0 - 80002c84: 01300193 li gp,19 - 80002c88: 31d09463 bne ra,t4,80002f90 - -0000000080002c8c : - 80002c8c: 00000213 li tp,0 - 80002c90: 00b00093 li ra,11 - 80002c94: 00d00113 li sp,13 - 80002c98: 0020af33 slt t5,ra,sp - 80002c9c: 000f0313 mv t1,t5 - 80002ca0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ca4: 00200293 li t0,2 - 80002ca8: fe5214e3 bne tp,t0,80002c90 - 80002cac: 00100e93 li t4,1 - 80002cb0: 01400193 li gp,20 - 80002cb4: 2dd31e63 bne t1,t4,80002f90 - -0000000080002cb8 : - 80002cb8: 00000213 li tp,0 - 80002cbc: 00e00093 li ra,14 - 80002cc0: 00d00113 li sp,13 - 80002cc4: 0020af33 slt t5,ra,sp - 80002cc8: 00000013 nop - 80002ccc: 000f0313 mv t1,t5 - 80002cd0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cd4: 00200293 li t0,2 - 80002cd8: fe5212e3 bne tp,t0,80002cbc - 80002cdc: 00000e93 li t4,0 - 80002ce0: 01500193 li gp,21 - 80002ce4: 2bd31663 bne t1,t4,80002f90 - -0000000080002ce8 : - 80002ce8: 00000213 li tp,0 - 80002cec: 00c00093 li ra,12 - 80002cf0: 00d00113 li sp,13 - 80002cf4: 0020af33 slt t5,ra,sp - 80002cf8: 00000013 nop - 80002cfc: 00000013 nop - 80002d00: 000f0313 mv t1,t5 - 80002d04: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d08: 00200293 li t0,2 - 80002d0c: fe5210e3 bne tp,t0,80002cec - 80002d10: 00100e93 li t4,1 - 80002d14: 01600193 li gp,22 - 80002d18: 27d31c63 bne t1,t4,80002f90 - -0000000080002d1c : - 80002d1c: 00000213 li tp,0 - 80002d20: 00e00093 li ra,14 - 80002d24: 00d00113 li sp,13 - 80002d28: 0020af33 slt t5,ra,sp - 80002d2c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d30: 00200293 li t0,2 - 80002d34: fe5216e3 bne tp,t0,80002d20 - 80002d38: 00000e93 li t4,0 - 80002d3c: 01700193 li gp,23 - 80002d40: 25df1863 bne t5,t4,80002f90 - -0000000080002d44 : - 80002d44: 00000213 li tp,0 - 80002d48: 00b00093 li ra,11 - 80002d4c: 00d00113 li sp,13 - 80002d50: 00000013 nop - 80002d54: 0020af33 slt t5,ra,sp - 80002d58: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d5c: 00200293 li t0,2 - 80002d60: fe5214e3 bne tp,t0,80002d48 - 80002d64: 00100e93 li t4,1 - 80002d68: 01800193 li gp,24 - 80002d6c: 23df1263 bne t5,t4,80002f90 - -0000000080002d70 : - 80002d70: 00000213 li tp,0 - 80002d74: 00f00093 li ra,15 - 80002d78: 00d00113 li sp,13 - 80002d7c: 00000013 nop - 80002d80: 00000013 nop - 80002d84: 0020af33 slt t5,ra,sp - 80002d88: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d8c: 00200293 li t0,2 - 80002d90: fe5212e3 bne tp,t0,80002d74 - 80002d94: 00000e93 li t4,0 - 80002d98: 01900193 li gp,25 - 80002d9c: 1fdf1a63 bne t5,t4,80002f90 - -0000000080002da0 : - 80002da0: 00000213 li tp,0 - 80002da4: 00a00093 li ra,10 - 80002da8: 00000013 nop - 80002dac: 00d00113 li sp,13 - 80002db0: 0020af33 slt t5,ra,sp - 80002db4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002db8: 00200293 li t0,2 - 80002dbc: fe5214e3 bne tp,t0,80002da4 - 80002dc0: 00100e93 li t4,1 - 80002dc4: 01a00193 li gp,26 - 80002dc8: 1ddf1463 bne t5,t4,80002f90 - -0000000080002dcc : - 80002dcc: 00000213 li tp,0 - 80002dd0: 01000093 li ra,16 - 80002dd4: 00000013 nop - 80002dd8: 00d00113 li sp,13 - 80002ddc: 00000013 nop - 80002de0: 0020af33 slt t5,ra,sp - 80002de4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002de8: 00200293 li t0,2 - 80002dec: fe5212e3 bne tp,t0,80002dd0 - 80002df0: 00000e93 li t4,0 - 80002df4: 01b00193 li gp,27 - 80002df8: 19df1c63 bne t5,t4,80002f90 - -0000000080002dfc : - 80002dfc: 00000213 li tp,0 - 80002e00: 00900093 li ra,9 - 80002e04: 00000013 nop - 80002e08: 00000013 nop - 80002e0c: 00d00113 li sp,13 - 80002e10: 0020af33 slt t5,ra,sp - 80002e14: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e18: 00200293 li t0,2 - 80002e1c: fe5212e3 bne tp,t0,80002e00 - 80002e20: 00100e93 li t4,1 - 80002e24: 01c00193 li gp,28 - 80002e28: 17df1463 bne t5,t4,80002f90 - -0000000080002e2c : - 80002e2c: 00000213 li tp,0 - 80002e30: 00d00113 li sp,13 - 80002e34: 01100093 li ra,17 - 80002e38: 0020af33 slt t5,ra,sp - 80002e3c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e40: 00200293 li t0,2 - 80002e44: fe5216e3 bne tp,t0,80002e30 - 80002e48: 00000e93 li t4,0 - 80002e4c: 01d00193 li gp,29 - 80002e50: 15df1063 bne t5,t4,80002f90 - -0000000080002e54 : - 80002e54: 00000213 li tp,0 - 80002e58: 00d00113 li sp,13 - 80002e5c: 00800093 li ra,8 - 80002e60: 00000013 nop - 80002e64: 0020af33 slt t5,ra,sp - 80002e68: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e6c: 00200293 li t0,2 - 80002e70: fe5214e3 bne tp,t0,80002e58 - 80002e74: 00100e93 li t4,1 - 80002e78: 01e00193 li gp,30 - 80002e7c: 11df1a63 bne t5,t4,80002f90 - -0000000080002e80 : - 80002e80: 00000213 li tp,0 - 80002e84: 00d00113 li sp,13 - 80002e88: 01200093 li ra,18 - 80002e8c: 00000013 nop - 80002e90: 00000013 nop - 80002e94: 0020af33 slt t5,ra,sp - 80002e98: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e9c: 00200293 li t0,2 - 80002ea0: fe5212e3 bne tp,t0,80002e84 - 80002ea4: 00000e93 li t4,0 - 80002ea8: 01f00193 li gp,31 - 80002eac: 0fdf1263 bne t5,t4,80002f90 - -0000000080002eb0 : - 80002eb0: 00000213 li tp,0 - 80002eb4: 00d00113 li sp,13 - 80002eb8: 00000013 nop - 80002ebc: 00700093 li ra,7 - 80002ec0: 0020af33 slt t5,ra,sp - 80002ec4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ec8: 00200293 li t0,2 - 80002ecc: fe5214e3 bne tp,t0,80002eb4 - 80002ed0: 00100e93 li t4,1 - 80002ed4: 02000193 li gp,32 - 80002ed8: 0bdf1c63 bne t5,t4,80002f90 - -0000000080002edc : - 80002edc: 00000213 li tp,0 - 80002ee0: 00d00113 li sp,13 - 80002ee4: 00000013 nop - 80002ee8: 01300093 li ra,19 - 80002eec: 00000013 nop - 80002ef0: 0020af33 slt t5,ra,sp - 80002ef4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ef8: 00200293 li t0,2 - 80002efc: fe5212e3 bne tp,t0,80002ee0 - 80002f00: 00000e93 li t4,0 - 80002f04: 02100193 li gp,33 - 80002f08: 09df1463 bne t5,t4,80002f90 - -0000000080002f0c : - 80002f0c: 00000213 li tp,0 - 80002f10: 00d00113 li sp,13 - 80002f14: 00000013 nop - 80002f18: 00000013 nop - 80002f1c: 00600093 li ra,6 - 80002f20: 0020af33 slt t5,ra,sp - 80002f24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f28: 00200293 li t0,2 - 80002f2c: fe5212e3 bne tp,t0,80002f10 - 80002f30: 00100e93 li t4,1 - 80002f34: 02200193 li gp,34 - 80002f38: 05df1c63 bne t5,t4,80002f90 - -0000000080002f3c : - 80002f3c: fff00093 li ra,-1 - 80002f40: 00102133 sgtz sp,ra - 80002f44: 00000e93 li t4,0 - 80002f48: 02300193 li gp,35 - 80002f4c: 05d11263 bne sp,t4,80002f90 - -0000000080002f50 : - 80002f50: fff00093 li ra,-1 - 80002f54: 0000a133 sltz sp,ra - 80002f58: 00100e93 li t4,1 - 80002f5c: 02400193 li gp,36 - 80002f60: 03d11863 bne sp,t4,80002f90 - -0000000080002f64 : - 80002f64: 000020b3 sltz ra,zero - 80002f68: 00000e93 li t4,0 - 80002f6c: 02500193 li gp,37 - 80002f70: 03d09063 bne ra,t4,80002f90 - -0000000080002f74 : - 80002f74: 01000093 li ra,16 - 80002f78: 01e00113 li sp,30 - 80002f7c: 0020a033 slt zero,ra,sp - 80002f80: 00000e93 li t4,0 - 80002f84: 02600193 li gp,38 - 80002f88: 01d01463 bne zero,t4,80002f90 - 80002f8c: 00301a63 bne zero,gp,80002fa0 - -0000000080002f90 : - 80002f90: 00119513 slli a0,gp,0x1 - 80002f94: 00050063 beqz a0,80002f94 - 80002f98: 00156513 ori a0,a0,1 - 80002f9c: 00000073 ecall - -0000000080002fa0 : - 80002fa0: 00100513 li a0,1 - 80002fa4: 00000073 ecall - 80002fa8: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-slt.elf b/test/riscv/tests/rv64ui-v-slt.elf deleted file mode 100644 index 318b70db..00000000 Binary files a/test/riscv/tests/rv64ui-v-slt.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-slti.dump b/test/riscv/tests/rv64ui-v-slti.dump deleted file mode 100644 index 56b39654..00000000 --- a/test/riscv/tests/rv64ui-v-slti.dump +++ /dev/null @@ -1,1043 +0,0 @@ - -rv64ui-v-slti: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 90068693 addi a3,a3,-1792 # 80002d58 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 93460613 addi a2,a2,-1740 # 80002de8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 8fc60613 addi a2,a2,-1796 # 80002e00 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 84c68693 addi a3,a3,-1972 # 80002da0 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 86868693 addi a3,a3,-1944 # 80002ed8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 7e860613 addi a2,a2,2024 # 80002eb0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 71c68693 addi a3,a3,1820 # 80002f08 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 63c68693 addi a3,a3,1596 # 80002e78 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 5cc68693 addi a3,a3,1484 # 80002e40 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 00800793 li a5,8 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 01e147b7 lui a5,0x1e14 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 4e578793 addi a5,a5,1253 # 1e144e5 <_start-0x7e1ebb1b> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000093 li ra,0 - 80002acc: 0000af13 slti t5,ra,0 - 80002ad0: 00000e93 li t4,0 - 80002ad4: 00200193 li gp,2 - 80002ad8: 27df1263 bne t5,t4,80002d3c - -0000000080002adc : - 80002adc: 00100093 li ra,1 - 80002ae0: 0010af13 slti t5,ra,1 - 80002ae4: 00000e93 li t4,0 - 80002ae8: 00300193 li gp,3 - 80002aec: 25df1863 bne t5,t4,80002d3c - -0000000080002af0 : - 80002af0: 00300093 li ra,3 - 80002af4: 0070af13 slti t5,ra,7 - 80002af8: 00100e93 li t4,1 - 80002afc: 00400193 li gp,4 - 80002b00: 23df1e63 bne t5,t4,80002d3c - -0000000080002b04 : - 80002b04: 00700093 li ra,7 - 80002b08: 0030af13 slti t5,ra,3 - 80002b0c: 00000e93 li t4,0 - 80002b10: 00500193 li gp,5 - 80002b14: 23df1463 bne t5,t4,80002d3c - -0000000080002b18 : - 80002b18: 00000093 li ra,0 - 80002b1c: 8000af13 slti t5,ra,-2048 - 80002b20: 00000e93 li t4,0 - 80002b24: 00600193 li gp,6 - 80002b28: 21df1a63 bne t5,t4,80002d3c - -0000000080002b2c : - 80002b2c: 800000b7 lui ra,0x80000 - 80002b30: 0000af13 slti t5,ra,0 - 80002b34: 00100e93 li t4,1 - 80002b38: 00700193 li gp,7 - 80002b3c: 21df1063 bne t5,t4,80002d3c - -0000000080002b40 : - 80002b40: 800000b7 lui ra,0x80000 - 80002b44: 8000af13 slti t5,ra,-2048 - 80002b48: 00100e93 li t4,1 - 80002b4c: 00800193 li gp,8 - 80002b50: 1fdf1663 bne t5,t4,80002d3c - -0000000080002b54 : - 80002b54: 00000093 li ra,0 - 80002b58: 7ff0af13 slti t5,ra,2047 - 80002b5c: 00100e93 li t4,1 - 80002b60: 00900193 li gp,9 - 80002b64: 1ddf1c63 bne t5,t4,80002d3c - -0000000080002b68 : - 80002b68: 800000b7 lui ra,0x80000 - 80002b6c: fff0809b addiw ra,ra,-1 - 80002b70: 0000af13 slti t5,ra,0 - 80002b74: 00000e93 li t4,0 - 80002b78: 00a00193 li gp,10 - 80002b7c: 1ddf1063 bne t5,t4,80002d3c - -0000000080002b80 : - 80002b80: 800000b7 lui ra,0x80000 - 80002b84: fff0809b addiw ra,ra,-1 - 80002b88: 7ff0af13 slti t5,ra,2047 - 80002b8c: 00000e93 li t4,0 - 80002b90: 00b00193 li gp,11 - 80002b94: 1bdf1463 bne t5,t4,80002d3c - -0000000080002b98 : - 80002b98: 800000b7 lui ra,0x80000 - 80002b9c: 7ff0af13 slti t5,ra,2047 - 80002ba0: 00100e93 li t4,1 - 80002ba4: 00c00193 li gp,12 - 80002ba8: 19df1a63 bne t5,t4,80002d3c - -0000000080002bac : - 80002bac: 800000b7 lui ra,0x80000 - 80002bb0: fff0809b addiw ra,ra,-1 - 80002bb4: 8000af13 slti t5,ra,-2048 - 80002bb8: 00000e93 li t4,0 - 80002bbc: 00d00193 li gp,13 - 80002bc0: 17df1e63 bne t5,t4,80002d3c - -0000000080002bc4 : - 80002bc4: 00000093 li ra,0 - 80002bc8: fff0af13 slti t5,ra,-1 - 80002bcc: 00000e93 li t4,0 - 80002bd0: 00e00193 li gp,14 - 80002bd4: 17df1463 bne t5,t4,80002d3c - -0000000080002bd8 : - 80002bd8: fff00093 li ra,-1 - 80002bdc: 0010af13 slti t5,ra,1 - 80002be0: 00100e93 li t4,1 - 80002be4: 00f00193 li gp,15 - 80002be8: 15df1a63 bne t5,t4,80002d3c - -0000000080002bec : - 80002bec: fff00093 li ra,-1 - 80002bf0: fff0af13 slti t5,ra,-1 - 80002bf4: 00000e93 li t4,0 - 80002bf8: 01000193 li gp,16 - 80002bfc: 15df1063 bne t5,t4,80002d3c - -0000000080002c00 : - 80002c00: 00b00093 li ra,11 - 80002c04: 00d0a093 slti ra,ra,13 - 80002c08: 00100e93 li t4,1 - 80002c0c: 01100193 li gp,17 - 80002c10: 13d09663 bne ra,t4,80002d3c - -0000000080002c14 : - 80002c14: 00000213 li tp,0 - 80002c18: 00f00093 li ra,15 - 80002c1c: 00a0af13 slti t5,ra,10 - 80002c20: 000f0313 mv t1,t5 - 80002c24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c28: 00200293 li t0,2 - 80002c2c: fe5216e3 bne tp,t0,80002c18 - 80002c30: 00000e93 li t4,0 - 80002c34: 01200193 li gp,18 - 80002c38: 11d31263 bne t1,t4,80002d3c - -0000000080002c3c : - 80002c3c: 00000213 li tp,0 - 80002c40: 00a00093 li ra,10 - 80002c44: 0100af13 slti t5,ra,16 - 80002c48: 00000013 nop - 80002c4c: 000f0313 mv t1,t5 - 80002c50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c54: 00200293 li t0,2 - 80002c58: fe5214e3 bne tp,t0,80002c40 - 80002c5c: 00100e93 li t4,1 - 80002c60: 01300193 li gp,19 - 80002c64: 0dd31c63 bne t1,t4,80002d3c - -0000000080002c68 : - 80002c68: 00000213 li tp,0 - 80002c6c: 01000093 li ra,16 - 80002c70: 0090af13 slti t5,ra,9 - 80002c74: 00000013 nop - 80002c78: 00000013 nop - 80002c7c: 000f0313 mv t1,t5 - 80002c80: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c84: 00200293 li t0,2 - 80002c88: fe5212e3 bne tp,t0,80002c6c - 80002c8c: 00000e93 li t4,0 - 80002c90: 01400193 li gp,20 - 80002c94: 0bd31463 bne t1,t4,80002d3c - -0000000080002c98 : - 80002c98: 00000213 li tp,0 - 80002c9c: 00b00093 li ra,11 - 80002ca0: 00f0af13 slti t5,ra,15 - 80002ca4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ca8: 00200293 li t0,2 - 80002cac: fe5218e3 bne tp,t0,80002c9c - 80002cb0: 00100e93 li t4,1 - 80002cb4: 01500193 li gp,21 - 80002cb8: 09df1263 bne t5,t4,80002d3c - -0000000080002cbc : - 80002cbc: 00000213 li tp,0 - 80002cc0: 01100093 li ra,17 - 80002cc4: 00000013 nop - 80002cc8: 0080af13 slti t5,ra,8 - 80002ccc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cd0: 00200293 li t0,2 - 80002cd4: fe5216e3 bne tp,t0,80002cc0 - 80002cd8: 00000e93 li t4,0 - 80002cdc: 01600193 li gp,22 - 80002ce0: 05df1e63 bne t5,t4,80002d3c - -0000000080002ce4 : - 80002ce4: 00000213 li tp,0 - 80002ce8: 00c00093 li ra,12 - 80002cec: 00000013 nop - 80002cf0: 00000013 nop - 80002cf4: 00e0af13 slti t5,ra,14 - 80002cf8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cfc: 00200293 li t0,2 - 80002d00: fe5214e3 bne tp,t0,80002ce8 - 80002d04: 00100e93 li t4,1 - 80002d08: 01700193 li gp,23 - 80002d0c: 03df1863 bne t5,t4,80002d3c - -0000000080002d10 : - 80002d10: fff02093 slti ra,zero,-1 - 80002d14: 00000e93 li t4,0 - 80002d18: 01800193 li gp,24 - 80002d1c: 03d09063 bne ra,t4,80002d3c - -0000000080002d20 : - 80002d20: 00ff00b7 lui ra,0xff0 - 80002d24: 0ff0809b addiw ra,ra,255 - 80002d28: fff0a013 slti zero,ra,-1 - 80002d2c: 00000e93 li t4,0 - 80002d30: 01900193 li gp,25 - 80002d34: 01d01463 bne zero,t4,80002d3c - 80002d38: 00301a63 bne zero,gp,80002d4c - -0000000080002d3c : - 80002d3c: 00119513 slli a0,gp,0x1 - 80002d40: 00050063 beqz a0,80002d40 - 80002d44: 00156513 ori a0,a0,1 - 80002d48: 00000073 ecall - -0000000080002d4c : - 80002d4c: 00100513 li a0,1 - 80002d50: 00000073 ecall - 80002d54: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-slti.elf b/test/riscv/tests/rv64ui-v-slti.elf deleted file mode 100644 index 477b7049..00000000 Binary files a/test/riscv/tests/rv64ui-v-slti.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-sltiu.dump b/test/riscv/tests/rv64ui-v-sltiu.dump deleted file mode 100644 index 98f8b1a5..00000000 --- a/test/riscv/tests/rv64ui-v-sltiu.dump +++ /dev/null @@ -1,1043 +0,0 @@ - -rv64ui-v-sltiu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 90068693 addi a3,a3,-1792 # 80002d58 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 93460613 addi a2,a2,-1740 # 80002de8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 8fc60613 addi a2,a2,-1796 # 80002e00 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 84c68693 addi a3,a3,-1972 # 80002da0 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 86868693 addi a3,a3,-1944 # 80002ed8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 7e860613 addi a2,a2,2024 # 80002eb0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 71c68693 addi a3,a3,1820 # 80002f08 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 63c68693 addi a3,a3,1596 # 80002e78 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 5cc68693 addi a3,a3,1484 # 80002e40 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 02100793 li a5,33 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 04ec47b7 lui a5,0x4ec4 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: b3078793 addi a5,a5,-1232 # 4ec3b30 <_start-0x7b13c4d0> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000093 li ra,0 - 80002acc: 0000bf13 sltiu t5,ra,0 - 80002ad0: 00000e93 li t4,0 - 80002ad4: 00200193 li gp,2 - 80002ad8: 27df1263 bne t5,t4,80002d3c - -0000000080002adc : - 80002adc: 00100093 li ra,1 - 80002ae0: 0010bf13 seqz t5,ra - 80002ae4: 00000e93 li t4,0 - 80002ae8: 00300193 li gp,3 - 80002aec: 25df1863 bne t5,t4,80002d3c - -0000000080002af0 : - 80002af0: 00300093 li ra,3 - 80002af4: 0070bf13 sltiu t5,ra,7 - 80002af8: 00100e93 li t4,1 - 80002afc: 00400193 li gp,4 - 80002b00: 23df1e63 bne t5,t4,80002d3c - -0000000080002b04 : - 80002b04: 00700093 li ra,7 - 80002b08: 0030bf13 sltiu t5,ra,3 - 80002b0c: 00000e93 li t4,0 - 80002b10: 00500193 li gp,5 - 80002b14: 23df1463 bne t5,t4,80002d3c - -0000000080002b18 : - 80002b18: 00000093 li ra,0 - 80002b1c: 8000bf13 sltiu t5,ra,-2048 - 80002b20: 00100e93 li t4,1 - 80002b24: 00600193 li gp,6 - 80002b28: 21df1a63 bne t5,t4,80002d3c - -0000000080002b2c : - 80002b2c: 800000b7 lui ra,0x80000 - 80002b30: 0000bf13 sltiu t5,ra,0 - 80002b34: 00000e93 li t4,0 - 80002b38: 00700193 li gp,7 - 80002b3c: 21df1063 bne t5,t4,80002d3c - -0000000080002b40 : - 80002b40: 800000b7 lui ra,0x80000 - 80002b44: 8000bf13 sltiu t5,ra,-2048 - 80002b48: 00100e93 li t4,1 - 80002b4c: 00800193 li gp,8 - 80002b50: 1fdf1663 bne t5,t4,80002d3c - -0000000080002b54 : - 80002b54: 00000093 li ra,0 - 80002b58: 7ff0bf13 sltiu t5,ra,2047 - 80002b5c: 00100e93 li t4,1 - 80002b60: 00900193 li gp,9 - 80002b64: 1ddf1c63 bne t5,t4,80002d3c - -0000000080002b68 : - 80002b68: 800000b7 lui ra,0x80000 - 80002b6c: fff0809b addiw ra,ra,-1 - 80002b70: 0000bf13 sltiu t5,ra,0 - 80002b74: 00000e93 li t4,0 - 80002b78: 00a00193 li gp,10 - 80002b7c: 1ddf1063 bne t5,t4,80002d3c - -0000000080002b80 : - 80002b80: 800000b7 lui ra,0x80000 - 80002b84: fff0809b addiw ra,ra,-1 - 80002b88: 7ff0bf13 sltiu t5,ra,2047 - 80002b8c: 00000e93 li t4,0 - 80002b90: 00b00193 li gp,11 - 80002b94: 1bdf1463 bne t5,t4,80002d3c - -0000000080002b98 : - 80002b98: 800000b7 lui ra,0x80000 - 80002b9c: 7ff0bf13 sltiu t5,ra,2047 - 80002ba0: 00000e93 li t4,0 - 80002ba4: 00c00193 li gp,12 - 80002ba8: 19df1a63 bne t5,t4,80002d3c - -0000000080002bac : - 80002bac: 800000b7 lui ra,0x80000 - 80002bb0: fff0809b addiw ra,ra,-1 - 80002bb4: 8000bf13 sltiu t5,ra,-2048 - 80002bb8: 00100e93 li t4,1 - 80002bbc: 00d00193 li gp,13 - 80002bc0: 17df1e63 bne t5,t4,80002d3c - -0000000080002bc4 : - 80002bc4: 00000093 li ra,0 - 80002bc8: fff0bf13 sltiu t5,ra,-1 - 80002bcc: 00100e93 li t4,1 - 80002bd0: 00e00193 li gp,14 - 80002bd4: 17df1463 bne t5,t4,80002d3c - -0000000080002bd8 : - 80002bd8: fff00093 li ra,-1 - 80002bdc: 0010bf13 seqz t5,ra - 80002be0: 00000e93 li t4,0 - 80002be4: 00f00193 li gp,15 - 80002be8: 15df1a63 bne t5,t4,80002d3c - -0000000080002bec : - 80002bec: fff00093 li ra,-1 - 80002bf0: fff0bf13 sltiu t5,ra,-1 - 80002bf4: 00000e93 li t4,0 - 80002bf8: 01000193 li gp,16 - 80002bfc: 15df1063 bne t5,t4,80002d3c - -0000000080002c00 : - 80002c00: 00b00093 li ra,11 - 80002c04: 00d0b093 sltiu ra,ra,13 - 80002c08: 00100e93 li t4,1 - 80002c0c: 01100193 li gp,17 - 80002c10: 13d09663 bne ra,t4,80002d3c - -0000000080002c14 : - 80002c14: 00000213 li tp,0 - 80002c18: 00f00093 li ra,15 - 80002c1c: 00a0bf13 sltiu t5,ra,10 - 80002c20: 000f0313 mv t1,t5 - 80002c24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c28: 00200293 li t0,2 - 80002c2c: fe5216e3 bne tp,t0,80002c18 - 80002c30: 00000e93 li t4,0 - 80002c34: 01200193 li gp,18 - 80002c38: 11d31263 bne t1,t4,80002d3c - -0000000080002c3c : - 80002c3c: 00000213 li tp,0 - 80002c40: 00a00093 li ra,10 - 80002c44: 0100bf13 sltiu t5,ra,16 - 80002c48: 00000013 nop - 80002c4c: 000f0313 mv t1,t5 - 80002c50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c54: 00200293 li t0,2 - 80002c58: fe5214e3 bne tp,t0,80002c40 - 80002c5c: 00100e93 li t4,1 - 80002c60: 01300193 li gp,19 - 80002c64: 0dd31c63 bne t1,t4,80002d3c - -0000000080002c68 : - 80002c68: 00000213 li tp,0 - 80002c6c: 01000093 li ra,16 - 80002c70: 0090bf13 sltiu t5,ra,9 - 80002c74: 00000013 nop - 80002c78: 00000013 nop - 80002c7c: 000f0313 mv t1,t5 - 80002c80: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c84: 00200293 li t0,2 - 80002c88: fe5212e3 bne tp,t0,80002c6c - 80002c8c: 00000e93 li t4,0 - 80002c90: 01400193 li gp,20 - 80002c94: 0bd31463 bne t1,t4,80002d3c - -0000000080002c98 : - 80002c98: 00000213 li tp,0 - 80002c9c: 00b00093 li ra,11 - 80002ca0: 00f0bf13 sltiu t5,ra,15 - 80002ca4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ca8: 00200293 li t0,2 - 80002cac: fe5218e3 bne tp,t0,80002c9c - 80002cb0: 00100e93 li t4,1 - 80002cb4: 01500193 li gp,21 - 80002cb8: 09df1263 bne t5,t4,80002d3c - -0000000080002cbc : - 80002cbc: 00000213 li tp,0 - 80002cc0: 01100093 li ra,17 - 80002cc4: 00000013 nop - 80002cc8: 0080bf13 sltiu t5,ra,8 - 80002ccc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cd0: 00200293 li t0,2 - 80002cd4: fe5216e3 bne tp,t0,80002cc0 - 80002cd8: 00000e93 li t4,0 - 80002cdc: 01600193 li gp,22 - 80002ce0: 05df1e63 bne t5,t4,80002d3c - -0000000080002ce4 : - 80002ce4: 00000213 li tp,0 - 80002ce8: 00c00093 li ra,12 - 80002cec: 00000013 nop - 80002cf0: 00000013 nop - 80002cf4: 00e0bf13 sltiu t5,ra,14 - 80002cf8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cfc: 00200293 li t0,2 - 80002d00: fe5214e3 bne tp,t0,80002ce8 - 80002d04: 00100e93 li t4,1 - 80002d08: 01700193 li gp,23 - 80002d0c: 03df1863 bne t5,t4,80002d3c - -0000000080002d10 : - 80002d10: fff03093 sltiu ra,zero,-1 - 80002d14: 00100e93 li t4,1 - 80002d18: 01800193 li gp,24 - 80002d1c: 03d09063 bne ra,t4,80002d3c - -0000000080002d20 : - 80002d20: 00ff00b7 lui ra,0xff0 - 80002d24: 0ff0809b addiw ra,ra,255 - 80002d28: fff0b013 sltiu zero,ra,-1 - 80002d2c: 00000e93 li t4,0 - 80002d30: 01900193 li gp,25 - 80002d34: 01d01463 bne zero,t4,80002d3c - 80002d38: 00301a63 bne zero,gp,80002d4c - -0000000080002d3c : - 80002d3c: 00119513 slli a0,gp,0x1 - 80002d40: 00050063 beqz a0,80002d40 - 80002d44: 00156513 ori a0,a0,1 - 80002d48: 00000073 ecall - -0000000080002d4c : - 80002d4c: 00100513 li a0,1 - 80002d50: 00000073 ecall - 80002d54: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-sltiu.elf b/test/riscv/tests/rv64ui-v-sltiu.elf deleted file mode 100644 index 197c5002..00000000 Binary files a/test/riscv/tests/rv64ui-v-sltiu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-sltu.dump b/test/riscv/tests/rv64ui-v-sltu.dump deleted file mode 100644 index 281d657f..00000000 --- a/test/riscv/tests/rv64ui-v-sltu.dump +++ /dev/null @@ -1,1235 +0,0 @@ - -rv64ui-v-sltu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: b9868693 addi a3,a3,-1128 # 80002ff0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: bcc60613 addi a2,a2,-1076 # 80003080 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: b9460613 addi a2,a2,-1132 # 80003098 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: ae468693 addi a3,a3,-1308 # 80003038 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: b0068693 addi a3,a3,-1280 # 80003170 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: a8060613 addi a2,a2,-1408 # 80003148 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: 9b468693 addi a3,a3,-1612 # 800031a0 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 8d468693 addi a3,a3,-1836 # 80003110 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00001697 auipc a3,0x1 - 80002878: 86468693 addi a3,a3,-1948 # 800030d8 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 00c00793 li a5,12 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 069e57b7 lui a5,0x69e5 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 8d578793 addi a5,a5,-1835 # 69e48d5 <_start-0x7961b72b> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000093 li ra,0 - 80002acc: 00000113 li sp,0 - 80002ad0: 0020bf33 sltu t5,ra,sp - 80002ad4: 00000e93 li t4,0 - 80002ad8: 00200193 li gp,2 - 80002adc: 4fdf1c63 bne t5,t4,80002fd4 - -0000000080002ae0 : - 80002ae0: 00100093 li ra,1 - 80002ae4: 00100113 li sp,1 - 80002ae8: 0020bf33 sltu t5,ra,sp - 80002aec: 00000e93 li t4,0 - 80002af0: 00300193 li gp,3 - 80002af4: 4fdf1063 bne t5,t4,80002fd4 - -0000000080002af8 : - 80002af8: 00300093 li ra,3 - 80002afc: 00700113 li sp,7 - 80002b00: 0020bf33 sltu t5,ra,sp - 80002b04: 00100e93 li t4,1 - 80002b08: 00400193 li gp,4 - 80002b0c: 4ddf1463 bne t5,t4,80002fd4 - -0000000080002b10 : - 80002b10: 00700093 li ra,7 - 80002b14: 00300113 li sp,3 - 80002b18: 0020bf33 sltu t5,ra,sp - 80002b1c: 00000e93 li t4,0 - 80002b20: 00500193 li gp,5 - 80002b24: 4bdf1863 bne t5,t4,80002fd4 - -0000000080002b28 : - 80002b28: 00000093 li ra,0 - 80002b2c: 00020137 lui sp,0x20 - 80002b30: fff1011b addiw sp,sp,-1 - 80002b34: 00f11113 slli sp,sp,0xf - 80002b38: 0020bf33 sltu t5,ra,sp - 80002b3c: 00100e93 li t4,1 - 80002b40: 00600193 li gp,6 - 80002b44: 49df1863 bne t5,t4,80002fd4 - -0000000080002b48 : - 80002b48: 0010009b addiw ra,zero,1 - 80002b4c: 01f09093 slli ra,ra,0x1f - 80002b50: 00000113 li sp,0 - 80002b54: 0020bf33 sltu t5,ra,sp - 80002b58: 00000e93 li t4,0 - 80002b5c: 00700193 li gp,7 - 80002b60: 47df1a63 bne t5,t4,80002fd4 - -0000000080002b64 : - 80002b64: 0010009b addiw ra,zero,1 - 80002b68: 01f09093 slli ra,ra,0x1f - 80002b6c: 00020137 lui sp,0x20 - 80002b70: fff1011b addiw sp,sp,-1 - 80002b74: 00f11113 slli sp,sp,0xf - 80002b78: 0020bf33 sltu t5,ra,sp - 80002b7c: 00100e93 li t4,1 - 80002b80: 00800193 li gp,8 - 80002b84: 45df1863 bne t5,t4,80002fd4 - -0000000080002b88 : - 80002b88: 00000093 li ra,0 - 80002b8c: 00008137 lui sp,0x8 - 80002b90: fff1011b addiw sp,sp,-1 - 80002b94: 0020bf33 sltu t5,ra,sp - 80002b98: 00100e93 li t4,1 - 80002b9c: 00900193 li gp,9 - 80002ba0: 43df1a63 bne t5,t4,80002fd4 - -0000000080002ba4 : - 80002ba4: 800000b7 lui ra,0x80000 - 80002ba8: fff0809b addiw ra,ra,-1 - 80002bac: 00000113 li sp,0 - 80002bb0: 0020bf33 sltu t5,ra,sp - 80002bb4: 00000e93 li t4,0 - 80002bb8: 00a00193 li gp,10 - 80002bbc: 41df1c63 bne t5,t4,80002fd4 - -0000000080002bc0 : - 80002bc0: 800000b7 lui ra,0x80000 - 80002bc4: fff0809b addiw ra,ra,-1 - 80002bc8: 00008137 lui sp,0x8 - 80002bcc: fff1011b addiw sp,sp,-1 - 80002bd0: 0020bf33 sltu t5,ra,sp - 80002bd4: 00000e93 li t4,0 - 80002bd8: 00b00193 li gp,11 - 80002bdc: 3fdf1c63 bne t5,t4,80002fd4 - -0000000080002be0 : - 80002be0: 0010009b addiw ra,zero,1 - 80002be4: 01f09093 slli ra,ra,0x1f - 80002be8: 00008137 lui sp,0x8 - 80002bec: fff1011b addiw sp,sp,-1 - 80002bf0: 0020bf33 sltu t5,ra,sp - 80002bf4: 00000e93 li t4,0 - 80002bf8: 00c00193 li gp,12 - 80002bfc: 3ddf1c63 bne t5,t4,80002fd4 - -0000000080002c00 : - 80002c00: 800000b7 lui ra,0x80000 - 80002c04: fff0809b addiw ra,ra,-1 - 80002c08: 00020137 lui sp,0x20 - 80002c0c: fff1011b addiw sp,sp,-1 - 80002c10: 00f11113 slli sp,sp,0xf - 80002c14: 0020bf33 sltu t5,ra,sp - 80002c18: 00100e93 li t4,1 - 80002c1c: 00d00193 li gp,13 - 80002c20: 3bdf1a63 bne t5,t4,80002fd4 - -0000000080002c24 : - 80002c24: 00000093 li ra,0 - 80002c28: 0010011b addiw sp,zero,1 - 80002c2c: 02011113 slli sp,sp,0x20 - 80002c30: fff10113 addi sp,sp,-1 # 1ffff <_start-0x7ffe0001> - 80002c34: 0020bf33 sltu t5,ra,sp - 80002c38: 00100e93 li t4,1 - 80002c3c: 00e00193 li gp,14 - 80002c40: 39df1a63 bne t5,t4,80002fd4 - -0000000080002c44 : - 80002c44: 0010009b addiw ra,zero,1 - 80002c48: 02009093 slli ra,ra,0x20 - 80002c4c: fff08093 addi ra,ra,-1 # ffffffff7fffffff <_end+0xfffffffeffff780f> - 80002c50: 00100113 li sp,1 - 80002c54: 0020bf33 sltu t5,ra,sp - 80002c58: 00000e93 li t4,0 - 80002c5c: 00f00193 li gp,15 - 80002c60: 37df1a63 bne t5,t4,80002fd4 - -0000000080002c64 : - 80002c64: 0010009b addiw ra,zero,1 - 80002c68: 02009093 slli ra,ra,0x20 - 80002c6c: fff08093 addi ra,ra,-1 - 80002c70: 0010011b addiw sp,zero,1 - 80002c74: 02011113 slli sp,sp,0x20 - 80002c78: fff10113 addi sp,sp,-1 - 80002c7c: 0020bf33 sltu t5,ra,sp - 80002c80: 00000e93 li t4,0 - 80002c84: 01000193 li gp,16 - 80002c88: 35df1663 bne t5,t4,80002fd4 - -0000000080002c8c : - 80002c8c: 00e00093 li ra,14 - 80002c90: 00d00113 li sp,13 - 80002c94: 0020b0b3 sltu ra,ra,sp - 80002c98: 00000e93 li t4,0 - 80002c9c: 01100193 li gp,17 - 80002ca0: 33d09a63 bne ra,t4,80002fd4 - -0000000080002ca4 : - 80002ca4: 00b00093 li ra,11 - 80002ca8: 00d00113 li sp,13 - 80002cac: 0020b133 sltu sp,ra,sp - 80002cb0: 00100e93 li t4,1 - 80002cb4: 01200193 li gp,18 - 80002cb8: 31d11e63 bne sp,t4,80002fd4 - -0000000080002cbc : - 80002cbc: 00d00093 li ra,13 - 80002cc0: 0010b0b3 sltu ra,ra,ra - 80002cc4: 00000e93 li t4,0 - 80002cc8: 01300193 li gp,19 - 80002ccc: 31d09463 bne ra,t4,80002fd4 - -0000000080002cd0 : - 80002cd0: 00000213 li tp,0 - 80002cd4: 00b00093 li ra,11 - 80002cd8: 00d00113 li sp,13 - 80002cdc: 0020bf33 sltu t5,ra,sp - 80002ce0: 000f0313 mv t1,t5 - 80002ce4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ce8: 00200293 li t0,2 - 80002cec: fe5214e3 bne tp,t0,80002cd4 - 80002cf0: 00100e93 li t4,1 - 80002cf4: 01400193 li gp,20 - 80002cf8: 2dd31e63 bne t1,t4,80002fd4 - -0000000080002cfc : - 80002cfc: 00000213 li tp,0 - 80002d00: 00e00093 li ra,14 - 80002d04: 00d00113 li sp,13 - 80002d08: 0020bf33 sltu t5,ra,sp - 80002d0c: 00000013 nop - 80002d10: 000f0313 mv t1,t5 - 80002d14: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d18: 00200293 li t0,2 - 80002d1c: fe5212e3 bne tp,t0,80002d00 - 80002d20: 00000e93 li t4,0 - 80002d24: 01500193 li gp,21 - 80002d28: 2bd31663 bne t1,t4,80002fd4 - -0000000080002d2c : - 80002d2c: 00000213 li tp,0 - 80002d30: 00c00093 li ra,12 - 80002d34: 00d00113 li sp,13 - 80002d38: 0020bf33 sltu t5,ra,sp - 80002d3c: 00000013 nop - 80002d40: 00000013 nop - 80002d44: 000f0313 mv t1,t5 - 80002d48: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d4c: 00200293 li t0,2 - 80002d50: fe5210e3 bne tp,t0,80002d30 - 80002d54: 00100e93 li t4,1 - 80002d58: 01600193 li gp,22 - 80002d5c: 27d31c63 bne t1,t4,80002fd4 - -0000000080002d60 : - 80002d60: 00000213 li tp,0 - 80002d64: 00e00093 li ra,14 - 80002d68: 00d00113 li sp,13 - 80002d6c: 0020bf33 sltu t5,ra,sp - 80002d70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d74: 00200293 li t0,2 - 80002d78: fe5216e3 bne tp,t0,80002d64 - 80002d7c: 00000e93 li t4,0 - 80002d80: 01700193 li gp,23 - 80002d84: 25df1863 bne t5,t4,80002fd4 - -0000000080002d88 : - 80002d88: 00000213 li tp,0 - 80002d8c: 00b00093 li ra,11 - 80002d90: 00d00113 li sp,13 - 80002d94: 00000013 nop - 80002d98: 0020bf33 sltu t5,ra,sp - 80002d9c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002da0: 00200293 li t0,2 - 80002da4: fe5214e3 bne tp,t0,80002d8c - 80002da8: 00100e93 li t4,1 - 80002dac: 01800193 li gp,24 - 80002db0: 23df1263 bne t5,t4,80002fd4 - -0000000080002db4 : - 80002db4: 00000213 li tp,0 - 80002db8: 00f00093 li ra,15 - 80002dbc: 00d00113 li sp,13 - 80002dc0: 00000013 nop - 80002dc4: 00000013 nop - 80002dc8: 0020bf33 sltu t5,ra,sp - 80002dcc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dd0: 00200293 li t0,2 - 80002dd4: fe5212e3 bne tp,t0,80002db8 - 80002dd8: 00000e93 li t4,0 - 80002ddc: 01900193 li gp,25 - 80002de0: 1fdf1a63 bne t5,t4,80002fd4 - -0000000080002de4 : - 80002de4: 00000213 li tp,0 - 80002de8: 00a00093 li ra,10 - 80002dec: 00000013 nop - 80002df0: 00d00113 li sp,13 - 80002df4: 0020bf33 sltu t5,ra,sp - 80002df8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dfc: 00200293 li t0,2 - 80002e00: fe5214e3 bne tp,t0,80002de8 - 80002e04: 00100e93 li t4,1 - 80002e08: 01a00193 li gp,26 - 80002e0c: 1ddf1463 bne t5,t4,80002fd4 - -0000000080002e10 : - 80002e10: 00000213 li tp,0 - 80002e14: 01000093 li ra,16 - 80002e18: 00000013 nop - 80002e1c: 00d00113 li sp,13 - 80002e20: 00000013 nop - 80002e24: 0020bf33 sltu t5,ra,sp - 80002e28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e2c: 00200293 li t0,2 - 80002e30: fe5212e3 bne tp,t0,80002e14 - 80002e34: 00000e93 li t4,0 - 80002e38: 01b00193 li gp,27 - 80002e3c: 19df1c63 bne t5,t4,80002fd4 - -0000000080002e40 : - 80002e40: 00000213 li tp,0 - 80002e44: 00900093 li ra,9 - 80002e48: 00000013 nop - 80002e4c: 00000013 nop - 80002e50: 00d00113 li sp,13 - 80002e54: 0020bf33 sltu t5,ra,sp - 80002e58: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e5c: 00200293 li t0,2 - 80002e60: fe5212e3 bne tp,t0,80002e44 - 80002e64: 00100e93 li t4,1 - 80002e68: 01c00193 li gp,28 - 80002e6c: 17df1463 bne t5,t4,80002fd4 - -0000000080002e70 : - 80002e70: 00000213 li tp,0 - 80002e74: 00d00113 li sp,13 - 80002e78: 01100093 li ra,17 - 80002e7c: 0020bf33 sltu t5,ra,sp - 80002e80: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e84: 00200293 li t0,2 - 80002e88: fe5216e3 bne tp,t0,80002e74 - 80002e8c: 00000e93 li t4,0 - 80002e90: 01d00193 li gp,29 - 80002e94: 15df1063 bne t5,t4,80002fd4 - -0000000080002e98 : - 80002e98: 00000213 li tp,0 - 80002e9c: 00d00113 li sp,13 - 80002ea0: 00800093 li ra,8 - 80002ea4: 00000013 nop - 80002ea8: 0020bf33 sltu t5,ra,sp - 80002eac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002eb0: 00200293 li t0,2 - 80002eb4: fe5214e3 bne tp,t0,80002e9c - 80002eb8: 00100e93 li t4,1 - 80002ebc: 01e00193 li gp,30 - 80002ec0: 11df1a63 bne t5,t4,80002fd4 - -0000000080002ec4 : - 80002ec4: 00000213 li tp,0 - 80002ec8: 00d00113 li sp,13 - 80002ecc: 01200093 li ra,18 - 80002ed0: 00000013 nop - 80002ed4: 00000013 nop - 80002ed8: 0020bf33 sltu t5,ra,sp - 80002edc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ee0: 00200293 li t0,2 - 80002ee4: fe5212e3 bne tp,t0,80002ec8 - 80002ee8: 00000e93 li t4,0 - 80002eec: 01f00193 li gp,31 - 80002ef0: 0fdf1263 bne t5,t4,80002fd4 - -0000000080002ef4 : - 80002ef4: 00000213 li tp,0 - 80002ef8: 00d00113 li sp,13 - 80002efc: 00000013 nop - 80002f00: 00700093 li ra,7 - 80002f04: 0020bf33 sltu t5,ra,sp - 80002f08: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f0c: 00200293 li t0,2 - 80002f10: fe5214e3 bne tp,t0,80002ef8 - 80002f14: 00100e93 li t4,1 - 80002f18: 02000193 li gp,32 - 80002f1c: 0bdf1c63 bne t5,t4,80002fd4 - -0000000080002f20 : - 80002f20: 00000213 li tp,0 - 80002f24: 00d00113 li sp,13 - 80002f28: 00000013 nop - 80002f2c: 01300093 li ra,19 - 80002f30: 00000013 nop - 80002f34: 0020bf33 sltu t5,ra,sp - 80002f38: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f3c: 00200293 li t0,2 - 80002f40: fe5212e3 bne tp,t0,80002f24 - 80002f44: 00000e93 li t4,0 - 80002f48: 02100193 li gp,33 - 80002f4c: 09df1463 bne t5,t4,80002fd4 - -0000000080002f50 : - 80002f50: 00000213 li tp,0 - 80002f54: 00d00113 li sp,13 - 80002f58: 00000013 nop - 80002f5c: 00000013 nop - 80002f60: 00600093 li ra,6 - 80002f64: 0020bf33 sltu t5,ra,sp - 80002f68: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f6c: 00200293 li t0,2 - 80002f70: fe5212e3 bne tp,t0,80002f54 - 80002f74: 00100e93 li t4,1 - 80002f78: 02200193 li gp,34 - 80002f7c: 05df1c63 bne t5,t4,80002fd4 - -0000000080002f80 : - 80002f80: fff00093 li ra,-1 - 80002f84: 00103133 snez sp,ra - 80002f88: 00100e93 li t4,1 - 80002f8c: 02300193 li gp,35 - 80002f90: 05d11263 bne sp,t4,80002fd4 - -0000000080002f94 : - 80002f94: fff00093 li ra,-1 - 80002f98: 0000b133 sltu sp,ra,zero - 80002f9c: 00000e93 li t4,0 - 80002fa0: 02400193 li gp,36 - 80002fa4: 03d11863 bne sp,t4,80002fd4 - -0000000080002fa8 : - 80002fa8: 000030b3 snez ra,zero - 80002fac: 00000e93 li t4,0 - 80002fb0: 02500193 li gp,37 - 80002fb4: 03d09063 bne ra,t4,80002fd4 - -0000000080002fb8 : - 80002fb8: 01000093 li ra,16 - 80002fbc: 01e00113 li sp,30 - 80002fc0: 0020b033 sltu zero,ra,sp - 80002fc4: 00000e93 li t4,0 - 80002fc8: 02600193 li gp,38 - 80002fcc: 01d01463 bne zero,t4,80002fd4 - 80002fd0: 00301a63 bne zero,gp,80002fe4 - -0000000080002fd4 : - 80002fd4: 00119513 slli a0,gp,0x1 - 80002fd8: 00050063 beqz a0,80002fd8 - 80002fdc: 00156513 ori a0,a0,1 - 80002fe0: 00000073 ecall - -0000000080002fe4 : - 80002fe4: 00100513 li a0,1 - 80002fe8: 00000073 ecall - 80002fec: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-sltu.elf b/test/riscv/tests/rv64ui-v-sltu.elf deleted file mode 100644 index 0bd9f902..00000000 Binary files a/test/riscv/tests/rv64ui-v-sltu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-sra.dump b/test/riscv/tests/rv64ui-v-sra.dump deleted file mode 100644 index 37705cb9..00000000 --- a/test/riscv/tests/rv64ui-v-sra.dump +++ /dev/null @@ -1,1281 +0,0 @@ - -rv64ui-v-sra: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: c2868693 addi a3,a3,-984 # 80003080 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: c5c60613 addi a2,a2,-932 # 80003110 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: c2460613 addi a2,a2,-988 # 80003128 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: b7468693 addi a3,a3,-1164 # 800030c8 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: b9068693 addi a3,a3,-1136 # 80003200 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: b1060613 addi a2,a2,-1264 # 800031d8 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: a4468693 addi a3,a3,-1468 # 80003230 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 96468693 addi a3,a3,-1692 # 800031a0 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00001697 auipc a3,0x1 - 80002878: 8f468693 addi a3,a3,-1804 # 80003168 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 02e00793 li a5,46 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0a2f77b7 lui a5,0xa2f7 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 09e78793 addi a5,a5,158 # a2f709e <_start-0x75d08f62> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 800000b7 lui ra,0x80000 - 80002acc: 00000113 li sp,0 - 80002ad0: 4020df33 sra t5,ra,sp - 80002ad4: 80000eb7 lui t4,0x80000 - 80002ad8: 00200193 li gp,2 - 80002adc: 59df1463 bne t5,t4,80003064 - -0000000080002ae0 : - 80002ae0: 800000b7 lui ra,0x80000 - 80002ae4: 00100113 li sp,1 - 80002ae8: 4020df33 sra t5,ra,sp - 80002aec: c0000eb7 lui t4,0xc0000 - 80002af0: 00300193 li gp,3 - 80002af4: 57df1863 bne t5,t4,80003064 - -0000000080002af8 : - 80002af8: 800000b7 lui ra,0x80000 - 80002afc: 00700113 li sp,7 - 80002b00: 4020df33 sra t5,ra,sp - 80002b04: ff000eb7 lui t4,0xff000 - 80002b08: 00400193 li gp,4 - 80002b0c: 55df1c63 bne t5,t4,80003064 - -0000000080002b10 : - 80002b10: 800000b7 lui ra,0x80000 - 80002b14: 00e00113 li sp,14 - 80002b18: 4020df33 sra t5,ra,sp - 80002b1c: fffe0eb7 lui t4,0xfffe0 - 80002b20: 00500193 li gp,5 - 80002b24: 55df1063 bne t5,t4,80003064 - -0000000080002b28 : - 80002b28: 800000b7 lui ra,0x80000 - 80002b2c: 0010809b addiw ra,ra,1 - 80002b30: 01f00113 li sp,31 - 80002b34: 4020df33 sra t5,ra,sp - 80002b38: fff00e93 li t4,-1 - 80002b3c: 00600193 li gp,6 - 80002b40: 53df1263 bne t5,t4,80003064 - -0000000080002b44 : - 80002b44: 800000b7 lui ra,0x80000 - 80002b48: fff0809b addiw ra,ra,-1 - 80002b4c: 00000113 li sp,0 - 80002b50: 4020df33 sra t5,ra,sp - 80002b54: 80000eb7 lui t4,0x80000 - 80002b58: fffe8e9b addiw t4,t4,-1 - 80002b5c: 00700193 li gp,7 - 80002b60: 51df1263 bne t5,t4,80003064 - -0000000080002b64 : - 80002b64: 800000b7 lui ra,0x80000 - 80002b68: fff0809b addiw ra,ra,-1 - 80002b6c: 00100113 li sp,1 - 80002b70: 4020df33 sra t5,ra,sp - 80002b74: 40000eb7 lui t4,0x40000 - 80002b78: fffe8e9b addiw t4,t4,-1 - 80002b7c: 00800193 li gp,8 - 80002b80: 4fdf1263 bne t5,t4,80003064 - -0000000080002b84 : - 80002b84: 800000b7 lui ra,0x80000 - 80002b88: fff0809b addiw ra,ra,-1 - 80002b8c: 00700113 li sp,7 - 80002b90: 4020df33 sra t5,ra,sp - 80002b94: 01000eb7 lui t4,0x1000 - 80002b98: fffe8e9b addiw t4,t4,-1 - 80002b9c: 00900193 li gp,9 - 80002ba0: 4ddf1263 bne t5,t4,80003064 - -0000000080002ba4 : - 80002ba4: 800000b7 lui ra,0x80000 - 80002ba8: fff0809b addiw ra,ra,-1 - 80002bac: 00e00113 li sp,14 - 80002bb0: 4020df33 sra t5,ra,sp - 80002bb4: 00020eb7 lui t4,0x20 - 80002bb8: fffe8e9b addiw t4,t4,-1 - 80002bbc: 00a00193 li gp,10 - 80002bc0: 4bdf1263 bne t5,t4,80003064 - -0000000080002bc4 : - 80002bc4: 800000b7 lui ra,0x80000 - 80002bc8: fff0809b addiw ra,ra,-1 - 80002bcc: 01f00113 li sp,31 - 80002bd0: 4020df33 sra t5,ra,sp - 80002bd4: 00000e93 li t4,0 - 80002bd8: 00b00193 li gp,11 - 80002bdc: 49df1463 bne t5,t4,80003064 - -0000000080002be0 : - 80002be0: 818180b7 lui ra,0x81818 - 80002be4: 1810809b addiw ra,ra,385 - 80002be8: 00000113 li sp,0 - 80002bec: 4020df33 sra t5,ra,sp - 80002bf0: 81818eb7 lui t4,0x81818 - 80002bf4: 181e8e9b addiw t4,t4,385 - 80002bf8: 00c00193 li gp,12 - 80002bfc: 47df1463 bne t5,t4,80003064 - -0000000080002c00 : - 80002c00: 818180b7 lui ra,0x81818 - 80002c04: 1810809b addiw ra,ra,385 - 80002c08: 00100113 li sp,1 - 80002c0c: 4020df33 sra t5,ra,sp - 80002c10: c0c0ceb7 lui t4,0xc0c0c - 80002c14: 0c0e8e9b addiw t4,t4,192 - 80002c18: 00d00193 li gp,13 - 80002c1c: 45df1463 bne t5,t4,80003064 - -0000000080002c20 : - 80002c20: 818180b7 lui ra,0x81818 - 80002c24: 1810809b addiw ra,ra,385 - 80002c28: 00700113 li sp,7 - 80002c2c: 4020df33 sra t5,ra,sp - 80002c30: ff030eb7 lui t4,0xff030 - 80002c34: 303e8e9b addiw t4,t4,771 - 80002c38: 00e00193 li gp,14 - 80002c3c: 43df1463 bne t5,t4,80003064 - -0000000080002c40 : - 80002c40: 818180b7 lui ra,0x81818 - 80002c44: 1810809b addiw ra,ra,385 - 80002c48: 00e00113 li sp,14 - 80002c4c: 4020df33 sra t5,ra,sp - 80002c50: fffe0eb7 lui t4,0xfffe0 - 80002c54: 606e8e9b addiw t4,t4,1542 - 80002c58: 00f00193 li gp,15 - 80002c5c: 41df1463 bne t5,t4,80003064 - -0000000080002c60 : - 80002c60: 818180b7 lui ra,0x81818 - 80002c64: 1810809b addiw ra,ra,385 - 80002c68: 01f00113 li sp,31 - 80002c6c: 4020df33 sra t5,ra,sp - 80002c70: fff00e93 li t4,-1 - 80002c74: 01000193 li gp,16 - 80002c78: 3fdf1663 bne t5,t4,80003064 - -0000000080002c7c : - 80002c7c: 818180b7 lui ra,0x81818 - 80002c80: 1810809b addiw ra,ra,385 - 80002c84: fc000113 li sp,-64 - 80002c88: 4020df33 sra t5,ra,sp - 80002c8c: 81818eb7 lui t4,0x81818 - 80002c90: 181e8e9b addiw t4,t4,385 - 80002c94: 01100193 li gp,17 - 80002c98: 3ddf1663 bne t5,t4,80003064 - -0000000080002c9c : - 80002c9c: 818180b7 lui ra,0x81818 - 80002ca0: 1810809b addiw ra,ra,385 - 80002ca4: fc100113 li sp,-63 - 80002ca8: 4020df33 sra t5,ra,sp - 80002cac: c0c0ceb7 lui t4,0xc0c0c - 80002cb0: 0c0e8e9b addiw t4,t4,192 - 80002cb4: 01200193 li gp,18 - 80002cb8: 3bdf1663 bne t5,t4,80003064 - -0000000080002cbc : - 80002cbc: 818180b7 lui ra,0x81818 - 80002cc0: 1810809b addiw ra,ra,385 - 80002cc4: fc700113 li sp,-57 - 80002cc8: 4020df33 sra t5,ra,sp - 80002ccc: ff030eb7 lui t4,0xff030 - 80002cd0: 303e8e9b addiw t4,t4,771 - 80002cd4: 01300193 li gp,19 - 80002cd8: 39df1663 bne t5,t4,80003064 - -0000000080002cdc : - 80002cdc: 818180b7 lui ra,0x81818 - 80002ce0: 1810809b addiw ra,ra,385 - 80002ce4: fce00113 li sp,-50 - 80002ce8: 4020df33 sra t5,ra,sp - 80002cec: fffe0eb7 lui t4,0xfffe0 - 80002cf0: 606e8e9b addiw t4,t4,1542 - 80002cf4: 01400193 li gp,20 - 80002cf8: 37df1663 bne t5,t4,80003064 - -0000000080002cfc : - 80002cfc: 818180b7 lui ra,0x81818 - 80002d00: 1810809b addiw ra,ra,385 - 80002d04: fff00113 li sp,-1 - 80002d08: 4020df33 sra t5,ra,sp - 80002d0c: fff00e93 li t4,-1 - 80002d10: 01500193 li gp,21 - 80002d14: 35df1863 bne t5,t4,80003064 - -0000000080002d18 : - 80002d18: 800000b7 lui ra,0x80000 - 80002d1c: 00700113 li sp,7 - 80002d20: 4020d0b3 sra ra,ra,sp - 80002d24: ff000eb7 lui t4,0xff000 - 80002d28: 01600193 li gp,22 - 80002d2c: 33d09c63 bne ra,t4,80003064 - -0000000080002d30 : - 80002d30: 800000b7 lui ra,0x80000 - 80002d34: 00e00113 li sp,14 - 80002d38: 4020d133 sra sp,ra,sp - 80002d3c: fffe0eb7 lui t4,0xfffe0 - 80002d40: 01700193 li gp,23 - 80002d44: 33d11063 bne sp,t4,80003064 - -0000000080002d48 : - 80002d48: 00700093 li ra,7 - 80002d4c: 4010d0b3 sra ra,ra,ra - 80002d50: 00000e93 li t4,0 - 80002d54: 01800193 li gp,24 - 80002d58: 31d09663 bne ra,t4,80003064 - -0000000080002d5c : - 80002d5c: 00000213 li tp,0 - 80002d60: 800000b7 lui ra,0x80000 - 80002d64: 00700113 li sp,7 - 80002d68: 4020df33 sra t5,ra,sp - 80002d6c: 000f0313 mv t1,t5 - 80002d70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d74: 00200293 li t0,2 - 80002d78: fe5214e3 bne tp,t0,80002d60 - 80002d7c: ff000eb7 lui t4,0xff000 - 80002d80: 01900193 li gp,25 - 80002d84: 2fd31063 bne t1,t4,80003064 - -0000000080002d88 : - 80002d88: 00000213 li tp,0 - 80002d8c: 800000b7 lui ra,0x80000 - 80002d90: 00e00113 li sp,14 - 80002d94: 4020df33 sra t5,ra,sp - 80002d98: 00000013 nop - 80002d9c: 000f0313 mv t1,t5 - 80002da0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002da4: 00200293 li t0,2 - 80002da8: fe5212e3 bne tp,t0,80002d8c - 80002dac: fffe0eb7 lui t4,0xfffe0 - 80002db0: 01a00193 li gp,26 - 80002db4: 2bd31863 bne t1,t4,80003064 - -0000000080002db8 : - 80002db8: 00000213 li tp,0 - 80002dbc: 800000b7 lui ra,0x80000 - 80002dc0: 01f00113 li sp,31 - 80002dc4: 4020df33 sra t5,ra,sp - 80002dc8: 00000013 nop - 80002dcc: 00000013 nop - 80002dd0: 000f0313 mv t1,t5 - 80002dd4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dd8: 00200293 li t0,2 - 80002ddc: fe5210e3 bne tp,t0,80002dbc - 80002de0: fff00e93 li t4,-1 - 80002de4: 01b00193 li gp,27 - 80002de8: 27d31e63 bne t1,t4,80003064 - -0000000080002dec : - 80002dec: 00000213 li tp,0 - 80002df0: 800000b7 lui ra,0x80000 - 80002df4: 00700113 li sp,7 - 80002df8: 4020df33 sra t5,ra,sp - 80002dfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e00: 00200293 li t0,2 - 80002e04: fe5216e3 bne tp,t0,80002df0 - 80002e08: ff000eb7 lui t4,0xff000 - 80002e0c: 01c00193 li gp,28 - 80002e10: 25df1a63 bne t5,t4,80003064 - -0000000080002e14 : - 80002e14: 00000213 li tp,0 - 80002e18: 800000b7 lui ra,0x80000 - 80002e1c: 00e00113 li sp,14 - 80002e20: 00000013 nop - 80002e24: 4020df33 sra t5,ra,sp - 80002e28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e2c: 00200293 li t0,2 - 80002e30: fe5214e3 bne tp,t0,80002e18 - 80002e34: fffe0eb7 lui t4,0xfffe0 - 80002e38: 01d00193 li gp,29 - 80002e3c: 23df1463 bne t5,t4,80003064 - -0000000080002e40 : - 80002e40: 00000213 li tp,0 - 80002e44: 800000b7 lui ra,0x80000 - 80002e48: 01f00113 li sp,31 - 80002e4c: 00000013 nop - 80002e50: 00000013 nop - 80002e54: 4020df33 sra t5,ra,sp - 80002e58: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e5c: 00200293 li t0,2 - 80002e60: fe5212e3 bne tp,t0,80002e44 - 80002e64: fff00e93 li t4,-1 - 80002e68: 01e00193 li gp,30 - 80002e6c: 1fdf1c63 bne t5,t4,80003064 - -0000000080002e70 : - 80002e70: 00000213 li tp,0 - 80002e74: 800000b7 lui ra,0x80000 - 80002e78: 00000013 nop - 80002e7c: 00700113 li sp,7 - 80002e80: 4020df33 sra t5,ra,sp - 80002e84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e88: 00200293 li t0,2 - 80002e8c: fe5214e3 bne tp,t0,80002e74 - 80002e90: ff000eb7 lui t4,0xff000 - 80002e94: 01f00193 li gp,31 - 80002e98: 1ddf1663 bne t5,t4,80003064 - -0000000080002e9c : - 80002e9c: 00000213 li tp,0 - 80002ea0: 800000b7 lui ra,0x80000 - 80002ea4: 00000013 nop - 80002ea8: 00e00113 li sp,14 - 80002eac: 00000013 nop - 80002eb0: 4020df33 sra t5,ra,sp - 80002eb4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002eb8: 00200293 li t0,2 - 80002ebc: fe5212e3 bne tp,t0,80002ea0 - 80002ec0: fffe0eb7 lui t4,0xfffe0 - 80002ec4: 02000193 li gp,32 - 80002ec8: 19df1e63 bne t5,t4,80003064 - -0000000080002ecc : - 80002ecc: 00000213 li tp,0 - 80002ed0: 800000b7 lui ra,0x80000 - 80002ed4: 00000013 nop - 80002ed8: 00000013 nop - 80002edc: 01f00113 li sp,31 - 80002ee0: 4020df33 sra t5,ra,sp - 80002ee4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ee8: 00200293 li t0,2 - 80002eec: fe5212e3 bne tp,t0,80002ed0 - 80002ef0: fff00e93 li t4,-1 - 80002ef4: 02100193 li gp,33 - 80002ef8: 17df1663 bne t5,t4,80003064 - -0000000080002efc : - 80002efc: 00000213 li tp,0 - 80002f00: 00700113 li sp,7 - 80002f04: 800000b7 lui ra,0x80000 - 80002f08: 4020df33 sra t5,ra,sp - 80002f0c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f10: 00200293 li t0,2 - 80002f14: fe5216e3 bne tp,t0,80002f00 - 80002f18: ff000eb7 lui t4,0xff000 - 80002f1c: 02200193 li gp,34 - 80002f20: 15df1263 bne t5,t4,80003064 - -0000000080002f24 : - 80002f24: 00000213 li tp,0 - 80002f28: 00e00113 li sp,14 - 80002f2c: 800000b7 lui ra,0x80000 - 80002f30: 00000013 nop - 80002f34: 4020df33 sra t5,ra,sp - 80002f38: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f3c: 00200293 li t0,2 - 80002f40: fe5214e3 bne tp,t0,80002f28 - 80002f44: fffe0eb7 lui t4,0xfffe0 - 80002f48: 02300193 li gp,35 - 80002f4c: 11df1c63 bne t5,t4,80003064 - -0000000080002f50 : - 80002f50: 00000213 li tp,0 - 80002f54: 01f00113 li sp,31 - 80002f58: 800000b7 lui ra,0x80000 - 80002f5c: 00000013 nop - 80002f60: 00000013 nop - 80002f64: 4020df33 sra t5,ra,sp - 80002f68: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f6c: 00200293 li t0,2 - 80002f70: fe5212e3 bne tp,t0,80002f54 - 80002f74: fff00e93 li t4,-1 - 80002f78: 02400193 li gp,36 - 80002f7c: 0fdf1463 bne t5,t4,80003064 - -0000000080002f80 : - 80002f80: 00000213 li tp,0 - 80002f84: 00700113 li sp,7 - 80002f88: 00000013 nop - 80002f8c: 800000b7 lui ra,0x80000 - 80002f90: 4020df33 sra t5,ra,sp - 80002f94: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f98: 00200293 li t0,2 - 80002f9c: fe5214e3 bne tp,t0,80002f84 - 80002fa0: ff000eb7 lui t4,0xff000 - 80002fa4: 02500193 li gp,37 - 80002fa8: 0bdf1e63 bne t5,t4,80003064 - -0000000080002fac : - 80002fac: 00000213 li tp,0 - 80002fb0: 00e00113 li sp,14 - 80002fb4: 00000013 nop - 80002fb8: 800000b7 lui ra,0x80000 - 80002fbc: 00000013 nop - 80002fc0: 4020df33 sra t5,ra,sp - 80002fc4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002fc8: 00200293 li t0,2 - 80002fcc: fe5212e3 bne tp,t0,80002fb0 - 80002fd0: fffe0eb7 lui t4,0xfffe0 - 80002fd4: 02600193 li gp,38 - 80002fd8: 09df1663 bne t5,t4,80003064 - -0000000080002fdc : - 80002fdc: 00000213 li tp,0 - 80002fe0: 01f00113 li sp,31 - 80002fe4: 00000013 nop - 80002fe8: 00000013 nop - 80002fec: 800000b7 lui ra,0x80000 - 80002ff0: 4020df33 sra t5,ra,sp - 80002ff4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ff8: 00200293 li t0,2 - 80002ffc: fe5212e3 bne tp,t0,80002fe0 - 80003000: fff00e93 li t4,-1 - 80003004: 02700193 li gp,39 - 80003008: 05df1e63 bne t5,t4,80003064 - -000000008000300c : - 8000300c: 00f00093 li ra,15 - 80003010: 40105133 sra sp,zero,ra - 80003014: 00000e93 li t4,0 - 80003018: 02800193 li gp,40 - 8000301c: 05d11463 bne sp,t4,80003064 - -0000000080003020 : - 80003020: 02000093 li ra,32 - 80003024: 4000d133 sra sp,ra,zero - 80003028: 02000e93 li t4,32 - 8000302c: 02900193 li gp,41 - 80003030: 03d11a63 bne sp,t4,80003064 - -0000000080003034 : - 80003034: 400050b3 sra ra,zero,zero - 80003038: 00000e93 li t4,0 - 8000303c: 02a00193 li gp,42 - 80003040: 03d09263 bne ra,t4,80003064 - -0000000080003044 : - 80003044: 40000093 li ra,1024 - 80003048: 00001137 lui sp,0x1 - 8000304c: 8001011b addiw sp,sp,-2048 - 80003050: 4020d033 sra zero,ra,sp - 80003054: 00000e93 li t4,0 - 80003058: 02b00193 li gp,43 - 8000305c: 01d01463 bne zero,t4,80003064 - 80003060: 00301a63 bne zero,gp,80003074 - -0000000080003064 : - 80003064: 00119513 slli a0,gp,0x1 - 80003068: 00050063 beqz a0,80003068 - 8000306c: 00156513 ori a0,a0,1 - 80003070: 00000073 ecall - -0000000080003074 : - 80003074: 00100513 li a0,1 - 80003078: 00000073 ecall - 8000307c: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-sra.elf b/test/riscv/tests/rv64ui-v-sra.elf deleted file mode 100644 index bfbb9dc1..00000000 Binary files a/test/riscv/tests/rv64ui-v-sra.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-srai.dump b/test/riscv/tests/rv64ui-v-srai.dump deleted file mode 100644 index 8926e559..00000000 --- a/test/riscv/tests/rv64ui-v-srai.dump +++ /dev/null @@ -1,1062 +0,0 @@ - -rv64ui-v-srai: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 95068693 addi a3,a3,-1712 # 80002da8 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 98460613 addi a2,a2,-1660 # 80002e38 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 94c60613 addi a2,a2,-1716 # 80002e50 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 89c68693 addi a3,a3,-1892 # 80002df0 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 8b868693 addi a3,a3,-1864 # 80002f28 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 83860613 addi a2,a2,-1992 # 80002f00 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 76c68693 addi a3,a3,1900 # 80002f58 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 68c68693 addi a3,a3,1676 # 80002ec8 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 61c68693 addi a3,a3,1564 # 80002e90 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 00400793 li a5,4 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 00a547b7 lui a5,0xa54 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: f8778793 addi a5,a5,-121 # a53f87 <_start-0x7f5ac079> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: fff0009b addiw ra,zero,-1 - 80002acc: 02709093 slli ra,ra,0x27 - 80002ad0: 4000df13 srai t5,ra,0x0 - 80002ad4: fff00e9b addiw t4,zero,-1 - 80002ad8: 027e9e93 slli t4,t4,0x27 - 80002adc: 00200193 li gp,2 - 80002ae0: 2bdf1463 bne t5,t4,80002d88 - -0000000080002ae4 : - 80002ae4: 800000b7 lui ra,0x80000 - 80002ae8: 4010df13 srai t5,ra,0x1 - 80002aec: c0000eb7 lui t4,0xc0000 - 80002af0: 00300193 li gp,3 - 80002af4: 29df1a63 bne t5,t4,80002d88 - -0000000080002af8 : - 80002af8: 800000b7 lui ra,0x80000 - 80002afc: 4070df13 srai t5,ra,0x7 - 80002b00: ff000eb7 lui t4,0xff000 - 80002b04: 00400193 li gp,4 - 80002b08: 29df1063 bne t5,t4,80002d88 - -0000000080002b0c : - 80002b0c: 800000b7 lui ra,0x80000 - 80002b10: 40e0df13 srai t5,ra,0xe - 80002b14: fffe0eb7 lui t4,0xfffe0 - 80002b18: 00500193 li gp,5 - 80002b1c: 27df1663 bne t5,t4,80002d88 - -0000000080002b20 : - 80002b20: 800000b7 lui ra,0x80000 - 80002b24: 0010809b addiw ra,ra,1 - 80002b28: 41f0df13 srai t5,ra,0x1f - 80002b2c: fff00e93 li t4,-1 - 80002b30: 00600193 li gp,6 - 80002b34: 25df1a63 bne t5,t4,80002d88 - -0000000080002b38 : - 80002b38: 800000b7 lui ra,0x80000 - 80002b3c: fff0809b addiw ra,ra,-1 - 80002b40: 4000df13 srai t5,ra,0x0 - 80002b44: 80000eb7 lui t4,0x80000 - 80002b48: fffe8e9b addiw t4,t4,-1 - 80002b4c: 00700193 li gp,7 - 80002b50: 23df1c63 bne t5,t4,80002d88 - -0000000080002b54 : - 80002b54: 800000b7 lui ra,0x80000 - 80002b58: fff0809b addiw ra,ra,-1 - 80002b5c: 4010df13 srai t5,ra,0x1 - 80002b60: 40000eb7 lui t4,0x40000 - 80002b64: fffe8e9b addiw t4,t4,-1 - 80002b68: 00800193 li gp,8 - 80002b6c: 21df1e63 bne t5,t4,80002d88 - -0000000080002b70 : - 80002b70: 800000b7 lui ra,0x80000 - 80002b74: fff0809b addiw ra,ra,-1 - 80002b78: 4070df13 srai t5,ra,0x7 - 80002b7c: 01000eb7 lui t4,0x1000 - 80002b80: fffe8e9b addiw t4,t4,-1 - 80002b84: 00900193 li gp,9 - 80002b88: 21df1063 bne t5,t4,80002d88 - -0000000080002b8c : - 80002b8c: 800000b7 lui ra,0x80000 - 80002b90: fff0809b addiw ra,ra,-1 - 80002b94: 40e0df13 srai t5,ra,0xe - 80002b98: 00020eb7 lui t4,0x20 - 80002b9c: fffe8e9b addiw t4,t4,-1 - 80002ba0: 00a00193 li gp,10 - 80002ba4: 1fdf1263 bne t5,t4,80002d88 - -0000000080002ba8 : - 80002ba8: 800000b7 lui ra,0x80000 - 80002bac: fff0809b addiw ra,ra,-1 - 80002bb0: 41f0df13 srai t5,ra,0x1f - 80002bb4: 00000e93 li t4,0 - 80002bb8: 00b00193 li gp,11 - 80002bbc: 1ddf1663 bne t5,t4,80002d88 - -0000000080002bc0 : - 80002bc0: 818180b7 lui ra,0x81818 - 80002bc4: 1810809b addiw ra,ra,385 - 80002bc8: 4000df13 srai t5,ra,0x0 - 80002bcc: 81818eb7 lui t4,0x81818 - 80002bd0: 181e8e9b addiw t4,t4,385 - 80002bd4: 00c00193 li gp,12 - 80002bd8: 1bdf1863 bne t5,t4,80002d88 - -0000000080002bdc : - 80002bdc: 818180b7 lui ra,0x81818 - 80002be0: 1810809b addiw ra,ra,385 - 80002be4: 4010df13 srai t5,ra,0x1 - 80002be8: c0c0ceb7 lui t4,0xc0c0c - 80002bec: 0c0e8e9b addiw t4,t4,192 - 80002bf0: 00d00193 li gp,13 - 80002bf4: 19df1a63 bne t5,t4,80002d88 - -0000000080002bf8 : - 80002bf8: 818180b7 lui ra,0x81818 - 80002bfc: 1810809b addiw ra,ra,385 - 80002c00: 4070df13 srai t5,ra,0x7 - 80002c04: ff030eb7 lui t4,0xff030 - 80002c08: 303e8e9b addiw t4,t4,771 - 80002c0c: 00e00193 li gp,14 - 80002c10: 17df1c63 bne t5,t4,80002d88 - -0000000080002c14 : - 80002c14: 818180b7 lui ra,0x81818 - 80002c18: 1810809b addiw ra,ra,385 - 80002c1c: 40e0df13 srai t5,ra,0xe - 80002c20: fffe0eb7 lui t4,0xfffe0 - 80002c24: 606e8e9b addiw t4,t4,1542 - 80002c28: 00f00193 li gp,15 - 80002c2c: 15df1e63 bne t5,t4,80002d88 - -0000000080002c30 : - 80002c30: 818180b7 lui ra,0x81818 - 80002c34: 1810809b addiw ra,ra,385 - 80002c38: 41f0df13 srai t5,ra,0x1f - 80002c3c: fff00e93 li t4,-1 - 80002c40: 01000193 li gp,16 - 80002c44: 15df1263 bne t5,t4,80002d88 - -0000000080002c48 : - 80002c48: 800000b7 lui ra,0x80000 - 80002c4c: 4070d093 srai ra,ra,0x7 - 80002c50: ff000eb7 lui t4,0xff000 - 80002c54: 01100193 li gp,17 - 80002c58: 13d09863 bne ra,t4,80002d88 - -0000000080002c5c : - 80002c5c: 00000213 li tp,0 - 80002c60: 800000b7 lui ra,0x80000 - 80002c64: 4070df13 srai t5,ra,0x7 - 80002c68: 000f0313 mv t1,t5 - 80002c6c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c70: 00200293 li t0,2 - 80002c74: fe5216e3 bne tp,t0,80002c60 - 80002c78: ff000eb7 lui t4,0xff000 - 80002c7c: 01200193 li gp,18 - 80002c80: 11d31463 bne t1,t4,80002d88 - -0000000080002c84 : - 80002c84: 00000213 li tp,0 - 80002c88: 800000b7 lui ra,0x80000 - 80002c8c: 40e0df13 srai t5,ra,0xe - 80002c90: 00000013 nop - 80002c94: 000f0313 mv t1,t5 - 80002c98: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c9c: 00200293 li t0,2 - 80002ca0: fe5214e3 bne tp,t0,80002c88 - 80002ca4: fffe0eb7 lui t4,0xfffe0 - 80002ca8: 01300193 li gp,19 - 80002cac: 0dd31e63 bne t1,t4,80002d88 - -0000000080002cb0 : - 80002cb0: 00000213 li tp,0 - 80002cb4: 800000b7 lui ra,0x80000 - 80002cb8: 0010809b addiw ra,ra,1 - 80002cbc: 41f0df13 srai t5,ra,0x1f - 80002cc0: 00000013 nop - 80002cc4: 00000013 nop - 80002cc8: 000f0313 mv t1,t5 - 80002ccc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cd0: 00200293 li t0,2 - 80002cd4: fe5210e3 bne tp,t0,80002cb4 - 80002cd8: fff00e93 li t4,-1 - 80002cdc: 01400193 li gp,20 - 80002ce0: 0bd31463 bne t1,t4,80002d88 - -0000000080002ce4 : - 80002ce4: 00000213 li tp,0 - 80002ce8: 800000b7 lui ra,0x80000 - 80002cec: 4070df13 srai t5,ra,0x7 - 80002cf0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cf4: 00200293 li t0,2 - 80002cf8: fe5218e3 bne tp,t0,80002ce8 - 80002cfc: ff000eb7 lui t4,0xff000 - 80002d00: 01500193 li gp,21 - 80002d04: 09df1263 bne t5,t4,80002d88 - -0000000080002d08 : - 80002d08: 00000213 li tp,0 - 80002d0c: 800000b7 lui ra,0x80000 - 80002d10: 00000013 nop - 80002d14: 40e0df13 srai t5,ra,0xe - 80002d18: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d1c: 00200293 li t0,2 - 80002d20: fe5216e3 bne tp,t0,80002d0c - 80002d24: fffe0eb7 lui t4,0xfffe0 - 80002d28: 01600193 li gp,22 - 80002d2c: 05df1e63 bne t5,t4,80002d88 - -0000000080002d30 : - 80002d30: 00000213 li tp,0 - 80002d34: 800000b7 lui ra,0x80000 - 80002d38: 0010809b addiw ra,ra,1 - 80002d3c: 00000013 nop - 80002d40: 00000013 nop - 80002d44: 41f0df13 srai t5,ra,0x1f - 80002d48: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d4c: 00200293 li t0,2 - 80002d50: fe5212e3 bne tp,t0,80002d34 - 80002d54: fff00e93 li t4,-1 - 80002d58: 01700193 li gp,23 - 80002d5c: 03df1663 bne t5,t4,80002d88 - -0000000080002d60 : - 80002d60: 40405093 srai ra,zero,0x4 - 80002d64: 00000e93 li t4,0 - 80002d68: 01800193 li gp,24 - 80002d6c: 01d09e63 bne ra,t4,80002d88 - -0000000080002d70 : - 80002d70: 02100093 li ra,33 - 80002d74: 40a0d013 srai zero,ra,0xa - 80002d78: 00000e93 li t4,0 - 80002d7c: 01900193 li gp,25 - 80002d80: 01d01463 bne zero,t4,80002d88 - 80002d84: 00301a63 bne zero,gp,80002d98 - -0000000080002d88 : - 80002d88: 00119513 slli a0,gp,0x1 - 80002d8c: 00050063 beqz a0,80002d8c - 80002d90: 00156513 ori a0,a0,1 - 80002d94: 00000073 ecall - -0000000080002d98 : - 80002d98: 00100513 li a0,1 - 80002d9c: 00000073 ecall - 80002da0: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-srai.elf b/test/riscv/tests/rv64ui-v-srai.elf deleted file mode 100644 index a84338f4..00000000 Binary files a/test/riscv/tests/rv64ui-v-srai.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-sraiw.dump b/test/riscv/tests/rv64ui-v-sraiw.dump deleted file mode 100644 index 276de6b8..00000000 --- a/test/riscv/tests/rv64ui-v-sraiw.dump +++ /dev/null @@ -1,1076 +0,0 @@ - -rv64ui-v-sraiw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 97868693 addi a3,a3,-1672 # 80002dd0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 9ac60613 addi a2,a2,-1620 # 80002e60 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 97460613 addi a2,a2,-1676 # 80002e78 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 8c468693 addi a3,a3,-1852 # 80002e18 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 8e068693 addi a3,a3,-1824 # 80002f50 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 86060613 addi a2,a2,-1952 # 80002f28 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 79468693 addi a3,a3,1940 # 80002f80 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 6b468693 addi a3,a3,1716 # 80002ef0 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 64468693 addi a3,a3,1604 # 80002eb8 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 00800793 li a5,8 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0e8fe7b7 lui a5,0xe8fe - 80002a70: 000805b7 lui a1,0x80 - 80002a74: ca478793 addi a5,a5,-860 # e8fdca4 <_start-0x7170235c> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 800000b7 lui ra,0x80000 - 80002acc: 4000df1b sraiw t5,ra,0x0 - 80002ad0: 80000eb7 lui t4,0x80000 - 80002ad4: 00200193 li gp,2 - 80002ad8: 2ddf1c63 bne t5,t4,80002db0 - -0000000080002adc : - 80002adc: 800000b7 lui ra,0x80000 - 80002ae0: 4010df1b sraiw t5,ra,0x1 - 80002ae4: c0000eb7 lui t4,0xc0000 - 80002ae8: 00300193 li gp,3 - 80002aec: 2ddf1263 bne t5,t4,80002db0 - -0000000080002af0 : - 80002af0: 800000b7 lui ra,0x80000 - 80002af4: 4070df1b sraiw t5,ra,0x7 - 80002af8: ff000eb7 lui t4,0xff000 - 80002afc: 00400193 li gp,4 - 80002b00: 2bdf1863 bne t5,t4,80002db0 - -0000000080002b04 : - 80002b04: 800000b7 lui ra,0x80000 - 80002b08: 40e0df1b sraiw t5,ra,0xe - 80002b0c: fffe0eb7 lui t4,0xfffe0 - 80002b10: 00500193 li gp,5 - 80002b14: 29df1e63 bne t5,t4,80002db0 - -0000000080002b18 : - 80002b18: 800000b7 lui ra,0x80000 - 80002b1c: 0010809b addiw ra,ra,1 - 80002b20: 41f0df1b sraiw t5,ra,0x1f - 80002b24: fff00e93 li t4,-1 - 80002b28: 00600193 li gp,6 - 80002b2c: 29df1263 bne t5,t4,80002db0 - -0000000080002b30 : - 80002b30: 800000b7 lui ra,0x80000 - 80002b34: fff0809b addiw ra,ra,-1 - 80002b38: 4000df1b sraiw t5,ra,0x0 - 80002b3c: 80000eb7 lui t4,0x80000 - 80002b40: fffe8e9b addiw t4,t4,-1 - 80002b44: 00700193 li gp,7 - 80002b48: 27df1463 bne t5,t4,80002db0 - -0000000080002b4c : - 80002b4c: 800000b7 lui ra,0x80000 - 80002b50: fff0809b addiw ra,ra,-1 - 80002b54: 4010df1b sraiw t5,ra,0x1 - 80002b58: 40000eb7 lui t4,0x40000 - 80002b5c: fffe8e9b addiw t4,t4,-1 - 80002b60: 00800193 li gp,8 - 80002b64: 25df1663 bne t5,t4,80002db0 - -0000000080002b68 : - 80002b68: 800000b7 lui ra,0x80000 - 80002b6c: fff0809b addiw ra,ra,-1 - 80002b70: 4070df1b sraiw t5,ra,0x7 - 80002b74: 01000eb7 lui t4,0x1000 - 80002b78: fffe8e9b addiw t4,t4,-1 - 80002b7c: 00900193 li gp,9 - 80002b80: 23df1863 bne t5,t4,80002db0 - -0000000080002b84 : - 80002b84: 800000b7 lui ra,0x80000 - 80002b88: fff0809b addiw ra,ra,-1 - 80002b8c: 40e0df1b sraiw t5,ra,0xe - 80002b90: 00020eb7 lui t4,0x20 - 80002b94: fffe8e9b addiw t4,t4,-1 - 80002b98: 00a00193 li gp,10 - 80002b9c: 21df1a63 bne t5,t4,80002db0 - -0000000080002ba0 : - 80002ba0: 800000b7 lui ra,0x80000 - 80002ba4: fff0809b addiw ra,ra,-1 - 80002ba8: 41f0df1b sraiw t5,ra,0x1f - 80002bac: 00000e93 li t4,0 - 80002bb0: 00b00193 li gp,11 - 80002bb4: 1fdf1e63 bne t5,t4,80002db0 - -0000000080002bb8 : - 80002bb8: 818180b7 lui ra,0x81818 - 80002bbc: 1810809b addiw ra,ra,385 - 80002bc0: 4000df1b sraiw t5,ra,0x0 - 80002bc4: 81818eb7 lui t4,0x81818 - 80002bc8: 181e8e9b addiw t4,t4,385 - 80002bcc: 00c00193 li gp,12 - 80002bd0: 1fdf1063 bne t5,t4,80002db0 - -0000000080002bd4 : - 80002bd4: 818180b7 lui ra,0x81818 - 80002bd8: 1810809b addiw ra,ra,385 - 80002bdc: 4010df1b sraiw t5,ra,0x1 - 80002be0: c0c0ceb7 lui t4,0xc0c0c - 80002be4: 0c0e8e9b addiw t4,t4,192 - 80002be8: 00d00193 li gp,13 - 80002bec: 1ddf1263 bne t5,t4,80002db0 - -0000000080002bf0 : - 80002bf0: 818180b7 lui ra,0x81818 - 80002bf4: 1810809b addiw ra,ra,385 - 80002bf8: 4070df1b sraiw t5,ra,0x7 - 80002bfc: ff030eb7 lui t4,0xff030 - 80002c00: 303e8e9b addiw t4,t4,771 - 80002c04: 00e00193 li gp,14 - 80002c08: 1bdf1463 bne t5,t4,80002db0 - -0000000080002c0c : - 80002c0c: 818180b7 lui ra,0x81818 - 80002c10: 1810809b addiw ra,ra,385 - 80002c14: 40e0df1b sraiw t5,ra,0xe - 80002c18: fffe0eb7 lui t4,0xfffe0 - 80002c1c: 606e8e9b addiw t4,t4,1542 - 80002c20: 00f00193 li gp,15 - 80002c24: 19df1663 bne t5,t4,80002db0 - -0000000080002c28 : - 80002c28: 818180b7 lui ra,0x81818 - 80002c2c: 1810809b addiw ra,ra,385 - 80002c30: 41f0df1b sraiw t5,ra,0x1f - 80002c34: fff00e93 li t4,-1 - 80002c38: 01000193 li gp,16 - 80002c3c: 17df1a63 bne t5,t4,80002db0 - -0000000080002c40 : - 80002c40: 800000b7 lui ra,0x80000 - 80002c44: 4070d09b sraiw ra,ra,0x7 - 80002c48: ff000eb7 lui t4,0xff000 - 80002c4c: 01100193 li gp,17 - 80002c50: 17d09063 bne ra,t4,80002db0 - -0000000080002c54 : - 80002c54: 00000213 li tp,0 - 80002c58: 800000b7 lui ra,0x80000 - 80002c5c: 4070df1b sraiw t5,ra,0x7 - 80002c60: 000f0313 mv t1,t5 - 80002c64: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c68: 00200293 li t0,2 - 80002c6c: fe5216e3 bne tp,t0,80002c58 - 80002c70: ff000eb7 lui t4,0xff000 - 80002c74: 01200193 li gp,18 - 80002c78: 13d31c63 bne t1,t4,80002db0 - -0000000080002c7c : - 80002c7c: 00000213 li tp,0 - 80002c80: 800000b7 lui ra,0x80000 - 80002c84: 40e0df1b sraiw t5,ra,0xe - 80002c88: 00000013 nop - 80002c8c: 000f0313 mv t1,t5 - 80002c90: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c94: 00200293 li t0,2 - 80002c98: fe5214e3 bne tp,t0,80002c80 - 80002c9c: fffe0eb7 lui t4,0xfffe0 - 80002ca0: 01300193 li gp,19 - 80002ca4: 11d31663 bne t1,t4,80002db0 - -0000000080002ca8 : - 80002ca8: 00000213 li tp,0 - 80002cac: 800000b7 lui ra,0x80000 - 80002cb0: 0010809b addiw ra,ra,1 - 80002cb4: 41f0df1b sraiw t5,ra,0x1f - 80002cb8: 00000013 nop - 80002cbc: 00000013 nop - 80002cc0: 000f0313 mv t1,t5 - 80002cc4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cc8: 00200293 li t0,2 - 80002ccc: fe5210e3 bne tp,t0,80002cac - 80002cd0: fff00e93 li t4,-1 - 80002cd4: 01400193 li gp,20 - 80002cd8: 0dd31c63 bne t1,t4,80002db0 - -0000000080002cdc : - 80002cdc: 00000213 li tp,0 - 80002ce0: 800000b7 lui ra,0x80000 - 80002ce4: 4070df1b sraiw t5,ra,0x7 - 80002ce8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cec: 00200293 li t0,2 - 80002cf0: fe5218e3 bne tp,t0,80002ce0 - 80002cf4: ff000eb7 lui t4,0xff000 - 80002cf8: 01500193 li gp,21 - 80002cfc: 0bdf1a63 bne t5,t4,80002db0 - -0000000080002d00 : - 80002d00: 00000213 li tp,0 - 80002d04: 800000b7 lui ra,0x80000 - 80002d08: 00000013 nop - 80002d0c: 40e0df1b sraiw t5,ra,0xe - 80002d10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d14: 00200293 li t0,2 - 80002d18: fe5216e3 bne tp,t0,80002d04 - 80002d1c: fffe0eb7 lui t4,0xfffe0 - 80002d20: 01600193 li gp,22 - 80002d24: 09df1663 bne t5,t4,80002db0 - -0000000080002d28 : - 80002d28: 00000213 li tp,0 - 80002d2c: 800000b7 lui ra,0x80000 - 80002d30: 0010809b addiw ra,ra,1 - 80002d34: 00000013 nop - 80002d38: 00000013 nop - 80002d3c: 41f0df1b sraiw t5,ra,0x1f - 80002d40: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d44: 00200293 li t0,2 - 80002d48: fe5212e3 bne tp,t0,80002d2c - 80002d4c: fff00e93 li t4,-1 - 80002d50: 01700193 li gp,23 - 80002d54: 05df1e63 bne t5,t4,80002db0 - -0000000080002d58 : - 80002d58: 41f0509b sraiw ra,zero,0x1f - 80002d5c: 00000e93 li t4,0 - 80002d60: 01800193 li gp,24 - 80002d64: 05d09663 bne ra,t4,80002db0 - -0000000080002d68 : - 80002d68: 01f00093 li ra,31 - 80002d6c: 41c0d01b sraiw zero,ra,0x1c - 80002d70: 00000e93 li t4,0 - 80002d74: 01900193 li gp,25 - 80002d78: 03d01c63 bne zero,t4,80002db0 - -0000000080002d7c : - 80002d7c: 0070009b addiw ra,zero,7 - 80002d80: 03509093 slli ra,ra,0x35 - 80002d84: 41c0df1b sraiw t5,ra,0x1c - 80002d88: 00000e93 li t4,0 - 80002d8c: 01a00193 li gp,26 - 80002d90: 03df1063 bne t5,t4,80002db0 - -0000000080002d94 : - 80002d94: 00f0009b addiw ra,zero,15 - 80002d98: 01c09093 slli ra,ra,0x1c - 80002d9c: 4040df1b sraiw t5,ra,0x4 - 80002da0: ff000eb7 lui t4,0xff000 - 80002da4: 01b00193 li gp,27 - 80002da8: 01df1463 bne t5,t4,80002db0 - 80002dac: 00301a63 bne zero,gp,80002dc0 - -0000000080002db0 : - 80002db0: 00119513 slli a0,gp,0x1 - 80002db4: 00050063 beqz a0,80002db4 - 80002db8: 00156513 ori a0,a0,1 - 80002dbc: 00000073 ecall - -0000000080002dc0 : - 80002dc0: 00100513 li a0,1 - 80002dc4: 00000073 ecall - 80002dc8: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-sraiw.elf b/test/riscv/tests/rv64ui-v-sraiw.elf deleted file mode 100644 index 9a16cd8e..00000000 Binary files a/test/riscv/tests/rv64ui-v-sraiw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-sraw.dump b/test/riscv/tests/rv64ui-v-sraw.dump deleted file mode 100644 index a2eaf367..00000000 --- a/test/riscv/tests/rv64ui-v-sraw.dump +++ /dev/null @@ -1,1281 +0,0 @@ - -rv64ui-v-sraw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: c2868693 addi a3,a3,-984 # 80003080 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: c5c60613 addi a2,a2,-932 # 80003110 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: c2460613 addi a2,a2,-988 # 80003128 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: b7468693 addi a3,a3,-1164 # 800030c8 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: b9068693 addi a3,a3,-1136 # 80003200 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: b1060613 addi a2,a2,-1264 # 800031d8 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: a4468693 addi a3,a3,-1468 # 80003230 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 96468693 addi a3,a3,-1692 # 800031a0 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00001697 auipc a3,0x1 - 80002878: 8f468693 addi a3,a3,-1804 # 80003168 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 03400793 li a5,52 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 077137b7 lui a5,0x7713 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 07b78793 addi a5,a5,123 # 771307b <_start-0x788ecf85> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 800000b7 lui ra,0x80000 - 80002acc: 00000113 li sp,0 - 80002ad0: 4020df3b sraw t5,ra,sp - 80002ad4: 80000eb7 lui t4,0x80000 - 80002ad8: 00200193 li gp,2 - 80002adc: 59df1463 bne t5,t4,80003064 - -0000000080002ae0 : - 80002ae0: 800000b7 lui ra,0x80000 - 80002ae4: 00100113 li sp,1 - 80002ae8: 4020df3b sraw t5,ra,sp - 80002aec: c0000eb7 lui t4,0xc0000 - 80002af0: 00300193 li gp,3 - 80002af4: 57df1863 bne t5,t4,80003064 - -0000000080002af8 : - 80002af8: 800000b7 lui ra,0x80000 - 80002afc: 00700113 li sp,7 - 80002b00: 4020df3b sraw t5,ra,sp - 80002b04: ff000eb7 lui t4,0xff000 - 80002b08: 00400193 li gp,4 - 80002b0c: 55df1c63 bne t5,t4,80003064 - -0000000080002b10 : - 80002b10: 800000b7 lui ra,0x80000 - 80002b14: 00e00113 li sp,14 - 80002b18: 4020df3b sraw t5,ra,sp - 80002b1c: fffe0eb7 lui t4,0xfffe0 - 80002b20: 00500193 li gp,5 - 80002b24: 55df1063 bne t5,t4,80003064 - -0000000080002b28 : - 80002b28: 800000b7 lui ra,0x80000 - 80002b2c: 0010809b addiw ra,ra,1 - 80002b30: 01f00113 li sp,31 - 80002b34: 4020df3b sraw t5,ra,sp - 80002b38: fff00e93 li t4,-1 - 80002b3c: 00600193 li gp,6 - 80002b40: 53df1263 bne t5,t4,80003064 - -0000000080002b44 : - 80002b44: 800000b7 lui ra,0x80000 - 80002b48: fff0809b addiw ra,ra,-1 - 80002b4c: 00000113 li sp,0 - 80002b50: 4020df3b sraw t5,ra,sp - 80002b54: 80000eb7 lui t4,0x80000 - 80002b58: fffe8e9b addiw t4,t4,-1 - 80002b5c: 00700193 li gp,7 - 80002b60: 51df1263 bne t5,t4,80003064 - -0000000080002b64 : - 80002b64: 800000b7 lui ra,0x80000 - 80002b68: fff0809b addiw ra,ra,-1 - 80002b6c: 00100113 li sp,1 - 80002b70: 4020df3b sraw t5,ra,sp - 80002b74: 40000eb7 lui t4,0x40000 - 80002b78: fffe8e9b addiw t4,t4,-1 - 80002b7c: 00800193 li gp,8 - 80002b80: 4fdf1263 bne t5,t4,80003064 - -0000000080002b84 : - 80002b84: 800000b7 lui ra,0x80000 - 80002b88: fff0809b addiw ra,ra,-1 - 80002b8c: 00700113 li sp,7 - 80002b90: 4020df3b sraw t5,ra,sp - 80002b94: 01000eb7 lui t4,0x1000 - 80002b98: fffe8e9b addiw t4,t4,-1 - 80002b9c: 00900193 li gp,9 - 80002ba0: 4ddf1263 bne t5,t4,80003064 - -0000000080002ba4 : - 80002ba4: 800000b7 lui ra,0x80000 - 80002ba8: fff0809b addiw ra,ra,-1 - 80002bac: 00e00113 li sp,14 - 80002bb0: 4020df3b sraw t5,ra,sp - 80002bb4: 00020eb7 lui t4,0x20 - 80002bb8: fffe8e9b addiw t4,t4,-1 - 80002bbc: 00a00193 li gp,10 - 80002bc0: 4bdf1263 bne t5,t4,80003064 - -0000000080002bc4 : - 80002bc4: 800000b7 lui ra,0x80000 - 80002bc8: fff0809b addiw ra,ra,-1 - 80002bcc: 01f00113 li sp,31 - 80002bd0: 4020df3b sraw t5,ra,sp - 80002bd4: 00000e93 li t4,0 - 80002bd8: 00b00193 li gp,11 - 80002bdc: 49df1463 bne t5,t4,80003064 - -0000000080002be0 : - 80002be0: 818180b7 lui ra,0x81818 - 80002be4: 1810809b addiw ra,ra,385 - 80002be8: 00000113 li sp,0 - 80002bec: 4020df3b sraw t5,ra,sp - 80002bf0: 81818eb7 lui t4,0x81818 - 80002bf4: 181e8e9b addiw t4,t4,385 - 80002bf8: 00c00193 li gp,12 - 80002bfc: 47df1463 bne t5,t4,80003064 - -0000000080002c00 : - 80002c00: 818180b7 lui ra,0x81818 - 80002c04: 1810809b addiw ra,ra,385 - 80002c08: 00100113 li sp,1 - 80002c0c: 4020df3b sraw t5,ra,sp - 80002c10: c0c0ceb7 lui t4,0xc0c0c - 80002c14: 0c0e8e9b addiw t4,t4,192 - 80002c18: 00d00193 li gp,13 - 80002c1c: 45df1463 bne t5,t4,80003064 - -0000000080002c20 : - 80002c20: 818180b7 lui ra,0x81818 - 80002c24: 1810809b addiw ra,ra,385 - 80002c28: 00700113 li sp,7 - 80002c2c: 4020df3b sraw t5,ra,sp - 80002c30: ff030eb7 lui t4,0xff030 - 80002c34: 303e8e9b addiw t4,t4,771 - 80002c38: 00e00193 li gp,14 - 80002c3c: 43df1463 bne t5,t4,80003064 - -0000000080002c40 : - 80002c40: 818180b7 lui ra,0x81818 - 80002c44: 1810809b addiw ra,ra,385 - 80002c48: 00e00113 li sp,14 - 80002c4c: 4020df3b sraw t5,ra,sp - 80002c50: fffe0eb7 lui t4,0xfffe0 - 80002c54: 606e8e9b addiw t4,t4,1542 - 80002c58: 00f00193 li gp,15 - 80002c5c: 41df1463 bne t5,t4,80003064 - -0000000080002c60 : - 80002c60: 818180b7 lui ra,0x81818 - 80002c64: 1810809b addiw ra,ra,385 - 80002c68: 01f00113 li sp,31 - 80002c6c: 4020df3b sraw t5,ra,sp - 80002c70: fff00e93 li t4,-1 - 80002c74: 01000193 li gp,16 - 80002c78: 3fdf1663 bne t5,t4,80003064 - -0000000080002c7c : - 80002c7c: 818180b7 lui ra,0x81818 - 80002c80: 1810809b addiw ra,ra,385 - 80002c84: fe000113 li sp,-32 - 80002c88: 4020df3b sraw t5,ra,sp - 80002c8c: 81818eb7 lui t4,0x81818 - 80002c90: 181e8e9b addiw t4,t4,385 - 80002c94: 01100193 li gp,17 - 80002c98: 3ddf1663 bne t5,t4,80003064 - -0000000080002c9c : - 80002c9c: 818180b7 lui ra,0x81818 - 80002ca0: 1810809b addiw ra,ra,385 - 80002ca4: fe100113 li sp,-31 - 80002ca8: 4020df3b sraw t5,ra,sp - 80002cac: c0c0ceb7 lui t4,0xc0c0c - 80002cb0: 0c0e8e9b addiw t4,t4,192 - 80002cb4: 01200193 li gp,18 - 80002cb8: 3bdf1663 bne t5,t4,80003064 - -0000000080002cbc : - 80002cbc: 818180b7 lui ra,0x81818 - 80002cc0: 1810809b addiw ra,ra,385 - 80002cc4: fe700113 li sp,-25 - 80002cc8: 4020df3b sraw t5,ra,sp - 80002ccc: ff030eb7 lui t4,0xff030 - 80002cd0: 303e8e9b addiw t4,t4,771 - 80002cd4: 01300193 li gp,19 - 80002cd8: 39df1663 bne t5,t4,80003064 - -0000000080002cdc : - 80002cdc: 818180b7 lui ra,0x81818 - 80002ce0: 1810809b addiw ra,ra,385 - 80002ce4: fee00113 li sp,-18 - 80002ce8: 4020df3b sraw t5,ra,sp - 80002cec: fffe0eb7 lui t4,0xfffe0 - 80002cf0: 606e8e9b addiw t4,t4,1542 - 80002cf4: 01400193 li gp,20 - 80002cf8: 37df1663 bne t5,t4,80003064 - -0000000080002cfc : - 80002cfc: 818180b7 lui ra,0x81818 - 80002d00: 1810809b addiw ra,ra,385 - 80002d04: fff00113 li sp,-1 - 80002d08: 4020df3b sraw t5,ra,sp - 80002d0c: fff00e93 li t4,-1 - 80002d10: 01500193 li gp,21 - 80002d14: 35df1863 bne t5,t4,80003064 - -0000000080002d18 : - 80002d18: 800000b7 lui ra,0x80000 - 80002d1c: 00700113 li sp,7 - 80002d20: 4020d0bb sraw ra,ra,sp - 80002d24: ff000eb7 lui t4,0xff000 - 80002d28: 01600193 li gp,22 - 80002d2c: 33d09c63 bne ra,t4,80003064 - -0000000080002d30 : - 80002d30: 800000b7 lui ra,0x80000 - 80002d34: 00e00113 li sp,14 - 80002d38: 4020d13b sraw sp,ra,sp - 80002d3c: fffe0eb7 lui t4,0xfffe0 - 80002d40: 01700193 li gp,23 - 80002d44: 33d11063 bne sp,t4,80003064 - -0000000080002d48 : - 80002d48: 00700093 li ra,7 - 80002d4c: 4010d0bb sraw ra,ra,ra - 80002d50: 00000e93 li t4,0 - 80002d54: 01800193 li gp,24 - 80002d58: 31d09663 bne ra,t4,80003064 - -0000000080002d5c : - 80002d5c: 00000213 li tp,0 - 80002d60: 800000b7 lui ra,0x80000 - 80002d64: 00700113 li sp,7 - 80002d68: 4020df3b sraw t5,ra,sp - 80002d6c: 000f0313 mv t1,t5 - 80002d70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d74: 00200293 li t0,2 - 80002d78: fe5214e3 bne tp,t0,80002d60 - 80002d7c: ff000eb7 lui t4,0xff000 - 80002d80: 01900193 li gp,25 - 80002d84: 2fd31063 bne t1,t4,80003064 - -0000000080002d88 : - 80002d88: 00000213 li tp,0 - 80002d8c: 800000b7 lui ra,0x80000 - 80002d90: 00e00113 li sp,14 - 80002d94: 4020df3b sraw t5,ra,sp - 80002d98: 00000013 nop - 80002d9c: 000f0313 mv t1,t5 - 80002da0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002da4: 00200293 li t0,2 - 80002da8: fe5212e3 bne tp,t0,80002d8c - 80002dac: fffe0eb7 lui t4,0xfffe0 - 80002db0: 01a00193 li gp,26 - 80002db4: 2bd31863 bne t1,t4,80003064 - -0000000080002db8 : - 80002db8: 00000213 li tp,0 - 80002dbc: 800000b7 lui ra,0x80000 - 80002dc0: 01f00113 li sp,31 - 80002dc4: 4020df3b sraw t5,ra,sp - 80002dc8: 00000013 nop - 80002dcc: 00000013 nop - 80002dd0: 000f0313 mv t1,t5 - 80002dd4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dd8: 00200293 li t0,2 - 80002ddc: fe5210e3 bne tp,t0,80002dbc - 80002de0: fff00e93 li t4,-1 - 80002de4: 01b00193 li gp,27 - 80002de8: 27d31e63 bne t1,t4,80003064 - -0000000080002dec : - 80002dec: 00000213 li tp,0 - 80002df0: 800000b7 lui ra,0x80000 - 80002df4: 00700113 li sp,7 - 80002df8: 4020df3b sraw t5,ra,sp - 80002dfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e00: 00200293 li t0,2 - 80002e04: fe5216e3 bne tp,t0,80002df0 - 80002e08: ff000eb7 lui t4,0xff000 - 80002e0c: 01c00193 li gp,28 - 80002e10: 25df1a63 bne t5,t4,80003064 - -0000000080002e14 : - 80002e14: 00000213 li tp,0 - 80002e18: 800000b7 lui ra,0x80000 - 80002e1c: 00e00113 li sp,14 - 80002e20: 00000013 nop - 80002e24: 4020df3b sraw t5,ra,sp - 80002e28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e2c: 00200293 li t0,2 - 80002e30: fe5214e3 bne tp,t0,80002e18 - 80002e34: fffe0eb7 lui t4,0xfffe0 - 80002e38: 01d00193 li gp,29 - 80002e3c: 23df1463 bne t5,t4,80003064 - -0000000080002e40 : - 80002e40: 00000213 li tp,0 - 80002e44: 800000b7 lui ra,0x80000 - 80002e48: 01f00113 li sp,31 - 80002e4c: 00000013 nop - 80002e50: 00000013 nop - 80002e54: 4020df3b sraw t5,ra,sp - 80002e58: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e5c: 00200293 li t0,2 - 80002e60: fe5212e3 bne tp,t0,80002e44 - 80002e64: fff00e93 li t4,-1 - 80002e68: 01e00193 li gp,30 - 80002e6c: 1fdf1c63 bne t5,t4,80003064 - -0000000080002e70 : - 80002e70: 00000213 li tp,0 - 80002e74: 800000b7 lui ra,0x80000 - 80002e78: 00000013 nop - 80002e7c: 00700113 li sp,7 - 80002e80: 4020df3b sraw t5,ra,sp - 80002e84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e88: 00200293 li t0,2 - 80002e8c: fe5214e3 bne tp,t0,80002e74 - 80002e90: ff000eb7 lui t4,0xff000 - 80002e94: 01f00193 li gp,31 - 80002e98: 1ddf1663 bne t5,t4,80003064 - -0000000080002e9c : - 80002e9c: 00000213 li tp,0 - 80002ea0: 800000b7 lui ra,0x80000 - 80002ea4: 00000013 nop - 80002ea8: 00e00113 li sp,14 - 80002eac: 00000013 nop - 80002eb0: 4020df3b sraw t5,ra,sp - 80002eb4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002eb8: 00200293 li t0,2 - 80002ebc: fe5212e3 bne tp,t0,80002ea0 - 80002ec0: fffe0eb7 lui t4,0xfffe0 - 80002ec4: 02000193 li gp,32 - 80002ec8: 19df1e63 bne t5,t4,80003064 - -0000000080002ecc : - 80002ecc: 00000213 li tp,0 - 80002ed0: 800000b7 lui ra,0x80000 - 80002ed4: 00000013 nop - 80002ed8: 00000013 nop - 80002edc: 01f00113 li sp,31 - 80002ee0: 4020df3b sraw t5,ra,sp - 80002ee4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ee8: 00200293 li t0,2 - 80002eec: fe5212e3 bne tp,t0,80002ed0 - 80002ef0: fff00e93 li t4,-1 - 80002ef4: 02100193 li gp,33 - 80002ef8: 17df1663 bne t5,t4,80003064 - -0000000080002efc : - 80002efc: 00000213 li tp,0 - 80002f00: 00700113 li sp,7 - 80002f04: 800000b7 lui ra,0x80000 - 80002f08: 4020df3b sraw t5,ra,sp - 80002f0c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f10: 00200293 li t0,2 - 80002f14: fe5216e3 bne tp,t0,80002f00 - 80002f18: ff000eb7 lui t4,0xff000 - 80002f1c: 02200193 li gp,34 - 80002f20: 15df1263 bne t5,t4,80003064 - -0000000080002f24 : - 80002f24: 00000213 li tp,0 - 80002f28: 00e00113 li sp,14 - 80002f2c: 800000b7 lui ra,0x80000 - 80002f30: 00000013 nop - 80002f34: 4020df3b sraw t5,ra,sp - 80002f38: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f3c: 00200293 li t0,2 - 80002f40: fe5214e3 bne tp,t0,80002f28 - 80002f44: fffe0eb7 lui t4,0xfffe0 - 80002f48: 02300193 li gp,35 - 80002f4c: 11df1c63 bne t5,t4,80003064 - -0000000080002f50 : - 80002f50: 00000213 li tp,0 - 80002f54: 01f00113 li sp,31 - 80002f58: 800000b7 lui ra,0x80000 - 80002f5c: 00000013 nop - 80002f60: 00000013 nop - 80002f64: 4020df3b sraw t5,ra,sp - 80002f68: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f6c: 00200293 li t0,2 - 80002f70: fe5212e3 bne tp,t0,80002f54 - 80002f74: fff00e93 li t4,-1 - 80002f78: 02400193 li gp,36 - 80002f7c: 0fdf1463 bne t5,t4,80003064 - -0000000080002f80 : - 80002f80: 00000213 li tp,0 - 80002f84: 00700113 li sp,7 - 80002f88: 00000013 nop - 80002f8c: 800000b7 lui ra,0x80000 - 80002f90: 4020df3b sraw t5,ra,sp - 80002f94: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f98: 00200293 li t0,2 - 80002f9c: fe5214e3 bne tp,t0,80002f84 - 80002fa0: ff000eb7 lui t4,0xff000 - 80002fa4: 02500193 li gp,37 - 80002fa8: 0bdf1e63 bne t5,t4,80003064 - -0000000080002fac : - 80002fac: 00000213 li tp,0 - 80002fb0: 00e00113 li sp,14 - 80002fb4: 00000013 nop - 80002fb8: 800000b7 lui ra,0x80000 - 80002fbc: 00000013 nop - 80002fc0: 4020df3b sraw t5,ra,sp - 80002fc4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002fc8: 00200293 li t0,2 - 80002fcc: fe5212e3 bne tp,t0,80002fb0 - 80002fd0: fffe0eb7 lui t4,0xfffe0 - 80002fd4: 02600193 li gp,38 - 80002fd8: 09df1663 bne t5,t4,80003064 - -0000000080002fdc : - 80002fdc: 00000213 li tp,0 - 80002fe0: 01f00113 li sp,31 - 80002fe4: 00000013 nop - 80002fe8: 00000013 nop - 80002fec: 800000b7 lui ra,0x80000 - 80002ff0: 4020df3b sraw t5,ra,sp - 80002ff4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ff8: 00200293 li t0,2 - 80002ffc: fe5212e3 bne tp,t0,80002fe0 - 80003000: fff00e93 li t4,-1 - 80003004: 02700193 li gp,39 - 80003008: 05df1e63 bne t5,t4,80003064 - -000000008000300c : - 8000300c: 00f00093 li ra,15 - 80003010: 4010513b sraw sp,zero,ra - 80003014: 00000e93 li t4,0 - 80003018: 02800193 li gp,40 - 8000301c: 05d11463 bne sp,t4,80003064 - -0000000080003020 : - 80003020: 02000093 li ra,32 - 80003024: 4000d13b sraw sp,ra,zero - 80003028: 02000e93 li t4,32 - 8000302c: 02900193 li gp,41 - 80003030: 03d11a63 bne sp,t4,80003064 - -0000000080003034 : - 80003034: 400050bb sraw ra,zero,zero - 80003038: 00000e93 li t4,0 - 8000303c: 02a00193 li gp,42 - 80003040: 03d09263 bne ra,t4,80003064 - -0000000080003044 : - 80003044: 40000093 li ra,1024 - 80003048: 00001137 lui sp,0x1 - 8000304c: 8001011b addiw sp,sp,-2048 - 80003050: 4020d03b sraw zero,ra,sp - 80003054: 00000e93 li t4,0 - 80003058: 02b00193 li gp,43 - 8000305c: 01d01463 bne zero,t4,80003064 - 80003060: 00301a63 bne zero,gp,80003074 - -0000000080003064 : - 80003064: 00119513 slli a0,gp,0x1 - 80003068: 00050063 beqz a0,80003068 - 8000306c: 00156513 ori a0,a0,1 - 80003070: 00000073 ecall - -0000000080003074 : - 80003074: 00100513 li a0,1 - 80003078: 00000073 ecall - 8000307c: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-sraw.elf b/test/riscv/tests/rv64ui-v-sraw.elf deleted file mode 100644 index 8894a1c3..00000000 Binary files a/test/riscv/tests/rv64ui-v-sraw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-srl.dump b/test/riscv/tests/rv64ui-v-srl.dump deleted file mode 100644 index 1fb24ac1..00000000 --- a/test/riscv/tests/rv64ui-v-srl.dump +++ /dev/null @@ -1,1308 +0,0 @@ - -rv64ui-v-srl: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: c9868693 addi a3,a3,-872 # 800030f0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: ccc60613 addi a2,a2,-820 # 80003180 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: c9460613 addi a2,a2,-876 # 80003198 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: be468693 addi a3,a3,-1052 # 80003138 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: c0068693 addi a3,a3,-1024 # 80003270 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: b8060613 addi a2,a2,-1152 # 80003248 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: ab468693 addi a3,a3,-1356 # 800032a0 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 9d468693 addi a3,a3,-1580 # 80003210 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00001697 auipc a3,0x1 - 80002878: 96468693 addi a3,a3,-1692 # 800031d8 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 02700793 li a5,39 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 01e8a7b7 lui a5,0x1e8a - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 84078793 addi a5,a5,-1984 # 1e89840 <_start-0x7e1767c0> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 800000b7 lui ra,0x80000 - 80002acc: 00000113 li sp,0 - 80002ad0: 0020df33 srl t5,ra,sp - 80002ad4: 80000eb7 lui t4,0x80000 - 80002ad8: 00200193 li gp,2 - 80002adc: 5fdf1a63 bne t5,t4,800030d0 - -0000000080002ae0 : - 80002ae0: 800000b7 lui ra,0x80000 - 80002ae4: 00100113 li sp,1 - 80002ae8: 0020df33 srl t5,ra,sp - 80002aec: 00100e9b addiw t4,zero,1 - 80002af0: 021e9e93 slli t4,t4,0x21 - 80002af4: fffe8e93 addi t4,t4,-1 # ffffffff7fffffff <_end+0xfffffffeffff780f> - 80002af8: 01ee9e93 slli t4,t4,0x1e - 80002afc: 00300193 li gp,3 - 80002b00: 5ddf1863 bne t5,t4,800030d0 - -0000000080002b04 : - 80002b04: 800000b7 lui ra,0x80000 - 80002b08: 00700113 li sp,7 - 80002b0c: 0020df33 srl t5,ra,sp - 80002b10: 00100e9b addiw t4,zero,1 - 80002b14: 021e9e93 slli t4,t4,0x21 - 80002b18: fffe8e93 addi t4,t4,-1 - 80002b1c: 018e9e93 slli t4,t4,0x18 - 80002b20: 00400193 li gp,4 - 80002b24: 5bdf1663 bne t5,t4,800030d0 - -0000000080002b28 : - 80002b28: 800000b7 lui ra,0x80000 - 80002b2c: 00e00113 li sp,14 - 80002b30: 0020df33 srl t5,ra,sp - 80002b34: 00100e9b addiw t4,zero,1 - 80002b38: 021e9e93 slli t4,t4,0x21 - 80002b3c: fffe8e93 addi t4,t4,-1 - 80002b40: 011e9e93 slli t4,t4,0x11 - 80002b44: 00500193 li gp,5 - 80002b48: 59df1463 bne t5,t4,800030d0 - -0000000080002b4c : - 80002b4c: 800000b7 lui ra,0x80000 - 80002b50: 0010809b addiw ra,ra,1 - 80002b54: 01f00113 li sp,31 - 80002b58: 0020df33 srl t5,ra,sp - 80002b5c: 00100e9b addiw t4,zero,1 - 80002b60: 021e9e93 slli t4,t4,0x21 - 80002b64: fffe8e93 addi t4,t4,-1 - 80002b68: 00600193 li gp,6 - 80002b6c: 57df1263 bne t5,t4,800030d0 - -0000000080002b70 : - 80002b70: fff00093 li ra,-1 - 80002b74: 00000113 li sp,0 - 80002b78: 0020df33 srl t5,ra,sp - 80002b7c: fff00e93 li t4,-1 - 80002b80: 00700193 li gp,7 - 80002b84: 55df1663 bne t5,t4,800030d0 - -0000000080002b88 : - 80002b88: fff00093 li ra,-1 - 80002b8c: 00100113 li sp,1 - 80002b90: 0020df33 srl t5,ra,sp - 80002b94: fff00e9b addiw t4,zero,-1 - 80002b98: 03fe9e93 slli t4,t4,0x3f - 80002b9c: fffe8e93 addi t4,t4,-1 - 80002ba0: 00800193 li gp,8 - 80002ba4: 53df1663 bne t5,t4,800030d0 - -0000000080002ba8 : - 80002ba8: fff00093 li ra,-1 - 80002bac: 00700113 li sp,7 - 80002bb0: 0020df33 srl t5,ra,sp - 80002bb4: 00100e9b addiw t4,zero,1 - 80002bb8: 039e9e93 slli t4,t4,0x39 - 80002bbc: fffe8e93 addi t4,t4,-1 - 80002bc0: 00900193 li gp,9 - 80002bc4: 51df1663 bne t5,t4,800030d0 - -0000000080002bc8 : - 80002bc8: fff00093 li ra,-1 - 80002bcc: 00e00113 li sp,14 - 80002bd0: 0020df33 srl t5,ra,sp - 80002bd4: 00100e9b addiw t4,zero,1 - 80002bd8: 032e9e93 slli t4,t4,0x32 - 80002bdc: fffe8e93 addi t4,t4,-1 - 80002be0: 00a00193 li gp,10 - 80002be4: 4fdf1663 bne t5,t4,800030d0 - -0000000080002be8 : - 80002be8: fff00093 li ra,-1 - 80002bec: 01f00113 li sp,31 - 80002bf0: 0020df33 srl t5,ra,sp - 80002bf4: 00100e9b addiw t4,zero,1 - 80002bf8: 021e9e93 slli t4,t4,0x21 - 80002bfc: fffe8e93 addi t4,t4,-1 - 80002c00: 00b00193 li gp,11 - 80002c04: 4ddf1663 bne t5,t4,800030d0 - -0000000080002c08 : - 80002c08: 212120b7 lui ra,0x21212 - 80002c0c: 1210809b addiw ra,ra,289 - 80002c10: 00000113 li sp,0 - 80002c14: 0020df33 srl t5,ra,sp - 80002c18: 21212eb7 lui t4,0x21212 - 80002c1c: 121e8e9b addiw t4,t4,289 - 80002c20: 00c00193 li gp,12 - 80002c24: 4bdf1663 bne t5,t4,800030d0 - -0000000080002c28 : - 80002c28: 212120b7 lui ra,0x21212 - 80002c2c: 1210809b addiw ra,ra,289 - 80002c30: 00100113 li sp,1 - 80002c34: 0020df33 srl t5,ra,sp - 80002c38: 10909eb7 lui t4,0x10909 - 80002c3c: 090e8e9b addiw t4,t4,144 - 80002c40: 00d00193 li gp,13 - 80002c44: 49df1663 bne t5,t4,800030d0 - -0000000080002c48 : - 80002c48: 212120b7 lui ra,0x21212 - 80002c4c: 1210809b addiw ra,ra,289 - 80002c50: 00700113 li sp,7 - 80002c54: 0020df33 srl t5,ra,sp - 80002c58: 00424eb7 lui t4,0x424 - 80002c5c: 242e8e9b addiw t4,t4,578 - 80002c60: 00e00193 li gp,14 - 80002c64: 47df1663 bne t5,t4,800030d0 - -0000000080002c68 : - 80002c68: 212120b7 lui ra,0x21212 - 80002c6c: 1210809b addiw ra,ra,289 - 80002c70: 00e00113 li sp,14 - 80002c74: 0020df33 srl t5,ra,sp - 80002c78: 00008eb7 lui t4,0x8 - 80002c7c: 484e8e9b addiw t4,t4,1156 - 80002c80: 00f00193 li gp,15 - 80002c84: 45df1663 bne t5,t4,800030d0 - -0000000080002c88 : - 80002c88: 212120b7 lui ra,0x21212 - 80002c8c: 1210809b addiw ra,ra,289 - 80002c90: 01f00113 li sp,31 - 80002c94: 0020df33 srl t5,ra,sp - 80002c98: 00000e93 li t4,0 - 80002c9c: 01000193 li gp,16 - 80002ca0: 43df1863 bne t5,t4,800030d0 - -0000000080002ca4 : - 80002ca4: 212120b7 lui ra,0x21212 - 80002ca8: 1210809b addiw ra,ra,289 - 80002cac: fc000113 li sp,-64 - 80002cb0: 0020df33 srl t5,ra,sp - 80002cb4: 21212eb7 lui t4,0x21212 - 80002cb8: 121e8e9b addiw t4,t4,289 - 80002cbc: 01100193 li gp,17 - 80002cc0: 41df1863 bne t5,t4,800030d0 - -0000000080002cc4 : - 80002cc4: 212120b7 lui ra,0x21212 - 80002cc8: 1210809b addiw ra,ra,289 - 80002ccc: fc100113 li sp,-63 - 80002cd0: 0020df33 srl t5,ra,sp - 80002cd4: 10909eb7 lui t4,0x10909 - 80002cd8: 090e8e9b addiw t4,t4,144 - 80002cdc: 01200193 li gp,18 - 80002ce0: 3fdf1863 bne t5,t4,800030d0 - -0000000080002ce4 : - 80002ce4: 212120b7 lui ra,0x21212 - 80002ce8: 1210809b addiw ra,ra,289 - 80002cec: fc700113 li sp,-57 - 80002cf0: 0020df33 srl t5,ra,sp - 80002cf4: 00424eb7 lui t4,0x424 - 80002cf8: 242e8e9b addiw t4,t4,578 - 80002cfc: 01300193 li gp,19 - 80002d00: 3ddf1863 bne t5,t4,800030d0 - -0000000080002d04 : - 80002d04: 212120b7 lui ra,0x21212 - 80002d08: 1210809b addiw ra,ra,289 - 80002d0c: fce00113 li sp,-50 - 80002d10: 0020df33 srl t5,ra,sp - 80002d14: 00008eb7 lui t4,0x8 - 80002d18: 484e8e9b addiw t4,t4,1156 - 80002d1c: 01400193 li gp,20 - 80002d20: 3bdf1863 bne t5,t4,800030d0 - -0000000080002d24 : - 80002d24: 212120b7 lui ra,0x21212 - 80002d28: 1210809b addiw ra,ra,289 - 80002d2c: fff00113 li sp,-1 - 80002d30: 0020df33 srl t5,ra,sp - 80002d34: 00000e93 li t4,0 - 80002d38: 01500193 li gp,21 - 80002d3c: 39df1a63 bne t5,t4,800030d0 - -0000000080002d40 : - 80002d40: 0010009b addiw ra,zero,1 - 80002d44: 01f09093 slli ra,ra,0x1f - 80002d48: 00700113 li sp,7 - 80002d4c: 0020d0b3 srl ra,ra,sp - 80002d50: 01000eb7 lui t4,0x1000 - 80002d54: 01600193 li gp,22 - 80002d58: 37d09c63 bne ra,t4,800030d0 - -0000000080002d5c : - 80002d5c: 0010009b addiw ra,zero,1 - 80002d60: 01f09093 slli ra,ra,0x1f - 80002d64: 00e00113 li sp,14 - 80002d68: 0020d133 srl sp,ra,sp - 80002d6c: 00020eb7 lui t4,0x20 - 80002d70: 01700193 li gp,23 - 80002d74: 35d11e63 bne sp,t4,800030d0 - -0000000080002d78 : - 80002d78: 00700093 li ra,7 - 80002d7c: 0010d0b3 srl ra,ra,ra - 80002d80: 00000e93 li t4,0 - 80002d84: 01800193 li gp,24 - 80002d88: 35d09463 bne ra,t4,800030d0 - -0000000080002d8c : - 80002d8c: 00000213 li tp,0 - 80002d90: 0010009b addiw ra,zero,1 - 80002d94: 01f09093 slli ra,ra,0x1f - 80002d98: 00700113 li sp,7 - 80002d9c: 0020df33 srl t5,ra,sp - 80002da0: 000f0313 mv t1,t5 - 80002da4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002da8: 00200293 li t0,2 - 80002dac: fe5212e3 bne tp,t0,80002d90 - 80002db0: 01000eb7 lui t4,0x1000 - 80002db4: 01900193 li gp,25 - 80002db8: 31d31c63 bne t1,t4,800030d0 - -0000000080002dbc : - 80002dbc: 00000213 li tp,0 - 80002dc0: 0010009b addiw ra,zero,1 - 80002dc4: 01f09093 slli ra,ra,0x1f - 80002dc8: 00e00113 li sp,14 - 80002dcc: 0020df33 srl t5,ra,sp - 80002dd0: 00000013 nop - 80002dd4: 000f0313 mv t1,t5 - 80002dd8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ddc: 00200293 li t0,2 - 80002de0: fe5210e3 bne tp,t0,80002dc0 - 80002de4: 00020eb7 lui t4,0x20 - 80002de8: 01a00193 li gp,26 - 80002dec: 2fd31263 bne t1,t4,800030d0 - -0000000080002df0 : - 80002df0: 00000213 li tp,0 - 80002df4: 0010009b addiw ra,zero,1 - 80002df8: 01f09093 slli ra,ra,0x1f - 80002dfc: 01f00113 li sp,31 - 80002e00: 0020df33 srl t5,ra,sp - 80002e04: 00000013 nop - 80002e08: 00000013 nop - 80002e0c: 000f0313 mv t1,t5 - 80002e10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e14: 00200293 li t0,2 - 80002e18: fc521ee3 bne tp,t0,80002df4 - 80002e1c: 00100e93 li t4,1 - 80002e20: 01b00193 li gp,27 - 80002e24: 2bd31663 bne t1,t4,800030d0 - -0000000080002e28 : - 80002e28: 00000213 li tp,0 - 80002e2c: 0010009b addiw ra,zero,1 - 80002e30: 01f09093 slli ra,ra,0x1f - 80002e34: 00700113 li sp,7 - 80002e38: 0020df33 srl t5,ra,sp - 80002e3c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e40: 00200293 li t0,2 - 80002e44: fe5214e3 bne tp,t0,80002e2c - 80002e48: 01000eb7 lui t4,0x1000 - 80002e4c: 01c00193 li gp,28 - 80002e50: 29df1063 bne t5,t4,800030d0 - -0000000080002e54 : - 80002e54: 00000213 li tp,0 - 80002e58: 0010009b addiw ra,zero,1 - 80002e5c: 01f09093 slli ra,ra,0x1f - 80002e60: 00e00113 li sp,14 - 80002e64: 00000013 nop - 80002e68: 0020df33 srl t5,ra,sp - 80002e6c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e70: 00200293 li t0,2 - 80002e74: fe5212e3 bne tp,t0,80002e58 - 80002e78: 00020eb7 lui t4,0x20 - 80002e7c: 01d00193 li gp,29 - 80002e80: 25df1863 bne t5,t4,800030d0 - -0000000080002e84 : - 80002e84: 00000213 li tp,0 - 80002e88: 0010009b addiw ra,zero,1 - 80002e8c: 01f09093 slli ra,ra,0x1f - 80002e90: 01f00113 li sp,31 - 80002e94: 00000013 nop - 80002e98: 00000013 nop - 80002e9c: 0020df33 srl t5,ra,sp - 80002ea0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ea4: 00200293 li t0,2 - 80002ea8: fe5210e3 bne tp,t0,80002e88 - 80002eac: 00100e93 li t4,1 - 80002eb0: 01e00193 li gp,30 - 80002eb4: 21df1e63 bne t5,t4,800030d0 - -0000000080002eb8 : - 80002eb8: 00000213 li tp,0 - 80002ebc: 0010009b addiw ra,zero,1 - 80002ec0: 01f09093 slli ra,ra,0x1f - 80002ec4: 00000013 nop - 80002ec8: 00700113 li sp,7 - 80002ecc: 0020df33 srl t5,ra,sp - 80002ed0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ed4: 00200293 li t0,2 - 80002ed8: fe5212e3 bne tp,t0,80002ebc - 80002edc: 01000eb7 lui t4,0x1000 - 80002ee0: 01f00193 li gp,31 - 80002ee4: 1fdf1663 bne t5,t4,800030d0 - -0000000080002ee8 : - 80002ee8: 00000213 li tp,0 - 80002eec: 0010009b addiw ra,zero,1 - 80002ef0: 01f09093 slli ra,ra,0x1f - 80002ef4: 00000013 nop - 80002ef8: 00e00113 li sp,14 - 80002efc: 00000013 nop - 80002f00: 0020df33 srl t5,ra,sp - 80002f04: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f08: 00200293 li t0,2 - 80002f0c: fe5210e3 bne tp,t0,80002eec - 80002f10: 00020eb7 lui t4,0x20 - 80002f14: 02000193 li gp,32 - 80002f18: 1bdf1c63 bne t5,t4,800030d0 - -0000000080002f1c : - 80002f1c: 00000213 li tp,0 - 80002f20: 0010009b addiw ra,zero,1 - 80002f24: 01f09093 slli ra,ra,0x1f - 80002f28: 00000013 nop - 80002f2c: 00000013 nop - 80002f30: 01f00113 li sp,31 - 80002f34: 0020df33 srl t5,ra,sp - 80002f38: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f3c: 00200293 li t0,2 - 80002f40: fe5210e3 bne tp,t0,80002f20 - 80002f44: 00100e93 li t4,1 - 80002f48: 02100193 li gp,33 - 80002f4c: 19df1263 bne t5,t4,800030d0 - -0000000080002f50 : - 80002f50: 00000213 li tp,0 - 80002f54: 00700113 li sp,7 - 80002f58: 0010009b addiw ra,zero,1 - 80002f5c: 01f09093 slli ra,ra,0x1f - 80002f60: 0020df33 srl t5,ra,sp - 80002f64: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f68: 00200293 li t0,2 - 80002f6c: fe5214e3 bne tp,t0,80002f54 - 80002f70: 01000eb7 lui t4,0x1000 - 80002f74: 02200193 li gp,34 - 80002f78: 15df1c63 bne t5,t4,800030d0 - -0000000080002f7c : - 80002f7c: 00000213 li tp,0 - 80002f80: 00e00113 li sp,14 - 80002f84: 0010009b addiw ra,zero,1 - 80002f88: 01f09093 slli ra,ra,0x1f - 80002f8c: 00000013 nop - 80002f90: 0020df33 srl t5,ra,sp - 80002f94: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f98: 00200293 li t0,2 - 80002f9c: fe5212e3 bne tp,t0,80002f80 - 80002fa0: 00020eb7 lui t4,0x20 - 80002fa4: 02300193 li gp,35 - 80002fa8: 13df1463 bne t5,t4,800030d0 - -0000000080002fac : - 80002fac: 00000213 li tp,0 - 80002fb0: 01f00113 li sp,31 - 80002fb4: 0010009b addiw ra,zero,1 - 80002fb8: 01f09093 slli ra,ra,0x1f - 80002fbc: 00000013 nop - 80002fc0: 00000013 nop - 80002fc4: 0020df33 srl t5,ra,sp - 80002fc8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002fcc: 00200293 li t0,2 - 80002fd0: fe5210e3 bne tp,t0,80002fb0 - 80002fd4: 00100e93 li t4,1 - 80002fd8: 02400193 li gp,36 - 80002fdc: 0fdf1a63 bne t5,t4,800030d0 - -0000000080002fe0 : - 80002fe0: 00000213 li tp,0 - 80002fe4: 00700113 li sp,7 - 80002fe8: 00000013 nop - 80002fec: 0010009b addiw ra,zero,1 - 80002ff0: 01f09093 slli ra,ra,0x1f - 80002ff4: 0020df33 srl t5,ra,sp - 80002ff8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ffc: 00200293 li t0,2 - 80003000: fe5212e3 bne tp,t0,80002fe4 - 80003004: 01000eb7 lui t4,0x1000 - 80003008: 02500193 li gp,37 - 8000300c: 0ddf1263 bne t5,t4,800030d0 - -0000000080003010 : - 80003010: 00000213 li tp,0 - 80003014: 00e00113 li sp,14 - 80003018: 00000013 nop - 8000301c: 0010009b addiw ra,zero,1 - 80003020: 01f09093 slli ra,ra,0x1f - 80003024: 00000013 nop - 80003028: 0020df33 srl t5,ra,sp - 8000302c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80003030: 00200293 li t0,2 - 80003034: fe5210e3 bne tp,t0,80003014 - 80003038: 00020eb7 lui t4,0x20 - 8000303c: 02600193 li gp,38 - 80003040: 09df1863 bne t5,t4,800030d0 - -0000000080003044 : - 80003044: 00000213 li tp,0 - 80003048: 01f00113 li sp,31 - 8000304c: 00000013 nop - 80003050: 00000013 nop - 80003054: 0010009b addiw ra,zero,1 - 80003058: 01f09093 slli ra,ra,0x1f - 8000305c: 0020df33 srl t5,ra,sp - 80003060: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80003064: 00200293 li t0,2 - 80003068: fe5210e3 bne tp,t0,80003048 - 8000306c: 00100e93 li t4,1 - 80003070: 02700193 li gp,39 - 80003074: 05df1e63 bne t5,t4,800030d0 - -0000000080003078 : - 80003078: 00f00093 li ra,15 - 8000307c: 00105133 srl sp,zero,ra - 80003080: 00000e93 li t4,0 - 80003084: 02800193 li gp,40 - 80003088: 05d11463 bne sp,t4,800030d0 - -000000008000308c : - 8000308c: 02000093 li ra,32 - 80003090: 0000d133 srl sp,ra,zero - 80003094: 02000e93 li t4,32 - 80003098: 02900193 li gp,41 - 8000309c: 03d11a63 bne sp,t4,800030d0 - -00000000800030a0 : - 800030a0: 000050b3 srl ra,zero,zero - 800030a4: 00000e93 li t4,0 - 800030a8: 02a00193 li gp,42 - 800030ac: 03d09263 bne ra,t4,800030d0 - -00000000800030b0 : - 800030b0: 40000093 li ra,1024 - 800030b4: 00001137 lui sp,0x1 - 800030b8: 8001011b addiw sp,sp,-2048 - 800030bc: 0020d033 srl zero,ra,sp - 800030c0: 00000e93 li t4,0 - 800030c4: 02b00193 li gp,43 - 800030c8: 01d01463 bne zero,t4,800030d0 - 800030cc: 00301a63 bne zero,gp,800030e0 - -00000000800030d0 : - 800030d0: 00119513 slli a0,gp,0x1 - 800030d4: 00050063 beqz a0,800030d4 - 800030d8: 00156513 ori a0,a0,1 - 800030dc: 00000073 ecall - -00000000800030e0 : - 800030e0: 00100513 li a0,1 - 800030e4: 00000073 ecall - 800030e8: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-srl.elf b/test/riscv/tests/rv64ui-v-srl.elf deleted file mode 100644 index eb8b7327..00000000 Binary files a/test/riscv/tests/rv64ui-v-srl.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-srli.dump b/test/riscv/tests/rv64ui-v-srli.dump deleted file mode 100644 index d900518e..00000000 --- a/test/riscv/tests/rv64ui-v-srli.dump +++ /dev/null @@ -1,1077 +0,0 @@ - -rv64ui-v-srli: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 98868693 addi a3,a3,-1656 # 80002de0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 9bc60613 addi a2,a2,-1604 # 80002e70 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 98460613 addi a2,a2,-1660 # 80002e88 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 8d468693 addi a3,a3,-1836 # 80002e28 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 8f068693 addi a3,a3,-1808 # 80002f60 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 87060613 addi a2,a2,-1936 # 80002f38 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 7a468693 addi a3,a3,1956 # 80002f90 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 6c468693 addi a3,a3,1732 # 80002f00 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 65468693 addi a3,a3,1620 # 80002ec8 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 02e00793 li a5,46 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0d3727b7 lui a5,0xd372 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 50c78793 addi a5,a5,1292 # d37250c <_start-0x72c8daf4> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 800000b7 lui ra,0x80000 - 80002acc: 0000df13 srli t5,ra,0x0 - 80002ad0: 80000eb7 lui t4,0x80000 - 80002ad4: 00200193 li gp,2 - 80002ad8: 2fdf1663 bne t5,t4,80002dc4 - -0000000080002adc : - 80002adc: 800000b7 lui ra,0x80000 - 80002ae0: 0010df13 srli t5,ra,0x1 - 80002ae4: 00100e9b addiw t4,zero,1 - 80002ae8: 021e9e93 slli t4,t4,0x21 - 80002aec: fffe8e93 addi t4,t4,-1 # ffffffff7fffffff <_end+0xfffffffeffff880f> - 80002af0: 01ee9e93 slli t4,t4,0x1e - 80002af4: 00300193 li gp,3 - 80002af8: 2ddf1663 bne t5,t4,80002dc4 - -0000000080002afc : - 80002afc: 800000b7 lui ra,0x80000 - 80002b00: 0070df13 srli t5,ra,0x7 - 80002b04: 00100e9b addiw t4,zero,1 - 80002b08: 021e9e93 slli t4,t4,0x21 - 80002b0c: fffe8e93 addi t4,t4,-1 - 80002b10: 018e9e93 slli t4,t4,0x18 - 80002b14: 00400193 li gp,4 - 80002b18: 2bdf1663 bne t5,t4,80002dc4 - -0000000080002b1c : - 80002b1c: 800000b7 lui ra,0x80000 - 80002b20: 00e0df13 srli t5,ra,0xe - 80002b24: 00100e9b addiw t4,zero,1 - 80002b28: 021e9e93 slli t4,t4,0x21 - 80002b2c: fffe8e93 addi t4,t4,-1 - 80002b30: 011e9e93 slli t4,t4,0x11 - 80002b34: 00500193 li gp,5 - 80002b38: 29df1663 bne t5,t4,80002dc4 - -0000000080002b3c : - 80002b3c: 800000b7 lui ra,0x80000 - 80002b40: 0010809b addiw ra,ra,1 - 80002b44: 01f0df13 srli t5,ra,0x1f - 80002b48: 00100e9b addiw t4,zero,1 - 80002b4c: 021e9e93 slli t4,t4,0x21 - 80002b50: fffe8e93 addi t4,t4,-1 - 80002b54: 00600193 li gp,6 - 80002b58: 27df1663 bne t5,t4,80002dc4 - -0000000080002b5c : - 80002b5c: fff00093 li ra,-1 - 80002b60: 0000df13 srli t5,ra,0x0 - 80002b64: fff00e93 li t4,-1 - 80002b68: 00700193 li gp,7 - 80002b6c: 25df1c63 bne t5,t4,80002dc4 - -0000000080002b70 : - 80002b70: fff00093 li ra,-1 - 80002b74: 0010df13 srli t5,ra,0x1 - 80002b78: fff00e9b addiw t4,zero,-1 - 80002b7c: 03fe9e93 slli t4,t4,0x3f - 80002b80: fffe8e93 addi t4,t4,-1 - 80002b84: 00800193 li gp,8 - 80002b88: 23df1e63 bne t5,t4,80002dc4 - -0000000080002b8c : - 80002b8c: fff00093 li ra,-1 - 80002b90: 0070df13 srli t5,ra,0x7 - 80002b94: 00100e9b addiw t4,zero,1 - 80002b98: 039e9e93 slli t4,t4,0x39 - 80002b9c: fffe8e93 addi t4,t4,-1 - 80002ba0: 00900193 li gp,9 - 80002ba4: 23df1063 bne t5,t4,80002dc4 - -0000000080002ba8 : - 80002ba8: fff00093 li ra,-1 - 80002bac: 00e0df13 srli t5,ra,0xe - 80002bb0: 00100e9b addiw t4,zero,1 - 80002bb4: 032e9e93 slli t4,t4,0x32 - 80002bb8: fffe8e93 addi t4,t4,-1 - 80002bbc: 00a00193 li gp,10 - 80002bc0: 21df1263 bne t5,t4,80002dc4 - -0000000080002bc4 : - 80002bc4: fff00093 li ra,-1 - 80002bc8: 01f0df13 srli t5,ra,0x1f - 80002bcc: 00100e9b addiw t4,zero,1 - 80002bd0: 021e9e93 slli t4,t4,0x21 - 80002bd4: fffe8e93 addi t4,t4,-1 - 80002bd8: 00b00193 li gp,11 - 80002bdc: 1fdf1463 bne t5,t4,80002dc4 - -0000000080002be0 : - 80002be0: 212120b7 lui ra,0x21212 - 80002be4: 1210809b addiw ra,ra,289 - 80002be8: 0000df13 srli t5,ra,0x0 - 80002bec: 21212eb7 lui t4,0x21212 - 80002bf0: 121e8e9b addiw t4,t4,289 - 80002bf4: 00c00193 li gp,12 - 80002bf8: 1ddf1663 bne t5,t4,80002dc4 - -0000000080002bfc : - 80002bfc: 212120b7 lui ra,0x21212 - 80002c00: 1210809b addiw ra,ra,289 - 80002c04: 0010df13 srli t5,ra,0x1 - 80002c08: 10909eb7 lui t4,0x10909 - 80002c0c: 090e8e9b addiw t4,t4,144 - 80002c10: 00d00193 li gp,13 - 80002c14: 1bdf1863 bne t5,t4,80002dc4 - -0000000080002c18 : - 80002c18: 212120b7 lui ra,0x21212 - 80002c1c: 1210809b addiw ra,ra,289 - 80002c20: 0070df13 srli t5,ra,0x7 - 80002c24: 00424eb7 lui t4,0x424 - 80002c28: 242e8e9b addiw t4,t4,578 - 80002c2c: 00e00193 li gp,14 - 80002c30: 19df1a63 bne t5,t4,80002dc4 - -0000000080002c34 : - 80002c34: 212120b7 lui ra,0x21212 - 80002c38: 1210809b addiw ra,ra,289 - 80002c3c: 00e0df13 srli t5,ra,0xe - 80002c40: 00008eb7 lui t4,0x8 - 80002c44: 484e8e9b addiw t4,t4,1156 - 80002c48: 00f00193 li gp,15 - 80002c4c: 17df1c63 bne t5,t4,80002dc4 - -0000000080002c50 : - 80002c50: 212120b7 lui ra,0x21212 - 80002c54: 1210809b addiw ra,ra,289 - 80002c58: 01f0df13 srli t5,ra,0x1f - 80002c5c: 00000e93 li t4,0 - 80002c60: 01000193 li gp,16 - 80002c64: 17df1063 bne t5,t4,80002dc4 - -0000000080002c68 : - 80002c68: 0010009b addiw ra,zero,1 - 80002c6c: 01f09093 slli ra,ra,0x1f - 80002c70: 0070d093 srli ra,ra,0x7 - 80002c74: 01000eb7 lui t4,0x1000 - 80002c78: 01100193 li gp,17 - 80002c7c: 15d09463 bne ra,t4,80002dc4 - -0000000080002c80 : - 80002c80: 00000213 li tp,0 - 80002c84: 0010009b addiw ra,zero,1 - 80002c88: 01f09093 slli ra,ra,0x1f - 80002c8c: 0070df13 srli t5,ra,0x7 - 80002c90: 000f0313 mv t1,t5 - 80002c94: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c98: 00200293 li t0,2 - 80002c9c: fe5214e3 bne tp,t0,80002c84 - 80002ca0: 01000eb7 lui t4,0x1000 - 80002ca4: 01200193 li gp,18 - 80002ca8: 11d31e63 bne t1,t4,80002dc4 - -0000000080002cac : - 80002cac: 00000213 li tp,0 - 80002cb0: 0010009b addiw ra,zero,1 - 80002cb4: 01f09093 slli ra,ra,0x1f - 80002cb8: 00e0df13 srli t5,ra,0xe - 80002cbc: 00000013 nop - 80002cc0: 000f0313 mv t1,t5 - 80002cc4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cc8: 00200293 li t0,2 - 80002ccc: fe5212e3 bne tp,t0,80002cb0 - 80002cd0: 00020eb7 lui t4,0x20 - 80002cd4: 01300193 li gp,19 - 80002cd8: 0fd31663 bne t1,t4,80002dc4 - -0000000080002cdc : - 80002cdc: 00000213 li tp,0 - 80002ce0: 0010009b addiw ra,zero,1 - 80002ce4: 01f09093 slli ra,ra,0x1f - 80002ce8: 00108093 addi ra,ra,1 # 21212001 <_start-0x5ededfff> - 80002cec: 01f0df13 srli t5,ra,0x1f - 80002cf0: 00000013 nop - 80002cf4: 00000013 nop - 80002cf8: 000f0313 mv t1,t5 - 80002cfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d00: 00200293 li t0,2 - 80002d04: fc521ee3 bne tp,t0,80002ce0 - 80002d08: 00100e93 li t4,1 - 80002d0c: 01400193 li gp,20 - 80002d10: 0bd31a63 bne t1,t4,80002dc4 - -0000000080002d14 : - 80002d14: 00000213 li tp,0 - 80002d18: 0010009b addiw ra,zero,1 - 80002d1c: 01f09093 slli ra,ra,0x1f - 80002d20: 0070df13 srli t5,ra,0x7 - 80002d24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d28: 00200293 li t0,2 - 80002d2c: fe5216e3 bne tp,t0,80002d18 - 80002d30: 01000eb7 lui t4,0x1000 - 80002d34: 01500193 li gp,21 - 80002d38: 09df1663 bne t5,t4,80002dc4 - -0000000080002d3c : - 80002d3c: 00000213 li tp,0 - 80002d40: 0010009b addiw ra,zero,1 - 80002d44: 01f09093 slli ra,ra,0x1f - 80002d48: 00000013 nop - 80002d4c: 00e0df13 srli t5,ra,0xe - 80002d50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d54: 00200293 li t0,2 - 80002d58: fe5214e3 bne tp,t0,80002d40 - 80002d5c: 00020eb7 lui t4,0x20 - 80002d60: 01600193 li gp,22 - 80002d64: 07df1063 bne t5,t4,80002dc4 - -0000000080002d68 : - 80002d68: 00000213 li tp,0 - 80002d6c: 0010009b addiw ra,zero,1 - 80002d70: 01f09093 slli ra,ra,0x1f - 80002d74: 00108093 addi ra,ra,1 - 80002d78: 00000013 nop - 80002d7c: 00000013 nop - 80002d80: 01f0df13 srli t5,ra,0x1f - 80002d84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d88: 00200293 li t0,2 - 80002d8c: fe5210e3 bne tp,t0,80002d6c - 80002d90: 00100e93 li t4,1 - 80002d94: 01700193 li gp,23 - 80002d98: 03df1663 bne t5,t4,80002dc4 - -0000000080002d9c : - 80002d9c: 00405093 srli ra,zero,0x4 - 80002da0: 00000e93 li t4,0 - 80002da4: 01800193 li gp,24 - 80002da8: 01d09e63 bne ra,t4,80002dc4 - -0000000080002dac : - 80002dac: 02100093 li ra,33 - 80002db0: 00a0d013 srli zero,ra,0xa - 80002db4: 00000e93 li t4,0 - 80002db8: 01900193 li gp,25 - 80002dbc: 01d01463 bne zero,t4,80002dc4 - 80002dc0: 00301a63 bne zero,gp,80002dd4 - -0000000080002dc4 : - 80002dc4: 00119513 slli a0,gp,0x1 - 80002dc8: 00050063 beqz a0,80002dc8 - 80002dcc: 00156513 ori a0,a0,1 - 80002dd0: 00000073 ecall - -0000000080002dd4 : - 80002dd4: 00100513 li a0,1 - 80002dd8: 00000073 ecall - 80002ddc: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-srli.elf b/test/riscv/tests/rv64ui-v-srli.elf deleted file mode 100644 index 4a1f2d68..00000000 Binary files a/test/riscv/tests/rv64ui-v-srli.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-srliw.dump b/test/riscv/tests/rv64ui-v-srliw.dump deleted file mode 100644 index 919e1deb..00000000 --- a/test/riscv/tests/rv64ui-v-srliw.dump +++ /dev/null @@ -1,1054 +0,0 @@ - -rv64ui-v-srliw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 93068693 addi a3,a3,-1744 # 80002d88 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 96460613 addi a2,a2,-1692 # 80002e18 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 92c60613 addi a2,a2,-1748 # 80002e30 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 87c68693 addi a3,a3,-1924 # 80002dd0 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 89868693 addi a3,a3,-1896 # 80002f08 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 81860613 addi a2,a2,-2024 # 80002ee0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 74c68693 addi a3,a3,1868 # 80002f38 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 66c68693 addi a3,a3,1644 # 80002ea8 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 5fc68693 addi a3,a3,1532 # 80002e70 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 02200793 li a5,34 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 029637b7 lui a5,0x2963 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 15178793 addi a5,a5,337 # 2963151 <_start-0x7d69ceaf> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 800000b7 lui ra,0x80000 - 80002acc: 0000df1b srliw t5,ra,0x0 - 80002ad0: 80000eb7 lui t4,0x80000 - 80002ad4: 00200193 li gp,2 - 80002ad8: 29df1863 bne t5,t4,80002d68 - -0000000080002adc : - 80002adc: 800000b7 lui ra,0x80000 - 80002ae0: 0010df1b srliw t5,ra,0x1 - 80002ae4: 40000eb7 lui t4,0x40000 - 80002ae8: 00300193 li gp,3 - 80002aec: 27df1e63 bne t5,t4,80002d68 - -0000000080002af0 : - 80002af0: 800000b7 lui ra,0x80000 - 80002af4: 0070df1b srliw t5,ra,0x7 - 80002af8: 01000eb7 lui t4,0x1000 - 80002afc: 00400193 li gp,4 - 80002b00: 27df1463 bne t5,t4,80002d68 - -0000000080002b04 : - 80002b04: 800000b7 lui ra,0x80000 - 80002b08: 00e0df1b srliw t5,ra,0xe - 80002b0c: 00020eb7 lui t4,0x20 - 80002b10: 00500193 li gp,5 - 80002b14: 25df1a63 bne t5,t4,80002d68 - -0000000080002b18 : - 80002b18: 800000b7 lui ra,0x80000 - 80002b1c: 0010809b addiw ra,ra,1 - 80002b20: 01f0df1b srliw t5,ra,0x1f - 80002b24: 00100e93 li t4,1 - 80002b28: 00600193 li gp,6 - 80002b2c: 23df1e63 bne t5,t4,80002d68 - -0000000080002b30 : - 80002b30: fff00093 li ra,-1 - 80002b34: 0000df1b srliw t5,ra,0x0 - 80002b38: fff00e93 li t4,-1 - 80002b3c: 00700193 li gp,7 - 80002b40: 23df1463 bne t5,t4,80002d68 - -0000000080002b44 : - 80002b44: fff00093 li ra,-1 - 80002b48: 0010df1b srliw t5,ra,0x1 - 80002b4c: 80000eb7 lui t4,0x80000 - 80002b50: fffe8e9b addiw t4,t4,-1 - 80002b54: 00800193 li gp,8 - 80002b58: 21df1863 bne t5,t4,80002d68 - -0000000080002b5c : - 80002b5c: fff00093 li ra,-1 - 80002b60: 0070df1b srliw t5,ra,0x7 - 80002b64: 02000eb7 lui t4,0x2000 - 80002b68: fffe8e9b addiw t4,t4,-1 - 80002b6c: 00900193 li gp,9 - 80002b70: 1fdf1c63 bne t5,t4,80002d68 - -0000000080002b74 : - 80002b74: fff00093 li ra,-1 - 80002b78: 00e0df1b srliw t5,ra,0xe - 80002b7c: 00040eb7 lui t4,0x40 - 80002b80: fffe8e9b addiw t4,t4,-1 - 80002b84: 00a00193 li gp,10 - 80002b88: 1fdf1063 bne t5,t4,80002d68 - -0000000080002b8c : - 80002b8c: fff00093 li ra,-1 - 80002b90: 01f0df1b srliw t5,ra,0x1f - 80002b94: 00100e93 li t4,1 - 80002b98: 00b00193 li gp,11 - 80002b9c: 1ddf1663 bne t5,t4,80002d68 - -0000000080002ba0 : - 80002ba0: 212120b7 lui ra,0x21212 - 80002ba4: 1210809b addiw ra,ra,289 - 80002ba8: 0000df1b srliw t5,ra,0x0 - 80002bac: 21212eb7 lui t4,0x21212 - 80002bb0: 121e8e9b addiw t4,t4,289 - 80002bb4: 00c00193 li gp,12 - 80002bb8: 1bdf1863 bne t5,t4,80002d68 - -0000000080002bbc : - 80002bbc: 212120b7 lui ra,0x21212 - 80002bc0: 1210809b addiw ra,ra,289 - 80002bc4: 0010df1b srliw t5,ra,0x1 - 80002bc8: 10909eb7 lui t4,0x10909 - 80002bcc: 090e8e9b addiw t4,t4,144 - 80002bd0: 00d00193 li gp,13 - 80002bd4: 19df1a63 bne t5,t4,80002d68 - -0000000080002bd8 : - 80002bd8: 212120b7 lui ra,0x21212 - 80002bdc: 1210809b addiw ra,ra,289 - 80002be0: 0070df1b srliw t5,ra,0x7 - 80002be4: 00424eb7 lui t4,0x424 - 80002be8: 242e8e9b addiw t4,t4,578 - 80002bec: 00e00193 li gp,14 - 80002bf0: 17df1c63 bne t5,t4,80002d68 - -0000000080002bf4 : - 80002bf4: 212120b7 lui ra,0x21212 - 80002bf8: 1210809b addiw ra,ra,289 - 80002bfc: 00e0df1b srliw t5,ra,0xe - 80002c00: 00008eb7 lui t4,0x8 - 80002c04: 484e8e9b addiw t4,t4,1156 - 80002c08: 00f00193 li gp,15 - 80002c0c: 15df1e63 bne t5,t4,80002d68 - -0000000080002c10 : - 80002c10: 212120b7 lui ra,0x21212 - 80002c14: 1210809b addiw ra,ra,289 - 80002c18: 01f0df1b srliw t5,ra,0x1f - 80002c1c: 00000e93 li t4,0 - 80002c20: 01000193 li gp,16 - 80002c24: 15df1263 bne t5,t4,80002d68 - -0000000080002c28 : - 80002c28: 800000b7 lui ra,0x80000 - 80002c2c: 0070d09b srliw ra,ra,0x7 - 80002c30: 01000eb7 lui t4,0x1000 - 80002c34: 01100193 li gp,17 - 80002c38: 13d09863 bne ra,t4,80002d68 - -0000000080002c3c : - 80002c3c: 00000213 li tp,0 - 80002c40: 800000b7 lui ra,0x80000 - 80002c44: 0070df1b srliw t5,ra,0x7 - 80002c48: 000f0313 mv t1,t5 - 80002c4c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c50: 00200293 li t0,2 - 80002c54: fe5216e3 bne tp,t0,80002c40 - 80002c58: 01000eb7 lui t4,0x1000 - 80002c5c: 01200193 li gp,18 - 80002c60: 11d31463 bne t1,t4,80002d68 - -0000000080002c64 : - 80002c64: 00000213 li tp,0 - 80002c68: 800000b7 lui ra,0x80000 - 80002c6c: 00e0df1b srliw t5,ra,0xe - 80002c70: 00000013 nop - 80002c74: 000f0313 mv t1,t5 - 80002c78: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c7c: 00200293 li t0,2 - 80002c80: fe5214e3 bne tp,t0,80002c68 - 80002c84: 00020eb7 lui t4,0x20 - 80002c88: 01300193 li gp,19 - 80002c8c: 0dd31e63 bne t1,t4,80002d68 - -0000000080002c90 : - 80002c90: 00000213 li tp,0 - 80002c94: 800000b7 lui ra,0x80000 - 80002c98: 0010809b addiw ra,ra,1 - 80002c9c: 01f0df1b srliw t5,ra,0x1f - 80002ca0: 00000013 nop - 80002ca4: 00000013 nop - 80002ca8: 000f0313 mv t1,t5 - 80002cac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cb0: 00200293 li t0,2 - 80002cb4: fe5210e3 bne tp,t0,80002c94 - 80002cb8: 00100e93 li t4,1 - 80002cbc: 01400193 li gp,20 - 80002cc0: 0bd31463 bne t1,t4,80002d68 - -0000000080002cc4 : - 80002cc4: 00000213 li tp,0 - 80002cc8: 800000b7 lui ra,0x80000 - 80002ccc: 0070df1b srliw t5,ra,0x7 - 80002cd0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cd4: 00200293 li t0,2 - 80002cd8: fe5218e3 bne tp,t0,80002cc8 - 80002cdc: 01000eb7 lui t4,0x1000 - 80002ce0: 01500193 li gp,21 - 80002ce4: 09df1263 bne t5,t4,80002d68 - -0000000080002ce8 : - 80002ce8: 00000213 li tp,0 - 80002cec: 800000b7 lui ra,0x80000 - 80002cf0: 00000013 nop - 80002cf4: 00e0df1b srliw t5,ra,0xe - 80002cf8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cfc: 00200293 li t0,2 - 80002d00: fe5216e3 bne tp,t0,80002cec - 80002d04: 00020eb7 lui t4,0x20 - 80002d08: 01600193 li gp,22 - 80002d0c: 05df1e63 bne t5,t4,80002d68 - -0000000080002d10 : - 80002d10: 00000213 li tp,0 - 80002d14: 800000b7 lui ra,0x80000 - 80002d18: 0010809b addiw ra,ra,1 - 80002d1c: 00000013 nop - 80002d20: 00000013 nop - 80002d24: 01f0df1b srliw t5,ra,0x1f - 80002d28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d2c: 00200293 li t0,2 - 80002d30: fe5212e3 bne tp,t0,80002d14 - 80002d34: 00100e93 li t4,1 - 80002d38: 01700193 li gp,23 - 80002d3c: 03df1663 bne t5,t4,80002d68 - -0000000080002d40 : - 80002d40: 01f0509b srliw ra,zero,0x1f - 80002d44: 00000e93 li t4,0 - 80002d48: 01800193 li gp,24 - 80002d4c: 01d09e63 bne ra,t4,80002d68 - -0000000080002d50 : - 80002d50: 01f00093 li ra,31 - 80002d54: 01c0d01b srliw zero,ra,0x1c - 80002d58: 00000e93 li t4,0 - 80002d5c: 01900193 li gp,25 - 80002d60: 01d01463 bne zero,t4,80002d68 - 80002d64: 00301a63 bne zero,gp,80002d78 - -0000000080002d68 : - 80002d68: 00119513 slli a0,gp,0x1 - 80002d6c: 00050063 beqz a0,80002d6c - 80002d70: 00156513 ori a0,a0,1 - 80002d74: 00000073 ecall - -0000000080002d78 : - 80002d78: 00100513 li a0,1 - 80002d7c: 00000073 ecall - 80002d80: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-srliw.elf b/test/riscv/tests/rv64ui-v-srliw.elf deleted file mode 100644 index eacd8701..00000000 Binary files a/test/riscv/tests/rv64ui-v-srliw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-srlw.dump b/test/riscv/tests/rv64ui-v-srlw.dump deleted file mode 100644 index 2cbf7502..00000000 --- a/test/riscv/tests/rv64ui-v-srlw.dump +++ /dev/null @@ -1,1275 +0,0 @@ - -rv64ui-v-srlw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: c1068693 addi a3,a3,-1008 # 80003068 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: c4460613 addi a2,a2,-956 # 800030f8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: c0c60613 addi a2,a2,-1012 # 80003110 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: b5c68693 addi a3,a3,-1188 # 800030b0 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: b7868693 addi a3,a3,-1160 # 800031e8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: af860613 addi a2,a2,-1288 # 800031c0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: a2c68693 addi a3,a3,-1492 # 80003218 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 94c68693 addi a3,a3,-1716 # 80003188 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00001697 auipc a3,0x1 - 80002878: 8dc68693 addi a3,a3,-1828 # 80003150 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 00800793 li a5,8 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 069877b7 lui a5,0x6987 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: d1f78793 addi a5,a5,-737 # 6986d1f <_start-0x796792e1> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 800000b7 lui ra,0x80000 - 80002acc: 00000113 li sp,0 - 80002ad0: 0020df3b srlw t5,ra,sp - 80002ad4: 80000eb7 lui t4,0x80000 - 80002ad8: 00200193 li gp,2 - 80002adc: 57df1863 bne t5,t4,8000304c - -0000000080002ae0 : - 80002ae0: 800000b7 lui ra,0x80000 - 80002ae4: 00100113 li sp,1 - 80002ae8: 0020df3b srlw t5,ra,sp - 80002aec: 40000eb7 lui t4,0x40000 - 80002af0: 00300193 li gp,3 - 80002af4: 55df1c63 bne t5,t4,8000304c - -0000000080002af8 : - 80002af8: 800000b7 lui ra,0x80000 - 80002afc: 00700113 li sp,7 - 80002b00: 0020df3b srlw t5,ra,sp - 80002b04: 01000eb7 lui t4,0x1000 - 80002b08: 00400193 li gp,4 - 80002b0c: 55df1063 bne t5,t4,8000304c - -0000000080002b10 : - 80002b10: 800000b7 lui ra,0x80000 - 80002b14: 00e00113 li sp,14 - 80002b18: 0020df3b srlw t5,ra,sp - 80002b1c: 00020eb7 lui t4,0x20 - 80002b20: 00500193 li gp,5 - 80002b24: 53df1463 bne t5,t4,8000304c - -0000000080002b28 : - 80002b28: 800000b7 lui ra,0x80000 - 80002b2c: 0010809b addiw ra,ra,1 - 80002b30: 01f00113 li sp,31 - 80002b34: 0020df3b srlw t5,ra,sp - 80002b38: 00100e93 li t4,1 - 80002b3c: 00600193 li gp,6 - 80002b40: 51df1663 bne t5,t4,8000304c - -0000000080002b44 : - 80002b44: fff00093 li ra,-1 - 80002b48: 00000113 li sp,0 - 80002b4c: 0020df3b srlw t5,ra,sp - 80002b50: fff00e93 li t4,-1 - 80002b54: 00700193 li gp,7 - 80002b58: 4fdf1a63 bne t5,t4,8000304c - -0000000080002b5c : - 80002b5c: fff00093 li ra,-1 - 80002b60: 00100113 li sp,1 - 80002b64: 0020df3b srlw t5,ra,sp - 80002b68: 80000eb7 lui t4,0x80000 - 80002b6c: fffe8e9b addiw t4,t4,-1 - 80002b70: 00800193 li gp,8 - 80002b74: 4ddf1c63 bne t5,t4,8000304c - -0000000080002b78 : - 80002b78: fff00093 li ra,-1 - 80002b7c: 00700113 li sp,7 - 80002b80: 0020df3b srlw t5,ra,sp - 80002b84: 02000eb7 lui t4,0x2000 - 80002b88: fffe8e9b addiw t4,t4,-1 - 80002b8c: 00900193 li gp,9 - 80002b90: 4bdf1e63 bne t5,t4,8000304c - -0000000080002b94 : - 80002b94: fff00093 li ra,-1 - 80002b98: 00e00113 li sp,14 - 80002b9c: 0020df3b srlw t5,ra,sp - 80002ba0: 00040eb7 lui t4,0x40 - 80002ba4: fffe8e9b addiw t4,t4,-1 - 80002ba8: 00a00193 li gp,10 - 80002bac: 4bdf1063 bne t5,t4,8000304c - -0000000080002bb0 : - 80002bb0: fff00093 li ra,-1 - 80002bb4: 01f00113 li sp,31 - 80002bb8: 0020df3b srlw t5,ra,sp - 80002bbc: 00100e93 li t4,1 - 80002bc0: 00b00193 li gp,11 - 80002bc4: 49df1463 bne t5,t4,8000304c - -0000000080002bc8 : - 80002bc8: 212120b7 lui ra,0x21212 - 80002bcc: 1210809b addiw ra,ra,289 - 80002bd0: 00000113 li sp,0 - 80002bd4: 0020df3b srlw t5,ra,sp - 80002bd8: 21212eb7 lui t4,0x21212 - 80002bdc: 121e8e9b addiw t4,t4,289 - 80002be0: 00c00193 li gp,12 - 80002be4: 47df1463 bne t5,t4,8000304c - -0000000080002be8 : - 80002be8: 212120b7 lui ra,0x21212 - 80002bec: 1210809b addiw ra,ra,289 - 80002bf0: 00100113 li sp,1 - 80002bf4: 0020df3b srlw t5,ra,sp - 80002bf8: 10909eb7 lui t4,0x10909 - 80002bfc: 090e8e9b addiw t4,t4,144 - 80002c00: 00d00193 li gp,13 - 80002c04: 45df1463 bne t5,t4,8000304c - -0000000080002c08 : - 80002c08: 212120b7 lui ra,0x21212 - 80002c0c: 1210809b addiw ra,ra,289 - 80002c10: 00700113 li sp,7 - 80002c14: 0020df3b srlw t5,ra,sp - 80002c18: 00424eb7 lui t4,0x424 - 80002c1c: 242e8e9b addiw t4,t4,578 - 80002c20: 00e00193 li gp,14 - 80002c24: 43df1463 bne t5,t4,8000304c - -0000000080002c28 : - 80002c28: 212120b7 lui ra,0x21212 - 80002c2c: 1210809b addiw ra,ra,289 - 80002c30: 00e00113 li sp,14 - 80002c34: 0020df3b srlw t5,ra,sp - 80002c38: 00008eb7 lui t4,0x8 - 80002c3c: 484e8e9b addiw t4,t4,1156 - 80002c40: 00f00193 li gp,15 - 80002c44: 41df1463 bne t5,t4,8000304c - -0000000080002c48 : - 80002c48: 212120b7 lui ra,0x21212 - 80002c4c: 1210809b addiw ra,ra,289 - 80002c50: 01f00113 li sp,31 - 80002c54: 0020df3b srlw t5,ra,sp - 80002c58: 00000e93 li t4,0 - 80002c5c: 01000193 li gp,16 - 80002c60: 3fdf1663 bne t5,t4,8000304c - -0000000080002c64 : - 80002c64: 212120b7 lui ra,0x21212 - 80002c68: 1210809b addiw ra,ra,289 - 80002c6c: fe000113 li sp,-32 - 80002c70: 0020df3b srlw t5,ra,sp - 80002c74: 21212eb7 lui t4,0x21212 - 80002c78: 121e8e9b addiw t4,t4,289 - 80002c7c: 01100193 li gp,17 - 80002c80: 3ddf1663 bne t5,t4,8000304c - -0000000080002c84 : - 80002c84: 212120b7 lui ra,0x21212 - 80002c88: 1210809b addiw ra,ra,289 - 80002c8c: fe100113 li sp,-31 - 80002c90: 0020df3b srlw t5,ra,sp - 80002c94: 10909eb7 lui t4,0x10909 - 80002c98: 090e8e9b addiw t4,t4,144 - 80002c9c: 01200193 li gp,18 - 80002ca0: 3bdf1663 bne t5,t4,8000304c - -0000000080002ca4 : - 80002ca4: 212120b7 lui ra,0x21212 - 80002ca8: 1210809b addiw ra,ra,289 - 80002cac: fe700113 li sp,-25 - 80002cb0: 0020df3b srlw t5,ra,sp - 80002cb4: 00424eb7 lui t4,0x424 - 80002cb8: 242e8e9b addiw t4,t4,578 - 80002cbc: 01300193 li gp,19 - 80002cc0: 39df1663 bne t5,t4,8000304c - -0000000080002cc4 : - 80002cc4: 212120b7 lui ra,0x21212 - 80002cc8: 1210809b addiw ra,ra,289 - 80002ccc: fee00113 li sp,-18 - 80002cd0: 0020df3b srlw t5,ra,sp - 80002cd4: 00008eb7 lui t4,0x8 - 80002cd8: 484e8e9b addiw t4,t4,1156 - 80002cdc: 01400193 li gp,20 - 80002ce0: 37df1663 bne t5,t4,8000304c - -0000000080002ce4 : - 80002ce4: 212120b7 lui ra,0x21212 - 80002ce8: 1210809b addiw ra,ra,289 - 80002cec: fff00113 li sp,-1 - 80002cf0: 0020df3b srlw t5,ra,sp - 80002cf4: 00000e93 li t4,0 - 80002cf8: 01500193 li gp,21 - 80002cfc: 35df1863 bne t5,t4,8000304c - -0000000080002d00 : - 80002d00: 800000b7 lui ra,0x80000 - 80002d04: 00700113 li sp,7 - 80002d08: 0020d0bb srlw ra,ra,sp - 80002d0c: 01000eb7 lui t4,0x1000 - 80002d10: 01600193 li gp,22 - 80002d14: 33d09c63 bne ra,t4,8000304c - -0000000080002d18 : - 80002d18: 800000b7 lui ra,0x80000 - 80002d1c: 00e00113 li sp,14 - 80002d20: 0020d13b srlw sp,ra,sp - 80002d24: 00020eb7 lui t4,0x20 - 80002d28: 01700193 li gp,23 - 80002d2c: 33d11063 bne sp,t4,8000304c - -0000000080002d30 : - 80002d30: 00700093 li ra,7 - 80002d34: 0010d0bb srlw ra,ra,ra - 80002d38: 00000e93 li t4,0 - 80002d3c: 01800193 li gp,24 - 80002d40: 31d09663 bne ra,t4,8000304c - -0000000080002d44 : - 80002d44: 00000213 li tp,0 - 80002d48: 800000b7 lui ra,0x80000 - 80002d4c: 00700113 li sp,7 - 80002d50: 0020df3b srlw t5,ra,sp - 80002d54: 000f0313 mv t1,t5 - 80002d58: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d5c: 00200293 li t0,2 - 80002d60: fe5214e3 bne tp,t0,80002d48 - 80002d64: 01000eb7 lui t4,0x1000 - 80002d68: 01900193 li gp,25 - 80002d6c: 2fd31063 bne t1,t4,8000304c - -0000000080002d70 : - 80002d70: 00000213 li tp,0 - 80002d74: 800000b7 lui ra,0x80000 - 80002d78: 00e00113 li sp,14 - 80002d7c: 0020df3b srlw t5,ra,sp - 80002d80: 00000013 nop - 80002d84: 000f0313 mv t1,t5 - 80002d88: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d8c: 00200293 li t0,2 - 80002d90: fe5212e3 bne tp,t0,80002d74 - 80002d94: 00020eb7 lui t4,0x20 - 80002d98: 01a00193 li gp,26 - 80002d9c: 2bd31863 bne t1,t4,8000304c - -0000000080002da0 : - 80002da0: 00000213 li tp,0 - 80002da4: 800000b7 lui ra,0x80000 - 80002da8: 01f00113 li sp,31 - 80002dac: 0020df3b srlw t5,ra,sp - 80002db0: 00000013 nop - 80002db4: 00000013 nop - 80002db8: 000f0313 mv t1,t5 - 80002dbc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dc0: 00200293 li t0,2 - 80002dc4: fe5210e3 bne tp,t0,80002da4 - 80002dc8: 00100e93 li t4,1 - 80002dcc: 01b00193 li gp,27 - 80002dd0: 27d31e63 bne t1,t4,8000304c - -0000000080002dd4 : - 80002dd4: 00000213 li tp,0 - 80002dd8: 800000b7 lui ra,0x80000 - 80002ddc: 00700113 li sp,7 - 80002de0: 0020df3b srlw t5,ra,sp - 80002de4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002de8: 00200293 li t0,2 - 80002dec: fe5216e3 bne tp,t0,80002dd8 - 80002df0: 01000eb7 lui t4,0x1000 - 80002df4: 01c00193 li gp,28 - 80002df8: 25df1a63 bne t5,t4,8000304c - -0000000080002dfc : - 80002dfc: 00000213 li tp,0 - 80002e00: 800000b7 lui ra,0x80000 - 80002e04: 00e00113 li sp,14 - 80002e08: 00000013 nop - 80002e0c: 0020df3b srlw t5,ra,sp - 80002e10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e14: 00200293 li t0,2 - 80002e18: fe5214e3 bne tp,t0,80002e00 - 80002e1c: 00020eb7 lui t4,0x20 - 80002e20: 01d00193 li gp,29 - 80002e24: 23df1463 bne t5,t4,8000304c - -0000000080002e28 : - 80002e28: 00000213 li tp,0 - 80002e2c: 800000b7 lui ra,0x80000 - 80002e30: 01f00113 li sp,31 - 80002e34: 00000013 nop - 80002e38: 00000013 nop - 80002e3c: 0020df3b srlw t5,ra,sp - 80002e40: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e44: 00200293 li t0,2 - 80002e48: fe5212e3 bne tp,t0,80002e2c - 80002e4c: 00100e93 li t4,1 - 80002e50: 01e00193 li gp,30 - 80002e54: 1fdf1c63 bne t5,t4,8000304c - -0000000080002e58 : - 80002e58: 00000213 li tp,0 - 80002e5c: 800000b7 lui ra,0x80000 - 80002e60: 00000013 nop - 80002e64: 00700113 li sp,7 - 80002e68: 0020df3b srlw t5,ra,sp - 80002e6c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e70: 00200293 li t0,2 - 80002e74: fe5214e3 bne tp,t0,80002e5c - 80002e78: 01000eb7 lui t4,0x1000 - 80002e7c: 01f00193 li gp,31 - 80002e80: 1ddf1663 bne t5,t4,8000304c - -0000000080002e84 : - 80002e84: 00000213 li tp,0 - 80002e88: 800000b7 lui ra,0x80000 - 80002e8c: 00000013 nop - 80002e90: 00e00113 li sp,14 - 80002e94: 00000013 nop - 80002e98: 0020df3b srlw t5,ra,sp - 80002e9c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ea0: 00200293 li t0,2 - 80002ea4: fe5212e3 bne tp,t0,80002e88 - 80002ea8: 00020eb7 lui t4,0x20 - 80002eac: 02000193 li gp,32 - 80002eb0: 19df1e63 bne t5,t4,8000304c - -0000000080002eb4 : - 80002eb4: 00000213 li tp,0 - 80002eb8: 800000b7 lui ra,0x80000 - 80002ebc: 00000013 nop - 80002ec0: 00000013 nop - 80002ec4: 01f00113 li sp,31 - 80002ec8: 0020df3b srlw t5,ra,sp - 80002ecc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ed0: 00200293 li t0,2 - 80002ed4: fe5212e3 bne tp,t0,80002eb8 - 80002ed8: 00100e93 li t4,1 - 80002edc: 02100193 li gp,33 - 80002ee0: 17df1663 bne t5,t4,8000304c - -0000000080002ee4 : - 80002ee4: 00000213 li tp,0 - 80002ee8: 00700113 li sp,7 - 80002eec: 800000b7 lui ra,0x80000 - 80002ef0: 0020df3b srlw t5,ra,sp - 80002ef4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ef8: 00200293 li t0,2 - 80002efc: fe5216e3 bne tp,t0,80002ee8 - 80002f00: 01000eb7 lui t4,0x1000 - 80002f04: 02200193 li gp,34 - 80002f08: 15df1263 bne t5,t4,8000304c - -0000000080002f0c : - 80002f0c: 00000213 li tp,0 - 80002f10: 00e00113 li sp,14 - 80002f14: 800000b7 lui ra,0x80000 - 80002f18: 00000013 nop - 80002f1c: 0020df3b srlw t5,ra,sp - 80002f20: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f24: 00200293 li t0,2 - 80002f28: fe5214e3 bne tp,t0,80002f10 - 80002f2c: 00020eb7 lui t4,0x20 - 80002f30: 02300193 li gp,35 - 80002f34: 11df1c63 bne t5,t4,8000304c - -0000000080002f38 : - 80002f38: 00000213 li tp,0 - 80002f3c: 01f00113 li sp,31 - 80002f40: 800000b7 lui ra,0x80000 - 80002f44: 00000013 nop - 80002f48: 00000013 nop - 80002f4c: 0020df3b srlw t5,ra,sp - 80002f50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f54: 00200293 li t0,2 - 80002f58: fe5212e3 bne tp,t0,80002f3c - 80002f5c: 00100e93 li t4,1 - 80002f60: 02400193 li gp,36 - 80002f64: 0fdf1463 bne t5,t4,8000304c - -0000000080002f68 : - 80002f68: 00000213 li tp,0 - 80002f6c: 00700113 li sp,7 - 80002f70: 00000013 nop - 80002f74: 800000b7 lui ra,0x80000 - 80002f78: 0020df3b srlw t5,ra,sp - 80002f7c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f80: 00200293 li t0,2 - 80002f84: fe5214e3 bne tp,t0,80002f6c - 80002f88: 01000eb7 lui t4,0x1000 - 80002f8c: 02500193 li gp,37 - 80002f90: 0bdf1e63 bne t5,t4,8000304c - -0000000080002f94 : - 80002f94: 00000213 li tp,0 - 80002f98: 00e00113 li sp,14 - 80002f9c: 00000013 nop - 80002fa0: 800000b7 lui ra,0x80000 - 80002fa4: 00000013 nop - 80002fa8: 0020df3b srlw t5,ra,sp - 80002fac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002fb0: 00200293 li t0,2 - 80002fb4: fe5212e3 bne tp,t0,80002f98 - 80002fb8: 00020eb7 lui t4,0x20 - 80002fbc: 02600193 li gp,38 - 80002fc0: 09df1663 bne t5,t4,8000304c - -0000000080002fc4 : - 80002fc4: 00000213 li tp,0 - 80002fc8: 01f00113 li sp,31 - 80002fcc: 00000013 nop - 80002fd0: 00000013 nop - 80002fd4: 800000b7 lui ra,0x80000 - 80002fd8: 0020df3b srlw t5,ra,sp - 80002fdc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002fe0: 00200293 li t0,2 - 80002fe4: fe5212e3 bne tp,t0,80002fc8 - 80002fe8: 00100e93 li t4,1 - 80002fec: 02700193 li gp,39 - 80002ff0: 05df1e63 bne t5,t4,8000304c - -0000000080002ff4 : - 80002ff4: 00f00093 li ra,15 - 80002ff8: 0010513b srlw sp,zero,ra - 80002ffc: 00000e93 li t4,0 - 80003000: 02800193 li gp,40 - 80003004: 05d11463 bne sp,t4,8000304c - -0000000080003008 : - 80003008: 02000093 li ra,32 - 8000300c: 0000d13b srlw sp,ra,zero - 80003010: 02000e93 li t4,32 - 80003014: 02900193 li gp,41 - 80003018: 03d11a63 bne sp,t4,8000304c - -000000008000301c : - 8000301c: 000050bb srlw ra,zero,zero - 80003020: 00000e93 li t4,0 - 80003024: 02a00193 li gp,42 - 80003028: 03d09263 bne ra,t4,8000304c - -000000008000302c : - 8000302c: 40000093 li ra,1024 - 80003030: 00001137 lui sp,0x1 - 80003034: 8001011b addiw sp,sp,-2048 - 80003038: 0020d03b srlw zero,ra,sp - 8000303c: 00000e93 li t4,0 - 80003040: 02b00193 li gp,43 - 80003044: 01d01463 bne zero,t4,8000304c - 80003048: 00301a63 bne zero,gp,8000305c - -000000008000304c : - 8000304c: 00119513 slli a0,gp,0x1 - 80003050: 00050063 beqz a0,80003050 - 80003054: 00156513 ori a0,a0,1 - 80003058: 00000073 ecall - -000000008000305c : - 8000305c: 00100513 li a0,1 - 80003060: 00000073 ecall - 80003064: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-srlw.elf b/test/riscv/tests/rv64ui-v-srlw.elf deleted file mode 100644 index 87f8e6d4..00000000 Binary files a/test/riscv/tests/rv64ui-v-srlw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-sub.dump b/test/riscv/tests/rv64ui-v-sub.dump deleted file mode 100644 index 1e59e971..00000000 --- a/test/riscv/tests/rv64ui-v-sub.dump +++ /dev/null @@ -1,1218 +0,0 @@ - -rv64ui-v-sub: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: b6068693 addi a3,a3,-1184 # 80002fb8 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: b9460613 addi a2,a2,-1132 # 80003048 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: b5c60613 addi a2,a2,-1188 # 80003060 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: aac68693 addi a3,a3,-1364 # 80003000 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: ac868693 addi a3,a3,-1336 # 80003138 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: a4860613 addi a2,a2,-1464 # 80003110 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: 97c68693 addi a3,a3,-1668 # 80003168 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 89c68693 addi a3,a3,-1892 # 800030d8 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00001697 auipc a3,0x1 - 80002878: 82c68693 addi a3,a3,-2004 # 800030a0 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 02500793 li a5,37 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0913b7b7 lui a5,0x913b - 80002a70: 000805b7 lui a1,0x80 - 80002a74: a7278793 addi a5,a5,-1422 # 913aa72 <_start-0x76ec558e> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000093 li ra,0 - 80002acc: 00000113 li sp,0 - 80002ad0: 40208f33 sub t5,ra,sp - 80002ad4: 00000e93 li t4,0 - 80002ad8: 00200193 li gp,2 - 80002adc: 4bdf1e63 bne t5,t4,80002f98 - -0000000080002ae0 : - 80002ae0: 00100093 li ra,1 - 80002ae4: 00100113 li sp,1 - 80002ae8: 40208f33 sub t5,ra,sp - 80002aec: 00000e93 li t4,0 - 80002af0: 00300193 li gp,3 - 80002af4: 4bdf1263 bne t5,t4,80002f98 - -0000000080002af8 : - 80002af8: 00300093 li ra,3 - 80002afc: 00700113 li sp,7 - 80002b00: 40208f33 sub t5,ra,sp - 80002b04: ffc00e93 li t4,-4 - 80002b08: 00400193 li gp,4 - 80002b0c: 49df1663 bne t5,t4,80002f98 - -0000000080002b10 : - 80002b10: 00000093 li ra,0 - 80002b14: ffff8137 lui sp,0xffff8 - 80002b18: 40208f33 sub t5,ra,sp - 80002b1c: 00008eb7 lui t4,0x8 - 80002b20: 00500193 li gp,5 - 80002b24: 47df1a63 bne t5,t4,80002f98 - -0000000080002b28 : - 80002b28: 800000b7 lui ra,0x80000 - 80002b2c: 00000113 li sp,0 - 80002b30: 40208f33 sub t5,ra,sp - 80002b34: 80000eb7 lui t4,0x80000 - 80002b38: 00600193 li gp,6 - 80002b3c: 45df1e63 bne t5,t4,80002f98 - -0000000080002b40 : - 80002b40: 800000b7 lui ra,0x80000 - 80002b44: ffff8137 lui sp,0xffff8 - 80002b48: 40208f33 sub t5,ra,sp - 80002b4c: 80008eb7 lui t4,0x80008 - 80002b50: 00700193 li gp,7 - 80002b54: 45df1263 bne t5,t4,80002f98 - -0000000080002b58 : - 80002b58: 00000093 li ra,0 - 80002b5c: 00008137 lui sp,0x8 - 80002b60: fff1011b addiw sp,sp,-1 - 80002b64: 40208f33 sub t5,ra,sp - 80002b68: ffff8eb7 lui t4,0xffff8 - 80002b6c: 001e8e9b addiw t4,t4,1 - 80002b70: 00800193 li gp,8 - 80002b74: 43df1263 bne t5,t4,80002f98 - -0000000080002b78 : - 80002b78: 800000b7 lui ra,0x80000 - 80002b7c: fff0809b addiw ra,ra,-1 - 80002b80: 00000113 li sp,0 - 80002b84: 40208f33 sub t5,ra,sp - 80002b88: 80000eb7 lui t4,0x80000 - 80002b8c: fffe8e9b addiw t4,t4,-1 - 80002b90: 00900193 li gp,9 - 80002b94: 41df1263 bne t5,t4,80002f98 - -0000000080002b98 : - 80002b98: 800000b7 lui ra,0x80000 - 80002b9c: fff0809b addiw ra,ra,-1 - 80002ba0: 00008137 lui sp,0x8 - 80002ba4: fff1011b addiw sp,sp,-1 - 80002ba8: 40208f33 sub t5,ra,sp - 80002bac: 7fff8eb7 lui t4,0x7fff8 - 80002bb0: 00a00193 li gp,10 - 80002bb4: 3fdf1263 bne t5,t4,80002f98 - -0000000080002bb8 : - 80002bb8: 800000b7 lui ra,0x80000 - 80002bbc: 00008137 lui sp,0x8 - 80002bc0: fff1011b addiw sp,sp,-1 - 80002bc4: 40208f33 sub t5,ra,sp - 80002bc8: ffff0eb7 lui t4,0xffff0 - 80002bcc: fffe8e9b addiw t4,t4,-1 - 80002bd0: 00fe9e93 slli t4,t4,0xf - 80002bd4: 001e8e93 addi t4,t4,1 # ffffffffffff0001 <_end+0xffffffff7ffe7811> - 80002bd8: 00b00193 li gp,11 - 80002bdc: 3bdf1e63 bne t5,t4,80002f98 - -0000000080002be0 : - 80002be0: 800000b7 lui ra,0x80000 - 80002be4: fff0809b addiw ra,ra,-1 - 80002be8: ffff8137 lui sp,0xffff8 - 80002bec: 40208f33 sub t5,ra,sp - 80002bf0: 00010eb7 lui t4,0x10 - 80002bf4: 001e8e9b addiw t4,t4,1 - 80002bf8: 00fe9e93 slli t4,t4,0xf - 80002bfc: fffe8e93 addi t4,t4,-1 # ffff <_start-0x7fff0001> - 80002c00: 00c00193 li gp,12 - 80002c04: 39df1a63 bne t5,t4,80002f98 - -0000000080002c08 : - 80002c08: 00000093 li ra,0 - 80002c0c: fff00113 li sp,-1 - 80002c10: 40208f33 sub t5,ra,sp - 80002c14: 00100e93 li t4,1 - 80002c18: 00d00193 li gp,13 - 80002c1c: 37df1e63 bne t5,t4,80002f98 - -0000000080002c20 : - 80002c20: fff00093 li ra,-1 - 80002c24: 00100113 li sp,1 - 80002c28: 40208f33 sub t5,ra,sp - 80002c2c: ffe00e93 li t4,-2 - 80002c30: 00e00193 li gp,14 - 80002c34: 37df1263 bne t5,t4,80002f98 - -0000000080002c38 : - 80002c38: fff00093 li ra,-1 - 80002c3c: fff00113 li sp,-1 - 80002c40: 40208f33 sub t5,ra,sp - 80002c44: 00000e93 li t4,0 - 80002c48: 00f00193 li gp,15 - 80002c4c: 35df1663 bne t5,t4,80002f98 - -0000000080002c50 : - 80002c50: 00d00093 li ra,13 - 80002c54: 00b00113 li sp,11 - 80002c58: 402080b3 sub ra,ra,sp - 80002c5c: 00200e93 li t4,2 - 80002c60: 01000193 li gp,16 - 80002c64: 33d09a63 bne ra,t4,80002f98 - -0000000080002c68 : - 80002c68: 00e00093 li ra,14 - 80002c6c: 00b00113 li sp,11 - 80002c70: 40208133 sub sp,ra,sp - 80002c74: 00300e93 li t4,3 - 80002c78: 01100193 li gp,17 - 80002c7c: 31d11e63 bne sp,t4,80002f98 - -0000000080002c80 : - 80002c80: 00d00093 li ra,13 - 80002c84: 401080b3 sub ra,ra,ra - 80002c88: 00000e93 li t4,0 - 80002c8c: 01200193 li gp,18 - 80002c90: 31d09463 bne ra,t4,80002f98 - -0000000080002c94 : - 80002c94: 00000213 li tp,0 - 80002c98: 00d00093 li ra,13 - 80002c9c: 00b00113 li sp,11 - 80002ca0: 40208f33 sub t5,ra,sp - 80002ca4: 000f0313 mv t1,t5 - 80002ca8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cac: 00200293 li t0,2 - 80002cb0: fe5214e3 bne tp,t0,80002c98 - 80002cb4: 00200e93 li t4,2 - 80002cb8: 01300193 li gp,19 - 80002cbc: 2dd31e63 bne t1,t4,80002f98 - -0000000080002cc0 : - 80002cc0: 00000213 li tp,0 - 80002cc4: 00e00093 li ra,14 - 80002cc8: 00b00113 li sp,11 - 80002ccc: 40208f33 sub t5,ra,sp - 80002cd0: 00000013 nop - 80002cd4: 000f0313 mv t1,t5 - 80002cd8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cdc: 00200293 li t0,2 - 80002ce0: fe5212e3 bne tp,t0,80002cc4 - 80002ce4: 00300e93 li t4,3 - 80002ce8: 01400193 li gp,20 - 80002cec: 2bd31663 bne t1,t4,80002f98 - -0000000080002cf0 : - 80002cf0: 00000213 li tp,0 - 80002cf4: 00f00093 li ra,15 - 80002cf8: 00b00113 li sp,11 - 80002cfc: 40208f33 sub t5,ra,sp - 80002d00: 00000013 nop - 80002d04: 00000013 nop - 80002d08: 000f0313 mv t1,t5 - 80002d0c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d10: 00200293 li t0,2 - 80002d14: fe5210e3 bne tp,t0,80002cf4 - 80002d18: 00400e93 li t4,4 - 80002d1c: 01500193 li gp,21 - 80002d20: 27d31c63 bne t1,t4,80002f98 - -0000000080002d24 : - 80002d24: 00000213 li tp,0 - 80002d28: 00d00093 li ra,13 - 80002d2c: 00b00113 li sp,11 - 80002d30: 40208f33 sub t5,ra,sp - 80002d34: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d38: 00200293 li t0,2 - 80002d3c: fe5216e3 bne tp,t0,80002d28 - 80002d40: 00200e93 li t4,2 - 80002d44: 01600193 li gp,22 - 80002d48: 25df1863 bne t5,t4,80002f98 - -0000000080002d4c : - 80002d4c: 00000213 li tp,0 - 80002d50: 00e00093 li ra,14 - 80002d54: 00b00113 li sp,11 - 80002d58: 00000013 nop - 80002d5c: 40208f33 sub t5,ra,sp - 80002d60: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d64: 00200293 li t0,2 - 80002d68: fe5214e3 bne tp,t0,80002d50 - 80002d6c: 00300e93 li t4,3 - 80002d70: 01700193 li gp,23 - 80002d74: 23df1263 bne t5,t4,80002f98 - -0000000080002d78 : - 80002d78: 00000213 li tp,0 - 80002d7c: 00f00093 li ra,15 - 80002d80: 00b00113 li sp,11 - 80002d84: 00000013 nop - 80002d88: 00000013 nop - 80002d8c: 40208f33 sub t5,ra,sp - 80002d90: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d94: 00200293 li t0,2 - 80002d98: fe5212e3 bne tp,t0,80002d7c - 80002d9c: 00400e93 li t4,4 - 80002da0: 01800193 li gp,24 - 80002da4: 1fdf1a63 bne t5,t4,80002f98 - -0000000080002da8 : - 80002da8: 00000213 li tp,0 - 80002dac: 00d00093 li ra,13 - 80002db0: 00000013 nop - 80002db4: 00b00113 li sp,11 - 80002db8: 40208f33 sub t5,ra,sp - 80002dbc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dc0: 00200293 li t0,2 - 80002dc4: fe5214e3 bne tp,t0,80002dac - 80002dc8: 00200e93 li t4,2 - 80002dcc: 01900193 li gp,25 - 80002dd0: 1ddf1463 bne t5,t4,80002f98 - -0000000080002dd4 : - 80002dd4: 00000213 li tp,0 - 80002dd8: 00e00093 li ra,14 - 80002ddc: 00000013 nop - 80002de0: 00b00113 li sp,11 - 80002de4: 00000013 nop - 80002de8: 40208f33 sub t5,ra,sp - 80002dec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002df0: 00200293 li t0,2 - 80002df4: fe5212e3 bne tp,t0,80002dd8 - 80002df8: 00300e93 li t4,3 - 80002dfc: 01a00193 li gp,26 - 80002e00: 19df1c63 bne t5,t4,80002f98 - -0000000080002e04 : - 80002e04: 00000213 li tp,0 - 80002e08: 00f00093 li ra,15 - 80002e0c: 00000013 nop - 80002e10: 00000013 nop - 80002e14: 00b00113 li sp,11 - 80002e18: 40208f33 sub t5,ra,sp - 80002e1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e20: 00200293 li t0,2 - 80002e24: fe5212e3 bne tp,t0,80002e08 - 80002e28: 00400e93 li t4,4 - 80002e2c: 01b00193 li gp,27 - 80002e30: 17df1463 bne t5,t4,80002f98 - -0000000080002e34 : - 80002e34: 00000213 li tp,0 - 80002e38: 00b00113 li sp,11 - 80002e3c: 00d00093 li ra,13 - 80002e40: 40208f33 sub t5,ra,sp - 80002e44: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e48: 00200293 li t0,2 - 80002e4c: fe5216e3 bne tp,t0,80002e38 - 80002e50: 00200e93 li t4,2 - 80002e54: 01c00193 li gp,28 - 80002e58: 15df1063 bne t5,t4,80002f98 - -0000000080002e5c : - 80002e5c: 00000213 li tp,0 - 80002e60: 00b00113 li sp,11 - 80002e64: 00e00093 li ra,14 - 80002e68: 00000013 nop - 80002e6c: 40208f33 sub t5,ra,sp - 80002e70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e74: 00200293 li t0,2 - 80002e78: fe5214e3 bne tp,t0,80002e60 - 80002e7c: 00300e93 li t4,3 - 80002e80: 01d00193 li gp,29 - 80002e84: 11df1a63 bne t5,t4,80002f98 - -0000000080002e88 : - 80002e88: 00000213 li tp,0 - 80002e8c: 00b00113 li sp,11 - 80002e90: 00f00093 li ra,15 - 80002e94: 00000013 nop - 80002e98: 00000013 nop - 80002e9c: 40208f33 sub t5,ra,sp - 80002ea0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ea4: 00200293 li t0,2 - 80002ea8: fe5212e3 bne tp,t0,80002e8c - 80002eac: 00400e93 li t4,4 - 80002eb0: 01e00193 li gp,30 - 80002eb4: 0fdf1263 bne t5,t4,80002f98 - -0000000080002eb8 : - 80002eb8: 00000213 li tp,0 - 80002ebc: 00b00113 li sp,11 - 80002ec0: 00000013 nop - 80002ec4: 00d00093 li ra,13 - 80002ec8: 40208f33 sub t5,ra,sp - 80002ecc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ed0: 00200293 li t0,2 - 80002ed4: fe5214e3 bne tp,t0,80002ebc - 80002ed8: 00200e93 li t4,2 - 80002edc: 01f00193 li gp,31 - 80002ee0: 0bdf1c63 bne t5,t4,80002f98 - -0000000080002ee4 : - 80002ee4: 00000213 li tp,0 - 80002ee8: 00b00113 li sp,11 - 80002eec: 00000013 nop - 80002ef0: 00e00093 li ra,14 - 80002ef4: 00000013 nop - 80002ef8: 40208f33 sub t5,ra,sp - 80002efc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f00: 00200293 li t0,2 - 80002f04: fe5212e3 bne tp,t0,80002ee8 - 80002f08: 00300e93 li t4,3 - 80002f0c: 02000193 li gp,32 - 80002f10: 09df1463 bne t5,t4,80002f98 - -0000000080002f14 : - 80002f14: 00000213 li tp,0 - 80002f18: 00b00113 li sp,11 - 80002f1c: 00000013 nop - 80002f20: 00000013 nop - 80002f24: 00f00093 li ra,15 - 80002f28: 40208f33 sub t5,ra,sp - 80002f2c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f30: 00200293 li t0,2 - 80002f34: fe5212e3 bne tp,t0,80002f18 - 80002f38: 00400e93 li t4,4 - 80002f3c: 02100193 li gp,33 - 80002f40: 05df1c63 bne t5,t4,80002f98 - -0000000080002f44 : - 80002f44: ff100093 li ra,-15 - 80002f48: 40100133 neg sp,ra - 80002f4c: 00f00e93 li t4,15 - 80002f50: 02200193 li gp,34 - 80002f54: 05d11263 bne sp,t4,80002f98 - -0000000080002f58 : - 80002f58: 02000093 li ra,32 - 80002f5c: 40008133 sub sp,ra,zero - 80002f60: 02000e93 li t4,32 - 80002f64: 02300193 li gp,35 - 80002f68: 03d11863 bne sp,t4,80002f98 - -0000000080002f6c : - 80002f6c: 400000b3 neg ra,zero - 80002f70: 00000e93 li t4,0 - 80002f74: 02400193 li gp,36 - 80002f78: 03d09063 bne ra,t4,80002f98 - -0000000080002f7c : - 80002f7c: 01000093 li ra,16 - 80002f80: 01e00113 li sp,30 - 80002f84: 40208033 sub zero,ra,sp - 80002f88: 00000e93 li t4,0 - 80002f8c: 02500193 li gp,37 - 80002f90: 01d01463 bne zero,t4,80002f98 - 80002f94: 00301a63 bne zero,gp,80002fa8 - -0000000080002f98 : - 80002f98: 00119513 slli a0,gp,0x1 - 80002f9c: 00050063 beqz a0,80002f9c - 80002fa0: 00156513 ori a0,a0,1 - 80002fa4: 00000073 ecall - -0000000080002fa8 : - 80002fa8: 00100513 li a0,1 - 80002fac: 00000073 ecall - 80002fb0: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-sub.elf b/test/riscv/tests/rv64ui-v-sub.elf deleted file mode 100644 index 25ce44fb..00000000 Binary files a/test/riscv/tests/rv64ui-v-sub.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-subw.dump b/test/riscv/tests/rv64ui-v-subw.dump deleted file mode 100644 index 8832cb76..00000000 --- a/test/riscv/tests/rv64ui-v-subw.dump +++ /dev/null @@ -1,1214 +0,0 @@ - -rv64ui-v-subw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: b5068693 addi a3,a3,-1200 # 80002fa8 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: b8460613 addi a2,a2,-1148 # 80003038 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: b4c60613 addi a2,a2,-1204 # 80003050 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: a9c68693 addi a3,a3,-1380 # 80002ff0 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: ab868693 addi a3,a3,-1352 # 80003128 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: a3860613 addi a2,a2,-1480 # 80003100 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: 96c68693 addi a3,a3,-1684 # 80003158 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 88c68693 addi a3,a3,-1908 # 800030c8 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00001697 auipc a3,0x1 - 80002878: 81c68693 addi a3,a3,-2020 # 80003090 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 02a00793 li a5,42 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0accb7b7 lui a5,0xaccb - 80002a70: 000805b7 lui a1,0x80 - 80002a74: c3078793 addi a5,a5,-976 # accac30 <_start-0x753353d0> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000093 li ra,0 - 80002acc: 00000113 li sp,0 - 80002ad0: 40208f3b subw t5,ra,sp - 80002ad4: 00000e93 li t4,0 - 80002ad8: 00200193 li gp,2 - 80002adc: 4bdf1663 bne t5,t4,80002f88 - -0000000080002ae0 : - 80002ae0: 00100093 li ra,1 - 80002ae4: 00100113 li sp,1 - 80002ae8: 40208f3b subw t5,ra,sp - 80002aec: 00000e93 li t4,0 - 80002af0: 00300193 li gp,3 - 80002af4: 49df1a63 bne t5,t4,80002f88 - -0000000080002af8 : - 80002af8: 00300093 li ra,3 - 80002afc: 00700113 li sp,7 - 80002b00: 40208f3b subw t5,ra,sp - 80002b04: ffc00e93 li t4,-4 - 80002b08: 00400193 li gp,4 - 80002b0c: 47df1e63 bne t5,t4,80002f88 - -0000000080002b10 : - 80002b10: 00000093 li ra,0 - 80002b14: ffff8137 lui sp,0xffff8 - 80002b18: 40208f3b subw t5,ra,sp - 80002b1c: 00008eb7 lui t4,0x8 - 80002b20: 00500193 li gp,5 - 80002b24: 47df1263 bne t5,t4,80002f88 - -0000000080002b28 : - 80002b28: 800000b7 lui ra,0x80000 - 80002b2c: 00000113 li sp,0 - 80002b30: 40208f3b subw t5,ra,sp - 80002b34: 80000eb7 lui t4,0x80000 - 80002b38: 00600193 li gp,6 - 80002b3c: 45df1663 bne t5,t4,80002f88 - -0000000080002b40 : - 80002b40: 800000b7 lui ra,0x80000 - 80002b44: ffff8137 lui sp,0xffff8 - 80002b48: 40208f3b subw t5,ra,sp - 80002b4c: 80008eb7 lui t4,0x80008 - 80002b50: 00700193 li gp,7 - 80002b54: 43df1a63 bne t5,t4,80002f88 - -0000000080002b58 : - 80002b58: 00000093 li ra,0 - 80002b5c: 00008137 lui sp,0x8 - 80002b60: fff1011b addiw sp,sp,-1 - 80002b64: 40208f3b subw t5,ra,sp - 80002b68: ffff8eb7 lui t4,0xffff8 - 80002b6c: 001e8e9b addiw t4,t4,1 - 80002b70: 00800193 li gp,8 - 80002b74: 41df1a63 bne t5,t4,80002f88 - -0000000080002b78 : - 80002b78: 800000b7 lui ra,0x80000 - 80002b7c: fff0809b addiw ra,ra,-1 - 80002b80: 00000113 li sp,0 - 80002b84: 40208f3b subw t5,ra,sp - 80002b88: 80000eb7 lui t4,0x80000 - 80002b8c: fffe8e9b addiw t4,t4,-1 - 80002b90: 00900193 li gp,9 - 80002b94: 3fdf1a63 bne t5,t4,80002f88 - -0000000080002b98 : - 80002b98: 800000b7 lui ra,0x80000 - 80002b9c: fff0809b addiw ra,ra,-1 - 80002ba0: 00008137 lui sp,0x8 - 80002ba4: fff1011b addiw sp,sp,-1 - 80002ba8: 40208f3b subw t5,ra,sp - 80002bac: 7fff8eb7 lui t4,0x7fff8 - 80002bb0: 00a00193 li gp,10 - 80002bb4: 3ddf1a63 bne t5,t4,80002f88 - -0000000080002bb8 : - 80002bb8: 800000b7 lui ra,0x80000 - 80002bbc: 00008137 lui sp,0x8 - 80002bc0: fff1011b addiw sp,sp,-1 - 80002bc4: 40208f3b subw t5,ra,sp - 80002bc8: 7fff8eb7 lui t4,0x7fff8 - 80002bcc: 001e8e9b addiw t4,t4,1 - 80002bd0: 00b00193 li gp,11 - 80002bd4: 3bdf1a63 bne t5,t4,80002f88 - -0000000080002bd8 : - 80002bd8: 800000b7 lui ra,0x80000 - 80002bdc: fff0809b addiw ra,ra,-1 - 80002be0: ffff8137 lui sp,0xffff8 - 80002be4: 40208f3b subw t5,ra,sp - 80002be8: 80008eb7 lui t4,0x80008 - 80002bec: fffe8e9b addiw t4,t4,-1 - 80002bf0: 00c00193 li gp,12 - 80002bf4: 39df1a63 bne t5,t4,80002f88 - -0000000080002bf8 : - 80002bf8: 00000093 li ra,0 - 80002bfc: fff00113 li sp,-1 - 80002c00: 40208f3b subw t5,ra,sp - 80002c04: 00100e93 li t4,1 - 80002c08: 00d00193 li gp,13 - 80002c0c: 37df1e63 bne t5,t4,80002f88 - -0000000080002c10 : - 80002c10: fff00093 li ra,-1 - 80002c14: 00100113 li sp,1 - 80002c18: 40208f3b subw t5,ra,sp - 80002c1c: ffe00e93 li t4,-2 - 80002c20: 00e00193 li gp,14 - 80002c24: 37df1263 bne t5,t4,80002f88 - -0000000080002c28 : - 80002c28: fff00093 li ra,-1 - 80002c2c: fff00113 li sp,-1 - 80002c30: 40208f3b subw t5,ra,sp - 80002c34: 00000e93 li t4,0 - 80002c38: 00f00193 li gp,15 - 80002c3c: 35df1663 bne t5,t4,80002f88 - -0000000080002c40 : - 80002c40: 00d00093 li ra,13 - 80002c44: 00b00113 li sp,11 - 80002c48: 402080bb subw ra,ra,sp - 80002c4c: 00200e93 li t4,2 - 80002c50: 01000193 li gp,16 - 80002c54: 33d09a63 bne ra,t4,80002f88 - -0000000080002c58 : - 80002c58: 00e00093 li ra,14 - 80002c5c: 00b00113 li sp,11 - 80002c60: 4020813b subw sp,ra,sp - 80002c64: 00300e93 li t4,3 - 80002c68: 01100193 li gp,17 - 80002c6c: 31d11e63 bne sp,t4,80002f88 - -0000000080002c70 : - 80002c70: 00d00093 li ra,13 - 80002c74: 401080bb subw ra,ra,ra - 80002c78: 00000e93 li t4,0 - 80002c7c: 01200193 li gp,18 - 80002c80: 31d09463 bne ra,t4,80002f88 - -0000000080002c84 : - 80002c84: 00000213 li tp,0 - 80002c88: 00d00093 li ra,13 - 80002c8c: 00b00113 li sp,11 - 80002c90: 40208f3b subw t5,ra,sp - 80002c94: 000f0313 mv t1,t5 - 80002c98: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c9c: 00200293 li t0,2 - 80002ca0: fe5214e3 bne tp,t0,80002c88 - 80002ca4: 00200e93 li t4,2 - 80002ca8: 01300193 li gp,19 - 80002cac: 2dd31e63 bne t1,t4,80002f88 - -0000000080002cb0 : - 80002cb0: 00000213 li tp,0 - 80002cb4: 00e00093 li ra,14 - 80002cb8: 00b00113 li sp,11 - 80002cbc: 40208f3b subw t5,ra,sp - 80002cc0: 00000013 nop - 80002cc4: 000f0313 mv t1,t5 - 80002cc8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ccc: 00200293 li t0,2 - 80002cd0: fe5212e3 bne tp,t0,80002cb4 - 80002cd4: 00300e93 li t4,3 - 80002cd8: 01400193 li gp,20 - 80002cdc: 2bd31663 bne t1,t4,80002f88 - -0000000080002ce0 : - 80002ce0: 00000213 li tp,0 - 80002ce4: 00f00093 li ra,15 - 80002ce8: 00b00113 li sp,11 - 80002cec: 40208f3b subw t5,ra,sp - 80002cf0: 00000013 nop - 80002cf4: 00000013 nop - 80002cf8: 000f0313 mv t1,t5 - 80002cfc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d00: 00200293 li t0,2 - 80002d04: fe5210e3 bne tp,t0,80002ce4 - 80002d08: 00400e93 li t4,4 - 80002d0c: 01500193 li gp,21 - 80002d10: 27d31c63 bne t1,t4,80002f88 - -0000000080002d14 : - 80002d14: 00000213 li tp,0 - 80002d18: 00d00093 li ra,13 - 80002d1c: 00b00113 li sp,11 - 80002d20: 40208f3b subw t5,ra,sp - 80002d24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d28: 00200293 li t0,2 - 80002d2c: fe5216e3 bne tp,t0,80002d18 - 80002d30: 00200e93 li t4,2 - 80002d34: 01600193 li gp,22 - 80002d38: 25df1863 bne t5,t4,80002f88 - -0000000080002d3c : - 80002d3c: 00000213 li tp,0 - 80002d40: 00e00093 li ra,14 - 80002d44: 00b00113 li sp,11 - 80002d48: 00000013 nop - 80002d4c: 40208f3b subw t5,ra,sp - 80002d50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d54: 00200293 li t0,2 - 80002d58: fe5214e3 bne tp,t0,80002d40 - 80002d5c: 00300e93 li t4,3 - 80002d60: 01700193 li gp,23 - 80002d64: 23df1263 bne t5,t4,80002f88 - -0000000080002d68 : - 80002d68: 00000213 li tp,0 - 80002d6c: 00f00093 li ra,15 - 80002d70: 00b00113 li sp,11 - 80002d74: 00000013 nop - 80002d78: 00000013 nop - 80002d7c: 40208f3b subw t5,ra,sp - 80002d80: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d84: 00200293 li t0,2 - 80002d88: fe5212e3 bne tp,t0,80002d6c - 80002d8c: 00400e93 li t4,4 - 80002d90: 01800193 li gp,24 - 80002d94: 1fdf1a63 bne t5,t4,80002f88 - -0000000080002d98 : - 80002d98: 00000213 li tp,0 - 80002d9c: 00d00093 li ra,13 - 80002da0: 00000013 nop - 80002da4: 00b00113 li sp,11 - 80002da8: 40208f3b subw t5,ra,sp - 80002dac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002db0: 00200293 li t0,2 - 80002db4: fe5214e3 bne tp,t0,80002d9c - 80002db8: 00200e93 li t4,2 - 80002dbc: 01900193 li gp,25 - 80002dc0: 1ddf1463 bne t5,t4,80002f88 - -0000000080002dc4 : - 80002dc4: 00000213 li tp,0 - 80002dc8: 00e00093 li ra,14 - 80002dcc: 00000013 nop - 80002dd0: 00b00113 li sp,11 - 80002dd4: 00000013 nop - 80002dd8: 40208f3b subw t5,ra,sp - 80002ddc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002de0: 00200293 li t0,2 - 80002de4: fe5212e3 bne tp,t0,80002dc8 - 80002de8: 00300e93 li t4,3 - 80002dec: 01a00193 li gp,26 - 80002df0: 19df1c63 bne t5,t4,80002f88 - -0000000080002df4 : - 80002df4: 00000213 li tp,0 - 80002df8: 00f00093 li ra,15 - 80002dfc: 00000013 nop - 80002e00: 00000013 nop - 80002e04: 00b00113 li sp,11 - 80002e08: 40208f3b subw t5,ra,sp - 80002e0c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e10: 00200293 li t0,2 - 80002e14: fe5212e3 bne tp,t0,80002df8 - 80002e18: 00400e93 li t4,4 - 80002e1c: 01b00193 li gp,27 - 80002e20: 17df1463 bne t5,t4,80002f88 - -0000000080002e24 : - 80002e24: 00000213 li tp,0 - 80002e28: 00b00113 li sp,11 - 80002e2c: 00d00093 li ra,13 - 80002e30: 40208f3b subw t5,ra,sp - 80002e34: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e38: 00200293 li t0,2 - 80002e3c: fe5216e3 bne tp,t0,80002e28 - 80002e40: 00200e93 li t4,2 - 80002e44: 01c00193 li gp,28 - 80002e48: 15df1063 bne t5,t4,80002f88 - -0000000080002e4c : - 80002e4c: 00000213 li tp,0 - 80002e50: 00b00113 li sp,11 - 80002e54: 00e00093 li ra,14 - 80002e58: 00000013 nop - 80002e5c: 40208f3b subw t5,ra,sp - 80002e60: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e64: 00200293 li t0,2 - 80002e68: fe5214e3 bne tp,t0,80002e50 - 80002e6c: 00300e93 li t4,3 - 80002e70: 01d00193 li gp,29 - 80002e74: 11df1a63 bne t5,t4,80002f88 - -0000000080002e78 : - 80002e78: 00000213 li tp,0 - 80002e7c: 00b00113 li sp,11 - 80002e80: 00f00093 li ra,15 - 80002e84: 00000013 nop - 80002e88: 00000013 nop - 80002e8c: 40208f3b subw t5,ra,sp - 80002e90: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e94: 00200293 li t0,2 - 80002e98: fe5212e3 bne tp,t0,80002e7c - 80002e9c: 00400e93 li t4,4 - 80002ea0: 01e00193 li gp,30 - 80002ea4: 0fdf1263 bne t5,t4,80002f88 - -0000000080002ea8 : - 80002ea8: 00000213 li tp,0 - 80002eac: 00b00113 li sp,11 - 80002eb0: 00000013 nop - 80002eb4: 00d00093 li ra,13 - 80002eb8: 40208f3b subw t5,ra,sp - 80002ebc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ec0: 00200293 li t0,2 - 80002ec4: fe5214e3 bne tp,t0,80002eac - 80002ec8: 00200e93 li t4,2 - 80002ecc: 01f00193 li gp,31 - 80002ed0: 0bdf1c63 bne t5,t4,80002f88 - -0000000080002ed4 : - 80002ed4: 00000213 li tp,0 - 80002ed8: 00b00113 li sp,11 - 80002edc: 00000013 nop - 80002ee0: 00e00093 li ra,14 - 80002ee4: 00000013 nop - 80002ee8: 40208f3b subw t5,ra,sp - 80002eec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ef0: 00200293 li t0,2 - 80002ef4: fe5212e3 bne tp,t0,80002ed8 - 80002ef8: 00300e93 li t4,3 - 80002efc: 02000193 li gp,32 - 80002f00: 09df1463 bne t5,t4,80002f88 - -0000000080002f04 : - 80002f04: 00000213 li tp,0 - 80002f08: 00b00113 li sp,11 - 80002f0c: 00000013 nop - 80002f10: 00000013 nop - 80002f14: 00f00093 li ra,15 - 80002f18: 40208f3b subw t5,ra,sp - 80002f1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f20: 00200293 li t0,2 - 80002f24: fe5212e3 bne tp,t0,80002f08 - 80002f28: 00400e93 li t4,4 - 80002f2c: 02100193 li gp,33 - 80002f30: 05df1c63 bne t5,t4,80002f88 - -0000000080002f34 : - 80002f34: ff100093 li ra,-15 - 80002f38: 4010013b negw sp,ra - 80002f3c: 00f00e93 li t4,15 - 80002f40: 02200193 li gp,34 - 80002f44: 05d11263 bne sp,t4,80002f88 - -0000000080002f48 : - 80002f48: 02000093 li ra,32 - 80002f4c: 4000813b subw sp,ra,zero - 80002f50: 02000e93 li t4,32 - 80002f54: 02300193 li gp,35 - 80002f58: 03d11863 bne sp,t4,80002f88 - -0000000080002f5c : - 80002f5c: 400000bb negw ra,zero - 80002f60: 00000e93 li t4,0 - 80002f64: 02400193 li gp,36 - 80002f68: 03d09063 bne ra,t4,80002f88 - -0000000080002f6c : - 80002f6c: 01000093 li ra,16 - 80002f70: 01e00113 li sp,30 - 80002f74: 4020803b subw zero,ra,sp - 80002f78: 00000e93 li t4,0 - 80002f7c: 02500193 li gp,37 - 80002f80: 01d01463 bne zero,t4,80002f88 - 80002f84: 00301a63 bne zero,gp,80002f98 - -0000000080002f88 : - 80002f88: 00119513 slli a0,gp,0x1 - 80002f8c: 00050063 beqz a0,80002f8c - 80002f90: 00156513 ori a0,a0,1 - 80002f94: 00000073 ecall - -0000000080002f98 : - 80002f98: 00100513 li a0,1 - 80002f9c: 00000073 ecall - 80002fa0: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-subw.elf b/test/riscv/tests/rv64ui-v-subw.elf deleted file mode 100644 index 0c451dbc..00000000 Binary files a/test/riscv/tests/rv64ui-v-subw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-sw.dump b/test/riscv/tests/rv64ui-v-sw.dump deleted file mode 100644 index 60671e20..00000000 --- a/test/riscv/tests/rv64ui-v-sw.dump +++ /dev/null @@ -1,1203 +0,0 @@ - -rv64ui-v-sw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 0000a117 auipc sp,0xa - 8000001c: 6b810113 addi sp,sp,1720 # 8000a6d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00003617 auipc a2,0x3 - 80002318: cec60613 addi a2,a2,-788 # 80005000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00007797 auipc a5,0x7 - 80002334: 4b878793 addi a5,a5,1208 # 800097e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00007717 auipc a4,0x7 - 80002348: 49c70713 addi a4,a4,1180 # 800097e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00007897 auipc a7,0x7 - 80002354: 48f8bc23 sd a5,1176(a7) # 800097e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00007797 auipc a5,0x7 - 80002384: 07078793 addi a5,a5,112 # 800093f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf6810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00007797 auipc a5,0x7 - 80002448: 3807be23 sd zero,924(a5) # 800097e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: b1068693 addi a3,a3,-1264 # 80002f68 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: b4460613 addi a2,a2,-1212 # 80002ff8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: b0c60613 addi a2,a2,-1268 # 80003010 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: a5c68693 addi a3,a3,-1444 # 80002fb0 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: a7868693 addi a3,a3,-1416 # 800030e8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 9f860613 addi a2,a2,-1544 # 800030c0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00007d17 auipc s10,0x7 - 80002720: cd4d0d13 addi s10,s10,-812 # 800093f0 - 80002724: 00003b97 auipc s7,0x3 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80005000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00007a17 auipc s4,0x7 - 80002738: 0aca0a13 addi s4,s4,172 # 800097e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00007717 auipc a4,0x7 - 8000274c: 08f73c23 sd a5,152(a4) # 800097e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00007717 auipc a4,0x7 - 800027d4: 00f73823 sd a5,16(a4) # 800097e0 - 800027d8: 00007717 auipc a4,0x7 - 800027dc: 00f73823 sd a5,16(a4) # 800097e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: 92c68693 addi a3,a3,-1748 # 80003118 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 84c68693 addi a3,a3,-1972 # 80003088 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 7dc68693 addi a3,a3,2012 # 80003050 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00003697 auipc a3,0x3 - 800028e0: 72468693 addi a3,a3,1828 # 80006000 - 800028e4: 00004717 auipc a4,0x4 - 800028e8: 71c70713 addi a4,a4,1820 # 80007000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00005797 auipc a5,0x5 - 800028f8: 70c78793 addi a5,a5,1804 # 80008000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00002897 auipc a7,0x2 - 80002914: 6ed8b823 sd a3,1776(a7) # 80005000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00003697 auipc a3,0x3 - 80002920: 6ce6be23 sd a4,1756(a3) # 80005ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00002617 auipc a2,0x2 - 80002938: 6cc60613 addi a2,a2,1740 # 80005000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00005697 auipc a3,0x5 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80007ff8 - 8000294c: 00003717 auipc a4,0x3 - 80002950: 6af73a23 sd a5,1716(a4) # 80006000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00006697 auipc a3,0x6 - 800029c0: 64468693 addi a3,a3,1604 # 80009000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00007617 auipc a2,0x7 - 800029d0: e0f63e23 sd a5,-484(a2) # 800097e8 - 800029d4: 00007797 auipc a5,0x7 - 800029d8: e0e7b623 sd a4,-500(a5) # 800097e0 - 800029dc: 00007317 auipc t1,0x7 - 800029e0: a1430313 addi t1,t1,-1516 # 800093f0 - 800029e4: 02900793 li a5,41 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00007797 auipc a5,0x7 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800093e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 06fb17b7 lui a5,0x6fb1 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: a0a78793 addi a5,a5,-1526 # 6fb0a0a <_start-0x7904f5f6> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00001097 auipc ra,0x1 - 80002acc: 53808093 addi ra,ra,1336 # 80004000 - 80002ad0: 00aa0137 lui sp,0xaa0 - 80002ad4: 0aa1011b addiw sp,sp,170 - 80002ad8: 0020a023 sw sp,0(ra) - 80002adc: 0000af03 lw t5,0(ra) - 80002ae0: 00aa0eb7 lui t4,0xaa0 - 80002ae4: 0aae8e9b addiw t4,t4,170 - 80002ae8: 00200193 li gp,2 - 80002aec: 47df1063 bne t5,t4,80002f4c - -0000000080002af0 : - 80002af0: 00001097 auipc ra,0x1 - 80002af4: 51008093 addi ra,ra,1296 # 80004000 - 80002af8: aa00b137 lui sp,0xaa00b - 80002afc: a001011b addiw sp,sp,-1536 - 80002b00: 0020a223 sw sp,4(ra) - 80002b04: 0040af03 lw t5,4(ra) - 80002b08: aa00beb7 lui t4,0xaa00b - 80002b0c: a00e8e9b addiw t4,t4,-1536 - 80002b10: 00300193 li gp,3 - 80002b14: 43df1c63 bne t5,t4,80002f4c - -0000000080002b18 : - 80002b18: 00001097 auipc ra,0x1 - 80002b1c: 4e808093 addi ra,ra,1256 # 80004000 - 80002b20: 0aa01137 lui sp,0xaa01 - 80002b24: aa01011b addiw sp,sp,-1376 - 80002b28: 0020a423 sw sp,8(ra) - 80002b2c: 0080af03 lw t5,8(ra) - 80002b30: 0aa01eb7 lui t4,0xaa01 - 80002b34: aa0e8e9b addiw t4,t4,-1376 - 80002b38: 00400193 li gp,4 - 80002b3c: 41df1863 bne t5,t4,80002f4c - -0000000080002b40 : - 80002b40: 00001097 auipc ra,0x1 - 80002b44: 4c008093 addi ra,ra,1216 # 80004000 - 80002b48: a00aa137 lui sp,0xa00aa - 80002b4c: 00a1011b addiw sp,sp,10 - 80002b50: 0020a623 sw sp,12(ra) - 80002b54: 00c0af03 lw t5,12(ra) - 80002b58: a00aaeb7 lui t4,0xa00aa - 80002b5c: 00ae8e9b addiw t4,t4,10 - 80002b60: 00500193 li gp,5 - 80002b64: 3fdf1463 bne t5,t4,80002f4c - -0000000080002b68 : - 80002b68: 00001097 auipc ra,0x1 - 80002b6c: 4b408093 addi ra,ra,1204 # 8000401c - 80002b70: 00aa0137 lui sp,0xaa0 - 80002b74: 0aa1011b addiw sp,sp,170 - 80002b78: fe20aa23 sw sp,-12(ra) - 80002b7c: ff40af03 lw t5,-12(ra) - 80002b80: 00aa0eb7 lui t4,0xaa0 - 80002b84: 0aae8e9b addiw t4,t4,170 - 80002b88: 00600193 li gp,6 - 80002b8c: 3ddf1063 bne t5,t4,80002f4c - -0000000080002b90 : - 80002b90: 00001097 auipc ra,0x1 - 80002b94: 48c08093 addi ra,ra,1164 # 8000401c - 80002b98: aa00b137 lui sp,0xaa00b - 80002b9c: a001011b addiw sp,sp,-1536 - 80002ba0: fe20ac23 sw sp,-8(ra) - 80002ba4: ff80af03 lw t5,-8(ra) - 80002ba8: aa00beb7 lui t4,0xaa00b - 80002bac: a00e8e9b addiw t4,t4,-1536 - 80002bb0: 00700193 li gp,7 - 80002bb4: 39df1c63 bne t5,t4,80002f4c - -0000000080002bb8 : - 80002bb8: 00001097 auipc ra,0x1 - 80002bbc: 46408093 addi ra,ra,1124 # 8000401c - 80002bc0: 0aa01137 lui sp,0xaa01 - 80002bc4: aa01011b addiw sp,sp,-1376 - 80002bc8: fe20ae23 sw sp,-4(ra) - 80002bcc: ffc0af03 lw t5,-4(ra) - 80002bd0: 0aa01eb7 lui t4,0xaa01 - 80002bd4: aa0e8e9b addiw t4,t4,-1376 - 80002bd8: 00800193 li gp,8 - 80002bdc: 37df1863 bne t5,t4,80002f4c - -0000000080002be0 : - 80002be0: 00001097 auipc ra,0x1 - 80002be4: 43c08093 addi ra,ra,1084 # 8000401c - 80002be8: a00aa137 lui sp,0xa00aa - 80002bec: 00a1011b addiw sp,sp,10 - 80002bf0: 0020a023 sw sp,0(ra) - 80002bf4: 0000af03 lw t5,0(ra) - 80002bf8: a00aaeb7 lui t4,0xa00aa - 80002bfc: 00ae8e9b addiw t4,t4,10 - 80002c00: 00900193 li gp,9 - 80002c04: 35df1463 bne t5,t4,80002f4c - -0000000080002c08 : - 80002c08: 00001097 auipc ra,0x1 - 80002c0c: 41808093 addi ra,ra,1048 # 80004020 - 80002c10: 12345137 lui sp,0x12345 - 80002c14: 6781011b addiw sp,sp,1656 - 80002c18: fe008213 addi tp,ra,-32 - 80002c1c: 02222023 sw sp,32(tp) # 20 <_start-0x7fffffe0> - 80002c20: 0000a283 lw t0,0(ra) - 80002c24: 12345eb7 lui t4,0x12345 - 80002c28: 678e8e9b addiw t4,t4,1656 - 80002c2c: 00a00193 li gp,10 - 80002c30: 31d29e63 bne t0,t4,80002f4c - -0000000080002c34 : - 80002c34: 00001097 auipc ra,0x1 - 80002c38: 3ec08093 addi ra,ra,1004 # 80004020 - 80002c3c: 58213137 lui sp,0x58213 - 80002c40: 0981011b addiw sp,sp,152 - 80002c44: ffd08093 addi ra,ra,-3 - 80002c48: 0020a3a3 sw sp,7(ra) - 80002c4c: 00001217 auipc tp,0x1 - 80002c50: 3d820213 addi tp,tp,984 # 80004024 - 80002c54: 00022283 lw t0,0(tp) # 0 <_start-0x80000000> - 80002c58: 58213eb7 lui t4,0x58213 - 80002c5c: 098e8e9b addiw t4,t4,152 - 80002c60: 00b00193 li gp,11 - 80002c64: 2fd29463 bne t0,t4,80002f4c - -0000000080002c68 : - 80002c68: 00c00193 li gp,12 - 80002c6c: 00000213 li tp,0 - 80002c70: aabbd0b7 lui ra,0xaabbd - 80002c74: cdd0809b addiw ra,ra,-803 - 80002c78: 00001117 auipc sp,0x1 - 80002c7c: 38810113 addi sp,sp,904 # 80004000 - 80002c80: 00112023 sw ra,0(sp) - 80002c84: 00012f03 lw t5,0(sp) - 80002c88: aabbdeb7 lui t4,0xaabbd - 80002c8c: cdde8e9b addiw t4,t4,-803 - 80002c90: 2bdf1e63 bne t5,t4,80002f4c - 80002c94: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c98: 00200293 li t0,2 - 80002c9c: fc521ae3 bne tp,t0,80002c70 - -0000000080002ca0 : - 80002ca0: 00d00193 li gp,13 - 80002ca4: 00000213 li tp,0 - 80002ca8: daabc0b7 lui ra,0xdaabc - 80002cac: ccd0809b addiw ra,ra,-819 - 80002cb0: 00001117 auipc sp,0x1 - 80002cb4: 35010113 addi sp,sp,848 # 80004000 - 80002cb8: 00000013 nop - 80002cbc: 00112223 sw ra,4(sp) - 80002cc0: 00412f03 lw t5,4(sp) - 80002cc4: daabceb7 lui t4,0xdaabc - 80002cc8: ccde8e9b addiw t4,t4,-819 - 80002ccc: 29df1063 bne t5,t4,80002f4c - 80002cd0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cd4: 00200293 li t0,2 - 80002cd8: fc5218e3 bne tp,t0,80002ca8 - -0000000080002cdc : - 80002cdc: 00e00193 li gp,14 - 80002ce0: 00000213 li tp,0 - 80002ce4: ddaac0b7 lui ra,0xddaac - 80002ce8: bcc0809b addiw ra,ra,-1076 - 80002cec: 00001117 auipc sp,0x1 - 80002cf0: 31410113 addi sp,sp,788 # 80004000 - 80002cf4: 00000013 nop - 80002cf8: 00000013 nop - 80002cfc: 00112423 sw ra,8(sp) - 80002d00: 00812f03 lw t5,8(sp) - 80002d04: ddaaceb7 lui t4,0xddaac - 80002d08: bcce8e9b addiw t4,t4,-1076 - 80002d0c: 25df1063 bne t5,t4,80002f4c - 80002d10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d14: 00200293 li t0,2 - 80002d18: fc5216e3 bne tp,t0,80002ce4 - -0000000080002d1c : - 80002d1c: 00f00193 li gp,15 - 80002d20: 00000213 li tp,0 - 80002d24: cddab0b7 lui ra,0xcddab - 80002d28: bbc0809b addiw ra,ra,-1092 - 80002d2c: 00000013 nop - 80002d30: 00001117 auipc sp,0x1 - 80002d34: 2d010113 addi sp,sp,720 # 80004000 - 80002d38: 00112623 sw ra,12(sp) - 80002d3c: 00c12f03 lw t5,12(sp) - 80002d40: cddabeb7 lui t4,0xcddab - 80002d44: bbce8e9b addiw t4,t4,-1092 - 80002d48: 21df1263 bne t5,t4,80002f4c - 80002d4c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d50: 00200293 li t0,2 - 80002d54: fc5218e3 bne tp,t0,80002d24 - -0000000080002d58 : - 80002d58: 01000193 li gp,16 - 80002d5c: 00000213 li tp,0 - 80002d60: ccddb0b7 lui ra,0xccddb - 80002d64: abb0809b addiw ra,ra,-1349 - 80002d68: 00000013 nop - 80002d6c: 00001117 auipc sp,0x1 - 80002d70: 29410113 addi sp,sp,660 # 80004000 - 80002d74: 00000013 nop - 80002d78: 00112823 sw ra,16(sp) - 80002d7c: 01012f03 lw t5,16(sp) - 80002d80: ccddbeb7 lui t4,0xccddb - 80002d84: abbe8e9b addiw t4,t4,-1349 - 80002d88: 1ddf1263 bne t5,t4,80002f4c - 80002d8c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d90: 00200293 li t0,2 - 80002d94: fc5216e3 bne tp,t0,80002d60 - -0000000080002d98 : - 80002d98: 01100193 li gp,17 - 80002d9c: 00000213 li tp,0 - 80002da0: bccde0b7 lui ra,0xbccde - 80002da4: aab0809b addiw ra,ra,-1365 - 80002da8: 00000013 nop - 80002dac: 00000013 nop - 80002db0: 00001117 auipc sp,0x1 - 80002db4: 25010113 addi sp,sp,592 # 80004000 - 80002db8: 00112a23 sw ra,20(sp) - 80002dbc: 01412f03 lw t5,20(sp) - 80002dc0: bccdeeb7 lui t4,0xbccde - 80002dc4: aabe8e9b addiw t4,t4,-1365 - 80002dc8: 19df1263 bne t5,t4,80002f4c - 80002dcc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dd0: 00200293 li t0,2 - 80002dd4: fc5216e3 bne tp,t0,80002da0 - -0000000080002dd8 : - 80002dd8: 01200193 li gp,18 - 80002ddc: 00000213 li tp,0 - 80002de0: 00001117 auipc sp,0x1 - 80002de4: 22010113 addi sp,sp,544 # 80004000 - 80002de8: 001120b7 lui ra,0x112 - 80002dec: 2330809b addiw ra,ra,563 - 80002df0: 00112023 sw ra,0(sp) - 80002df4: 00012f03 lw t5,0(sp) - 80002df8: 00112eb7 lui t4,0x112 - 80002dfc: 233e8e9b addiw t4,t4,563 - 80002e00: 15df1663 bne t5,t4,80002f4c - 80002e04: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e08: 00200293 li t0,2 - 80002e0c: fc521ae3 bne tp,t0,80002de0 - -0000000080002e10 : - 80002e10: 01300193 li gp,19 - 80002e14: 00000213 li tp,0 - 80002e18: 00001117 auipc sp,0x1 - 80002e1c: 1e810113 addi sp,sp,488 # 80004000 - 80002e20: 300110b7 lui ra,0x30011 - 80002e24: 2230809b addiw ra,ra,547 - 80002e28: 00000013 nop - 80002e2c: 00112223 sw ra,4(sp) - 80002e30: 00412f03 lw t5,4(sp) - 80002e34: 30011eb7 lui t4,0x30011 - 80002e38: 223e8e9b addiw t4,t4,547 - 80002e3c: 11df1863 bne t5,t4,80002f4c - 80002e40: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e44: 00200293 li t0,2 - 80002e48: fc5218e3 bne tp,t0,80002e18 - -0000000080002e4c : - 80002e4c: 01400193 li gp,20 - 80002e50: 00000213 li tp,0 - 80002e54: 00001117 auipc sp,0x1 - 80002e58: 1ac10113 addi sp,sp,428 # 80004000 - 80002e5c: 330010b7 lui ra,0x33001 - 80002e60: 1220809b addiw ra,ra,290 - 80002e64: 00000013 nop - 80002e68: 00000013 nop - 80002e6c: 00112423 sw ra,8(sp) - 80002e70: 00812f03 lw t5,8(sp) - 80002e74: 33001eb7 lui t4,0x33001 - 80002e78: 122e8e9b addiw t4,t4,290 - 80002e7c: 0ddf1863 bne t5,t4,80002f4c - 80002e80: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e84: 00200293 li t0,2 - 80002e88: fc5216e3 bne tp,t0,80002e54 - -0000000080002e8c : - 80002e8c: 01500193 li gp,21 - 80002e90: 00000213 li tp,0 - 80002e94: 00001117 auipc sp,0x1 - 80002e98: 16c10113 addi sp,sp,364 # 80004000 - 80002e9c: 00000013 nop - 80002ea0: 233000b7 lui ra,0x23300 - 80002ea4: 1120809b addiw ra,ra,274 - 80002ea8: 00112623 sw ra,12(sp) - 80002eac: 00c12f03 lw t5,12(sp) - 80002eb0: 23300eb7 lui t4,0x23300 - 80002eb4: 112e8e9b addiw t4,t4,274 - 80002eb8: 09df1a63 bne t5,t4,80002f4c - 80002ebc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ec0: 00200293 li t0,2 - 80002ec4: fc5218e3 bne tp,t0,80002e94 - -0000000080002ec8 : - 80002ec8: 01600193 li gp,22 - 80002ecc: 00000213 li tp,0 - 80002ed0: 00001117 auipc sp,0x1 - 80002ed4: 13010113 addi sp,sp,304 # 80004000 - 80002ed8: 00000013 nop - 80002edc: 223300b7 lui ra,0x22330 - 80002ee0: 0110809b addiw ra,ra,17 - 80002ee4: 00000013 nop - 80002ee8: 00112823 sw ra,16(sp) - 80002eec: 01012f03 lw t5,16(sp) - 80002ef0: 22330eb7 lui t4,0x22330 - 80002ef4: 011e8e9b addiw t4,t4,17 - 80002ef8: 05df1a63 bne t5,t4,80002f4c - 80002efc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f00: 00200293 li t0,2 - 80002f04: fc5216e3 bne tp,t0,80002ed0 - -0000000080002f08 : - 80002f08: 01700193 li gp,23 - 80002f0c: 00000213 li tp,0 - 80002f10: 00001117 auipc sp,0x1 - 80002f14: 0f010113 addi sp,sp,240 # 80004000 - 80002f18: 00000013 nop - 80002f1c: 00000013 nop - 80002f20: 122330b7 lui ra,0x12233 - 80002f24: 0010809b addiw ra,ra,1 - 80002f28: 00112a23 sw ra,20(sp) - 80002f2c: 01412f03 lw t5,20(sp) - 80002f30: 12233eb7 lui t4,0x12233 - 80002f34: 001e8e9b addiw t4,t4,1 - 80002f38: 01df1a63 bne t5,t4,80002f4c - 80002f3c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f40: 00200293 li t0,2 - 80002f44: fc5216e3 bne tp,t0,80002f10 - 80002f48: 00301a63 bne zero,gp,80002f5c - -0000000080002f4c : - 80002f4c: 00119513 slli a0,gp,0x1 - 80002f50: 00050063 beqz a0,80002f50 - 80002f54: 00156513 ori a0,a0,1 - 80002f58: 00000073 ecall - -0000000080002f5c : - 80002f5c: 00100513 li a0,1 - 80002f60: 00000073 ecall - 80002f64: c0001073 unimp - -Disassembly of section .data: - -0000000080004000 : - 80004000: deadbeef jal t4,7ffdf5ea <_start-0x20a16> - -0000000080004004 : - 80004004: deadbeef jal t4,7ffdf5ee <_start-0x20a12> - -0000000080004008 : - 80004008: deadbeef jal t4,7ffdf5f2 <_start-0x20a0e> - -000000008000400c : - 8000400c: deadbeef jal t4,7ffdf5f6 <_start-0x20a0a> - -0000000080004010 : - 80004010: deadbeef jal t4,7ffdf5fa <_start-0x20a06> - -0000000080004014 : - 80004014: deadbeef jal t4,7ffdf5fe <_start-0x20a02> - -0000000080004018 : - 80004018: deadbeef jal t4,7ffdf602 <_start-0x209fe> - -000000008000401c : - 8000401c: deadbeef jal t4,7ffdf606 <_start-0x209fa> - -0000000080004020 : - 80004020: deadbeef jal t4,7ffdf60a <_start-0x209f6> - -0000000080004024 : - 80004024: deadbeef jal t4,7ffdf60e <_start-0x209f2> diff --git a/test/riscv/tests/rv64ui-v-sw.elf b/test/riscv/tests/rv64ui-v-sw.elf deleted file mode 100644 index d52322bf..00000000 Binary files a/test/riscv/tests/rv64ui-v-sw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-xor.dump b/test/riscv/tests/rv64ui-v-xor.dump deleted file mode 100644 index 8b95600c..00000000 --- a/test/riscv/tests/rv64ui-v-xor.dump +++ /dev/null @@ -1,1260 +0,0 @@ - -rv64ui-v-xor: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: c5868693 addi a3,a3,-936 # 800030b0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: c8c60613 addi a2,a2,-884 # 80003140 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: c5460613 addi a2,a2,-940 # 80003158 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: ba468693 addi a3,a3,-1116 # 800030f8 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: bc068693 addi a3,a3,-1088 # 80003230 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: b4060613 addi a2,a2,-1216 # 80003208 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: a7468693 addi a3,a3,-1420 # 80003260 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 99468693 addi a3,a3,-1644 # 800031d0 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00001697 auipc a3,0x1 - 80002878: 92468693 addi a3,a3,-1756 # 80003198 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 02900793 li a5,41 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0c2b87b7 lui a5,0xc2b8 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 9f278793 addi a5,a5,-1550 # c2b79f2 <_start-0x73d4860e> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 000100b7 lui ra,0x10 - 80002acc: f010809b addiw ra,ra,-255 - 80002ad0: 01009093 slli ra,ra,0x10 - 80002ad4: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002ad8: 0f0f1137 lui sp,0xf0f1 - 80002adc: f0f1011b addiw sp,sp,-241 - 80002ae0: 0020cf33 xor t5,ra,sp - 80002ae4: 000f0eb7 lui t4,0xf0 - 80002ae8: 0ffe8e9b addiw t4,t4,255 - 80002aec: 00ce9e93 slli t4,t4,0xc - 80002af0: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 80002af4: 00200193 li gp,2 - 80002af8: 59df1c63 bne t5,t4,80003090 - -0000000080002afc : - 80002afc: 0ff010b7 lui ra,0xff01 - 80002b00: ff00809b addiw ra,ra,-16 - 80002b04: 000f1137 lui sp,0xf1 - 80002b08: f0f1011b addiw sp,sp,-241 - 80002b0c: 00c11113 slli sp,sp,0xc - 80002b10: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002b14: 0020cf33 xor t5,ra,sp - 80002b18: 00010eb7 lui t4,0x10 - 80002b1c: f01e8e9b addiw t4,t4,-255 - 80002b20: 010e9e93 slli t4,t4,0x10 - 80002b24: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80002b28: 00300193 li gp,3 - 80002b2c: 57df1263 bne t5,t4,80003090 - -0000000080002b30 : - 80002b30: 00ff00b7 lui ra,0xff0 - 80002b34: 0ff0809b addiw ra,ra,255 - 80002b38: 0f0f1137 lui sp,0xf0f1 - 80002b3c: f0f1011b addiw sp,sp,-241 - 80002b40: 0020cf33 xor t5,ra,sp - 80002b44: 0ff01eb7 lui t4,0xff01 - 80002b48: ff0e8e9b addiw t4,t4,-16 - 80002b4c: 00400193 li gp,4 - 80002b50: 55df1063 bne t5,t4,80003090 - -0000000080002b54 : - 80002b54: 000f00b7 lui ra,0xf0 - 80002b58: 0ff0809b addiw ra,ra,255 - 80002b5c: 00c09093 slli ra,ra,0xc - 80002b60: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> - 80002b64: 000f1137 lui sp,0xf1 - 80002b68: f0f1011b addiw sp,sp,-241 - 80002b6c: 00c11113 slli sp,sp,0xc - 80002b70: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002b74: 0020cf33 xor t5,ra,sp - 80002b78: 00ff0eb7 lui t4,0xff0 - 80002b7c: 0ffe8e9b addiw t4,t4,255 - 80002b80: 00500193 li gp,5 - 80002b84: 51df1663 bne t5,t4,80003090 - -0000000080002b88 : - 80002b88: 000100b7 lui ra,0x10 - 80002b8c: f010809b addiw ra,ra,-255 - 80002b90: 01009093 slli ra,ra,0x10 - 80002b94: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002b98: 0f0f1137 lui sp,0xf0f1 - 80002b9c: f0f1011b addiw sp,sp,-241 - 80002ba0: 0020c0b3 xor ra,ra,sp - 80002ba4: 000f0eb7 lui t4,0xf0 - 80002ba8: 0ffe8e9b addiw t4,t4,255 - 80002bac: 00ce9e93 slli t4,t4,0xc - 80002bb0: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 80002bb4: 00600193 li gp,6 - 80002bb8: 4dd09c63 bne ra,t4,80003090 - -0000000080002bbc : - 80002bbc: 000100b7 lui ra,0x10 - 80002bc0: f010809b addiw ra,ra,-255 - 80002bc4: 01009093 slli ra,ra,0x10 - 80002bc8: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002bcc: 0f0f1137 lui sp,0xf0f1 - 80002bd0: f0f1011b addiw sp,sp,-241 - 80002bd4: 0020c133 xor sp,ra,sp - 80002bd8: 000f0eb7 lui t4,0xf0 - 80002bdc: 0ffe8e9b addiw t4,t4,255 - 80002be0: 00ce9e93 slli t4,t4,0xc - 80002be4: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 80002be8: 00700193 li gp,7 - 80002bec: 4bd11263 bne sp,t4,80003090 - -0000000080002bf0 : - 80002bf0: 000100b7 lui ra,0x10 - 80002bf4: f010809b addiw ra,ra,-255 - 80002bf8: 01009093 slli ra,ra,0x10 - 80002bfc: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002c00: 0010c0b3 xor ra,ra,ra - 80002c04: 00000e93 li t4,0 - 80002c08: 00800193 li gp,8 - 80002c0c: 49d09263 bne ra,t4,80003090 - -0000000080002c10 : - 80002c10: 00000213 li tp,0 - 80002c14: 000100b7 lui ra,0x10 - 80002c18: f010809b addiw ra,ra,-255 - 80002c1c: 01009093 slli ra,ra,0x10 - 80002c20: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002c24: 0f0f1137 lui sp,0xf0f1 - 80002c28: f0f1011b addiw sp,sp,-241 - 80002c2c: 0020cf33 xor t5,ra,sp - 80002c30: 000f0313 mv t1,t5 - 80002c34: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c38: 00200293 li t0,2 - 80002c3c: fc521ce3 bne tp,t0,80002c14 - 80002c40: 000f0eb7 lui t4,0xf0 - 80002c44: 0ffe8e9b addiw t4,t4,255 - 80002c48: 00ce9e93 slli t4,t4,0xc - 80002c4c: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 80002c50: 00900193 li gp,9 - 80002c54: 43d31e63 bne t1,t4,80003090 - -0000000080002c58 : - 80002c58: 00000213 li tp,0 - 80002c5c: 0ff010b7 lui ra,0xff01 - 80002c60: ff00809b addiw ra,ra,-16 - 80002c64: 000f1137 lui sp,0xf1 - 80002c68: f0f1011b addiw sp,sp,-241 - 80002c6c: 00c11113 slli sp,sp,0xc - 80002c70: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002c74: 0020cf33 xor t5,ra,sp - 80002c78: 00000013 nop - 80002c7c: 000f0313 mv t1,t5 - 80002c80: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c84: 00200293 li t0,2 - 80002c88: fc521ae3 bne tp,t0,80002c5c - 80002c8c: 00010eb7 lui t4,0x10 - 80002c90: f01e8e9b addiw t4,t4,-255 - 80002c94: 010e9e93 slli t4,t4,0x10 - 80002c98: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80002c9c: 00a00193 li gp,10 - 80002ca0: 3fd31863 bne t1,t4,80003090 - -0000000080002ca4 : - 80002ca4: 00000213 li tp,0 - 80002ca8: 00ff00b7 lui ra,0xff0 - 80002cac: 0ff0809b addiw ra,ra,255 - 80002cb0: 0f0f1137 lui sp,0xf0f1 - 80002cb4: f0f1011b addiw sp,sp,-241 - 80002cb8: 0020cf33 xor t5,ra,sp - 80002cbc: 00000013 nop - 80002cc0: 00000013 nop - 80002cc4: 000f0313 mv t1,t5 - 80002cc8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ccc: 00200293 li t0,2 - 80002cd0: fc521ce3 bne tp,t0,80002ca8 - 80002cd4: 0ff01eb7 lui t4,0xff01 - 80002cd8: ff0e8e9b addiw t4,t4,-16 - 80002cdc: 00b00193 li gp,11 - 80002ce0: 3bd31863 bne t1,t4,80003090 - -0000000080002ce4 : - 80002ce4: 00000213 li tp,0 - 80002ce8: 000100b7 lui ra,0x10 - 80002cec: f010809b addiw ra,ra,-255 - 80002cf0: 01009093 slli ra,ra,0x10 - 80002cf4: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002cf8: 0f0f1137 lui sp,0xf0f1 - 80002cfc: f0f1011b addiw sp,sp,-241 - 80002d00: 0020cf33 xor t5,ra,sp - 80002d04: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d08: 00200293 li t0,2 - 80002d0c: fc521ee3 bne tp,t0,80002ce8 - 80002d10: 000f0eb7 lui t4,0xf0 - 80002d14: 0ffe8e9b addiw t4,t4,255 - 80002d18: 00ce9e93 slli t4,t4,0xc - 80002d1c: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 80002d20: 00c00193 li gp,12 - 80002d24: 37df1663 bne t5,t4,80003090 - -0000000080002d28 : - 80002d28: 00000213 li tp,0 - 80002d2c: 0ff010b7 lui ra,0xff01 - 80002d30: ff00809b addiw ra,ra,-16 - 80002d34: 000f1137 lui sp,0xf1 - 80002d38: f0f1011b addiw sp,sp,-241 - 80002d3c: 00c11113 slli sp,sp,0xc - 80002d40: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002d44: 00000013 nop - 80002d48: 0020cf33 xor t5,ra,sp - 80002d4c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d50: 00200293 li t0,2 - 80002d54: fc521ce3 bne tp,t0,80002d2c - 80002d58: 00010eb7 lui t4,0x10 - 80002d5c: f01e8e9b addiw t4,t4,-255 - 80002d60: 010e9e93 slli t4,t4,0x10 - 80002d64: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80002d68: 00d00193 li gp,13 - 80002d6c: 33df1263 bne t5,t4,80003090 - -0000000080002d70 : - 80002d70: 00000213 li tp,0 - 80002d74: 00ff00b7 lui ra,0xff0 - 80002d78: 0ff0809b addiw ra,ra,255 - 80002d7c: 0f0f1137 lui sp,0xf0f1 - 80002d80: f0f1011b addiw sp,sp,-241 - 80002d84: 00000013 nop - 80002d88: 00000013 nop - 80002d8c: 0020cf33 xor t5,ra,sp - 80002d90: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d94: 00200293 li t0,2 - 80002d98: fc521ee3 bne tp,t0,80002d74 - 80002d9c: 0ff01eb7 lui t4,0xff01 - 80002da0: ff0e8e9b addiw t4,t4,-16 - 80002da4: 00e00193 li gp,14 - 80002da8: 2fdf1463 bne t5,t4,80003090 - -0000000080002dac : - 80002dac: 00000213 li tp,0 - 80002db0: 000100b7 lui ra,0x10 - 80002db4: f010809b addiw ra,ra,-255 - 80002db8: 01009093 slli ra,ra,0x10 - 80002dbc: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002dc0: 00000013 nop - 80002dc4: 0f0f1137 lui sp,0xf0f1 - 80002dc8: f0f1011b addiw sp,sp,-241 - 80002dcc: 0020cf33 xor t5,ra,sp - 80002dd0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dd4: 00200293 li t0,2 - 80002dd8: fc521ce3 bne tp,t0,80002db0 - 80002ddc: 000f0eb7 lui t4,0xf0 - 80002de0: 0ffe8e9b addiw t4,t4,255 - 80002de4: 00ce9e93 slli t4,t4,0xc - 80002de8: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 80002dec: 00f00193 li gp,15 - 80002df0: 2bdf1063 bne t5,t4,80003090 - -0000000080002df4 : - 80002df4: 00000213 li tp,0 - 80002df8: 0ff010b7 lui ra,0xff01 - 80002dfc: ff00809b addiw ra,ra,-16 - 80002e00: 00000013 nop - 80002e04: 000f1137 lui sp,0xf1 - 80002e08: f0f1011b addiw sp,sp,-241 - 80002e0c: 00c11113 slli sp,sp,0xc - 80002e10: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002e14: 00000013 nop - 80002e18: 0020cf33 xor t5,ra,sp - 80002e1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e20: 00200293 li t0,2 - 80002e24: fc521ae3 bne tp,t0,80002df8 - 80002e28: 00010eb7 lui t4,0x10 - 80002e2c: f01e8e9b addiw t4,t4,-255 - 80002e30: 010e9e93 slli t4,t4,0x10 - 80002e34: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80002e38: 01000193 li gp,16 - 80002e3c: 25df1a63 bne t5,t4,80003090 - -0000000080002e40 : - 80002e40: 00000213 li tp,0 - 80002e44: 00ff00b7 lui ra,0xff0 - 80002e48: 0ff0809b addiw ra,ra,255 - 80002e4c: 00000013 nop - 80002e50: 00000013 nop - 80002e54: 0f0f1137 lui sp,0xf0f1 - 80002e58: f0f1011b addiw sp,sp,-241 - 80002e5c: 0020cf33 xor t5,ra,sp - 80002e60: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e64: 00200293 li t0,2 - 80002e68: fc521ee3 bne tp,t0,80002e44 - 80002e6c: 0ff01eb7 lui t4,0xff01 - 80002e70: ff0e8e9b addiw t4,t4,-16 - 80002e74: 01100193 li gp,17 - 80002e78: 21df1c63 bne t5,t4,80003090 - -0000000080002e7c : - 80002e7c: 00000213 li tp,0 - 80002e80: 0f0f1137 lui sp,0xf0f1 - 80002e84: f0f1011b addiw sp,sp,-241 - 80002e88: 000100b7 lui ra,0x10 - 80002e8c: f010809b addiw ra,ra,-255 - 80002e90: 01009093 slli ra,ra,0x10 - 80002e94: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002e98: 0020cf33 xor t5,ra,sp - 80002e9c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ea0: 00200293 li t0,2 - 80002ea4: fc521ee3 bne tp,t0,80002e80 - 80002ea8: 000f0eb7 lui t4,0xf0 - 80002eac: 0ffe8e9b addiw t4,t4,255 - 80002eb0: 00ce9e93 slli t4,t4,0xc - 80002eb4: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 80002eb8: 01200193 li gp,18 - 80002ebc: 1ddf1a63 bne t5,t4,80003090 - -0000000080002ec0 : - 80002ec0: 00000213 li tp,0 - 80002ec4: 000f1137 lui sp,0xf1 - 80002ec8: f0f1011b addiw sp,sp,-241 - 80002ecc: 00c11113 slli sp,sp,0xc - 80002ed0: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002ed4: 0ff010b7 lui ra,0xff01 - 80002ed8: ff00809b addiw ra,ra,-16 - 80002edc: 00000013 nop - 80002ee0: 0020cf33 xor t5,ra,sp - 80002ee4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ee8: 00200293 li t0,2 - 80002eec: fc521ce3 bne tp,t0,80002ec4 - 80002ef0: 00010eb7 lui t4,0x10 - 80002ef4: f01e8e9b addiw t4,t4,-255 - 80002ef8: 010e9e93 slli t4,t4,0x10 - 80002efc: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80002f00: 01300193 li gp,19 - 80002f04: 19df1663 bne t5,t4,80003090 - -0000000080002f08 : - 80002f08: 00000213 li tp,0 - 80002f0c: 0f0f1137 lui sp,0xf0f1 - 80002f10: f0f1011b addiw sp,sp,-241 - 80002f14: 00ff00b7 lui ra,0xff0 - 80002f18: 0ff0809b addiw ra,ra,255 - 80002f1c: 00000013 nop - 80002f20: 00000013 nop - 80002f24: 0020cf33 xor t5,ra,sp - 80002f28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f2c: 00200293 li t0,2 - 80002f30: fc521ee3 bne tp,t0,80002f0c - 80002f34: 0ff01eb7 lui t4,0xff01 - 80002f38: ff0e8e9b addiw t4,t4,-16 - 80002f3c: 01400193 li gp,20 - 80002f40: 15df1863 bne t5,t4,80003090 - -0000000080002f44 : - 80002f44: 00000213 li tp,0 - 80002f48: 0f0f1137 lui sp,0xf0f1 - 80002f4c: f0f1011b addiw sp,sp,-241 - 80002f50: 00000013 nop - 80002f54: 000100b7 lui ra,0x10 - 80002f58: f010809b addiw ra,ra,-255 - 80002f5c: 01009093 slli ra,ra,0x10 - 80002f60: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80002f64: 0020cf33 xor t5,ra,sp - 80002f68: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f6c: 00200293 li t0,2 - 80002f70: fc521ce3 bne tp,t0,80002f48 - 80002f74: 000f0eb7 lui t4,0xf0 - 80002f78: 0ffe8e9b addiw t4,t4,255 - 80002f7c: 00ce9e93 slli t4,t4,0xc - 80002f80: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> - 80002f84: 01500193 li gp,21 - 80002f88: 11df1463 bne t5,t4,80003090 - -0000000080002f8c : - 80002f8c: 00000213 li tp,0 - 80002f90: 000f1137 lui sp,0xf1 - 80002f94: f0f1011b addiw sp,sp,-241 - 80002f98: 00c11113 slli sp,sp,0xc - 80002f9c: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> - 80002fa0: 00000013 nop - 80002fa4: 0ff010b7 lui ra,0xff01 - 80002fa8: ff00809b addiw ra,ra,-16 - 80002fac: 00000013 nop - 80002fb0: 0020cf33 xor t5,ra,sp - 80002fb4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002fb8: 00200293 li t0,2 - 80002fbc: fc521ae3 bne tp,t0,80002f90 - 80002fc0: 00010eb7 lui t4,0x10 - 80002fc4: f01e8e9b addiw t4,t4,-255 - 80002fc8: 010e9e93 slli t4,t4,0x10 - 80002fcc: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80002fd0: 01600193 li gp,22 - 80002fd4: 0bdf1e63 bne t5,t4,80003090 - -0000000080002fd8 : - 80002fd8: 00000213 li tp,0 - 80002fdc: 0f0f1137 lui sp,0xf0f1 - 80002fe0: f0f1011b addiw sp,sp,-241 - 80002fe4: 00000013 nop - 80002fe8: 00000013 nop - 80002fec: 00ff00b7 lui ra,0xff0 - 80002ff0: 0ff0809b addiw ra,ra,255 - 80002ff4: 0020cf33 xor t5,ra,sp - 80002ff8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ffc: 00200293 li t0,2 - 80003000: fc521ee3 bne tp,t0,80002fdc - 80003004: 0ff01eb7 lui t4,0xff01 - 80003008: ff0e8e9b addiw t4,t4,-16 - 8000300c: 01700193 li gp,23 - 80003010: 09df1063 bne t5,t4,80003090 - -0000000080003014 : - 80003014: 000100b7 lui ra,0x10 - 80003018: f010809b addiw ra,ra,-255 - 8000301c: 01009093 slli ra,ra,0x10 - 80003020: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> - 80003024: 00104133 xor sp,zero,ra - 80003028: 00010eb7 lui t4,0x10 - 8000302c: f01e8e9b addiw t4,t4,-255 - 80003030: 010e9e93 slli t4,t4,0x10 - 80003034: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> - 80003038: 01800193 li gp,24 - 8000303c: 05d11a63 bne sp,t4,80003090 - -0000000080003040 : - 80003040: 00ff00b7 lui ra,0xff0 - 80003044: 0ff0809b addiw ra,ra,255 - 80003048: 0000c133 xor sp,ra,zero - 8000304c: 00ff0eb7 lui t4,0xff0 - 80003050: 0ffe8e9b addiw t4,t4,255 - 80003054: 01900193 li gp,25 - 80003058: 03d11c63 bne sp,t4,80003090 - -000000008000305c : - 8000305c: 000040b3 xor ra,zero,zero - 80003060: 00000e93 li t4,0 - 80003064: 01a00193 li gp,26 - 80003068: 03d09463 bne ra,t4,80003090 - -000000008000306c : - 8000306c: 111110b7 lui ra,0x11111 - 80003070: 1110809b addiw ra,ra,273 - 80003074: 22222137 lui sp,0x22222 - 80003078: 2221011b addiw sp,sp,546 - 8000307c: 0020c033 xor zero,ra,sp - 80003080: 00000e93 li t4,0 - 80003084: 01b00193 li gp,27 - 80003088: 01d01463 bne zero,t4,80003090 - 8000308c: 00301a63 bne zero,gp,800030a0 - -0000000080003090 : - 80003090: 00119513 slli a0,gp,0x1 - 80003094: 00050063 beqz a0,80003094 - 80003098: 00156513 ori a0,a0,1 - 8000309c: 00000073 ecall - -00000000800030a0 : - 800030a0: 00100513 li a0,1 - 800030a4: 00000073 ecall - 800030a8: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-xor.elf b/test/riscv/tests/rv64ui-v-xor.elf deleted file mode 100644 index 151c2119..00000000 Binary files a/test/riscv/tests/rv64ui-v-xor.elf and /dev/null differ diff --git a/test/riscv/tests/rv64ui-v-xori.dump b/test/riscv/tests/rv64ui-v-xori.dump deleted file mode 100644 index cc0d051a..00000000 --- a/test/riscv/tests/rv64ui-v-xori.dump +++ /dev/null @@ -1,985 +0,0 @@ - -rv64ui-v-xori: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: 87068693 addi a3,a3,-1936 # 80002cc8 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: 8a460613 addi a2,a2,-1884 # 80002d58 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: 86c60613 addi a2,a2,-1940 # 80002d70 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 7bc68693 addi a3,a3,1980 # 80002d10 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 7d868693 addi a3,a3,2008 # 80002e48 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 75860613 addi a2,a2,1880 # 80002e20 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 68c68693 addi a3,a3,1676 # 80002e78 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 5ac68693 addi a3,a3,1452 # 80002de8 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 53c68693 addi a3,a3,1340 # 80002db0 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 02400793 li a5,36 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 08da87b7 lui a5,0x8da8 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: ffc78793 addi a5,a5,-4 # 8da7ffc <_start-0x77258004> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00ff10b7 lui ra,0xff1 - 80002acc: f000809b addiw ra,ra,-256 - 80002ad0: f0f0cf13 xori t5,ra,-241 - 80002ad4: ff00feb7 lui t4,0xff00f - 80002ad8: 00fe8e9b addiw t4,t4,15 - 80002adc: 00200193 li gp,2 - 80002ae0: 1ddf1663 bne t5,t4,80002cac - -0000000080002ae4 : - 80002ae4: 0ff010b7 lui ra,0xff01 - 80002ae8: ff00809b addiw ra,ra,-16 - 80002aec: 0f00cf13 xori t5,ra,240 - 80002af0: 0ff01eb7 lui t4,0xff01 - 80002af4: f00e8e9b addiw t4,t4,-256 - 80002af8: 00300193 li gp,3 - 80002afc: 1bdf1863 bne t5,t4,80002cac - -0000000080002b00 : - 80002b00: 00ff10b7 lui ra,0xff1 - 80002b04: 8ff0809b addiw ra,ra,-1793 - 80002b08: 70f0cf13 xori t5,ra,1807 - 80002b0c: 00ff1eb7 lui t4,0xff1 - 80002b10: ff0e8e9b addiw t4,t4,-16 - 80002b14: 00400193 li gp,4 - 80002b18: 19df1a63 bne t5,t4,80002cac - -0000000080002b1c : - 80002b1c: f00ff0b7 lui ra,0xf00ff - 80002b20: 00f0809b addiw ra,ra,15 - 80002b24: 0f00cf13 xori t5,ra,240 - 80002b28: f00ffeb7 lui t4,0xf00ff - 80002b2c: 0ffe8e9b addiw t4,t4,255 - 80002b30: 00500193 li gp,5 - 80002b34: 17df1c63 bne t5,t4,80002cac - -0000000080002b38 : - 80002b38: ff00f0b7 lui ra,0xff00f - 80002b3c: 7000809b addiw ra,ra,1792 - 80002b40: 70f0c093 xori ra,ra,1807 - 80002b44: ff00feb7 lui t4,0xff00f - 80002b48: 00fe8e9b addiw t4,t4,15 - 80002b4c: 00600193 li gp,6 - 80002b50: 15d09e63 bne ra,t4,80002cac - -0000000080002b54 : - 80002b54: 00000213 li tp,0 - 80002b58: 0ff010b7 lui ra,0xff01 - 80002b5c: ff00809b addiw ra,ra,-16 - 80002b60: 0f00cf13 xori t5,ra,240 - 80002b64: 000f0313 mv t1,t5 - 80002b68: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002b6c: 00200293 li t0,2 - 80002b70: fe5214e3 bne tp,t0,80002b58 - 80002b74: 0ff01eb7 lui t4,0xff01 - 80002b78: f00e8e9b addiw t4,t4,-256 - 80002b7c: 00700193 li gp,7 - 80002b80: 13d31663 bne t1,t4,80002cac - -0000000080002b84 : - 80002b84: 00000213 li tp,0 - 80002b88: 00ff10b7 lui ra,0xff1 - 80002b8c: 8ff0809b addiw ra,ra,-1793 - 80002b90: 70f0cf13 xori t5,ra,1807 - 80002b94: 00000013 nop - 80002b98: 000f0313 mv t1,t5 - 80002b9c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ba0: 00200293 li t0,2 - 80002ba4: fe5212e3 bne tp,t0,80002b88 - 80002ba8: 00ff1eb7 lui t4,0xff1 - 80002bac: ff0e8e9b addiw t4,t4,-16 - 80002bb0: 00800193 li gp,8 - 80002bb4: 0fd31c63 bne t1,t4,80002cac - -0000000080002bb8 : - 80002bb8: 00000213 li tp,0 - 80002bbc: f00ff0b7 lui ra,0xf00ff - 80002bc0: 00f0809b addiw ra,ra,15 - 80002bc4: 0f00cf13 xori t5,ra,240 - 80002bc8: 00000013 nop - 80002bcc: 00000013 nop - 80002bd0: 000f0313 mv t1,t5 - 80002bd4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002bd8: 00200293 li t0,2 - 80002bdc: fe5210e3 bne tp,t0,80002bbc - 80002be0: f00ffeb7 lui t4,0xf00ff - 80002be4: 0ffe8e9b addiw t4,t4,255 - 80002be8: 00900193 li gp,9 - 80002bec: 0dd31063 bne t1,t4,80002cac - -0000000080002bf0 : - 80002bf0: 00000213 li tp,0 - 80002bf4: 0ff010b7 lui ra,0xff01 - 80002bf8: ff00809b addiw ra,ra,-16 - 80002bfc: 0f00cf13 xori t5,ra,240 - 80002c00: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c04: 00200293 li t0,2 - 80002c08: fe5216e3 bne tp,t0,80002bf4 - 80002c0c: 0ff01eb7 lui t4,0xff01 - 80002c10: f00e8e9b addiw t4,t4,-256 - 80002c14: 00a00193 li gp,10 - 80002c18: 09df1a63 bne t5,t4,80002cac - -0000000080002c1c : - 80002c1c: 00000213 li tp,0 - 80002c20: 00ff10b7 lui ra,0xff1 - 80002c24: fff0809b addiw ra,ra,-1 - 80002c28: 00000013 nop - 80002c2c: 00f0cf13 xori t5,ra,15 - 80002c30: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c34: 00200293 li t0,2 - 80002c38: fe5214e3 bne tp,t0,80002c20 - 80002c3c: 00ff1eb7 lui t4,0xff1 - 80002c40: ff0e8e9b addiw t4,t4,-16 - 80002c44: 00b00193 li gp,11 - 80002c48: 07df1263 bne t5,t4,80002cac - -0000000080002c4c : - 80002c4c: 00000213 li tp,0 - 80002c50: f00ff0b7 lui ra,0xf00ff - 80002c54: 00f0809b addiw ra,ra,15 - 80002c58: 00000013 nop - 80002c5c: 00000013 nop - 80002c60: 0f00cf13 xori t5,ra,240 - 80002c64: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c68: 00200293 li t0,2 - 80002c6c: fe5212e3 bne tp,t0,80002c50 - 80002c70: f00ffeb7 lui t4,0xf00ff - 80002c74: 0ffe8e9b addiw t4,t4,255 - 80002c78: 00c00193 li gp,12 - 80002c7c: 03df1863 bne t5,t4,80002cac - -0000000080002c80 : - 80002c80: 0f004093 xori ra,zero,240 - 80002c84: 0f000e93 li t4,240 - 80002c88: 00d00193 li gp,13 - 80002c8c: 03d09063 bne ra,t4,80002cac - -0000000080002c90 : - 80002c90: 00ff00b7 lui ra,0xff0 - 80002c94: 0ff0809b addiw ra,ra,255 - 80002c98: 70f0c013 xori zero,ra,1807 - 80002c9c: 00000e93 li t4,0 - 80002ca0: 00e00193 li gp,14 - 80002ca4: 01d01463 bne zero,t4,80002cac - 80002ca8: 00301a63 bne zero,gp,80002cbc - -0000000080002cac : - 80002cac: 00119513 slli a0,gp,0x1 - 80002cb0: 00050063 beqz a0,80002cb0 - 80002cb4: 00156513 ori a0,a0,1 - 80002cb8: 00000073 ecall - -0000000080002cbc : - 80002cbc: 00100513 li a0,1 - 80002cc0: 00000073 ecall - 80002cc4: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-v-xori.elf b/test/riscv/tests/rv64ui-v-xori.elf deleted file mode 100644 index d716ff2e..00000000 Binary files a/test/riscv/tests/rv64ui-v-xori.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-p-div.dump b/test/riscv/tests/rv64um-p-div.dump deleted file mode 100644 index b117c5cd..00000000 --- a/test/riscv/tests/rv64um-p-div.dump +++ /dev/null @@ -1,195 +0,0 @@ - -rv64um-p-div: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 01400093 li ra,20 - 80000100: 00600113 li sp,6 - 80000104: 0220cf33 div t5,ra,sp - 80000108: 00300e93 li t4,3 - 8000010c: 00200193 li gp,2 - 80000110: 0ddf1e63 bne t5,t4,800001ec - -0000000080000114 : - 80000114: fec00093 li ra,-20 - 80000118: 00600113 li sp,6 - 8000011c: 0220cf33 div t5,ra,sp - 80000120: ffd00e93 li t4,-3 - 80000124: 00300193 li gp,3 - 80000128: 0ddf1263 bne t5,t4,800001ec - -000000008000012c : - 8000012c: 01400093 li ra,20 - 80000130: ffa00113 li sp,-6 - 80000134: 0220cf33 div t5,ra,sp - 80000138: ffd00e93 li t4,-3 - 8000013c: 00400193 li gp,4 - 80000140: 0bdf1663 bne t5,t4,800001ec - -0000000080000144 : - 80000144: fec00093 li ra,-20 - 80000148: ffa00113 li sp,-6 - 8000014c: 0220cf33 div t5,ra,sp - 80000150: 00300e93 li t4,3 - 80000154: 00500193 li gp,5 - 80000158: 09df1a63 bne t5,t4,800001ec - -000000008000015c : - 8000015c: fff0009b addiw ra,zero,-1 - 80000160: 03f09093 slli ra,ra,0x3f - 80000164: 00100113 li sp,1 - 80000168: 0220cf33 div t5,ra,sp - 8000016c: fff00e9b addiw t4,zero,-1 - 80000170: 03fe9e93 slli t4,t4,0x3f - 80000174: 00600193 li gp,6 - 80000178: 07df1a63 bne t5,t4,800001ec - -000000008000017c : - 8000017c: fff0009b addiw ra,zero,-1 - 80000180: 03f09093 slli ra,ra,0x3f - 80000184: fff00113 li sp,-1 - 80000188: 0220cf33 div t5,ra,sp - 8000018c: fff00e9b addiw t4,zero,-1 - 80000190: 03fe9e93 slli t4,t4,0x3f - 80000194: 00700193 li gp,7 - 80000198: 05df1a63 bne t5,t4,800001ec - -000000008000019c : - 8000019c: fff0009b addiw ra,zero,-1 - 800001a0: 03f09093 slli ra,ra,0x3f - 800001a4: 00000113 li sp,0 - 800001a8: 0220cf33 div t5,ra,sp - 800001ac: fff00e93 li t4,-1 - 800001b0: 00800193 li gp,8 - 800001b4: 03df1c63 bne t5,t4,800001ec - -00000000800001b8 : - 800001b8: 00100093 li ra,1 - 800001bc: 00000113 li sp,0 - 800001c0: 0220cf33 div t5,ra,sp - 800001c4: fff00e93 li t4,-1 - 800001c8: 00900193 li gp,9 - 800001cc: 03df1063 bne t5,t4,800001ec - -00000000800001d0 : - 800001d0: 00000093 li ra,0 - 800001d4: 00000113 li sp,0 - 800001d8: 0220cf33 div t5,ra,sp - 800001dc: fff00e93 li t4,-1 - 800001e0: 00a00193 li gp,10 - 800001e4: 01df1463 bne t5,t4,800001ec - 800001e8: 00301c63 bne zero,gp,80000200 - -00000000800001ec : - 800001ec: 0ff0000f fence - 800001f0: 00018063 beqz gp,800001f0 - 800001f4: 00119193 slli gp,gp,0x1 - 800001f8: 0011e193 ori gp,gp,1 - 800001fc: 00000073 ecall - -0000000080000200 : - 80000200: 0ff0000f fence - 80000204: 00100193 li gp,1 - 80000208: 00000073 ecall - 8000020c: c0001073 unimp - 80000210: 0000 unimp - 80000212: 0000 unimp - 80000214: 0000 unimp - 80000216: 0000 unimp - 80000218: 0000 unimp - 8000021a: 0000 unimp - 8000021c: 0000 unimp - 8000021e: 0000 unimp - 80000220: 0000 unimp - 80000222: 0000 unimp - 80000224: 0000 unimp - 80000226: 0000 unimp - 80000228: 0000 unimp - 8000022a: 0000 unimp - 8000022c: 0000 unimp - 8000022e: 0000 unimp - 80000230: 0000 unimp - 80000232: 0000 unimp - 80000234: 0000 unimp - 80000236: 0000 unimp - 80000238: 0000 unimp - 8000023a: 0000 unimp - 8000023c: 0000 unimp - 8000023e: 0000 unimp - 80000240: 0000 unimp - 80000242: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-div.elf b/test/riscv/tests/rv64um-p-div.elf deleted file mode 100644 index d202d094..00000000 Binary files a/test/riscv/tests/rv64um-p-div.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-p-divu.dump b/test/riscv/tests/rv64um-p-divu.dump deleted file mode 100644 index f987025d..00000000 --- a/test/riscv/tests/rv64um-p-divu.dump +++ /dev/null @@ -1,189 +0,0 @@ - -rv64um-p-divu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 01400093 li ra,20 - 80000100: 00600113 li sp,6 - 80000104: 0220df33 divu t5,ra,sp - 80000108: 00300e93 li t4,3 - 8000010c: 00200193 li gp,2 - 80000110: 0fdf1a63 bne t5,t4,80000204 - -0000000080000114 : - 80000114: fec00093 li ra,-20 - 80000118: 00600113 li sp,6 - 8000011c: 0220df33 divu t5,ra,sp - 80000120: 02aabeb7 lui t4,0x2aab - 80000124: aabe8e9b addiw t4,t4,-1365 - 80000128: 00ce9e93 slli t4,t4,0xc - 8000012c: aabe8e93 addi t4,t4,-1365 # 2aaaaab <_start-0x7d555555> - 80000130: 00ce9e93 slli t4,t4,0xc - 80000134: aabe8e93 addi t4,t4,-1365 - 80000138: 00ce9e93 slli t4,t4,0xc - 8000013c: aa7e8e93 addi t4,t4,-1369 - 80000140: 00300193 li gp,3 - 80000144: 0ddf1063 bne t5,t4,80000204 - -0000000080000148 : - 80000148: 01400093 li ra,20 - 8000014c: ffa00113 li sp,-6 - 80000150: 0220df33 divu t5,ra,sp - 80000154: 00000e93 li t4,0 - 80000158: 00400193 li gp,4 - 8000015c: 0bdf1463 bne t5,t4,80000204 - -0000000080000160 : - 80000160: fec00093 li ra,-20 - 80000164: ffa00113 li sp,-6 - 80000168: 0220df33 divu t5,ra,sp - 8000016c: 00000e93 li t4,0 - 80000170: 00500193 li gp,5 - 80000174: 09df1863 bne t5,t4,80000204 - -0000000080000178 : - 80000178: fff0009b addiw ra,zero,-1 - 8000017c: 03f09093 slli ra,ra,0x3f - 80000180: 00100113 li sp,1 - 80000184: 0220df33 divu t5,ra,sp - 80000188: fff00e9b addiw t4,zero,-1 - 8000018c: 03fe9e93 slli t4,t4,0x3f - 80000190: 00600193 li gp,6 - 80000194: 07df1863 bne t5,t4,80000204 - -0000000080000198 : - 80000198: fff0009b addiw ra,zero,-1 - 8000019c: 03f09093 slli ra,ra,0x3f - 800001a0: fff00113 li sp,-1 - 800001a4: 0220df33 divu t5,ra,sp - 800001a8: 00000e93 li t4,0 - 800001ac: 00700193 li gp,7 - 800001b0: 05df1a63 bne t5,t4,80000204 - -00000000800001b4 : - 800001b4: fff0009b addiw ra,zero,-1 - 800001b8: 03f09093 slli ra,ra,0x3f - 800001bc: 00000113 li sp,0 - 800001c0: 0220df33 divu t5,ra,sp - 800001c4: fff00e93 li t4,-1 - 800001c8: 00800193 li gp,8 - 800001cc: 03df1c63 bne t5,t4,80000204 - -00000000800001d0 : - 800001d0: 00100093 li ra,1 - 800001d4: 00000113 li sp,0 - 800001d8: 0220df33 divu t5,ra,sp - 800001dc: fff00e93 li t4,-1 - 800001e0: 00900193 li gp,9 - 800001e4: 03df1063 bne t5,t4,80000204 - -00000000800001e8 : - 800001e8: 00000093 li ra,0 - 800001ec: 00000113 li sp,0 - 800001f0: 0220df33 divu t5,ra,sp - 800001f4: fff00e93 li t4,-1 - 800001f8: 00a00193 li gp,10 - 800001fc: 01df1463 bne t5,t4,80000204 - 80000200: 00301c63 bne zero,gp,80000218 - -0000000080000204 : - 80000204: 0ff0000f fence - 80000208: 00018063 beqz gp,80000208 - 8000020c: 00119193 slli gp,gp,0x1 - 80000210: 0011e193 ori gp,gp,1 - 80000214: 00000073 ecall - -0000000080000218 : - 80000218: 0ff0000f fence - 8000021c: 00100193 li gp,1 - 80000220: 00000073 ecall - 80000224: c0001073 unimp - 80000228: 0000 unimp - 8000022a: 0000 unimp - 8000022c: 0000 unimp - 8000022e: 0000 unimp - 80000230: 0000 unimp - 80000232: 0000 unimp - 80000234: 0000 unimp - 80000236: 0000 unimp - 80000238: 0000 unimp - 8000023a: 0000 unimp - 8000023c: 0000 unimp - 8000023e: 0000 unimp - 80000240: 0000 unimp - 80000242: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-divu.elf b/test/riscv/tests/rv64um-p-divu.elf deleted file mode 100644 index bef0d696..00000000 Binary files a/test/riscv/tests/rv64um-p-divu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-p-divuw.dump b/test/riscv/tests/rv64um-p-divuw.dump deleted file mode 100644 index 576f2638..00000000 --- a/test/riscv/tests/rv64um-p-divuw.dump +++ /dev/null @@ -1,197 +0,0 @@ - -rv64um-p-divuw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 01400093 li ra,20 - 80000100: 00600113 li sp,6 - 80000104: 0220df3b divuw t5,ra,sp - 80000108: 00300e93 li t4,3 - 8000010c: 00200193 li gp,2 - 80000110: 0ddf1a63 bne t5,t4,800001e4 - -0000000080000114 : - 80000114: 0010009b addiw ra,zero,1 - 80000118: 02009093 slli ra,ra,0x20 - 8000011c: fec08093 addi ra,ra,-20 - 80000120: 00600113 li sp,6 - 80000124: 0220df3b divuw t5,ra,sp - 80000128: 2aaabeb7 lui t4,0x2aaab - 8000012c: aa7e8e9b addiw t4,t4,-1369 - 80000130: 00300193 li gp,3 - 80000134: 0bdf1863 bne t5,t4,800001e4 - -0000000080000138 : - 80000138: 01400093 li ra,20 - 8000013c: ffa00113 li sp,-6 - 80000140: 0220df3b divuw t5,ra,sp - 80000144: 00000e93 li t4,0 - 80000148: 00400193 li gp,4 - 8000014c: 09df1c63 bne t5,t4,800001e4 - -0000000080000150 : - 80000150: fec00093 li ra,-20 - 80000154: ffa00113 li sp,-6 - 80000158: 0220df3b divuw t5,ra,sp - 8000015c: 00000e93 li t4,0 - 80000160: 00500193 li gp,5 - 80000164: 09df1063 bne t5,t4,800001e4 - -0000000080000168 : - 80000168: 800000b7 lui ra,0x80000 - 8000016c: 00100113 li sp,1 - 80000170: 0220df3b divuw t5,ra,sp - 80000174: 80000eb7 lui t4,0x80000 - 80000178: 00600193 li gp,6 - 8000017c: 07df1463 bne t5,t4,800001e4 - -0000000080000180 : - 80000180: 800000b7 lui ra,0x80000 - 80000184: fff00113 li sp,-1 - 80000188: 0220df3b divuw t5,ra,sp - 8000018c: 00000e93 li t4,0 - 80000190: 00700193 li gp,7 - 80000194: 05df1863 bne t5,t4,800001e4 - -0000000080000198 : - 80000198: 800000b7 lui ra,0x80000 - 8000019c: 00000113 li sp,0 - 800001a0: 0220df3b divuw t5,ra,sp - 800001a4: fff00e93 li t4,-1 - 800001a8: 00800193 li gp,8 - 800001ac: 03df1c63 bne t5,t4,800001e4 - -00000000800001b0 : - 800001b0: 00100093 li ra,1 - 800001b4: 00000113 li sp,0 - 800001b8: 0220df3b divuw t5,ra,sp - 800001bc: fff00e93 li t4,-1 - 800001c0: 00900193 li gp,9 - 800001c4: 03df1063 bne t5,t4,800001e4 - -00000000800001c8 : - 800001c8: 00000093 li ra,0 - 800001cc: 00000113 li sp,0 - 800001d0: 0220df3b divuw t5,ra,sp - 800001d4: fff00e93 li t4,-1 - 800001d8: 00a00193 li gp,10 - 800001dc: 01df1463 bne t5,t4,800001e4 - 800001e0: 00301c63 bne zero,gp,800001f8 - -00000000800001e4 : - 800001e4: 0ff0000f fence - 800001e8: 00018063 beqz gp,800001e8 - 800001ec: 00119193 slli gp,gp,0x1 - 800001f0: 0011e193 ori gp,gp,1 - 800001f4: 00000073 ecall - -00000000800001f8 : - 800001f8: 0ff0000f fence - 800001fc: 00100193 li gp,1 - 80000200: 00000073 ecall - 80000204: c0001073 unimp - 80000208: 0000 unimp - 8000020a: 0000 unimp - 8000020c: 0000 unimp - 8000020e: 0000 unimp - 80000210: 0000 unimp - 80000212: 0000 unimp - 80000214: 0000 unimp - 80000216: 0000 unimp - 80000218: 0000 unimp - 8000021a: 0000 unimp - 8000021c: 0000 unimp - 8000021e: 0000 unimp - 80000220: 0000 unimp - 80000222: 0000 unimp - 80000224: 0000 unimp - 80000226: 0000 unimp - 80000228: 0000 unimp - 8000022a: 0000 unimp - 8000022c: 0000 unimp - 8000022e: 0000 unimp - 80000230: 0000 unimp - 80000232: 0000 unimp - 80000234: 0000 unimp - 80000236: 0000 unimp - 80000238: 0000 unimp - 8000023a: 0000 unimp - 8000023c: 0000 unimp - 8000023e: 0000 unimp - 80000240: 0000 unimp - 80000242: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-divuw.elf b/test/riscv/tests/rv64um-p-divuw.elf deleted file mode 100644 index 1d1e44fa..00000000 Binary files a/test/riscv/tests/rv64um-p-divuw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-p-divw.dump b/test/riscv/tests/rv64um-p-divw.dump deleted file mode 100644 index 2d331a94..00000000 --- a/test/riscv/tests/rv64um-p-divw.dump +++ /dev/null @@ -1,168 +0,0 @@ - -rv64um-p-divw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 01400093 li ra,20 - 80000100: 00600113 li sp,6 - 80000104: 0220cf3b divw t5,ra,sp - 80000108: 00300e93 li t4,3 - 8000010c: 00200193 li gp,2 - 80000110: 0ddf1463 bne t5,t4,800001d8 - -0000000080000114 : - 80000114: fec00093 li ra,-20 - 80000118: 00600113 li sp,6 - 8000011c: 0220cf3b divw t5,ra,sp - 80000120: ffd00e93 li t4,-3 - 80000124: 00300193 li gp,3 - 80000128: 0bdf1863 bne t5,t4,800001d8 - -000000008000012c : - 8000012c: 01400093 li ra,20 - 80000130: ffa00113 li sp,-6 - 80000134: 0220cf3b divw t5,ra,sp - 80000138: ffd00e93 li t4,-3 - 8000013c: 00400193 li gp,4 - 80000140: 09df1c63 bne t5,t4,800001d8 - -0000000080000144 : - 80000144: fec00093 li ra,-20 - 80000148: ffa00113 li sp,-6 - 8000014c: 0220cf3b divw t5,ra,sp - 80000150: 00300e93 li t4,3 - 80000154: 00500193 li gp,5 - 80000158: 09df1063 bne t5,t4,800001d8 - -000000008000015c : - 8000015c: 800000b7 lui ra,0x80000 - 80000160: 00100113 li sp,1 - 80000164: 0220cf3b divw t5,ra,sp - 80000168: 80000eb7 lui t4,0x80000 - 8000016c: 00600193 li gp,6 - 80000170: 07df1463 bne t5,t4,800001d8 - -0000000080000174 : - 80000174: 800000b7 lui ra,0x80000 - 80000178: fff00113 li sp,-1 - 8000017c: 0220cf3b divw t5,ra,sp - 80000180: 80000eb7 lui t4,0x80000 - 80000184: 00700193 li gp,7 - 80000188: 05df1863 bne t5,t4,800001d8 - -000000008000018c : - 8000018c: 800000b7 lui ra,0x80000 - 80000190: 00000113 li sp,0 - 80000194: 0220cf3b divw t5,ra,sp - 80000198: fff00e93 li t4,-1 - 8000019c: 00800193 li gp,8 - 800001a0: 03df1c63 bne t5,t4,800001d8 - -00000000800001a4 : - 800001a4: 00100093 li ra,1 - 800001a8: 00000113 li sp,0 - 800001ac: 0220cf3b divw t5,ra,sp - 800001b0: fff00e93 li t4,-1 - 800001b4: 00900193 li gp,9 - 800001b8: 03df1063 bne t5,t4,800001d8 - -00000000800001bc : - 800001bc: 00000093 li ra,0 - 800001c0: 00000113 li sp,0 - 800001c4: 0220cf3b divw t5,ra,sp - 800001c8: fff00e93 li t4,-1 - 800001cc: 00a00193 li gp,10 - 800001d0: 01df1463 bne t5,t4,800001d8 - 800001d4: 00301c63 bne zero,gp,800001ec - -00000000800001d8 : - 800001d8: 0ff0000f fence - 800001dc: 00018063 beqz gp,800001dc - 800001e0: 00119193 slli gp,gp,0x1 - 800001e4: 0011e193 ori gp,gp,1 - 800001e8: 00000073 ecall - -00000000800001ec : - 800001ec: 0ff0000f fence - 800001f0: 00100193 li gp,1 - 800001f4: 00000073 ecall - 800001f8: c0001073 unimp - 800001fc: 0000 unimp - 800001fe: 0000 unimp - 80000200: 0000 unimp - 80000202: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-divw.elf b/test/riscv/tests/rv64um-p-divw.elf deleted file mode 100644 index e39eb53d..00000000 Binary files a/test/riscv/tests/rv64um-p-divw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-p-mul.dump b/test/riscv/tests/rv64um-p-mul.dump deleted file mode 100644 index b546f6c9..00000000 --- a/test/riscv/tests/rv64um-p-mul.dump +++ /dev/null @@ -1,474 +0,0 @@ - -rv64um-p-mul: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 000080b7 lui ra,0x8 - 80000100: e000809b addiw ra,ra,-512 - 80000104: 06db7137 lui sp,0x6db7 - 80000108: db71011b addiw sp,sp,-585 - 8000010c: 00c11113 slli sp,sp,0xc - 80000110: db710113 addi sp,sp,-585 # 6db6db7 <_start-0x79249249> - 80000114: 00c11113 slli sp,sp,0xc - 80000118: db710113 addi sp,sp,-585 - 8000011c: 00c11113 slli sp,sp,0xc - 80000120: db710113 addi sp,sp,-585 - 80000124: 02208f33 mul t5,ra,sp - 80000128: 00001eb7 lui t4,0x1 - 8000012c: 200e8e9b addiw t4,t4,512 - 80000130: 02000193 li gp,32 - 80000134: 49df1a63 bne t5,t4,800005c8 - -0000000080000138 : - 80000138: 000080b7 lui ra,0x8 - 8000013c: fc00809b addiw ra,ra,-64 - 80000140: 06db7137 lui sp,0x6db7 - 80000144: db71011b addiw sp,sp,-585 - 80000148: 00c11113 slli sp,sp,0xc - 8000014c: db710113 addi sp,sp,-585 # 6db6db7 <_start-0x79249249> - 80000150: 00c11113 slli sp,sp,0xc - 80000154: db710113 addi sp,sp,-585 - 80000158: 00c11113 slli sp,sp,0xc - 8000015c: db710113 addi sp,sp,-585 - 80000160: 02208f33 mul t5,ra,sp - 80000164: 00001eb7 lui t4,0x1 - 80000168: 240e8e9b addiw t4,t4,576 - 8000016c: 02100193 li gp,33 - 80000170: 45df1c63 bne t5,t4,800005c8 - -0000000080000174 : - 80000174: 00000093 li ra,0 - 80000178: 00000113 li sp,0 - 8000017c: 02208f33 mul t5,ra,sp - 80000180: 00000e93 li t4,0 - 80000184: 00200193 li gp,2 - 80000188: 45df1063 bne t5,t4,800005c8 - -000000008000018c : - 8000018c: 00100093 li ra,1 - 80000190: 00100113 li sp,1 - 80000194: 02208f33 mul t5,ra,sp - 80000198: 00100e93 li t4,1 - 8000019c: 00300193 li gp,3 - 800001a0: 43df1463 bne t5,t4,800005c8 - -00000000800001a4 : - 800001a4: 00300093 li ra,3 - 800001a8: 00700113 li sp,7 - 800001ac: 02208f33 mul t5,ra,sp - 800001b0: 01500e93 li t4,21 - 800001b4: 00400193 li gp,4 - 800001b8: 41df1863 bne t5,t4,800005c8 - -00000000800001bc : - 800001bc: 00000093 li ra,0 - 800001c0: ffff8137 lui sp,0xffff8 - 800001c4: 02208f33 mul t5,ra,sp - 800001c8: 00000e93 li t4,0 - 800001cc: 00500193 li gp,5 - 800001d0: 3fdf1c63 bne t5,t4,800005c8 - -00000000800001d4 : - 800001d4: 800000b7 lui ra,0x80000 - 800001d8: 00000113 li sp,0 - 800001dc: 02208f33 mul t5,ra,sp - 800001e0: 00000e93 li t4,0 - 800001e4: 00600193 li gp,6 - 800001e8: 3fdf1063 bne t5,t4,800005c8 - -00000000800001ec : - 800001ec: 800000b7 lui ra,0x80000 - 800001f0: ffff8137 lui sp,0xffff8 - 800001f4: 02208f33 mul t5,ra,sp - 800001f8: 00100e9b addiw t4,zero,1 - 800001fc: 02ee9e93 slli t4,t4,0x2e - 80000200: 00700193 li gp,7 - 80000204: 3ddf1263 bne t5,t4,800005c8 - -0000000080000208 : - 80000208: faaab0b7 lui ra,0xfaaab - 8000020c: aab0809b addiw ra,ra,-1365 - 80000210: 00c09093 slli ra,ra,0xc - 80000214: aab08093 addi ra,ra,-1365 # fffffffffaaaaaab <_end+0xffffffff7aaa8aab> - 80000218: 00c09093 slli ra,ra,0xc - 8000021c: aab08093 addi ra,ra,-1365 - 80000220: 00c09093 slli ra,ra,0xc - 80000224: aab08093 addi ra,ra,-1365 - 80000228: 00030137 lui sp,0x30 - 8000022c: e7d1011b addiw sp,sp,-387 - 80000230: 02208f33 mul t5,ra,sp - 80000234: 00010eb7 lui t4,0x10 - 80000238: f7fe8e9b addiw t4,t4,-129 - 8000023c: 01e00193 li gp,30 - 80000240: 39df1463 bne t5,t4,800005c8 - -0000000080000244 : - 80000244: 000300b7 lui ra,0x30 - 80000248: e7d0809b addiw ra,ra,-387 - 8000024c: faaab137 lui sp,0xfaaab - 80000250: aab1011b addiw sp,sp,-1365 - 80000254: 00c11113 slli sp,sp,0xc - 80000258: aab10113 addi sp,sp,-1365 # fffffffffaaaaaab <_end+0xffffffff7aaa8aab> - 8000025c: 00c11113 slli sp,sp,0xc - 80000260: aab10113 addi sp,sp,-1365 - 80000264: 00c11113 slli sp,sp,0xc - 80000268: aab10113 addi sp,sp,-1365 - 8000026c: 02208f33 mul t5,ra,sp - 80000270: 00010eb7 lui t4,0x10 - 80000274: f7fe8e9b addiw t4,t4,-129 - 80000278: 01f00193 li gp,31 - 8000027c: 35df1663 bne t5,t4,800005c8 - -0000000080000280 : - 80000280: 00d00093 li ra,13 - 80000284: 00b00113 li sp,11 - 80000288: 022080b3 mul ra,ra,sp - 8000028c: 08f00e93 li t4,143 - 80000290: 00800193 li gp,8 - 80000294: 33d09a63 bne ra,t4,800005c8 - -0000000080000298 : - 80000298: 00e00093 li ra,14 - 8000029c: 00b00113 li sp,11 - 800002a0: 02208133 mul sp,ra,sp - 800002a4: 09a00e93 li t4,154 - 800002a8: 00900193 li gp,9 - 800002ac: 31d11e63 bne sp,t4,800005c8 - -00000000800002b0 : - 800002b0: 00d00093 li ra,13 - 800002b4: 021080b3 mul ra,ra,ra - 800002b8: 0a900e93 li t4,169 - 800002bc: 00a00193 li gp,10 - 800002c0: 31d09463 bne ra,t4,800005c8 - -00000000800002c4 : - 800002c4: 00000213 li tp,0 - 800002c8: 00d00093 li ra,13 - 800002cc: 00b00113 li sp,11 - 800002d0: 02208f33 mul t5,ra,sp - 800002d4: 000f0313 mv t1,t5 - 800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002dc: 00200293 li t0,2 - 800002e0: fe5214e3 bne tp,t0,800002c8 - 800002e4: 08f00e93 li t4,143 - 800002e8: 00b00193 li gp,11 - 800002ec: 2dd31e63 bne t1,t4,800005c8 - -00000000800002f0 : - 800002f0: 00000213 li tp,0 - 800002f4: 00e00093 li ra,14 - 800002f8: 00b00113 li sp,11 - 800002fc: 02208f33 mul t5,ra,sp - 80000300: 00000013 nop - 80000304: 000f0313 mv t1,t5 - 80000308: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000030c: 00200293 li t0,2 - 80000310: fe5212e3 bne tp,t0,800002f4 - 80000314: 09a00e93 li t4,154 - 80000318: 00c00193 li gp,12 - 8000031c: 2bd31663 bne t1,t4,800005c8 - -0000000080000320 : - 80000320: 00000213 li tp,0 - 80000324: 00f00093 li ra,15 - 80000328: 00b00113 li sp,11 - 8000032c: 02208f33 mul t5,ra,sp - 80000330: 00000013 nop - 80000334: 00000013 nop - 80000338: 000f0313 mv t1,t5 - 8000033c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000340: 00200293 li t0,2 - 80000344: fe5210e3 bne tp,t0,80000324 - 80000348: 0a500e93 li t4,165 - 8000034c: 00d00193 li gp,13 - 80000350: 27d31c63 bne t1,t4,800005c8 - -0000000080000354 : - 80000354: 00000213 li tp,0 - 80000358: 00d00093 li ra,13 - 8000035c: 00b00113 li sp,11 - 80000360: 02208f33 mul t5,ra,sp - 80000364: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000368: 00200293 li t0,2 - 8000036c: fe5216e3 bne tp,t0,80000358 - 80000370: 08f00e93 li t4,143 - 80000374: 00e00193 li gp,14 - 80000378: 25df1863 bne t5,t4,800005c8 - -000000008000037c : - 8000037c: 00000213 li tp,0 - 80000380: 00e00093 li ra,14 - 80000384: 00b00113 li sp,11 - 80000388: 00000013 nop - 8000038c: 02208f33 mul t5,ra,sp - 80000390: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000394: 00200293 li t0,2 - 80000398: fe5214e3 bne tp,t0,80000380 - 8000039c: 09a00e93 li t4,154 - 800003a0: 00f00193 li gp,15 - 800003a4: 23df1263 bne t5,t4,800005c8 - -00000000800003a8 : - 800003a8: 00000213 li tp,0 - 800003ac: 00f00093 li ra,15 - 800003b0: 00b00113 li sp,11 - 800003b4: 00000013 nop - 800003b8: 00000013 nop - 800003bc: 02208f33 mul t5,ra,sp - 800003c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003c4: 00200293 li t0,2 - 800003c8: fe5212e3 bne tp,t0,800003ac - 800003cc: 0a500e93 li t4,165 - 800003d0: 01000193 li gp,16 - 800003d4: 1fdf1a63 bne t5,t4,800005c8 - -00000000800003d8 : - 800003d8: 00000213 li tp,0 - 800003dc: 00d00093 li ra,13 - 800003e0: 00000013 nop - 800003e4: 00b00113 li sp,11 - 800003e8: 02208f33 mul t5,ra,sp - 800003ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003f0: 00200293 li t0,2 - 800003f4: fe5214e3 bne tp,t0,800003dc - 800003f8: 08f00e93 li t4,143 - 800003fc: 01100193 li gp,17 - 80000400: 1ddf1463 bne t5,t4,800005c8 - -0000000080000404 : - 80000404: 00000213 li tp,0 - 80000408: 00e00093 li ra,14 - 8000040c: 00000013 nop - 80000410: 00b00113 li sp,11 - 80000414: 00000013 nop - 80000418: 02208f33 mul t5,ra,sp - 8000041c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000420: 00200293 li t0,2 - 80000424: fe5212e3 bne tp,t0,80000408 - 80000428: 09a00e93 li t4,154 - 8000042c: 01200193 li gp,18 - 80000430: 19df1c63 bne t5,t4,800005c8 - -0000000080000434 : - 80000434: 00000213 li tp,0 - 80000438: 00f00093 li ra,15 - 8000043c: 00000013 nop - 80000440: 00000013 nop - 80000444: 00b00113 li sp,11 - 80000448: 02208f33 mul t5,ra,sp - 8000044c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000450: 00200293 li t0,2 - 80000454: fe5212e3 bne tp,t0,80000438 - 80000458: 0a500e93 li t4,165 - 8000045c: 01300193 li gp,19 - 80000460: 17df1463 bne t5,t4,800005c8 - -0000000080000464 : - 80000464: 00000213 li tp,0 - 80000468: 00b00113 li sp,11 - 8000046c: 00d00093 li ra,13 - 80000470: 02208f33 mul t5,ra,sp - 80000474: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000478: 00200293 li t0,2 - 8000047c: fe5216e3 bne tp,t0,80000468 - 80000480: 08f00e93 li t4,143 - 80000484: 01400193 li gp,20 - 80000488: 15df1063 bne t5,t4,800005c8 - -000000008000048c : - 8000048c: 00000213 li tp,0 - 80000490: 00b00113 li sp,11 - 80000494: 00e00093 li ra,14 - 80000498: 00000013 nop - 8000049c: 02208f33 mul t5,ra,sp - 800004a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004a4: 00200293 li t0,2 - 800004a8: fe5214e3 bne tp,t0,80000490 - 800004ac: 09a00e93 li t4,154 - 800004b0: 01500193 li gp,21 - 800004b4: 11df1a63 bne t5,t4,800005c8 - -00000000800004b8 : - 800004b8: 00000213 li tp,0 - 800004bc: 00b00113 li sp,11 - 800004c0: 00f00093 li ra,15 - 800004c4: 00000013 nop - 800004c8: 00000013 nop - 800004cc: 02208f33 mul t5,ra,sp - 800004d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004d4: 00200293 li t0,2 - 800004d8: fe5212e3 bne tp,t0,800004bc - 800004dc: 0a500e93 li t4,165 - 800004e0: 01600193 li gp,22 - 800004e4: 0fdf1263 bne t5,t4,800005c8 - -00000000800004e8 : - 800004e8: 00000213 li tp,0 - 800004ec: 00b00113 li sp,11 - 800004f0: 00000013 nop - 800004f4: 00d00093 li ra,13 - 800004f8: 02208f33 mul t5,ra,sp - 800004fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000500: 00200293 li t0,2 - 80000504: fe5214e3 bne tp,t0,800004ec - 80000508: 08f00e93 li t4,143 - 8000050c: 01700193 li gp,23 - 80000510: 0bdf1c63 bne t5,t4,800005c8 - -0000000080000514 : - 80000514: 00000213 li tp,0 - 80000518: 00b00113 li sp,11 - 8000051c: 00000013 nop - 80000520: 00e00093 li ra,14 - 80000524: 00000013 nop - 80000528: 02208f33 mul t5,ra,sp - 8000052c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000530: 00200293 li t0,2 - 80000534: fe5212e3 bne tp,t0,80000518 - 80000538: 09a00e93 li t4,154 - 8000053c: 01800193 li gp,24 - 80000540: 09df1463 bne t5,t4,800005c8 - -0000000080000544 : - 80000544: 00000213 li tp,0 - 80000548: 00b00113 li sp,11 - 8000054c: 00000013 nop - 80000550: 00000013 nop - 80000554: 00f00093 li ra,15 - 80000558: 02208f33 mul t5,ra,sp - 8000055c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000560: 00200293 li t0,2 - 80000564: fe5212e3 bne tp,t0,80000548 - 80000568: 0a500e93 li t4,165 - 8000056c: 01900193 li gp,25 - 80000570: 05df1c63 bne t5,t4,800005c8 - -0000000080000574 : - 80000574: 01f00093 li ra,31 - 80000578: 02100133 mul sp,zero,ra - 8000057c: 00000e93 li t4,0 - 80000580: 01a00193 li gp,26 - 80000584: 05d11263 bne sp,t4,800005c8 - -0000000080000588 : - 80000588: 02000093 li ra,32 - 8000058c: 02008133 mul sp,ra,zero - 80000590: 00000e93 li t4,0 - 80000594: 01b00193 li gp,27 - 80000598: 03d11863 bne sp,t4,800005c8 - -000000008000059c : - 8000059c: 020000b3 mul ra,zero,zero - 800005a0: 00000e93 li t4,0 - 800005a4: 01c00193 li gp,28 - 800005a8: 03d09063 bne ra,t4,800005c8 - -00000000800005ac : - 800005ac: 02100093 li ra,33 - 800005b0: 02200113 li sp,34 - 800005b4: 02208033 mul zero,ra,sp - 800005b8: 00000e93 li t4,0 - 800005bc: 01d00193 li gp,29 - 800005c0: 01d01463 bne zero,t4,800005c8 - 800005c4: 00301c63 bne zero,gp,800005dc - -00000000800005c8 : - 800005c8: 0ff0000f fence - 800005cc: 00018063 beqz gp,800005cc - 800005d0: 00119193 slli gp,gp,0x1 - 800005d4: 0011e193 ori gp,gp,1 - 800005d8: 00000073 ecall - -00000000800005dc : - 800005dc: 0ff0000f fence - 800005e0: 00100193 li gp,1 - 800005e4: 00000073 ecall - 800005e8: c0001073 unimp - 800005ec: 0000 unimp - 800005ee: 0000 unimp - 800005f0: 0000 unimp - 800005f2: 0000 unimp - 800005f4: 0000 unimp - 800005f6: 0000 unimp - 800005f8: 0000 unimp - 800005fa: 0000 unimp - 800005fc: 0000 unimp - 800005fe: 0000 unimp - 80000600: 0000 unimp - 80000602: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-mul.elf b/test/riscv/tests/rv64um-p-mul.elf deleted file mode 100644 index 4983abe5..00000000 Binary files a/test/riscv/tests/rv64um-p-mul.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-p-mulh.dump b/test/riscv/tests/rv64um-p-mulh.dump deleted file mode 100644 index 59475e6d..00000000 --- a/test/riscv/tests/rv64um-p-mulh.dump +++ /dev/null @@ -1,456 +0,0 @@ - -rv64um-p-mulh: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00000093 li ra,0 - 80000100: 00000113 li sp,0 - 80000104: 02209f33 mulh t5,ra,sp - 80000108: 00000e93 li t4,0 - 8000010c: 00200193 li gp,2 - 80000110: 47df1063 bne t5,t4,80000570 - -0000000080000114 : - 80000114: 00100093 li ra,1 - 80000118: 00100113 li sp,1 - 8000011c: 02209f33 mulh t5,ra,sp - 80000120: 00000e93 li t4,0 - 80000124: 00300193 li gp,3 - 80000128: 45df1463 bne t5,t4,80000570 - -000000008000012c : - 8000012c: 00300093 li ra,3 - 80000130: 00700113 li sp,7 - 80000134: 02209f33 mulh t5,ra,sp - 80000138: 00000e93 li t4,0 - 8000013c: 00400193 li gp,4 - 80000140: 43df1863 bne t5,t4,80000570 - -0000000080000144 : - 80000144: 00000093 li ra,0 - 80000148: ffff8137 lui sp,0xffff8 - 8000014c: 02209f33 mulh t5,ra,sp - 80000150: 00000e93 li t4,0 - 80000154: 00500193 li gp,5 - 80000158: 41df1c63 bne t5,t4,80000570 - -000000008000015c : - 8000015c: 800000b7 lui ra,0x80000 - 80000160: 00000113 li sp,0 - 80000164: 02209f33 mulh t5,ra,sp - 80000168: 00000e93 li t4,0 - 8000016c: 00600193 li gp,6 - 80000170: 41df1063 bne t5,t4,80000570 - -0000000080000174 : - 80000174: 800000b7 lui ra,0x80000 - 80000178: ffff8137 lui sp,0xffff8 - 8000017c: 02209f33 mulh t5,ra,sp - 80000180: 00000e93 li t4,0 - 80000184: 00700193 li gp,7 - 80000188: 3fdf1463 bne t5,t4,80000570 - -000000008000018c : - 8000018c: 00d0009b addiw ra,zero,13 - 80000190: 02009093 slli ra,ra,0x20 - 80000194: 00b0011b addiw sp,zero,11 - 80000198: 02011113 slli sp,sp,0x20 - 8000019c: 022090b3 mulh ra,ra,sp - 800001a0: 08f00e93 li t4,143 - 800001a4: 00800193 li gp,8 - 800001a8: 3dd09463 bne ra,t4,80000570 - -00000000800001ac : - 800001ac: 0070009b addiw ra,zero,7 - 800001b0: 02109093 slli ra,ra,0x21 - 800001b4: 00b0011b addiw sp,zero,11 - 800001b8: 02011113 slli sp,sp,0x20 - 800001bc: 02209133 mulh sp,ra,sp - 800001c0: 09a00e93 li t4,154 - 800001c4: 00900193 li gp,9 - 800001c8: 3bd11463 bne sp,t4,80000570 - -00000000800001cc : - 800001cc: 00d0009b addiw ra,zero,13 - 800001d0: 02009093 slli ra,ra,0x20 - 800001d4: 021090b3 mulh ra,ra,ra - 800001d8: 0a900e93 li t4,169 - 800001dc: 00a00193 li gp,10 - 800001e0: 39d09863 bne ra,t4,80000570 - -00000000800001e4 : - 800001e4: 00000213 li tp,0 - 800001e8: 00d0009b addiw ra,zero,13 - 800001ec: 02009093 slli ra,ra,0x20 - 800001f0: 00b0011b addiw sp,zero,11 - 800001f4: 02011113 slli sp,sp,0x20 - 800001f8: 02209f33 mulh t5,ra,sp - 800001fc: 000f0313 mv t1,t5 - 80000200: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000204: 00200293 li t0,2 - 80000208: fe5210e3 bne tp,t0,800001e8 - 8000020c: 08f00e93 li t4,143 - 80000210: 00b00193 li gp,11 - 80000214: 35d31e63 bne t1,t4,80000570 - -0000000080000218 : - 80000218: 00000213 li tp,0 - 8000021c: 0070009b addiw ra,zero,7 - 80000220: 02109093 slli ra,ra,0x21 - 80000224: 00b0011b addiw sp,zero,11 - 80000228: 02011113 slli sp,sp,0x20 - 8000022c: 02209f33 mulh t5,ra,sp - 80000230: 00000013 nop - 80000234: 000f0313 mv t1,t5 - 80000238: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000023c: 00200293 li t0,2 - 80000240: fc521ee3 bne tp,t0,8000021c - 80000244: 09a00e93 li t4,154 - 80000248: 00c00193 li gp,12 - 8000024c: 33d31263 bne t1,t4,80000570 - -0000000080000250 : - 80000250: 00000213 li tp,0 - 80000254: 00f0009b addiw ra,zero,15 - 80000258: 02009093 slli ra,ra,0x20 - 8000025c: 00b0011b addiw sp,zero,11 - 80000260: 02011113 slli sp,sp,0x20 - 80000264: 02209f33 mulh t5,ra,sp - 80000268: 00000013 nop - 8000026c: 00000013 nop - 80000270: 000f0313 mv t1,t5 - 80000274: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000278: 00200293 li t0,2 - 8000027c: fc521ce3 bne tp,t0,80000254 - 80000280: 0a500e93 li t4,165 - 80000284: 00d00193 li gp,13 - 80000288: 2fd31463 bne t1,t4,80000570 - -000000008000028c : - 8000028c: 00000213 li tp,0 - 80000290: 00d0009b addiw ra,zero,13 - 80000294: 02009093 slli ra,ra,0x20 - 80000298: 00b0011b addiw sp,zero,11 - 8000029c: 02011113 slli sp,sp,0x20 - 800002a0: 02209f33 mulh t5,ra,sp - 800002a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002a8: 00200293 li t0,2 - 800002ac: fe5212e3 bne tp,t0,80000290 - 800002b0: 08f00e93 li t4,143 - 800002b4: 00e00193 li gp,14 - 800002b8: 2bdf1c63 bne t5,t4,80000570 - -00000000800002bc : - 800002bc: 00000213 li tp,0 - 800002c0: 0070009b addiw ra,zero,7 - 800002c4: 02109093 slli ra,ra,0x21 - 800002c8: 00b0011b addiw sp,zero,11 - 800002cc: 02011113 slli sp,sp,0x20 - 800002d0: 00000013 nop - 800002d4: 02209f33 mulh t5,ra,sp - 800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002dc: 00200293 li t0,2 - 800002e0: fe5210e3 bne tp,t0,800002c0 - 800002e4: 09a00e93 li t4,154 - 800002e8: 00f00193 li gp,15 - 800002ec: 29df1263 bne t5,t4,80000570 - -00000000800002f0 : - 800002f0: 00000213 li tp,0 - 800002f4: 00f0009b addiw ra,zero,15 - 800002f8: 02009093 slli ra,ra,0x20 - 800002fc: 00b0011b addiw sp,zero,11 - 80000300: 02011113 slli sp,sp,0x20 - 80000304: 00000013 nop - 80000308: 00000013 nop - 8000030c: 02209f33 mulh t5,ra,sp - 80000310: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000314: 00200293 li t0,2 - 80000318: fc521ee3 bne tp,t0,800002f4 - 8000031c: 0a500e93 li t4,165 - 80000320: 01000193 li gp,16 - 80000324: 25df1663 bne t5,t4,80000570 - -0000000080000328 : - 80000328: 00000213 li tp,0 - 8000032c: 00d0009b addiw ra,zero,13 - 80000330: 02009093 slli ra,ra,0x20 - 80000334: 00000013 nop - 80000338: 00b0011b addiw sp,zero,11 - 8000033c: 02011113 slli sp,sp,0x20 - 80000340: 02209f33 mulh t5,ra,sp - 80000344: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000348: 00200293 li t0,2 - 8000034c: fe5210e3 bne tp,t0,8000032c - 80000350: 08f00e93 li t4,143 - 80000354: 01100193 li gp,17 - 80000358: 21df1c63 bne t5,t4,80000570 - -000000008000035c : - 8000035c: 00000213 li tp,0 - 80000360: 0070009b addiw ra,zero,7 - 80000364: 02109093 slli ra,ra,0x21 - 80000368: 00000013 nop - 8000036c: 00b0011b addiw sp,zero,11 - 80000370: 02011113 slli sp,sp,0x20 - 80000374: 00000013 nop - 80000378: 02209f33 mulh t5,ra,sp - 8000037c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000380: 00200293 li t0,2 - 80000384: fc521ee3 bne tp,t0,80000360 - 80000388: 09a00e93 li t4,154 - 8000038c: 01200193 li gp,18 - 80000390: 1fdf1063 bne t5,t4,80000570 - -0000000080000394 : - 80000394: 00000213 li tp,0 - 80000398: 00f0009b addiw ra,zero,15 - 8000039c: 02009093 slli ra,ra,0x20 - 800003a0: 00000013 nop - 800003a4: 00000013 nop - 800003a8: 00b0011b addiw sp,zero,11 - 800003ac: 02011113 slli sp,sp,0x20 - 800003b0: 02209f33 mulh t5,ra,sp - 800003b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003b8: 00200293 li t0,2 - 800003bc: fc521ee3 bne tp,t0,80000398 - 800003c0: 0a500e93 li t4,165 - 800003c4: 01300193 li gp,19 - 800003c8: 1bdf1463 bne t5,t4,80000570 - -00000000800003cc : - 800003cc: 00000213 li tp,0 - 800003d0: 00b0011b addiw sp,zero,11 - 800003d4: 02011113 slli sp,sp,0x20 - 800003d8: 00d0009b addiw ra,zero,13 - 800003dc: 02009093 slli ra,ra,0x20 - 800003e0: 02209f33 mulh t5,ra,sp - 800003e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003e8: 00200293 li t0,2 - 800003ec: fe5212e3 bne tp,t0,800003d0 - 800003f0: 08f00e93 li t4,143 - 800003f4: 01400193 li gp,20 - 800003f8: 17df1c63 bne t5,t4,80000570 - -00000000800003fc : - 800003fc: 00000213 li tp,0 - 80000400: 00b0011b addiw sp,zero,11 - 80000404: 02011113 slli sp,sp,0x20 - 80000408: 0070009b addiw ra,zero,7 - 8000040c: 02109093 slli ra,ra,0x21 - 80000410: 00000013 nop - 80000414: 02209f33 mulh t5,ra,sp - 80000418: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000041c: 00200293 li t0,2 - 80000420: fe5210e3 bne tp,t0,80000400 - 80000424: 09a00e93 li t4,154 - 80000428: 01500193 li gp,21 - 8000042c: 15df1263 bne t5,t4,80000570 - -0000000080000430 : - 80000430: 00000213 li tp,0 - 80000434: 00b0011b addiw sp,zero,11 - 80000438: 02011113 slli sp,sp,0x20 - 8000043c: 00f0009b addiw ra,zero,15 - 80000440: 02009093 slli ra,ra,0x20 - 80000444: 00000013 nop - 80000448: 00000013 nop - 8000044c: 02209f33 mulh t5,ra,sp - 80000450: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000454: 00200293 li t0,2 - 80000458: fc521ee3 bne tp,t0,80000434 - 8000045c: 0a500e93 li t4,165 - 80000460: 01600193 li gp,22 - 80000464: 11df1663 bne t5,t4,80000570 - -0000000080000468 : - 80000468: 00000213 li tp,0 - 8000046c: 00b0011b addiw sp,zero,11 - 80000470: 02011113 slli sp,sp,0x20 - 80000474: 00000013 nop - 80000478: 00d0009b addiw ra,zero,13 - 8000047c: 02009093 slli ra,ra,0x20 - 80000480: 02209f33 mulh t5,ra,sp - 80000484: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000488: 00200293 li t0,2 - 8000048c: fe5210e3 bne tp,t0,8000046c - 80000490: 08f00e93 li t4,143 - 80000494: 01700193 li gp,23 - 80000498: 0ddf1c63 bne t5,t4,80000570 - -000000008000049c : - 8000049c: 00000213 li tp,0 - 800004a0: 00b0011b addiw sp,zero,11 - 800004a4: 02011113 slli sp,sp,0x20 - 800004a8: 00000013 nop - 800004ac: 0070009b addiw ra,zero,7 - 800004b0: 02109093 slli ra,ra,0x21 - 800004b4: 00000013 nop - 800004b8: 02209f33 mulh t5,ra,sp - 800004bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004c0: 00200293 li t0,2 - 800004c4: fc521ee3 bne tp,t0,800004a0 - 800004c8: 09a00e93 li t4,154 - 800004cc: 01800193 li gp,24 - 800004d0: 0bdf1063 bne t5,t4,80000570 - -00000000800004d4 : - 800004d4: 00000213 li tp,0 - 800004d8: 00b0011b addiw sp,zero,11 - 800004dc: 02011113 slli sp,sp,0x20 - 800004e0: 00000013 nop - 800004e4: 00000013 nop - 800004e8: 00f0009b addiw ra,zero,15 - 800004ec: 02009093 slli ra,ra,0x20 - 800004f0: 02209f33 mulh t5,ra,sp - 800004f4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004f8: 00200293 li t0,2 - 800004fc: fc521ee3 bne tp,t0,800004d8 - 80000500: 0a500e93 li t4,165 - 80000504: 01900193 li gp,25 - 80000508: 07df1463 bne t5,t4,80000570 - -000000008000050c : - 8000050c: 01f0009b addiw ra,zero,31 - 80000510: 02009093 slli ra,ra,0x20 - 80000514: 02101133 mulh sp,zero,ra - 80000518: 00000e93 li t4,0 - 8000051c: 01a00193 li gp,26 - 80000520: 05d11863 bne sp,t4,80000570 - -0000000080000524 : - 80000524: 0010009b addiw ra,zero,1 - 80000528: 02509093 slli ra,ra,0x25 - 8000052c: 02009133 mulh sp,ra,zero - 80000530: 00000e93 li t4,0 - 80000534: 01b00193 li gp,27 - 80000538: 03d11c63 bne sp,t4,80000570 - -000000008000053c : - 8000053c: 020010b3 mulh ra,zero,zero - 80000540: 00000e93 li t4,0 - 80000544: 01c00193 li gp,28 - 80000548: 03d09463 bne ra,t4,80000570 - -000000008000054c : - 8000054c: 0210009b addiw ra,zero,33 - 80000550: 02009093 slli ra,ra,0x20 - 80000554: 0110011b addiw sp,zero,17 - 80000558: 02111113 slli sp,sp,0x21 - 8000055c: 02209033 mulh zero,ra,sp - 80000560: 00000e93 li t4,0 - 80000564: 01d00193 li gp,29 - 80000568: 01d01463 bne zero,t4,80000570 - 8000056c: 00301c63 bne zero,gp,80000584 - -0000000080000570 : - 80000570: 0ff0000f fence - 80000574: 00018063 beqz gp,80000574 - 80000578: 00119193 slli gp,gp,0x1 - 8000057c: 0011e193 ori gp,gp,1 - 80000580: 00000073 ecall - -0000000080000584 : - 80000584: 0ff0000f fence - 80000588: 00100193 li gp,1 - 8000058c: 00000073 ecall - 80000590: c0001073 unimp - 80000594: 0000 unimp - 80000596: 0000 unimp - 80000598: 0000 unimp - 8000059a: 0000 unimp - 8000059c: 0000 unimp - 8000059e: 0000 unimp - 800005a0: 0000 unimp - 800005a2: 0000 unimp - 800005a4: 0000 unimp - 800005a6: 0000 unimp - 800005a8: 0000 unimp - 800005aa: 0000 unimp - 800005ac: 0000 unimp - 800005ae: 0000 unimp - 800005b0: 0000 unimp - 800005b2: 0000 unimp - 800005b4: 0000 unimp - 800005b6: 0000 unimp - 800005b8: 0000 unimp - 800005ba: 0000 unimp - 800005bc: 0000 unimp - 800005be: 0000 unimp - 800005c0: 0000 unimp - 800005c2: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-mulh.elf b/test/riscv/tests/rv64um-p-mulh.elf deleted file mode 100644 index 4118cecd..00000000 Binary files a/test/riscv/tests/rv64um-p-mulh.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-p-mulhsu.dump b/test/riscv/tests/rv64um-p-mulhsu.dump deleted file mode 100644 index 56d5b6da..00000000 --- a/test/riscv/tests/rv64um-p-mulhsu.dump +++ /dev/null @@ -1,456 +0,0 @@ - -rv64um-p-mulhsu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00000093 li ra,0 - 80000100: 00000113 li sp,0 - 80000104: 0220af33 mulhsu t5,ra,sp - 80000108: 00000e93 li t4,0 - 8000010c: 00200193 li gp,2 - 80000110: 47df1063 bne t5,t4,80000570 - -0000000080000114 : - 80000114: 00100093 li ra,1 - 80000118: 00100113 li sp,1 - 8000011c: 0220af33 mulhsu t5,ra,sp - 80000120: 00000e93 li t4,0 - 80000124: 00300193 li gp,3 - 80000128: 45df1463 bne t5,t4,80000570 - -000000008000012c : - 8000012c: 00300093 li ra,3 - 80000130: 00700113 li sp,7 - 80000134: 0220af33 mulhsu t5,ra,sp - 80000138: 00000e93 li t4,0 - 8000013c: 00400193 li gp,4 - 80000140: 43df1863 bne t5,t4,80000570 - -0000000080000144 : - 80000144: 00000093 li ra,0 - 80000148: ffff8137 lui sp,0xffff8 - 8000014c: 0220af33 mulhsu t5,ra,sp - 80000150: 00000e93 li t4,0 - 80000154: 00500193 li gp,5 - 80000158: 41df1c63 bne t5,t4,80000570 - -000000008000015c : - 8000015c: 800000b7 lui ra,0x80000 - 80000160: 00000113 li sp,0 - 80000164: 0220af33 mulhsu t5,ra,sp - 80000168: 00000e93 li t4,0 - 8000016c: 00600193 li gp,6 - 80000170: 41df1063 bne t5,t4,80000570 - -0000000080000174 : - 80000174: 800000b7 lui ra,0x80000 - 80000178: ffff8137 lui sp,0xffff8 - 8000017c: 0220af33 mulhsu t5,ra,sp - 80000180: 80000eb7 lui t4,0x80000 - 80000184: 00700193 li gp,7 - 80000188: 3fdf1463 bne t5,t4,80000570 - -000000008000018c : - 8000018c: 00d0009b addiw ra,zero,13 - 80000190: 02009093 slli ra,ra,0x20 - 80000194: 00b0011b addiw sp,zero,11 - 80000198: 02011113 slli sp,sp,0x20 - 8000019c: 0220a0b3 mulhsu ra,ra,sp - 800001a0: 08f00e93 li t4,143 - 800001a4: 00800193 li gp,8 - 800001a8: 3dd09463 bne ra,t4,80000570 - -00000000800001ac : - 800001ac: 0070009b addiw ra,zero,7 - 800001b0: 02109093 slli ra,ra,0x21 - 800001b4: 00b0011b addiw sp,zero,11 - 800001b8: 02011113 slli sp,sp,0x20 - 800001bc: 0220a133 mulhsu sp,ra,sp - 800001c0: 09a00e93 li t4,154 - 800001c4: 00900193 li gp,9 - 800001c8: 3bd11463 bne sp,t4,80000570 - -00000000800001cc : - 800001cc: 00d0009b addiw ra,zero,13 - 800001d0: 02009093 slli ra,ra,0x20 - 800001d4: 0210a0b3 mulhsu ra,ra,ra - 800001d8: 0a900e93 li t4,169 - 800001dc: 00a00193 li gp,10 - 800001e0: 39d09863 bne ra,t4,80000570 - -00000000800001e4 : - 800001e4: 00000213 li tp,0 - 800001e8: 00d0009b addiw ra,zero,13 - 800001ec: 02009093 slli ra,ra,0x20 - 800001f0: 00b0011b addiw sp,zero,11 - 800001f4: 02011113 slli sp,sp,0x20 - 800001f8: 0220af33 mulhsu t5,ra,sp - 800001fc: 000f0313 mv t1,t5 - 80000200: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000204: 00200293 li t0,2 - 80000208: fe5210e3 bne tp,t0,800001e8 - 8000020c: 08f00e93 li t4,143 - 80000210: 00b00193 li gp,11 - 80000214: 35d31e63 bne t1,t4,80000570 - -0000000080000218 : - 80000218: 00000213 li tp,0 - 8000021c: 0070009b addiw ra,zero,7 - 80000220: 02109093 slli ra,ra,0x21 - 80000224: 00b0011b addiw sp,zero,11 - 80000228: 02011113 slli sp,sp,0x20 - 8000022c: 0220af33 mulhsu t5,ra,sp - 80000230: 00000013 nop - 80000234: 000f0313 mv t1,t5 - 80000238: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000023c: 00200293 li t0,2 - 80000240: fc521ee3 bne tp,t0,8000021c - 80000244: 09a00e93 li t4,154 - 80000248: 00c00193 li gp,12 - 8000024c: 33d31263 bne t1,t4,80000570 - -0000000080000250 : - 80000250: 00000213 li tp,0 - 80000254: 00f0009b addiw ra,zero,15 - 80000258: 02009093 slli ra,ra,0x20 - 8000025c: 00b0011b addiw sp,zero,11 - 80000260: 02011113 slli sp,sp,0x20 - 80000264: 0220af33 mulhsu t5,ra,sp - 80000268: 00000013 nop - 8000026c: 00000013 nop - 80000270: 000f0313 mv t1,t5 - 80000274: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000278: 00200293 li t0,2 - 8000027c: fc521ce3 bne tp,t0,80000254 - 80000280: 0a500e93 li t4,165 - 80000284: 00d00193 li gp,13 - 80000288: 2fd31463 bne t1,t4,80000570 - -000000008000028c : - 8000028c: 00000213 li tp,0 - 80000290: 00d0009b addiw ra,zero,13 - 80000294: 02009093 slli ra,ra,0x20 - 80000298: 00b0011b addiw sp,zero,11 - 8000029c: 02011113 slli sp,sp,0x20 - 800002a0: 0220af33 mulhsu t5,ra,sp - 800002a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002a8: 00200293 li t0,2 - 800002ac: fe5212e3 bne tp,t0,80000290 - 800002b0: 08f00e93 li t4,143 - 800002b4: 00e00193 li gp,14 - 800002b8: 2bdf1c63 bne t5,t4,80000570 - -00000000800002bc : - 800002bc: 00000213 li tp,0 - 800002c0: 0070009b addiw ra,zero,7 - 800002c4: 02109093 slli ra,ra,0x21 - 800002c8: 00b0011b addiw sp,zero,11 - 800002cc: 02011113 slli sp,sp,0x20 - 800002d0: 00000013 nop - 800002d4: 0220af33 mulhsu t5,ra,sp - 800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002dc: 00200293 li t0,2 - 800002e0: fe5210e3 bne tp,t0,800002c0 - 800002e4: 09a00e93 li t4,154 - 800002e8: 00f00193 li gp,15 - 800002ec: 29df1263 bne t5,t4,80000570 - -00000000800002f0 : - 800002f0: 00000213 li tp,0 - 800002f4: 00f0009b addiw ra,zero,15 - 800002f8: 02009093 slli ra,ra,0x20 - 800002fc: 00b0011b addiw sp,zero,11 - 80000300: 02011113 slli sp,sp,0x20 - 80000304: 00000013 nop - 80000308: 00000013 nop - 8000030c: 0220af33 mulhsu t5,ra,sp - 80000310: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000314: 00200293 li t0,2 - 80000318: fc521ee3 bne tp,t0,800002f4 - 8000031c: 0a500e93 li t4,165 - 80000320: 01000193 li gp,16 - 80000324: 25df1663 bne t5,t4,80000570 - -0000000080000328 : - 80000328: 00000213 li tp,0 - 8000032c: 00d0009b addiw ra,zero,13 - 80000330: 02009093 slli ra,ra,0x20 - 80000334: 00000013 nop - 80000338: 00b0011b addiw sp,zero,11 - 8000033c: 02011113 slli sp,sp,0x20 - 80000340: 0220af33 mulhsu t5,ra,sp - 80000344: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000348: 00200293 li t0,2 - 8000034c: fe5210e3 bne tp,t0,8000032c - 80000350: 08f00e93 li t4,143 - 80000354: 01100193 li gp,17 - 80000358: 21df1c63 bne t5,t4,80000570 - -000000008000035c : - 8000035c: 00000213 li tp,0 - 80000360: 0070009b addiw ra,zero,7 - 80000364: 02109093 slli ra,ra,0x21 - 80000368: 00000013 nop - 8000036c: 00b0011b addiw sp,zero,11 - 80000370: 02011113 slli sp,sp,0x20 - 80000374: 00000013 nop - 80000378: 0220af33 mulhsu t5,ra,sp - 8000037c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000380: 00200293 li t0,2 - 80000384: fc521ee3 bne tp,t0,80000360 - 80000388: 09a00e93 li t4,154 - 8000038c: 01200193 li gp,18 - 80000390: 1fdf1063 bne t5,t4,80000570 - -0000000080000394 : - 80000394: 00000213 li tp,0 - 80000398: 00f0009b addiw ra,zero,15 - 8000039c: 02009093 slli ra,ra,0x20 - 800003a0: 00000013 nop - 800003a4: 00000013 nop - 800003a8: 00b0011b addiw sp,zero,11 - 800003ac: 02011113 slli sp,sp,0x20 - 800003b0: 0220af33 mulhsu t5,ra,sp - 800003b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003b8: 00200293 li t0,2 - 800003bc: fc521ee3 bne tp,t0,80000398 - 800003c0: 0a500e93 li t4,165 - 800003c4: 01300193 li gp,19 - 800003c8: 1bdf1463 bne t5,t4,80000570 - -00000000800003cc : - 800003cc: 00000213 li tp,0 - 800003d0: 00b0011b addiw sp,zero,11 - 800003d4: 02011113 slli sp,sp,0x20 - 800003d8: 00d0009b addiw ra,zero,13 - 800003dc: 02009093 slli ra,ra,0x20 - 800003e0: 0220af33 mulhsu t5,ra,sp - 800003e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003e8: 00200293 li t0,2 - 800003ec: fe5212e3 bne tp,t0,800003d0 - 800003f0: 08f00e93 li t4,143 - 800003f4: 01400193 li gp,20 - 800003f8: 17df1c63 bne t5,t4,80000570 - -00000000800003fc : - 800003fc: 00000213 li tp,0 - 80000400: 00b0011b addiw sp,zero,11 - 80000404: 02011113 slli sp,sp,0x20 - 80000408: 0070009b addiw ra,zero,7 - 8000040c: 02109093 slli ra,ra,0x21 - 80000410: 00000013 nop - 80000414: 0220af33 mulhsu t5,ra,sp - 80000418: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000041c: 00200293 li t0,2 - 80000420: fe5210e3 bne tp,t0,80000400 - 80000424: 09a00e93 li t4,154 - 80000428: 01500193 li gp,21 - 8000042c: 15df1263 bne t5,t4,80000570 - -0000000080000430 : - 80000430: 00000213 li tp,0 - 80000434: 00b0011b addiw sp,zero,11 - 80000438: 02011113 slli sp,sp,0x20 - 8000043c: 00f0009b addiw ra,zero,15 - 80000440: 02009093 slli ra,ra,0x20 - 80000444: 00000013 nop - 80000448: 00000013 nop - 8000044c: 0220af33 mulhsu t5,ra,sp - 80000450: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000454: 00200293 li t0,2 - 80000458: fc521ee3 bne tp,t0,80000434 - 8000045c: 0a500e93 li t4,165 - 80000460: 01600193 li gp,22 - 80000464: 11df1663 bne t5,t4,80000570 - -0000000080000468 : - 80000468: 00000213 li tp,0 - 8000046c: 00b0011b addiw sp,zero,11 - 80000470: 02011113 slli sp,sp,0x20 - 80000474: 00000013 nop - 80000478: 00d0009b addiw ra,zero,13 - 8000047c: 02009093 slli ra,ra,0x20 - 80000480: 0220af33 mulhsu t5,ra,sp - 80000484: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000488: 00200293 li t0,2 - 8000048c: fe5210e3 bne tp,t0,8000046c - 80000490: 08f00e93 li t4,143 - 80000494: 01700193 li gp,23 - 80000498: 0ddf1c63 bne t5,t4,80000570 - -000000008000049c : - 8000049c: 00000213 li tp,0 - 800004a0: 00b0011b addiw sp,zero,11 - 800004a4: 02011113 slli sp,sp,0x20 - 800004a8: 00000013 nop - 800004ac: 0070009b addiw ra,zero,7 - 800004b0: 02109093 slli ra,ra,0x21 - 800004b4: 00000013 nop - 800004b8: 0220af33 mulhsu t5,ra,sp - 800004bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004c0: 00200293 li t0,2 - 800004c4: fc521ee3 bne tp,t0,800004a0 - 800004c8: 09a00e93 li t4,154 - 800004cc: 01800193 li gp,24 - 800004d0: 0bdf1063 bne t5,t4,80000570 - -00000000800004d4 : - 800004d4: 00000213 li tp,0 - 800004d8: 00b0011b addiw sp,zero,11 - 800004dc: 02011113 slli sp,sp,0x20 - 800004e0: 00000013 nop - 800004e4: 00000013 nop - 800004e8: 00f0009b addiw ra,zero,15 - 800004ec: 02009093 slli ra,ra,0x20 - 800004f0: 0220af33 mulhsu t5,ra,sp - 800004f4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004f8: 00200293 li t0,2 - 800004fc: fc521ee3 bne tp,t0,800004d8 - 80000500: 0a500e93 li t4,165 - 80000504: 01900193 li gp,25 - 80000508: 07df1463 bne t5,t4,80000570 - -000000008000050c : - 8000050c: 01f0009b addiw ra,zero,31 - 80000510: 02009093 slli ra,ra,0x20 - 80000514: 02102133 mulhsu sp,zero,ra - 80000518: 00000e93 li t4,0 - 8000051c: 01a00193 li gp,26 - 80000520: 05d11863 bne sp,t4,80000570 - -0000000080000524 : - 80000524: 0010009b addiw ra,zero,1 - 80000528: 02509093 slli ra,ra,0x25 - 8000052c: 0200a133 mulhsu sp,ra,zero - 80000530: 00000e93 li t4,0 - 80000534: 01b00193 li gp,27 - 80000538: 03d11c63 bne sp,t4,80000570 - -000000008000053c : - 8000053c: 020020b3 mulhsu ra,zero,zero - 80000540: 00000e93 li t4,0 - 80000544: 01c00193 li gp,28 - 80000548: 03d09463 bne ra,t4,80000570 - -000000008000054c : - 8000054c: 0210009b addiw ra,zero,33 - 80000550: 02009093 slli ra,ra,0x20 - 80000554: 0110011b addiw sp,zero,17 - 80000558: 02111113 slli sp,sp,0x21 - 8000055c: 0220a033 mulhsu zero,ra,sp - 80000560: 00000e93 li t4,0 - 80000564: 01d00193 li gp,29 - 80000568: 01d01463 bne zero,t4,80000570 - 8000056c: 00301c63 bne zero,gp,80000584 - -0000000080000570 : - 80000570: 0ff0000f fence - 80000574: 00018063 beqz gp,80000574 - 80000578: 00119193 slli gp,gp,0x1 - 8000057c: 0011e193 ori gp,gp,1 - 80000580: 00000073 ecall - -0000000080000584 : - 80000584: 0ff0000f fence - 80000588: 00100193 li gp,1 - 8000058c: 00000073 ecall - 80000590: c0001073 unimp - 80000594: 0000 unimp - 80000596: 0000 unimp - 80000598: 0000 unimp - 8000059a: 0000 unimp - 8000059c: 0000 unimp - 8000059e: 0000 unimp - 800005a0: 0000 unimp - 800005a2: 0000 unimp - 800005a4: 0000 unimp - 800005a6: 0000 unimp - 800005a8: 0000 unimp - 800005aa: 0000 unimp - 800005ac: 0000 unimp - 800005ae: 0000 unimp - 800005b0: 0000 unimp - 800005b2: 0000 unimp - 800005b4: 0000 unimp - 800005b6: 0000 unimp - 800005b8: 0000 unimp - 800005ba: 0000 unimp - 800005bc: 0000 unimp - 800005be: 0000 unimp - 800005c0: 0000 unimp - 800005c2: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-mulhsu.elf b/test/riscv/tests/rv64um-p-mulhsu.elf deleted file mode 100644 index 37979feb..00000000 Binary files a/test/riscv/tests/rv64um-p-mulhsu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-p-mulhu.dump b/test/riscv/tests/rv64um-p-mulhu.dump deleted file mode 100644 index 82860e14..00000000 --- a/test/riscv/tests/rv64um-p-mulhu.dump +++ /dev/null @@ -1,492 +0,0 @@ - -rv64um-p-mulhu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00000093 li ra,0 - 80000100: 00000113 li sp,0 - 80000104: 0220bf33 mulhu t5,ra,sp - 80000108: 00000e93 li t4,0 - 8000010c: 00200193 li gp,2 - 80000110: 4fdf1063 bne t5,t4,800005f0 - -0000000080000114 : - 80000114: 00100093 li ra,1 - 80000118: 00100113 li sp,1 - 8000011c: 0220bf33 mulhu t5,ra,sp - 80000120: 00000e93 li t4,0 - 80000124: 00300193 li gp,3 - 80000128: 4ddf1463 bne t5,t4,800005f0 - -000000008000012c : - 8000012c: 00300093 li ra,3 - 80000130: 00700113 li sp,7 - 80000134: 0220bf33 mulhu t5,ra,sp - 80000138: 00000e93 li t4,0 - 8000013c: 00400193 li gp,4 - 80000140: 4bdf1863 bne t5,t4,800005f0 - -0000000080000144 : - 80000144: 00000093 li ra,0 - 80000148: ffff8137 lui sp,0xffff8 - 8000014c: 0220bf33 mulhu t5,ra,sp - 80000150: 00000e93 li t4,0 - 80000154: 00500193 li gp,5 - 80000158: 49df1c63 bne t5,t4,800005f0 - -000000008000015c : - 8000015c: 800000b7 lui ra,0x80000 - 80000160: 00000113 li sp,0 - 80000164: 0220bf33 mulhu t5,ra,sp - 80000168: 00000e93 li t4,0 - 8000016c: 00600193 li gp,6 - 80000170: 49df1063 bne t5,t4,800005f0 - -0000000080000174 : - 80000174: 800000b7 lui ra,0x80000 - 80000178: ffff8137 lui sp,0xffff8 - 8000017c: 0220bf33 mulhu t5,ra,sp - 80000180: ffff0eb7 lui t4,0xffff0 - 80000184: fffe8e9b addiw t4,t4,-1 - 80000188: 00fe9e93 slli t4,t4,0xf - 8000018c: 00700193 li gp,7 - 80000190: 47df1063 bne t5,t4,800005f0 - -0000000080000194 : - 80000194: faaab0b7 lui ra,0xfaaab - 80000198: aab0809b addiw ra,ra,-1365 - 8000019c: 00c09093 slli ra,ra,0xc - 800001a0: aab08093 addi ra,ra,-1365 # fffffffffaaaaaab <_end+0xffffffff7aaa8aab> - 800001a4: 00c09093 slli ra,ra,0xc - 800001a8: aab08093 addi ra,ra,-1365 - 800001ac: 00c09093 slli ra,ra,0xc - 800001b0: aab08093 addi ra,ra,-1365 - 800001b4: 00030137 lui sp,0x30 - 800001b8: e7d1011b addiw sp,sp,-387 - 800001bc: 0220bf33 mulhu t5,ra,sp - 800001c0: 00020eb7 lui t4,0x20 - 800001c4: efee8e9b addiw t4,t4,-258 - 800001c8: 01e00193 li gp,30 - 800001cc: 43df1263 bne t5,t4,800005f0 - -00000000800001d0 : - 800001d0: 000300b7 lui ra,0x30 - 800001d4: e7d0809b addiw ra,ra,-387 - 800001d8: faaab137 lui sp,0xfaaab - 800001dc: aab1011b addiw sp,sp,-1365 - 800001e0: 00c11113 slli sp,sp,0xc - 800001e4: aab10113 addi sp,sp,-1365 # fffffffffaaaaaab <_end+0xffffffff7aaa8aab> - 800001e8: 00c11113 slli sp,sp,0xc - 800001ec: aab10113 addi sp,sp,-1365 - 800001f0: 00c11113 slli sp,sp,0xc - 800001f4: aab10113 addi sp,sp,-1365 - 800001f8: 0220bf33 mulhu t5,ra,sp - 800001fc: 00020eb7 lui t4,0x20 - 80000200: efee8e9b addiw t4,t4,-258 - 80000204: 01f00193 li gp,31 - 80000208: 3fdf1463 bne t5,t4,800005f0 - -000000008000020c : - 8000020c: 00d0009b addiw ra,zero,13 - 80000210: 02009093 slli ra,ra,0x20 - 80000214: 00b0011b addiw sp,zero,11 - 80000218: 02011113 slli sp,sp,0x20 - 8000021c: 0220b0b3 mulhu ra,ra,sp - 80000220: 08f00e93 li t4,143 - 80000224: 00800193 li gp,8 - 80000228: 3dd09463 bne ra,t4,800005f0 - -000000008000022c : - 8000022c: 0070009b addiw ra,zero,7 - 80000230: 02109093 slli ra,ra,0x21 - 80000234: 00b0011b addiw sp,zero,11 - 80000238: 02011113 slli sp,sp,0x20 - 8000023c: 0220b133 mulhu sp,ra,sp - 80000240: 09a00e93 li t4,154 - 80000244: 00900193 li gp,9 - 80000248: 3bd11463 bne sp,t4,800005f0 - -000000008000024c : - 8000024c: 00d0009b addiw ra,zero,13 - 80000250: 02009093 slli ra,ra,0x20 - 80000254: 0210b0b3 mulhu ra,ra,ra - 80000258: 0a900e93 li t4,169 - 8000025c: 00a00193 li gp,10 - 80000260: 39d09863 bne ra,t4,800005f0 - -0000000080000264 : - 80000264: 00000213 li tp,0 - 80000268: 00d0009b addiw ra,zero,13 - 8000026c: 02009093 slli ra,ra,0x20 - 80000270: 00b0011b addiw sp,zero,11 - 80000274: 02011113 slli sp,sp,0x20 - 80000278: 0220bf33 mulhu t5,ra,sp - 8000027c: 000f0313 mv t1,t5 - 80000280: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000284: 00200293 li t0,2 - 80000288: fe5210e3 bne tp,t0,80000268 - 8000028c: 08f00e93 li t4,143 - 80000290: 00b00193 li gp,11 - 80000294: 35d31e63 bne t1,t4,800005f0 - -0000000080000298 : - 80000298: 00000213 li tp,0 - 8000029c: 0070009b addiw ra,zero,7 - 800002a0: 02109093 slli ra,ra,0x21 - 800002a4: 00b0011b addiw sp,zero,11 - 800002a8: 02011113 slli sp,sp,0x20 - 800002ac: 0220bf33 mulhu t5,ra,sp - 800002b0: 00000013 nop - 800002b4: 000f0313 mv t1,t5 - 800002b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002bc: 00200293 li t0,2 - 800002c0: fc521ee3 bne tp,t0,8000029c - 800002c4: 09a00e93 li t4,154 - 800002c8: 00c00193 li gp,12 - 800002cc: 33d31263 bne t1,t4,800005f0 - -00000000800002d0 : - 800002d0: 00000213 li tp,0 - 800002d4: 00f0009b addiw ra,zero,15 - 800002d8: 02009093 slli ra,ra,0x20 - 800002dc: 00b0011b addiw sp,zero,11 - 800002e0: 02011113 slli sp,sp,0x20 - 800002e4: 0220bf33 mulhu t5,ra,sp - 800002e8: 00000013 nop - 800002ec: 00000013 nop - 800002f0: 000f0313 mv t1,t5 - 800002f4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002f8: 00200293 li t0,2 - 800002fc: fc521ce3 bne tp,t0,800002d4 - 80000300: 0a500e93 li t4,165 - 80000304: 00d00193 li gp,13 - 80000308: 2fd31463 bne t1,t4,800005f0 - -000000008000030c : - 8000030c: 00000213 li tp,0 - 80000310: 00d0009b addiw ra,zero,13 - 80000314: 02009093 slli ra,ra,0x20 - 80000318: 00b0011b addiw sp,zero,11 - 8000031c: 02011113 slli sp,sp,0x20 - 80000320: 0220bf33 mulhu t5,ra,sp - 80000324: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000328: 00200293 li t0,2 - 8000032c: fe5212e3 bne tp,t0,80000310 - 80000330: 08f00e93 li t4,143 - 80000334: 00e00193 li gp,14 - 80000338: 2bdf1c63 bne t5,t4,800005f0 - -000000008000033c : - 8000033c: 00000213 li tp,0 - 80000340: 0070009b addiw ra,zero,7 - 80000344: 02109093 slli ra,ra,0x21 - 80000348: 00b0011b addiw sp,zero,11 - 8000034c: 02011113 slli sp,sp,0x20 - 80000350: 00000013 nop - 80000354: 0220bf33 mulhu t5,ra,sp - 80000358: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000035c: 00200293 li t0,2 - 80000360: fe5210e3 bne tp,t0,80000340 - 80000364: 09a00e93 li t4,154 - 80000368: 00f00193 li gp,15 - 8000036c: 29df1263 bne t5,t4,800005f0 - -0000000080000370 : - 80000370: 00000213 li tp,0 - 80000374: 00f0009b addiw ra,zero,15 - 80000378: 02009093 slli ra,ra,0x20 - 8000037c: 00b0011b addiw sp,zero,11 - 80000380: 02011113 slli sp,sp,0x20 - 80000384: 00000013 nop - 80000388: 00000013 nop - 8000038c: 0220bf33 mulhu t5,ra,sp - 80000390: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000394: 00200293 li t0,2 - 80000398: fc521ee3 bne tp,t0,80000374 - 8000039c: 0a500e93 li t4,165 - 800003a0: 01000193 li gp,16 - 800003a4: 25df1663 bne t5,t4,800005f0 - -00000000800003a8 : - 800003a8: 00000213 li tp,0 - 800003ac: 00d0009b addiw ra,zero,13 - 800003b0: 02009093 slli ra,ra,0x20 - 800003b4: 00000013 nop - 800003b8: 00b0011b addiw sp,zero,11 - 800003bc: 02011113 slli sp,sp,0x20 - 800003c0: 0220bf33 mulhu t5,ra,sp - 800003c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003c8: 00200293 li t0,2 - 800003cc: fe5210e3 bne tp,t0,800003ac - 800003d0: 08f00e93 li t4,143 - 800003d4: 01100193 li gp,17 - 800003d8: 21df1c63 bne t5,t4,800005f0 - -00000000800003dc : - 800003dc: 00000213 li tp,0 - 800003e0: 0070009b addiw ra,zero,7 - 800003e4: 02109093 slli ra,ra,0x21 - 800003e8: 00000013 nop - 800003ec: 00b0011b addiw sp,zero,11 - 800003f0: 02011113 slli sp,sp,0x20 - 800003f4: 00000013 nop - 800003f8: 0220bf33 mulhu t5,ra,sp - 800003fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000400: 00200293 li t0,2 - 80000404: fc521ee3 bne tp,t0,800003e0 - 80000408: 09a00e93 li t4,154 - 8000040c: 01200193 li gp,18 - 80000410: 1fdf1063 bne t5,t4,800005f0 - -0000000080000414 : - 80000414: 00000213 li tp,0 - 80000418: 00f0009b addiw ra,zero,15 - 8000041c: 02009093 slli ra,ra,0x20 - 80000420: 00000013 nop - 80000424: 00000013 nop - 80000428: 00b0011b addiw sp,zero,11 - 8000042c: 02011113 slli sp,sp,0x20 - 80000430: 0220bf33 mulhu t5,ra,sp - 80000434: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000438: 00200293 li t0,2 - 8000043c: fc521ee3 bne tp,t0,80000418 - 80000440: 0a500e93 li t4,165 - 80000444: 01300193 li gp,19 - 80000448: 1bdf1463 bne t5,t4,800005f0 - -000000008000044c : - 8000044c: 00000213 li tp,0 - 80000450: 00b0011b addiw sp,zero,11 - 80000454: 02011113 slli sp,sp,0x20 - 80000458: 00d0009b addiw ra,zero,13 - 8000045c: 02009093 slli ra,ra,0x20 - 80000460: 0220bf33 mulhu t5,ra,sp - 80000464: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000468: 00200293 li t0,2 - 8000046c: fe5212e3 bne tp,t0,80000450 - 80000470: 08f00e93 li t4,143 - 80000474: 01400193 li gp,20 - 80000478: 17df1c63 bne t5,t4,800005f0 - -000000008000047c : - 8000047c: 00000213 li tp,0 - 80000480: 00b0011b addiw sp,zero,11 - 80000484: 02011113 slli sp,sp,0x20 - 80000488: 0070009b addiw ra,zero,7 - 8000048c: 02109093 slli ra,ra,0x21 - 80000490: 00000013 nop - 80000494: 0220bf33 mulhu t5,ra,sp - 80000498: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000049c: 00200293 li t0,2 - 800004a0: fe5210e3 bne tp,t0,80000480 - 800004a4: 09a00e93 li t4,154 - 800004a8: 01500193 li gp,21 - 800004ac: 15df1263 bne t5,t4,800005f0 - -00000000800004b0 : - 800004b0: 00000213 li tp,0 - 800004b4: 00b0011b addiw sp,zero,11 - 800004b8: 02011113 slli sp,sp,0x20 - 800004bc: 00f0009b addiw ra,zero,15 - 800004c0: 02009093 slli ra,ra,0x20 - 800004c4: 00000013 nop - 800004c8: 00000013 nop - 800004cc: 0220bf33 mulhu t5,ra,sp - 800004d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800004d4: 00200293 li t0,2 - 800004d8: fc521ee3 bne tp,t0,800004b4 - 800004dc: 0a500e93 li t4,165 - 800004e0: 01600193 li gp,22 - 800004e4: 11df1663 bne t5,t4,800005f0 - -00000000800004e8 : - 800004e8: 00000213 li tp,0 - 800004ec: 00b0011b addiw sp,zero,11 - 800004f0: 02011113 slli sp,sp,0x20 - 800004f4: 00000013 nop - 800004f8: 00d0009b addiw ra,zero,13 - 800004fc: 02009093 slli ra,ra,0x20 - 80000500: 0220bf33 mulhu t5,ra,sp - 80000504: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000508: 00200293 li t0,2 - 8000050c: fe5210e3 bne tp,t0,800004ec - 80000510: 08f00e93 li t4,143 - 80000514: 01700193 li gp,23 - 80000518: 0ddf1c63 bne t5,t4,800005f0 - -000000008000051c : - 8000051c: 00000213 li tp,0 - 80000520: 00b0011b addiw sp,zero,11 - 80000524: 02011113 slli sp,sp,0x20 - 80000528: 00000013 nop - 8000052c: 0070009b addiw ra,zero,7 - 80000530: 02109093 slli ra,ra,0x21 - 80000534: 00000013 nop - 80000538: 0220bf33 mulhu t5,ra,sp - 8000053c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000540: 00200293 li t0,2 - 80000544: fc521ee3 bne tp,t0,80000520 - 80000548: 09a00e93 li t4,154 - 8000054c: 01800193 li gp,24 - 80000550: 0bdf1063 bne t5,t4,800005f0 - -0000000080000554 : - 80000554: 00000213 li tp,0 - 80000558: 00b0011b addiw sp,zero,11 - 8000055c: 02011113 slli sp,sp,0x20 - 80000560: 00000013 nop - 80000564: 00000013 nop - 80000568: 00f0009b addiw ra,zero,15 - 8000056c: 02009093 slli ra,ra,0x20 - 80000570: 0220bf33 mulhu t5,ra,sp - 80000574: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000578: 00200293 li t0,2 - 8000057c: fc521ee3 bne tp,t0,80000558 - 80000580: 0a500e93 li t4,165 - 80000584: 01900193 li gp,25 - 80000588: 07df1463 bne t5,t4,800005f0 - -000000008000058c : - 8000058c: 01f0009b addiw ra,zero,31 - 80000590: 02009093 slli ra,ra,0x20 - 80000594: 02103133 mulhu sp,zero,ra - 80000598: 00000e93 li t4,0 - 8000059c: 01a00193 li gp,26 - 800005a0: 05d11863 bne sp,t4,800005f0 - -00000000800005a4 : - 800005a4: 0010009b addiw ra,zero,1 - 800005a8: 02509093 slli ra,ra,0x25 - 800005ac: 0200b133 mulhu sp,ra,zero - 800005b0: 00000e93 li t4,0 - 800005b4: 01b00193 li gp,27 - 800005b8: 03d11c63 bne sp,t4,800005f0 - -00000000800005bc : - 800005bc: 020030b3 mulhu ra,zero,zero - 800005c0: 00000e93 li t4,0 - 800005c4: 01c00193 li gp,28 - 800005c8: 03d09463 bne ra,t4,800005f0 - -00000000800005cc : - 800005cc: 0210009b addiw ra,zero,33 - 800005d0: 02009093 slli ra,ra,0x20 - 800005d4: 0110011b addiw sp,zero,17 - 800005d8: 02111113 slli sp,sp,0x21 - 800005dc: 0220b033 mulhu zero,ra,sp - 800005e0: 00000e93 li t4,0 - 800005e4: 01d00193 li gp,29 - 800005e8: 01d01463 bne zero,t4,800005f0 - 800005ec: 00301c63 bne zero,gp,80000604 - -00000000800005f0 : - 800005f0: 0ff0000f fence - 800005f4: 00018063 beqz gp,800005f4 - 800005f8: 00119193 slli gp,gp,0x1 - 800005fc: 0011e193 ori gp,gp,1 - 80000600: 00000073 ecall - -0000000080000604 : - 80000604: 0ff0000f fence - 80000608: 00100193 li gp,1 - 8000060c: 00000073 ecall - 80000610: c0001073 unimp - 80000614: 0000 unimp - 80000616: 0000 unimp - 80000618: 0000 unimp - 8000061a: 0000 unimp - 8000061c: 0000 unimp - 8000061e: 0000 unimp - 80000620: 0000 unimp - 80000622: 0000 unimp - 80000624: 0000 unimp - 80000626: 0000 unimp - 80000628: 0000 unimp - 8000062a: 0000 unimp - 8000062c: 0000 unimp - 8000062e: 0000 unimp - 80000630: 0000 unimp - 80000632: 0000 unimp - 80000634: 0000 unimp - 80000636: 0000 unimp - 80000638: 0000 unimp - 8000063a: 0000 unimp - 8000063c: 0000 unimp - 8000063e: 0000 unimp - 80000640: 0000 unimp - 80000642: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-mulhu.elf b/test/riscv/tests/rv64um-p-mulhu.elf deleted file mode 100644 index e3ae453e..00000000 Binary files a/test/riscv/tests/rv64um-p-mulhu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-p-mulw.dump b/test/riscv/tests/rv64um-p-mulw.dump deleted file mode 100644 index c9c2d8de..00000000 --- a/test/riscv/tests/rv64um-p-mulw.dump +++ /dev/null @@ -1,399 +0,0 @@ - -rv64um-p-mulw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 00000093 li ra,0 - 80000100: 00000113 li sp,0 - 80000104: 02208f3b mulw t5,ra,sp - 80000108: 00000e93 li t4,0 - 8000010c: 00200193 li gp,2 - 80000110: 3ddf1263 bne t5,t4,800004d4 - -0000000080000114 : - 80000114: 00100093 li ra,1 - 80000118: 00100113 li sp,1 - 8000011c: 02208f3b mulw t5,ra,sp - 80000120: 00100e93 li t4,1 - 80000124: 00300193 li gp,3 - 80000128: 3bdf1663 bne t5,t4,800004d4 - -000000008000012c : - 8000012c: 00300093 li ra,3 - 80000130: 00700113 li sp,7 - 80000134: 02208f3b mulw t5,ra,sp - 80000138: 01500e93 li t4,21 - 8000013c: 00400193 li gp,4 - 80000140: 39df1a63 bne t5,t4,800004d4 - -0000000080000144 : - 80000144: 00000093 li ra,0 - 80000148: ffff8137 lui sp,0xffff8 - 8000014c: 02208f3b mulw t5,ra,sp - 80000150: 00000e93 li t4,0 - 80000154: 00500193 li gp,5 - 80000158: 37df1e63 bne t5,t4,800004d4 - -000000008000015c : - 8000015c: 800000b7 lui ra,0x80000 - 80000160: 00000113 li sp,0 - 80000164: 02208f3b mulw t5,ra,sp - 80000168: 00000e93 li t4,0 - 8000016c: 00600193 li gp,6 - 80000170: 37df1263 bne t5,t4,800004d4 - -0000000080000174 : - 80000174: 800000b7 lui ra,0x80000 - 80000178: ffff8137 lui sp,0xffff8 - 8000017c: 02208f3b mulw t5,ra,sp - 80000180: 00000e93 li t4,0 - 80000184: 00700193 li gp,7 - 80000188: 35df1663 bne t5,t4,800004d4 - -000000008000018c : - 8000018c: 00d00093 li ra,13 - 80000190: 00b00113 li sp,11 - 80000194: 022080bb mulw ra,ra,sp - 80000198: 08f00e93 li t4,143 - 8000019c: 00800193 li gp,8 - 800001a0: 33d09a63 bne ra,t4,800004d4 - -00000000800001a4 : - 800001a4: 00e00093 li ra,14 - 800001a8: 00b00113 li sp,11 - 800001ac: 0220813b mulw sp,ra,sp - 800001b0: 09a00e93 li t4,154 - 800001b4: 00900193 li gp,9 - 800001b8: 31d11e63 bne sp,t4,800004d4 - -00000000800001bc : - 800001bc: 00d00093 li ra,13 - 800001c0: 021080bb mulw ra,ra,ra - 800001c4: 0a900e93 li t4,169 - 800001c8: 00a00193 li gp,10 - 800001cc: 31d09463 bne ra,t4,800004d4 - -00000000800001d0 : - 800001d0: 00000213 li tp,0 - 800001d4: 00d00093 li ra,13 - 800001d8: 00b00113 li sp,11 - 800001dc: 02208f3b mulw t5,ra,sp - 800001e0: 000f0313 mv t1,t5 - 800001e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800001e8: 00200293 li t0,2 - 800001ec: fe5214e3 bne tp,t0,800001d4 - 800001f0: 08f00e93 li t4,143 - 800001f4: 00b00193 li gp,11 - 800001f8: 2dd31e63 bne t1,t4,800004d4 - -00000000800001fc : - 800001fc: 00000213 li tp,0 - 80000200: 00e00093 li ra,14 - 80000204: 00b00113 li sp,11 - 80000208: 02208f3b mulw t5,ra,sp - 8000020c: 00000013 nop - 80000210: 000f0313 mv t1,t5 - 80000214: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000218: 00200293 li t0,2 - 8000021c: fe5212e3 bne tp,t0,80000200 - 80000220: 09a00e93 li t4,154 - 80000224: 00c00193 li gp,12 - 80000228: 2bd31663 bne t1,t4,800004d4 - -000000008000022c : - 8000022c: 00000213 li tp,0 - 80000230: 00f00093 li ra,15 - 80000234: 00b00113 li sp,11 - 80000238: 02208f3b mulw t5,ra,sp - 8000023c: 00000013 nop - 80000240: 00000013 nop - 80000244: 000f0313 mv t1,t5 - 80000248: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000024c: 00200293 li t0,2 - 80000250: fe5210e3 bne tp,t0,80000230 - 80000254: 0a500e93 li t4,165 - 80000258: 00d00193 li gp,13 - 8000025c: 27d31c63 bne t1,t4,800004d4 - -0000000080000260 : - 80000260: 00000213 li tp,0 - 80000264: 00d00093 li ra,13 - 80000268: 00b00113 li sp,11 - 8000026c: 02208f3b mulw t5,ra,sp - 80000270: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000274: 00200293 li t0,2 - 80000278: fe5216e3 bne tp,t0,80000264 - 8000027c: 08f00e93 li t4,143 - 80000280: 00e00193 li gp,14 - 80000284: 25df1863 bne t5,t4,800004d4 - -0000000080000288 : - 80000288: 00000213 li tp,0 - 8000028c: 00e00093 li ra,14 - 80000290: 00b00113 li sp,11 - 80000294: 00000013 nop - 80000298: 02208f3b mulw t5,ra,sp - 8000029c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002a0: 00200293 li t0,2 - 800002a4: fe5214e3 bne tp,t0,8000028c - 800002a8: 09a00e93 li t4,154 - 800002ac: 00f00193 li gp,15 - 800002b0: 23df1263 bne t5,t4,800004d4 - -00000000800002b4 : - 800002b4: 00000213 li tp,0 - 800002b8: 00f00093 li ra,15 - 800002bc: 00b00113 li sp,11 - 800002c0: 00000013 nop - 800002c4: 00000013 nop - 800002c8: 02208f3b mulw t5,ra,sp - 800002cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002d0: 00200293 li t0,2 - 800002d4: fe5212e3 bne tp,t0,800002b8 - 800002d8: 0a500e93 li t4,165 - 800002dc: 01000193 li gp,16 - 800002e0: 1fdf1a63 bne t5,t4,800004d4 - -00000000800002e4 : - 800002e4: 00000213 li tp,0 - 800002e8: 00d00093 li ra,13 - 800002ec: 00000013 nop - 800002f0: 00b00113 li sp,11 - 800002f4: 02208f3b mulw t5,ra,sp - 800002f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800002fc: 00200293 li t0,2 - 80000300: fe5214e3 bne tp,t0,800002e8 - 80000304: 08f00e93 li t4,143 - 80000308: 01100193 li gp,17 - 8000030c: 1ddf1463 bne t5,t4,800004d4 - -0000000080000310 : - 80000310: 00000213 li tp,0 - 80000314: 00e00093 li ra,14 - 80000318: 00000013 nop - 8000031c: 00b00113 li sp,11 - 80000320: 00000013 nop - 80000324: 02208f3b mulw t5,ra,sp - 80000328: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000032c: 00200293 li t0,2 - 80000330: fe5212e3 bne tp,t0,80000314 - 80000334: 09a00e93 li t4,154 - 80000338: 01200193 li gp,18 - 8000033c: 19df1c63 bne t5,t4,800004d4 - -0000000080000340 : - 80000340: 00000213 li tp,0 - 80000344: 00f00093 li ra,15 - 80000348: 00000013 nop - 8000034c: 00000013 nop - 80000350: 00b00113 li sp,11 - 80000354: 02208f3b mulw t5,ra,sp - 80000358: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000035c: 00200293 li t0,2 - 80000360: fe5212e3 bne tp,t0,80000344 - 80000364: 0a500e93 li t4,165 - 80000368: 01300193 li gp,19 - 8000036c: 17df1463 bne t5,t4,800004d4 - -0000000080000370 : - 80000370: 00000213 li tp,0 - 80000374: 00b00113 li sp,11 - 80000378: 00d00093 li ra,13 - 8000037c: 02208f3b mulw t5,ra,sp - 80000380: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80000384: 00200293 li t0,2 - 80000388: fe5216e3 bne tp,t0,80000374 - 8000038c: 08f00e93 li t4,143 - 80000390: 01400193 li gp,20 - 80000394: 15df1063 bne t5,t4,800004d4 - -0000000080000398 : - 80000398: 00000213 li tp,0 - 8000039c: 00b00113 li sp,11 - 800003a0: 00e00093 li ra,14 - 800003a4: 00000013 nop - 800003a8: 02208f3b mulw t5,ra,sp - 800003ac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003b0: 00200293 li t0,2 - 800003b4: fe5214e3 bne tp,t0,8000039c - 800003b8: 09a00e93 li t4,154 - 800003bc: 01500193 li gp,21 - 800003c0: 11df1a63 bne t5,t4,800004d4 - -00000000800003c4 : - 800003c4: 00000213 li tp,0 - 800003c8: 00b00113 li sp,11 - 800003cc: 00f00093 li ra,15 - 800003d0: 00000013 nop - 800003d4: 00000013 nop - 800003d8: 02208f3b mulw t5,ra,sp - 800003dc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 800003e0: 00200293 li t0,2 - 800003e4: fe5212e3 bne tp,t0,800003c8 - 800003e8: 0a500e93 li t4,165 - 800003ec: 01600193 li gp,22 - 800003f0: 0fdf1263 bne t5,t4,800004d4 - -00000000800003f4 : - 800003f4: 00000213 li tp,0 - 800003f8: 00b00113 li sp,11 - 800003fc: 00000013 nop - 80000400: 00d00093 li ra,13 - 80000404: 02208f3b mulw t5,ra,sp - 80000408: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000040c: 00200293 li t0,2 - 80000410: fe5214e3 bne tp,t0,800003f8 - 80000414: 08f00e93 li t4,143 - 80000418: 01700193 li gp,23 - 8000041c: 0bdf1c63 bne t5,t4,800004d4 - -0000000080000420 : - 80000420: 00000213 li tp,0 - 80000424: 00b00113 li sp,11 - 80000428: 00000013 nop - 8000042c: 00e00093 li ra,14 - 80000430: 00000013 nop - 80000434: 02208f3b mulw t5,ra,sp - 80000438: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000043c: 00200293 li t0,2 - 80000440: fe5212e3 bne tp,t0,80000424 - 80000444: 09a00e93 li t4,154 - 80000448: 01800193 li gp,24 - 8000044c: 09df1463 bne t5,t4,800004d4 - -0000000080000450 : - 80000450: 00000213 li tp,0 - 80000454: 00b00113 li sp,11 - 80000458: 00000013 nop - 8000045c: 00000013 nop - 80000460: 00f00093 li ra,15 - 80000464: 02208f3b mulw t5,ra,sp - 80000468: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 8000046c: 00200293 li t0,2 - 80000470: fe5212e3 bne tp,t0,80000454 - 80000474: 0a500e93 li t4,165 - 80000478: 01900193 li gp,25 - 8000047c: 05df1c63 bne t5,t4,800004d4 - -0000000080000480 : - 80000480: 01f00093 li ra,31 - 80000484: 0210013b mulw sp,zero,ra - 80000488: 00000e93 li t4,0 - 8000048c: 01a00193 li gp,26 - 80000490: 05d11263 bne sp,t4,800004d4 - -0000000080000494 : - 80000494: 02000093 li ra,32 - 80000498: 0200813b mulw sp,ra,zero - 8000049c: 00000e93 li t4,0 - 800004a0: 01b00193 li gp,27 - 800004a4: 03d11863 bne sp,t4,800004d4 - -00000000800004a8 : - 800004a8: 020000bb mulw ra,zero,zero - 800004ac: 00000e93 li t4,0 - 800004b0: 01c00193 li gp,28 - 800004b4: 03d09063 bne ra,t4,800004d4 - -00000000800004b8 : - 800004b8: 02100093 li ra,33 - 800004bc: 02200113 li sp,34 - 800004c0: 0220803b mulw zero,ra,sp - 800004c4: 00000e93 li t4,0 - 800004c8: 01d00193 li gp,29 - 800004cc: 01d01463 bne zero,t4,800004d4 - 800004d0: 00301c63 bne zero,gp,800004e8 - -00000000800004d4 : - 800004d4: 0ff0000f fence - 800004d8: 00018063 beqz gp,800004d8 - 800004dc: 00119193 slli gp,gp,0x1 - 800004e0: 0011e193 ori gp,gp,1 - 800004e4: 00000073 ecall - -00000000800004e8 : - 800004e8: 0ff0000f fence - 800004ec: 00100193 li gp,1 - 800004f0: 00000073 ecall - 800004f4: c0001073 unimp - 800004f8: 0000 unimp - 800004fa: 0000 unimp - 800004fc: 0000 unimp - 800004fe: 0000 unimp - 80000500: 0000 unimp - 80000502: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-mulw.elf b/test/riscv/tests/rv64um-p-mulw.elf deleted file mode 100644 index 9c3214c6..00000000 Binary files a/test/riscv/tests/rv64um-p-mulw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-p-rem.dump b/test/riscv/tests/rv64um-p-rem.dump deleted file mode 100644 index a3676862..00000000 --- a/test/riscv/tests/rv64um-p-rem.dump +++ /dev/null @@ -1,196 +0,0 @@ - -rv64um-p-rem: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 01400093 li ra,20 - 80000100: 00600113 li sp,6 - 80000104: 0220ef33 rem t5,ra,sp - 80000108: 00200e93 li t4,2 - 8000010c: 00200193 li gp,2 - 80000110: 0ddf1c63 bne t5,t4,800001e8 - -0000000080000114 : - 80000114: fec00093 li ra,-20 - 80000118: 00600113 li sp,6 - 8000011c: 0220ef33 rem t5,ra,sp - 80000120: ffe00e93 li t4,-2 - 80000124: 00300193 li gp,3 - 80000128: 0ddf1063 bne t5,t4,800001e8 - -000000008000012c : - 8000012c: 01400093 li ra,20 - 80000130: ffa00113 li sp,-6 - 80000134: 0220ef33 rem t5,ra,sp - 80000138: 00200e93 li t4,2 - 8000013c: 00400193 li gp,4 - 80000140: 0bdf1463 bne t5,t4,800001e8 - -0000000080000144 : - 80000144: fec00093 li ra,-20 - 80000148: ffa00113 li sp,-6 - 8000014c: 0220ef33 rem t5,ra,sp - 80000150: ffe00e93 li t4,-2 - 80000154: 00500193 li gp,5 - 80000158: 09df1863 bne t5,t4,800001e8 - -000000008000015c : - 8000015c: fff0009b addiw ra,zero,-1 - 80000160: 03f09093 slli ra,ra,0x3f - 80000164: 00100113 li sp,1 - 80000168: 0220ef33 rem t5,ra,sp - 8000016c: 00000e93 li t4,0 - 80000170: 00600193 li gp,6 - 80000174: 07df1a63 bne t5,t4,800001e8 - -0000000080000178 : - 80000178: fff0009b addiw ra,zero,-1 - 8000017c: 03f09093 slli ra,ra,0x3f - 80000180: fff00113 li sp,-1 - 80000184: 0220ef33 rem t5,ra,sp - 80000188: 00000e93 li t4,0 - 8000018c: 00700193 li gp,7 - 80000190: 05df1c63 bne t5,t4,800001e8 - -0000000080000194 : - 80000194: fff0009b addiw ra,zero,-1 - 80000198: 03f09093 slli ra,ra,0x3f - 8000019c: 00000113 li sp,0 - 800001a0: 0220ef33 rem t5,ra,sp - 800001a4: fff00e9b addiw t4,zero,-1 - 800001a8: 03fe9e93 slli t4,t4,0x3f - 800001ac: 00800193 li gp,8 - 800001b0: 03df1c63 bne t5,t4,800001e8 - -00000000800001b4 : - 800001b4: 00100093 li ra,1 - 800001b8: 00000113 li sp,0 - 800001bc: 0220ef33 rem t5,ra,sp - 800001c0: 00100e93 li t4,1 - 800001c4: 00900193 li gp,9 - 800001c8: 03df1063 bne t5,t4,800001e8 - -00000000800001cc : - 800001cc: 00000093 li ra,0 - 800001d0: 00000113 li sp,0 - 800001d4: 0220ef33 rem t5,ra,sp - 800001d8: 00000e93 li t4,0 - 800001dc: 00a00193 li gp,10 - 800001e0: 01df1463 bne t5,t4,800001e8 - 800001e4: 00301c63 bne zero,gp,800001fc - -00000000800001e8 : - 800001e8: 0ff0000f fence - 800001ec: 00018063 beqz gp,800001ec - 800001f0: 00119193 slli gp,gp,0x1 - 800001f4: 0011e193 ori gp,gp,1 - 800001f8: 00000073 ecall - -00000000800001fc : - 800001fc: 0ff0000f fence - 80000200: 00100193 li gp,1 - 80000204: 00000073 ecall - 80000208: c0001073 unimp - 8000020c: 0000 unimp - 8000020e: 0000 unimp - 80000210: 0000 unimp - 80000212: 0000 unimp - 80000214: 0000 unimp - 80000216: 0000 unimp - 80000218: 0000 unimp - 8000021a: 0000 unimp - 8000021c: 0000 unimp - 8000021e: 0000 unimp - 80000220: 0000 unimp - 80000222: 0000 unimp - 80000224: 0000 unimp - 80000226: 0000 unimp - 80000228: 0000 unimp - 8000022a: 0000 unimp - 8000022c: 0000 unimp - 8000022e: 0000 unimp - 80000230: 0000 unimp - 80000232: 0000 unimp - 80000234: 0000 unimp - 80000236: 0000 unimp - 80000238: 0000 unimp - 8000023a: 0000 unimp - 8000023c: 0000 unimp - 8000023e: 0000 unimp - 80000240: 0000 unimp - 80000242: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-rem.elf b/test/riscv/tests/rv64um-p-rem.elf deleted file mode 100644 index cfe6e6c2..00000000 Binary files a/test/riscv/tests/rv64um-p-rem.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-p-remu.dump b/test/riscv/tests/rv64um-p-remu.dump deleted file mode 100644 index f33af39a..00000000 --- a/test/riscv/tests/rv64um-p-remu.dump +++ /dev/null @@ -1,195 +0,0 @@ - -rv64um-p-remu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 01400093 li ra,20 - 80000100: 00600113 li sp,6 - 80000104: 0220ff33 remu t5,ra,sp - 80000108: 00200e93 li t4,2 - 8000010c: 00200193 li gp,2 - 80000110: 0ddf1e63 bne t5,t4,800001ec - -0000000080000114 : - 80000114: fec00093 li ra,-20 - 80000118: 00600113 li sp,6 - 8000011c: 0220ff33 remu t5,ra,sp - 80000120: 00200e93 li t4,2 - 80000124: 00300193 li gp,3 - 80000128: 0ddf1263 bne t5,t4,800001ec - -000000008000012c : - 8000012c: 01400093 li ra,20 - 80000130: ffa00113 li sp,-6 - 80000134: 0220ff33 remu t5,ra,sp - 80000138: 01400e93 li t4,20 - 8000013c: 00400193 li gp,4 - 80000140: 0bdf1663 bne t5,t4,800001ec - -0000000080000144 : - 80000144: fec00093 li ra,-20 - 80000148: ffa00113 li sp,-6 - 8000014c: 0220ff33 remu t5,ra,sp - 80000150: fec00e93 li t4,-20 - 80000154: 00500193 li gp,5 - 80000158: 09df1a63 bne t5,t4,800001ec - -000000008000015c : - 8000015c: fff0009b addiw ra,zero,-1 - 80000160: 03f09093 slli ra,ra,0x3f - 80000164: 00100113 li sp,1 - 80000168: 0220ff33 remu t5,ra,sp - 8000016c: 00000e93 li t4,0 - 80000170: 00600193 li gp,6 - 80000174: 07df1c63 bne t5,t4,800001ec - -0000000080000178 : - 80000178: fff0009b addiw ra,zero,-1 - 8000017c: 03f09093 slli ra,ra,0x3f - 80000180: fff00113 li sp,-1 - 80000184: 0220ff33 remu t5,ra,sp - 80000188: fff00e9b addiw t4,zero,-1 - 8000018c: 03fe9e93 slli t4,t4,0x3f - 80000190: 00700193 li gp,7 - 80000194: 05df1c63 bne t5,t4,800001ec - -0000000080000198 : - 80000198: fff0009b addiw ra,zero,-1 - 8000019c: 03f09093 slli ra,ra,0x3f - 800001a0: 00000113 li sp,0 - 800001a4: 0220ff33 remu t5,ra,sp - 800001a8: fff00e9b addiw t4,zero,-1 - 800001ac: 03fe9e93 slli t4,t4,0x3f - 800001b0: 00800193 li gp,8 - 800001b4: 03df1c63 bne t5,t4,800001ec - -00000000800001b8 : - 800001b8: 00100093 li ra,1 - 800001bc: 00000113 li sp,0 - 800001c0: 0220ff33 remu t5,ra,sp - 800001c4: 00100e93 li t4,1 - 800001c8: 00900193 li gp,9 - 800001cc: 03df1063 bne t5,t4,800001ec - -00000000800001d0 : - 800001d0: 00000093 li ra,0 - 800001d4: 00000113 li sp,0 - 800001d8: 0220ff33 remu t5,ra,sp - 800001dc: 00000e93 li t4,0 - 800001e0: 00a00193 li gp,10 - 800001e4: 01df1463 bne t5,t4,800001ec - 800001e8: 00301c63 bne zero,gp,80000200 - -00000000800001ec : - 800001ec: 0ff0000f fence - 800001f0: 00018063 beqz gp,800001f0 - 800001f4: 00119193 slli gp,gp,0x1 - 800001f8: 0011e193 ori gp,gp,1 - 800001fc: 00000073 ecall - -0000000080000200 : - 80000200: 0ff0000f fence - 80000204: 00100193 li gp,1 - 80000208: 00000073 ecall - 8000020c: c0001073 unimp - 80000210: 0000 unimp - 80000212: 0000 unimp - 80000214: 0000 unimp - 80000216: 0000 unimp - 80000218: 0000 unimp - 8000021a: 0000 unimp - 8000021c: 0000 unimp - 8000021e: 0000 unimp - 80000220: 0000 unimp - 80000222: 0000 unimp - 80000224: 0000 unimp - 80000226: 0000 unimp - 80000228: 0000 unimp - 8000022a: 0000 unimp - 8000022c: 0000 unimp - 8000022e: 0000 unimp - 80000230: 0000 unimp - 80000232: 0000 unimp - 80000234: 0000 unimp - 80000236: 0000 unimp - 80000238: 0000 unimp - 8000023a: 0000 unimp - 8000023c: 0000 unimp - 8000023e: 0000 unimp - 80000240: 0000 unimp - 80000242: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-remu.elf b/test/riscv/tests/rv64um-p-remu.elf deleted file mode 100644 index 93dcf5ed..00000000 Binary files a/test/riscv/tests/rv64um-p-remu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-p-remuw.dump b/test/riscv/tests/rv64um-p-remuw.dump deleted file mode 100644 index 43ddd98a..00000000 --- a/test/riscv/tests/rv64um-p-remuw.dump +++ /dev/null @@ -1,168 +0,0 @@ - -rv64um-p-remuw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 01400093 li ra,20 - 80000100: 00600113 li sp,6 - 80000104: 0220ff3b remuw t5,ra,sp - 80000108: 00200e93 li t4,2 - 8000010c: 00200193 li gp,2 - 80000110: 0ddf1463 bne t5,t4,800001d8 - -0000000080000114 : - 80000114: fec00093 li ra,-20 - 80000118: 00600113 li sp,6 - 8000011c: 0220ff3b remuw t5,ra,sp - 80000120: 00200e93 li t4,2 - 80000124: 00300193 li gp,3 - 80000128: 0bdf1863 bne t5,t4,800001d8 - -000000008000012c : - 8000012c: 01400093 li ra,20 - 80000130: ffa00113 li sp,-6 - 80000134: 0220ff3b remuw t5,ra,sp - 80000138: 01400e93 li t4,20 - 8000013c: 00400193 li gp,4 - 80000140: 09df1c63 bne t5,t4,800001d8 - -0000000080000144 : - 80000144: fec00093 li ra,-20 - 80000148: ffa00113 li sp,-6 - 8000014c: 0220ff3b remuw t5,ra,sp - 80000150: fec00e93 li t4,-20 - 80000154: 00500193 li gp,5 - 80000158: 09df1063 bne t5,t4,800001d8 - -000000008000015c : - 8000015c: 800000b7 lui ra,0x80000 - 80000160: 00100113 li sp,1 - 80000164: 0220ff3b remuw t5,ra,sp - 80000168: 00000e93 li t4,0 - 8000016c: 00600193 li gp,6 - 80000170: 07df1463 bne t5,t4,800001d8 - -0000000080000174 : - 80000174: 800000b7 lui ra,0x80000 - 80000178: fff00113 li sp,-1 - 8000017c: 0220ff3b remuw t5,ra,sp - 80000180: 80000eb7 lui t4,0x80000 - 80000184: 00700193 li gp,7 - 80000188: 05df1863 bne t5,t4,800001d8 - -000000008000018c : - 8000018c: 800000b7 lui ra,0x80000 - 80000190: 00000113 li sp,0 - 80000194: 0220ff3b remuw t5,ra,sp - 80000198: 80000eb7 lui t4,0x80000 - 8000019c: 00800193 li gp,8 - 800001a0: 03df1c63 bne t5,t4,800001d8 - -00000000800001a4 : - 800001a4: 00100093 li ra,1 - 800001a8: 00000113 li sp,0 - 800001ac: 0220ff3b remuw t5,ra,sp - 800001b0: 00100e93 li t4,1 - 800001b4: 00900193 li gp,9 - 800001b8: 03df1063 bne t5,t4,800001d8 - -00000000800001bc : - 800001bc: 00000093 li ra,0 - 800001c0: 00000113 li sp,0 - 800001c4: 0220ff3b remuw t5,ra,sp - 800001c8: 00000e93 li t4,0 - 800001cc: 00a00193 li gp,10 - 800001d0: 01df1463 bne t5,t4,800001d8 - 800001d4: 00301c63 bne zero,gp,800001ec - -00000000800001d8 : - 800001d8: 0ff0000f fence - 800001dc: 00018063 beqz gp,800001dc - 800001e0: 00119193 slli gp,gp,0x1 - 800001e4: 0011e193 ori gp,gp,1 - 800001e8: 00000073 ecall - -00000000800001ec : - 800001ec: 0ff0000f fence - 800001f0: 00100193 li gp,1 - 800001f4: 00000073 ecall - 800001f8: c0001073 unimp - 800001fc: 0000 unimp - 800001fe: 0000 unimp - 80000200: 0000 unimp - 80000202: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-remuw.elf b/test/riscv/tests/rv64um-p-remuw.elf deleted file mode 100644 index ba166ff5..00000000 Binary files a/test/riscv/tests/rv64um-p-remuw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-p-remw.dump b/test/riscv/tests/rv64um-p-remw.dump deleted file mode 100644 index 48fcac9f..00000000 --- a/test/riscv/tests/rv64um-p-remw.dump +++ /dev/null @@ -1,196 +0,0 @@ - -rv64um-p-remw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 04c0006f j 8000004c - -0000000080000004 : - 80000004: 34202f73 csrr t5,mcause - 80000008: 00800f93 li t6,8 - 8000000c: 03ff0a63 beq t5,t6,80000040 - 80000010: 00900f93 li t6,9 - 80000014: 03ff0663 beq t5,t6,80000040 - 80000018: 00b00f93 li t6,11 - 8000001c: 03ff0263 beq t5,t6,80000040 - 80000020: 80000f17 auipc t5,0x80000 - 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> - 80000028: 000f0463 beqz t5,80000030 - 8000002c: 000f0067 jr t5 - 80000030: 34202f73 csrr t5,mcause - 80000034: 000f5463 bgez t5,8000003c - 80000038: 0040006f j 8000003c - -000000008000003c : - 8000003c: 5391e193 ori gp,gp,1337 - -0000000080000040 : - 80000040: 00001f17 auipc t5,0x1 - 80000044: fc3f2023 sw gp,-64(t5) # 80001000 - 80000048: ff9ff06f j 80000040 - -000000008000004c : - 8000004c: f1402573 csrr a0,mhartid - 80000050: 00051063 bnez a0,80000050 - 80000054: 00000297 auipc t0,0x0 - 80000058: 01028293 addi t0,t0,16 # 80000064 - 8000005c: 30529073 csrw mtvec,t0 - 80000060: 18005073 csrwi satp,0 - 80000064: 00000297 auipc t0,0x0 - 80000068: 01c28293 addi t0,t0,28 # 80000080 - 8000006c: 30529073 csrw mtvec,t0 - 80000070: fff00293 li t0,-1 - 80000074: 3b029073 csrw pmpaddr0,t0 - 80000078: 01f00293 li t0,31 - 8000007c: 3a029073 csrw pmpcfg0,t0 - 80000080: 00000297 auipc t0,0x0 - 80000084: 01828293 addi t0,t0,24 # 80000098 - 80000088: 30529073 csrw mtvec,t0 - 8000008c: 30205073 csrwi medeleg,0 - 80000090: 30305073 csrwi mideleg,0 - 80000094: 30405073 csrwi mie,0 - 80000098: 00000193 li gp,0 - 8000009c: 00000297 auipc t0,0x0 - 800000a0: f6828293 addi t0,t0,-152 # 80000004 - 800000a4: 30529073 csrw mtvec,t0 - 800000a8: 00100513 li a0,1 - 800000ac: 01f51513 slli a0,a0,0x1f - 800000b0: 00055863 bgez a0,800000c0 - 800000b4: 0ff0000f fence - 800000b8: 00100193 li gp,1 - 800000bc: 00000073 ecall - 800000c0: 80000297 auipc t0,0x80000 - 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> - 800000c8: 00028e63 beqz t0,800000e4 - 800000cc: 10529073 csrw stvec,t0 - 800000d0: 0000b2b7 lui t0,0xb - 800000d4: 1092829b addiw t0,t0,265 - 800000d8: 30229073 csrw medeleg,t0 - 800000dc: 30202373 csrr t1,medeleg - 800000e0: f4629ee3 bne t0,t1,8000003c - 800000e4: 30005073 csrwi mstatus,0 - 800000e8: 00000297 auipc t0,0x0 - 800000ec: 01428293 addi t0,t0,20 # 800000fc - 800000f0: 34129073 csrw mepc,t0 - 800000f4: f1402573 csrr a0,mhartid - 800000f8: 30200073 mret - -00000000800000fc : - 800000fc: 01400093 li ra,20 - 80000100: 00600113 li sp,6 - 80000104: 0220ef3b remw t5,ra,sp - 80000108: 00200e93 li t4,2 - 8000010c: 00200193 li gp,2 - 80000110: 0fdf1063 bne t5,t4,800001f0 - -0000000080000114 : - 80000114: fec00093 li ra,-20 - 80000118: 00600113 li sp,6 - 8000011c: 0220ef3b remw t5,ra,sp - 80000120: ffe00e93 li t4,-2 - 80000124: 00300193 li gp,3 - 80000128: 0ddf1463 bne t5,t4,800001f0 - -000000008000012c : - 8000012c: 01400093 li ra,20 - 80000130: ffa00113 li sp,-6 - 80000134: 0220ef3b remw t5,ra,sp - 80000138: 00200e93 li t4,2 - 8000013c: 00400193 li gp,4 - 80000140: 0bdf1863 bne t5,t4,800001f0 - -0000000080000144 : - 80000144: fec00093 li ra,-20 - 80000148: ffa00113 li sp,-6 - 8000014c: 0220ef3b remw t5,ra,sp - 80000150: ffe00e93 li t4,-2 - 80000154: 00500193 li gp,5 - 80000158: 09df1c63 bne t5,t4,800001f0 - -000000008000015c : - 8000015c: 800000b7 lui ra,0x80000 - 80000160: 00100113 li sp,1 - 80000164: 0220ef3b remw t5,ra,sp - 80000168: 00000e93 li t4,0 - 8000016c: 00600193 li gp,6 - 80000170: 09df1063 bne t5,t4,800001f0 - -0000000080000174 : - 80000174: 800000b7 lui ra,0x80000 - 80000178: fff00113 li sp,-1 - 8000017c: 0220ef3b remw t5,ra,sp - 80000180: 00000e93 li t4,0 - 80000184: 00700193 li gp,7 - 80000188: 07df1463 bne t5,t4,800001f0 - -000000008000018c : - 8000018c: 800000b7 lui ra,0x80000 - 80000190: 00000113 li sp,0 - 80000194: 0220ef3b remw t5,ra,sp - 80000198: 80000eb7 lui t4,0x80000 - 8000019c: 00800193 li gp,8 - 800001a0: 05df1863 bne t5,t4,800001f0 - -00000000800001a4 : - 800001a4: 00100093 li ra,1 - 800001a8: 00000113 li sp,0 - 800001ac: 0220ef3b remw t5,ra,sp - 800001b0: 00100e93 li t4,1 - 800001b4: 00900193 li gp,9 - 800001b8: 03df1c63 bne t5,t4,800001f0 - -00000000800001bc : - 800001bc: 00000093 li ra,0 - 800001c0: 00000113 li sp,0 - 800001c4: 0220ef3b remw t5,ra,sp - 800001c8: 00000e93 li t4,0 - 800001cc: 00a00193 li gp,10 - 800001d0: 03df1063 bne t5,t4,800001f0 - -00000000800001d4 : - 800001d4: 89700093 li ra,-1897 - 800001d8: 00000113 li sp,0 - 800001dc: 0220ef3b remw t5,ra,sp - 800001e0: 89700e93 li t4,-1897 - 800001e4: 00b00193 li gp,11 - 800001e8: 01df1463 bne t5,t4,800001f0 - 800001ec: 00301c63 bne zero,gp,80000204 - -00000000800001f0 : - 800001f0: 0ff0000f fence - 800001f4: 00018063 beqz gp,800001f4 - 800001f8: 00119193 slli gp,gp,0x1 - 800001fc: 0011e193 ori gp,gp,1 - 80000200: 00000073 ecall - -0000000080000204 : - 80000204: 0ff0000f fence - 80000208: 00100193 li gp,1 - 8000020c: 00000073 ecall - 80000210: c0001073 unimp - 80000214: 0000 unimp - 80000216: 0000 unimp - 80000218: 0000 unimp - 8000021a: 0000 unimp - 8000021c: 0000 unimp - 8000021e: 0000 unimp - 80000220: 0000 unimp - 80000222: 0000 unimp - 80000224: 0000 unimp - 80000226: 0000 unimp - 80000228: 0000 unimp - 8000022a: 0000 unimp - 8000022c: 0000 unimp - 8000022e: 0000 unimp - 80000230: 0000 unimp - 80000232: 0000 unimp - 80000234: 0000 unimp - 80000236: 0000 unimp - 80000238: 0000 unimp - 8000023a: 0000 unimp - 8000023c: 0000 unimp - 8000023e: 0000 unimp - 80000240: 0000 unimp - 80000242: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-remw.elf b/test/riscv/tests/rv64um-p-remw.elf deleted file mode 100644 index 55798a6e..00000000 Binary files a/test/riscv/tests/rv64um-p-remw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-v-div.dump b/test/riscv/tests/rv64um-v-div.dump deleted file mode 100644 index bfc4ab13..00000000 --- a/test/riscv/tests/rv64um-v-div.dump +++ /dev/null @@ -1,916 +0,0 @@ - -rv64um-v-div: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 78068693 addi a3,a3,1920 # 80002bd8 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 7b460613 addi a2,a2,1972 # 80002c68 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 77c60613 addi a2,a2,1916 # 80002c80 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 6cc68693 addi a3,a3,1740 # 80002c20 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 6e868693 addi a3,a3,1768 # 80002d58 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 66860613 addi a2,a2,1640 # 80002d30 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 59c68693 addi a3,a3,1436 # 80002d88 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 4bc68693 addi a3,a3,1212 # 80002cf8 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 44c68693 addi a3,a3,1100 # 80002cc0 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 03c00793 li a5,60 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 07a167b7 lui a5,0x7a16 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: cc378793 addi a5,a5,-829 # 7a15cc3 <_start-0x785ea33d> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 01400093 li ra,20 - 80002acc: 00600113 li sp,6 - 80002ad0: 0220cf33 div t5,ra,sp - 80002ad4: 00300e93 li t4,3 - 80002ad8: 00200193 li gp,2 - 80002adc: 0ddf1e63 bne t5,t4,80002bb8 - -0000000080002ae0 : - 80002ae0: fec00093 li ra,-20 - 80002ae4: 00600113 li sp,6 - 80002ae8: 0220cf33 div t5,ra,sp - 80002aec: ffd00e93 li t4,-3 - 80002af0: 00300193 li gp,3 - 80002af4: 0ddf1263 bne t5,t4,80002bb8 - -0000000080002af8 : - 80002af8: 01400093 li ra,20 - 80002afc: ffa00113 li sp,-6 - 80002b00: 0220cf33 div t5,ra,sp - 80002b04: ffd00e93 li t4,-3 - 80002b08: 00400193 li gp,4 - 80002b0c: 0bdf1663 bne t5,t4,80002bb8 - -0000000080002b10 : - 80002b10: fec00093 li ra,-20 - 80002b14: ffa00113 li sp,-6 - 80002b18: 0220cf33 div t5,ra,sp - 80002b1c: 00300e93 li t4,3 - 80002b20: 00500193 li gp,5 - 80002b24: 09df1a63 bne t5,t4,80002bb8 - -0000000080002b28 : - 80002b28: fff0009b addiw ra,zero,-1 - 80002b2c: 03f09093 slli ra,ra,0x3f - 80002b30: 00100113 li sp,1 - 80002b34: 0220cf33 div t5,ra,sp - 80002b38: fff00e9b addiw t4,zero,-1 - 80002b3c: 03fe9e93 slli t4,t4,0x3f - 80002b40: 00600193 li gp,6 - 80002b44: 07df1a63 bne t5,t4,80002bb8 - -0000000080002b48 : - 80002b48: fff0009b addiw ra,zero,-1 - 80002b4c: 03f09093 slli ra,ra,0x3f - 80002b50: fff00113 li sp,-1 - 80002b54: 0220cf33 div t5,ra,sp - 80002b58: fff00e9b addiw t4,zero,-1 - 80002b5c: 03fe9e93 slli t4,t4,0x3f - 80002b60: 00700193 li gp,7 - 80002b64: 05df1a63 bne t5,t4,80002bb8 - -0000000080002b68 : - 80002b68: fff0009b addiw ra,zero,-1 - 80002b6c: 03f09093 slli ra,ra,0x3f - 80002b70: 00000113 li sp,0 - 80002b74: 0220cf33 div t5,ra,sp - 80002b78: fff00e93 li t4,-1 - 80002b7c: 00800193 li gp,8 - 80002b80: 03df1c63 bne t5,t4,80002bb8 - -0000000080002b84 : - 80002b84: 00100093 li ra,1 - 80002b88: 00000113 li sp,0 - 80002b8c: 0220cf33 div t5,ra,sp - 80002b90: fff00e93 li t4,-1 - 80002b94: 00900193 li gp,9 - 80002b98: 03df1063 bne t5,t4,80002bb8 - -0000000080002b9c : - 80002b9c: 00000093 li ra,0 - 80002ba0: 00000113 li sp,0 - 80002ba4: 0220cf33 div t5,ra,sp - 80002ba8: fff00e93 li t4,-1 - 80002bac: 00a00193 li gp,10 - 80002bb0: 01df1463 bne t5,t4,80002bb8 - 80002bb4: 00301a63 bne zero,gp,80002bc8 - -0000000080002bb8 : - 80002bb8: 00119513 slli a0,gp,0x1 - 80002bbc: 00050063 beqz a0,80002bbc - 80002bc0: 00156513 ori a0,a0,1 - 80002bc4: 00000073 ecall - -0000000080002bc8 : - 80002bc8: 00100513 li a0,1 - 80002bcc: 00000073 ecall - 80002bd0: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-div.elf b/test/riscv/tests/rv64um-v-div.elf deleted file mode 100644 index 3374b8ae..00000000 Binary files a/test/riscv/tests/rv64um-v-div.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-v-divu.dump b/test/riscv/tests/rv64um-v-divu.dump deleted file mode 100644 index 68b9aab4..00000000 --- a/test/riscv/tests/rv64um-v-divu.dump +++ /dev/null @@ -1,922 +0,0 @@ - -rv64um-v-divu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 79868693 addi a3,a3,1944 # 80002bf0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 7cc60613 addi a2,a2,1996 # 80002c80 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 79460613 addi a2,a2,1940 # 80002c98 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 6e468693 addi a3,a3,1764 # 80002c38 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 70068693 addi a3,a3,1792 # 80002d70 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 68060613 addi a2,a2,1664 # 80002d48 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 5b468693 addi a3,a3,1460 # 80002da0 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 4d468693 addi a3,a3,1236 # 80002d10 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 46468693 addi a3,a3,1124 # 80002cd8 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 01c00793 li a5,28 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0472c7b7 lui a5,0x472c - 80002a70: 000805b7 lui a1,0x80 - 80002a74: f1278793 addi a5,a5,-238 # 472bf12 <_start-0x7b8d40ee> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 01400093 li ra,20 - 80002acc: 00600113 li sp,6 - 80002ad0: 0220df33 divu t5,ra,sp - 80002ad4: 00300e93 li t4,3 - 80002ad8: 00200193 li gp,2 - 80002adc: 0fdf1a63 bne t5,t4,80002bd0 - -0000000080002ae0 : - 80002ae0: fec00093 li ra,-20 - 80002ae4: 00600113 li sp,6 - 80002ae8: 0220df33 divu t5,ra,sp - 80002aec: 02aabeb7 lui t4,0x2aab - 80002af0: aabe8e9b addiw t4,t4,-1365 - 80002af4: 00ce9e93 slli t4,t4,0xc - 80002af8: aabe8e93 addi t4,t4,-1365 # 2aaaaab <_start-0x7d555555> - 80002afc: 00ce9e93 slli t4,t4,0xc - 80002b00: aabe8e93 addi t4,t4,-1365 - 80002b04: 00ce9e93 slli t4,t4,0xc - 80002b08: aa7e8e93 addi t4,t4,-1369 - 80002b0c: 00300193 li gp,3 - 80002b10: 0ddf1063 bne t5,t4,80002bd0 - -0000000080002b14 : - 80002b14: 01400093 li ra,20 - 80002b18: ffa00113 li sp,-6 - 80002b1c: 0220df33 divu t5,ra,sp - 80002b20: 00000e93 li t4,0 - 80002b24: 00400193 li gp,4 - 80002b28: 0bdf1463 bne t5,t4,80002bd0 - -0000000080002b2c : - 80002b2c: fec00093 li ra,-20 - 80002b30: ffa00113 li sp,-6 - 80002b34: 0220df33 divu t5,ra,sp - 80002b38: 00000e93 li t4,0 - 80002b3c: 00500193 li gp,5 - 80002b40: 09df1863 bne t5,t4,80002bd0 - -0000000080002b44 : - 80002b44: fff0009b addiw ra,zero,-1 - 80002b48: 03f09093 slli ra,ra,0x3f - 80002b4c: 00100113 li sp,1 - 80002b50: 0220df33 divu t5,ra,sp - 80002b54: fff00e9b addiw t4,zero,-1 - 80002b58: 03fe9e93 slli t4,t4,0x3f - 80002b5c: 00600193 li gp,6 - 80002b60: 07df1863 bne t5,t4,80002bd0 - -0000000080002b64 : - 80002b64: fff0009b addiw ra,zero,-1 - 80002b68: 03f09093 slli ra,ra,0x3f - 80002b6c: fff00113 li sp,-1 - 80002b70: 0220df33 divu t5,ra,sp - 80002b74: 00000e93 li t4,0 - 80002b78: 00700193 li gp,7 - 80002b7c: 05df1a63 bne t5,t4,80002bd0 - -0000000080002b80 : - 80002b80: fff0009b addiw ra,zero,-1 - 80002b84: 03f09093 slli ra,ra,0x3f - 80002b88: 00000113 li sp,0 - 80002b8c: 0220df33 divu t5,ra,sp - 80002b90: fff00e93 li t4,-1 - 80002b94: 00800193 li gp,8 - 80002b98: 03df1c63 bne t5,t4,80002bd0 - -0000000080002b9c : - 80002b9c: 00100093 li ra,1 - 80002ba0: 00000113 li sp,0 - 80002ba4: 0220df33 divu t5,ra,sp - 80002ba8: fff00e93 li t4,-1 - 80002bac: 00900193 li gp,9 - 80002bb0: 03df1063 bne t5,t4,80002bd0 - -0000000080002bb4 : - 80002bb4: 00000093 li ra,0 - 80002bb8: 00000113 li sp,0 - 80002bbc: 0220df33 divu t5,ra,sp - 80002bc0: fff00e93 li t4,-1 - 80002bc4: 00a00193 li gp,10 - 80002bc8: 01df1463 bne t5,t4,80002bd0 - 80002bcc: 00301a63 bne zero,gp,80002be0 - -0000000080002bd0 : - 80002bd0: 00119513 slli a0,gp,0x1 - 80002bd4: 00050063 beqz a0,80002bd4 - 80002bd8: 00156513 ori a0,a0,1 - 80002bdc: 00000073 ecall - -0000000080002be0 : - 80002be0: 00100513 li a0,1 - 80002be4: 00000073 ecall - 80002be8: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-divu.elf b/test/riscv/tests/rv64um-v-divu.elf deleted file mode 100644 index 4eec5386..00000000 Binary files a/test/riscv/tests/rv64um-v-divu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-v-divuw.dump b/test/riscv/tests/rv64um-v-divuw.dump deleted file mode 100644 index 644f517e..00000000 --- a/test/riscv/tests/rv64um-v-divuw.dump +++ /dev/null @@ -1,914 +0,0 @@ - -rv64um-v-divuw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 77868693 addi a3,a3,1912 # 80002bd0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 7ac60613 addi a2,a2,1964 # 80002c60 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 77460613 addi a2,a2,1908 # 80002c78 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 6c468693 addi a3,a3,1732 # 80002c18 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 6e068693 addi a3,a3,1760 # 80002d50 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 66060613 addi a2,a2,1632 # 80002d28 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 59468693 addi a3,a3,1428 # 80002d80 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 4b468693 addi a3,a3,1204 # 80002cf0 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 44468693 addi a3,a3,1092 # 80002cb8 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 02f00793 li a5,47 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0a3e47b7 lui a5,0xa3e4 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 49e78793 addi a5,a5,1182 # a3e449e <_start-0x75c1bb62> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 01400093 li ra,20 - 80002acc: 00600113 li sp,6 - 80002ad0: 0220df3b divuw t5,ra,sp - 80002ad4: 00300e93 li t4,3 - 80002ad8: 00200193 li gp,2 - 80002adc: 0ddf1a63 bne t5,t4,80002bb0 - -0000000080002ae0 : - 80002ae0: 0010009b addiw ra,zero,1 - 80002ae4: 02009093 slli ra,ra,0x20 - 80002ae8: fec08093 addi ra,ra,-20 - 80002aec: 00600113 li sp,6 - 80002af0: 0220df3b divuw t5,ra,sp - 80002af4: 2aaabeb7 lui t4,0x2aaab - 80002af8: aa7e8e9b addiw t4,t4,-1369 - 80002afc: 00300193 li gp,3 - 80002b00: 0bdf1863 bne t5,t4,80002bb0 - -0000000080002b04 : - 80002b04: 01400093 li ra,20 - 80002b08: ffa00113 li sp,-6 - 80002b0c: 0220df3b divuw t5,ra,sp - 80002b10: 00000e93 li t4,0 - 80002b14: 00400193 li gp,4 - 80002b18: 09df1c63 bne t5,t4,80002bb0 - -0000000080002b1c : - 80002b1c: fec00093 li ra,-20 - 80002b20: ffa00113 li sp,-6 - 80002b24: 0220df3b divuw t5,ra,sp - 80002b28: 00000e93 li t4,0 - 80002b2c: 00500193 li gp,5 - 80002b30: 09df1063 bne t5,t4,80002bb0 - -0000000080002b34 : - 80002b34: 800000b7 lui ra,0x80000 - 80002b38: 00100113 li sp,1 - 80002b3c: 0220df3b divuw t5,ra,sp - 80002b40: 80000eb7 lui t4,0x80000 - 80002b44: 00600193 li gp,6 - 80002b48: 07df1463 bne t5,t4,80002bb0 - -0000000080002b4c : - 80002b4c: 800000b7 lui ra,0x80000 - 80002b50: fff00113 li sp,-1 - 80002b54: 0220df3b divuw t5,ra,sp - 80002b58: 00000e93 li t4,0 - 80002b5c: 00700193 li gp,7 - 80002b60: 05df1863 bne t5,t4,80002bb0 - -0000000080002b64 : - 80002b64: 800000b7 lui ra,0x80000 - 80002b68: 00000113 li sp,0 - 80002b6c: 0220df3b divuw t5,ra,sp - 80002b70: fff00e93 li t4,-1 - 80002b74: 00800193 li gp,8 - 80002b78: 03df1c63 bne t5,t4,80002bb0 - -0000000080002b7c : - 80002b7c: 00100093 li ra,1 - 80002b80: 00000113 li sp,0 - 80002b84: 0220df3b divuw t5,ra,sp - 80002b88: fff00e93 li t4,-1 - 80002b8c: 00900193 li gp,9 - 80002b90: 03df1063 bne t5,t4,80002bb0 - -0000000080002b94 : - 80002b94: 00000093 li ra,0 - 80002b98: 00000113 li sp,0 - 80002b9c: 0220df3b divuw t5,ra,sp - 80002ba0: fff00e93 li t4,-1 - 80002ba4: 00a00193 li gp,10 - 80002ba8: 01df1463 bne t5,t4,80002bb0 - 80002bac: 00301a63 bne zero,gp,80002bc0 - -0000000080002bb0 : - 80002bb0: 00119513 slli a0,gp,0x1 - 80002bb4: 00050063 beqz a0,80002bb4 - 80002bb8: 00156513 ori a0,a0,1 - 80002bbc: 00000073 ecall - -0000000080002bc0 : - 80002bc0: 00100513 li a0,1 - 80002bc4: 00000073 ecall - 80002bc8: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-divuw.elf b/test/riscv/tests/rv64um-v-divuw.elf deleted file mode 100644 index f5ae7cb1..00000000 Binary files a/test/riscv/tests/rv64um-v-divuw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-v-divw.dump b/test/riscv/tests/rv64um-v-divw.dump deleted file mode 100644 index e2ba647c..00000000 --- a/test/riscv/tests/rv64um-v-divw.dump +++ /dev/null @@ -1,911 +0,0 @@ - -rv64um-v-divw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 76868693 addi a3,a3,1896 # 80002bc0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 79c60613 addi a2,a2,1948 # 80002c50 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 76460613 addi a2,a2,1892 # 80002c68 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 6b468693 addi a3,a3,1716 # 80002c08 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 6d068693 addi a3,a3,1744 # 80002d40 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 65060613 addi a2,a2,1616 # 80002d18 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 58468693 addi a3,a3,1412 # 80002d70 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 4a468693 addi a3,a3,1188 # 80002ce0 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 43468693 addi a3,a3,1076 # 80002ca8 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 01700793 li a5,23 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 026ec7b7 lui a5,0x26ec - 80002a70: 000805b7 lui a1,0x80 - 80002a74: f8e78793 addi a5,a5,-114 # 26ebf8e <_start-0x7d914072> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 01400093 li ra,20 - 80002acc: 00600113 li sp,6 - 80002ad0: 0220cf3b divw t5,ra,sp - 80002ad4: 00300e93 li t4,3 - 80002ad8: 00200193 li gp,2 - 80002adc: 0ddf1463 bne t5,t4,80002ba4 - -0000000080002ae0 : - 80002ae0: fec00093 li ra,-20 - 80002ae4: 00600113 li sp,6 - 80002ae8: 0220cf3b divw t5,ra,sp - 80002aec: ffd00e93 li t4,-3 - 80002af0: 00300193 li gp,3 - 80002af4: 0bdf1863 bne t5,t4,80002ba4 - -0000000080002af8 : - 80002af8: 01400093 li ra,20 - 80002afc: ffa00113 li sp,-6 - 80002b00: 0220cf3b divw t5,ra,sp - 80002b04: ffd00e93 li t4,-3 - 80002b08: 00400193 li gp,4 - 80002b0c: 09df1c63 bne t5,t4,80002ba4 - -0000000080002b10 : - 80002b10: fec00093 li ra,-20 - 80002b14: ffa00113 li sp,-6 - 80002b18: 0220cf3b divw t5,ra,sp - 80002b1c: 00300e93 li t4,3 - 80002b20: 00500193 li gp,5 - 80002b24: 09df1063 bne t5,t4,80002ba4 - -0000000080002b28 : - 80002b28: 800000b7 lui ra,0x80000 - 80002b2c: 00100113 li sp,1 - 80002b30: 0220cf3b divw t5,ra,sp - 80002b34: 80000eb7 lui t4,0x80000 - 80002b38: 00600193 li gp,6 - 80002b3c: 07df1463 bne t5,t4,80002ba4 - -0000000080002b40 : - 80002b40: 800000b7 lui ra,0x80000 - 80002b44: fff00113 li sp,-1 - 80002b48: 0220cf3b divw t5,ra,sp - 80002b4c: 80000eb7 lui t4,0x80000 - 80002b50: 00700193 li gp,7 - 80002b54: 05df1863 bne t5,t4,80002ba4 - -0000000080002b58 : - 80002b58: 800000b7 lui ra,0x80000 - 80002b5c: 00000113 li sp,0 - 80002b60: 0220cf3b divw t5,ra,sp - 80002b64: fff00e93 li t4,-1 - 80002b68: 00800193 li gp,8 - 80002b6c: 03df1c63 bne t5,t4,80002ba4 - -0000000080002b70 : - 80002b70: 00100093 li ra,1 - 80002b74: 00000113 li sp,0 - 80002b78: 0220cf3b divw t5,ra,sp - 80002b7c: fff00e93 li t4,-1 - 80002b80: 00900193 li gp,9 - 80002b84: 03df1063 bne t5,t4,80002ba4 - -0000000080002b88 : - 80002b88: 00000093 li ra,0 - 80002b8c: 00000113 li sp,0 - 80002b90: 0220cf3b divw t5,ra,sp - 80002b94: fff00e93 li t4,-1 - 80002b98: 00a00193 li gp,10 - 80002b9c: 01df1463 bne t5,t4,80002ba4 - 80002ba0: 00301a63 bne zero,gp,80002bb4 - -0000000080002ba4 : - 80002ba4: 00119513 slli a0,gp,0x1 - 80002ba8: 00050063 beqz a0,80002ba8 - 80002bac: 00156513 ori a0,a0,1 - 80002bb0: 00000073 ecall - -0000000080002bb4 : - 80002bb4: 00100513 li a0,1 - 80002bb8: 00000073 ecall - 80002bbc: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-divw.elf b/test/riscv/tests/rv64um-v-divw.elf deleted file mode 100644 index 1ecdfcfb..00000000 Binary files a/test/riscv/tests/rv64um-v-divw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-v-mul.dump b/test/riscv/tests/rv64um-v-mul.dump deleted file mode 100644 index 784ee417..00000000 --- a/test/riscv/tests/rv64um-v-mul.dump +++ /dev/null @@ -1,1209 +0,0 @@ - -rv64um-v-mul: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: b5868693 addi a3,a3,-1192 # 80002fb0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: b8c60613 addi a2,a2,-1140 # 80003040 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: b5460613 addi a2,a2,-1196 # 80003058 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: aa468693 addi a3,a3,-1372 # 80002ff8 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: ac068693 addi a3,a3,-1344 # 80003130 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: a4060613 addi a2,a2,-1472 # 80003108 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: 97468693 addi a3,a3,-1676 # 80003160 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 89468693 addi a3,a3,-1900 # 800030d0 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00001697 auipc a3,0x1 - 80002878: 82468693 addi a3,a3,-2012 # 80003098 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 02600793 li a5,38 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 054df7b7 lui a5,0x54df - 80002a70: 000805b7 lui a1,0x80 - 80002a74: b0278793 addi a5,a5,-1278 # 54deb02 <_start-0x7ab214fe> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 000080b7 lui ra,0x8 - 80002acc: e000809b addiw ra,ra,-512 - 80002ad0: 06db7137 lui sp,0x6db7 - 80002ad4: db71011b addiw sp,sp,-585 - 80002ad8: 00c11113 slli sp,sp,0xc - 80002adc: db710113 addi sp,sp,-585 # 6db6db7 <_start-0x79249249> - 80002ae0: 00c11113 slli sp,sp,0xc - 80002ae4: db710113 addi sp,sp,-585 - 80002ae8: 00c11113 slli sp,sp,0xc - 80002aec: db710113 addi sp,sp,-585 - 80002af0: 02208f33 mul t5,ra,sp - 80002af4: 00001eb7 lui t4,0x1 - 80002af8: 200e8e9b addiw t4,t4,512 - 80002afc: 02000193 li gp,32 - 80002b00: 49df1a63 bne t5,t4,80002f94 - -0000000080002b04 : - 80002b04: 000080b7 lui ra,0x8 - 80002b08: fc00809b addiw ra,ra,-64 - 80002b0c: 06db7137 lui sp,0x6db7 - 80002b10: db71011b addiw sp,sp,-585 - 80002b14: 00c11113 slli sp,sp,0xc - 80002b18: db710113 addi sp,sp,-585 # 6db6db7 <_start-0x79249249> - 80002b1c: 00c11113 slli sp,sp,0xc - 80002b20: db710113 addi sp,sp,-585 - 80002b24: 00c11113 slli sp,sp,0xc - 80002b28: db710113 addi sp,sp,-585 - 80002b2c: 02208f33 mul t5,ra,sp - 80002b30: 00001eb7 lui t4,0x1 - 80002b34: 240e8e9b addiw t4,t4,576 - 80002b38: 02100193 li gp,33 - 80002b3c: 45df1c63 bne t5,t4,80002f94 - -0000000080002b40 : - 80002b40: 00000093 li ra,0 - 80002b44: 00000113 li sp,0 - 80002b48: 02208f33 mul t5,ra,sp - 80002b4c: 00000e93 li t4,0 - 80002b50: 00200193 li gp,2 - 80002b54: 45df1063 bne t5,t4,80002f94 - -0000000080002b58 : - 80002b58: 00100093 li ra,1 - 80002b5c: 00100113 li sp,1 - 80002b60: 02208f33 mul t5,ra,sp - 80002b64: 00100e93 li t4,1 - 80002b68: 00300193 li gp,3 - 80002b6c: 43df1463 bne t5,t4,80002f94 - -0000000080002b70 : - 80002b70: 00300093 li ra,3 - 80002b74: 00700113 li sp,7 - 80002b78: 02208f33 mul t5,ra,sp - 80002b7c: 01500e93 li t4,21 - 80002b80: 00400193 li gp,4 - 80002b84: 41df1863 bne t5,t4,80002f94 - -0000000080002b88 : - 80002b88: 00000093 li ra,0 - 80002b8c: ffff8137 lui sp,0xffff8 - 80002b90: 02208f33 mul t5,ra,sp - 80002b94: 00000e93 li t4,0 - 80002b98: 00500193 li gp,5 - 80002b9c: 3fdf1c63 bne t5,t4,80002f94 - -0000000080002ba0 : - 80002ba0: 800000b7 lui ra,0x80000 - 80002ba4: 00000113 li sp,0 - 80002ba8: 02208f33 mul t5,ra,sp - 80002bac: 00000e93 li t4,0 - 80002bb0: 00600193 li gp,6 - 80002bb4: 3fdf1063 bne t5,t4,80002f94 - -0000000080002bb8 : - 80002bb8: 800000b7 lui ra,0x80000 - 80002bbc: ffff8137 lui sp,0xffff8 - 80002bc0: 02208f33 mul t5,ra,sp - 80002bc4: 00100e9b addiw t4,zero,1 - 80002bc8: 02ee9e93 slli t4,t4,0x2e - 80002bcc: 00700193 li gp,7 - 80002bd0: 3ddf1263 bne t5,t4,80002f94 - -0000000080002bd4 : - 80002bd4: faaab0b7 lui ra,0xfaaab - 80002bd8: aab0809b addiw ra,ra,-1365 - 80002bdc: 00c09093 slli ra,ra,0xc - 80002be0: aab08093 addi ra,ra,-1365 # fffffffffaaaaaab <_end+0xffffffff7aaa22bb> - 80002be4: 00c09093 slli ra,ra,0xc - 80002be8: aab08093 addi ra,ra,-1365 - 80002bec: 00c09093 slli ra,ra,0xc - 80002bf0: aab08093 addi ra,ra,-1365 - 80002bf4: 00030137 lui sp,0x30 - 80002bf8: e7d1011b addiw sp,sp,-387 - 80002bfc: 02208f33 mul t5,ra,sp - 80002c00: 00010eb7 lui t4,0x10 - 80002c04: f7fe8e9b addiw t4,t4,-129 - 80002c08: 01e00193 li gp,30 - 80002c0c: 39df1463 bne t5,t4,80002f94 - -0000000080002c10 : - 80002c10: 000300b7 lui ra,0x30 - 80002c14: e7d0809b addiw ra,ra,-387 - 80002c18: faaab137 lui sp,0xfaaab - 80002c1c: aab1011b addiw sp,sp,-1365 - 80002c20: 00c11113 slli sp,sp,0xc - 80002c24: aab10113 addi sp,sp,-1365 # fffffffffaaaaaab <_end+0xffffffff7aaa22bb> - 80002c28: 00c11113 slli sp,sp,0xc - 80002c2c: aab10113 addi sp,sp,-1365 - 80002c30: 00c11113 slli sp,sp,0xc - 80002c34: aab10113 addi sp,sp,-1365 - 80002c38: 02208f33 mul t5,ra,sp - 80002c3c: 00010eb7 lui t4,0x10 - 80002c40: f7fe8e9b addiw t4,t4,-129 - 80002c44: 01f00193 li gp,31 - 80002c48: 35df1663 bne t5,t4,80002f94 - -0000000080002c4c : - 80002c4c: 00d00093 li ra,13 - 80002c50: 00b00113 li sp,11 - 80002c54: 022080b3 mul ra,ra,sp - 80002c58: 08f00e93 li t4,143 - 80002c5c: 00800193 li gp,8 - 80002c60: 33d09a63 bne ra,t4,80002f94 - -0000000080002c64 : - 80002c64: 00e00093 li ra,14 - 80002c68: 00b00113 li sp,11 - 80002c6c: 02208133 mul sp,ra,sp - 80002c70: 09a00e93 li t4,154 - 80002c74: 00900193 li gp,9 - 80002c78: 31d11e63 bne sp,t4,80002f94 - -0000000080002c7c : - 80002c7c: 00d00093 li ra,13 - 80002c80: 021080b3 mul ra,ra,ra - 80002c84: 0a900e93 li t4,169 - 80002c88: 00a00193 li gp,10 - 80002c8c: 31d09463 bne ra,t4,80002f94 - -0000000080002c90 : - 80002c90: 00000213 li tp,0 - 80002c94: 00d00093 li ra,13 - 80002c98: 00b00113 li sp,11 - 80002c9c: 02208f33 mul t5,ra,sp - 80002ca0: 000f0313 mv t1,t5 - 80002ca4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ca8: 00200293 li t0,2 - 80002cac: fe5214e3 bne tp,t0,80002c94 - 80002cb0: 08f00e93 li t4,143 - 80002cb4: 00b00193 li gp,11 - 80002cb8: 2dd31e63 bne t1,t4,80002f94 - -0000000080002cbc : - 80002cbc: 00000213 li tp,0 - 80002cc0: 00e00093 li ra,14 - 80002cc4: 00b00113 li sp,11 - 80002cc8: 02208f33 mul t5,ra,sp - 80002ccc: 00000013 nop - 80002cd0: 000f0313 mv t1,t5 - 80002cd4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cd8: 00200293 li t0,2 - 80002cdc: fe5212e3 bne tp,t0,80002cc0 - 80002ce0: 09a00e93 li t4,154 - 80002ce4: 00c00193 li gp,12 - 80002ce8: 2bd31663 bne t1,t4,80002f94 - -0000000080002cec : - 80002cec: 00000213 li tp,0 - 80002cf0: 00f00093 li ra,15 - 80002cf4: 00b00113 li sp,11 - 80002cf8: 02208f33 mul t5,ra,sp - 80002cfc: 00000013 nop - 80002d00: 00000013 nop - 80002d04: 000f0313 mv t1,t5 - 80002d08: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d0c: 00200293 li t0,2 - 80002d10: fe5210e3 bne tp,t0,80002cf0 - 80002d14: 0a500e93 li t4,165 - 80002d18: 00d00193 li gp,13 - 80002d1c: 27d31c63 bne t1,t4,80002f94 - -0000000080002d20 : - 80002d20: 00000213 li tp,0 - 80002d24: 00d00093 li ra,13 - 80002d28: 00b00113 li sp,11 - 80002d2c: 02208f33 mul t5,ra,sp - 80002d30: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d34: 00200293 li t0,2 - 80002d38: fe5216e3 bne tp,t0,80002d24 - 80002d3c: 08f00e93 li t4,143 - 80002d40: 00e00193 li gp,14 - 80002d44: 25df1863 bne t5,t4,80002f94 - -0000000080002d48 : - 80002d48: 00000213 li tp,0 - 80002d4c: 00e00093 li ra,14 - 80002d50: 00b00113 li sp,11 - 80002d54: 00000013 nop - 80002d58: 02208f33 mul t5,ra,sp - 80002d5c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d60: 00200293 li t0,2 - 80002d64: fe5214e3 bne tp,t0,80002d4c - 80002d68: 09a00e93 li t4,154 - 80002d6c: 00f00193 li gp,15 - 80002d70: 23df1263 bne t5,t4,80002f94 - -0000000080002d74 : - 80002d74: 00000213 li tp,0 - 80002d78: 00f00093 li ra,15 - 80002d7c: 00b00113 li sp,11 - 80002d80: 00000013 nop - 80002d84: 00000013 nop - 80002d88: 02208f33 mul t5,ra,sp - 80002d8c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d90: 00200293 li t0,2 - 80002d94: fe5212e3 bne tp,t0,80002d78 - 80002d98: 0a500e93 li t4,165 - 80002d9c: 01000193 li gp,16 - 80002da0: 1fdf1a63 bne t5,t4,80002f94 - -0000000080002da4 : - 80002da4: 00000213 li tp,0 - 80002da8: 00d00093 li ra,13 - 80002dac: 00000013 nop - 80002db0: 00b00113 li sp,11 - 80002db4: 02208f33 mul t5,ra,sp - 80002db8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dbc: 00200293 li t0,2 - 80002dc0: fe5214e3 bne tp,t0,80002da8 - 80002dc4: 08f00e93 li t4,143 - 80002dc8: 01100193 li gp,17 - 80002dcc: 1ddf1463 bne t5,t4,80002f94 - -0000000080002dd0 : - 80002dd0: 00000213 li tp,0 - 80002dd4: 00e00093 li ra,14 - 80002dd8: 00000013 nop - 80002ddc: 00b00113 li sp,11 - 80002de0: 00000013 nop - 80002de4: 02208f33 mul t5,ra,sp - 80002de8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dec: 00200293 li t0,2 - 80002df0: fe5212e3 bne tp,t0,80002dd4 - 80002df4: 09a00e93 li t4,154 - 80002df8: 01200193 li gp,18 - 80002dfc: 19df1c63 bne t5,t4,80002f94 - -0000000080002e00 : - 80002e00: 00000213 li tp,0 - 80002e04: 00f00093 li ra,15 - 80002e08: 00000013 nop - 80002e0c: 00000013 nop - 80002e10: 00b00113 li sp,11 - 80002e14: 02208f33 mul t5,ra,sp - 80002e18: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e1c: 00200293 li t0,2 - 80002e20: fe5212e3 bne tp,t0,80002e04 - 80002e24: 0a500e93 li t4,165 - 80002e28: 01300193 li gp,19 - 80002e2c: 17df1463 bne t5,t4,80002f94 - -0000000080002e30 : - 80002e30: 00000213 li tp,0 - 80002e34: 00b00113 li sp,11 - 80002e38: 00d00093 li ra,13 - 80002e3c: 02208f33 mul t5,ra,sp - 80002e40: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e44: 00200293 li t0,2 - 80002e48: fe5216e3 bne tp,t0,80002e34 - 80002e4c: 08f00e93 li t4,143 - 80002e50: 01400193 li gp,20 - 80002e54: 15df1063 bne t5,t4,80002f94 - -0000000080002e58 : - 80002e58: 00000213 li tp,0 - 80002e5c: 00b00113 li sp,11 - 80002e60: 00e00093 li ra,14 - 80002e64: 00000013 nop - 80002e68: 02208f33 mul t5,ra,sp - 80002e6c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e70: 00200293 li t0,2 - 80002e74: fe5214e3 bne tp,t0,80002e5c - 80002e78: 09a00e93 li t4,154 - 80002e7c: 01500193 li gp,21 - 80002e80: 11df1a63 bne t5,t4,80002f94 - -0000000080002e84 : - 80002e84: 00000213 li tp,0 - 80002e88: 00b00113 li sp,11 - 80002e8c: 00f00093 li ra,15 - 80002e90: 00000013 nop - 80002e94: 00000013 nop - 80002e98: 02208f33 mul t5,ra,sp - 80002e9c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ea0: 00200293 li t0,2 - 80002ea4: fe5212e3 bne tp,t0,80002e88 - 80002ea8: 0a500e93 li t4,165 - 80002eac: 01600193 li gp,22 - 80002eb0: 0fdf1263 bne t5,t4,80002f94 - -0000000080002eb4 : - 80002eb4: 00000213 li tp,0 - 80002eb8: 00b00113 li sp,11 - 80002ebc: 00000013 nop - 80002ec0: 00d00093 li ra,13 - 80002ec4: 02208f33 mul t5,ra,sp - 80002ec8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ecc: 00200293 li t0,2 - 80002ed0: fe5214e3 bne tp,t0,80002eb8 - 80002ed4: 08f00e93 li t4,143 - 80002ed8: 01700193 li gp,23 - 80002edc: 0bdf1c63 bne t5,t4,80002f94 - -0000000080002ee0 : - 80002ee0: 00000213 li tp,0 - 80002ee4: 00b00113 li sp,11 - 80002ee8: 00000013 nop - 80002eec: 00e00093 li ra,14 - 80002ef0: 00000013 nop - 80002ef4: 02208f33 mul t5,ra,sp - 80002ef8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002efc: 00200293 li t0,2 - 80002f00: fe5212e3 bne tp,t0,80002ee4 - 80002f04: 09a00e93 li t4,154 - 80002f08: 01800193 li gp,24 - 80002f0c: 09df1463 bne t5,t4,80002f94 - -0000000080002f10 : - 80002f10: 00000213 li tp,0 - 80002f14: 00b00113 li sp,11 - 80002f18: 00000013 nop - 80002f1c: 00000013 nop - 80002f20: 00f00093 li ra,15 - 80002f24: 02208f33 mul t5,ra,sp - 80002f28: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f2c: 00200293 li t0,2 - 80002f30: fe5212e3 bne tp,t0,80002f14 - 80002f34: 0a500e93 li t4,165 - 80002f38: 01900193 li gp,25 - 80002f3c: 05df1c63 bne t5,t4,80002f94 - -0000000080002f40 : - 80002f40: 01f00093 li ra,31 - 80002f44: 02100133 mul sp,zero,ra - 80002f48: 00000e93 li t4,0 - 80002f4c: 01a00193 li gp,26 - 80002f50: 05d11263 bne sp,t4,80002f94 - -0000000080002f54 : - 80002f54: 02000093 li ra,32 - 80002f58: 02008133 mul sp,ra,zero - 80002f5c: 00000e93 li t4,0 - 80002f60: 01b00193 li gp,27 - 80002f64: 03d11863 bne sp,t4,80002f94 - -0000000080002f68 : - 80002f68: 020000b3 mul ra,zero,zero - 80002f6c: 00000e93 li t4,0 - 80002f70: 01c00193 li gp,28 - 80002f74: 03d09063 bne ra,t4,80002f94 - -0000000080002f78 : - 80002f78: 02100093 li ra,33 - 80002f7c: 02200113 li sp,34 - 80002f80: 02208033 mul zero,ra,sp - 80002f84: 00000e93 li t4,0 - 80002f88: 01d00193 li gp,29 - 80002f8c: 01d01463 bne zero,t4,80002f94 - 80002f90: 00301a63 bne zero,gp,80002fa4 - -0000000080002f94 : - 80002f94: 00119513 slli a0,gp,0x1 - 80002f98: 00050063 beqz a0,80002f98 - 80002f9c: 00156513 ori a0,a0,1 - 80002fa0: 00000073 ecall - -0000000080002fa4 : - 80002fa4: 00100513 li a0,1 - 80002fa8: 00000073 ecall - 80002fac: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-mul.elf b/test/riscv/tests/rv64um-v-mul.elf deleted file mode 100644 index 64107a2c..00000000 Binary files a/test/riscv/tests/rv64um-v-mul.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-v-mulh.dump b/test/riscv/tests/rv64um-v-mulh.dump deleted file mode 100644 index 17befcd4..00000000 --- a/test/riscv/tests/rv64um-v-mulh.dump +++ /dev/null @@ -1,1179 +0,0 @@ - -rv64um-v-mulh: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: b0068693 addi a3,a3,-1280 # 80002f58 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: b3460613 addi a2,a2,-1228 # 80002fe8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: afc60613 addi a2,a2,-1284 # 80003000 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: a4c68693 addi a3,a3,-1460 # 80002fa0 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: a6868693 addi a3,a3,-1432 # 800030d8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 9e860613 addi a2,a2,-1560 # 800030b0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: 91c68693 addi a3,a3,-1764 # 80003108 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 83c68693 addi a3,a3,-1988 # 80003078 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 7cc68693 addi a3,a3,1996 # 80003040 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 01700793 li a5,23 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0cb6d7b7 lui a5,0xcb6d - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 32278793 addi a5,a5,802 # cb6d322 <_start-0x73492cde> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000093 li ra,0 - 80002acc: 00000113 li sp,0 - 80002ad0: 02209f33 mulh t5,ra,sp - 80002ad4: 00000e93 li t4,0 - 80002ad8: 00200193 li gp,2 - 80002adc: 47df1063 bne t5,t4,80002f3c - -0000000080002ae0 : - 80002ae0: 00100093 li ra,1 - 80002ae4: 00100113 li sp,1 - 80002ae8: 02209f33 mulh t5,ra,sp - 80002aec: 00000e93 li t4,0 - 80002af0: 00300193 li gp,3 - 80002af4: 45df1463 bne t5,t4,80002f3c - -0000000080002af8 : - 80002af8: 00300093 li ra,3 - 80002afc: 00700113 li sp,7 - 80002b00: 02209f33 mulh t5,ra,sp - 80002b04: 00000e93 li t4,0 - 80002b08: 00400193 li gp,4 - 80002b0c: 43df1863 bne t5,t4,80002f3c - -0000000080002b10 : - 80002b10: 00000093 li ra,0 - 80002b14: ffff8137 lui sp,0xffff8 - 80002b18: 02209f33 mulh t5,ra,sp - 80002b1c: 00000e93 li t4,0 - 80002b20: 00500193 li gp,5 - 80002b24: 41df1c63 bne t5,t4,80002f3c - -0000000080002b28 : - 80002b28: 800000b7 lui ra,0x80000 - 80002b2c: 00000113 li sp,0 - 80002b30: 02209f33 mulh t5,ra,sp - 80002b34: 00000e93 li t4,0 - 80002b38: 00600193 li gp,6 - 80002b3c: 41df1063 bne t5,t4,80002f3c - -0000000080002b40 : - 80002b40: 800000b7 lui ra,0x80000 - 80002b44: ffff8137 lui sp,0xffff8 - 80002b48: 02209f33 mulh t5,ra,sp - 80002b4c: 00000e93 li t4,0 - 80002b50: 00700193 li gp,7 - 80002b54: 3fdf1463 bne t5,t4,80002f3c - -0000000080002b58 : - 80002b58: 00d0009b addiw ra,zero,13 - 80002b5c: 02009093 slli ra,ra,0x20 - 80002b60: 00b0011b addiw sp,zero,11 - 80002b64: 02011113 slli sp,sp,0x20 - 80002b68: 022090b3 mulh ra,ra,sp - 80002b6c: 08f00e93 li t4,143 - 80002b70: 00800193 li gp,8 - 80002b74: 3dd09463 bne ra,t4,80002f3c - -0000000080002b78 : - 80002b78: 0070009b addiw ra,zero,7 - 80002b7c: 02109093 slli ra,ra,0x21 - 80002b80: 00b0011b addiw sp,zero,11 - 80002b84: 02011113 slli sp,sp,0x20 - 80002b88: 02209133 mulh sp,ra,sp - 80002b8c: 09a00e93 li t4,154 - 80002b90: 00900193 li gp,9 - 80002b94: 3bd11463 bne sp,t4,80002f3c - -0000000080002b98 : - 80002b98: 00d0009b addiw ra,zero,13 - 80002b9c: 02009093 slli ra,ra,0x20 - 80002ba0: 021090b3 mulh ra,ra,ra - 80002ba4: 0a900e93 li t4,169 - 80002ba8: 00a00193 li gp,10 - 80002bac: 39d09863 bne ra,t4,80002f3c - -0000000080002bb0 : - 80002bb0: 00000213 li tp,0 - 80002bb4: 00d0009b addiw ra,zero,13 - 80002bb8: 02009093 slli ra,ra,0x20 - 80002bbc: 00b0011b addiw sp,zero,11 - 80002bc0: 02011113 slli sp,sp,0x20 - 80002bc4: 02209f33 mulh t5,ra,sp - 80002bc8: 000f0313 mv t1,t5 - 80002bcc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002bd0: 00200293 li t0,2 - 80002bd4: fe5210e3 bne tp,t0,80002bb4 - 80002bd8: 08f00e93 li t4,143 - 80002bdc: 00b00193 li gp,11 - 80002be0: 35d31e63 bne t1,t4,80002f3c - -0000000080002be4 : - 80002be4: 00000213 li tp,0 - 80002be8: 0070009b addiw ra,zero,7 - 80002bec: 02109093 slli ra,ra,0x21 - 80002bf0: 00b0011b addiw sp,zero,11 - 80002bf4: 02011113 slli sp,sp,0x20 - 80002bf8: 02209f33 mulh t5,ra,sp - 80002bfc: 00000013 nop - 80002c00: 000f0313 mv t1,t5 - 80002c04: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c08: 00200293 li t0,2 - 80002c0c: fc521ee3 bne tp,t0,80002be8 - 80002c10: 09a00e93 li t4,154 - 80002c14: 00c00193 li gp,12 - 80002c18: 33d31263 bne t1,t4,80002f3c - -0000000080002c1c : - 80002c1c: 00000213 li tp,0 - 80002c20: 00f0009b addiw ra,zero,15 - 80002c24: 02009093 slli ra,ra,0x20 - 80002c28: 00b0011b addiw sp,zero,11 - 80002c2c: 02011113 slli sp,sp,0x20 - 80002c30: 02209f33 mulh t5,ra,sp - 80002c34: 00000013 nop - 80002c38: 00000013 nop - 80002c3c: 000f0313 mv t1,t5 - 80002c40: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c44: 00200293 li t0,2 - 80002c48: fc521ce3 bne tp,t0,80002c20 - 80002c4c: 0a500e93 li t4,165 - 80002c50: 00d00193 li gp,13 - 80002c54: 2fd31463 bne t1,t4,80002f3c - -0000000080002c58 : - 80002c58: 00000213 li tp,0 - 80002c5c: 00d0009b addiw ra,zero,13 - 80002c60: 02009093 slli ra,ra,0x20 - 80002c64: 00b0011b addiw sp,zero,11 - 80002c68: 02011113 slli sp,sp,0x20 - 80002c6c: 02209f33 mulh t5,ra,sp - 80002c70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c74: 00200293 li t0,2 - 80002c78: fe5212e3 bne tp,t0,80002c5c - 80002c7c: 08f00e93 li t4,143 - 80002c80: 00e00193 li gp,14 - 80002c84: 2bdf1c63 bne t5,t4,80002f3c - -0000000080002c88 : - 80002c88: 00000213 li tp,0 - 80002c8c: 0070009b addiw ra,zero,7 - 80002c90: 02109093 slli ra,ra,0x21 - 80002c94: 00b0011b addiw sp,zero,11 - 80002c98: 02011113 slli sp,sp,0x20 - 80002c9c: 00000013 nop - 80002ca0: 02209f33 mulh t5,ra,sp - 80002ca4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ca8: 00200293 li t0,2 - 80002cac: fe5210e3 bne tp,t0,80002c8c - 80002cb0: 09a00e93 li t4,154 - 80002cb4: 00f00193 li gp,15 - 80002cb8: 29df1263 bne t5,t4,80002f3c - -0000000080002cbc : - 80002cbc: 00000213 li tp,0 - 80002cc0: 00f0009b addiw ra,zero,15 - 80002cc4: 02009093 slli ra,ra,0x20 - 80002cc8: 00b0011b addiw sp,zero,11 - 80002ccc: 02011113 slli sp,sp,0x20 - 80002cd0: 00000013 nop - 80002cd4: 00000013 nop - 80002cd8: 02209f33 mulh t5,ra,sp - 80002cdc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ce0: 00200293 li t0,2 - 80002ce4: fc521ee3 bne tp,t0,80002cc0 - 80002ce8: 0a500e93 li t4,165 - 80002cec: 01000193 li gp,16 - 80002cf0: 25df1663 bne t5,t4,80002f3c - -0000000080002cf4 : - 80002cf4: 00000213 li tp,0 - 80002cf8: 00d0009b addiw ra,zero,13 - 80002cfc: 02009093 slli ra,ra,0x20 - 80002d00: 00000013 nop - 80002d04: 00b0011b addiw sp,zero,11 - 80002d08: 02011113 slli sp,sp,0x20 - 80002d0c: 02209f33 mulh t5,ra,sp - 80002d10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d14: 00200293 li t0,2 - 80002d18: fe5210e3 bne tp,t0,80002cf8 - 80002d1c: 08f00e93 li t4,143 - 80002d20: 01100193 li gp,17 - 80002d24: 21df1c63 bne t5,t4,80002f3c - -0000000080002d28 : - 80002d28: 00000213 li tp,0 - 80002d2c: 0070009b addiw ra,zero,7 - 80002d30: 02109093 slli ra,ra,0x21 - 80002d34: 00000013 nop - 80002d38: 00b0011b addiw sp,zero,11 - 80002d3c: 02011113 slli sp,sp,0x20 - 80002d40: 00000013 nop - 80002d44: 02209f33 mulh t5,ra,sp - 80002d48: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d4c: 00200293 li t0,2 - 80002d50: fc521ee3 bne tp,t0,80002d2c - 80002d54: 09a00e93 li t4,154 - 80002d58: 01200193 li gp,18 - 80002d5c: 1fdf1063 bne t5,t4,80002f3c - -0000000080002d60 : - 80002d60: 00000213 li tp,0 - 80002d64: 00f0009b addiw ra,zero,15 - 80002d68: 02009093 slli ra,ra,0x20 - 80002d6c: 00000013 nop - 80002d70: 00000013 nop - 80002d74: 00b0011b addiw sp,zero,11 - 80002d78: 02011113 slli sp,sp,0x20 - 80002d7c: 02209f33 mulh t5,ra,sp - 80002d80: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d84: 00200293 li t0,2 - 80002d88: fc521ee3 bne tp,t0,80002d64 - 80002d8c: 0a500e93 li t4,165 - 80002d90: 01300193 li gp,19 - 80002d94: 1bdf1463 bne t5,t4,80002f3c - -0000000080002d98 : - 80002d98: 00000213 li tp,0 - 80002d9c: 00b0011b addiw sp,zero,11 - 80002da0: 02011113 slli sp,sp,0x20 - 80002da4: 00d0009b addiw ra,zero,13 - 80002da8: 02009093 slli ra,ra,0x20 - 80002dac: 02209f33 mulh t5,ra,sp - 80002db0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002db4: 00200293 li t0,2 - 80002db8: fe5212e3 bne tp,t0,80002d9c - 80002dbc: 08f00e93 li t4,143 - 80002dc0: 01400193 li gp,20 - 80002dc4: 17df1c63 bne t5,t4,80002f3c - -0000000080002dc8 : - 80002dc8: 00000213 li tp,0 - 80002dcc: 00b0011b addiw sp,zero,11 - 80002dd0: 02011113 slli sp,sp,0x20 - 80002dd4: 0070009b addiw ra,zero,7 - 80002dd8: 02109093 slli ra,ra,0x21 - 80002ddc: 00000013 nop - 80002de0: 02209f33 mulh t5,ra,sp - 80002de4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002de8: 00200293 li t0,2 - 80002dec: fe5210e3 bne tp,t0,80002dcc - 80002df0: 09a00e93 li t4,154 - 80002df4: 01500193 li gp,21 - 80002df8: 15df1263 bne t5,t4,80002f3c - -0000000080002dfc : - 80002dfc: 00000213 li tp,0 - 80002e00: 00b0011b addiw sp,zero,11 - 80002e04: 02011113 slli sp,sp,0x20 - 80002e08: 00f0009b addiw ra,zero,15 - 80002e0c: 02009093 slli ra,ra,0x20 - 80002e10: 00000013 nop - 80002e14: 00000013 nop - 80002e18: 02209f33 mulh t5,ra,sp - 80002e1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e20: 00200293 li t0,2 - 80002e24: fc521ee3 bne tp,t0,80002e00 - 80002e28: 0a500e93 li t4,165 - 80002e2c: 01600193 li gp,22 - 80002e30: 11df1663 bne t5,t4,80002f3c - -0000000080002e34 : - 80002e34: 00000213 li tp,0 - 80002e38: 00b0011b addiw sp,zero,11 - 80002e3c: 02011113 slli sp,sp,0x20 - 80002e40: 00000013 nop - 80002e44: 00d0009b addiw ra,zero,13 - 80002e48: 02009093 slli ra,ra,0x20 - 80002e4c: 02209f33 mulh t5,ra,sp - 80002e50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e54: 00200293 li t0,2 - 80002e58: fe5210e3 bne tp,t0,80002e38 - 80002e5c: 08f00e93 li t4,143 - 80002e60: 01700193 li gp,23 - 80002e64: 0ddf1c63 bne t5,t4,80002f3c - -0000000080002e68 : - 80002e68: 00000213 li tp,0 - 80002e6c: 00b0011b addiw sp,zero,11 - 80002e70: 02011113 slli sp,sp,0x20 - 80002e74: 00000013 nop - 80002e78: 0070009b addiw ra,zero,7 - 80002e7c: 02109093 slli ra,ra,0x21 - 80002e80: 00000013 nop - 80002e84: 02209f33 mulh t5,ra,sp - 80002e88: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e8c: 00200293 li t0,2 - 80002e90: fc521ee3 bne tp,t0,80002e6c - 80002e94: 09a00e93 li t4,154 - 80002e98: 01800193 li gp,24 - 80002e9c: 0bdf1063 bne t5,t4,80002f3c - -0000000080002ea0 : - 80002ea0: 00000213 li tp,0 - 80002ea4: 00b0011b addiw sp,zero,11 - 80002ea8: 02011113 slli sp,sp,0x20 - 80002eac: 00000013 nop - 80002eb0: 00000013 nop - 80002eb4: 00f0009b addiw ra,zero,15 - 80002eb8: 02009093 slli ra,ra,0x20 - 80002ebc: 02209f33 mulh t5,ra,sp - 80002ec0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ec4: 00200293 li t0,2 - 80002ec8: fc521ee3 bne tp,t0,80002ea4 - 80002ecc: 0a500e93 li t4,165 - 80002ed0: 01900193 li gp,25 - 80002ed4: 07df1463 bne t5,t4,80002f3c - -0000000080002ed8 : - 80002ed8: 01f0009b addiw ra,zero,31 - 80002edc: 02009093 slli ra,ra,0x20 - 80002ee0: 02101133 mulh sp,zero,ra - 80002ee4: 00000e93 li t4,0 - 80002ee8: 01a00193 li gp,26 - 80002eec: 05d11863 bne sp,t4,80002f3c - -0000000080002ef0 : - 80002ef0: 0010009b addiw ra,zero,1 - 80002ef4: 02509093 slli ra,ra,0x25 - 80002ef8: 02009133 mulh sp,ra,zero - 80002efc: 00000e93 li t4,0 - 80002f00: 01b00193 li gp,27 - 80002f04: 03d11c63 bne sp,t4,80002f3c - -0000000080002f08 : - 80002f08: 020010b3 mulh ra,zero,zero - 80002f0c: 00000e93 li t4,0 - 80002f10: 01c00193 li gp,28 - 80002f14: 03d09463 bne ra,t4,80002f3c - -0000000080002f18 : - 80002f18: 0210009b addiw ra,zero,33 - 80002f1c: 02009093 slli ra,ra,0x20 - 80002f20: 0110011b addiw sp,zero,17 - 80002f24: 02111113 slli sp,sp,0x21 - 80002f28: 02209033 mulh zero,ra,sp - 80002f2c: 00000e93 li t4,0 - 80002f30: 01d00193 li gp,29 - 80002f34: 01d01463 bne zero,t4,80002f3c - 80002f38: 00301a63 bne zero,gp,80002f4c - -0000000080002f3c : - 80002f3c: 00119513 slli a0,gp,0x1 - 80002f40: 00050063 beqz a0,80002f40 - 80002f44: 00156513 ori a0,a0,1 - 80002f48: 00000073 ecall - -0000000080002f4c : - 80002f4c: 00100513 li a0,1 - 80002f50: 00000073 ecall - 80002f54: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-mulh.elf b/test/riscv/tests/rv64um-v-mulh.elf deleted file mode 100644 index a644ac43..00000000 Binary files a/test/riscv/tests/rv64um-v-mulh.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-v-mulhsu.dump b/test/riscv/tests/rv64um-v-mulhsu.dump deleted file mode 100644 index 061224b6..00000000 --- a/test/riscv/tests/rv64um-v-mulhsu.dump +++ /dev/null @@ -1,1179 +0,0 @@ - -rv64um-v-mulhsu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: b0068693 addi a3,a3,-1280 # 80002f58 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: b3460613 addi a2,a2,-1228 # 80002fe8 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: afc60613 addi a2,a2,-1284 # 80003000 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: a4c68693 addi a3,a3,-1460 # 80002fa0 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: a6868693 addi a3,a3,-1432 # 800030d8 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 9e860613 addi a2,a2,-1560 # 800030b0 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: 91c68693 addi a3,a3,-1764 # 80003108 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 83c68693 addi a3,a3,-1988 # 80003078 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 7cc68693 addi a3,a3,1996 # 80003040 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 01000793 li a5,16 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 09a677b7 lui a5,0x9a67 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: d4078793 addi a5,a5,-704 # 9a66d40 <_start-0x765992c0> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000093 li ra,0 - 80002acc: 00000113 li sp,0 - 80002ad0: 0220af33 mulhsu t5,ra,sp - 80002ad4: 00000e93 li t4,0 - 80002ad8: 00200193 li gp,2 - 80002adc: 47df1063 bne t5,t4,80002f3c - -0000000080002ae0 : - 80002ae0: 00100093 li ra,1 - 80002ae4: 00100113 li sp,1 - 80002ae8: 0220af33 mulhsu t5,ra,sp - 80002aec: 00000e93 li t4,0 - 80002af0: 00300193 li gp,3 - 80002af4: 45df1463 bne t5,t4,80002f3c - -0000000080002af8 : - 80002af8: 00300093 li ra,3 - 80002afc: 00700113 li sp,7 - 80002b00: 0220af33 mulhsu t5,ra,sp - 80002b04: 00000e93 li t4,0 - 80002b08: 00400193 li gp,4 - 80002b0c: 43df1863 bne t5,t4,80002f3c - -0000000080002b10 : - 80002b10: 00000093 li ra,0 - 80002b14: ffff8137 lui sp,0xffff8 - 80002b18: 0220af33 mulhsu t5,ra,sp - 80002b1c: 00000e93 li t4,0 - 80002b20: 00500193 li gp,5 - 80002b24: 41df1c63 bne t5,t4,80002f3c - -0000000080002b28 : - 80002b28: 800000b7 lui ra,0x80000 - 80002b2c: 00000113 li sp,0 - 80002b30: 0220af33 mulhsu t5,ra,sp - 80002b34: 00000e93 li t4,0 - 80002b38: 00600193 li gp,6 - 80002b3c: 41df1063 bne t5,t4,80002f3c - -0000000080002b40 : - 80002b40: 800000b7 lui ra,0x80000 - 80002b44: ffff8137 lui sp,0xffff8 - 80002b48: 0220af33 mulhsu t5,ra,sp - 80002b4c: 80000eb7 lui t4,0x80000 - 80002b50: 00700193 li gp,7 - 80002b54: 3fdf1463 bne t5,t4,80002f3c - -0000000080002b58 : - 80002b58: 00d0009b addiw ra,zero,13 - 80002b5c: 02009093 slli ra,ra,0x20 - 80002b60: 00b0011b addiw sp,zero,11 - 80002b64: 02011113 slli sp,sp,0x20 - 80002b68: 0220a0b3 mulhsu ra,ra,sp - 80002b6c: 08f00e93 li t4,143 - 80002b70: 00800193 li gp,8 - 80002b74: 3dd09463 bne ra,t4,80002f3c - -0000000080002b78 : - 80002b78: 0070009b addiw ra,zero,7 - 80002b7c: 02109093 slli ra,ra,0x21 - 80002b80: 00b0011b addiw sp,zero,11 - 80002b84: 02011113 slli sp,sp,0x20 - 80002b88: 0220a133 mulhsu sp,ra,sp - 80002b8c: 09a00e93 li t4,154 - 80002b90: 00900193 li gp,9 - 80002b94: 3bd11463 bne sp,t4,80002f3c - -0000000080002b98 : - 80002b98: 00d0009b addiw ra,zero,13 - 80002b9c: 02009093 slli ra,ra,0x20 - 80002ba0: 0210a0b3 mulhsu ra,ra,ra - 80002ba4: 0a900e93 li t4,169 - 80002ba8: 00a00193 li gp,10 - 80002bac: 39d09863 bne ra,t4,80002f3c - -0000000080002bb0 : - 80002bb0: 00000213 li tp,0 - 80002bb4: 00d0009b addiw ra,zero,13 - 80002bb8: 02009093 slli ra,ra,0x20 - 80002bbc: 00b0011b addiw sp,zero,11 - 80002bc0: 02011113 slli sp,sp,0x20 - 80002bc4: 0220af33 mulhsu t5,ra,sp - 80002bc8: 000f0313 mv t1,t5 - 80002bcc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002bd0: 00200293 li t0,2 - 80002bd4: fe5210e3 bne tp,t0,80002bb4 - 80002bd8: 08f00e93 li t4,143 - 80002bdc: 00b00193 li gp,11 - 80002be0: 35d31e63 bne t1,t4,80002f3c - -0000000080002be4 : - 80002be4: 00000213 li tp,0 - 80002be8: 0070009b addiw ra,zero,7 - 80002bec: 02109093 slli ra,ra,0x21 - 80002bf0: 00b0011b addiw sp,zero,11 - 80002bf4: 02011113 slli sp,sp,0x20 - 80002bf8: 0220af33 mulhsu t5,ra,sp - 80002bfc: 00000013 nop - 80002c00: 000f0313 mv t1,t5 - 80002c04: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c08: 00200293 li t0,2 - 80002c0c: fc521ee3 bne tp,t0,80002be8 - 80002c10: 09a00e93 li t4,154 - 80002c14: 00c00193 li gp,12 - 80002c18: 33d31263 bne t1,t4,80002f3c - -0000000080002c1c : - 80002c1c: 00000213 li tp,0 - 80002c20: 00f0009b addiw ra,zero,15 - 80002c24: 02009093 slli ra,ra,0x20 - 80002c28: 00b0011b addiw sp,zero,11 - 80002c2c: 02011113 slli sp,sp,0x20 - 80002c30: 0220af33 mulhsu t5,ra,sp - 80002c34: 00000013 nop - 80002c38: 00000013 nop - 80002c3c: 000f0313 mv t1,t5 - 80002c40: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c44: 00200293 li t0,2 - 80002c48: fc521ce3 bne tp,t0,80002c20 - 80002c4c: 0a500e93 li t4,165 - 80002c50: 00d00193 li gp,13 - 80002c54: 2fd31463 bne t1,t4,80002f3c - -0000000080002c58 : - 80002c58: 00000213 li tp,0 - 80002c5c: 00d0009b addiw ra,zero,13 - 80002c60: 02009093 slli ra,ra,0x20 - 80002c64: 00b0011b addiw sp,zero,11 - 80002c68: 02011113 slli sp,sp,0x20 - 80002c6c: 0220af33 mulhsu t5,ra,sp - 80002c70: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c74: 00200293 li t0,2 - 80002c78: fe5212e3 bne tp,t0,80002c5c - 80002c7c: 08f00e93 li t4,143 - 80002c80: 00e00193 li gp,14 - 80002c84: 2bdf1c63 bne t5,t4,80002f3c - -0000000080002c88 : - 80002c88: 00000213 li tp,0 - 80002c8c: 0070009b addiw ra,zero,7 - 80002c90: 02109093 slli ra,ra,0x21 - 80002c94: 00b0011b addiw sp,zero,11 - 80002c98: 02011113 slli sp,sp,0x20 - 80002c9c: 00000013 nop - 80002ca0: 0220af33 mulhsu t5,ra,sp - 80002ca4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ca8: 00200293 li t0,2 - 80002cac: fe5210e3 bne tp,t0,80002c8c - 80002cb0: 09a00e93 li t4,154 - 80002cb4: 00f00193 li gp,15 - 80002cb8: 29df1263 bne t5,t4,80002f3c - -0000000080002cbc : - 80002cbc: 00000213 li tp,0 - 80002cc0: 00f0009b addiw ra,zero,15 - 80002cc4: 02009093 slli ra,ra,0x20 - 80002cc8: 00b0011b addiw sp,zero,11 - 80002ccc: 02011113 slli sp,sp,0x20 - 80002cd0: 00000013 nop - 80002cd4: 00000013 nop - 80002cd8: 0220af33 mulhsu t5,ra,sp - 80002cdc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ce0: 00200293 li t0,2 - 80002ce4: fc521ee3 bne tp,t0,80002cc0 - 80002ce8: 0a500e93 li t4,165 - 80002cec: 01000193 li gp,16 - 80002cf0: 25df1663 bne t5,t4,80002f3c - -0000000080002cf4 : - 80002cf4: 00000213 li tp,0 - 80002cf8: 00d0009b addiw ra,zero,13 - 80002cfc: 02009093 slli ra,ra,0x20 - 80002d00: 00000013 nop - 80002d04: 00b0011b addiw sp,zero,11 - 80002d08: 02011113 slli sp,sp,0x20 - 80002d0c: 0220af33 mulhsu t5,ra,sp - 80002d10: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d14: 00200293 li t0,2 - 80002d18: fe5210e3 bne tp,t0,80002cf8 - 80002d1c: 08f00e93 li t4,143 - 80002d20: 01100193 li gp,17 - 80002d24: 21df1c63 bne t5,t4,80002f3c - -0000000080002d28 : - 80002d28: 00000213 li tp,0 - 80002d2c: 0070009b addiw ra,zero,7 - 80002d30: 02109093 slli ra,ra,0x21 - 80002d34: 00000013 nop - 80002d38: 00b0011b addiw sp,zero,11 - 80002d3c: 02011113 slli sp,sp,0x20 - 80002d40: 00000013 nop - 80002d44: 0220af33 mulhsu t5,ra,sp - 80002d48: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d4c: 00200293 li t0,2 - 80002d50: fc521ee3 bne tp,t0,80002d2c - 80002d54: 09a00e93 li t4,154 - 80002d58: 01200193 li gp,18 - 80002d5c: 1fdf1063 bne t5,t4,80002f3c - -0000000080002d60 : - 80002d60: 00000213 li tp,0 - 80002d64: 00f0009b addiw ra,zero,15 - 80002d68: 02009093 slli ra,ra,0x20 - 80002d6c: 00000013 nop - 80002d70: 00000013 nop - 80002d74: 00b0011b addiw sp,zero,11 - 80002d78: 02011113 slli sp,sp,0x20 - 80002d7c: 0220af33 mulhsu t5,ra,sp - 80002d80: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d84: 00200293 li t0,2 - 80002d88: fc521ee3 bne tp,t0,80002d64 - 80002d8c: 0a500e93 li t4,165 - 80002d90: 01300193 li gp,19 - 80002d94: 1bdf1463 bne t5,t4,80002f3c - -0000000080002d98 : - 80002d98: 00000213 li tp,0 - 80002d9c: 00b0011b addiw sp,zero,11 - 80002da0: 02011113 slli sp,sp,0x20 - 80002da4: 00d0009b addiw ra,zero,13 - 80002da8: 02009093 slli ra,ra,0x20 - 80002dac: 0220af33 mulhsu t5,ra,sp - 80002db0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002db4: 00200293 li t0,2 - 80002db8: fe5212e3 bne tp,t0,80002d9c - 80002dbc: 08f00e93 li t4,143 - 80002dc0: 01400193 li gp,20 - 80002dc4: 17df1c63 bne t5,t4,80002f3c - -0000000080002dc8 : - 80002dc8: 00000213 li tp,0 - 80002dcc: 00b0011b addiw sp,zero,11 - 80002dd0: 02011113 slli sp,sp,0x20 - 80002dd4: 0070009b addiw ra,zero,7 - 80002dd8: 02109093 slli ra,ra,0x21 - 80002ddc: 00000013 nop - 80002de0: 0220af33 mulhsu t5,ra,sp - 80002de4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002de8: 00200293 li t0,2 - 80002dec: fe5210e3 bne tp,t0,80002dcc - 80002df0: 09a00e93 li t4,154 - 80002df4: 01500193 li gp,21 - 80002df8: 15df1263 bne t5,t4,80002f3c - -0000000080002dfc : - 80002dfc: 00000213 li tp,0 - 80002e00: 00b0011b addiw sp,zero,11 - 80002e04: 02011113 slli sp,sp,0x20 - 80002e08: 00f0009b addiw ra,zero,15 - 80002e0c: 02009093 slli ra,ra,0x20 - 80002e10: 00000013 nop - 80002e14: 00000013 nop - 80002e18: 0220af33 mulhsu t5,ra,sp - 80002e1c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e20: 00200293 li t0,2 - 80002e24: fc521ee3 bne tp,t0,80002e00 - 80002e28: 0a500e93 li t4,165 - 80002e2c: 01600193 li gp,22 - 80002e30: 11df1663 bne t5,t4,80002f3c - -0000000080002e34 : - 80002e34: 00000213 li tp,0 - 80002e38: 00b0011b addiw sp,zero,11 - 80002e3c: 02011113 slli sp,sp,0x20 - 80002e40: 00000013 nop - 80002e44: 00d0009b addiw ra,zero,13 - 80002e48: 02009093 slli ra,ra,0x20 - 80002e4c: 0220af33 mulhsu t5,ra,sp - 80002e50: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e54: 00200293 li t0,2 - 80002e58: fe5210e3 bne tp,t0,80002e38 - 80002e5c: 08f00e93 li t4,143 - 80002e60: 01700193 li gp,23 - 80002e64: 0ddf1c63 bne t5,t4,80002f3c - -0000000080002e68 : - 80002e68: 00000213 li tp,0 - 80002e6c: 00b0011b addiw sp,zero,11 - 80002e70: 02011113 slli sp,sp,0x20 - 80002e74: 00000013 nop - 80002e78: 0070009b addiw ra,zero,7 - 80002e7c: 02109093 slli ra,ra,0x21 - 80002e80: 00000013 nop - 80002e84: 0220af33 mulhsu t5,ra,sp - 80002e88: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e8c: 00200293 li t0,2 - 80002e90: fc521ee3 bne tp,t0,80002e6c - 80002e94: 09a00e93 li t4,154 - 80002e98: 01800193 li gp,24 - 80002e9c: 0bdf1063 bne t5,t4,80002f3c - -0000000080002ea0 : - 80002ea0: 00000213 li tp,0 - 80002ea4: 00b0011b addiw sp,zero,11 - 80002ea8: 02011113 slli sp,sp,0x20 - 80002eac: 00000013 nop - 80002eb0: 00000013 nop - 80002eb4: 00f0009b addiw ra,zero,15 - 80002eb8: 02009093 slli ra,ra,0x20 - 80002ebc: 0220af33 mulhsu t5,ra,sp - 80002ec0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ec4: 00200293 li t0,2 - 80002ec8: fc521ee3 bne tp,t0,80002ea4 - 80002ecc: 0a500e93 li t4,165 - 80002ed0: 01900193 li gp,25 - 80002ed4: 07df1463 bne t5,t4,80002f3c - -0000000080002ed8 : - 80002ed8: 01f0009b addiw ra,zero,31 - 80002edc: 02009093 slli ra,ra,0x20 - 80002ee0: 02102133 mulhsu sp,zero,ra - 80002ee4: 00000e93 li t4,0 - 80002ee8: 01a00193 li gp,26 - 80002eec: 05d11863 bne sp,t4,80002f3c - -0000000080002ef0 : - 80002ef0: 0010009b addiw ra,zero,1 - 80002ef4: 02509093 slli ra,ra,0x25 - 80002ef8: 0200a133 mulhsu sp,ra,zero - 80002efc: 00000e93 li t4,0 - 80002f00: 01b00193 li gp,27 - 80002f04: 03d11c63 bne sp,t4,80002f3c - -0000000080002f08 : - 80002f08: 020020b3 mulhsu ra,zero,zero - 80002f0c: 00000e93 li t4,0 - 80002f10: 01c00193 li gp,28 - 80002f14: 03d09463 bne ra,t4,80002f3c - -0000000080002f18 : - 80002f18: 0210009b addiw ra,zero,33 - 80002f1c: 02009093 slli ra,ra,0x20 - 80002f20: 0110011b addiw sp,zero,17 - 80002f24: 02111113 slli sp,sp,0x21 - 80002f28: 0220a033 mulhsu zero,ra,sp - 80002f2c: 00000e93 li t4,0 - 80002f30: 01d00193 li gp,29 - 80002f34: 01d01463 bne zero,t4,80002f3c - 80002f38: 00301a63 bne zero,gp,80002f4c - -0000000080002f3c : - 80002f3c: 00119513 slli a0,gp,0x1 - 80002f40: 00050063 beqz a0,80002f40 - 80002f44: 00156513 ori a0,a0,1 - 80002f48: 00000073 ecall - -0000000080002f4c : - 80002f4c: 00100513 li a0,1 - 80002f50: 00000073 ecall - 80002f54: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-mulhsu.elf b/test/riscv/tests/rv64um-v-mulhsu.elf deleted file mode 100644 index a8afeaa1..00000000 Binary files a/test/riscv/tests/rv64um-v-mulhsu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-v-mulhu.dump b/test/riscv/tests/rv64um-v-mulhu.dump deleted file mode 100644 index 85b66d05..00000000 --- a/test/riscv/tests/rv64um-v-mulhu.dump +++ /dev/null @@ -1,1215 +0,0 @@ - -rv64um-v-mulhu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: b8068693 addi a3,a3,-1152 # 80002fd8 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: bb460613 addi a2,a2,-1100 # 80003068 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: b7c60613 addi a2,a2,-1156 # 80003080 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: acc68693 addi a3,a3,-1332 # 80003020 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: ae868693 addi a3,a3,-1304 # 80003158 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: a6860613 addi a2,a2,-1432 # 80003130 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: 99c68693 addi a3,a3,-1636 # 80003188 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00001697 auipc a3,0x1 - 80002840: 8bc68693 addi a3,a3,-1860 # 800030f8 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00001697 auipc a3,0x1 - 80002878: 84c68693 addi a3,a3,-1972 # 800030c0 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 03200793 li a5,50 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0c0917b7 lui a5,0xc091 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 24978793 addi a5,a5,585 # c091249 <_start-0x73f6edb7> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000093 li ra,0 - 80002acc: 00000113 li sp,0 - 80002ad0: 0220bf33 mulhu t5,ra,sp - 80002ad4: 00000e93 li t4,0 - 80002ad8: 00200193 li gp,2 - 80002adc: 4fdf1063 bne t5,t4,80002fbc - -0000000080002ae0 : - 80002ae0: 00100093 li ra,1 - 80002ae4: 00100113 li sp,1 - 80002ae8: 0220bf33 mulhu t5,ra,sp - 80002aec: 00000e93 li t4,0 - 80002af0: 00300193 li gp,3 - 80002af4: 4ddf1463 bne t5,t4,80002fbc - -0000000080002af8 : - 80002af8: 00300093 li ra,3 - 80002afc: 00700113 li sp,7 - 80002b00: 0220bf33 mulhu t5,ra,sp - 80002b04: 00000e93 li t4,0 - 80002b08: 00400193 li gp,4 - 80002b0c: 4bdf1863 bne t5,t4,80002fbc - -0000000080002b10 : - 80002b10: 00000093 li ra,0 - 80002b14: ffff8137 lui sp,0xffff8 - 80002b18: 0220bf33 mulhu t5,ra,sp - 80002b1c: 00000e93 li t4,0 - 80002b20: 00500193 li gp,5 - 80002b24: 49df1c63 bne t5,t4,80002fbc - -0000000080002b28 : - 80002b28: 800000b7 lui ra,0x80000 - 80002b2c: 00000113 li sp,0 - 80002b30: 0220bf33 mulhu t5,ra,sp - 80002b34: 00000e93 li t4,0 - 80002b38: 00600193 li gp,6 - 80002b3c: 49df1063 bne t5,t4,80002fbc - -0000000080002b40 : - 80002b40: 800000b7 lui ra,0x80000 - 80002b44: ffff8137 lui sp,0xffff8 - 80002b48: 0220bf33 mulhu t5,ra,sp - 80002b4c: ffff0eb7 lui t4,0xffff0 - 80002b50: fffe8e9b addiw t4,t4,-1 - 80002b54: 00fe9e93 slli t4,t4,0xf - 80002b58: 00700193 li gp,7 - 80002b5c: 47df1063 bne t5,t4,80002fbc - -0000000080002b60 : - 80002b60: faaab0b7 lui ra,0xfaaab - 80002b64: aab0809b addiw ra,ra,-1365 - 80002b68: 00c09093 slli ra,ra,0xc - 80002b6c: aab08093 addi ra,ra,-1365 # fffffffffaaaaaab <_end+0xffffffff7aaa22bb> - 80002b70: 00c09093 slli ra,ra,0xc - 80002b74: aab08093 addi ra,ra,-1365 - 80002b78: 00c09093 slli ra,ra,0xc - 80002b7c: aab08093 addi ra,ra,-1365 - 80002b80: 00030137 lui sp,0x30 - 80002b84: e7d1011b addiw sp,sp,-387 - 80002b88: 0220bf33 mulhu t5,ra,sp - 80002b8c: 00020eb7 lui t4,0x20 - 80002b90: efee8e9b addiw t4,t4,-258 - 80002b94: 01e00193 li gp,30 - 80002b98: 43df1263 bne t5,t4,80002fbc - -0000000080002b9c : - 80002b9c: 000300b7 lui ra,0x30 - 80002ba0: e7d0809b addiw ra,ra,-387 - 80002ba4: faaab137 lui sp,0xfaaab - 80002ba8: aab1011b addiw sp,sp,-1365 - 80002bac: 00c11113 slli sp,sp,0xc - 80002bb0: aab10113 addi sp,sp,-1365 # fffffffffaaaaaab <_end+0xffffffff7aaa22bb> - 80002bb4: 00c11113 slli sp,sp,0xc - 80002bb8: aab10113 addi sp,sp,-1365 - 80002bbc: 00c11113 slli sp,sp,0xc - 80002bc0: aab10113 addi sp,sp,-1365 - 80002bc4: 0220bf33 mulhu t5,ra,sp - 80002bc8: 00020eb7 lui t4,0x20 - 80002bcc: efee8e9b addiw t4,t4,-258 - 80002bd0: 01f00193 li gp,31 - 80002bd4: 3fdf1463 bne t5,t4,80002fbc - -0000000080002bd8 : - 80002bd8: 00d0009b addiw ra,zero,13 - 80002bdc: 02009093 slli ra,ra,0x20 - 80002be0: 00b0011b addiw sp,zero,11 - 80002be4: 02011113 slli sp,sp,0x20 - 80002be8: 0220b0b3 mulhu ra,ra,sp - 80002bec: 08f00e93 li t4,143 - 80002bf0: 00800193 li gp,8 - 80002bf4: 3dd09463 bne ra,t4,80002fbc - -0000000080002bf8 : - 80002bf8: 0070009b addiw ra,zero,7 - 80002bfc: 02109093 slli ra,ra,0x21 - 80002c00: 00b0011b addiw sp,zero,11 - 80002c04: 02011113 slli sp,sp,0x20 - 80002c08: 0220b133 mulhu sp,ra,sp - 80002c0c: 09a00e93 li t4,154 - 80002c10: 00900193 li gp,9 - 80002c14: 3bd11463 bne sp,t4,80002fbc - -0000000080002c18 : - 80002c18: 00d0009b addiw ra,zero,13 - 80002c1c: 02009093 slli ra,ra,0x20 - 80002c20: 0210b0b3 mulhu ra,ra,ra - 80002c24: 0a900e93 li t4,169 - 80002c28: 00a00193 li gp,10 - 80002c2c: 39d09863 bne ra,t4,80002fbc - -0000000080002c30 : - 80002c30: 00000213 li tp,0 - 80002c34: 00d0009b addiw ra,zero,13 - 80002c38: 02009093 slli ra,ra,0x20 - 80002c3c: 00b0011b addiw sp,zero,11 - 80002c40: 02011113 slli sp,sp,0x20 - 80002c44: 0220bf33 mulhu t5,ra,sp - 80002c48: 000f0313 mv t1,t5 - 80002c4c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c50: 00200293 li t0,2 - 80002c54: fe5210e3 bne tp,t0,80002c34 - 80002c58: 08f00e93 li t4,143 - 80002c5c: 00b00193 li gp,11 - 80002c60: 35d31e63 bne t1,t4,80002fbc - -0000000080002c64 : - 80002c64: 00000213 li tp,0 - 80002c68: 0070009b addiw ra,zero,7 - 80002c6c: 02109093 slli ra,ra,0x21 - 80002c70: 00b0011b addiw sp,zero,11 - 80002c74: 02011113 slli sp,sp,0x20 - 80002c78: 0220bf33 mulhu t5,ra,sp - 80002c7c: 00000013 nop - 80002c80: 000f0313 mv t1,t5 - 80002c84: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c88: 00200293 li t0,2 - 80002c8c: fc521ee3 bne tp,t0,80002c68 - 80002c90: 09a00e93 li t4,154 - 80002c94: 00c00193 li gp,12 - 80002c98: 33d31263 bne t1,t4,80002fbc - -0000000080002c9c : - 80002c9c: 00000213 li tp,0 - 80002ca0: 00f0009b addiw ra,zero,15 - 80002ca4: 02009093 slli ra,ra,0x20 - 80002ca8: 00b0011b addiw sp,zero,11 - 80002cac: 02011113 slli sp,sp,0x20 - 80002cb0: 0220bf33 mulhu t5,ra,sp - 80002cb4: 00000013 nop - 80002cb8: 00000013 nop - 80002cbc: 000f0313 mv t1,t5 - 80002cc0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cc4: 00200293 li t0,2 - 80002cc8: fc521ce3 bne tp,t0,80002ca0 - 80002ccc: 0a500e93 li t4,165 - 80002cd0: 00d00193 li gp,13 - 80002cd4: 2fd31463 bne t1,t4,80002fbc - -0000000080002cd8 : - 80002cd8: 00000213 li tp,0 - 80002cdc: 00d0009b addiw ra,zero,13 - 80002ce0: 02009093 slli ra,ra,0x20 - 80002ce4: 00b0011b addiw sp,zero,11 - 80002ce8: 02011113 slli sp,sp,0x20 - 80002cec: 0220bf33 mulhu t5,ra,sp - 80002cf0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cf4: 00200293 li t0,2 - 80002cf8: fe5212e3 bne tp,t0,80002cdc - 80002cfc: 08f00e93 li t4,143 - 80002d00: 00e00193 li gp,14 - 80002d04: 2bdf1c63 bne t5,t4,80002fbc - -0000000080002d08 : - 80002d08: 00000213 li tp,0 - 80002d0c: 0070009b addiw ra,zero,7 - 80002d10: 02109093 slli ra,ra,0x21 - 80002d14: 00b0011b addiw sp,zero,11 - 80002d18: 02011113 slli sp,sp,0x20 - 80002d1c: 00000013 nop - 80002d20: 0220bf33 mulhu t5,ra,sp - 80002d24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d28: 00200293 li t0,2 - 80002d2c: fe5210e3 bne tp,t0,80002d0c - 80002d30: 09a00e93 li t4,154 - 80002d34: 00f00193 li gp,15 - 80002d38: 29df1263 bne t5,t4,80002fbc - -0000000080002d3c : - 80002d3c: 00000213 li tp,0 - 80002d40: 00f0009b addiw ra,zero,15 - 80002d44: 02009093 slli ra,ra,0x20 - 80002d48: 00b0011b addiw sp,zero,11 - 80002d4c: 02011113 slli sp,sp,0x20 - 80002d50: 00000013 nop - 80002d54: 00000013 nop - 80002d58: 0220bf33 mulhu t5,ra,sp - 80002d5c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d60: 00200293 li t0,2 - 80002d64: fc521ee3 bne tp,t0,80002d40 - 80002d68: 0a500e93 li t4,165 - 80002d6c: 01000193 li gp,16 - 80002d70: 25df1663 bne t5,t4,80002fbc - -0000000080002d74 : - 80002d74: 00000213 li tp,0 - 80002d78: 00d0009b addiw ra,zero,13 - 80002d7c: 02009093 slli ra,ra,0x20 - 80002d80: 00000013 nop - 80002d84: 00b0011b addiw sp,zero,11 - 80002d88: 02011113 slli sp,sp,0x20 - 80002d8c: 0220bf33 mulhu t5,ra,sp - 80002d90: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d94: 00200293 li t0,2 - 80002d98: fe5210e3 bne tp,t0,80002d78 - 80002d9c: 08f00e93 li t4,143 - 80002da0: 01100193 li gp,17 - 80002da4: 21df1c63 bne t5,t4,80002fbc - -0000000080002da8 : - 80002da8: 00000213 li tp,0 - 80002dac: 0070009b addiw ra,zero,7 - 80002db0: 02109093 slli ra,ra,0x21 - 80002db4: 00000013 nop - 80002db8: 00b0011b addiw sp,zero,11 - 80002dbc: 02011113 slli sp,sp,0x20 - 80002dc0: 00000013 nop - 80002dc4: 0220bf33 mulhu t5,ra,sp - 80002dc8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dcc: 00200293 li t0,2 - 80002dd0: fc521ee3 bne tp,t0,80002dac - 80002dd4: 09a00e93 li t4,154 - 80002dd8: 01200193 li gp,18 - 80002ddc: 1fdf1063 bne t5,t4,80002fbc - -0000000080002de0 : - 80002de0: 00000213 li tp,0 - 80002de4: 00f0009b addiw ra,zero,15 - 80002de8: 02009093 slli ra,ra,0x20 - 80002dec: 00000013 nop - 80002df0: 00000013 nop - 80002df4: 00b0011b addiw sp,zero,11 - 80002df8: 02011113 slli sp,sp,0x20 - 80002dfc: 0220bf33 mulhu t5,ra,sp - 80002e00: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e04: 00200293 li t0,2 - 80002e08: fc521ee3 bne tp,t0,80002de4 - 80002e0c: 0a500e93 li t4,165 - 80002e10: 01300193 li gp,19 - 80002e14: 1bdf1463 bne t5,t4,80002fbc - -0000000080002e18 : - 80002e18: 00000213 li tp,0 - 80002e1c: 00b0011b addiw sp,zero,11 - 80002e20: 02011113 slli sp,sp,0x20 - 80002e24: 00d0009b addiw ra,zero,13 - 80002e28: 02009093 slli ra,ra,0x20 - 80002e2c: 0220bf33 mulhu t5,ra,sp - 80002e30: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e34: 00200293 li t0,2 - 80002e38: fe5212e3 bne tp,t0,80002e1c - 80002e3c: 08f00e93 li t4,143 - 80002e40: 01400193 li gp,20 - 80002e44: 17df1c63 bne t5,t4,80002fbc - -0000000080002e48 : - 80002e48: 00000213 li tp,0 - 80002e4c: 00b0011b addiw sp,zero,11 - 80002e50: 02011113 slli sp,sp,0x20 - 80002e54: 0070009b addiw ra,zero,7 - 80002e58: 02109093 slli ra,ra,0x21 - 80002e5c: 00000013 nop - 80002e60: 0220bf33 mulhu t5,ra,sp - 80002e64: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e68: 00200293 li t0,2 - 80002e6c: fe5210e3 bne tp,t0,80002e4c - 80002e70: 09a00e93 li t4,154 - 80002e74: 01500193 li gp,21 - 80002e78: 15df1263 bne t5,t4,80002fbc - -0000000080002e7c : - 80002e7c: 00000213 li tp,0 - 80002e80: 00b0011b addiw sp,zero,11 - 80002e84: 02011113 slli sp,sp,0x20 - 80002e88: 00f0009b addiw ra,zero,15 - 80002e8c: 02009093 slli ra,ra,0x20 - 80002e90: 00000013 nop - 80002e94: 00000013 nop - 80002e98: 0220bf33 mulhu t5,ra,sp - 80002e9c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ea0: 00200293 li t0,2 - 80002ea4: fc521ee3 bne tp,t0,80002e80 - 80002ea8: 0a500e93 li t4,165 - 80002eac: 01600193 li gp,22 - 80002eb0: 11df1663 bne t5,t4,80002fbc - -0000000080002eb4 : - 80002eb4: 00000213 li tp,0 - 80002eb8: 00b0011b addiw sp,zero,11 - 80002ebc: 02011113 slli sp,sp,0x20 - 80002ec0: 00000013 nop - 80002ec4: 00d0009b addiw ra,zero,13 - 80002ec8: 02009093 slli ra,ra,0x20 - 80002ecc: 0220bf33 mulhu t5,ra,sp - 80002ed0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002ed4: 00200293 li t0,2 - 80002ed8: fe5210e3 bne tp,t0,80002eb8 - 80002edc: 08f00e93 li t4,143 - 80002ee0: 01700193 li gp,23 - 80002ee4: 0ddf1c63 bne t5,t4,80002fbc - -0000000080002ee8 : - 80002ee8: 00000213 li tp,0 - 80002eec: 00b0011b addiw sp,zero,11 - 80002ef0: 02011113 slli sp,sp,0x20 - 80002ef4: 00000013 nop - 80002ef8: 0070009b addiw ra,zero,7 - 80002efc: 02109093 slli ra,ra,0x21 - 80002f00: 00000013 nop - 80002f04: 0220bf33 mulhu t5,ra,sp - 80002f08: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f0c: 00200293 li t0,2 - 80002f10: fc521ee3 bne tp,t0,80002eec - 80002f14: 09a00e93 li t4,154 - 80002f18: 01800193 li gp,24 - 80002f1c: 0bdf1063 bne t5,t4,80002fbc - -0000000080002f20 : - 80002f20: 00000213 li tp,0 - 80002f24: 00b0011b addiw sp,zero,11 - 80002f28: 02011113 slli sp,sp,0x20 - 80002f2c: 00000013 nop - 80002f30: 00000013 nop - 80002f34: 00f0009b addiw ra,zero,15 - 80002f38: 02009093 slli ra,ra,0x20 - 80002f3c: 0220bf33 mulhu t5,ra,sp - 80002f40: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002f44: 00200293 li t0,2 - 80002f48: fc521ee3 bne tp,t0,80002f24 - 80002f4c: 0a500e93 li t4,165 - 80002f50: 01900193 li gp,25 - 80002f54: 07df1463 bne t5,t4,80002fbc - -0000000080002f58 : - 80002f58: 01f0009b addiw ra,zero,31 - 80002f5c: 02009093 slli ra,ra,0x20 - 80002f60: 02103133 mulhu sp,zero,ra - 80002f64: 00000e93 li t4,0 - 80002f68: 01a00193 li gp,26 - 80002f6c: 05d11863 bne sp,t4,80002fbc - -0000000080002f70 : - 80002f70: 0010009b addiw ra,zero,1 - 80002f74: 02509093 slli ra,ra,0x25 - 80002f78: 0200b133 mulhu sp,ra,zero - 80002f7c: 00000e93 li t4,0 - 80002f80: 01b00193 li gp,27 - 80002f84: 03d11c63 bne sp,t4,80002fbc - -0000000080002f88 : - 80002f88: 020030b3 mulhu ra,zero,zero - 80002f8c: 00000e93 li t4,0 - 80002f90: 01c00193 li gp,28 - 80002f94: 03d09463 bne ra,t4,80002fbc - -0000000080002f98 : - 80002f98: 0210009b addiw ra,zero,33 - 80002f9c: 02009093 slli ra,ra,0x20 - 80002fa0: 0110011b addiw sp,zero,17 - 80002fa4: 02111113 slli sp,sp,0x21 - 80002fa8: 0220b033 mulhu zero,ra,sp - 80002fac: 00000e93 li t4,0 - 80002fb0: 01d00193 li gp,29 - 80002fb4: 01d01463 bne zero,t4,80002fbc - 80002fb8: 00301a63 bne zero,gp,80002fcc - -0000000080002fbc : - 80002fbc: 00119513 slli a0,gp,0x1 - 80002fc0: 00050063 beqz a0,80002fc0 - 80002fc4: 00156513 ori a0,a0,1 - 80002fc8: 00000073 ecall - -0000000080002fcc : - 80002fcc: 00100513 li a0,1 - 80002fd0: 00000073 ecall - 80002fd4: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-mulhu.elf b/test/riscv/tests/rv64um-v-mulhu.elf deleted file mode 100644 index 62759c83..00000000 Binary files a/test/riscv/tests/rv64um-v-mulhu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-v-mulw.dump b/test/riscv/tests/rv64um-v-mulw.dump deleted file mode 100644 index 0d3598ff..00000000 --- a/test/riscv/tests/rv64um-v-mulw.dump +++ /dev/null @@ -1,1140 +0,0 @@ - -rv64um-v-mulw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00009117 auipc sp,0x9 - 8000001c: 6b810113 addi sp,sp,1720 # 800096d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00002617 auipc a2,0x2 - 80002318: cec60613 addi a2,a2,-788 # 80004000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00006797 auipc a5,0x6 - 80002334: 4b878793 addi a5,a5,1208 # 800087e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00006717 auipc a4,0x6 - 80002348: 49c70713 addi a4,a4,1180 # 800087e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00006897 auipc a7,0x6 - 80002354: 48f8bc23 sd a5,1176(a7) # 800087e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00006797 auipc a5,0x6 - 80002384: 07078793 addi a5,a5,112 # 800083f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf7810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00006797 auipc a5,0x6 - 80002448: 3807be23 sd zero,924(a5) # 800087e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00001697 auipc a3,0x1 - 8000245c: a6868693 addi a3,a3,-1432 # 80002ec0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00001617 auipc a2,0x1 - 800024b8: a9c60613 addi a2,a2,-1380 # 80002f50 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00001617 auipc a2,0x1 - 80002508: a6460613 addi a2,a2,-1436 # 80002f68 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00001697 auipc a3,0x1 - 80002558: 9b468693 addi a3,a3,-1612 # 80002f08 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00001697 auipc a3,0x1 - 80002674: 9d068693 addi a3,a3,-1584 # 80003040 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00001617 auipc a2,0x1 - 800026cc: 95060613 addi a2,a2,-1712 # 80003018 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00006d17 auipc s10,0x6 - 80002720: cd4d0d13 addi s10,s10,-812 # 800083f0 - 80002724: 00002b97 auipc s7,0x2 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80004000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00006a17 auipc s4,0x6 - 80002738: 0aca0a13 addi s4,s4,172 # 800087e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00006717 auipc a4,0x6 - 8000274c: 08f73c23 sd a5,152(a4) # 800087e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00006717 auipc a4,0x6 - 800027d4: 00f73823 sd a5,16(a4) # 800087e0 - 800027d8: 00006717 auipc a4,0x6 - 800027dc: 00f73823 sd a5,16(a4) # 800087e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00001697 auipc a3,0x1 - 800027f0: 88468693 addi a3,a3,-1916 # 80003070 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 7a468693 addi a3,a3,1956 # 80002fe0 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 73468693 addi a3,a3,1844 # 80002fa8 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00002697 auipc a3,0x2 - 800028e0: 72468693 addi a3,a3,1828 # 80005000 - 800028e4: 00003717 auipc a4,0x3 - 800028e8: 71c70713 addi a4,a4,1820 # 80006000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00004797 auipc a5,0x4 - 800028f8: 70c78793 addi a5,a5,1804 # 80007000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00001897 auipc a7,0x1 - 80002914: 6ed8b823 sd a3,1776(a7) # 80004000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00002697 auipc a3,0x2 - 80002920: 6ce6be23 sd a4,1756(a3) # 80004ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00001617 auipc a2,0x1 - 80002938: 6cc60613 addi a2,a2,1740 # 80004000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00004697 auipc a3,0x4 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80006ff8 - 8000294c: 00002717 auipc a4,0x2 - 80002950: 6af73a23 sd a5,1716(a4) # 80005000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00005697 auipc a3,0x5 - 800029c0: 64468693 addi a3,a3,1604 # 80008000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00006617 auipc a2,0x6 - 800029d0: e0f63e23 sd a5,-484(a2) # 800087e8 - 800029d4: 00006797 auipc a5,0x6 - 800029d8: e0e7b623 sd a4,-500(a5) # 800087e0 - 800029dc: 00006317 auipc t1,0x6 - 800029e0: a1430313 addi t1,t1,-1516 # 800083f0 - 800029e4: 01100793 li a5,17 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00006797 auipc a5,0x6 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800083e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0e99b7b7 lui a5,0xe99b - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 1b978793 addi a5,a5,441 # e99b1b9 <_start-0x71664e47> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 00000093 li ra,0 - 80002acc: 00000113 li sp,0 - 80002ad0: 02208f3b mulw t5,ra,sp - 80002ad4: 00000e93 li t4,0 - 80002ad8: 00200193 li gp,2 - 80002adc: 3ddf1263 bne t5,t4,80002ea0 - -0000000080002ae0 : - 80002ae0: 00100093 li ra,1 - 80002ae4: 00100113 li sp,1 - 80002ae8: 02208f3b mulw t5,ra,sp - 80002aec: 00100e93 li t4,1 - 80002af0: 00300193 li gp,3 - 80002af4: 3bdf1663 bne t5,t4,80002ea0 - -0000000080002af8 : - 80002af8: 00300093 li ra,3 - 80002afc: 00700113 li sp,7 - 80002b00: 02208f3b mulw t5,ra,sp - 80002b04: 01500e93 li t4,21 - 80002b08: 00400193 li gp,4 - 80002b0c: 39df1a63 bne t5,t4,80002ea0 - -0000000080002b10 : - 80002b10: 00000093 li ra,0 - 80002b14: ffff8137 lui sp,0xffff8 - 80002b18: 02208f3b mulw t5,ra,sp - 80002b1c: 00000e93 li t4,0 - 80002b20: 00500193 li gp,5 - 80002b24: 37df1e63 bne t5,t4,80002ea0 - -0000000080002b28 : - 80002b28: 800000b7 lui ra,0x80000 - 80002b2c: 00000113 li sp,0 - 80002b30: 02208f3b mulw t5,ra,sp - 80002b34: 00000e93 li t4,0 - 80002b38: 00600193 li gp,6 - 80002b3c: 37df1263 bne t5,t4,80002ea0 - -0000000080002b40 : - 80002b40: 800000b7 lui ra,0x80000 - 80002b44: ffff8137 lui sp,0xffff8 - 80002b48: 02208f3b mulw t5,ra,sp - 80002b4c: 00000e93 li t4,0 - 80002b50: 00700193 li gp,7 - 80002b54: 35df1663 bne t5,t4,80002ea0 - -0000000080002b58 : - 80002b58: 00d00093 li ra,13 - 80002b5c: 00b00113 li sp,11 - 80002b60: 022080bb mulw ra,ra,sp - 80002b64: 08f00e93 li t4,143 - 80002b68: 00800193 li gp,8 - 80002b6c: 33d09a63 bne ra,t4,80002ea0 - -0000000080002b70 : - 80002b70: 00e00093 li ra,14 - 80002b74: 00b00113 li sp,11 - 80002b78: 0220813b mulw sp,ra,sp - 80002b7c: 09a00e93 li t4,154 - 80002b80: 00900193 li gp,9 - 80002b84: 31d11e63 bne sp,t4,80002ea0 - -0000000080002b88 : - 80002b88: 00d00093 li ra,13 - 80002b8c: 021080bb mulw ra,ra,ra - 80002b90: 0a900e93 li t4,169 - 80002b94: 00a00193 li gp,10 - 80002b98: 31d09463 bne ra,t4,80002ea0 - -0000000080002b9c : - 80002b9c: 00000213 li tp,0 - 80002ba0: 00d00093 li ra,13 - 80002ba4: 00b00113 li sp,11 - 80002ba8: 02208f3b mulw t5,ra,sp - 80002bac: 000f0313 mv t1,t5 - 80002bb0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002bb4: 00200293 li t0,2 - 80002bb8: fe5214e3 bne tp,t0,80002ba0 - 80002bbc: 08f00e93 li t4,143 - 80002bc0: 00b00193 li gp,11 - 80002bc4: 2dd31e63 bne t1,t4,80002ea0 - -0000000080002bc8 : - 80002bc8: 00000213 li tp,0 - 80002bcc: 00e00093 li ra,14 - 80002bd0: 00b00113 li sp,11 - 80002bd4: 02208f3b mulw t5,ra,sp - 80002bd8: 00000013 nop - 80002bdc: 000f0313 mv t1,t5 - 80002be0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002be4: 00200293 li t0,2 - 80002be8: fe5212e3 bne tp,t0,80002bcc - 80002bec: 09a00e93 li t4,154 - 80002bf0: 00c00193 li gp,12 - 80002bf4: 2bd31663 bne t1,t4,80002ea0 - -0000000080002bf8 : - 80002bf8: 00000213 li tp,0 - 80002bfc: 00f00093 li ra,15 - 80002c00: 00b00113 li sp,11 - 80002c04: 02208f3b mulw t5,ra,sp - 80002c08: 00000013 nop - 80002c0c: 00000013 nop - 80002c10: 000f0313 mv t1,t5 - 80002c14: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c18: 00200293 li t0,2 - 80002c1c: fe5210e3 bne tp,t0,80002bfc - 80002c20: 0a500e93 li t4,165 - 80002c24: 00d00193 li gp,13 - 80002c28: 27d31c63 bne t1,t4,80002ea0 - -0000000080002c2c : - 80002c2c: 00000213 li tp,0 - 80002c30: 00d00093 li ra,13 - 80002c34: 00b00113 li sp,11 - 80002c38: 02208f3b mulw t5,ra,sp - 80002c3c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c40: 00200293 li t0,2 - 80002c44: fe5216e3 bne tp,t0,80002c30 - 80002c48: 08f00e93 li t4,143 - 80002c4c: 00e00193 li gp,14 - 80002c50: 25df1863 bne t5,t4,80002ea0 - -0000000080002c54 : - 80002c54: 00000213 li tp,0 - 80002c58: 00e00093 li ra,14 - 80002c5c: 00b00113 li sp,11 - 80002c60: 00000013 nop - 80002c64: 02208f3b mulw t5,ra,sp - 80002c68: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c6c: 00200293 li t0,2 - 80002c70: fe5214e3 bne tp,t0,80002c58 - 80002c74: 09a00e93 li t4,154 - 80002c78: 00f00193 li gp,15 - 80002c7c: 23df1263 bne t5,t4,80002ea0 - -0000000080002c80 : - 80002c80: 00000213 li tp,0 - 80002c84: 00f00093 li ra,15 - 80002c88: 00b00113 li sp,11 - 80002c8c: 00000013 nop - 80002c90: 00000013 nop - 80002c94: 02208f3b mulw t5,ra,sp - 80002c98: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002c9c: 00200293 li t0,2 - 80002ca0: fe5212e3 bne tp,t0,80002c84 - 80002ca4: 0a500e93 li t4,165 - 80002ca8: 01000193 li gp,16 - 80002cac: 1fdf1a63 bne t5,t4,80002ea0 - -0000000080002cb0 : - 80002cb0: 00000213 li tp,0 - 80002cb4: 00d00093 li ra,13 - 80002cb8: 00000013 nop - 80002cbc: 00b00113 li sp,11 - 80002cc0: 02208f3b mulw t5,ra,sp - 80002cc4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cc8: 00200293 li t0,2 - 80002ccc: fe5214e3 bne tp,t0,80002cb4 - 80002cd0: 08f00e93 li t4,143 - 80002cd4: 01100193 li gp,17 - 80002cd8: 1ddf1463 bne t5,t4,80002ea0 - -0000000080002cdc : - 80002cdc: 00000213 li tp,0 - 80002ce0: 00e00093 li ra,14 - 80002ce4: 00000013 nop - 80002ce8: 00b00113 li sp,11 - 80002cec: 00000013 nop - 80002cf0: 02208f3b mulw t5,ra,sp - 80002cf4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002cf8: 00200293 li t0,2 - 80002cfc: fe5212e3 bne tp,t0,80002ce0 - 80002d00: 09a00e93 li t4,154 - 80002d04: 01200193 li gp,18 - 80002d08: 19df1c63 bne t5,t4,80002ea0 - -0000000080002d0c : - 80002d0c: 00000213 li tp,0 - 80002d10: 00f00093 li ra,15 - 80002d14: 00000013 nop - 80002d18: 00000013 nop - 80002d1c: 00b00113 li sp,11 - 80002d20: 02208f3b mulw t5,ra,sp - 80002d24: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d28: 00200293 li t0,2 - 80002d2c: fe5212e3 bne tp,t0,80002d10 - 80002d30: 0a500e93 li t4,165 - 80002d34: 01300193 li gp,19 - 80002d38: 17df1463 bne t5,t4,80002ea0 - -0000000080002d3c : - 80002d3c: 00000213 li tp,0 - 80002d40: 00b00113 li sp,11 - 80002d44: 00d00093 li ra,13 - 80002d48: 02208f3b mulw t5,ra,sp - 80002d4c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d50: 00200293 li t0,2 - 80002d54: fe5216e3 bne tp,t0,80002d40 - 80002d58: 08f00e93 li t4,143 - 80002d5c: 01400193 li gp,20 - 80002d60: 15df1063 bne t5,t4,80002ea0 - -0000000080002d64 : - 80002d64: 00000213 li tp,0 - 80002d68: 00b00113 li sp,11 - 80002d6c: 00e00093 li ra,14 - 80002d70: 00000013 nop - 80002d74: 02208f3b mulw t5,ra,sp - 80002d78: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002d7c: 00200293 li t0,2 - 80002d80: fe5214e3 bne tp,t0,80002d68 - 80002d84: 09a00e93 li t4,154 - 80002d88: 01500193 li gp,21 - 80002d8c: 11df1a63 bne t5,t4,80002ea0 - -0000000080002d90 : - 80002d90: 00000213 li tp,0 - 80002d94: 00b00113 li sp,11 - 80002d98: 00f00093 li ra,15 - 80002d9c: 00000013 nop - 80002da0: 00000013 nop - 80002da4: 02208f3b mulw t5,ra,sp - 80002da8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dac: 00200293 li t0,2 - 80002db0: fe5212e3 bne tp,t0,80002d94 - 80002db4: 0a500e93 li t4,165 - 80002db8: 01600193 li gp,22 - 80002dbc: 0fdf1263 bne t5,t4,80002ea0 - -0000000080002dc0 : - 80002dc0: 00000213 li tp,0 - 80002dc4: 00b00113 li sp,11 - 80002dc8: 00000013 nop - 80002dcc: 00d00093 li ra,13 - 80002dd0: 02208f3b mulw t5,ra,sp - 80002dd4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002dd8: 00200293 li t0,2 - 80002ddc: fe5214e3 bne tp,t0,80002dc4 - 80002de0: 08f00e93 li t4,143 - 80002de4: 01700193 li gp,23 - 80002de8: 0bdf1c63 bne t5,t4,80002ea0 - -0000000080002dec : - 80002dec: 00000213 li tp,0 - 80002df0: 00b00113 li sp,11 - 80002df4: 00000013 nop - 80002df8: 00e00093 li ra,14 - 80002dfc: 00000013 nop - 80002e00: 02208f3b mulw t5,ra,sp - 80002e04: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e08: 00200293 li t0,2 - 80002e0c: fe5212e3 bne tp,t0,80002df0 - 80002e10: 09a00e93 li t4,154 - 80002e14: 01800193 li gp,24 - 80002e18: 09df1463 bne t5,t4,80002ea0 - -0000000080002e1c : - 80002e1c: 00000213 li tp,0 - 80002e20: 00b00113 li sp,11 - 80002e24: 00000013 nop - 80002e28: 00000013 nop - 80002e2c: 00f00093 li ra,15 - 80002e30: 02208f3b mulw t5,ra,sp - 80002e34: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> - 80002e38: 00200293 li t0,2 - 80002e3c: fe5212e3 bne tp,t0,80002e20 - 80002e40: 0a500e93 li t4,165 - 80002e44: 01900193 li gp,25 - 80002e48: 05df1c63 bne t5,t4,80002ea0 - -0000000080002e4c : - 80002e4c: 01f00093 li ra,31 - 80002e50: 0210013b mulw sp,zero,ra - 80002e54: 00000e93 li t4,0 - 80002e58: 01a00193 li gp,26 - 80002e5c: 05d11263 bne sp,t4,80002ea0 - -0000000080002e60 : - 80002e60: 02000093 li ra,32 - 80002e64: 0200813b mulw sp,ra,zero - 80002e68: 00000e93 li t4,0 - 80002e6c: 01b00193 li gp,27 - 80002e70: 03d11863 bne sp,t4,80002ea0 - -0000000080002e74 : - 80002e74: 020000bb mulw ra,zero,zero - 80002e78: 00000e93 li t4,0 - 80002e7c: 01c00193 li gp,28 - 80002e80: 03d09063 bne ra,t4,80002ea0 - -0000000080002e84 : - 80002e84: 02100093 li ra,33 - 80002e88: 02200113 li sp,34 - 80002e8c: 0220803b mulw zero,ra,sp - 80002e90: 00000e93 li t4,0 - 80002e94: 01d00193 li gp,29 - 80002e98: 01d01463 bne zero,t4,80002ea0 - 80002e9c: 00301a63 bne zero,gp,80002eb0 - -0000000080002ea0 : - 80002ea0: 00119513 slli a0,gp,0x1 - 80002ea4: 00050063 beqz a0,80002ea4 - 80002ea8: 00156513 ori a0,a0,1 - 80002eac: 00000073 ecall - -0000000080002eb0 : - 80002eb0: 00100513 li a0,1 - 80002eb4: 00000073 ecall - 80002eb8: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-mulw.elf b/test/riscv/tests/rv64um-v-mulw.elf deleted file mode 100644 index bfc28b25..00000000 Binary files a/test/riscv/tests/rv64um-v-mulw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-v-rem.dump b/test/riscv/tests/rv64um-v-rem.dump deleted file mode 100644 index 8c29a0c4..00000000 --- a/test/riscv/tests/rv64um-v-rem.dump +++ /dev/null @@ -1,915 +0,0 @@ - -rv64um-v-rem: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 77868693 addi a3,a3,1912 # 80002bd0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 7ac60613 addi a2,a2,1964 # 80002c60 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 77460613 addi a2,a2,1908 # 80002c78 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 6c468693 addi a3,a3,1732 # 80002c18 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 6e068693 addi a3,a3,1760 # 80002d50 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 66060613 addi a2,a2,1632 # 80002d28 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 59468693 addi a3,a3,1428 # 80002d80 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 4b468693 addi a3,a3,1204 # 80002cf0 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 44468693 addi a3,a3,1092 # 80002cb8 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 03100793 li a5,49 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 03a277b7 lui a5,0x3a27 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: ea378793 addi a5,a5,-349 # 3a26ea3 <_start-0x7c5d915d> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 01400093 li ra,20 - 80002acc: 00600113 li sp,6 - 80002ad0: 0220ef33 rem t5,ra,sp - 80002ad4: 00200e93 li t4,2 - 80002ad8: 00200193 li gp,2 - 80002adc: 0ddf1c63 bne t5,t4,80002bb4 - -0000000080002ae0 : - 80002ae0: fec00093 li ra,-20 - 80002ae4: 00600113 li sp,6 - 80002ae8: 0220ef33 rem t5,ra,sp - 80002aec: ffe00e93 li t4,-2 - 80002af0: 00300193 li gp,3 - 80002af4: 0ddf1063 bne t5,t4,80002bb4 - -0000000080002af8 : - 80002af8: 01400093 li ra,20 - 80002afc: ffa00113 li sp,-6 - 80002b00: 0220ef33 rem t5,ra,sp - 80002b04: 00200e93 li t4,2 - 80002b08: 00400193 li gp,4 - 80002b0c: 0bdf1463 bne t5,t4,80002bb4 - -0000000080002b10 : - 80002b10: fec00093 li ra,-20 - 80002b14: ffa00113 li sp,-6 - 80002b18: 0220ef33 rem t5,ra,sp - 80002b1c: ffe00e93 li t4,-2 - 80002b20: 00500193 li gp,5 - 80002b24: 09df1863 bne t5,t4,80002bb4 - -0000000080002b28 : - 80002b28: fff0009b addiw ra,zero,-1 - 80002b2c: 03f09093 slli ra,ra,0x3f - 80002b30: 00100113 li sp,1 - 80002b34: 0220ef33 rem t5,ra,sp - 80002b38: 00000e93 li t4,0 - 80002b3c: 00600193 li gp,6 - 80002b40: 07df1a63 bne t5,t4,80002bb4 - -0000000080002b44 : - 80002b44: fff0009b addiw ra,zero,-1 - 80002b48: 03f09093 slli ra,ra,0x3f - 80002b4c: fff00113 li sp,-1 - 80002b50: 0220ef33 rem t5,ra,sp - 80002b54: 00000e93 li t4,0 - 80002b58: 00700193 li gp,7 - 80002b5c: 05df1c63 bne t5,t4,80002bb4 - -0000000080002b60 : - 80002b60: fff0009b addiw ra,zero,-1 - 80002b64: 03f09093 slli ra,ra,0x3f - 80002b68: 00000113 li sp,0 - 80002b6c: 0220ef33 rem t5,ra,sp - 80002b70: fff00e9b addiw t4,zero,-1 - 80002b74: 03fe9e93 slli t4,t4,0x3f - 80002b78: 00800193 li gp,8 - 80002b7c: 03df1c63 bne t5,t4,80002bb4 - -0000000080002b80 : - 80002b80: 00100093 li ra,1 - 80002b84: 00000113 li sp,0 - 80002b88: 0220ef33 rem t5,ra,sp - 80002b8c: 00100e93 li t4,1 - 80002b90: 00900193 li gp,9 - 80002b94: 03df1063 bne t5,t4,80002bb4 - -0000000080002b98 : - 80002b98: 00000093 li ra,0 - 80002b9c: 00000113 li sp,0 - 80002ba0: 0220ef33 rem t5,ra,sp - 80002ba4: 00000e93 li t4,0 - 80002ba8: 00a00193 li gp,10 - 80002bac: 01df1463 bne t5,t4,80002bb4 - 80002bb0: 00301a63 bne zero,gp,80002bc4 - -0000000080002bb4 : - 80002bb4: 00119513 slli a0,gp,0x1 - 80002bb8: 00050063 beqz a0,80002bb8 - 80002bbc: 00156513 ori a0,a0,1 - 80002bc0: 00000073 ecall - -0000000080002bc4 : - 80002bc4: 00100513 li a0,1 - 80002bc8: 00000073 ecall - 80002bcc: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-rem.elf b/test/riscv/tests/rv64um-v-rem.elf deleted file mode 100644 index 9caa3b3b..00000000 Binary files a/test/riscv/tests/rv64um-v-rem.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-v-remu.dump b/test/riscv/tests/rv64um-v-remu.dump deleted file mode 100644 index 01d50acb..00000000 --- a/test/riscv/tests/rv64um-v-remu.dump +++ /dev/null @@ -1,916 +0,0 @@ - -rv64um-v-remu: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 78068693 addi a3,a3,1920 # 80002bd8 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 7b460613 addi a2,a2,1972 # 80002c68 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 77c60613 addi a2,a2,1916 # 80002c80 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 6cc68693 addi a3,a3,1740 # 80002c20 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 6e868693 addi a3,a3,1768 # 80002d58 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 66860613 addi a2,a2,1640 # 80002d30 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 59c68693 addi a3,a3,1436 # 80002d88 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 4bc68693 addi a3,a3,1212 # 80002cf8 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 44c68693 addi a3,a3,1100 # 80002cc0 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 03e00793 li a5,62 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 05d337b7 lui a5,0x5d33 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 2c578793 addi a5,a5,709 # 5d332c5 <_start-0x7a2ccd3b> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 01400093 li ra,20 - 80002acc: 00600113 li sp,6 - 80002ad0: 0220ff33 remu t5,ra,sp - 80002ad4: 00200e93 li t4,2 - 80002ad8: 00200193 li gp,2 - 80002adc: 0ddf1e63 bne t5,t4,80002bb8 - -0000000080002ae0 : - 80002ae0: fec00093 li ra,-20 - 80002ae4: 00600113 li sp,6 - 80002ae8: 0220ff33 remu t5,ra,sp - 80002aec: 00200e93 li t4,2 - 80002af0: 00300193 li gp,3 - 80002af4: 0ddf1263 bne t5,t4,80002bb8 - -0000000080002af8 : - 80002af8: 01400093 li ra,20 - 80002afc: ffa00113 li sp,-6 - 80002b00: 0220ff33 remu t5,ra,sp - 80002b04: 01400e93 li t4,20 - 80002b08: 00400193 li gp,4 - 80002b0c: 0bdf1663 bne t5,t4,80002bb8 - -0000000080002b10 : - 80002b10: fec00093 li ra,-20 - 80002b14: ffa00113 li sp,-6 - 80002b18: 0220ff33 remu t5,ra,sp - 80002b1c: fec00e93 li t4,-20 - 80002b20: 00500193 li gp,5 - 80002b24: 09df1a63 bne t5,t4,80002bb8 - -0000000080002b28 : - 80002b28: fff0009b addiw ra,zero,-1 - 80002b2c: 03f09093 slli ra,ra,0x3f - 80002b30: 00100113 li sp,1 - 80002b34: 0220ff33 remu t5,ra,sp - 80002b38: 00000e93 li t4,0 - 80002b3c: 00600193 li gp,6 - 80002b40: 07df1c63 bne t5,t4,80002bb8 - -0000000080002b44 : - 80002b44: fff0009b addiw ra,zero,-1 - 80002b48: 03f09093 slli ra,ra,0x3f - 80002b4c: fff00113 li sp,-1 - 80002b50: 0220ff33 remu t5,ra,sp - 80002b54: fff00e9b addiw t4,zero,-1 - 80002b58: 03fe9e93 slli t4,t4,0x3f - 80002b5c: 00700193 li gp,7 - 80002b60: 05df1c63 bne t5,t4,80002bb8 - -0000000080002b64 : - 80002b64: fff0009b addiw ra,zero,-1 - 80002b68: 03f09093 slli ra,ra,0x3f - 80002b6c: 00000113 li sp,0 - 80002b70: 0220ff33 remu t5,ra,sp - 80002b74: fff00e9b addiw t4,zero,-1 - 80002b78: 03fe9e93 slli t4,t4,0x3f - 80002b7c: 00800193 li gp,8 - 80002b80: 03df1c63 bne t5,t4,80002bb8 - -0000000080002b84 : - 80002b84: 00100093 li ra,1 - 80002b88: 00000113 li sp,0 - 80002b8c: 0220ff33 remu t5,ra,sp - 80002b90: 00100e93 li t4,1 - 80002b94: 00900193 li gp,9 - 80002b98: 03df1063 bne t5,t4,80002bb8 - -0000000080002b9c : - 80002b9c: 00000093 li ra,0 - 80002ba0: 00000113 li sp,0 - 80002ba4: 0220ff33 remu t5,ra,sp - 80002ba8: 00000e93 li t4,0 - 80002bac: 00a00193 li gp,10 - 80002bb0: 01df1463 bne t5,t4,80002bb8 - 80002bb4: 00301a63 bne zero,gp,80002bc8 - -0000000080002bb8 : - 80002bb8: 00119513 slli a0,gp,0x1 - 80002bbc: 00050063 beqz a0,80002bbc - 80002bc0: 00156513 ori a0,a0,1 - 80002bc4: 00000073 ecall - -0000000080002bc8 : - 80002bc8: 00100513 li a0,1 - 80002bcc: 00000073 ecall - 80002bd0: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-remu.elf b/test/riscv/tests/rv64um-v-remu.elf deleted file mode 100644 index 26ead9d0..00000000 Binary files a/test/riscv/tests/rv64um-v-remu.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-v-remuw.dump b/test/riscv/tests/rv64um-v-remuw.dump deleted file mode 100644 index f0688a43..00000000 --- a/test/riscv/tests/rv64um-v-remuw.dump +++ /dev/null @@ -1,911 +0,0 @@ - -rv64um-v-remuw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 76868693 addi a3,a3,1896 # 80002bc0 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 79c60613 addi a2,a2,1948 # 80002c50 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 76460613 addi a2,a2,1892 # 80002c68 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 6b468693 addi a3,a3,1716 # 80002c08 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 6d068693 addi a3,a3,1744 # 80002d40 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 65060613 addi a2,a2,1616 # 80002d18 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 58468693 addi a3,a3,1412 # 80002d70 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 4a468693 addi a3,a3,1188 # 80002ce0 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 43468693 addi a3,a3,1076 # 80002ca8 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 01700793 li a5,23 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 01bd87b7 lui a5,0x1bd8 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 7ed78793 addi a5,a5,2029 # 1bd87ed <_start-0x7e427813> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 01400093 li ra,20 - 80002acc: 00600113 li sp,6 - 80002ad0: 0220ff3b remuw t5,ra,sp - 80002ad4: 00200e93 li t4,2 - 80002ad8: 00200193 li gp,2 - 80002adc: 0ddf1463 bne t5,t4,80002ba4 - -0000000080002ae0 : - 80002ae0: fec00093 li ra,-20 - 80002ae4: 00600113 li sp,6 - 80002ae8: 0220ff3b remuw t5,ra,sp - 80002aec: 00200e93 li t4,2 - 80002af0: 00300193 li gp,3 - 80002af4: 0bdf1863 bne t5,t4,80002ba4 - -0000000080002af8 : - 80002af8: 01400093 li ra,20 - 80002afc: ffa00113 li sp,-6 - 80002b00: 0220ff3b remuw t5,ra,sp - 80002b04: 01400e93 li t4,20 - 80002b08: 00400193 li gp,4 - 80002b0c: 09df1c63 bne t5,t4,80002ba4 - -0000000080002b10 : - 80002b10: fec00093 li ra,-20 - 80002b14: ffa00113 li sp,-6 - 80002b18: 0220ff3b remuw t5,ra,sp - 80002b1c: fec00e93 li t4,-20 - 80002b20: 00500193 li gp,5 - 80002b24: 09df1063 bne t5,t4,80002ba4 - -0000000080002b28 : - 80002b28: 800000b7 lui ra,0x80000 - 80002b2c: 00100113 li sp,1 - 80002b30: 0220ff3b remuw t5,ra,sp - 80002b34: 00000e93 li t4,0 - 80002b38: 00600193 li gp,6 - 80002b3c: 07df1463 bne t5,t4,80002ba4 - -0000000080002b40 : - 80002b40: 800000b7 lui ra,0x80000 - 80002b44: fff00113 li sp,-1 - 80002b48: 0220ff3b remuw t5,ra,sp - 80002b4c: 80000eb7 lui t4,0x80000 - 80002b50: 00700193 li gp,7 - 80002b54: 05df1863 bne t5,t4,80002ba4 - -0000000080002b58 : - 80002b58: 800000b7 lui ra,0x80000 - 80002b5c: 00000113 li sp,0 - 80002b60: 0220ff3b remuw t5,ra,sp - 80002b64: 80000eb7 lui t4,0x80000 - 80002b68: 00800193 li gp,8 - 80002b6c: 03df1c63 bne t5,t4,80002ba4 - -0000000080002b70 : - 80002b70: 00100093 li ra,1 - 80002b74: 00000113 li sp,0 - 80002b78: 0220ff3b remuw t5,ra,sp - 80002b7c: 00100e93 li t4,1 - 80002b80: 00900193 li gp,9 - 80002b84: 03df1063 bne t5,t4,80002ba4 - -0000000080002b88 : - 80002b88: 00000093 li ra,0 - 80002b8c: 00000113 li sp,0 - 80002b90: 0220ff3b remuw t5,ra,sp - 80002b94: 00000e93 li t4,0 - 80002b98: 00a00193 li gp,10 - 80002b9c: 01df1463 bne t5,t4,80002ba4 - 80002ba0: 00301a63 bne zero,gp,80002bb4 - -0000000080002ba4 : - 80002ba4: 00119513 slli a0,gp,0x1 - 80002ba8: 00050063 beqz a0,80002ba8 - 80002bac: 00156513 ori a0,a0,1 - 80002bb0: 00000073 ecall - -0000000080002bb4 : - 80002bb4: 00100513 li a0,1 - 80002bb8: 00000073 ecall - 80002bbc: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-remuw.elf b/test/riscv/tests/rv64um-v-remuw.elf deleted file mode 100644 index 795ae59c..00000000 Binary files a/test/riscv/tests/rv64um-v-remuw.elf and /dev/null differ diff --git a/test/riscv/tests/rv64um-v-remw.dump b/test/riscv/tests/rv64um-v-remw.dump deleted file mode 100644 index 659d882e..00000000 --- a/test/riscv/tests/rv64um-v-remw.dump +++ /dev/null @@ -1,919 +0,0 @@ - -rv64um-v-remw: file format elf64-littleriscv - - -Disassembly of section .text.init: - -0000000080000000 <_start>: - 80000000: 00c0006f j 8000000c - -0000000080000004 : - 80000004: 2580206f j 8000225c - -0000000080000008 : - 80000008: 2540206f j 8000225c - -000000008000000c : - 8000000c: 00000297 auipc t0,0x0 - 80000010: ffc28293 addi t0,t0,-4 # 80000008 - 80000014: 30529073 csrw mtvec,t0 - 80000018: 00008117 auipc sp,0x8 - 8000001c: 6b810113 addi sp,sp,1720 # 800086d0 <_end+0xee0> - 80000020: f14022f3 csrr t0,mhartid - 80000024: 00c29293 slli t0,t0,0xc - 80000028: 00510133 add sp,sp,t0 - 8000002c: 34011073 csrw mscratch,sp - 80000030: 00003517 auipc a0,0x3 - 80000034: a9850513 addi a0,a0,-1384 # 80002ac8 - 80000038: 09d0206f j 800028d4 - -000000008000003c : - 8000003c: 10853283 ld t0,264(a0) - 80000040: 14129073 csrw sepc,t0 - 80000044: 00853083 ld ra,8(a0) - 80000048: 01053103 ld sp,16(a0) - 8000004c: 01853183 ld gp,24(a0) - 80000050: 02053203 ld tp,32(a0) - 80000054: 02853283 ld t0,40(a0) - 80000058: 03053303 ld t1,48(a0) - 8000005c: 03853383 ld t2,56(a0) - 80000060: 04053403 ld s0,64(a0) - 80000064: 04853483 ld s1,72(a0) - 80000068: 05853583 ld a1,88(a0) - 8000006c: 06053603 ld a2,96(a0) - 80000070: 06853683 ld a3,104(a0) - 80000074: 07053703 ld a4,112(a0) - 80000078: 07853783 ld a5,120(a0) - 8000007c: 08053803 ld a6,128(a0) - 80000080: 08853883 ld a7,136(a0) - 80000084: 09053903 ld s2,144(a0) - 80000088: 09853983 ld s3,152(a0) - 8000008c: 0a053a03 ld s4,160(a0) - 80000090: 0a853a83 ld s5,168(a0) - 80000094: 0b053b03 ld s6,176(a0) - 80000098: 0b853b83 ld s7,184(a0) - 8000009c: 0c053c03 ld s8,192(a0) - 800000a0: 0c853c83 ld s9,200(a0) - 800000a4: 0d053d03 ld s10,208(a0) - 800000a8: 0d853d83 ld s11,216(a0) - 800000ac: 0e053e03 ld t3,224(a0) - 800000b0: 0e853e83 ld t4,232(a0) - 800000b4: 0f053f03 ld t5,240(a0) - 800000b8: 0f853f83 ld t6,248(a0) - 800000bc: 05053503 ld a0,80(a0) - 800000c0: 10200073 sret - -00000000800000c4 : - 800000c4: 14011173 csrrw sp,sscratch,sp - 800000c8: 00113423 sd ra,8(sp) - 800000cc: 00313c23 sd gp,24(sp) - 800000d0: 02413023 sd tp,32(sp) - 800000d4: 02513423 sd t0,40(sp) - 800000d8: 02613823 sd t1,48(sp) - 800000dc: 02713c23 sd t2,56(sp) - 800000e0: 04813023 sd s0,64(sp) - 800000e4: 04913423 sd s1,72(sp) - 800000e8: 04a13823 sd a0,80(sp) - 800000ec: 04b13c23 sd a1,88(sp) - 800000f0: 06c13023 sd a2,96(sp) - 800000f4: 06d13423 sd a3,104(sp) - 800000f8: 06e13823 sd a4,112(sp) - 800000fc: 06f13c23 sd a5,120(sp) - 80000100: 09013023 sd a6,128(sp) - 80000104: 09113423 sd a7,136(sp) - 80000108: 09213823 sd s2,144(sp) - 8000010c: 09313c23 sd s3,152(sp) - 80000110: 0b413023 sd s4,160(sp) - 80000114: 0b513423 sd s5,168(sp) - 80000118: 0b613823 sd s6,176(sp) - 8000011c: 0b713c23 sd s7,184(sp) - 80000120: 0d813023 sd s8,192(sp) - 80000124: 0d913423 sd s9,200(sp) - 80000128: 0da13823 sd s10,208(sp) - 8000012c: 0db13c23 sd s11,216(sp) - 80000130: 0fc13023 sd t3,224(sp) - 80000134: 0fd13423 sd t4,232(sp) - 80000138: 0fe13823 sd t5,240(sp) - 8000013c: 0ff13c23 sd t6,248(sp) - 80000140: 140112f3 csrrw t0,sscratch,sp - 80000144: 00513823 sd t0,16(sp) - 80000148: 100022f3 csrr t0,sstatus - 8000014c: 10513023 sd t0,256(sp) - 80000150: 141022f3 csrr t0,sepc - 80000154: 10513423 sd t0,264(sp) - 80000158: 143022f3 csrr t0,sbadaddr - 8000015c: 10513823 sd t0,272(sp) - 80000160: 142022f3 csrr t0,scause - 80000164: 10513c23 sd t0,280(sp) - 80000168: 00010513 mv a0,sp - 8000016c: 4300206f j 8000259c - -Disassembly of section .text: - -0000000080002000 : - 80002000: 00c5e7b3 or a5,a1,a2 - 80002004: 00f567b3 or a5,a0,a5 - 80002008: 0077f793 andi a5,a5,7 - 8000200c: 00c506b3 add a3,a0,a2 - 80002010: 02078463 beqz a5,80002038 - 80002014: 00c58633 add a2,a1,a2 - 80002018: 00050793 mv a5,a0 - 8000201c: 02d57e63 bleu a3,a0,80002058 - 80002020: 00158593 addi a1,a1,1 - 80002024: fff5c703 lbu a4,-1(a1) - 80002028: 00178793 addi a5,a5,1 - 8000202c: fee78fa3 sb a4,-1(a5) - 80002030: feb618e3 bne a2,a1,80002020 - 80002034: 00008067 ret - 80002038: fed57ee3 bleu a3,a0,80002034 - 8000203c: 00050793 mv a5,a0 - 80002040: 00858593 addi a1,a1,8 - 80002044: ff85b703 ld a4,-8(a1) - 80002048: 00878793 addi a5,a5,8 - 8000204c: fee7bc23 sd a4,-8(a5) - 80002050: fed7e8e3 bltu a5,a3,80002040 - 80002054: 00008067 ret - 80002058: 00008067 ret - -000000008000205c : - 8000205c: 00c567b3 or a5,a0,a2 - 80002060: 0077f793 andi a5,a5,7 - 80002064: 00c50633 add a2,a0,a2 - 80002068: 0ff5f593 andi a1,a1,255 - 8000206c: 00078e63 beqz a5,80002088 - 80002070: 00050793 mv a5,a0 - 80002074: 04c57263 bleu a2,a0,800020b8 - 80002078: 00178793 addi a5,a5,1 - 8000207c: feb78fa3 sb a1,-1(a5) - 80002080: fef61ce3 bne a2,a5,80002078 - 80002084: 00008067 ret - 80002088: 00859793 slli a5,a1,0x8 - 8000208c: 00b7e5b3 or a1,a5,a1 - 80002090: 01059793 slli a5,a1,0x10 - 80002094: 00b7e7b3 or a5,a5,a1 - 80002098: 02079593 slli a1,a5,0x20 - 8000209c: 00f5e5b3 or a1,a1,a5 - 800020a0: fec572e3 bleu a2,a0,80002084 - 800020a4: 00050793 mv a5,a0 - 800020a8: 00878793 addi a5,a5,8 - 800020ac: feb7bc23 sd a1,-8(a5) - 800020b0: fec7ece3 bltu a5,a2,800020a8 - 800020b4: 00008067 ret - 800020b8: 00008067 ret - -00000000800020bc : - 800020bc: 00054783 lbu a5,0(a0) - 800020c0: 00050713 mv a4,a0 - 800020c4: 00078c63 beqz a5,800020dc - 800020c8: 00150513 addi a0,a0,1 - 800020cc: 00054783 lbu a5,0(a0) - 800020d0: fe079ce3 bnez a5,800020c8 - 800020d4: 40e50533 sub a0,a0,a4 - 800020d8: 00008067 ret - 800020dc: 00000513 li a0,0 - 800020e0: 00008067 ret - -00000000800020e4 : - 800020e4: 00150513 addi a0,a0,1 - 800020e8: fff54783 lbu a5,-1(a0) - 800020ec: 00158593 addi a1,a1,1 - 800020f0: fff5c703 lbu a4,-1(a1) - 800020f4: 00078a63 beqz a5,80002108 - 800020f8: fee786e3 beq a5,a4,800020e4 - 800020fc: 0007851b sext.w a0,a5 - 80002100: 40e5053b subw a0,a0,a4 - 80002104: 00008067 ret - 80002108: 00000513 li a0,0 - 8000210c: ff5ff06f j 80002100 - -0000000080002110 : - 80002110: 00b567b3 or a5,a0,a1 - 80002114: 0077f793 andi a5,a5,7 - 80002118: 04079263 bnez a5,8000215c - 8000211c: ff867693 andi a3,a2,-8 - 80002120: 00d506b3 add a3,a0,a3 - 80002124: 00050813 mv a6,a0 - 80002128: 02d57a63 bleu a3,a0,8000215c - 8000212c: 00053703 ld a4,0(a0) - 80002130: 0005b783 ld a5,0(a1) - 80002134: 00f70a63 beq a4,a5,80002148 - 80002138: 0240006f j 8000215c - 8000213c: 00053703 ld a4,0(a0) - 80002140: 0005b783 ld a5,0(a1) - 80002144: 00f71863 bne a4,a5,80002154 - 80002148: 00850513 addi a0,a0,8 - 8000214c: 00858593 addi a1,a1,8 - 80002150: fed566e3 bltu a0,a3,8000213c - 80002154: 41050833 sub a6,a0,a6 - 80002158: 41060633 sub a2,a2,a6 - 8000215c: 00c58633 add a2,a1,a2 - 80002160: 0140006f j 80002174 - 80002164: 00158593 addi a1,a1,1 - 80002168: fff54783 lbu a5,-1(a0) - 8000216c: fff5c703 lbu a4,-1(a1) - 80002170: 00e79a63 bne a5,a4,80002184 - 80002174: 00150513 addi a0,a0,1 - 80002178: fec596e3 bne a1,a2,80002164 - 8000217c: 00000513 li a0,0 - 80002180: 00008067 ret - 80002184: 40e7853b subw a0,a5,a4 - 80002188: 00008067 ret - -000000008000218c : - 8000218c: 00050793 mv a5,a0 - 80002190: 00158593 addi a1,a1,1 - 80002194: fff5c703 lbu a4,-1(a1) - 80002198: 00178793 addi a5,a5,1 - 8000219c: fee78fa3 sb a4,-1(a5) - 800021a0: fe0718e3 bnez a4,80002190 - 800021a4: 00008067 ret - -00000000800021a8 : - 800021a8: 00054783 lbu a5,0(a0) - 800021ac: 02000713 li a4,32 - 800021b0: 00e79863 bne a5,a4,800021c0 - 800021b4: 00150513 addi a0,a0,1 - 800021b8: 00054783 lbu a5,0(a0) - 800021bc: fee78ce3 beq a5,a4,800021b4 - 800021c0: fd57871b addiw a4,a5,-43 - 800021c4: 0fd77713 andi a4,a4,253 - 800021c8: 04070263 beqz a4,8000220c - 800021cc: 00054683 lbu a3,0(a0) - 800021d0: 00050793 mv a5,a0 - 800021d4: 00000613 li a2,0 - 800021d8: 04068863 beqz a3,80002228 - 800021dc: 00000513 li a0,0 - 800021e0: 00178793 addi a5,a5,1 - 800021e4: fd06859b addiw a1,a3,-48 - 800021e8: 00251713 slli a4,a0,0x2 - 800021ec: 0007c683 lbu a3,0(a5) - 800021f0: 00a70533 add a0,a4,a0 - 800021f4: 00151513 slli a0,a0,0x1 - 800021f8: 00a58533 add a0,a1,a0 - 800021fc: fe0692e3 bnez a3,800021e0 - 80002200: 00060463 beqz a2,80002208 - 80002204: 40a00533 neg a0,a0 - 80002208: 00008067 ret - 8000220c: 00154683 lbu a3,1(a0) - 80002210: fd378793 addi a5,a5,-45 - 80002214: 0017b613 seqz a2,a5 - 80002218: 00150793 addi a5,a0,1 - 8000221c: fc0690e3 bnez a3,800021dc - 80002220: 00000513 li a0,0 - 80002224: fddff06f j 80002200 - 80002228: 00000513 li a0,0 - 8000222c: 00008067 ret - -0000000080002230 : - 80002230: fffff797 auipc a5,0xfffff - 80002234: dd078793 addi a5,a5,-560 # 80001000 - 80002238: 0007b703 ld a4,0(a5) - 8000223c: 00070a63 beqz a4,80002250 - 80002240: fffff717 auipc a4,0xfffff - 80002244: e0073023 sd zero,-512(a4) # 80001040 - 80002248: 0007b703 ld a4,0(a5) - 8000224c: fe071ae3 bnez a4,80002240 - 80002250: fffff797 auipc a5,0xfffff - 80002254: daa7b823 sd a0,-592(a5) # 80001000 - 80002258: 0000006f j 80002258 - -000000008000225c : - 8000225c: ff010113 addi sp,sp,-16 - 80002260: 34900513 li a0,841 - 80002264: 00113423 sd ra,8(sp) - 80002268: fc9ff0ef jal ra,80002230 - -000000008000226c : - 8000226c: fe010113 addi sp,sp,-32 - 80002270: 01710713 addi a4,sp,23 - 80002274: 00710813 addi a6,sp,7 - 80002278: 00900593 li a1,9 - 8000227c: 00f57793 andi a5,a0,15 - 80002280: 03000613 li a2,48 - 80002284: 0ff7f693 andi a3,a5,255 - 80002288: 00f5f463 bleu a5,a1,80002290 - 8000228c: 05700613 li a2,87 - 80002290: 00c687bb addw a5,a3,a2 - 80002294: 00f70023 sb a5,0(a4) - 80002298: fff70713 addi a4,a4,-1 - 8000229c: 00455513 srli a0,a0,0x4 - 800022a0: fd071ee3 bne a4,a6,8000227c - 800022a4: 00814783 lbu a5,8(sp) - 800022a8: 00010c23 sb zero,24(sp) - 800022ac: 04078463 beqz a5,800022f4 - 800022b0: 10100513 li a0,257 - 800022b4: 00810693 addi a3,sp,8 - 800022b8: fffff717 auipc a4,0xfffff - 800022bc: d4870713 addi a4,a4,-696 # 80001000 - 800022c0: 03051513 slli a0,a0,0x30 - 800022c4: 00073583 ld a1,0(a4) - 800022c8: 00168693 addi a3,a3,1 - 800022cc: 00a7e633 or a2,a5,a0 - 800022d0: 00058a63 beqz a1,800022e4 - 800022d4: fffff797 auipc a5,0xfffff - 800022d8: d607b623 sd zero,-660(a5) # 80001040 - 800022dc: 00073783 ld a5,0(a4) - 800022e0: fe079ae3 bnez a5,800022d4 - 800022e4: 0006c783 lbu a5,0(a3) - 800022e8: fffff597 auipc a1,0xfffff - 800022ec: d0c5bc23 sd a2,-744(a1) # 80001000 - 800022f0: fc079ae3 bnez a5,800022c4 - 800022f4: 02010113 addi sp,sp,32 - 800022f8: 00008067 ret - -00000000800022fc : - 800022fc: fffff8b7 lui a7,0xfffff - 80002300: 01150733 add a4,a0,a7 - 80002304: 0003e7b7 lui a5,0x3e - 80002308: 14f77463 bleu a5,a4,80002450 - 8000230c: 00c55693 srli a3,a0,0xc - 80002310: 60068813 addi a6,a3,1536 - 80002314: 00001617 auipc a2,0x1 - 80002318: cec60613 addi a2,a2,-788 # 80003000 - 8000231c: 00381793 slli a5,a6,0x3 - 80002320: 00f607b3 add a5,a2,a5 - 80002324: 0007b703 ld a4,0(a5) # 3e000 <_start-0x7ffc2000> - 80002328: 01157533 and a0,a0,a7 - 8000232c: 0e071063 bnez a4,8000240c - 80002330: 00005797 auipc a5,0x5 - 80002334: 4b878793 addi a5,a5,1208 # 800077e8 - 80002338: 0007b583 ld a1,0(a5) - 8000233c: 16058863 beqz a1,800024ac - 80002340: 0085b783 ld a5,8(a1) - 80002344: 00005717 auipc a4,0x5 - 80002348: 49c70713 addi a4,a4,1180 # 800077e0 - 8000234c: 00073703 ld a4,0(a4) - 80002350: 00005897 auipc a7,0x5 - 80002354: 48f8bc23 sd a5,1176(a7) # 800077e8 - 80002358: 0ee78663 beq a5,a4,80002444 - 8000235c: 0005b783 ld a5,0(a1) - 80002360: 00381893 slli a7,a6,0x3 - 80002364: 011608b3 add a7,a2,a7 - 80002368: 00c7d793 srli a5,a5,0xc - 8000236c: 00a79793 slli a5,a5,0xa - 80002370: 0df7e313 ori t1,a5,223 - 80002374: 01f7e713 ori a4,a5,31 - 80002378: 0068b023 sd t1,0(a7) - 8000237c: 12050073 sfence.vma a0 - 80002380: 00005797 auipc a5,0x5 - 80002384: 07078793 addi a5,a5,112 # 800073f0 - 80002388: 00469693 slli a3,a3,0x4 - 8000238c: 00d786b3 add a3,a5,a3 - 80002390: 0006b783 ld a5,0(a3) - 80002394: 16079463 bnez a5,800024fc - 80002398: 0005b783 ld a5,0(a1) - 8000239c: 00f6b023 sd a5,0(a3) - 800023a0: 0085b783 ld a5,8(a1) - 800023a4: 00f6b423 sd a5,8(a3) - 800023a8: 000407b7 lui a5,0x40 - 800023ac: 1007a8f3 csrrs a7,sstatus,a5 - 800023b0: ffe007b7 lui a5,0xffe00 - 800023b4: 00f507b3 add a5,a0,a5 - 800023b8: 000015b7 lui a1,0x1 - 800023bc: 00050693 mv a3,a0 - 800023c0: 00b785b3 add a1,a5,a1 - 800023c4: 0007bf03 ld t5,0(a5) # ffffffffffe00000 <_end+0xffffffff7fdf8810> - 800023c8: 0087be83 ld t4,8(a5) - 800023cc: 0107be03 ld t3,16(a5) - 800023d0: 0187b303 ld t1,24(a5) - 800023d4: 01e6b023 sd t5,0(a3) - 800023d8: 01d6b423 sd t4,8(a3) - 800023dc: 01c6b823 sd t3,16(a3) - 800023e0: 0066bc23 sd t1,24(a3) - 800023e4: 02078793 addi a5,a5,32 - 800023e8: 02068693 addi a3,a3,32 - 800023ec: fcb79ce3 bne a5,a1,800023c4 - 800023f0: 10089073 csrw sstatus,a7 - 800023f4: 00381813 slli a6,a6,0x3 - 800023f8: 01060633 add a2,a2,a6 - 800023fc: 00e63023 sd a4,0(a2) - 80002400: 12050073 sfence.vma a0 - 80002404: 0000100f fence.i - 80002408: 00008067 ret - 8000240c: 04077693 andi a3,a4,64 - 80002410: 00069a63 bnez a3,80002424 - 80002414: 04076713 ori a4,a4,64 - 80002418: 00e7b023 sd a4,0(a5) - 8000241c: 12050073 sfence.vma a0 - 80002420: 00008067 ret - 80002424: 08077693 andi a3,a4,128 - 80002428: 12069263 bnez a3,8000254c - 8000242c: 00f00693 li a3,15 - 80002430: 10d59e63 bne a1,a3,8000254c - 80002434: 08076713 ori a4,a4,128 - 80002438: 00e7b023 sd a4,0(a5) - 8000243c: 12050073 sfence.vma a0 - 80002440: 00008067 ret - 80002444: 00005797 auipc a5,0x5 - 80002448: 3807be23 sd zero,924(a5) # 800077e0 - 8000244c: f11ff06f j 8000235c - 80002450: 10100613 li a2,257 - 80002454: 04100713 li a4,65 - 80002458: 00000697 auipc a3,0x0 - 8000245c: 78068693 addi a3,a3,1920 # 80002bd8 - 80002460: fffff797 auipc a5,0xfffff - 80002464: ba078793 addi a5,a5,-1120 # 80001000 - 80002468: 03061613 slli a2,a2,0x30 - 8000246c: 0007b503 ld a0,0(a5) - 80002470: 00168693 addi a3,a3,1 - 80002474: 00c765b3 or a1,a4,a2 - 80002478: 00050a63 beqz a0,8000248c - 8000247c: fffff717 auipc a4,0xfffff - 80002480: bc073223 sd zero,-1084(a4) # 80001040 - 80002484: 0007b703 ld a4,0(a5) - 80002488: fe071ae3 bnez a4,8000247c - 8000248c: 0006c703 lbu a4,0(a3) - 80002490: fffff517 auipc a0,0xfffff - 80002494: b6b53823 sd a1,-1168(a0) # 80001000 - 80002498: fc071ae3 bnez a4,8000246c - 8000249c: ff010113 addi sp,sp,-16 - 800024a0: 00300513 li a0,3 - 800024a4: 00113423 sd ra,8(sp) - 800024a8: d89ff0ef jal ra,80002230 - 800024ac: 10100693 li a3,257 - 800024b0: 04100713 li a4,65 - 800024b4: 00000617 auipc a2,0x0 - 800024b8: 7b460613 addi a2,a2,1972 # 80002c68 - 800024bc: fffff797 auipc a5,0xfffff - 800024c0: b4478793 addi a5,a5,-1212 # 80001000 - 800024c4: 03069693 slli a3,a3,0x30 - 800024c8: 0007b503 ld a0,0(a5) - 800024cc: 00160613 addi a2,a2,1 - 800024d0: 00d765b3 or a1,a4,a3 - 800024d4: 00050a63 beqz a0,800024e8 - 800024d8: fffff717 auipc a4,0xfffff - 800024dc: b6073423 sd zero,-1176(a4) # 80001040 - 800024e0: 0007b703 ld a4,0(a5) - 800024e4: fe071ae3 bnez a4,800024d8 - 800024e8: 00064703 lbu a4,0(a2) - 800024ec: fffff517 auipc a0,0xfffff - 800024f0: b0b53a23 sd a1,-1260(a0) # 80001000 - 800024f4: fc071ae3 bnez a4,800024c8 - 800024f8: fa5ff06f j 8000249c - 800024fc: 10100693 li a3,257 - 80002500: 04100713 li a4,65 - 80002504: 00000617 auipc a2,0x0 - 80002508: 77c60613 addi a2,a2,1916 # 80002c80 - 8000250c: fffff797 auipc a5,0xfffff - 80002510: af478793 addi a5,a5,-1292 # 80001000 - 80002514: 03069693 slli a3,a3,0x30 - 80002518: 0007b503 ld a0,0(a5) - 8000251c: 00160613 addi a2,a2,1 - 80002520: 00d765b3 or a1,a4,a3 - 80002524: 00050a63 beqz a0,80002538 - 80002528: fffff717 auipc a4,0xfffff - 8000252c: b0073c23 sd zero,-1256(a4) # 80001040 - 80002530: 0007b703 ld a4,0(a5) - 80002534: fe071ae3 bnez a4,80002528 - 80002538: 00064703 lbu a4,0(a2) - 8000253c: fffff517 auipc a0,0xfffff - 80002540: acb53223 sd a1,-1340(a0) # 80001000 - 80002544: fc071ae3 bnez a4,80002518 - 80002548: f55ff06f j 8000249c - 8000254c: 10100613 li a2,257 - 80002550: 04100713 li a4,65 - 80002554: 00000697 auipc a3,0x0 - 80002558: 6cc68693 addi a3,a3,1740 # 80002c20 - 8000255c: fffff797 auipc a5,0xfffff - 80002560: aa478793 addi a5,a5,-1372 # 80001000 - 80002564: 03061613 slli a2,a2,0x30 - 80002568: 0007b503 ld a0,0(a5) - 8000256c: 00168693 addi a3,a3,1 - 80002570: 00c765b3 or a1,a4,a2 - 80002574: 00050a63 beqz a0,80002588 - 80002578: fffff717 auipc a4,0xfffff - 8000257c: ac073423 sd zero,-1336(a4) # 80001040 - 80002580: 0007b703 ld a4,0(a5) - 80002584: fe071ae3 bnez a4,80002578 - 80002588: 0006c703 lbu a4,0(a3) - 8000258c: fffff517 auipc a0,0xfffff - 80002590: a6b53a23 sd a1,-1420(a0) # 80001000 - 80002594: fc071ae3 bnez a4,80002568 - 80002598: f05ff06f j 8000249c - -000000008000259c : - 8000259c: 11853583 ld a1,280(a0) - 800025a0: f9010113 addi sp,sp,-112 - 800025a4: 06813023 sd s0,96(sp) - 800025a8: 06113423 sd ra,104(sp) - 800025ac: 04913c23 sd s1,88(sp) - 800025b0: 05213823 sd s2,80(sp) - 800025b4: 05313423 sd s3,72(sp) - 800025b8: 05413023 sd s4,64(sp) - 800025bc: 03513c23 sd s5,56(sp) - 800025c0: 03613823 sd s6,48(sp) - 800025c4: 03713423 sd s7,40(sp) - 800025c8: 03813023 sd s8,32(sp) - 800025cc: 01913c23 sd s9,24(sp) - 800025d0: 01a13823 sd s10,16(sp) - 800025d4: 01b13423 sd s11,8(sp) - 800025d8: 00800793 li a5,8 - 800025dc: 00050413 mv s0,a0 - 800025e0: 12f58a63 beq a1,a5,80002714 - 800025e4: 00200793 li a5,2 - 800025e8: 06f58063 beq a1,a5,80002648 - 800025ec: ff458793 addi a5,a1,-12 # ff4 <_start-0x7ffff00c> - 800025f0: 00100713 li a4,1 - 800025f4: 00f77663 bleu a5,a4,80002600 - 800025f8: 00f00793 li a5,15 - 800025fc: 1ef59463 bne a1,a5,800027e4 - 80002600: 11043503 ld a0,272(s0) - 80002604: cf9ff0ef jal ra,800022fc - 80002608: 00040513 mv a0,s0 - 8000260c: 06013403 ld s0,96(sp) - 80002610: 06813083 ld ra,104(sp) - 80002614: 05813483 ld s1,88(sp) - 80002618: 05013903 ld s2,80(sp) - 8000261c: 04813983 ld s3,72(sp) - 80002620: 04013a03 ld s4,64(sp) - 80002624: 03813a83 ld s5,56(sp) - 80002628: 03013b03 ld s6,48(sp) - 8000262c: 02813b83 ld s7,40(sp) - 80002630: 02013c03 ld s8,32(sp) - 80002634: 01813c83 ld s9,24(sp) - 80002638: 01013d03 ld s10,16(sp) - 8000263c: 00813d83 ld s11,8(sp) - 80002640: 07010113 addi sp,sp,112 - 80002644: 9f9fd06f j 8000003c - 80002648: 10853703 ld a4,264(a0) - 8000264c: 00377793 andi a5,a4,3 - 80002650: 06079a63 bnez a5,800026c4 - 80002654: 008007ef jal a5,8000265c - 80002658: 00301073 fssr zero - 8000265c: 00072703 lw a4,0(a4) - 80002660: 0007a783 lw a5,0(a5) - 80002664: 04f70c63 beq a4,a5,800026bc - 80002668: 10100513 li a0,257 - 8000266c: 04100793 li a5,65 - 80002670: 00000697 auipc a3,0x0 - 80002674: 6e868693 addi a3,a3,1768 # 80002d58 - 80002678: fffff717 auipc a4,0xfffff - 8000267c: 98870713 addi a4,a4,-1656 # 80001000 - 80002680: 03051513 slli a0,a0,0x30 - 80002684: 00073583 ld a1,0(a4) - 80002688: 00168693 addi a3,a3,1 - 8000268c: 00a7e633 or a2,a5,a0 - 80002690: 00058a63 beqz a1,800026a4 - 80002694: fffff797 auipc a5,0xfffff - 80002698: 9a07b623 sd zero,-1620(a5) # 80001040 - 8000269c: 00073783 ld a5,0(a4) - 800026a0: fe079ae3 bnez a5,80002694 - 800026a4: 0006c783 lbu a5,0(a3) - 800026a8: fffff597 auipc a1,0xfffff - 800026ac: 94c5bc23 sd a2,-1704(a1) # 80001000 - 800026b0: fc079ae3 bnez a5,80002684 - 800026b4: 00300513 li a0,3 - 800026b8: b79ff0ef jal ra,80002230 - 800026bc: 00100513 li a0,1 - 800026c0: b71ff0ef jal ra,80002230 - 800026c4: 10100793 li a5,257 - 800026c8: 00000617 auipc a2,0x0 - 800026cc: 66860613 addi a2,a2,1640 # 80002d30 - 800026d0: 04100693 li a3,65 - 800026d4: fffff717 auipc a4,0xfffff - 800026d8: 92c70713 addi a4,a4,-1748 # 80001000 - 800026dc: 03079793 slli a5,a5,0x30 - 800026e0: 00073503 ld a0,0(a4) - 800026e4: 00160613 addi a2,a2,1 - 800026e8: 00f6e5b3 or a1,a3,a5 - 800026ec: 00050a63 beqz a0,80002700 - 800026f0: fffff697 auipc a3,0xfffff - 800026f4: 9406b823 sd zero,-1712(a3) # 80001040 - 800026f8: 00073683 ld a3,0(a4) - 800026fc: fe069ae3 bnez a3,800026f0 - 80002700: 00064683 lbu a3,0(a2) - 80002704: fffff517 auipc a0,0xfffff - 80002708: 8eb53e23 sd a1,-1796(a0) # 80001000 - 8000270c: fc069ae3 bnez a3,800026e0 - 80002710: fa5ff06f j 800026b4 - 80002714: 05052983 lw s3,80(a0) - 80002718: 00001437 lui s0,0x1 - 8000271c: 00005d17 auipc s10,0x5 - 80002720: cd4d0d13 addi s10,s10,-812 # 800073f0 - 80002724: 00001b97 auipc s7,0x1 - 80002728: 8dcb8b93 addi s7,s7,-1828 # 80003000 - 8000272c: 00040b37 lui s6,0x40 - 80002730: ffe00ab7 lui s5,0xffe00 - 80002734: 00005a17 auipc s4,0x5 - 80002738: 0aca0a13 addi s4,s4,172 # 800077e0 - 8000273c: 0003f937 lui s2,0x3f - 80002740: 01c0006f j 8000275c - 80002744: 00f73423 sd a5,8(a4) - 80002748: 00005717 auipc a4,0x5 - 8000274c: 08f73c23 sd a5,152(a4) # 800077e0 - 80002750: 000017b7 lui a5,0x1 - 80002754: 00f40433 add s0,s0,a5 - 80002758: 15240663 beq s0,s2,800028a4 - 8000275c: 00c45793 srli a5,s0,0xc - 80002760: 00479493 slli s1,a5,0x4 - 80002764: 009d0733 add a4,s10,s1 - 80002768: 00073703 ld a4,0(a4) - 8000276c: fe0702e3 beqz a4,80002750 - 80002770: 60078793 addi a5,a5,1536 # 1600 <_start-0x7fffea00> - 80002774: 00379793 slli a5,a5,0x3 - 80002778: 00fb87b3 add a5,s7,a5 - 8000277c: 0007bc03 ld s8,0(a5) - 80002780: 040c7793 andi a5,s8,64 - 80002784: 0e078463 beqz a5,8000286c - 80002788: 100b2cf3 csrrs s9,sstatus,s6 - 8000278c: 01540db3 add s11,s0,s5 - 80002790: 00001637 lui a2,0x1 - 80002794: 000d8593 mv a1,s11 - 80002798: 00040513 mv a0,s0 - 8000279c: 975ff0ef jal ra,80002110 - 800027a0: 00050e63 beqz a0,800027bc - 800027a4: 080c7c13 andi s8,s8,128 - 800027a8: 080c0663 beqz s8,80002834 - 800027ac: 00001637 lui a2,0x1 - 800027b0: 000d8593 mv a1,s11 - 800027b4: 00040513 mv a0,s0 - 800027b8: 849ff0ef jal ra,80002000 - 800027bc: 009d07b3 add a5,s10,s1 - 800027c0: 100c9073 csrw sstatus,s9 - 800027c4: 000a3703 ld a4,0(s4) - 800027c8: 0007b023 sd zero,0(a5) - 800027cc: f6071ce3 bnez a4,80002744 - 800027d0: 00005717 auipc a4,0x5 - 800027d4: 00f73823 sd a5,16(a4) # 800077e0 - 800027d8: 00005717 auipc a4,0x5 - 800027dc: 00f73823 sd a5,16(a4) # 800077e8 - 800027e0: f71ff06f j 80002750 - 800027e4: 10100793 li a5,257 - 800027e8: 04100613 li a2,65 - 800027ec: 00000697 auipc a3,0x0 - 800027f0: 59c68693 addi a3,a3,1436 # 80002d88 - 800027f4: fffff717 auipc a4,0xfffff - 800027f8: 80c70713 addi a4,a4,-2036 # 80001000 - 800027fc: 03079793 slli a5,a5,0x30 - 80002800: 00073503 ld a0,0(a4) - 80002804: 00168693 addi a3,a3,1 - 80002808: 00f665b3 or a1,a2,a5 - 8000280c: 00050a63 beqz a0,80002820 - 80002810: fffff617 auipc a2,0xfffff - 80002814: 82063823 sd zero,-2000(a2) # 80001040 - 80002818: 00073603 ld a2,0(a4) - 8000281c: fe061ae3 bnez a2,80002810 - 80002820: 0006c603 lbu a2,0(a3) - 80002824: ffffe517 auipc a0,0xffffe - 80002828: 7cb53e23 sd a1,2012(a0) # 80001000 - 8000282c: fc061ae3 bnez a2,80002800 - 80002830: e85ff06f j 800026b4 - 80002834: 10100793 li a5,257 - 80002838: 04100613 li a2,65 - 8000283c: 00000697 auipc a3,0x0 - 80002840: 4bc68693 addi a3,a3,1212 # 80002cf8 - 80002844: ffffe717 auipc a4,0xffffe - 80002848: 7bc70713 addi a4,a4,1980 # 80001000 - 8000284c: 03079793 slli a5,a5,0x30 - 80002850: 00168693 addi a3,a3,1 - 80002854: 00f665b3 or a1,a2,a5 - 80002858: 00073603 ld a2,0(a4) - 8000285c: 04060863 beqz a2,800028ac - 80002860: ffffe617 auipc a2,0xffffe - 80002864: 7e063023 sd zero,2016(a2) # 80001040 - 80002868: ff1ff06f j 80002858 - 8000286c: 10100793 li a5,257 - 80002870: 04100613 li a2,65 - 80002874: 00000697 auipc a3,0x0 - 80002878: 44c68693 addi a3,a3,1100 # 80002cc0 - 8000287c: ffffe717 auipc a4,0xffffe - 80002880: 78470713 addi a4,a4,1924 # 80001000 - 80002884: 03079793 slli a5,a5,0x30 - 80002888: 00168693 addi a3,a3,1 - 8000288c: 00f665b3 or a1,a2,a5 - 80002890: 00073603 ld a2,0(a4) - 80002894: 02060663 beqz a2,800028c0 - 80002898: ffffe617 auipc a2,0xffffe - 8000289c: 7a063423 sd zero,1960(a2) # 80001040 - 800028a0: ff1ff06f j 80002890 - 800028a4: 00098513 mv a0,s3 - 800028a8: 989ff0ef jal ra,80002230 - 800028ac: 0006c603 lbu a2,0(a3) - 800028b0: ffffe517 auipc a0,0xffffe - 800028b4: 74b53823 sd a1,1872(a0) # 80001000 - 800028b8: f8061ce3 bnez a2,80002850 - 800028bc: df9ff06f j 800026b4 - 800028c0: 0006c603 lbu a2,0(a3) - 800028c4: ffffe517 auipc a0,0xffffe - 800028c8: 72b53e23 sd a1,1852(a0) # 80001000 - 800028cc: fa061ee3 bnez a2,80002888 - 800028d0: de5ff06f j 800026b4 - -00000000800028d4 : - 800028d4: f14027f3 csrr a5,mhartid - 800028d8: 18079a63 bnez a5,80002a6c - 800028dc: 00001697 auipc a3,0x1 - 800028e0: 72468693 addi a3,a3,1828 # 80004000 - 800028e4: 00002717 auipc a4,0x2 - 800028e8: 71c70713 addi a4,a4,1820 # 80005000 - 800028ec: 00c6d693 srli a3,a3,0xc - 800028f0: 00c75713 srli a4,a4,0xc - 800028f4: 00003797 auipc a5,0x3 - 800028f8: 70c78793 addi a5,a5,1804 # 80006000 - 800028fc: 00a69693 slli a3,a3,0xa - 80002900: 00a71713 slli a4,a4,0xa - 80002904: 0016e693 ori a3,a3,1 - 80002908: 00176713 ori a4,a4,1 - 8000290c: 00c7d793 srli a5,a5,0xc - 80002910: 00000897 auipc a7,0x0 - 80002914: 6ed8b823 sd a3,1776(a7) # 80003000 - 80002918: 00a79793 slli a5,a5,0xa - 8000291c: 00001697 auipc a3,0x1 - 80002920: 6ce6be23 sd a4,1756(a3) # 80003ff8 - 80002924: 20000737 lui a4,0x20000 - 80002928: 0cf70713 addi a4,a4,207 # 200000cf <_start-0x5fffff31> - 8000292c: fff00593 li a1,-1 - 80002930: 0017e793 ori a5,a5,1 - 80002934: 00000617 auipc a2,0x0 - 80002938: 6cc60613 addi a2,a2,1740 # 80003000 - 8000293c: ed010113 addi sp,sp,-304 - 80002940: 03f59813 slli a6,a1,0x3f - 80002944: 00003697 auipc a3,0x3 - 80002948: 6ae6ba23 sd a4,1716(a3) # 80005ff8 - 8000294c: 00001717 auipc a4,0x1 - 80002950: 6af73a23 sd a5,1716(a4) # 80004000 - 80002954: 00c65793 srli a5,a2,0xc - 80002958: 12113423 sd ra,296(sp) - 8000295c: 12813023 sd s0,288(sp) - 80002960: 0107e7b3 or a5,a5,a6 - 80002964: 18079073 csrw satp,a5 - 80002968: 01f00793 li a5,31 - 8000296c: 00000297 auipc t0,0x0 - 80002970: 01428293 addi t0,t0,20 # 80002980 - 80002974: 305292f3 csrrw t0,mtvec,t0 - 80002978: 3b059073 csrw pmpaddr0,a1 - 8000297c: 3a079073 csrw pmpcfg0,a5 - 80002980: bff00813 li a6,-1025 - 80002984: 01581813 slli a6,a6,0x15 - 80002988: ffffd797 auipc a5,0xffffd - 8000298c: 73c78793 addi a5,a5,1852 # 800000c4 - 80002990: 010787b3 add a5,a5,a6 - 80002994: 10579073 csrw stvec,a5 - 80002998: 340027f3 csrr a5,mscratch - 8000299c: 010787b3 add a5,a5,a6 - 800029a0: 14079073 csrw sscratch,a5 - 800029a4: 0000b7b7 lui a5,0xb - 800029a8: 1007879b addiw a5,a5,256 - 800029ac: 30279073 csrw medeleg,a5 - 800029b0: 0001e7b7 lui a5,0x1e - 800029b4: 30079073 csrw mstatus,a5 - 800029b8: 30405073 csrwi mie,0 - 800029bc: 00004697 auipc a3,0x4 - 800029c0: 64468693 addi a3,a3,1604 # 80007000 - 800029c4: 010687b3 add a5,a3,a6 - 800029c8: 3e078713 addi a4,a5,992 # 1e3e0 <_start-0x7ffe1c20> - 800029cc: 00005617 auipc a2,0x5 - 800029d0: e0f63e23 sd a5,-484(a2) # 800077e8 - 800029d4: 00005797 auipc a5,0x5 - 800029d8: e0e7b623 sd a4,-500(a5) # 800077e0 - 800029dc: 00005317 auipc t1,0x5 - 800029e0: a1430313 addi t1,t1,-1516 # 800073f0 - 800029e4: 03d00793 li a5,61 - 800029e8: 000808b7 lui a7,0x80 - 800029ec: 01080813 addi a6,a6,16 - 800029f0: 03f7871b addiw a4,a5,63 - 800029f4: 02071713 slli a4,a4,0x20 - 800029f8: 0017d61b srliw a2,a5,0x1 - 800029fc: 02075713 srli a4,a4,0x20 - 80002a00: 00c7c7b3 xor a5,a5,a2 - 80002a04: 01170733 add a4,a4,a7 - 80002a08: 010685b3 add a1,a3,a6 - 80002a0c: 00c71713 slli a4,a4,0xc - 80002a10: 0057979b slliw a5,a5,0x5 - 80002a14: 00e6b023 sd a4,0(a3) - 80002a18: 00b6b423 sd a1,8(a3) - 80002a1c: 0207f793 andi a5,a5,32 - 80002a20: 01068693 addi a3,a3,16 - 80002a24: 00c7e7b3 or a5,a5,a2 - 80002a28: fcd314e3 bne t1,a3,800029f0 - 80002a2c: 00050413 mv s0,a0 - 80002a30: 12000613 li a2,288 - 80002a34: 00000593 li a1,0 - 80002a38: 00010513 mv a0,sp - 80002a3c: 00005797 auipc a5,0x5 - 80002a40: 9a07b623 sd zero,-1620(a5) # 800073e8 - 80002a44: e18ff0ef jal ra,8000205c - 80002a48: 800007b7 lui a5,0x80000 - 80002a4c: 00f40433 add s0,s0,a5 - 80002a50: 00010513 mv a0,sp - 80002a54: 10813423 sd s0,264(sp) - 80002a58: de4fd0ef jal ra,8000003c - 80002a5c: 12813083 ld ra,296(sp) - 80002a60: 12013403 ld s0,288(sp) - 80002a64: 13010113 addi sp,sp,304 - 80002a68: 00008067 ret - 80002a6c: 0ffa37b7 lui a5,0xffa3 - 80002a70: 000805b7 lui a1,0x80 - 80002a74: 57578793 addi a5,a5,1397 # ffa3575 <_start-0x7005ca8b> - 80002a78: ffc58593 addi a1,a1,-4 # 7fffc <_start-0x7ff80004> - 80002a7c: 00100613 li a2,1 - 80002a80: 00b7f733 and a4,a5,a1 - 80002a84: 01f61613 slli a2,a2,0x1f - 80002a88: 0017f693 andi a3,a5,1 - 80002a8c: 02079793 slli a5,a5,0x20 - 80002a90: 0207d793 srli a5,a5,0x20 - 80002a94: 00c70733 add a4,a4,a2 - 80002a98: 02068263 beqz a3,80002abc - 80002a9c: 0007202f amoadd.w zero,zero,(a4) - 80002aa0: 0017d793 srli a5,a5,0x1 - 80002aa4: 00b7f733 and a4,a5,a1 - 80002aa8: 0017f693 andi a3,a5,1 - 80002aac: 02079793 slli a5,a5,0x20 - 80002ab0: 0207d793 srli a5,a5,0x20 - 80002ab4: 00c70733 add a4,a4,a2 - 80002ab8: fe0692e3 bnez a3,80002a9c - 80002abc: 00072003 lw zero,0(a4) - 80002ac0: 0017d793 srli a5,a5,0x1 - 80002ac4: fe1ff06f j 80002aa4 - -0000000080002ac8 : - 80002ac8: 01400093 li ra,20 - 80002acc: 00600113 li sp,6 - 80002ad0: 0220ef3b remw t5,ra,sp - 80002ad4: 00200e93 li t4,2 - 80002ad8: 00200193 li gp,2 - 80002adc: 0fdf1063 bne t5,t4,80002bbc - -0000000080002ae0 : - 80002ae0: fec00093 li ra,-20 - 80002ae4: 00600113 li sp,6 - 80002ae8: 0220ef3b remw t5,ra,sp - 80002aec: ffe00e93 li t4,-2 - 80002af0: 00300193 li gp,3 - 80002af4: 0ddf1463 bne t5,t4,80002bbc - -0000000080002af8 : - 80002af8: 01400093 li ra,20 - 80002afc: ffa00113 li sp,-6 - 80002b00: 0220ef3b remw t5,ra,sp - 80002b04: 00200e93 li t4,2 - 80002b08: 00400193 li gp,4 - 80002b0c: 0bdf1863 bne t5,t4,80002bbc - -0000000080002b10 : - 80002b10: fec00093 li ra,-20 - 80002b14: ffa00113 li sp,-6 - 80002b18: 0220ef3b remw t5,ra,sp - 80002b1c: ffe00e93 li t4,-2 - 80002b20: 00500193 li gp,5 - 80002b24: 09df1c63 bne t5,t4,80002bbc - -0000000080002b28 : - 80002b28: 800000b7 lui ra,0x80000 - 80002b2c: 00100113 li sp,1 - 80002b30: 0220ef3b remw t5,ra,sp - 80002b34: 00000e93 li t4,0 - 80002b38: 00600193 li gp,6 - 80002b3c: 09df1063 bne t5,t4,80002bbc - -0000000080002b40 : - 80002b40: 800000b7 lui ra,0x80000 - 80002b44: fff00113 li sp,-1 - 80002b48: 0220ef3b remw t5,ra,sp - 80002b4c: 00000e93 li t4,0 - 80002b50: 00700193 li gp,7 - 80002b54: 07df1463 bne t5,t4,80002bbc - -0000000080002b58 : - 80002b58: 800000b7 lui ra,0x80000 - 80002b5c: 00000113 li sp,0 - 80002b60: 0220ef3b remw t5,ra,sp - 80002b64: 80000eb7 lui t4,0x80000 - 80002b68: 00800193 li gp,8 - 80002b6c: 05df1863 bne t5,t4,80002bbc - -0000000080002b70 : - 80002b70: 00100093 li ra,1 - 80002b74: 00000113 li sp,0 - 80002b78: 0220ef3b remw t5,ra,sp - 80002b7c: 00100e93 li t4,1 - 80002b80: 00900193 li gp,9 - 80002b84: 03df1c63 bne t5,t4,80002bbc - -0000000080002b88 : - 80002b88: 00000093 li ra,0 - 80002b8c: 00000113 li sp,0 - 80002b90: 0220ef3b remw t5,ra,sp - 80002b94: 00000e93 li t4,0 - 80002b98: 00a00193 li gp,10 - 80002b9c: 03df1063 bne t5,t4,80002bbc - -0000000080002ba0 : - 80002ba0: 89700093 li ra,-1897 - 80002ba4: 00000113 li sp,0 - 80002ba8: 0220ef3b remw t5,ra,sp - 80002bac: 89700e93 li t4,-1897 - 80002bb0: 00b00193 li gp,11 - 80002bb4: 01df1463 bne t5,t4,80002bbc - 80002bb8: 00301a63 bne zero,gp,80002bcc - -0000000080002bbc : - 80002bbc: 00119513 slli a0,gp,0x1 - 80002bc0: 00050063 beqz a0,80002bc0 - 80002bc4: 00156513 ori a0,a0,1 - 80002bc8: 00000073 ecall - -0000000080002bcc : - 80002bcc: 00100513 li a0,1 - 80002bd0: 00000073 ecall - 80002bd4: c0001073 unimp diff --git a/test/riscv/tests/rv64um-v-remw.elf b/test/riscv/tests/rv64um-v-remw.elf deleted file mode 100644 index 74715363..00000000 Binary files a/test/riscv/tests/rv64um-v-remw.elf and /dev/null differ diff --git a/test/run_tests.sh b/test/run_tests.sh index ba0a2112..71c3eea1 100755 --- a/test/run_tests.sh +++ b/test/run_tests.sh @@ -41,8 +41,3 @@ printf "==========================================\n" ./arm/run_tests.sh -printf "\n==========================================\n" -printf "RISCV spec tests\n" -printf "==========================================\n" - -./riscv/run_tests.sh -- cgit v1.2.3 From 8dbe18b8976e30fa88814542ea913ddc4193cd8b Mon Sep 17 00:00:00 2001 From: Shaked Flur Date: Sat, 22 Dec 2018 15:40:32 +0000 Subject: Added RISC-V fence.tso --- etc/regfp.sail | 1 + lib/regfp.sail | 1 + src/lem_interp/sail2_instr_kinds.lem | 7 +++++-- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/etc/regfp.sail b/etc/regfp.sail index 9a6172a9..de842c5c 100644 --- a/etc/regfp.sail +++ b/etc/regfp.sail @@ -75,6 +75,7 @@ typedef barrier_kind = enumerate { Barrier_RISCV_r_r; Barrier_RISCV_rw_w; Barrier_RISCV_w_w; + Barrier_RISCV_tso; Barrier_RISCV_i; Barrier_x86_MFENCE; } diff --git a/lib/regfp.sail b/lib/regfp.sail index fcf10850..cc017585 100644 --- a/lib/regfp.sail +++ b/lib/regfp.sail @@ -79,6 +79,7 @@ enum barrier_kind = { Barrier_RISCV_rw_r, Barrier_RISCV_r_w, Barrier_RISCV_w_r, + Barrier_RISCV_tso, Barrier_RISCV_i, Barrier_x86_MFENCE } diff --git a/src/lem_interp/sail2_instr_kinds.lem b/src/lem_interp/sail2_instr_kinds.lem index 3d238676..eadc85bf 100644 --- a/src/lem_interp/sail2_instr_kinds.lem +++ b/src/lem_interp/sail2_instr_kinds.lem @@ -155,6 +155,7 @@ type barrier_kind = | Barrier_RISCV_rw_r | Barrier_RISCV_r_w | Barrier_RISCV_w_r + | Barrier_RISCV_tso | Barrier_RISCV_i (* X86 *) | Barrier_x86_MFENCE @@ -184,6 +185,7 @@ instance (Show barrier_kind) | Barrier_RISCV_rw_r -> "Barrier_RISCV_rw_r" | Barrier_RISCV_r_w -> "Barrier_RISCV_r_w" | Barrier_RISCV_w_r -> "Barrier_RISCV_w_r" + | Barrier_RISCV_tso -> "Barrier_RISCV_tso" | Barrier_RISCV_i -> "Barrier_RISCV_i" | Barrier_x86_MFENCE -> "Barrier_x86_MFENCE" end @@ -300,7 +302,8 @@ instance (EnumerationType barrier_kind) | Barrier_RISCV_rw_r -> 19 | Barrier_RISCV_r_w -> 20 | Barrier_RISCV_w_r -> 21 - | Barrier_RISCV_i -> 22 - | Barrier_x86_MFENCE -> 23 + | Barrier_RISCV_tso -> 22 + | Barrier_RISCV_i -> 23 + | Barrier_x86_MFENCE -> 24 end end -- cgit v1.2.3 From f70f187dbf667df5e8610978e928d9ba76af8e0e Mon Sep 17 00:00:00 2001 From: Thomas Bauereiss Date: Sun, 23 Dec 2018 13:55:46 +0100 Subject: Remove a comment that breaks Isabelle build With the new comment syntax, Isabelle seems to barf on that comment, apparently due to the backslashes. --- src/gen_lib/sail2_string.lem | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/gen_lib/sail2_string.lem b/src/gen_lib/sail2_string.lem index de7588dc..33a665a0 100644 --- a/src/gen_lib/sail2_string.lem +++ b/src/gen_lib/sail2_string.lem @@ -64,10 +64,6 @@ let rec n_leading_spaces s = | _ -> 0 end else - (* match len with - * (\* | 0 -> 0 *\) - * (\* | 1 -> *\) - * | len -> *) (* Isabelle generation for pattern matching on characters is currently broken, so use an if-expression *) if nth s 0 = #' ' -- cgit v1.2.3 From cb5773b3b4d69750f9693e9c9f4e20de5e06ed3b Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Thu, 20 Dec 2018 16:41:39 +0000 Subject: Coq: make solver try hints before stripping away existentials (which allows us to avoid a Coq bug where the proof isn't recorded correctly) --- lib/coq/Sail2_values.v | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/coq/Sail2_values.v b/lib/coq/Sail2_values.v index b7e9bbc9..e3e039c2 100644 --- a/lib/coq/Sail2_values.v +++ b/lib/coq/Sail2_values.v @@ -1180,6 +1180,8 @@ prepare_for_solver; [ match goal with |- ArithFact (?x _) => is_evar x; idtac "Warning: unknown constraint"; constructor; exact (I : (fun _ => True) _) end | apply ArithFact_mword; assumption | constructor; omega with Z + (* Try sail hints before dropping the existential *) + | constructor; eauto 3 with zarith sail (* The datatypes hints give us some list handling, esp In *) | constructor; drop_exists; eauto 3 with datatypes zarith sail | constructor; idtac "Unable to solve constraint"; dump_context; fail -- cgit v1.2.3 From 1940388163a9379cd6c157f3636439a93c5d4b67 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Thu, 27 Dec 2018 15:17:41 +0000 Subject: Coq: fix name clashes and instantiation calculation --- src/pretty_print_coq.ml | 33 ++++++++++++++++++++++++++++++--- test/coq/pass/fncasts.sail | 21 +++++++++++++++++++++ 2 files changed, 51 insertions(+), 3 deletions(-) create mode 100644 test/coq/pass/fncasts.sail diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml index 9bbe056b..2f63327d 100644 --- a/src/pretty_print_coq.ml +++ b/src/pretty_print_coq.ml @@ -1196,13 +1196,39 @@ let doc_exp, doc_let = else if IdSet.mem f ctxt.recursive_ids then doc_id f, false, false, true else doc_id f, false, false, false in - let (tqs,fn_ty) = Env.get_val_spec_orig f env in + let (tqs,fn_ty) = Env.get_val_spec f env in + (* Calculate the renaming *) + let tqs_map = List.fold_left + (fun m k -> + let kid = kopt_kid k in + KBindings.add (orig_kid kid) kid m) + KBindings.empty (quant_kopts tqs) in let arg_typs, ret_typ, eff = match fn_ty with | Typ_aux (Typ_fn (arg_typs,ret_typ,eff),_) -> arg_typs, ret_typ, eff | _ -> raise (Reporting.err_unreachable l __POS__ "Function not a function type") in let inst = - match instantiation_of_without_type full_exp with + (* We attempt to get an instantiation of the function signature's + type variables which agrees with Coq by + 1. using dummy variables with the expected type of each argument + (avoiding the inferred type, which might have (e.g.) stripped + out an existential quantifier) + 2. calculating the instantiation without using the expected + return type, so that we can work out if we need a cast around + the function call. *) + let dummy_args = + Util.list_mapi (fun i exp -> mk_id ("#coq#arg" ^ string_of_int i), + general_typ_of exp) args + in + let dummy_exp = mk_exp (E_app (f, List.map (fun (id,_) -> mk_exp (E_id id)) dummy_args)) in + let dummy_env = List.fold_left (fun env (id,typ) -> Env.add_local id (Immutable,typ) env) env dummy_args in + let inst_exp = + try infer_exp dummy_env dummy_exp + with ex -> + debug ctxt (lazy (" cannot infer dummy application " ^ Printexc.to_string ex)); + full_exp + in + match instantiation_of_without_type inst_exp with | x -> x (* Not all function applications can be inferred, so try falling back to the type inferred when we know the target type. @@ -1210,7 +1236,8 @@ let doc_exp, doc_let = to cast. *) | exception _ -> instantiation_of full_exp in - let inst = KBindings.fold (fun k u m -> KBindings.add (orig_kid k) u m) inst KBindings.empty in + let inst = KBindings.fold (fun k u m -> KBindings.add (KBindings.find (orig_kid k) tqs_map) u m) inst KBindings.empty in + let () = debug ctxt (lazy (" instantiations: " ^ String.concat ", " (List.map (fun (kid,tyarg) -> string_of_kid kid ^ " => " ^ string_of_typ_arg tyarg) (KBindings.bindings inst)))) in (* Insert existential packing of arguments where necessary *) let doc_arg want_parens arg typ_from_fn = diff --git a/test/coq/pass/fncasts.sail b/test/coq/pass/fncasts.sail new file mode 100644 index 00000000..a18c9ecc --- /dev/null +++ b/test/coq/pass/fncasts.sail @@ -0,0 +1,21 @@ +default Order dec + +$include + +// Check that the Coq backend correctly inserts autocasts. + +// Here we need a cast after the call to concat to change 'n + 'm to 'm + 'n +val cast_result : forall 'n 'm, 'n >= 0 & 'm >= 0. (bits('n), bits('m)) -> bits('m + 'n) +function cast_result (v,w) = v @ w + +/* FIXME: ought to cast result as if there were a type annotation +val no_call : forall 'n 'm, 'n > 0 & 'm > 0. bits('n + 'm) -> bits('m + 'n) +function no_call(v) = v +*/ + +val div_ex : forall 'n 'm, 'n > 0 & 'm > 0. (atom('n), bits('n * 'm)) -> bits('m) + +// Here we need a cast before the call to div_ex to change 'n to 1*'n +val cast_arg : forall 'n, 'n > 0. bits('n) -> bits('n) +function cast_arg(v) = div_ex(1,v) + -- cgit v1.2.3 From 2c887e7d01331d3165120695594eac7a2650ec03 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Thu, 27 Dec 2018 20:00:56 +0000 Subject: Coq: avoid putting ambiguous numeric literals in Coq output There are situations when we really want a more refined expression, such as 8 * n instead of 64 (when we know n = 8 from a case split), but we might not be able to generate it. For now we generate an underscore and let Coq figure it out from the context. --- src/pretty_print_coq.ml | 29 ++++++++++++++++++++++------- test/coq/pass/avoid_lit.sail | 13 +++++++++++++ 2 files changed, 35 insertions(+), 7 deletions(-) create mode 100644 test/coq/pass/avoid_lit.sail diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml index 2f63327d..09c6cafc 100644 --- a/src/pretty_print_coq.ml +++ b/src/pretty_print_coq.ml @@ -1262,14 +1262,29 @@ let doc_exp, doc_let = not (similar_nexps ctxt env n1 n2) | _ -> false in - let want_parens1 = want_parens || autocast in - let arg_pp = - construct_dep_pairs env want_parens1 arg typ_from_fn + (* If the argument is an integer that can be inferred from the + context in a different form, let Coq fill it in. E.g., + when "64" is really "8 * width". Avoid cases where the + type checker has introduced a phantom type variable while + calculating the instantiations. *) + let vars_in_env n = + let ekids = Env.get_typ_vars env in + KidSet.for_all (fun kid -> KBindings.mem kid ekids) (nexp_frees n) in - if autocast && false - then let arg_pp = string "autocast" ^^ space ^^ arg_pp in - if want_parens then parens arg_pp else arg_pp - else arg_pp + match typ_of_arg, typ_from_fn with + | Typ_aux (Typ_app (Id_aux (Id "atom",_),[A_aux (A_nexp n1,_)]),_), + Typ_aux (Typ_app (Id_aux (Id "atom",_),[A_aux (A_nexp n2,_)]),_) + when vars_in_env n2 && not (similar_nexps ctxt env n1 n2) -> + underscore + | _ -> + let want_parens1 = want_parens || autocast in + let arg_pp = + construct_dep_pairs env want_parens1 arg typ_from_fn + in + if autocast && false + then let arg_pp = string "autocast" ^^ space ^^ arg_pp in + if want_parens then parens arg_pp else arg_pp + else arg_pp in let epp = if is_ctor diff --git a/test/coq/pass/avoid_lit.sail b/test/coq/pass/avoid_lit.sail new file mode 100644 index 00000000..7af9ad82 --- /dev/null +++ b/test/coq/pass/avoid_lit.sail @@ -0,0 +1,13 @@ +default Order dec + +$include + +// In the calls to sail_zeros below the Coq version needs to end up with +// 'n for the argument, rather than the literal 8 or 16. We currently do +// this by replacing the literal with an underscore and letting Coq figure +// it out. + +val test : forall 'n, 'n in {8,16}. atom('n) -> bits('n) + +function test(8) = sail_zeros(8) +and test(16) = sail_zeros(16) -- cgit v1.2.3 From ac945514d59d91e51a63149b39b472421e59e299 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Sat, 29 Dec 2018 14:00:40 +0000 Subject: Add separate termination_measure declarations --- language/sail.ott | 2 ++ src/initial_check.ml | 2 ++ src/lexer.mll | 1 + src/parse_ast.ml | 1 + src/parser.mly | 4 +++- src/pretty_print_sail.ml | 3 +++ src/rewriter.ml | 1 + src/rewrites.ml | 31 +++++++++++++++++++++++++++++++ src/type_check.ml | 21 ++++++++++++++++++--- 9 files changed, 62 insertions(+), 4 deletions(-) diff --git a/language/sail.ott b/language/sail.ott index dfd9a423..a07f19ff 100644 --- a/language/sail.ott +++ b/language/sail.ott @@ -990,6 +990,8 @@ def :: 'DEF_' ::= {{ com default kind and type assumptions }} | scattered_def :: :: scattered {{ com scattered function and type definition }} + | 'termination_measure' id pat = exp :: :: measure + {{ com separate termination measure declaration }} | dec_spec :: :: reg_dec {{ com register declaration }} | fundef1 .. fundefn :: I :: internal_mutrec diff --git a/src/initial_check.ml b/src/initial_check.ml index 17b4b515..78314363 100644 --- a/src/initial_check.ml +++ b/src/initial_check.ml @@ -743,6 +743,8 @@ let to_ast_def ctx def : unit def ctx_out = | P.DEF_scattered sdef -> let sdef, ctx = to_ast_scattered ctx sdef in DEF_scattered sdef, ctx + | P.DEF_measure (id, pat, exp) -> + DEF_measure (to_ast_id id, to_ast_pat ctx pat, to_ast_exp ctx exp), ctx let rec remove_mutrec = function | [] -> [] diff --git a/src/lexer.mll b/src/lexer.mll index 57580e7a..1d48b82b 100644 --- a/src/lexer.mll +++ b/src/lexer.mll @@ -182,6 +182,7 @@ let kw_table = ("nondet", (fun x -> Nondet)); ("escape", (fun x -> Escape)); ("configuration", (fun _ -> Configuration)); + ("termination_measure", (fun _ -> TerminationMeasure)); ] diff --git a/src/parse_ast.ml b/src/parse_ast.ml index 65b11373..20a0f48a 100644 --- a/src/parse_ast.ml +++ b/src/parse_ast.ml @@ -531,6 +531,7 @@ def = (* Top-level definition *) | DEF_spec of val_spec (* top-level type constraint *) | DEF_default of default_typing_spec (* default kind and type assumptions *) | DEF_scattered of scattered_def (* scattered definition *) + | DEF_measure of id * pat * exp (* separate termination measure declaration *) | DEF_reg_dec of dec_spec (* register declaration *) | DEF_pragma of string * string * l | DEF_internal_mutrec of fundef list diff --git a/src/parser.mly b/src/parser.mly index 66902953..3ad0931a 100644 --- a/src/parser.mly +++ b/src/parser.mly @@ -183,7 +183,7 @@ let rec desugar_rchain chain s e = %token Pure Register Return Scattered Sizeof Struct Then True TwoCaret TYPE Typedef %token Undefined Union Newtype With Val Constant Constraint Throw Try Catch Exit Bitfield %token Barr Depend Rreg Wreg Rmem Rmemt Wmem Wmv Wmvt Eamem Exmem Undef Unspec Nondet Escape -%token Repeat Until While Do Mutual Var Ref Configuration +%token Repeat Until While Do Mutual Var Ref Configuration TerminationMeasure %nonassoc Then %nonassoc Else @@ -1430,6 +1430,8 @@ def: { DEF_internal_mutrec $3 } | Pragma { DEF_pragma (fst $1, snd $1, loc $startpos $endpos) } + | TerminationMeasure id pat Eq exp + { DEF_measure ($2, $3, $5) } defs_list: | def diff --git a/src/pretty_print_sail.ml b/src/pretty_print_sail.ml index 345312f7..d5758303 100644 --- a/src/pretty_print_sail.ml +++ b/src/pretty_print_sail.ml @@ -662,6 +662,9 @@ let rec doc_def def = group (match def with ^^ hardline ^^ string "}" | DEF_reg_dec dec -> doc_dec dec | DEF_scattered sdef -> doc_scattered sdef + | DEF_measure (id,pat,exp) -> + string "termination_measure" ^^ space ^^ doc_id id ^/^ doc_pat pat ^^ + space ^^ equals ^/^ doc_exp exp | DEF_pragma (pragma, arg, l) -> string ("$" ^ pragma ^ " " ^ arg) | DEF_fixity (prec, n, id) -> diff --git a/src/rewriter.ml b/src/rewriter.ml index a70f6fab..21310b91 100644 --- a/src/rewriter.ml +++ b/src/rewriter.ml @@ -364,6 +364,7 @@ let rewrite_def rewriters d = match d with | DEF_val letbind -> DEF_val (rewriters.rewrite_let rewriters letbind) | DEF_pragma (pragma, arg, l) -> DEF_pragma (pragma, arg, l) | DEF_scattered _ -> raise (Reporting.err_unreachable Parse_ast.Unknown __POS__ "DEF_scattered survived to rewritter") + | DEF_measure (id,pat,exp) -> DEF_measure (id,rewriters.rewrite_pat rewriters pat, rewriters.rewrite_exp rewriters exp) let rewrite_defs_base rewriters (Defs defs) = let rec rewrite ds = match ds with diff --git a/src/rewrites.ml b/src/rewrites.ml index 0ad4c56e..8d53ea54 100644 --- a/src/rewrites.ml +++ b/src/rewrites.ml @@ -4763,6 +4763,35 @@ let minimise_recursive_functions (Defs defs) = | d -> d in Defs (List.map rewrite_def defs) +let move_termination_measures (Defs defs) = + let scan_for id defs = + let rec aux = function + | [] -> None + | (DEF_measure (id',pat,exp))::t -> + if Id.compare id id' == 0 then Some (pat,exp) else aux t + | (DEF_fundef (FD_aux (FD_function (_,_,_,FCL_aux (FCL_Funcl (id',_),_)::_),_)))::_ + | (DEF_spec (VS_aux (VS_val_spec (_,id',_,_),_))::_) + when Id.compare id id' == 0 -> None + | _::t -> aux t + in aux defs + in + let rec aux acc = function + | [] -> List.rev acc + | (DEF_fundef (FD_aux (FD_function (r,ty,e,fs),(l,f_ann))) as d)::t -> begin + let id = match fs with + | [] -> assert false (* TODO *) + | (FCL_aux (FCL_Funcl (id,_),_))::_ -> id + in + match scan_for id t with + | None -> aux (d::acc) t + | Some (pat,exp) -> + let r = Rec_aux (Rec_measure (pat,exp), Generated l) in + aux (DEF_fundef (FD_aux (FD_function (r,ty,e,fs),(l,f_ann)))::acc) t + end + | (DEF_measure _)::t -> aux acc t + | h::t -> aux (h::acc) t + in Defs (aux [] defs) + (* Make recursive functions with a measure use the measure as an explicit recursion limit, enforced by an assertion. *) let rewrite_explicit_measure (Defs defs) = @@ -4881,6 +4910,7 @@ let rewrite_explicit_measure (Defs defs) = | [wpat] -> wpat | _ -> P_aux (P_tup wpats,(loc,empty_tannot)) in + let measure_exp = E_aux (E_cast (int_typ, measure_exp),(loc,empty_tannot)) in let wbody = E_aux (E_app (rec_id id,wexps@[measure_exp]),(loc,empty_tannot)) in let wrapper = FCL_aux (FCL_Funcl (id, Pat_aux (Pat_exp (wpat,wbody),(loc,empty_tannot))),(loc,empty_tannot)) @@ -5008,6 +5038,7 @@ let rewrite_defs_coq = [ ("toplevel_string_append", rewrite_defs_toplevel_string_append); ("pat_string_append", rewrite_defs_pat_string_append); ("mapping_builtins", rewrite_defs_mapping_patterns); + ("move_termination_measures", move_termination_measures); ("rewrite_undefined", rewrite_undefined_if_gen true); ("rewrite_defs_vector_string_pats_to_bit_list", rewrite_defs_vector_string_pats_to_bit_list); ("remove_not_pats", rewrite_defs_not_pats); diff --git a/src/type_check.ml b/src/type_check.ml index 53d87a05..ee80296f 100644 --- a/src/type_check.ml +++ b/src/type_check.ml @@ -4158,6 +4158,22 @@ let check_tannotopt env typq ret_typ = function then () else typ_error l (string_of_bind (typq, ret_typ) ^ " and " ^ string_of_bind (annot_typq, annot_ret_typ) ^ " do not match between function and val spec") +let check_termination_measure env arg_typs pat exp = + let typ = match arg_typs with [x] -> x | _ -> Typ_aux (Typ_tup arg_typs,Unknown) in + let tpat, env = bind_pat_no_guard env (strip_pat pat) typ in + let texp = check_exp env (strip_exp exp) int_typ in + tpat, texp + +let check_termination_measure_decl env (id, pat, exp) = + let quant, typ = Env.get_val_spec id env in + let arg_typs, l = match typ with + | Typ_aux (Typ_fn (arg_typs, _ ,_),l) -> arg_typs,l + | _ -> typ_error (id_loc id) "Function val spec is not a function type" + in + let env = add_typquant l quant env in + let tpat, texp = check_termination_measure env arg_typs pat exp in + DEF_measure (id, tpat, texp) + let check_fundef env (FD_aux (FD_function (recopt, tannotopt, effectopt, funcls), (l, _)) as fd_aux) = let id = match (List.fold_right @@ -4190,9 +4206,7 @@ let check_fundef env (FD_aux (FD_function (recopt, tannotopt, effectopt, funcls) | Rec_aux (Rec_nonrec, l) -> Rec_aux (Rec_nonrec, l) | Rec_aux (Rec_rec, l) -> Rec_aux (Rec_rec, l) | Rec_aux (Rec_measure (measure_p, measure_e), l) -> - let typ = match vtyp_args with [x] -> x | _ -> Typ_aux (Typ_tup vtyp_args,Unknown) in - let tpat, env = bind_pat_no_guard funcl_env (strip_pat measure_p) typ in - let texp = check_exp env (strip_exp measure_e) int_typ in + let tpat, texp = check_termination_measure funcl_env vtyp_args measure_p measure_e in Rec_aux (Rec_measure (tpat, texp), l) in let funcls = List.map (fun funcl -> check_funcl funcl_env funcl typ) funcls in @@ -4439,6 +4453,7 @@ and check_def : 'a. Env.t -> 'a def -> (tannot def) list * Env.t = | DEF_reg_dec (DEC_aux (DEC_alias (id, aspec), (l, annot))) -> cd_err () | DEF_reg_dec (DEC_aux (DEC_typ_alias (typ, id, aspec), (l, tannot))) -> cd_err () | DEF_scattered sdef -> check_scattered env sdef + | DEF_measure (id, pat, exp) -> [check_termination_measure_decl env (id, pat, exp)], env and check : 'a. Env.t -> 'a defs -> tannot defs * Env.t = fun env (Defs defs) -> -- cgit v1.2.3 From 771f041a48f611a4869a7a19fa39672581b5ba9a Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Sat, 29 Dec 2018 14:59:09 +0000 Subject: Coq: ensure that recursive functions compute --- lib/coq/Sail2_prompt.v | 21 +++++++++++++++++++++ src/pretty_print_coq.ml | 2 +- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/lib/coq/Sail2_prompt.v b/lib/coq/Sail2_prompt.v index 85ca95f6..bd0d7750 100644 --- a/lib/coq/Sail2_prompt.v +++ b/lib/coq/Sail2_prompt.v @@ -86,6 +86,27 @@ red. omega. Defined. +(* A version of well-foundedness of measures with a guard to ensure that + definitions can be reduced without inspecting proofs, based on a coq-club + thread featuring Barras, Gonthier and Gregoire, see + https://sympa.inria.fr/sympa/arc/coq-club/2007-07/msg00014.html *) + +Fixpoint pos_guard_wf {A:Type} {R:A -> A -> Prop} (p:positive) : well_founded R -> well_founded R := + match p with + | xH => fun wfR x => Acc_intro x (fun y _ => wfR y) + | xO p' => fun wfR x => let F := pos_guard_wf p' in Acc_intro x (fun y _ => F (F +wfR) y) + | xI p' => fun wfR x => let F := pos_guard_wf p' in Acc_intro x (fun y _ => F (F +wfR) y) + end. + +Definition Zwf_guarded (z:Z) : Acc (Zwf 0) z := + match z with + | Zpos p => pos_guard_wf p (Zwf_well_founded _) _ + | _ => Zwf_well_founded _ _ + end. + + (*val whileM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) -> ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e let rec whileM vars cond body = diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml index 09c6cafc..08844eb5 100644 --- a/src/pretty_print_coq.ml +++ b/src/pretty_print_coq.ml @@ -1296,7 +1296,7 @@ let doc_exp, doc_let = [parens (string "_limit_reduces _acc")] else match f with | Id_aux (Id x,_) when is_prefix "#rec#" x -> - main_call @ [parens (string "Zwf_well_founded _ _")] + main_call @ [parens (string "Zwf_guarded _")] | _ -> main_call in hang 2 (flow (break 1) all) in -- cgit v1.2.3 From 269fdb0ed57814f3fbb41b206a67a3cc7bafc810 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Sun, 30 Dec 2018 14:06:20 +0000 Subject: Sort dependencies of termination measures properly --- src/rewrites.ml | 2 +- src/spec_analysis.ml | 15 ++++++++++++--- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/src/rewrites.ml b/src/rewrites.ml index 8d53ea54..afbba659 100644 --- a/src/rewrites.ml +++ b/src/rewrites.ml @@ -5038,7 +5038,6 @@ let rewrite_defs_coq = [ ("toplevel_string_append", rewrite_defs_toplevel_string_append); ("pat_string_append", rewrite_defs_pat_string_append); ("mapping_builtins", rewrite_defs_mapping_patterns); - ("move_termination_measures", move_termination_measures); ("rewrite_undefined", rewrite_undefined_if_gen true); ("rewrite_defs_vector_string_pats_to_bit_list", rewrite_defs_vector_string_pats_to_bit_list); ("remove_not_pats", rewrite_defs_not_pats); @@ -5060,6 +5059,7 @@ let rewrite_defs_coq = [ ("exp_lift_assign", rewrite_defs_exp_lift_assign); (* ("constraint", rewrite_constraint); *) (* ("remove_assert", rewrite_defs_remove_assert); *) + ("move_termination_measures", move_termination_measures); ("top_sort_defs", top_sort_defs); ("trivial_sizeof", rewrite_trivial_sizeof); ("sizeof", rewrite_sizeof); diff --git a/src/spec_analysis.ml b/src/spec_analysis.ml index 940fbfe5..398f20b5 100644 --- a/src/spec_analysis.ml +++ b/src/spec_analysis.ml @@ -356,9 +356,10 @@ let fv_of_fun consider_var (FD_aux (FD_function(rec_opt,tannot_opt,_,funcls),_) | [] -> failwith "fv_of_fun fell off the end looking for the function name" | FCL_aux(FCL_Funcl(id,_),_)::_ -> string_of_id id in let base_bounds = match rec_opt with - (* Current Sail does not have syntax for declaring functions as recursive, + (* Current Sail does not require syntax for declaring functions as recursive, and type checker does not check whether functions are recursive, so - just always add a self-dependency of functions on themselves + just always add a self-dependency of functions on themselves, as well as + adding dependencies from any specified termination measure further below | Rec_aux(Ast.Rec_rec,_) -> init_env fun_name | _ -> mt*) | _ -> init_env fun_name in @@ -369,6 +370,13 @@ let fv_of_fun consider_var (FD_aux (FD_function(rec_opt,tannot_opt,_,funcls),_) bound, fv_of_typ consider_var bound mt typ | Typ_annot_opt_aux(Typ_annot_opt_none, _) -> base_bounds, mt in + let ns_measure = match rec_opt with + | Rec_aux(Rec_measure (pat,exp),_) -> + let pat_bs,pat_ns = pat_bindings consider_var base_bounds mt pat in + let _, exp_ns,_ = fv_of_exp consider_var pat_bs pat_ns Nameset.empty exp in + exp_ns + | _ -> mt + in let ns = List.fold_right (fun (FCL_aux(FCL_Funcl(_,pexp),_)) ns -> match pexp with | Pat_aux(Pat_exp (pat,exp),_) -> @@ -383,7 +391,7 @@ let fv_of_fun consider_var (FD_aux (FD_function(rec_opt,tannot_opt,_,funcls),_) ) funcls mt in let ns_vs = init_env ("val:" ^ (string_of_id (id_of_fundef fd))) in (* let _ = Printf.eprintf "Function %s uses %s\n" fun_name (set_to_string (Nameset.union ns ns_r)) in *) - init_env fun_name, Nameset.union ns_vs (Nameset.union ns ns_r) + init_env fun_name, Nameset.union ns_vs (Nameset.union ns (Nameset.union ns_r ns_measure)) let fv_of_vspec consider_var (VS_aux(vspec,_)) = match vspec with | VS_val_spec(ts,id,_,_) -> @@ -499,6 +507,7 @@ let fv_of_def consider_var consider_scatter_as_one all_defs = function | DEF_scattered sdef -> fv_of_scattered consider_var consider_scatter_as_one all_defs sdef | DEF_reg_dec rdec -> fv_of_rd consider_var rdec | DEF_pragma _ -> mt,mt + | DEF_measure _ -> mt,mt (* currently removed beforehand *) let group_defs consider_scatter_as_one (Ast.Defs defs) = List.map (fun d -> (fv_of_def false consider_scatter_as_one defs d,d)) defs -- cgit v1.2.3 From dccff374cc4ff0d2ac9737a1abd1907118af6456 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Mon, 31 Dec 2018 11:01:54 +0000 Subject: Coq: move function clause merging to keep measure argument intact --- src/rewrites.ml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/rewrites.ml b/src/rewrites.ml index afbba659..3cd89b89 100644 --- a/src/rewrites.ml +++ b/src/rewrites.ml @@ -5065,6 +5065,9 @@ let rewrite_defs_coq = [ ("sizeof", rewrite_sizeof); ("early_return", rewrite_defs_early_return); ("make_cases_exhaustive", MakeExhaustive.rewrite); + (* merge funcls before adding the measure argument so that it doesn't + disappear into an internal pattern match *) + ("merge function clauses", merge_funcls); ("rewrite_explicit_measure", rewrite_explicit_measure); ("recheck_defs_without_effects", recheck_defs_without_effects); ("fix_val_specs", rewrite_fix_val_specs); @@ -5074,7 +5077,6 @@ let rewrite_defs_coq = [ ("internal_lets", rewrite_defs_internal_lets); ("remove_superfluous_letbinds", rewrite_defs_remove_superfluous_letbinds); ("remove_superfluous_returns", rewrite_defs_remove_superfluous_returns); - ("merge function clauses", merge_funcls); ("recheck_defs", recheck_defs) ] -- cgit v1.2.3 From 534e02c863b5a571c6d8bd65cf72a4ce92fe4701 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Mon, 31 Dec 2018 19:58:32 +0000 Subject: Last rewrite reordering needs more typechecking --- src/rewrites.ml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/rewrites.ml b/src/rewrites.ml index 3cd89b89..7ccff222 100644 --- a/src/rewrites.ml +++ b/src/rewrites.ml @@ -5064,10 +5064,11 @@ let rewrite_defs_coq = [ ("trivial_sizeof", rewrite_trivial_sizeof); ("sizeof", rewrite_sizeof); ("early_return", rewrite_defs_early_return); - ("make_cases_exhaustive", MakeExhaustive.rewrite); (* merge funcls before adding the measure argument so that it doesn't disappear into an internal pattern match *) ("merge function clauses", merge_funcls); + ("recheck_defs", recheck_defs); + ("make_cases_exhaustive", MakeExhaustive.rewrite); ("rewrite_explicit_measure", rewrite_explicit_measure); ("recheck_defs_without_effects", recheck_defs_without_effects); ("fix_val_specs", rewrite_fix_val_specs); -- cgit v1.2.3 From 3e311bd2a9072146f53bf6c2db9a811d38aee601 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Tue, 1 Jan 2019 13:54:31 +0000 Subject: Coq: update instr_kinds from Lem --- lib/coq/Sail2_instr_kinds.v | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/lib/coq/Sail2_instr_kinds.v b/lib/coq/Sail2_instr_kinds.v index eadc567a..c6fb866b 100644 --- a/lib/coq/Sail2_instr_kinds.v +++ b/lib/coq/Sail2_instr_kinds.v @@ -157,6 +157,7 @@ Inductive barrier_kind := | Barrier_RISCV_rw_r | Barrier_RISCV_r_w | Barrier_RISCV_w_r + | Barrier_RISCV_tso | Barrier_RISCV_i (* X86 *) | Barrier_x86_MFENCE. @@ -182,6 +183,11 @@ instance (Show barrier_kind) | Barrier_RISCV_r_r -> "Barrier_RISCV_r_r" | Barrier_RISCV_rw_w -> "Barrier_RISCV_rw_w" | Barrier_RISCV_w_w -> "Barrier_RISCV_w_w" + | Barrier_RISCV_w_rw -> "Barrier_RISCV_w_rw" + | Barrier_RISCV_rw_r -> "Barrier_RISCV_rw_r" + | Barrier_RISCV_r_w -> "Barrier_RISCV_r_w" + | Barrier_RISCV_w_r -> "Barrier_RISCV_w_r" + | Barrier_RISCV_tso -> "Barrier_RISCV_tso" | Barrier_RISCV_i -> "Barrier_RISCV_i" | Barrier_x86_MFENCE -> "Barrier_x86_MFENCE" end @@ -295,8 +301,13 @@ instance (EnumerationType barrier_kind) | Barrier_RISCV_r_r -> 15 | Barrier_RISCV_rw_w -> 16 | Barrier_RISCV_w_w -> 17 - | Barrier_RISCV_i -> 18 - | Barrier_x86_MFENCE -> 19 + | Barrier_RISCV_w_rw -> 18 + | Barrier_RISCV_rw_r -> 19 + | Barrier_RISCV_r_w -> 20 + | Barrier_RISCV_w_r -> 21 + | Barrier_RISCV_tso -> 22 + | Barrier_RISCV_i -> 23 + | Barrier_x86_MFENCE -> 24 end end *) -- cgit v1.2.3 From 5aa29f88c1e31bb9435929f86325f499dccf6d50 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Wed, 2 Jan 2019 20:22:35 +0000 Subject: Coq: tweak recently introduced type check to ignore effects --- src/rewrites.ml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/rewrites.ml b/src/rewrites.ml index 7ccff222..8894f2c8 100644 --- a/src/rewrites.ml +++ b/src/rewrites.ml @@ -4835,8 +4835,8 @@ let rewrite_explicit_measure (Defs defs) = | exception Not_found -> [vs] in (* Add extra argument and assertion to each funcl, and rewrite recursive calls *) - let rewrite_funcl (FCL_aux (FCL_Funcl (id,pexp),ann) as fcl) = - let loc = Parse_ast.Generated (fst ann) in + let rewrite_funcl (FCL_aux (FCL_Funcl (id,pexp),fcl_ann) as fcl) = + let loc = Parse_ast.Generated (fst fcl_ann) in let P_aux (pat,pann),guard,body,ann = destruct_pexp pexp in let extra_pat = P_aux (P_id limit,(loc,empty_tannot)) in let pat = match pat with @@ -4868,7 +4868,7 @@ let rewrite_explicit_measure (Defs defs) = } body in let body = E_aux (E_block [assert_exp; body],(loc,empty_tannot)) in - FCL_aux (FCL_Funcl (rec_id id, construct_pexp (P_aux (pat,pann),guard,body,ann)),ann) + FCL_aux (FCL_Funcl (rec_id id, construct_pexp (P_aux (pat,pann),guard,body,ann)),fcl_ann) in let rewrite_function (FD_aux (FD_function (r,t,e,fcls),ann) as fd) = let loc = Parse_ast.Generated (fst ann) in @@ -5067,7 +5067,7 @@ let rewrite_defs_coq = [ (* merge funcls before adding the measure argument so that it doesn't disappear into an internal pattern match *) ("merge function clauses", merge_funcls); - ("recheck_defs", recheck_defs); + ("recheck_defs_without_effects", recheck_defs_without_effects); ("make_cases_exhaustive", MakeExhaustive.rewrite); ("rewrite_explicit_measure", rewrite_explicit_measure); ("recheck_defs_without_effects", recheck_defs_without_effects); -- cgit v1.2.3 From 31adf7edc7957562555037df1df6bad0cca51cf6 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Wed, 9 Jan 2019 11:01:42 +0000 Subject: Coq: add truncateLSB and import Zeuclid by default --- lib/coq/Sail2_operators_mwords.v | 9 +++++++++ lib/coq/Sail2_values.v | 1 + 2 files changed, 10 insertions(+) diff --git a/lib/coq/Sail2_operators_mwords.v b/lib/coq/Sail2_operators_mwords.v index 809f9d89..7e4abe29 100644 --- a/lib/coq/Sail2_operators_mwords.v +++ b/lib/coq/Sail2_operators_mwords.v @@ -185,10 +185,19 @@ assert ((Z.to_nat m <= Z.to_nat n)%nat). { apply Z2Nat.inj_le; omega. } omega. Qed. +Lemma truncateLSB_eq {m n} : m >= 0 -> m <= n -> (Z.to_nat n = (Z.to_nat n - Z.to_nat m) + Z.to_nat m)%nat. +intros. +assert ((Z.to_nat m <= Z.to_nat n)%nat). +{ apply Z2Nat.inj_le; omega. } +omega. +Qed. Definition vector_truncate {n} (v : mword n) (m : Z) `{ArithFact (m >= 0)} `{ArithFact (m <= n)} : mword m := cast_to_mword (Word.split1 _ _ (cast_word (get_word v) (ltac:(unwrap_ArithFacts; apply truncate_eq; auto) : Z.to_nat n = Z.to_nat m + (Z.to_nat n - Z.to_nat m))%nat)) (ltac:(unwrap_ArithFacts; apply Z2Nat.id; omega) : Z.of_nat (Z.to_nat m) = m). +Definition vector_truncateLSB {n} (v : mword n) (m : Z) `{ArithFact (m >= 0)} `{ArithFact (m <= n)} : mword m := + cast_to_mword (Word.split2 _ _ (cast_word (get_word v) (ltac:(unwrap_ArithFacts; apply truncateLSB_eq; auto) : Z.to_nat n = (Z.to_nat n - Z.to_nat m) + Z.to_nat m)%nat)) (ltac:(unwrap_ArithFacts; apply Z2Nat.id; omega) : Z.of_nat (Z.to_nat m) = m). + Lemma concat_eq {a b} : a >= 0 -> b >= 0 -> Z.of_nat (Z.to_nat b + Z.to_nat a)%nat = a + b. intros. rewrite Nat2Z.inj_add. diff --git a/lib/coq/Sail2_values.v b/lib/coq/Sail2_values.v index e3e039c2..2eabacb3 100644 --- a/lib/coq/Sail2_values.v +++ b/lib/coq/Sail2_values.v @@ -9,6 +9,7 @@ Require Export List. Require Export Sumbool. Require Export DecidableClass. Require Import Eqdep_dec. +Require Export Zeuclid. Import ListNotations. Open Scope Z. -- cgit v1.2.3 From 7d33d9c1837149d31df06b803ed4dbf2ce4053ca Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Wed, 9 Jan 2019 11:02:13 +0000 Subject: Coq: add parens around negative integer literals --- src/pretty_print_coq.ml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml index 08844eb5..5cf17056 100644 --- a/src/pretty_print_coq.ml +++ b/src/pretty_print_coq.ml @@ -585,8 +585,9 @@ let doc_lit (L_aux(lit,l)) = | L_false -> utf8string "false" | L_true -> utf8string "true" | L_num i -> - let ipp = Big_int.to_string i in - utf8string ipp + let s = Big_int.to_string i in + let ipp = utf8string s in + if Big_int.less i Big_int.zero then parens ipp else ipp | L_hex n -> failwith "Shouldn't happen" (*"(num_to_vec " ^ ("0x" ^ n) ^ ")" (*shouldn't happen*)*) | L_bin n -> failwith "Shouldn't happen" (*"(num_to_vec " ^ ("0b" ^ n) ^ ")" (*shouldn't happen*)*) | L_undef -> -- cgit v1.2.3 From 1c80d84c47faef38149e87e000c6721f6aa6245e Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Wed, 9 Jan 2019 13:43:16 +0000 Subject: Coq: the division used in smt.sail should be Euclidean --- lib/coq/Sail2_values.v | 4 ++-- lib/smt.sail | 4 ++-- src/pretty_print_coq.ml | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/lib/coq/Sail2_values.v b/lib/coq/Sail2_values.v index 2eabacb3..219a6f84 100644 --- a/lib/coq/Sail2_values.v +++ b/lib/coq/Sail2_values.v @@ -1655,8 +1655,8 @@ end (* Arithmetic functions which return proofs that match the expected Sail types in smt.sail. *) -Definition div_with_eq n m : {o : Z & ArithFact (o = Z.quot n m)} := build_ex (Z.quot n m). -Definition mod_with_eq n m : {o : Z & ArithFact (o = Z.rem n m)} := build_ex (Z.rem n m). +Definition ediv_with_eq n m : {o : Z & ArithFact (o = ZEuclid.div n m)} := build_ex (ZEuclid.div n m). +Definition emod_with_eq n m : {o : Z & ArithFact (o = ZEuclid.modulo n m)} := build_ex (ZEuclid.modulo n m). Definition abs_with_eq n : {o : Z & ArithFact (o = Z.abs n)} := build_ex (Z.abs n). (* Similarly, for ranges (currently in MIPS) *) diff --git a/lib/smt.sail b/lib/smt.sail index c57f7bd1..7006b190 100644 --- a/lib/smt.sail +++ b/lib/smt.sail @@ -8,7 +8,7 @@ val div = { ocaml: "quotient", lem: "integerDiv", c: "tdiv_int", - coq: "div_with_eq" + coq: "ediv_with_eq" } : forall 'n 'm. (atom('n), atom('m)) -> {'o, 'o == div('n, 'm). atom('o)} overload operator / = {div} @@ -18,7 +18,7 @@ val mod = { ocaml: "modulus", lem: "integerMod", c: "tmod_int", - coq: "mod_with_eq" + coq: "emod_with_eq" } : forall 'n 'm. (atom('n), atom('m)) -> {'o, 'o == mod('n, 'm). atom('o)} overload operator % = {mod} diff --git a/src/pretty_print_coq.ml b/src/pretty_print_coq.ml index 5cf17056..20db317b 100644 --- a/src/pretty_print_coq.ml +++ b/src/pretty_print_coq.ml @@ -239,9 +239,9 @@ let doc_nexp ctx ?(skip_vars=KidSet.empty) nexp = and app (Nexp_aux (n,l) as nexp) = match n with | Nexp_app (Id_aux (Id "div",_), [n1;n2]) - -> separate space [string "Z.quot"; atomic n1; atomic n2] + -> separate space [string "ZEuclid.div"; atomic n1; atomic n2] | Nexp_app (Id_aux (Id "mod",_), [n1;n2]) - -> separate space [string "Z.rem"; atomic n1; atomic n2] + -> separate space [string "ZEuclid.modulo"; atomic n1; atomic n2] | Nexp_app (Id_aux (Id "abs_atom",_), [n1]) -> separate space [string "Z.abs"; atomic n1] | _ -> atomic nexp -- cgit v1.2.3 From de0c19e00194daf0336fc7799f2f2987a2215109 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Wed, 9 Jan 2019 17:11:49 +0000 Subject: Update Coq snapshots --- snapshots/coq-riscv/README.md | 14 - snapshots/coq-riscv/bbv/.gitignore | 10 - snapshots/coq-riscv/bbv/.travis.yml | 5 - snapshots/coq-riscv/bbv/CONTRIBUTORS | 19 - snapshots/coq-riscv/bbv/LICENSE | 21 - snapshots/coq-riscv/bbv/Makefile | 26 - snapshots/coq-riscv/bbv/README.md | 11 - snapshots/coq-riscv/bbv/print_assumptions.sh | 14 - snapshots/coq-riscv/bbv/theories/BinNotation.v | 58 - snapshots/coq-riscv/bbv/theories/BinNotationZ.v | 7 - snapshots/coq-riscv/bbv/theories/DepEq.v | 75 - snapshots/coq-riscv/bbv/theories/DepEqNat.v | 66 - snapshots/coq-riscv/bbv/theories/HexNotation.v | 75 - snapshots/coq-riscv/bbv/theories/HexNotationWord.v | 12 - snapshots/coq-riscv/bbv/theories/HexNotationZ.v | 7 - snapshots/coq-riscv/bbv/theories/NLib.v | 12 - snapshots/coq-riscv/bbv/theories/NatLib.v | 558 - snapshots/coq-riscv/bbv/theories/Nomega.v | 71 - snapshots/coq-riscv/bbv/theories/Word.v | 7283 ---- snapshots/coq-riscv/bbv/theories/WordScope.v | 10 - snapshots/coq-riscv/bbv/theories/ZLib.v | 25 - snapshots/coq-riscv/build | 16 - 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-This directory contains the Coq files for the Sail RISC-V model, in -`sail/riscv`, along with the Sail Coq library (`sail/lib/coq`) and the -MIT BBV library for bitvector support. The `build` script checks all -of the files, and `clean` removes the generated files. The main model -is in `sail/riscv/riscv.v`. - -The Coq version of the model was generated from the Sail sources -available at , -commit `9e9506a582763f7ad4c6c8c57dc514d9fb89b9df`, and were manually -patched to deal with parts of the model that the tool does not fully -deal with, mostly due to recursive functions. The manual changes can -be found in `sail/riscv/coq.patch`. diff --git a/snapshots/coq-riscv/bbv/.gitignore b/snapshots/coq-riscv/bbv/.gitignore deleted file mode 100644 index fb3dc885..00000000 --- a/snapshots/coq-riscv/bbv/.gitignore +++ /dev/null @@ -1,10 +0,0 @@ -*.vo -*.glob -*.aux -*.d -.depend -.*.cache -_CoqProject -Makefile.coq.conf -Makefile.coq -html/ diff --git a/snapshots/coq-riscv/bbv/.travis.yml b/snapshots/coq-riscv/bbv/.travis.yml deleted file mode 100644 index 09ff7977..00000000 --- a/snapshots/coq-riscv/bbv/.travis.yml +++ /dev/null @@ -1,5 +0,0 @@ -# we don't use travis, but the mit-plv organization enabled it for all repos by default, -# so we blacklist all branches: -branches: - except: - - /.*/ diff --git a/snapshots/coq-riscv/bbv/CONTRIBUTORS b/snapshots/coq-riscv/bbv/CONTRIBUTORS deleted file mode 100644 index e134ab51..00000000 --- a/snapshots/coq-riscv/bbv/CONTRIBUTORS +++ /dev/null @@ -1,19 +0,0 @@ -Contributors (in alphabetical order): - -Tej Chajed -Haogang Chen -Adam Chlipala -Joonwon Choi -Andres Erbsen -Jason Gross -Samuel Gruetter -Frans Kaashoek -Alex Konradi -Gregory Malecha -Duckki Oe -Murali Vijayaraghavan -Nickolai Zeldovich -Daniel Ziegler - -This list was generated from the commit history of the various projects from which bbv was merged, so it's likely that some people are missing. If you think someone should be added, please make a pull request! - diff --git a/snapshots/coq-riscv/bbv/LICENSE b/snapshots/coq-riscv/bbv/LICENSE deleted file mode 100644 index 4d718ec2..00000000 --- a/snapshots/coq-riscv/bbv/LICENSE +++ /dev/null @@ -1,21 +0,0 @@ -The MIT License (MIT) - -Copyright (c) 2011-2018, Massachusetts Institute of Technology - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. diff --git a/snapshots/coq-riscv/bbv/Makefile b/snapshots/coq-riscv/bbv/Makefile deleted file mode 100644 index f877aedf..00000000 --- a/snapshots/coq-riscv/bbv/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -default_target: all - -COQMAKEFILE=$(COQBIN)coq_makefile - -all: Makefile.coq - $(MAKE) -f Makefile.coq - -doc: all - $(MAKE) -f Makefile.coq html - -html: doc - -clean: Makefile.coq - $(MAKE) -f Makefile.coq clean - rm -f Makefile.coq Makefile.coq.conf _CoqProject - -install: Makefile.coq - $(MAKE) -f Makefile.coq install - -Makefile.coq: _CoqProject - $(COQMAKEFILE) -f _CoqProject -o Makefile.coq - -_CoqProject:: - rm -f _CoqProject - echo "-Q theories bbv" > _CoqProject - find theories -type f -name '*.v' | sort >> _CoqProject diff --git a/snapshots/coq-riscv/bbv/README.md b/snapshots/coq-riscv/bbv/README.md deleted file mode 100644 index 7bb553bf..00000000 --- a/snapshots/coq-riscv/bbv/README.md +++ /dev/null @@ -1,11 +0,0 @@ -# bbv - Bedrock Bit Vectors - -Several Coq projects at MIT use a file called Word.v, defining bit vectors and lemmas about them. - -This repo unifies the different versions of this file into one repository, so that everyone can benefit from additions made by other projects. - -Suggested collaboration protocol: - -- For non-breaking, backwards-compatible (i.e. just additions) changes you just push to master, to keep the workflow as lightweight as possible. -- For more "controversial" changes which might break something, make a PR. - diff --git a/snapshots/coq-riscv/bbv/print_assumptions.sh b/snapshots/coq-riscv/bbv/print_assumptions.sh deleted file mode 100755 index c0fb4ba6..00000000 --- a/snapshots/coq-riscv/bbv/print_assumptions.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/sh - -if [ "$#" -ne 1 ]; then - echo "Illegal number of parameters" - echo "Usage: 1 arg (name of coq module to consider without .v extension)" - exit 1 -fi - -infile="theories/$1.v" -outfile="$1_print_assumptions.v" - -echo "Require Import bbv.$1." > "$outfile" - -grep -E "$infile" -e '^ *(Lemma|Theorem|Corollary)' | grep -v 'Note: not axiom free' | sed -E -e 's/ *(Lemma|Theorem|Corollary) //g' -e 's/^([^ :]+).*/About \1. Print Assumptions \1./g' >> "$outfile" diff --git a/snapshots/coq-riscv/bbv/theories/BinNotation.v b/snapshots/coq-riscv/bbv/theories/BinNotation.v deleted file mode 100644 index 40763711..00000000 --- a/snapshots/coq-riscv/bbv/theories/BinNotation.v +++ /dev/null @@ -1,58 +0,0 @@ - -(* Adapted from http://poleiro.info/posts/2013-04-03-parse-errors-as-type-errors.html, - https://github.com/arthuraa/poleiro/blob/master/theories/ForceOption.v - to produce N instead of nat *) - -Require Import Coq.Strings.String. -Require Import Coq.Strings.Ascii. -Require Import Coq.NArith.NArith. - -Local Open Scope char_scope. - -Local Open Scope N_scope. - -Definition binDigitToN (c : ascii) : option N := - match c with - | "0" => Some 0 - | "1" => Some 1 - | _ => None - end. - -Open Scope string_scope. - -Fixpoint readBinNAux (s : string) (acc : N) : option N := - match s with - | "" => Some acc - | String c s' => - match binDigitToN c with - | Some n => readBinNAux s' (2 * acc + n) - | None => None - end - end. - -Definition readBinN (s : string) : option N := readBinNAux s 0. - -Goal readBinN "11111111" = Some 255. -Proof. reflexivity. Qed. - -Definition forceOption A Err (o : option A) (err : Err) : match o with - | Some _ => A - | None => Err - end := - match o with - | Some a => a - | None => err - end. - -Inductive parseError := ParseError. - -Definition bin (s : string) := forceOption N parseError (readBinN s) ParseError. - -Goal bin"11111111" = 255. -Proof. reflexivity. Qed. - -Goal bin"1011" = 11. -Proof. reflexivity. Qed. - -Goal bin"1O" = ParseError. -Proof. reflexivity. Qed. diff --git a/snapshots/coq-riscv/bbv/theories/BinNotationZ.v b/snapshots/coq-riscv/bbv/theories/BinNotationZ.v deleted file mode 100644 index c06166d7..00000000 --- a/snapshots/coq-riscv/bbv/theories/BinNotationZ.v +++ /dev/null @@ -1,7 +0,0 @@ -Require Export bbv.BinNotation. -Require Import Coq.ZArith.BinInt. - -Notation "'Ob' a" := (Z.of_N (bin a)) (at level 50). - -Goal Ob"01000001" = 65%Z. -Proof. reflexivity. Qed. diff --git a/snapshots/coq-riscv/bbv/theories/DepEq.v b/snapshots/coq-riscv/bbv/theories/DepEq.v deleted file mode 100644 index 83e9cbad..00000000 --- a/snapshots/coq-riscv/bbv/theories/DepEq.v +++ /dev/null @@ -1,75 +0,0 @@ -Require Import Coq.Arith.Peano_dec. -Require Import Coq.Logic.Eqdep Coq.Logic.Eqdep_dec Coq.Program.Equality. - -(** * Equalities on dependent types *) - -Theorem eq_rect_nat_double : forall T (a b c : nat) x ab bc, - eq_rect b T (eq_rect a T x b ab) c bc = eq_rect a T x c (eq_trans ab bc). -Proof. - intros. - destruct ab. - destruct bc. - rewrite (UIP_dec eq_nat_dec (eq_trans eq_refl eq_refl) eq_refl). - simpl. - auto. -Qed. - -Hint Rewrite eq_rect_nat_double. -Hint Rewrite <- (eq_rect_eq_dec eq_nat_dec). - -Ltac generalize_proof := - match goal with - | [ |- context[eq_rect _ _ _ _ ?H ] ] => generalize H - end. - -Ltac eq_rect_simpl := - unfold eq_rec_r, eq_rec; - repeat rewrite eq_rect_nat_double; - repeat rewrite <- (eq_rect_eq_dec eq_nat_dec). - -Ltac destruct_existT := - repeat match goal with - | [H: existT _ _ _ = existT _ _ _ |- _] => - (apply Eqdep.EqdepTheory.inj_pair2 in H; subst) - end. - -Lemma eq_rect_word_offset_helper : forall a b c, - a = b -> c + a = c + b. -Proof. - intros; congruence. -Qed. - -Lemma eq_rect_word_mult_helper : forall a b c, - a = b -> a * c = b * c. -Proof. - intros; congruence. -Qed. - -Lemma existT_eq_rect: - forall (X: Type) (P: X -> Type) (x1 x2: X) (H1: P x1) (Hx: x1 = x2), - existT P x2 (eq_rect x1 P H1 x2 Hx) = - existT P x1 H1. -Proof. - intros; subst; reflexivity. -Qed. - -Lemma existT_eq_rect_eq: - forall (X: Type) (P: X -> Type) (x1 x2: X) - (H1: P x1) (H2: P x2) (Hx: x1 = x2), - H2 = eq_rect _ P H1 _ Hx -> - existT P x1 H1 = existT P x2 H2. -Proof. - intros; subst; reflexivity. -Qed. - -Lemma eq_rect_existT_eq: - forall (X: Type) (P: X -> Type) (x1 x2: X) - (H1: P x1) (H2: P x2) (Hx: x1 = x2) - (Hex: existT P x1 H1 = existT P x2 H2), - H2 = eq_rect _ P H1 _ Hx. -Proof. - intros; subst. - subst; destruct_existT. - reflexivity. -Qed. - diff --git a/snapshots/coq-riscv/bbv/theories/DepEqNat.v b/snapshots/coq-riscv/bbv/theories/DepEqNat.v deleted file mode 100644 index b68c7e34..00000000 --- a/snapshots/coq-riscv/bbv/theories/DepEqNat.v +++ /dev/null @@ -1,66 +0,0 @@ - -(* This file defines nat_cast, an alternative to eq_rect which works only for type nat instead - of any type A. - The motivation behind nat_cast is that it only matches on proofs in contradictory cases, - so functions using nat_cast can always be run inside Coq using cbv, whereas function using - eq_rect cannot. *) - -Arguments id {A} x. - -(* Transport equality, only matching on eq_refl in contradictory cases, to make sure - terms using this function reduce *) -Fixpoint nat_cast (P : nat -> Type) {n m} : n = m -> P n -> P m. - refine match n, m return n = m -> P n -> P m with - | O, O => fun _ => id - | S n, S m => fun pf => @nat_cast (fun n => P (S n)) n m (f_equal pred pf) - | _, _ => fun pf => match _ pf : False with end - end; - clear; abstract congruence. -Defined. (* thx Jason *) - -Lemma nat_cast_eq_rect: forall (P : nat -> Type), - forall (n m : nat) (e: n = m) (pn: P n), - nat_cast P e pn = eq_rect n P pn m e. -Proof. - destruct e. - revert dependent P; induction n; simpl; intros. - - reflexivity. - - rewrite IHn. reflexivity. -Qed. (* thx Clement *) - -Lemma nat_cast_proof_irrel: forall (P : nat -> Type), - forall (n m : nat) (e1 e2: n = m) (pn: P n), - nat_cast P e1 pn = nat_cast P e2 pn. -Proof. - destruct e1. - revert dependent P; induction n; simpl; intros. - - reflexivity. - - erewrite IHn. reflexivity. -Qed. - -Lemma nat_cast_same: forall (P: nat -> Type) (s: nat) (n: P s), - nat_cast P eq_refl n = n. -Proof. - intros. rewrite nat_cast_eq_rect. reflexivity. -Qed. - -Lemma nat_cast_fuse: forall (P: nat -> Type) (n1 n2 n3: nat) (e12: n1 = n2) (e23: n2 = n3) (x: P n1), - nat_cast P e23 (nat_cast P e12 x) = nat_cast P (eq_trans e12 e23) x. -Proof. - destruct e12. - destruct e23. - intros. - rewrite nat_cast_same. - reflexivity. -Qed. - -Lemma nat_cast_cast ni no (pf: ni = no) (P: nat -> Type) (x : P ni): - nat_cast P pf x = match pf in _ = Y return P Y with - | eq_refl => x - end. -Proof. - destruct pf. - rewrite nat_cast_same. - auto. -Qed. - \ No newline at end of file diff --git a/snapshots/coq-riscv/bbv/theories/HexNotation.v b/snapshots/coq-riscv/bbv/theories/HexNotation.v deleted file mode 100644 index e6f5abfb..00000000 --- a/snapshots/coq-riscv/bbv/theories/HexNotation.v +++ /dev/null @@ -1,75 +0,0 @@ - -(* Adapted from http://poleiro.info/posts/2013-04-03-parse-errors-as-type-errors.html, - https://github.com/arthuraa/poleiro/blob/master/theories/ForceOption.v - to produce N instead of nat *) - -Require Import Coq.Strings.String. -Require Import Coq.Strings.Ascii. -Require Import Coq.NArith.NArith. - -Local Open Scope char_scope. - -Local Open Scope N_scope. - -Definition hexDigitToN (c : ascii) : option N := - match c with - | "0" => Some 0 - | "1" => Some 1 - | "2" => Some 2 - | "3" => Some 3 - | "4" => Some 4 - | "5" => Some 5 - | "6" => Some 6 - | "7" => Some 7 - | "8" => Some 8 - | "9" => Some 9 - | "a" | "A" => Some 10 - | "b" | "B" => Some 11 - | "c" | "C" => Some 12 - | "d" | "D" => Some 13 - | "e" | "E" => Some 14 - | "f" | "F" => Some 15 - | _ => None - end. - -Open Scope string_scope. - -Fixpoint readHexNAux (s : string) (acc : N) : option N := - match s with - | "" => Some acc - | String c s' => - match hexDigitToN c with - | Some n => readHexNAux s' (16 * acc + n) - | None => None - end - end. - -Definition readHexN (s : string) : option N := readHexNAux s 0. - -Goal readHexN "ff" = Some 255. -Proof. reflexivity. Qed. - -Definition forceOption A Err (o : option A) (err : Err) : match o with - | Some _ => A - | None => Err - end := - match o with - | Some a => a - | None => err - end. - -Inductive parseError := ParseError. - -Definition hex (s : string) := forceOption N parseError (readHexN s) ParseError. - -Goal hex"ff" = 255. -Proof. reflexivity. Qed. - -Goal hex"a0f" = 2575. -Proof. reflexivity. Qed. - -Goal hex"1O" = ParseError. -Proof. reflexivity. Qed. - -Goal hex"ff34c8e3" = 4281649379. -Proof. reflexivity. Qed. diff --git a/snapshots/coq-riscv/bbv/theories/HexNotationWord.v b/snapshots/coq-riscv/bbv/theories/HexNotationWord.v deleted file mode 100644 index 1b32427e..00000000 --- a/snapshots/coq-riscv/bbv/theories/HexNotationWord.v +++ /dev/null @@ -1,12 +0,0 @@ -Require Export bbv.HexNotation. -Require Import bbv.WordScope. - -Notation "'Ox' a" := (NToWord _ (hex a)) (at level 50). - -Notation "sz ''h' a" := (NToWord sz (hex a)) (at level 50). - -Goal 8'h"a" = WO~0~0~0~0~1~0~1~0. -Proof. reflexivity. Qed. - -Goal Ox"41" = WO~1~0~0~0~0~0~1. -Proof. reflexivity. Qed. diff --git a/snapshots/coq-riscv/bbv/theories/HexNotationZ.v b/snapshots/coq-riscv/bbv/theories/HexNotationZ.v deleted file mode 100644 index 528f32fb..00000000 --- a/snapshots/coq-riscv/bbv/theories/HexNotationZ.v +++ /dev/null @@ -1,7 +0,0 @@ -Require Export bbv.HexNotation. -Require Import Coq.ZArith.BinInt. - -Notation "'Ox' a" := (Z.of_N (hex a)) (at level 50). - -Goal Ox"41" = 65%Z. -Proof. reflexivity. Qed. diff --git a/snapshots/coq-riscv/bbv/theories/NLib.v b/snapshots/coq-riscv/bbv/theories/NLib.v deleted file mode 100644 index 9def8f83..00000000 --- a/snapshots/coq-riscv/bbv/theories/NLib.v +++ /dev/null @@ -1,12 +0,0 @@ -Require Import Coq.NArith.NArith. - -Local Open Scope N_scope. - -Definition Nlt_dec: forall (l r : N), {l < r} + {l >= r}. - refine (fun l r => - match N.compare l r as k return N.compare l r = k -> _ with - | Lt => fun pf => left _ _ - | _ => fun pf => right _ _ - end (refl_equal _)); - abstract congruence. -Defined. diff --git a/snapshots/coq-riscv/bbv/theories/NatLib.v b/snapshots/coq-riscv/bbv/theories/NatLib.v deleted file mode 100644 index e8bd7c44..00000000 --- a/snapshots/coq-riscv/bbv/theories/NatLib.v +++ /dev/null @@ -1,558 +0,0 @@ -Require Import Coq.Arith.Div2. -Require Import Coq.omega.Omega. -Require Import Coq.NArith.NArith. -Require Import Coq.ZArith.ZArith. - -Require Export bbv.Nomega. - -Set Implicit Arguments. - -Fixpoint mod2 (n : nat) : bool := - match n with - | 0 => false - | 1 => true - | S (S n') => mod2 n' - end. - -Ltac rethink := - match goal with - | [ H : ?f ?n = _ |- ?f ?m = _ ] => replace m with n; simpl; auto - end. - -Theorem mod2_S_double : forall n, mod2 (S (2 * n)) = true. - induction n; simpl; intuition; rethink. -Qed. - -Theorem mod2_double : forall n, mod2 (2 * n) = false. - induction n; simpl; intuition; rewrite <- plus_n_Sm; rethink. -Qed. - -Theorem div2_double : forall n, div2 (2 * n) = n. - induction n; simpl; intuition; rewrite <- plus_n_Sm; f_equal; rethink. -Qed. - -Theorem div2_S_double : forall n, div2 (S (2 * n)) = n. - induction n; simpl; intuition; f_equal; rethink. -Qed. - -Notation pow2 := (Nat.pow 2). - -Fixpoint Npow2 (n : nat) : N := - match n with - | O => 1 - | S n' => 2 * Npow2 n' - end%N. - -Theorem untimes2 : forall n, n + (n + 0) = 2 * n. - auto. -Qed. - -Section strong. - Variable P : nat -> Prop. - - Hypothesis PH : forall n, (forall m, m < n -> P m) -> P n. - - Lemma strong' : forall n m, m <= n -> P m. - induction n; simpl; intuition; apply PH; intuition. - elimtype False; omega. - Qed. - - Theorem strong : forall n, P n. - intros; eapply strong'; eauto. - Qed. -End strong. - -Theorem div2_odd : forall n, - mod2 n = true - -> n = S (2 * div2 n). - induction n as [n] using strong; simpl; intuition. - - destruct n as [|n]; simpl in *; intuition. - discriminate. - destruct n as [|n]; simpl in *; intuition. - do 2 f_equal. - replace (div2 n + S (div2 n + 0)) with (S (div2 n + (div2 n + 0))); auto. -Qed. - -Theorem div2_even : forall n, - mod2 n = false - -> n = 2 * div2 n. - induction n as [n] using strong; simpl; intuition. - - destruct n as [|n]; simpl in *; intuition. - destruct n as [|n]; simpl in *; intuition. - discriminate. - f_equal. - replace (div2 n + S (div2 n + 0)) with (S (div2 n + (div2 n + 0))); auto. -Qed. - -Theorem drop_mod2 : forall n k, - 2 * k <= n - -> mod2 (n - 2 * k) = mod2 n. - induction n as [n] using strong; intros. - - do 2 (destruct n; simpl in *; repeat rewrite untimes2 in *; intuition). - - destruct k; simpl in *; intuition. - - destruct k; simpl; intuition. - rewrite <- plus_n_Sm. - repeat rewrite untimes2 in *. - simpl; auto. - apply H; omega. -Qed. - -Theorem div2_minus_2 : forall n k, - 2 * k <= n - -> div2 (n - 2 * k) = div2 n - k. - induction n as [n] using strong; intros. - - do 2 (destruct n; simpl in *; intuition; repeat rewrite untimes2 in *). - destruct k; simpl in *; intuition. - - destruct k; simpl in *; intuition. - rewrite <- plus_n_Sm. - apply H; omega. -Qed. - -Theorem div2_bound : forall k n, - 2 * k <= n - -> k <= div2 n. - intros ? n H; case_eq (mod2 n); intro Heq. - - rewrite (div2_odd _ Heq) in H. - omega. - - rewrite (div2_even _ Heq) in H. - omega. -Qed. - -Lemma two_times_div2_bound: forall n, 2 * Nat.div2 n <= n. -Proof. - eapply strong. intros n IH. - destruct n. - - constructor. - - destruct n. - + simpl. constructor. constructor. - + simpl (Nat.div2 (S (S n))). - specialize (IH n). omega. -Qed. - -Lemma div2_compat_lt_l: forall a b, b < 2 * a -> Nat.div2 b < a. -Proof. - induction a; intros. - - omega. - - destruct b. - + simpl. omega. - + destruct b. - * simpl. omega. - * simpl. apply lt_n_S. apply IHa. omega. -Qed. - -(* otherwise b is made implicit, while a isn't, which is weird *) -Arguments div2_compat_lt_l {_} {_} _. - -Lemma pow2_add_mul: forall a b, - pow2 (a + b) = (pow2 a) * (pow2 b). -Proof. - induction a; destruct b; firstorder; simpl. - repeat rewrite Nat.add_0_r. - rewrite Nat.mul_1_r; auto. - repeat rewrite Nat.add_0_r. - rewrite IHa. - simpl. - repeat rewrite Nat.add_0_r. - rewrite Nat.mul_add_distr_r; auto. -Qed. - -Lemma mult_pow2_bound: forall a b x y, - x < pow2 a -> y < pow2 b -> x * y < pow2 (a + b). -Proof. - intros. - rewrite pow2_add_mul. - apply Nat.mul_lt_mono_nonneg; omega. -Qed. - -Lemma mult_pow2_bound_ex: forall a c x y, - x < pow2 a -> y < pow2 (c - a) -> c >= a -> x * y < pow2 c. -Proof. - intros. - replace c with (a + (c - a)) by omega. - apply mult_pow2_bound; auto. -Qed. - -Lemma lt_mul_mono' : forall c a b, - a < b -> a < b * (S c). -Proof. - induction c; intros. - rewrite Nat.mul_1_r; auto. - rewrite Nat.mul_succ_r. - apply lt_plus_trans. - apply IHc; auto. -Qed. - -Lemma lt_mul_mono : forall a b c, - c <> 0 -> a < b -> a < b * c. -Proof. - intros. - replace c with (S (c - 1)) by omega. - apply lt_mul_mono'; auto. -Qed. - -Lemma zero_lt_pow2 : forall sz, 0 < pow2 sz. -Proof. - induction sz; simpl; omega. -Qed. - -Lemma one_lt_pow2: - forall n, - 1 < pow2 (S n). -Proof. - intros. - induction n. - simpl; omega. - remember (S n); simpl. - omega. -Qed. - -Lemma one_le_pow2 : forall sz, 1 <= pow2 sz. -Proof. - intros. pose proof (zero_lt_pow2 sz). omega. -Qed. - -Lemma pow2_ne_zero: forall n, pow2 n <> 0. -Proof. - intros. - pose proof (zero_lt_pow2 n). - omega. -Qed. - -Lemma mul2_add : forall n, n * 2 = n + n. -Proof. - induction n; firstorder. -Qed. - -Lemma pow2_le_S : forall sz, (pow2 sz) + 1 <= pow2 (sz + 1). -Proof. - induction sz; simpl; auto. - repeat rewrite Nat.add_0_r. - rewrite pow2_add_mul. - repeat rewrite mul2_add. - pose proof (zero_lt_pow2 sz). - omega. -Qed. - -Lemma pow2_bound_mono: forall a b x, - x < pow2 a -> a <= b -> x < pow2 b. -Proof. - intros. - replace b with (a + (b - a)) by omega. - rewrite pow2_add_mul. - apply lt_mul_mono; auto. - pose proof (zero_lt_pow2 (b - a)). - omega. -Qed. - -Lemma pow2_inc : forall n m, - 0 < n -> n < m -> - pow2 n < pow2 m. -Proof. - intros. - generalize dependent n; intros. - induction m; simpl. - intros. inversion H0. - unfold lt in H0. - rewrite Nat.add_0_r. - inversion H0. - apply Nat.lt_add_pos_r. - apply zero_lt_pow2. - apply Nat.lt_trans with (pow2 m). - apply IHm. - exact H2. - apply Nat.lt_add_pos_r. - apply zero_lt_pow2. -Qed. - -Lemma pow2_S: forall x, pow2 (S x) = 2 * pow2 x. -Proof. intros. reflexivity. Qed. - -Lemma mod2_S_S : forall n, - mod2 (S (S n)) = mod2 n. -Proof. - intros. - destruct n; auto; destruct n; auto. -Qed. - -Lemma mod2_S_not : forall n, - mod2 (S n) = if (mod2 n) then false else true. -Proof. - intros. - induction n; auto. - rewrite mod2_S_S. - destruct (mod2 n); replace (mod2 (S n)); auto. -Qed. - -Lemma mod2_S_eq : forall n k, - mod2 n = mod2 k -> - mod2 (S n) = mod2 (S k). -Proof. - intros. - do 2 rewrite mod2_S_not. - rewrite H. - auto. -Qed. - -Theorem drop_mod2_add : forall n k, - mod2 (n + 2 * k) = mod2 n. -Proof. - intros. - induction n. - simpl. - rewrite Nat.add_0_r. - replace (k + k) with (2 * k) by omega. - apply mod2_double. - replace (S n + 2 * k) with (S (n + 2 * k)) by omega. - apply mod2_S_eq; auto. -Qed. - -Lemma mod2sub: forall a b, - b <= a -> - mod2 (a - b) = xorb (mod2 a) (mod2 b). -Proof. - intros. remember (a - b) as c. revert dependent b. revert a. revert c. - change (forall c, - (fun c => forall a b, b <= a -> c = a - b -> mod2 c = xorb (mod2 a) (mod2 b)) c). - apply strong. - intros c IH a b AB N. - destruct c. - - assert (a=b) by omega. subst. rewrite Bool.xorb_nilpotent. reflexivity. - - destruct c. - + assert (a = S b) by omega. subst a. simpl (mod2 1). rewrite mod2_S_not. - destruct (mod2 b); reflexivity. - + destruct a; [omega|]. - destruct a; [omega|]. - simpl. - apply IH; omega. -Qed. - -Theorem mod2_pow2_twice: forall n, - mod2 (pow2 n + (pow2 n + 0)) = false. -Proof. - intros. - replace (pow2 n + (pow2 n + 0)) with (2 * pow2 n) by omega. - apply mod2_double. -Qed. - -Theorem div2_plus_2 : forall n k, - div2 (n + 2 * k) = div2 n + k. -Proof. - induction n; intros. - simpl. - rewrite Nat.add_0_r. - replace (k + k) with (2 * k) by omega. - apply div2_double. - replace (S n + 2 * k) with (S (n + 2 * k)) by omega. - destruct (Even.even_or_odd n). - - rewrite <- even_div2. - rewrite <- even_div2 by auto. - apply IHn. - apply Even.even_even_plus; auto. - apply Even.even_mult_l; repeat constructor. - - - rewrite <- odd_div2. - rewrite <- odd_div2 by auto. - rewrite IHn. - omega. - apply Even.odd_plus_l; auto. - apply Even.even_mult_l; repeat constructor. -Qed. - -Lemma pred_add: - forall n, n <> 0 -> pred n + 1 = n. -Proof. - intros; rewrite pred_of_minus; omega. -Qed. - -Lemma pow2_zero: forall sz, (pow2 sz > 0)%nat. -Proof. - induction sz; simpl; auto; omega. -Qed. - -Theorem Npow2_nat : forall n, nat_of_N (Npow2 n) = pow2 n. - induction n as [|n IHn]; simpl; intuition. - rewrite <- IHn; clear IHn. - case_eq (Npow2 n); intuition. - rewrite untimes2. - match goal with - | [ |- context[Npos ?p~0] ] - => replace (Npos p~0) with (N.double (Npos p)) by reflexivity - end. - apply nat_of_Ndouble. -Qed. - -Theorem pow2_N : forall n, Npow2 n = N.of_nat (pow2 n). -Proof. - intro n. apply nat_of_N_eq. rewrite Nat2N.id. apply Npow2_nat. -Qed. - -Lemma pow2_S_z: - forall n, Z.of_nat (pow2 (S n)) = (2 * Z.of_nat (pow2 n))%Z. -Proof. - intros. - replace (2 * Z.of_nat (pow2 n))%Z with - (Z.of_nat (pow2 n) + Z.of_nat (pow2 n))%Z by omega. - simpl. - repeat rewrite Nat2Z.inj_add. - ring. -Qed. - -Lemma pow2_le: - forall n m, (n <= m)%nat -> (pow2 n <= pow2 m)%nat. -Proof. - intros. - assert (exists s, n + s = m) by (exists (m - n); omega). - destruct H0; subst. - rewrite pow2_add_mul. - pose proof (pow2_zero x). - replace (pow2 n) with (pow2 n * 1) at 1 by omega. - apply mult_le_compat_l. - omega. -Qed. - -Lemma Zabs_of_nat: - forall n, Z.abs (Z.of_nat n) = Z.of_nat n. -Proof. - unfold Z.of_nat; intros. - destruct n; auto. -Qed. - -Lemma Npow2_not_zero: - forall n, Npow2 n <> 0%N. -Proof. - induction n; simpl; intros; [discriminate|]. - destruct (Npow2 n); auto. - discriminate. -Qed. - -Lemma Npow2_S: - forall n, Npow2 (S n) = (Npow2 n + Npow2 n)%N. -Proof. - simpl; intros. - destruct (Npow2 n); auto. - rewrite <-Pos.add_diag. - reflexivity. -Qed. - -Lemma Npow2_pos: forall a, - (0 < Npow2 a)%N. -Proof. - intros. - destruct (Npow2 a) eqn: E. - - exfalso. apply (Npow2_not_zero a). assumption. - - constructor. -Qed. - -Lemma minus_minus: forall a b c, - c <= b <= a -> - a - (b - c) = a - b + c. -Proof. intros. omega. Qed. - -Lemma even_odd_destruct: forall n, - (exists a, n = 2 * a) \/ (exists a, n = 2 * a + 1). -Proof. - induction n. - - left. exists 0. reflexivity. - - destruct IHn as [[a E] | [a E]]. - + right. exists a. omega. - + left. exists (S a). omega. -Qed. - -Lemma mul_div_undo: forall i c, - c <> 0 -> - c * i / c = i. -Proof. - intros. - pose proof (Nat.div_mul_cancel_l i 1 c) as P. - rewrite Nat.div_1_r in P. - rewrite Nat.mul_1_r in P. - apply P; auto. -Qed. - -Lemma mod_add_r: forall a b, - b <> 0 -> - (a + b) mod b = a mod b. -Proof. - intros. rewrite <- Nat.add_mod_idemp_r by omega. - rewrite Nat.mod_same by omega. - rewrite Nat.add_0_r. - reflexivity. -Qed. - -Lemma mod2_cases: forall (n: nat), n mod 2 = 0 \/ n mod 2 = 1. -Proof. - intros. - assert (n mod 2 < 2). { - apply Nat.mod_upper_bound. congruence. - } - omega. -Qed. - -Lemma div_mul_undo: forall a b, - b <> 0 -> - a mod b = 0 -> - a / b * b = a. -Proof. - intros. - pose proof Nat.div_mul_cancel_l as A. specialize (A a 1 b). - replace (b * 1) with b in A by omega. - rewrite Nat.div_1_r in A. - rewrite mult_comm. - rewrite <- Nat.divide_div_mul_exact; try assumption. - - apply A; congruence. - - apply Nat.mod_divide; assumption. -Qed. - -Lemma Smod2_1: forall k, S k mod 2 = 1 -> k mod 2 = 0. -Proof. - intros k C. - change (S k) with (1 + k) in C. - rewrite Nat.add_mod in C by congruence. - pose proof (Nat.mod_upper_bound k 2). - assert (k mod 2 = 0 \/ k mod 2 = 1) as E by omega. - destruct E as [E | E]; [assumption|]. - rewrite E in C. simpl in C. discriminate. -Qed. - -Lemma mod_0_r: forall (m: nat), - m mod 0 = 0. -Proof. - intros. reflexivity. -Qed. - -Lemma sub_mod_0: forall (a b m: nat), - a mod m = 0 -> - b mod m = 0 -> - (a - b) mod m = 0. -Proof. - intros. assert (m = 0 \/ m <> 0) as C by omega. destruct C as [C | C]. - - subst. apply mod_0_r. - - assert (a - b = 0 \/ b < a) as D by omega. destruct D as [D | D]. - + rewrite D. apply Nat.mod_0_l. assumption. - + apply Nat2Z.inj. simpl. - rewrite Zdiv.mod_Zmod by assumption. - rewrite Nat2Z.inj_sub by omega. - rewrite Zdiv.Zminus_mod. - rewrite <-! Zdiv.mod_Zmod by assumption. - rewrite H. rewrite H0. - apply Z.mod_0_l. - omega. -Qed. - -Lemma mul_div_exact: forall (a b: nat), - b <> 0 -> - a mod b = 0 -> - b * (a / b) = a. -Proof. - intros. edestruct Nat.div_exact as [_ P]; [eassumption|]. - specialize (P H0). symmetry. exact P. -Qed. diff --git a/snapshots/coq-riscv/bbv/theories/Nomega.v b/snapshots/coq-riscv/bbv/theories/Nomega.v deleted file mode 100644 index 9b284f15..00000000 --- a/snapshots/coq-riscv/bbv/theories/Nomega.v +++ /dev/null @@ -1,71 +0,0 @@ -(* Make [omega] work for [N] *) - -Require Import Coq.Arith.Arith Coq.omega.Omega Coq.NArith.NArith. - -Local Open Scope N_scope. - -Hint Rewrite Nplus_0_r nat_of_Nsucc nat_of_Nplus nat_of_Nminus - N_of_nat_of_N nat_of_N_of_nat - nat_of_P_o_P_of_succ_nat_eq_succ nat_of_P_succ_morphism : N. - -Theorem nat_of_N_eq : forall n m, - nat_of_N n = nat_of_N m - -> n = m. - intros ? ? H; apply (f_equal N_of_nat) in H; - autorewrite with N in *; assumption. -Qed. - -Theorem Nneq_in : forall n m, - nat_of_N n <> nat_of_N m - -> n <> m. - congruence. -Qed. - -Theorem Nneq_out : forall n m, - n <> m - -> nat_of_N n <> nat_of_N m. - intuition. - match goal with H0 : _ |- _ => apply nat_of_N_eq in H0; tauto end. -Qed. - -Theorem Nlt_out : forall n m, n < m - -> (nat_of_N n < nat_of_N m)%nat. - unfold N.lt; intros ?? H. - rewrite nat_of_Ncompare in H. - apply nat_compare_Lt_lt; assumption. -Qed. - -Theorem Nlt_in : forall n m, (nat_of_N n < nat_of_N m)%nat - -> n < m. - unfold N.lt; intros. - rewrite nat_of_Ncompare. - apply (proj1 (nat_compare_lt _ _)); assumption. -Qed. - -Theorem Nge_out : forall n m, n >= m - -> (nat_of_N n >= nat_of_N m)%nat. - unfold N.ge; intros ?? H. - rewrite nat_of_Ncompare in H. - apply nat_compare_ge; assumption. -Qed. - -Theorem Nge_in : forall n m, (nat_of_N n >= nat_of_N m)%nat - -> n >= m. - unfold N.ge; intros. - rewrite nat_of_Ncompare. - apply nat_compare_ge; assumption. -Qed. - -Ltac nsimp H := simpl in H; repeat progress (autorewrite with N in H; simpl in H). - -Ltac pre_nomega := - try (apply nat_of_N_eq || apply Nneq_in || apply Nlt_in || apply Nge_in); simpl; - repeat (progress autorewrite with N; simpl); - repeat match goal with - | [ H : _ <> _ |- _ ] => apply Nneq_out in H; nsimp H - | [ H : _ = _ -> False |- _ ] => apply Nneq_out in H; nsimp H - | [ H : _ |- _ ] => (apply (f_equal nat_of_N) in H - || apply Nlt_out in H || apply Nge_out in H); nsimp H - end. - -Ltac nomega := pre_nomega; omega || (unfold nat_of_P in *; simpl in *; omega). diff --git a/snapshots/coq-riscv/bbv/theories/Word.v b/snapshots/coq-riscv/bbv/theories/Word.v deleted file mode 100644 index 672c2254..00000000 --- a/snapshots/coq-riscv/bbv/theories/Word.v +++ /dev/null @@ -1,7283 +0,0 @@ -(** Fixed precision machine words *) - -Require Import Coq.Arith.Arith Coq.Arith.Div2 Coq.NArith.NArith Coq.Bool.Bool Coq.omega.Omega. -Require Import Coq.Logic.Eqdep_dec Coq.Logic.EqdepFacts. -Require Import Coq.Program.Tactics Coq.Program.Equality. -Require Import Coq.setoid_ring.Ring. -Require Import Coq.setoid_ring.Ring_polynom. -Require Import bbv.Nomega. -Require Export bbv.ZLib bbv.NatLib bbv.NLib. -Require Export bbv.DepEq bbv.DepEqNat. - -Require Import Coq.micromega.Lia. -(* for nia (integer arithmetic with multiplications that omega cannot solve *) - -Set Implicit Arguments. - -(*! Definitions *) - -(** * [word] *) - -Inductive word : nat -> Set := -| WO : word O -| WS : bool -> forall n, word n -> word (S n). - -Delimit Scope word_scope with word. -Bind Scope word_scope with word. - -(* This scope will be closed at the end of the file. *) -(* Coq trunk seems to inherit open scopes across imports? *) -Open Scope word_scope. - -(** * Conversion to and from [nat] (or [N]), zero and one *) - -Fixpoint wordToNat sz (w : word sz) : nat := - match w with - | WO => O - | WS false w' => (wordToNat w') * 2 - | WS true w' => S (wordToNat w' * 2) - end. - -Fixpoint wordToNat' sz (w : word sz) : nat := - match w with - | WO => O - | WS false w' => 2 * wordToNat w' - | WS true w' => S (2 * wordToNat w') - end. - -Fixpoint natToWord (sz n : nat) : word sz := - match sz with - | O => WO - | S sz' => WS (mod2 n) (natToWord sz' (div2 n)) - end. - -Fixpoint wordToN sz (w : word sz) : N := - match w with - | WO => 0 - | WS false w' => 2 * wordToN w' - | WS true w' => N.succ (2 * wordToN w') - end%N. - -Definition wzero sz := natToWord sz 0. - -Fixpoint wzero' (sz : nat) : word sz := - match sz with - | O => WO - | S sz' => WS false (wzero' sz') - end. - -Fixpoint posToWord (sz : nat) (p : positive) {struct p} : word sz := - match sz with - | O => WO - | S sz' => - match p with - | xI p' => WS true (posToWord sz' p') - | xO p' => WS false (posToWord sz' p') - | xH => WS true (wzero' sz') - end - end. - -Definition NToWord (sz : nat) (n : N) : word sz := - match n with - | N0 => wzero' sz - | Npos p => posToWord sz p - end. - -Definition wone sz := natToWord sz 1. - -Fixpoint wones (sz : nat) : word sz := - match sz with - | O => WO - | S sz' => WS true (wones sz') - end. - -(** * MSB, LSB, head, and tail *) - -Fixpoint wmsb sz (w : word sz) (a : bool) : bool := - match w with - | WO => a - | WS b x => wmsb x b - end. - -Definition wlsb sz (w: word (S sz)) := - match w with - | WO => idProp - | WS b _ => b - end. - -Definition whd sz (w : word (S sz)) : bool := - match w in word sz' return match sz' with - | O => unit - | S _ => bool - end with - | WO => tt - | WS b _ => b - end. - -Definition wtl sz (w : word (S sz)) : word sz := - match w in word sz' return match sz' with - | O => unit - | S sz'' => word sz'' - end with - | WO => tt - | WS _ w' => w' - end. - -Fixpoint rep_bit (n : nat) (b : word 1) : word n := - match n as n0 return (word n0) with - | 0 => WO - | S n0 => WS (whd b) (rep_bit n0 b) - end. - -(** * Shattering (to define [weq]) and decidable equality **) - -Lemma shatter_word : forall n (a : word n), - match n return word n -> Prop with - | O => fun a => a = WO - | S _ => fun a => a = WS (whd a) (wtl a) - end a. - destruct a; eauto. -Qed. - -Lemma shatter_word_S : forall n (a : word (S n)), - exists b, exists c, a = WS b c. -Proof. - intros n a; repeat eexists; apply (shatter_word a). -Qed. -Lemma shatter_word_0 : forall a : word 0, - a = WO. -Proof. - intros a; apply (shatter_word a). -Qed. - -Hint Resolve shatter_word_0. - -Definition weq : forall sz (x y : word sz), {x = y} + {x <> y}. - refine (fix weq sz (x : word sz) : forall y : word sz, {x = y} + {x <> y} := - match x in word sz return forall y : word sz, {x = y} + {x <> y} with - | WO => fun _ => left _ _ - | WS b x' => fun y => if bool_dec b (whd y) - then if weq _ x' (wtl y) then left _ _ else right _ _ - else right _ _ - end); clear weq. - - abstract (symmetry; apply shatter_word_0). - - abstract (subst; symmetry; apply (shatter_word (n:=S _) _)). - - let y' := y in (* kludge around warning of mechanically generated names not playing well with [abstract] *) - abstract (rewrite (shatter_word y'); simpl; intro H; injection H; intros; - eauto using inj_pair2_eq_dec, eq_nat_dec). - - let y' := y in (* kludge around warning of mechanically generated names not playing well with [abstract] *) - abstract (rewrite (shatter_word y'); simpl; intro H; injection H; auto). -Defined. - -Fixpoint weqb sz (x : word sz) : word sz -> bool := - match x in word sz return word sz -> bool with - | WO => fun _ => true - | WS b x' => fun y => - if eqb b (whd y) - then if @weqb _ x' (wtl y) then true else false - else false - end. - -(** * Combining and splitting *) - -Fixpoint combine (sz1 : nat) (w : word sz1) : forall sz2, word sz2 -> word (sz1 + sz2) := - match w in word sz1 return forall sz2, word sz2 -> word (sz1 + sz2) with - | WO => fun _ w' => w' - | WS b w' => fun _ w'' => WS b (combine w' w'') - end. - -Fixpoint split1 (sz1 sz2 : nat) : word (sz1 + sz2) -> word sz1 := - match sz1 with - | O => fun _ => WO - | S sz1' => fun w => WS (whd w) (split1 sz1' sz2 (wtl w)) - end. - -Fixpoint split2 (sz1 sz2 : nat) : word (sz1 + sz2) -> word sz2 := - match sz1 with - | O => fun w => w - | S sz1' => fun w => split2 sz1' sz2 (wtl w) - end. - -(** * Extension operators *) - -Definition sext (sz : nat) (w : word sz) (sz' : nat) : word (sz + sz') := - if wmsb w false then - combine w (wones sz') - else - combine w (wzero sz'). - -Definition zext (sz : nat) (w : word sz) (sz' : nat) : word (sz + sz') := - combine w (wzero sz'). - -(** * Arithmetic *) - -Definition wneg sz (x : word sz) : word sz := - NToWord sz (Npow2 sz - wordToN x). - -Definition wordBin (f : N -> N -> N) sz (x y : word sz) : word sz := - NToWord sz (f (wordToN x) (wordToN y)). - -Definition wplus := wordBin Nplus. -Definition wmult := wordBin Nmult. -Definition wdiv := wordBin N.div. -Definition wmod := wordBin Nmod. -Definition wmult' sz (x y : word sz) : word sz := - split2 sz sz (NToWord (sz + sz) (Nmult (wordToN x) (wordToN y))). -Definition wminus sz (x y : word sz) : word sz := wplus x (wneg y). -Definition wnegN sz (x : word sz) : word sz := - natToWord sz (pow2 sz - wordToNat x). - -Definition wordBinN (f : nat -> nat -> nat) sz (x y : word sz) : word sz := - natToWord sz (f (wordToNat x) (wordToNat y)). - -Definition wplusN := wordBinN plus. - -Definition wmultN := wordBinN mult. -Definition wmultN' sz (x y : word sz) : word sz := - split2 sz sz (natToWord (sz + sz) (mult (wordToNat x) (wordToNat y))). - -Definition wminusN sz (x y : word sz) : word sz := wplusN x (wnegN y). - -Notation "w ~ 1" := (WS true w) - (at level 7, left associativity, format "w '~' '1'") : word_scope. -Notation "w ~ 0" := (WS false w) - (at level 7, left associativity, format "w '~' '0'") : word_scope. - -Notation "^~" := wneg. -Notation "l ^+ r" := (@wplus _ l%word r%word) (at level 50, left associativity). -Notation "l ^* r" := (@wmult _ l%word r%word) (at level 40, left associativity). -Notation "l ^- r" := (@wminus _ l%word r%word) (at level 50, left associativity). -Notation "l ^/ r" := (@wdiv _ l%word r%word) (at level 50, left associativity). -Notation "l ^% r" := (@wmod _ l%word r%word) (at level 50, left associativity). - -(** * Bitwise operators *) - -Fixpoint wnot sz (w : word sz) : word sz := - match w with - | WO => WO - | WS b w' => WS (negb b) (wnot w') - end. - -Fixpoint bitwp (f : bool -> bool -> bool) sz (w1 : word sz) : word sz -> word sz := - match w1 with - | WO => fun _ => WO - | WS b w1' => fun w2 => WS (f b (whd w2)) (bitwp f w1' (wtl w2)) - end. - -Definition wnot' sz := bitwp xorb (wones sz). - -Definition wor := bitwp orb. -Definition wand := bitwp andb. -Definition wxor := bitwp xorb. - -Notation "l ^| r" := (@wor _ l%word r%word) (at level 50, left associativity). -Notation "l ^& r" := (@wand _ l%word r%word) (at level 40, left associativity). - -(** * Conversion to and from [Z] *) - -Definition wordToZ sz (w : word sz) : Z := - if wmsb w false then - (** Negative **) - match wordToN (wneg w) with - | N0 => 0%Z - | Npos x => Zneg x - end - else - (** Positive **) - match wordToN w with - | N0 => 0%Z - | Npos x => Zpos x - end. - -Definition uwordToZ sz (w : word sz) : Z := Z.of_N (wordToN w). - -Definition ZToWord (sz : nat) (z : Z) : word sz := - match z with - | Z0 => wzero' sz - | Zpos x => posToWord sz x - | Zneg x => wneg (posToWord sz x) - end. - -(** * Arithmetic by [Z] *) - -Definition wordBinZ (f : Z -> Z -> Z) sz (x y : word sz) : word sz := - ZToWord sz (f (wordToZ x) (wordToZ y)). - -Definition wplusZ := wordBinZ Z.add. -Definition wminusZ := wordBinZ Z.sub. -Definition wmultZ := wordBinZ Z.mul. -Definition wmultZsu sz (x y : word sz) := - ZToWord sz (Z.mul (wordToZ x) (Z.of_N (wordToN y))). -Definition wdivZ := wordBinZ Z.quot. -Definition wdivZsu sz (x y : word sz) := - ZToWord sz (Z.div (wordToZ x) (Z.of_N (wordToN y))). -Definition wremZ := wordBinZ Z.rem. -Definition wremZsu sz (x y : word sz) := - ZToWord sz (Z.modulo (wordToZ x) (Z.of_N (wordToN y))). - -(** * Comparison predicates and deciders *) - -Definition wlt sz (l r : word sz) : Prop := - N.lt (wordToN l) (wordToN r). -Definition wslt sz (l r : word sz) : Prop := - Z.lt (wordToZ l) (wordToZ r). - -Notation "w1 > w2" := (@wlt _ w2%word w1%word) : word_scope. -Notation "w1 >= w2" := (~(@wlt _ w1%word w2%word)) : word_scope. -Notation "w1 < w2" := (@wlt _ w1%word w2%word) : word_scope. -Notation "w1 <= w2" := (~(@wlt _ w2%word w1%word)) : word_scope. - -Notation "w1 '>s' w2" := (@wslt _ w2%word w1%word) (at level 70, w2 at next level) : word_scope. -Notation "w1 '>s=' w2" := (~(@wslt _ w1%word w2%word)) (at level 70, w2 at next level) : word_scope. -Notation "w1 ' WO~1 - | S sz' => (wpow2 sz')~0 - end. - -Notation "l ^<< r" := (@wlshift _ _ l%word r%word) (at level 35). -Notation "l ^>> r" := (@wrshift _ _ l%word r%word) (at level 35). - -(** * Setting an individual bit *) - -Definition wbit sz sz' (n : word sz') := natToWord sz (pow2 (wordToNat n)). - - -(*! Facts *) - -Hint Rewrite div2_double div2_S_double: div2. -Local Hint Resolve mod2_S_double mod2_double. - -Theorem eq_rect_word_offset : forall n n' offset w Heq, - eq_rect n (fun n => word (offset + n)) w n' Heq = - eq_rect (offset + n) (fun n => word n) w (offset + n') (eq_rect_word_offset_helper _ _ _ Heq). -Proof. - intros. - destruct Heq. - rewrite (UIP_dec eq_nat_dec (eq_rect_word_offset_helper _ _ offset eq_refl) eq_refl). - reflexivity. -Qed. - -Theorem eq_rect_word_mult : forall n n' scale w Heq, - eq_rect n (fun n => word (n * scale)) w n' Heq = - eq_rect (n * scale) (fun n => word n) w (n' * scale) (eq_rect_word_mult_helper _ _ _ Heq). -Proof. - intros. - destruct Heq. - rewrite (UIP_dec eq_nat_dec (eq_rect_word_mult_helper _ _ scale eq_refl) eq_refl). - reflexivity. -Qed. - -Theorem eq_rect_word_match : forall n n' (w : word n) (H : n = n'), - match H in (_ = N) return (word N) with - | eq_refl => w - end = eq_rect n (fun n => word n) w n' H. -Proof. - intros. - destruct H. - rewrite <- (eq_rect_eq_dec eq_nat_dec). - reflexivity. -Qed. - -Theorem whd_match : forall n n' (w : word (S n)) (Heq : S n = S n'), - whd w = whd (match Heq in (_ = N) return (word N) with - | eq_refl => w - end). -Proof. - intros. - rewrite eq_rect_word_match. - generalize dependent w. - remember Heq as Heq'. clear HeqHeq'. - generalize dependent Heq'. - replace (n') with (n) by omega. - intros. rewrite <- (eq_rect_eq_dec eq_nat_dec). reflexivity. -Qed. - -Theorem wtl_match : forall n n' (w : word (S n)) (Heq : S n = S n') (Heq' : n = n'), - (match Heq' in (_ = N) return (word N) with - | eq_refl => wtl w - end) = wtl (match Heq in (_ = N) return (word N) with - | eq_refl => w - end). -Proof. - intros. - repeat match goal with - | [ |- context[match ?pf with refl_equal => _ end] ] => generalize pf - end. - generalize dependent w; clear. - intros. - generalize Heq Heq'. - subst. - intros. - rewrite (UIP_dec eq_nat_dec Heq' (refl_equal _)). - rewrite (UIP_dec eq_nat_dec Heq0 (refl_equal _)). - reflexivity. -Qed. - -Theorem word0: forall (w : word 0), w = WO. -Proof. - firstorder. -Qed. - -Theorem wordToNat_wordToNat' : forall sz (w : word sz), - wordToNat w = wordToNat' w. -Proof. - induction w. auto. unfold wordToNat. simpl. rewrite mult_comm. reflexivity. -Qed. - -Theorem natToWord_wordToNat : forall sz w, natToWord sz (wordToNat w) = w. - induction w as [|b]; rewrite wordToNat_wordToNat'; intuition; f_equal; unfold natToWord, wordToNat'; fold natToWord; fold wordToNat'; - destruct b; f_equal; autorewrite with div2; intuition. -Qed. - -Theorem roundTrip_0 : forall sz, wordToNat (natToWord sz 0) = 0. - induction sz; simpl; intuition. -Qed. - -Hint Rewrite roundTrip_0 : wordToNat. - -Lemma wordToNat_natToWord' : forall sz w, exists k, wordToNat (natToWord sz w) + k * pow2 sz = w. - induction sz as [|sz IHsz]; simpl; intro w; intuition; repeat rewrite untimes2. - - exists w; intuition. - - case_eq (mod2 w); intro Hmw. - - specialize (IHsz (div2 w)); firstorder. - rewrite wordToNat_wordToNat' in *. - let x' := match goal with H : _ + ?x * _ = _ |- _ => x end in - rename x' into x. (* force non-auto-generated name *) - exists x; intuition. - rewrite mult_assoc. - rewrite (mult_comm x 2). - rewrite mult_comm. simpl mult at 1. - rewrite (plus_Sn_m (2 * wordToNat' (natToWord sz (div2 w)))). - rewrite <- mult_assoc. - rewrite <- mult_plus_distr_l. - rewrite H; clear H. - symmetry; apply div2_odd; auto. - - specialize (IHsz (div2 w)); firstorder. - let x' := match goal with H : _ + ?x * _ = _ |- _ => x end in - rename x' into x. (* force non-auto-generated name *) - exists x; intuition. - rewrite mult_assoc. - rewrite (mult_comm x 2). - rewrite <- mult_assoc. - rewrite mult_comm. - rewrite <- mult_plus_distr_l. - match goal with H : _ |- _ => rewrite H; clear H end. - symmetry; apply div2_even; auto. -Qed. - -Theorem wordToNat_natToWord: - forall sz w, exists k, wordToNat (natToWord sz w) = w - k * pow2 sz /\ (k * pow2 sz <= w)%nat. -Proof. - intros sz w; destruct (wordToNat_natToWord' sz w) as [k]; exists k; intuition. -Qed. - -Lemma wordToNat_natToWord_2: forall sz w : nat, - (w < pow2 sz)%nat -> wordToNat (natToWord sz w) = w. -Proof. - intros. - pose proof (wordToNat_natToWord sz w). - destruct H0; destruct H0. - rewrite H0 in *; clear H0. - destruct x; try omega. - exfalso; simpl in H1. - - pose proof (Lt.le_lt_trans _ _ _ H1 H). - pose proof (Plus.le_plus_l (pow2 sz) (x * pow2 sz)). - pose proof (Lt.le_lt_trans _ _ _ H2 H0). - omega. -Qed. - -Lemma natToWord_times2: forall sz x, - ((natToWord sz x)~0)%word = natToWord (S sz) (2 * x). -Proof. - intros. unfold natToWord. fold natToWord. f_equal. - - symmetry. apply mod2_double. - - rewrite div2_double. reflexivity. -Qed. - -Theorem WS_neq : forall b1 b2 sz (w1 w2 : word sz), - (b1 <> b2 \/ w1 <> w2) - -> WS b1 w1 <> WS b2 w2. - intros b1 b2 sz w1 w2 ? H0; intuition. - apply (f_equal (@whd _)) in H0; tauto. - apply (f_equal (@wtl _)) in H0; tauto. -Qed. - -Theorem weqb_true_iff : forall sz x y, - @weqb sz x y = true <-> x = y. -Proof. - induction x as [|b ? x IHx]; simpl; intros y. - { split; auto. } - { rewrite (shatter_word y) in *. simpl in *. - case_eq (eqb b (whd y)); intros H. - case_eq (weqb x (wtl y)); intros H0. - split; auto; intros. rewrite eqb_true_iff in H. f_equal; eauto. eapply IHx; eauto. - split; intros H1; try congruence. inversion H1; clear H1; subst. - eapply inj_pair2_eq_dec in H4. eapply IHx in H4. congruence. - eapply Peano_dec.eq_nat_dec. - split; intros; try congruence. - inversion H0. apply eqb_false_iff in H. congruence. } -Qed. - -Ltac shatterer := simpl; intuition; - match goal with - | [ w : _ |- _ ] => rewrite (shatter_word w); simpl - end; f_equal; auto. - -Theorem combine_split : forall sz1 sz2 (w : word (sz1 + sz2)), - combine (split1 sz1 sz2 w) (split2 sz1 sz2 w) = w. - induction sz1; shatterer. -Qed. - -Theorem split1_combine : forall sz1 sz2 (w : word sz1) (z : word sz2), - split1 sz1 sz2 (combine w z) = w. - induction sz1; shatterer. -Qed. - -Theorem split2_combine : forall sz1 sz2 (w : word sz1) (z : word sz2), - split2 sz1 sz2 (combine w z) = z. - induction sz1; shatterer. -Qed. - -Hint Rewrite combine_split. -Hint Rewrite split1_combine. -Hint Rewrite split2_combine. - -Theorem combine_assoc : forall n1 (w1 : word n1) n2 n3 (w2 : word n2) (w3 : word n3) Heq, - combine (combine w1 w2) w3 - = match Heq in _ = N return word N with - | refl_equal => combine w1 (combine w2 w3) - end. - induction w1 as [|?? w1 IHw1]; simpl; intros n2 n3 w2 w3 Heq; intuition. - - rewrite (UIP_dec eq_nat_dec Heq (refl_equal _)); reflexivity. - - rewrite (IHw1 _ _ _ _ (plus_assoc _ _ _)); clear IHw1. - repeat match goal with - | [ |- context[match ?pf with refl_equal => _ end] ] => generalize pf - end. - generalize dependent (combine w1 (combine w2 w3)). - rewrite plus_assoc; intros w Heq0 e. - rewrite (UIP_dec eq_nat_dec e (refl_equal _)). - rewrite (UIP_dec eq_nat_dec Heq0 (refl_equal _)). - reflexivity. -Qed. - -Theorem split1_iter : forall n1 n2 n3 Heq w, - split1 n1 n2 (split1 (n1 + n2) n3 w) - = split1 n1 (n2 + n3) (match Heq in _ = N return word N with - | refl_equal => w - end). -Proof. - induction n1; simpl; intuition. - - f_equal. - apply whd_match. - assert (n1 + n2 + n3 = n1 + (n2 + n3)) as Heq' by omega. - rewrite IHn1 with (Heq:=Heq'). - f_equal. - apply wtl_match. -Qed. - -Theorem split2_iter : forall n1 n2 n3 Heq w, - split2 n2 n3 (split2 n1 (n2 + n3) w) - = split2 (n1 + n2) n3 (match Heq in _ = N return word N with - | refl_equal => w - end). - induction n1 as [|n1 IHn1]; simpl; intros n2 n3 Heq w; intuition. - - rewrite (UIP_dec eq_nat_dec Heq (refl_equal _)); reflexivity. - - rewrite (IHn1 _ _ (plus_assoc _ _ _)). - f_equal. - apply wtl_match. -Qed. - -Theorem split1_split2 : forall n1 n2 n3 Heq w, - split1 n2 n3 (split2 n1 (n2 + n3) w) = - split2 n1 n2 (split1 (n1 + n2) n3 (match Heq in _ = N return word N with - | refl_equal => w - end)). -Proof. - induction n1; simpl; intros. - - rewrite (UIP_dec eq_nat_dec Heq (refl_equal _)). - reflexivity. - - rewrite (shatter_word w). - simpl. - assert (n1 + (n2 + n3) = n1 + n2 + n3) as Heq' by omega. - rewrite <- wtl_match with (Heq':=Heq'). - rewrite <- IHn1. - f_equal. -Qed. - -Theorem split2_split1 : forall n1 n2 n3 Heq w, - split2 n1 n2 (split1 (n1+n2) n3 w) = - split1 n2 n3 (split2 n1 (n2+n3) (match Heq in _ = N return word N with - | refl_equal => w - end)). -Proof. - induction n1; simpl; intros. - - rewrite (UIP_dec eq_nat_dec Heq (refl_equal _)). - reflexivity. - - rewrite (shatter_word w). - simpl. - assert (n1 + n2 + n3 = n1 + (n2 + n3)) as Heq' by omega. - rewrite <- wtl_match with (Heq':=Heq'). - rewrite <- IHn1. - f_equal. -Qed. - -Theorem combine_0_n : forall sz2 (w: word 0) (v: word sz2), - combine w v = v. -Proof. - intros. - replace w with WO. - auto. - rewrite word0; auto. -Qed. - -Lemma WS_eq_rect : forall b n (w: word n) n' H H', - eq_rect _ word (@WS b n w) _ H = @WS b n' (eq_rect _ word w _ H'). -Proof. - destruct n; intros; subst; - eq_rect_simpl; auto. -Qed. - -Theorem combine_eq_rect2 : forall sz n n' - (H: n = n') H' - (a: word sz) (b: word n), - combine a b = - eq_rect _ word (combine a (eq_rect _ word b _ H)) _ H'. -Proof. - induction a; simpl; intros. - eq_rect_simpl; auto. - erewrite WS_eq_rect. - erewrite IHa. - auto. - - Grab Existential Variables. - omega. -Qed. - -Theorem combine_n_0 : forall sz1 (w : word sz1) (v : word 0), - combine w v = eq_rect _ word w _ (plus_n_O sz1). -Proof. - induction w; intros. - - replace v with WO; auto. - - simpl; rewrite IHw. - erewrite WS_eq_rect. - reflexivity. -Qed. - -Lemma whd_eq_rect : forall n w Heq, - whd (eq_rect (S n) word w (S (n + 0)) Heq) = - whd w. -Proof. - intros. - generalize Heq. - replace (n + 0) with n by omega. - intros. - f_equal. - eq_rect_simpl. - reflexivity. -Qed. - -Lemma wtl_eq_rect : forall n w Heq Heq', - wtl (eq_rect (S n) word w (S (n + 0)) Heq) = - eq_rect n word (wtl w) (n + 0) Heq'. -Proof. - intros. - generalize dependent Heq. - rewrite <- Heq'; simpl; intros. - rewrite <- (eq_rect_eq_dec eq_nat_dec). - reflexivity. -Qed. - -Lemma whd_eq_rect_mul : forall n w Heq, - whd (eq_rect (S n) word w (S (n * 1)) Heq) = - whd w. -Proof. - intros. - generalize Heq. - replace (n * 1) with n by auto. - intros. - eq_rect_simpl. - reflexivity. -Qed. - -Lemma wtl_eq_rect_mul : forall n w b Heq Heq', - wtl (eq_rect (S n) word (WS b w) (S (n * 1)) Heq) = - eq_rect _ word w _ Heq'. -Proof. - intros. - generalize Heq. - rewrite <- Heq'. - intros. eq_rect_simpl. - reflexivity. -Qed. - -Theorem split1_0 : forall n w Heq, - split1 n 0 (eq_rect _ word w _ Heq) = w. -Proof. - intros. - induction n; intros. - shatterer. - simpl. - erewrite wtl_eq_rect. - rewrite IHn. - rewrite whd_eq_rect. - simpl. - shatterer. - - Grab Existential Variables. - omega. -Qed. - -Theorem split2_0 : forall n w Heq, - split2 0 n (eq_rect _ word w _ Heq) = w. -Proof. - intros. - simpl. - eq_rect_simpl. - reflexivity. -Qed. - -Theorem combine_end : forall n1 n2 n3 Heq w, - combine (split1 n2 n3 (split2 n1 (n2 + n3) w)) - (split2 (n1 + n2) n3 (match Heq in _ = N return word N with - | refl_equal => w - end)) - = split2 n1 (n2 + n3) w. - induction n1 as [|n1 IHn1]; simpl; intros n2 n3 Heq w. - - rewrite (UIP_dec eq_nat_dec Heq (refl_equal _)). - apply combine_split. - - rewrite (shatter_word w) in *. - simpl. - eapply trans_eq; [ | apply IHn1 with (Heq := plus_assoc _ _ _) ]; clear IHn1. - repeat f_equal. - repeat match goal with - | [ |- context[match ?pf with refl_equal => _ end] ] => generalize pf - end. - simpl. - generalize dependent w. - rewrite plus_assoc. - intros. - rewrite (UIP_dec eq_nat_dec e (refl_equal _)). - rewrite (UIP_dec eq_nat_dec Heq0 (refl_equal _)). - reflexivity. -Qed. - -Theorem eq_rect_combine : forall n1 n2 n2' (w1 : word n1) (w2 : word n2') Heq, - eq_rect (n1 + n2') (fun n => word n) - (combine w1 w2) (n1 + n2) Heq = - combine w1 (eq_rect n2' (fun n => word n) w2 n2 (plus_reg_l _ _ _ Heq)). -Proof. - intros. - generalize (plus_reg_l n2' n2 n1 Heq); intros. - generalize dependent Heq. - generalize dependent w2. - rewrite e; intros. - repeat rewrite <- (eq_rect_eq_dec eq_nat_dec). - reflexivity. -Qed. - -Lemma eq_rect_combine_assoc' : forall a b c H wa wb wc, - eq_rect (a + (b + c)) word (combine wa (combine wb wc)) _ H = combine (combine wa wb) wc. -Proof. - intros. - erewrite combine_assoc, eq_rect_word_match. - reflexivity. -Qed. - -Lemma eq_rect_split2_helper : forall a b c, - a = b -> c + a = c + b. -Proof. - intros; omega. -Qed. - -Theorem eq_rect_split2 : forall n1 n2 n2' (w : word (n1 + n2')) Heq, - eq_rect n2' (fun n => word n) - (split2 n1 n2' w) n2 Heq = - split2 n1 n2 (eq_rect (n1+n2') (fun n => word n) w (n1+n2) (eq_rect_split2_helper _ Heq)). -Proof. - intros. - generalize (eq_rect_split2_helper n1 Heq); intros. - generalize dependent Heq. - generalize dependent w. - assert (n2' = n2) as H' by omega. - generalize dependent e. - rewrite H'; intros. - repeat rewrite <- (eq_rect_eq_dec eq_nat_dec). - reflexivity. -Qed. - -Theorem eq_rect_split2_eq2 : forall n1 n2 n2' (w : word (n1 + n2)) Heq Heq2, - eq_rect n2 (fun n => word n) - (split2 n1 n2 w) n2' Heq = - split2 n1 n2' (eq_rect (n1+n2) (fun n => word n) w (n1+n2') Heq2). -Proof. - intros. - assert (H' := Heq). - generalize dependent w. - generalize dependent Heq. - generalize dependent Heq2. - rewrite H'; intros. - repeat rewrite <- (eq_rect_eq_dec eq_nat_dec). - reflexivity. -Qed. - -Theorem eq_rect_split2_eq1 : forall n1 n1' n2 (w: word (n1 + n2)) Heq, - split2 n1 n2 w = split2 n1' n2 - (eq_rect (n1 + n2) (fun y : nat => word y) w - (n1' + n2) Heq). -Proof. - intros. - assert (n1 = n1') as H' by omega. - generalize dependent w. - generalize dependent Heq. - rewrite H'; intros. - rewrite <- (eq_rect_eq_dec eq_nat_dec). - reflexivity. -Qed. - -Theorem combine_split_eq_rect2 : forall n1 n2 n2' (w : word (n1 + n2)) Heq, - combine (split1 n1 n2 w) - (eq_rect n2 (fun n => word n) (split2 n1 n2 w) - n2' Heq) = - eq_rect (n1 + n2) (fun n => word n) w - (n1 + n2') (eq_rect_split2_helper _ Heq). -Proof. - intros. - assert (n2 = n2') by omega. - generalize dependent Heq. - generalize dependent w. - rewrite <- H; intros. - repeat rewrite <- (eq_rect_eq_dec eq_nat_dec). - apply combine_split. -Qed. - -Lemma eq_rect_split1_helper : forall a b c, - a = b -> a + c = b + c. -Proof. - intros; omega. -Qed. - -Lemma eq_rect_split1_eq2_helper : forall a b c, - a = b -> c + a = c + b. -Proof. - intros; omega. -Qed. - -Theorem eq_rect_split1 : forall n1 n1' n2 (w : word (n1' + n2)) Heq, - eq_rect n1' (fun n => word n) - (split1 n1' n2 w) n1 Heq = - split1 n1 n2 (eq_rect (n1'+n2) (fun n => word n) w (n1+n2) (eq_rect_split1_helper _ Heq)). -Proof. - intros. - generalize (eq_rect_split1_helper n2 Heq); intros. - generalize dependent Heq. - generalize dependent w. - assert (n1' = n1) as H' by omega. - generalize dependent e. - rewrite H'; intros. - repeat rewrite <- (eq_rect_eq_dec eq_nat_dec). - reflexivity. -Qed. - -Theorem eq_rect_split1_eq1 : forall n1 n1' n2 (w : word (n1 + n2)) Heq Heq1, - eq_rect n1 (fun n => word n) - (split1 n1 n2 w) n1' Heq = - split1 n1' n2 (eq_rect (n1+n2) (fun n => word n) w (n1'+n2) Heq1). -Proof. - intros. - generalize dependent w. - generalize dependent Heq1. - rewrite Heq; intros. - repeat rewrite <- (eq_rect_eq_dec eq_nat_dec). - reflexivity. -Qed. - -Lemma split1_eq_rect_eq1_helper : forall a b c, b = a -> a + c = b + c. -Proof. intros. subst. reflexivity. Qed. - -Theorem split1_eq_rect_eq1 : forall a a' b H w, - split1 a b w = eq_rect _ word (split1 a' b - (eq_rect _ word w _ (split1_eq_rect_eq1_helper b H))) _ H. -Proof. - intros a a' b H. - subst a'; intros; eq_rect_simpl; auto. -Qed. - -Theorem eq_rect_split1_eq2 : forall n1 n2 n2' (w: word (n1 + n2)) Heq, - split1 n1 n2 w = split1 n1 n2' - (eq_rect (n1 + n2) (fun y : nat => word y) w - (n1 + n2') Heq). -Proof. - intros. - assert (n2 = n2') as H' by omega. - generalize dependent w. - generalize dependent Heq. - rewrite H'; intros. - rewrite <- (eq_rect_eq_dec eq_nat_dec). - reflexivity. -Qed. - -Fact eq_rect_combine_dist_helper1 : forall a b c d, b * c = d -> (a + b) * c = a * c + d. -Proof. intros; subst. apply Nat.mul_add_distr_r. Qed. - -Fact eq_rect_combine_dist_helper2 : forall a b c d, b * c = d -> a * c + d = (a + b) * c. -Proof. intros; subst. symmetry; apply Nat.mul_add_distr_r. Qed. - -Theorem eq_rect_combine_dist : forall a b c d (w : word ((a + b) * c)) (H : b * c = d), - b * c = d -> - let H1 := (eq_rect_combine_dist_helper1 a b c H) in - let H2 := (eq_rect_combine_dist_helper2 a b c H) in - let w' := eq_rec ((a + b) * c) word w _ H1 in - w = eq_rec _ word (combine (split1 (a * c) d w') (split2 (a * c) d w')) _ H2. -Proof. - intros. - subst d. - rewrite combine_split. - eq_rect_simpl. - generalize dependent w. - generalize dependent H2. - rewrite H1. - intros. - eq_rect_simpl; auto. -Qed. - -Lemma wzero_dist : forall a b c H, - wzero ((a + b) * c) = eq_rect _ word (wzero (a * c + b * c)) _ H. -Proof. - intros a b c H. - rewrite H. - reflexivity. -Qed. - -Lemma wzero_rev : forall (a b : nat) H, - wzero (a + b) = eq_rect _ word (wzero (b + a)) _ H. -Proof. intros a b H. rewrite H. auto. Qed. - -Lemma split1_zero : forall sz1 sz2, split1 sz1 sz2 (natToWord _ O) = natToWord _ O. -Proof. - induction sz1; auto; simpl; intros. - f_equal. eauto. -Qed. - -Lemma split2_zero : forall sz1 sz2, split2 sz1 sz2 (natToWord _ O) = natToWord _ O. -Proof. - induction sz1; auto. -Qed. - -Theorem combine_inj : forall sz1 sz2 a b c d, - @combine sz1 a sz2 b = @combine sz1 c sz2 d -> a = c /\ b = d. -Proof. - induction sz1; simpl; intros. - - rewrite (word0 a) in *. - rewrite (word0 c) in *. - simpl in *. - intuition. - - rewrite (shatter_word a) in *. - rewrite (shatter_word c) in *. - simpl in *. - inversion H. - apply (inj_pair2_eq_dec _ eq_nat_dec) in H2. - destruct (IHsz1 _ _ _ _ _ H2). - intuition. - f_equal; auto. -Qed. - -Theorem combine_wzero : forall sz1 sz2, combine (wzero sz1) (wzero sz2) = wzero (sz1 + sz2). -Proof. - induction sz1; auto. - unfold wzero in *. - intros; simpl; f_equal; auto. -Qed. - -Theorem combine_wones : forall sz1 sz2, combine (wones sz1) (wones sz2) = wones (sz1 + sz2). -Proof. - induction sz1; auto. - intros; simpl; f_equal; auto. -Qed. - -Theorem wordToN_nat : forall sz (w : word sz), wordToN w = N_of_nat (wordToNat w). -Proof. - induction w; intuition. - destruct b; unfold wordToN, wordToNat; fold wordToN; fold wordToNat. - - rewrite N_of_S. - rewrite N_of_mult. - rewrite <- IHw. - rewrite Nmult_comm. - reflexivity. - - rewrite N_of_mult. - rewrite <- IHw. - rewrite Nmult_comm. - reflexivity. -Qed. - -Lemma wordToN_to_nat sz: forall (w: word sz), BinNat.N.to_nat (wordToN w) = wordToNat w. -Proof. - intros. - rewrite wordToN_nat. - rewrite Nnat.Nat2N.id. - reflexivity. -Qed. - -Local Hint Extern 1 (@eq nat _ _) => omega. - -Theorem mod2_S : forall n k, - 2 * k = S n - -> mod2 n = true. - induction n as [n] using strong; intros. - destruct n; simpl in *. - elimtype False; omega. - destruct n; simpl in *; auto. - destruct k as [|k]; simpl in *. - discriminate. - apply H with k; auto. -Qed. - -Theorem wzero'_def : forall sz, wzero' sz = wzero sz. - unfold wzero; induction sz; simpl; intuition. - congruence. -Qed. - -Theorem posToWord_nat : forall p sz, posToWord sz p = natToWord sz (nat_of_P p). - induction p as [ p IHp | p IHp | ]; destruct sz; simpl; intuition; f_equal; try rewrite wzero'_def in *. - - rewrite ZL6. - destruct (ZL4 p) as [x Heq]; rewrite Heq; simpl. - replace (x + S x) with (S (2 * x)) by omega. - symmetry; apply mod2_S_double. - - rewrite IHp. - rewrite ZL6. - destruct (nat_of_P p); simpl; intuition. - replace (n + S n) with (S (2 * n)) by omega. - rewrite div2_S_double; auto. - - unfold nat_of_P; simpl. - rewrite ZL6. - replace (nat_of_P p + nat_of_P p) with (2 * nat_of_P p) by omega. - symmetry; apply mod2_double. - - rewrite IHp. - unfold nat_of_P; simpl. - rewrite ZL6. - replace (nat_of_P p + nat_of_P p) with (2 * nat_of_P p) by omega. - rewrite div2_double. - auto. - auto. -Qed. - -Lemma posToWord_sz0: forall p, posToWord 0 p = $0. -Proof. - intros. unfold posToWord. destruct p; reflexivity. -Qed. - -Theorem NToWord_nat : forall sz n, NToWord sz n = natToWord sz (nat_of_N n). - destruct n; simpl; intuition; try rewrite wzero'_def in *. - auto. - apply posToWord_nat. -Qed. - -Theorem wplus_alt : forall sz (x y : word sz), wplus x y = wplusN x y. - unfold wplusN, wplus, wordBinN, wordBin; intros. - - repeat rewrite wordToN_nat; repeat rewrite NToWord_nat. - rewrite nat_of_Nplus. - repeat rewrite nat_of_N_of_nat. - reflexivity. -Qed. - -Theorem wmult_alt : forall sz (x y : word sz), wmult x y = wmultN x y. - unfold wmultN, wmult, wordBinN, wordBin; intros. - - repeat rewrite wordToN_nat; repeat rewrite NToWord_nat. - rewrite nat_of_Nmult. - repeat rewrite nat_of_N_of_nat. - reflexivity. -Qed. - -Theorem wneg_alt : forall sz (x : word sz), wneg x = wnegN x. - unfold wnegN, wneg; intros. - repeat rewrite wordToN_nat; repeat rewrite NToWord_nat. - rewrite nat_of_Nminus. - do 2 f_equal. - apply Npow2_nat. - apply nat_of_N_of_nat. -Qed. - -Theorem wminus_Alt : forall sz (x y : word sz), wminus x y = wminusN x y. - intros; unfold wminusN, wminus; rewrite wneg_alt; apply wplus_alt. -Qed. - -Theorem wplus_unit : forall sz (x : word sz), natToWord sz 0 ^+ x = x. - intros; rewrite wplus_alt; unfold wplusN, wordBinN; intros. - rewrite roundTrip_0; apply natToWord_wordToNat. -Qed. - -Theorem wplus_comm : forall sz (x y : word sz), x ^+ y = y ^+ x. - intros; repeat rewrite wplus_alt; unfold wplusN, wordBinN; f_equal; auto. -Qed. - -Theorem drop_sub : - forall sz n k, - (k * pow2 sz <= n)%nat -> - natToWord sz (n - k * pow2 sz) = natToWord sz n. -Proof. - induction sz as [|sz IHsz]; simpl; intros n k *; intuition; repeat rewrite untimes2 in *; f_equal. - - rewrite mult_assoc. - rewrite (mult_comm k). - rewrite <- mult_assoc. - apply drop_mod2. - rewrite mult_assoc. - rewrite (mult_comm 2). - rewrite <- mult_assoc. - auto. - - rewrite <- (IHsz (div2 n) k). - rewrite mult_assoc. - rewrite (mult_comm k). - rewrite <- mult_assoc. - rewrite div2_minus_2. - reflexivity. - rewrite mult_assoc. - rewrite (mult_comm 2). - rewrite <- mult_assoc. - auto. - - apply div2_bound. - rewrite mult_assoc. - rewrite (mult_comm 2). - rewrite <- mult_assoc. - auto. -Qed. - -Local Hint Extern 1 (_ <= _)%nat => omega. - -Theorem wplus_assoc : forall sz (x y z : word sz), x ^+ (y ^+ z) = x ^+ y ^+ z. - intros sz x y z *; repeat rewrite wplus_alt; unfold wplusN, wordBinN; intros. - - repeat match goal with - | [ |- context[wordToNat (natToWord ?sz ?w)] ] => - let Heq := fresh "Heq" in - destruct (wordToNat_natToWord sz w) as [? [Heq ?]]; rewrite Heq - end. - - match goal with - | [ |- context[wordToNat ?x + wordToNat ?y - ?x1 * pow2 ?sz + wordToNat ?z] ] - => replace (wordToNat x + wordToNat y - x1 * pow2 sz + wordToNat z) - with (wordToNat x + wordToNat y + wordToNat z - x1 * pow2 sz) by auto - end. - match goal with - | [ |- context[wordToNat ?x + (wordToNat ?y + wordToNat ?z - ?x0 * pow2 ?sz)] ] - => replace (wordToNat x + (wordToNat y + wordToNat z - x0 * pow2 sz)) - with (wordToNat x + wordToNat y + wordToNat z - x0 * pow2 sz) by auto - end. - repeat rewrite drop_sub; auto. -Qed. - -Theorem roundTrip_1 : forall sz, wordToNat (natToWord (S sz) 1) = 1. - induction sz; simpl in *; intuition. -Qed. - -Theorem mod2_WS : forall sz (x : word sz) b, mod2 (wordToNat (WS b x)) = b. - intros sz x b. rewrite wordToNat_wordToNat'. - destruct b; simpl. - - rewrite untimes2. - case_eq (2 * wordToNat x); intuition. - eapply mod2_S; eauto. - rewrite <- (mod2_double (wordToNat x)); f_equal; omega. -Qed. - -Theorem div2_WS : forall sz (x : word sz) b, div2 (wordToNat (WS b x)) = wordToNat x. - destruct b; rewrite wordToNat_wordToNat'; unfold wordToNat'; fold wordToNat'. - apply div2_S_double. - apply div2_double. -Qed. - -Theorem wmult_unit : forall sz (x : word sz), natToWord sz 1 ^* x = x. - intros sz x; rewrite wmult_alt; unfold wmultN, wordBinN; intros. - destruct sz; simpl. - rewrite (shatter_word x); reflexivity. - rewrite roundTrip_0; simpl. - rewrite plus_0_r. - rewrite (shatter_word x). - f_equal. - - apply mod2_WS. - - rewrite div2_WS. - apply natToWord_wordToNat. -Qed. - -Theorem wmult_comm : forall sz (x y : word sz), x ^* y = y ^* x. - intros; repeat rewrite wmult_alt; unfold wmultN, wordBinN; auto with arith. -Qed. - -Theorem wmult_unit_r : forall sz (x : word sz), x ^* natToWord sz 1 = x. -Proof. - intros. - rewrite wmult_comm. - apply wmult_unit. -Qed. - -Lemma wmult_neut_l: forall (sz : nat) (x : word sz), $0 ^* x = $0. -Proof. - intros. unfold wmult. unfold wordBin. do 2 rewrite wordToN_nat. - rewrite <- Nnat.Nat2N.inj_mul. rewrite roundTrip_0. - rewrite Nat.mul_0_l. simpl. rewrite wzero'_def. reflexivity. -Qed. - -Lemma wmult_neut_r: forall (sz : nat) (x : word sz), x ^* $0 = $0. -Proof. - intros. unfold wmult. unfold wordBin. do 2 rewrite wordToN_nat. - rewrite <- Nnat.Nat2N.inj_mul. rewrite roundTrip_0. - rewrite Nat.mul_0_r. simpl. rewrite wzero'_def. reflexivity. -Qed. - -Theorem wmult_assoc : forall sz (x y z : word sz), x ^* (y ^* z) = x ^* y ^* z. - intros sz x y z; repeat rewrite wmult_alt; unfold wmultN, wordBinN; intros. - - repeat match goal with - | [ |- context[wordToNat (natToWord ?sz ?w)] ] => - let Heq := fresh "Heq" in - destruct (wordToNat_natToWord sz w) as [? [Heq ?]]; rewrite Heq - end. - - rewrite mult_minus_distr_l. - rewrite mult_minus_distr_r. - match goal with - | [ |- natToWord _ (_ - _ * (?x0' * _)) = natToWord _ (_ - ?x1' * _ * _) ] - => rename x0' into x0, x1' into x1 (* force the names to not be autogenerated *) - end. - rewrite (mult_assoc (wordToNat x) x0). - rewrite <- (mult_assoc x1). - rewrite (mult_comm (pow2 sz)). - rewrite (mult_assoc x1). - repeat rewrite drop_sub; auto with arith. - rewrite (mult_comm x1). - rewrite <- (mult_assoc (wordToNat x)). - rewrite (mult_comm (wordToNat y)). - rewrite mult_assoc. - rewrite (mult_comm (wordToNat x)). - repeat rewrite <- mult_assoc. - auto with arith. - repeat rewrite <- mult_assoc. - auto with arith. -Qed. - -Theorem wmult_plus_distr : forall sz (x y z : word sz), (x ^+ y) ^* z = (x ^* z) ^+ (y ^* z). - intros sz x y z; repeat rewrite wmult_alt; repeat rewrite wplus_alt; unfold wmultN, wplusN, wordBinN; intros. - - repeat match goal with - | [ |- context[wordToNat (natToWord ?sz ?w)] ] => - let Heq := fresh "Heq" in - destruct (wordToNat_natToWord sz w) as [? [Heq ?]]; rewrite Heq - end. - - rewrite mult_minus_distr_r. - match goal with - | [ |- natToWord _ (_ - ?x0' * _ * _) = natToWord _ (_ - ?x1' * _ + (_ - ?x2' * _)) ] - => rename x0' into x0, x1' into x1, x2' into x2 (* force the names to not be autogenerated *) - end. - rewrite <- (mult_assoc x0). - rewrite (mult_comm (pow2 sz)). - rewrite (mult_assoc x0). - - replace (wordToNat x * wordToNat z - x1 * pow2 sz + - (wordToNat y * wordToNat z - x2 * pow2 sz)) - with (wordToNat x * wordToNat z + wordToNat y * wordToNat z - x1 * pow2 sz - x2 * pow2 sz). - repeat rewrite drop_sub; auto with arith. - rewrite (mult_comm x0). - rewrite (mult_comm (wordToNat x + wordToNat y)). - rewrite <- (mult_assoc (wordToNat z)). - auto with arith. - generalize dependent (wordToNat x * wordToNat z). - generalize dependent (wordToNat y * wordToNat z). - intros. - omega. -Qed. - -Theorem wminus_def : forall sz (x y : word sz), x ^- y = x ^+ ^~ y. - reflexivity. -Qed. - -Theorem wordToNat_bound : forall sz (w : word sz), (wordToNat w < pow2 sz)%nat. - induction w as [|b]; simpl; intuition. - destruct b; simpl; omega. -Qed. - -Theorem natToWord_pow2 : forall sz, natToWord sz (pow2 sz) = natToWord sz 0. - induction sz as [|sz]; simpl; intuition. - - generalize (div2_double (pow2 sz)); simpl; intro Hr; rewrite Hr; clear Hr. - f_equal. - generalize (mod2_double (pow2 sz)); auto. - auto. -Qed. - -Theorem wminus_inv : forall sz (x : word sz), x ^+ ^~ x = wzero sz. - intros sz x; rewrite wneg_alt; rewrite wplus_alt; unfold wnegN, wplusN, wzero, wordBinN; intros. - - repeat match goal with - | [ |- context[wordToNat (natToWord ?sz ?w)] ] => - let Heq := fresh "Heq" in - destruct (wordToNat_natToWord sz w) as [? [Heq ?]]; rewrite Heq - end. - - match goal with - | [ |- context[wordToNat ?x + (pow2 ?sz - wordToNat ?x - ?x0 * pow2 ?sz)] ] - => replace (wordToNat x + (pow2 sz - wordToNat x - x0 * pow2 sz)) - with (pow2 sz - x0 * pow2 sz) - end. - rewrite drop_sub; auto with arith. - apply natToWord_pow2. - generalize (wordToNat_bound x). - omega. -Qed. - -Definition wring (sz : nat) : ring_theory (wzero sz) (wone sz) (@wplus sz) (@wmult sz) (@wminus sz) (@wneg sz) (@eq _) := - mk_rt _ _ _ _ _ _ _ - (@wplus_unit _) (@wplus_comm _) (@wplus_assoc _) - (@wmult_unit _) (@wmult_comm _) (@wmult_assoc _) - (@wmult_plus_distr _) (@wminus_def _) (@wminus_inv _). - -Theorem weqb_sound : forall sz (x y : word sz), weqb x y = true -> x = y. -Proof. - eapply weqb_true_iff. -Qed. - -Arguments weqb_sound : clear implicits. - -Lemma weqb_eq: forall sz (a b: word sz), a = b -> weqb a b = true. -Proof. intros. rewrite weqb_true_iff. assumption. Qed. - -Lemma weqb_ne: forall sz (a b: word sz), a <> b -> weqb a b = false. -Proof. - intros. destruct (weqb a b) eqn: E. - - rewrite weqb_true_iff in E. contradiction. - - reflexivity. -Qed. - -Ltac is_nat_cst n := - match eval hnf in n with - | O => constr:(true) - | S ?n' => is_nat_cst n' - | _ => constr:(false) - end. - -Ltac isWcst w := - match eval hnf in w with - | WO => constr:(true) - | WS ?b ?w' => - match eval hnf in b with - | true => isWcst w' - | false => isWcst w' - | _ => constr:(false) - end - | natToWord _ ?n => is_nat_cst n - | _ => constr:(false) - end. - -Ltac wcst w := - let b := isWcst w in - match b with - | true => w - | _ => constr:(NotConstant) - end. - -(* Here's how you can add a ring for a specific bit-width. - There doesn't seem to be a polymorphic method, so this code really does need to be copied. *) - -(* -Definition wring8 := wring 8. -Add Ring wring8 : wring8 (decidable (weqb_sound 8), constants [wcst]). -*) - -Ltac noptac x := idtac. - -Ltac PackWring sz F := - let RNG := (fun proj => proj - inv_morph_nothing inv_morph_nothing noptac noptac - (word sz) (@eq (word sz)) (wzero sz) (wone sz) - (@wplus sz) (@wmult sz) (@wminus sz) (@wneg sz) - (BinNums.Z) (BinNums.N) (id_phi_N) - (pow_N (wone sz) (@wmult sz)) - (ring_correct (@Eqsth (word sz)) - (Eq_ext _ _ _) - (Rth_ARth (@Eqsth (word sz)) (Eq_ext _ _ _) (wring sz)) - (gen_phiZ_morph (@Eqsth (word sz)) (Eq_ext _ _ _) (wring sz)) - (pow_N_th _ _ (@Eqsth (word sz))) - (triv_div_th (@Eqsth (word sz)) - (Eq_ext _ _ _) - (Rth_ARth (@Eqsth (word sz)) (Eq_ext _ _ _) (wring sz)) - (gen_phiZ_morph (@Eqsth (word sz)) (Eq_ext _ _ _) (wring sz))) - ) - tt) in - F RNG (@nil (word sz)) (@nil (word sz)). - -Ltac ring_sz sz := PackWring sz Ring_gen. - -Fact bitwp_wtl : forall sz (w w' : word (S sz)) op, bitwp op (wtl w) (wtl w') = wtl (bitwp op w w'). -Proof. - intros. - rewrite (shatter_word w), (shatter_word w'). - auto. -Qed. - -Lemma split1_bitwp_dist : forall sz1 sz2 w w' op, - split1 sz1 sz2 (bitwp op w w') = bitwp op (split1 sz1 sz2 w) (split1 sz1 sz2 w'). -Proof. - induction sz1; intros; auto. - simpl. - f_equal. - rewrite (shatter_word w), (shatter_word w'); auto. - rewrite <- IHsz1, bitwp_wtl. - reflexivity. -Qed. - -Lemma split2_bitwp_dist : forall sz1 sz2 w w' op, - split2 sz1 sz2 (bitwp op w w') = bitwp op (split2 sz1 sz2 w) (split2 sz1 sz2 w'). -Proof. - induction sz1; intros; auto. - simpl; rewrite <- IHsz1, bitwp_wtl. - reflexivity. -Qed. - -Lemma combine_bitwp : forall sz1 sz2 (wa wa' : word sz1) (wb wb' : word sz2) op, - combine (bitwp op wa wa') (bitwp op wb wb') = bitwp op (combine wa wb) (combine wa' wb'). -Proof. - induction sz1; intros; rewrite (shatter_word wa), (shatter_word wa'); simpl; f_equal; auto. -Qed. - -Lemma eq_rect_bitwp : forall a b Heq f w1 w2, - bitwp f w1 w2 = eq_rect a word ( - bitwp f (eq_rect b word w1 a Heq) (eq_rect b word w2 a Heq)) b (eq_sym Heq). -Proof. - intros a b H; subst a. - intros; eq_rect_simpl; reflexivity. -Qed. - -Fact eq_rect_bitwp' : forall a b Heq f w1 w2, - eq_rect b word (bitwp f w1 w2) a Heq = bitwp f (eq_rect b word w1 a Heq) (eq_rect b word w2 a Heq). -Proof. - intros a b H1; subst a. - intros; eq_rect_simpl; reflexivity. -Qed. - -Fact eq_rect_bitwp_1 : forall a b Heq f w1 w2, - bitwp f (eq_rect a word w1 b Heq) w2 = eq_rect a word (bitwp f w1 (eq_rect b word w2 a (eq_sym Heq))) b Heq. -Proof. - intros a b H. - subst a; intros; eq_rect_simpl; auto. -Qed. - -Theorem wnot_wnot'_equiv : forall sz (w : word sz), wnot w = wnot' w. -Proof. - unfold wnot'. - induction sz; intros w; shatterer. -Qed. - -Theorem wnot_split1 : forall sz1 sz2 w, wnot (split1 sz1 sz2 w) = split1 sz1 sz2 (wnot w). -Proof. - intros. - repeat rewrite wnot_wnot'_equiv. - unfold wnot'. - erewrite <- split1_combine with (w := wones _). - rewrite <- split1_bitwp_dist, combine_wones. - reflexivity. -Qed. - -Theorem wnot_split2 : forall sz1 sz2 w, wnot (split2 sz1 sz2 w) = split2 sz1 sz2 (wnot w). -Proof. - intros. - repeat rewrite wnot_wnot'_equiv. - unfold wnot'. - erewrite <- split2_combine with (z := wones _). - rewrite <- split2_bitwp_dist, combine_wones. - reflexivity. -Qed. - -Theorem wnot_combine : forall sz1 sz2 (w1 : word sz1) (w2 : word sz2), - wnot (combine w1 w2) = combine (wnot w1) (wnot w2). -Proof. - intros. - repeat rewrite wnot_wnot'_equiv. - unfold wnot'. - rewrite <- combine_wones, combine_bitwp. - reflexivity. -Qed. - -Theorem wnot_zero: forall sz, wnot (wzero sz) = wones sz. -Proof. - induction sz; simpl; f_equal; eauto. -Qed. - -Theorem wnot_ones : forall sz, wnot (wones sz) = wzero sz. -Proof. - induction sz; simpl; f_equal; try rewrite IHsz; eauto. -Qed. - -Theorem wnot_eq_rect : forall a b H (w : word a), wnot (eq_rect a word w b H) = eq_rect a word (wnot w) b H. -Proof. - intros. - subst b; eq_rect_simpl; auto. -Qed. - -Theorem wor_unit : forall sz (x : word sz), wzero sz ^| x = x. -Proof. - unfold wzero, wor; induction x; simpl; intuition congruence. -Qed. - -Theorem wor_comm : forall sz (x y : word sz), x ^| y = y ^| x. -Proof. - unfold wor; induction x; intro y; rewrite (shatter_word y); simpl; intuition; f_equal; auto with bool. -Qed. - -Theorem wor_assoc : forall sz (x y z : word sz), x ^| (y ^| z) = x ^| y ^| z. -Proof. - unfold wor; induction x; intro y; rewrite (shatter_word y); simpl; intuition; f_equal; auto with bool. -Qed. - -Theorem wand_unit : forall sz (x : word sz), wones sz ^& x = x. -Proof. - unfold wand; induction x; simpl; intuition congruence. -Qed. - -Theorem wand_kill : forall sz (x : word sz), wzero sz ^& x = wzero sz. -Proof. - unfold wzero, wand; induction x; simpl; intuition congruence. -Qed. - -Theorem wand_comm : forall sz (x y : word sz), x ^& y = y ^& x. -Proof. - unfold wand; induction x; intro y; rewrite (shatter_word y); simpl; intuition; f_equal; auto with bool. -Qed. - -Theorem wand_assoc : forall sz (x y z : word sz), x ^& (y ^& z) = x ^& y ^& z. -Proof. - unfold wand; induction x; intro y; rewrite (shatter_word y); simpl; intuition; f_equal; auto with bool. -Qed. - -Theorem wand_or_distr : forall sz (x y z : word sz), (x ^| y) ^& z = (x ^& z) ^| (y ^& z). -Proof. - unfold wand, wor; induction x; intro y; rewrite (shatter_word y); intro z; rewrite (shatter_word z); simpl; intuition; f_equal; auto with bool. - destruct (whd y); destruct (whd z); destruct b; reflexivity. -Qed. - -Lemma wor_wones : forall sz w, wones sz ^| w = wones sz. -Proof. - unfold wor; induction sz; intros; simpl; auto. - rewrite IHsz; auto. -Qed. - -Lemma wor_wzero : forall sz w, wzero sz ^| w = w. -Proof. - unfold wor; induction sz; shatterer. -Qed. - -Lemma wand_wones : forall sz w, wones sz ^& w = w. -Proof. - unfold wand; induction sz; shatterer. -Qed. - -Lemma wand_wzero : forall sz w, wzero sz ^& w = wzero sz. -Proof. - intros. rewrite <- wzero'_def. - unfold wand; induction sz; shatterer. -Qed. - -Lemma wxor_wones : forall sz w, wxor (wones sz) w = wnot w. -Proof. - unfold wxor; induction sz; shatterer. -Qed. - -Lemma wxor_wzero : forall sz w, wxor (wzero sz) w = w. -Proof. - unfold wxor; induction sz; shatterer; destruct (whd w); auto. -Qed. - -Lemma wxor_comm : forall sz (w1 w2 : word sz), wxor w1 w2 = wxor w2 w1. -Proof. - unfold wxor; induction sz. shatterer. - intros. rewrite (shatter_word w1), (shatter_word w2). - simpl. - rewrite xorb_comm, IHsz. - reflexivity. -Qed. - -Lemma wxor_assoc : forall sz (w1 w2 w3 : word sz), wxor w1 (wxor w2 w3) = wxor (wxor w1 w2) w3. -Proof. - unfold wxor. - induction sz; intros; rewrite (shatter_word w1), (shatter_word w2), (shatter_word w3); auto. - simpl; f_equal. - rewrite xorb_assoc_reverse; auto. - rewrite IHsz. - reflexivity. -Qed. - -Lemma wor_wone : forall sz (w : word sz) b, - WS b w ^| wone _ = WS true w. -Proof. - intros. - compute [wone natToWord wor]. simpl. - fold natToWord. - change (natToWord sz 0) with (wzero sz). - rewrite orb_true_r. - rewrite wor_comm, wor_wzero. - reflexivity. -Qed. - -Lemma wand_wone : forall sz (w : word sz) b, - WS b w ^& wone _ = WS b (wzero _). -Proof. - intros. - compute [wone natToWord wand]. simpl. - fold natToWord. - change (natToWord sz 0) with (wzero sz). - rewrite andb_true_r. - rewrite wand_comm, wand_wzero. - reflexivity. -Qed. - -Lemma wxor_wone : forall sz (w : word sz) b, - wxor (WS b w) (wone _) = WS (negb b) w. -Proof. - intros. - compute [wone natToWord wxor]. simpl. - fold natToWord. - change (natToWord sz 0) with (wzero sz). - rewrite xorb_true_r. - rewrite wxor_comm, wxor_wzero. - reflexivity. -Qed. - -Definition wbring (sz : nat) : semi_ring_theory (wzero sz) (wones sz) (@wor sz) (@wand sz) (@eq _) := - mk_srt _ _ _ _ _ - (@wor_unit _) (@wor_comm _) (@wor_assoc _) - (@wand_unit _) (@wand_kill _) (@wand_comm _) (@wand_assoc _) - (@wand_or_distr _). - -(** * Inequality proofs *) - -Ltac word_simpl := unfold sext, zext, wzero in *; simpl in *. - -Ltac word_eq := ring. - -Ltac word_eq1 := match goal with - | _ => ring - | [ H : _ = _ |- _ ] => ring [H] - end. - -Theorem word_neq : forall sz (w1 w2 : word sz), - w1 ^- w2 <> wzero sz - -> w1 <> w2. - intros; intro; subst. - unfold wminus in H. - rewrite wminus_inv in H. - tauto. -Qed. - -Ltac word_neq := apply word_neq; let H := fresh "H" in intro H; simpl in H; ring_simplify in H; try discriminate. - -Ltac word_contra := match goal with - | [ H : _ <> _ |- False ] => apply H; ring - end. - -Ltac word_contra1 := match goal with - | [ H : _ <> _ |- False ] => apply H; - match goal with - | _ => ring - | [ H' : _ = _ |- _ ] => ring [H'] - end - end. - -Lemma not_wlt_ge : forall sz (l r : word sz), - ((l < r) -> False) -> (r <= l). -Proof. - intros. - case_eq (wlt_dec l r); intros; - try contradiction; - auto. -Qed. - -Lemma not_wle_gt : forall sz (l r : word sz), - ((l <= r) -> False) -> (r < l). -Proof. - intros. - case_eq (wlt_dec r l); intros; - try contradiction; - auto. -Qed. - -Lemma lt_le : forall sz (a b : word sz), - a < b -> a <= b. -Proof. - unfold wlt, N.lt. intros sz a b H H0. rewrite N.compare_antisym in H0. rewrite H in H0. simpl in *. congruence. -Qed. - -Lemma eq_le : forall sz (a b : word sz), - a = b -> a <= b. -Proof. - intros; subst. unfold wlt, N.lt. rewrite N.compare_refl. congruence. -Qed. - -Lemma wordToN_inj : forall sz (a b : word sz), - wordToN a = wordToN b -> a = b. -Proof. - induction a; intro b0; rewrite (shatter_word b0); intuition. - simpl in H. - destruct b; destruct (whd b0); intros. - f_equal. eapply IHa. eapply N.succ_inj in H. - destruct (wordToN a); destruct (wordToN (wtl b0)); try congruence. - destruct (wordToN (wtl b0)); destruct (wordToN a); inversion H. - destruct (wordToN (wtl b0)); destruct (wordToN a); inversion H. - f_equal. eapply IHa. - destruct (wordToN a); destruct (wordToN (wtl b0)); try congruence. -Qed. - -Lemma wordToNat_inj : forall sz (a b : word sz), - wordToNat a = wordToNat b -> a = b. -Proof. - intros; apply wordToN_inj. - repeat rewrite wordToN_nat. - apply Nat2N.inj_iff; auto. -Qed. - -Lemma unique_inverse : forall sz (a b1 b2 : word sz), - a ^+ b1 = wzero _ -> - a ^+ b2 = wzero _ -> - b1 = b2. -Proof. - intros sz a b1 b2 H *. - transitivity (b1 ^+ wzero _). - rewrite wplus_comm. rewrite wplus_unit. auto. - transitivity (b1 ^+ (a ^+ b2)). congruence. - rewrite wplus_assoc. - rewrite (wplus_comm b1). rewrite H. rewrite wplus_unit. auto. -Qed. - -Lemma sub_0_eq : forall sz (a b : word sz), - a ^- b = wzero _ -> a = b. -Proof. - intros sz a b H. destruct (weq (wneg b) (wneg a)) as [e|n]. - transitivity (a ^+ (^~ b ^+ b)). - rewrite (wplus_comm (^~ b)). rewrite wminus_inv. - rewrite wplus_comm. rewrite wplus_unit. auto. - rewrite e. rewrite wplus_assoc. rewrite wminus_inv. rewrite wplus_unit. auto. - unfold wminus in H. - generalize (unique_inverse a (wneg a) (^~ b)). - intro H0. elimtype False. apply n. symmetry; apply H0. - apply wminus_inv. - auto. -Qed. - -Lemma le_neq_lt : forall sz (a b : word sz), - b <= a -> a <> b -> b < a. -Proof. - intros sz a b H H0; destruct (wlt_dec b a) as [?|n]; auto. - elimtype False. apply H0. unfold wlt, N.lt in *. - eapply wordToN_inj. eapply Ncompare_eq_correct. - case_eq ((wordToN a ?= wordToN b)%N); auto; try congruence. - intros H1. rewrite N.compare_antisym in n. rewrite H1 in n. simpl in *. congruence. -Qed. - - -Hint Resolve word_neq lt_le eq_le sub_0_eq le_neq_lt : worder. - -Ltac shatter_word x := - match type of x with - | word 0 => try rewrite (shatter_word_0 x) in * - | word (S ?N) => - let x' := fresh in - let H := fresh in - destruct (@shatter_word_S N x) as [ ? [ x' H ] ]; - rewrite H in *; clear H; shatter_word x' - end. - - -(** Uniqueness of equality proofs **) -Lemma rewrite_weq : forall sz (a b : word sz) - (pf : a = b), - weq a b = left _ pf. -Proof. - intros sz a b *; destruct (weq a b); try solve [ elimtype False; auto ]. - f_equal. - eapply UIP_dec. eapply weq. -Qed. - - -(** * Some more useful derived facts *) - -Lemma natToWord_plus : forall sz n m, natToWord sz (n + m) = natToWord _ n ^+ natToWord _ m. - destruct sz as [|sz]; intros n m; intuition. - rewrite wplus_alt. - unfold wplusN, wordBinN. - destruct (wordToNat_natToWord (S sz) n); intuition. - destruct (wordToNat_natToWord (S sz) m); intuition. - do 2 match goal with H : _ |- _ => rewrite H; clear H end. - match goal with - | [ |- context[?n - ?x * pow2 (S ?sz) + (?m - ?x0 * pow2 (S ?sz))] ] - => replace (n - x * pow2 (S sz) + (m - x0 * pow2 (S sz))) with (n + m - x * pow2 (S sz) - x0 * pow2 (S sz)) - by omega - end. - repeat rewrite drop_sub; auto; omega. -Qed. - -Lemma natToWord_S : forall sz n, natToWord sz (S n) = natToWord _ 1 ^+ natToWord _ n. - intros sz n; change (S n) with (1 + n); apply natToWord_plus. -Qed. - -Theorem natToWord_inj : forall sz n m, natToWord sz n = natToWord sz m - -> (n < pow2 sz)%nat - -> (m < pow2 sz)%nat - -> n = m. - intros sz n m H H0 H1. - apply (f_equal (@wordToNat _)) in H. - destruct (wordToNat_natToWord sz n) as [x H2]. - destruct (wordToNat_natToWord sz m) as [x0 H3]. - intuition. - match goal with - | [ H : wordToNat ?x = wordToNat ?y, H' : wordToNat ?x = ?a, H'' : wordToNat ?y = ?b |- _ ] - => let H0 := fresh in assert (H0 : a = b) by congruence; clear H H' H''; rename H0 into H - end. - assert (x = 0). - destruct x; auto. - simpl in *. - generalize dependent (x * pow2 sz). - intros. - omega. - assert (x0 = 0). - destruct x0; auto. - simpl in *. - generalize dependent (x0 * pow2 sz). - intros. - omega. - subst; simpl in *; omega. -Qed. - -Lemma wordToNat_natToWord_idempotent : forall sz n, - (N.of_nat n < Npow2 sz)%N - -> wordToNat (natToWord sz n) = n. - intros sz n H. - destruct (wordToNat_natToWord sz n) as [x]; intuition. - destruct x as [|x]. - simpl in *; omega. - simpl in *. - apply Nlt_out in H. - autorewrite with N in *. - rewrite Npow2_nat in *. - generalize dependent (x * pow2 sz). - intros; omega. -Qed. - -Lemma wplus_cancel : forall sz (a b c : word sz), - a ^+ c = b ^+ c - -> a = b. - intros sz a b c H. - apply (f_equal (fun x => x ^+ ^~ c)) in H. - repeat rewrite <- wplus_assoc in H. - rewrite wminus_inv in H. - repeat rewrite (wplus_comm _ (wzero sz)) in H. - repeat rewrite wplus_unit in H. - assumption. -Qed. - -Lemma wminus_plus_distr: - forall {sz} (x y z: word sz), x ^- (y ^+ z) = x ^- y ^- z. -Proof. - intros. - apply wplus_cancel with (c:= y ^+ z). - rewrite wminus_def, <-wplus_assoc. - rewrite wplus_comm with (y:= y ^+ z), wminus_inv. - rewrite wplus_comm with (x:= x), wplus_unit. - rewrite !wminus_def, <-wplus_assoc. - rewrite wplus_assoc with (x:= ^~ z). - rewrite wplus_comm with (x:= ^~ z). - rewrite <-wplus_assoc with (x:= y). - rewrite wplus_comm with (x:= ^~ z), wminus_inv. - rewrite wplus_comm with (x:= y), wplus_unit. - rewrite <-wplus_assoc. - rewrite wplus_comm with (x:= ^~ y), wminus_inv. - rewrite wplus_comm, wplus_unit. - reflexivity. -Qed. - -Lemma wminus_wplus_undo: forall sz (a b: word sz), - a ^- b ^+ b = a. -Proof. - intros. - rewrite wminus_def. - rewrite <- wplus_assoc. - rewrite (wplus_comm (^~ b)). - rewrite wminus_inv. - rewrite wplus_comm. - rewrite wplus_unit. - reflexivity. -Qed. - -Lemma wneg_zero: - forall {sz} (w: word sz), ^~ w = (natToWord sz 0) -> w = natToWord sz 0. -Proof. - intros. - apply wplus_cancel with (c:= ^~ w). - rewrite wminus_inv, wplus_unit; auto. -Qed. - -Lemma wneg_idempotent: - forall {sz} (w: word sz), ^~ (^~ w) = w. -Proof. - intros. - apply sub_0_eq. - rewrite wminus_def. - rewrite wplus_comm. - apply wminus_inv. -Qed. - -Lemma wneg_zero': forall sz, - wneg (natToWord sz 0) = natToWord sz 0. -Proof. - intros. apply wneg_zero. apply wneg_idempotent. -Qed. - -Lemma wplus_one_neq: forall {sz} (w: word (S sz)), w ^+ (natToWord (S sz) 1) <> w. -Proof. - intros; intro Hx. - rewrite wplus_comm in Hx. - assert ((natToWord (S sz) 1) ^+ w ^- w = w ^- w) by (rewrite Hx; reflexivity). - clear Hx. - do 2 rewrite wminus_def in H. - rewrite <-wplus_assoc in H. - rewrite wminus_inv in H. - rewrite wplus_comm, wplus_unit in H. - inversion H. -Qed. - -Lemma wneg_one_pow2_minus_one: forall {sz}, wordToNat (^~ (natToWord sz 1)) = pow2 sz - 1. -Proof. - destruct sz; auto. - unfold wneg; intros. - rewrite wordToN_nat, roundTrip_1. - simpl BinNat.N.of_nat. - rewrite NToWord_nat, Nnat.N2Nat.inj_sub, Npow2_nat. - apply wordToNat_natToWord_2. - pose (pow2_zero (S sz)). - omega. -Qed. - -Lemma wones_pow2_minus_one: forall {sz}, wordToNat (wones sz) = pow2 sz - 1. -Proof. - induction sz; simpl; auto. - rewrite IHsz; pose (pow2_zero sz). - omega. -Qed. - -Lemma pow2_minus_one_wones: forall {sz} (w: word sz), - wordToNat w = pow2 sz - 1 -> w = wones sz. -Proof. - intros; rewrite <-wones_pow2_minus_one in H. - apply wordToNat_inj; auto. -Qed. - -Lemma wones_natToWord: forall sz, - wones sz = $ (pow2 sz - 1). -Proof. - induction sz. - - reflexivity. - - unfold wones. fold wones. rewrite IHsz. - unfold natToWord at 2. fold natToWord. f_equal. - + rewrite mod2sub. - * simpl. rewrite mod2_pow2_twice. reflexivity. - * pose proof (zero_lt_pow2 (S sz)). omega. - + f_equal. unfold pow2 at 2. fold pow2. - rewrite <- (div2_S_double (pow2 sz - 1)). f_equal. - pose proof (zero_lt_pow2 sz). omega. -Qed. - -Lemma wones_wneg_one: forall {sz}, wones sz = ^~ (natToWord sz 1). -Proof. - intros; apply wordToNat_inj. - rewrite wneg_one_pow2_minus_one. - rewrite wones_pow2_minus_one. - reflexivity. -Qed. - -Lemma wordToNat_natToWord_pred: - forall {sz} (w: word sz), w <> wzero sz -> - pred (wordToNat w) = - wordToNat (w ^- (natToWord sz 1)). -Proof. - intros; remember (wordToNat w) as wn; destruct wn; simpl in *. - - elim H. - apply wordToNat_inj. - rewrite roundTrip_0; auto. - - apply natToWord_inj with (sz:= sz). - + rewrite natToWord_wordToNat. - apply wplus_cancel with (c:= (natToWord sz 1)). - rewrite wminus_def, <-wplus_assoc. - rewrite wplus_comm with (x:= ^~ (natToWord sz 1)). - rewrite wminus_inv. - rewrite wplus_comm with (x:= w). - rewrite wplus_unit. - rewrite wplus_comm, <-natToWord_S. - apply wordToNat_inj. - rewrite wordToNat_natToWord_2; auto. - rewrite Heqwn. - apply wordToNat_bound. - + pose proof (wordToNat_bound w); omega. - + apply wordToNat_bound. -Qed. - -Lemma natToWord_mult : forall sz n m, natToWord sz (n * m) = natToWord _ n ^* natToWord _ m. -Proof. - destruct sz; intuition. - rewrite wmult_alt. - unfold wmultN, wordBinN. - destruct (wordToNat_natToWord (S sz) n); intuition. - destruct (wordToNat_natToWord (S sz) m); intuition. - rewrite H0; rewrite H2; clear H0 H2. - replace ((n - x * pow2 (S sz)) * (m - x0 * pow2 (S sz))) - with ((n - x * pow2 (S sz)) * m - (n - x * pow2 (S sz)) * (x0 * pow2 (S sz))) - by (rewrite Nat.mul_sub_distr_l; auto). - rewrite mult_assoc; rewrite drop_sub. - repeat rewrite mult_comm with (m:=m). - replace (m * (n - x * pow2 (S sz))) - with (m * n - m * (x * pow2 (S sz))) - by (rewrite Nat.mul_sub_distr_l; auto). - rewrite mult_assoc; rewrite drop_sub. - auto. - rewrite <- mult_assoc; apply Nat.mul_le_mono_l; auto. - rewrite <- mult_assoc; apply Nat.mul_le_mono_l; auto. -Qed. - -Lemma wlt_lt: forall sz (a b : word sz), a < b -> - (wordToNat a < wordToNat b)%nat. -Proof. - intros. - unfold wlt in H. - repeat rewrite wordToN_nat in *. - apply Nlt_out in H. - repeat rewrite Nat2N.id in *. - auto. -Qed. - -Lemma wle_le: forall sz (a b : word sz), (a <= b)%word -> - (wordToNat a <= wordToNat b)%nat. -Proof. - intros. - unfold wlt in H. - repeat rewrite wordToN_nat in *. - apply Nge_out in H. - repeat rewrite Nat2N.id in *. - auto. -Qed. - -Lemma wlt_lt': forall sz a b, (a < pow2 sz)%nat - -> natToWord sz a < b - -> (wordToNat (natToWord sz a) < wordToNat b)%nat. -Proof. - intros. - apply wlt_lt. - auto. -Qed. - -Lemma lt_word_lt_nat : forall (sz:nat) (n:word sz) (m:nat), - (n < (natToWord sz m))%word -> - (wordToNat n < m)%nat. -Proof. - intros. - apply wlt_lt in H. - destruct (wordToNat_natToWord' sz m). - rewrite <- H0. - apply lt_plus_trans with (p := x * pow2 sz). - assumption. -Qed. - -Lemma le_word_le_nat : forall (sz:nat) (n:word sz) (m:nat), - (n <= (natToWord sz m))%word -> - (wordToNat n <= m)%nat. -Proof. - intros. - apply wle_le in H. - destruct (wordToNat_natToWord' sz m). - rewrite <- H0. - apply le_plus_trans with (p := x * pow2 sz). - assumption. -Qed. - -(* Chain [lt_word_lt_nat] and [Nat.lt_le_incl] - Avoids using [Hint Resolve Nat.lt_le_incl] for this specific lemma, - though this may be a premature optimization. *) -Lemma lt_word_le_nat : forall (sz:nat) (n:word sz) (m:nat), - (n < (natToWord sz m))%word -> - (wordToNat n <= m)%nat. -Proof. - intros. - apply lt_word_lt_nat in H. - apply Nat.lt_le_incl. - assumption. -Qed. - -Hint Resolve lt_word_le_nat. - -Lemma wordToNat_natToWord_idempotent' : forall sz n, - (n < pow2 sz)%nat - -> wordToNat (natToWord sz n) = n. -Proof. - intros. - destruct (wordToNat_natToWord sz n); intuition. - destruct x. - simpl in *; omega. - simpl in *. - generalize dependent (x * pow2 sz). - intros; omega. -Qed. - -Lemma le_word_le_nat': forall (sz:nat) n m, - (n < pow2 sz)%nat -> - (natToWord sz n <= m)%word -> - (n <= wordToNat m)%nat. -Proof. - intros. - apply wle_le in H0. - rewrite wordToNat_natToWord_idempotent' in H0; auto. -Qed. - -Lemma wordToNat_natToWord_bound : forall sz n (bound : word sz), - (n <= wordToNat bound)%nat - -> wordToNat (natToWord sz n) = n. -Proof. - intros. - apply wordToNat_natToWord_idempotent'. - eapply le_lt_trans; eauto. - apply wordToNat_bound. -Qed. - -Lemma wordToNat_natToWord_le : forall sz n, - (wordToNat (natToWord sz n) <= n)%nat. -Proof. - intros. - case_eq (lt_dec n (pow2 sz)); intros. - rewrite wordToNat_natToWord_idempotent'; auto. - eapply le_trans. - apply Nat.lt_le_incl. - apply wordToNat_bound. - omega. -Qed. - -Lemma wordToNat_natToWord_lt : forall sz n b, - (n < b -> wordToNat (natToWord sz n) < b)%nat. -Proof. - intros. - eapply le_lt_trans. - apply wordToNat_natToWord_le. - auto. -Qed. - -Lemma wordToNat_eq_natToWord : forall sz (w : word sz) n, - wordToNat w = n - -> w = natToWord sz n. -Proof. - intros. rewrite <- H. rewrite natToWord_wordToNat. auto. -Qed. - -Lemma wlt_lt_bound: forall sz (a : word sz) (b bound : nat), - (a < natToWord sz b)%word - -> (b <= wordToNat (natToWord sz bound))%nat - -> (wordToNat a < b)%nat. -Proof. - intros. - apply wlt_lt in H. - erewrite wordToNat_natToWord_bound in H; eauto. -Qed. - -Lemma natplus1_wordplus1_eq: - forall sz (a bound : word sz), - (0 < sz)%nat -> - (a < bound)%word -> - (wordToNat a) + 1 = wordToNat (a ^+ (natToWord sz 1)). -Proof. - intros. - rewrite wplus_alt. unfold wplusN, wordBinN. simpl. - assert ((1 < pow2 sz)%nat). - inversion H. - simpl; auto. - apply one_lt_pow2. - erewrite wordToNat_natToWord_bound. - rewrite wordToNat_natToWord_idempotent' by auto. - reflexivity. - apply wlt_lt in H0. - rewrite wordToNat_natToWord_idempotent' by auto. - instantiate (1:=bound). omega. -Qed. - -Lemma lt_wlt: forall sz (n : word sz) m, (wordToNat n < wordToNat m)%nat -> - n < m. -Proof. - intros. - unfold wlt. - repeat rewrite wordToN_nat. - apply Nlt_in. - repeat rewrite Nat2N.id. - auto. -Qed. - -Lemma le_wle: forall sz (n : word sz) m, (wordToNat n <= wordToNat m)%nat -> - n <= m. -Proof. - intros. - unfold wlt. - repeat rewrite wordToN_nat. - apply N.le_ngt. - apply N.ge_le. - apply Nge_in. - repeat rewrite Nat2N.id. - auto. -Qed. - -Lemma wlt_wle_incl : forall sz (a b : word sz), - (a < b)%word -> (a <= b)%word. -Proof. - intros. - apply wlt_lt in H. - apply le_wle. - omega. -Qed. - -Lemma wminus_Alt2: forall sz x y, y <= x -> - @wminusN sz x y = wordBinN minus x y. -Proof. - intros. - unfold wminusN, wplusN, wnegN, wordBinN. - destruct (weq y (natToWord sz 0)); subst. - - rewrite roundTrip_0. - repeat rewrite <- minus_n_O. - rewrite <- drop_sub with (k:=1) (n:=pow2 sz); try omega. - replace (pow2 sz - 1 * pow2 sz) with (0) by omega. - rewrite roundTrip_0. - rewrite <- plus_n_O. - reflexivity. - - rewrite wordToNat_natToWord_idempotent' with (n:=pow2 sz - wordToNat y). - rewrite <- drop_sub with (k:=1). - simpl. - rewrite <- plus_n_O. - replace (wordToNat x + (pow2 sz - wordToNat y) - pow2 sz) with (wordToNat x - wordToNat y). - auto. - rewrite Nat.add_sub_assoc. - omega. - - remember (wordToNat_bound y); omega. - - simpl. rewrite <- plus_n_O. - rewrite Nat.add_sub_assoc; [| remember (wordToNat_bound y); omega ]. - rewrite plus_comm. - rewrite <- Nat.add_sub_assoc. - omega. - - apply Nat.nlt_ge. - unfold not in *; intros. - apply H. - apply lt_wlt; auto. - - apply Nat.sub_lt. - remember (wordToNat_bound y); omega. - - assert (wordToNat y <> 0); try omega. - - assert (wordToN y <> wordToN (natToWord sz 0)). - unfold not in *. intros. apply n. - apply wordToN_inj. - auto. - - repeat rewrite wordToN_nat in H0. - unfold not in *. intros. apply H0. - apply N2Nat.inj. - repeat rewrite Nat2N.id. - rewrite roundTrip_0. - auto. -Qed. - -Theorem wlt_wf: - forall sz, well_founded (@wlt sz). -Proof. - intros. - eapply well_founded_lt_compat with (f:=@wordToNat sz). - apply wlt_lt. -Qed. - -Ltac wlt_ind := - match goal with - | [ |- forall (n: word ?len), ?P ] => - refine (well_founded_ind (@wlt_wf len) (fun n => P) _) - end. - -Theorem wordToNat_plusone: forall sz w w', w < w' -> - wordToNat (w ^+ natToWord sz 1) = S (wordToNat w). -Proof. - intros. - - destruct sz. - exfalso. - rewrite word0 with (w:=w') in H. - rewrite word0 with (w:=w) in H. - apply wlt_lt in H. - omega. - - rewrite wplus_alt. - unfold wplusN, wordBinN. - rewrite wordToNat_natToWord_idempotent'. - - rewrite roundTrip_1. - omega. - - eapply Nat.le_lt_trans; [| apply wordToNat_bound ]. - rewrite wordToNat_natToWord_idempotent'; - [| erewrite <- roundTrip_1 at 1; apply wordToNat_bound ]. - apply wlt_lt in H. - instantiate (1:=w'). - omega. -Qed. - - -Theorem wordToNat_minus_one': forall sz n, n <> natToWord sz 0 -> - S (wordToNat (n ^- natToWord sz 1)) = wordToNat n. -Proof. - intros. - destruct sz. - rewrite word0 with (w:=n) in H. - rewrite word0 with (w:=natToWord 0 0) in H. - exfalso; auto. - - destruct (weq n (natToWord (S sz) 0)); intuition. - rewrite wminus_Alt. - rewrite wminus_Alt2. - unfold wordBinN. - rewrite roundTrip_1. - erewrite wordToNat_natToWord_bound with (bound:=n); try omega. - assert (wordToNat n <> 0); try omega. - unfold not; intros; apply n0; clear n0. - rewrite <- H0; rewrite natToWord_wordToNat; auto. - unfold not; intros; apply n0; clear n0. - apply wlt_lt in H0. - replace n with (natToWord (S sz) (wordToNat n)) by (rewrite natToWord_wordToNat; auto). - f_equal; rewrite roundTrip_1 in *. - omega. -Qed. - -Theorem wordToNat_minus_one: forall sz n, n <> natToWord sz 0 -> - wordToNat (n ^- natToWord sz 1) = wordToNat n - 1. -Proof. - intros. - erewrite Nat.succ_inj with (n2 := wordToNat (n ^- (natToWord sz 1))); auto. - rewrite wordToNat_minus_one'; auto. - assert (wordToNat n <> 0). - intuition. - erewrite <- roundTrip_0 with (sz := sz) in H0. - apply wordToNat_inj in H0; tauto. - omega. -Qed. - -Lemma lt_minus : forall a b c, - (b <= a -> b < c -> a < c -> a - b < c)%nat. -Proof. - intros; omega. -Qed. - -Lemma wminus_minus : forall sz (a b : word sz), - b <= a - -> wordToNat (a ^- b) = wordToNat a - wordToNat b. -Proof. - intros. - rewrite wminus_Alt. - rewrite wminus_Alt2; auto. - unfold wordBinN. - eapply wordToNat_natToWord_idempotent'. - apply lt_minus. - apply wle_le; auto. - apply wordToNat_bound. - apply wordToNat_bound. -Qed. - -Lemma wminus_minus': forall (sz : nat) (a b : word sz), - (#b <= #a)%nat -> - #(a ^- b) = #a - #b. -Proof. - intros. apply wminus_minus. - unfold wlt. intro C. - apply Nlt_out in C. - rewrite! wordToN_to_nat in *. - omega. -Qed. - -Lemma wordToNat_neq_inj: forall sz (a b : word sz), - a <> b <-> wordToNat a <> wordToNat b. -Proof. - split; intuition. - apply wordToNat_inj in H0; auto. - subst; auto. -Qed. - -Lemma natToWord_discriminate: forall sz, (sz > 0)%nat -> natToWord sz 0 <> natToWord sz 1. -Proof. - unfold not. - intros. - induction sz. - omega. - unfold natToWord in H0; fold natToWord in H0. - discriminate H0. -Qed. - -Definition bit_dec : forall (a : word 1), {a = $0} + {a = $1}. - intro. - rewrite (shatter_word a). - replace (wtl a) with WO by auto. - destruct (whd a). - right; apply eq_refl. - left; apply eq_refl. -Defined. - -Lemma neq0_wneq0: forall sz (n : word sz), - wordToNat n <> 0 <-> n <> $0. -Proof. - split; intros. - apply wordToNat_neq_inj. - rewrite roundTrip_0; auto. - apply wordToNat_neq_inj in H. - rewrite roundTrip_0 in H; auto. -Qed. - -Lemma gt0_wneq0: forall sz (n : word sz), - (wordToNat n > 0)%nat <-> n <> $0. -Proof. - split; intros. - apply neq0_wneq0; omega. - apply wordToNat_neq_inj in H. - rewrite roundTrip_0 in H; omega. -Qed. - -Lemma weq_minus1_wlt: forall sz (a b : word sz), - (a <> $0 -> a ^- $1 = b -> a > b)%word. -Proof. - intros. - apply lt_wlt; subst. - rewrite wordToNat_minus_one; auto. - apply gt0_wneq0 in H. - omega. -Qed. - -Lemma wordnat_minus1_eq : forall sz n (w : word sz), - (n > 0)%nat - -> n = wordToNat w - -> n - 1 = wordToNat (w ^- $1). -Proof. - intros; rewrite wordToNat_minus_one; auto. - apply gt0_wneq0; subst; auto. -Qed. - -Theorem wlshift_0 : forall sz (w : word sz), @wlshift sz w 0 = w. -Proof. - intros. - unfold wlshift. - eapply split1_0. -Qed. - -Theorem wrshift_0 : forall sz (w : word sz), @wrshift sz w 0 = w. -Proof. - intros. - unfold wrshift. - simpl. - rewrite combine_n_0. - eq_rect_simpl. reflexivity. -Qed. - -Theorem wlshift_gt : forall sz n (w : word sz), (n > sz)%nat -> - wlshift w n = wzero sz. -Proof. - intros sz n w H. - generalize dependent w. - remember (n - sz) as e. - assert (n = sz + e) by omega; subst n. - intros w. - unfold wlshift. - rewrite <- combine_wzero. - erewrite combine_assoc, eq_rect_word_match. - eq_rect_simpl. - rewrite eq_rect_combine. - apply split1_combine. - Grab Existential Variables. omega. -Qed. - -Theorem wrshift_gt : forall sz n (w : word sz), (n > sz)%nat -> - wrshift w n = wzero sz. -Proof. - intros sz n w H. - generalize dependent w. - remember (n - sz) as e. - assert (n = sz + e) by omega; subst n. - intros w. - unfold wrshift. - erewrite wzero_rev, <- combine_wzero. - eq_rect_simpl. - rewrite <- eq_rect_word_match, <- eq_rect_combine, eq_rect_word_match. - eq_rect_simpl. - rewrite eq_rect_combine_assoc', split2_combine. - reflexivity. - Grab Existential Variables. omega. -Qed. - -Theorem wlshift_bitwp : forall sz (w1 w2 : word sz) f n, - wlshift (bitwp f w1 w2) n = split1 sz n ( - eq_rec _ word (combine (wzero n) (bitwp f w1 w2)) _ (eq_sym (Nat.add_comm sz n))). -Proof. - intros. - unfold wlshift. - eq_rect_simpl. - reflexivity. -Qed. - -Theorem wrshift_bitwp : forall sz (w1 w2 : word sz) f n, - wrshift (bitwp f w1 w2) n = split2 n sz ( - eq_rect _ word (combine (bitwp f w1 w2) (wzero n)) _ (eq_sym (Nat.add_comm n sz))). -Proof. - intros. - unfold wrshift. - eq_rect_simpl. - reflexivity. -Qed. - -Theorem wnot_wlshift : forall sz (w : word sz) n, - wnot (wlshift w n) = split1 sz n (eq_rect _ word (combine (wones n) (wnot w)) _ (eq_sym (Nat.add_comm sz n))). -Proof. - intros. - unfold wlshift. - rewrite wnot_split1. - eq_rect_simpl. - rewrite wnot_eq_rect. - rewrite wnot_combine. - rewrite wnot_zero. - reflexivity. -Qed. - -Theorem wnot_wrshift : forall sz (w : word sz) n, - wnot (wrshift w n) = split2 n sz (eq_rect _ word (combine (wnot w) (wones n)) _ (eq_sym (Nat.add_comm n sz))). -Proof. - intros. - unfold wrshift. - rewrite wnot_split2. - eq_rect_simpl. - rewrite wnot_eq_rect. - rewrite wnot_combine. - rewrite wnot_zero. - reflexivity. -Qed. - -Lemma wlshift_alt: forall sz n (a: word sz), - wlshift' a n = wlshift a n. -Proof. - intros. unfold wlshift, wlshift'. - unfold eq_rec_r. - unfold eq_rec. - erewrite nat_cast_proof_irrel. - rewrite nat_cast_eq_rect. - reflexivity. -Qed. - -Theorem div2_pow2_twice: forall n, - Nat.div2 (pow2 n + (pow2 n + 0)) = pow2 n. -Proof. - intros. - replace (pow2 n + (pow2 n + 0)) with (2 * pow2 n) by omega. - rewrite Nat.div2_double. - auto. -Qed. - -Theorem zero_or_wordToNat_S: forall sz (n : word sz), - n = $0 \/ - exists nn, wordToNat n = S nn /\ wordToNat (n ^- $1) = nn. -Proof. - intros. - destruct sz. - left. rewrite (word0 n). auto. - destruct (weq n $0); intuition. - right. - exists (wordToNat (n ^- $1)); intuition. - rewrite wminus_Alt. - rewrite wminus_Alt2. - unfold wordBinN. - rewrite roundTrip_1. - erewrite wordToNat_natToWord_bound with (bound:=n); try omega. - assert (wordToNat n <> 0); try omega. - unfold not; intros; apply n0; clear n0. - rewrite <- H. rewrite natToWord_wordToNat; auto. - unfold not; intros; apply n0; clear n0. - apply wlt_lt in H. - replace n with (natToWord (S sz) (wordToNat n)) by (rewrite natToWord_wordToNat; auto). - f_equal. - rewrite roundTrip_1 in *. - omega. -Qed. - -Theorem wbit_or_same : forall sz sz' (n : word sz'), (wordToNat n < sz)%nat - -> (wbit sz n) ^| (wbit sz n) <> wzero sz. -Proof. - unfold not. - induction sz; intros; try omega. - unfold wbit, wzero, wor in *. - simpl in *. - destruct (zero_or_wordToNat_S n). - subst; rewrite roundTrip_0 in *. discriminate. - destruct H1. destruct H1. - rewrite H1 in *. - inversion H0. - apply (inj_pair2_eq_dec _ eq_nat_dec) in H5. - rewrite div2_pow2_twice in H5. - repeat rewrite <- H2 in H5. - eapply IHsz; eauto. - omega. -Qed. - -Theorem wbit_or_other : forall sz sz' (n1 n2 : word sz'), (wordToNat n1 < sz)%nat - -> (wordToNat n2 < sz)%nat - -> (n1 <> n2) - -> (wbit sz n1) ^& (wbit sz n2) = wzero sz. -Proof. - induction sz; intros; try omega. - unfold wbit, wzero, wand. - simpl. - destruct (zero_or_wordToNat_S n1); destruct (zero_or_wordToNat_S n2); - try congruence; destruct_conjs; subst; try rewrite roundTrip_0. - - repeat rewrite H4; simpl; repeat rewrite mod2_pow2_twice; f_equal. - rewrite wand_kill; auto. - - repeat rewrite H4; simpl; repeat rewrite mod2_pow2_twice; f_equal. - rewrite wand_comm; rewrite wand_kill; auto. - - repeat rewrite H4; repeat rewrite H6; simpl. - repeat rewrite mod2_pow2_twice; f_equal. - repeat rewrite div2_pow2_twice. - eapply IHsz; try omega. - - apply word_neq. - unfold not in *; intros; apply H1; clear H1. - apply sub_0_eq; rewrite <- H2. - ring_sz sz'. -Qed. - -Theorem wbit_and_not: forall sz sz' (n : word sz'), (wordToNat n < sz)%nat - -> (wbit sz n) ^& wnot (wbit sz n) = wzero sz. -Proof. - induction sz; intros; try omega. - unfold wbit, wzero, wand, wnot. - simpl. - f_equal. - apply andb_negb_r. - - destruct (zero_or_wordToNat_S n); subst. - rewrite roundTrip_0; simpl. - apply wand_kill. - - do 2 destruct H0. - rewrite H0; simpl. - rewrite div2_pow2_twice. - fold wnot. - rewrite <- H1. - eapply IHsz. - omega. -Qed. - -Theorem wbit_and_not_other: forall sz sz' (n1 n2 : word sz'), (wordToNat n1 < sz)%nat - -> (wordToNat n2 < sz)%nat - -> n1 <> n2 - -> (wbit sz n1) ^& wnot (wbit sz n2) = wbit sz n1. -Proof. - induction sz; intros; try omega. - unfold wbit, wzero, wand, wnot. - simpl. - destruct (zero_or_wordToNat_S n1); destruct (zero_or_wordToNat_S n2); - try congruence; destruct_conjs; subst; fold wnot; try rewrite roundTrip_0; simpl; - f_equal. - - rewrite H4; simpl; rewrite mod2_pow2_twice; auto. - rewrite H4; simpl; rewrite div2_pow2_twice; apply wand_kill. - - rewrite H4; simpl; rewrite mod2_pow2_twice; auto. - rewrite H4; simpl; rewrite div2_pow2_twice. - rewrite wnot_zero. rewrite wand_comm. apply wand_unit. - - rewrite H4; simpl; rewrite mod2_pow2_twice; simpl; apply andb_true_r. - rewrite H4; rewrite H6; simpl. - repeat rewrite div2_pow2_twice. - apply IHsz; try omega. - - apply word_neq. - unfold not in *; intros; apply H1. - apply sub_0_eq. - rewrite <- H2. - ring_sz sz'. -Qed. - -Lemma wordToNat_wzero: - forall sz, wordToNat (wzero sz) = 0. -Proof. - unfold wzero; intros. - apply roundTrip_0. -Qed. - -Lemma wordToN_wzero: - forall sz, wordToN (wzero sz) = 0%N. -Proof. - intros; rewrite wordToN_nat. - rewrite wordToNat_wzero. - reflexivity. -Qed. - -Lemma combine_zero: - forall n m, combine (natToWord n 0) (natToWord m 0) = natToWord _ 0. -Proof. - induction n; simpl; intros; [reflexivity|]. - rewrite IHn; reflexivity. -Qed. - -Lemma combine_one: - forall n m, combine (natToWord (S n) 1) (natToWord m 0) = natToWord _ 1. -Proof. - cbn; intros. - rewrite combine_zero; reflexivity. -Qed. - -Lemma wmsb_wzero': - forall sz, wmsb (wzero' sz) false = false. -Proof. induction sz; auto. Qed. - -Lemma wmsb_wzero: - forall sz, wmsb (wzero sz) false = false. -Proof. - intros. - rewrite <-wzero'_def. - apply wmsb_wzero'. -Qed. - -Lemma wmsb_wones: - forall sz, wmsb (wones (S sz)) false = true. -Proof. - induction sz; cbn; auto. -Qed. - -Lemma wmsb_0: forall sz (m: word (S sz)) default, - (# m < pow2 sz)%nat -> - @wmsb (S sz) m default = false. -Proof. - induction sz; intros. - - simpl in *. assert (#m = 0) as N by omega. - rewrite <- (roundTrip_0 1) in N. - apply wordToNat_inj in N. subst m. - simpl. reflexivity. - - pose proof (shatter_word_S m) as P. - destruct P as [b [m0 E]]. subst. - unfold wmsb. fold wmsb. - apply IHsz. - simpl in H. destruct b; omega. -Qed. - -Lemma wmsb_1: forall sz (m: word (S sz)) default, - pow2 sz <= # m < 2 * pow2 sz -> - @wmsb (S sz) m default = true. -Proof. - induction sz; intros. - - simpl in *. assert (#m = 1) as N by omega. - rewrite <- (roundTrip_1 1) in N. - apply (wordToNat_inj m ($ 1)) in N. subst m. - simpl. reflexivity. - - pose proof (shatter_word_S m) as P. - destruct P as [b [m0 E]]. subst. - unfold wmsb. fold wmsb. - apply IHsz. - simpl in H. destruct b; omega. -Qed. - -Lemma wmsb_0_natToWord: forall sz n default, - (2 * n < pow2 (S sz))%nat -> - @wmsb (S sz) (natToWord (S sz) n) default = false. -Proof. - intros. apply wmsb_0. - pose proof (wordToNat_natToWord_le (S sz) n). unfold pow2 in H. fold pow2 in H. omega. -Qed. - -Lemma wmsb_1_natToWord: forall sz n default, - pow2 sz <= n < 2 * pow2 sz -> - @wmsb (S sz) (natToWord (S sz) n) default = true. -Proof. - intros. apply wmsb_1. - rewrite wordToNat_natToWord_idempotent'; simpl; omega. -Qed. - -Lemma wordToN_wzero': - forall sz, wordToN (wzero' sz) = 0%N. -Proof. - induction sz; simpl; auto. - rewrite IHsz; auto. -Qed. - -Lemma wordToZ_wzero': - forall sz, wordToZ (wzero' sz) = 0%Z. -Proof. - unfold wordToZ; intros. - rewrite wmsb_wzero'. - rewrite wordToN_wzero'. - reflexivity. -Qed. - -Lemma wordToZ_wzero: - forall sz, wordToZ (wzero sz) = 0%Z. -Proof. - unfold wordToZ; intros. - rewrite wmsb_wzero. - rewrite wordToN_wzero. - reflexivity. -Qed. - -Lemma wmsb_existT: (* Note: not axiom free *) - forall sz1 (w1: word sz1) sz2 (w2: word sz2), - existT word _ w1 = existT word _ w2 -> - forall b, wmsb w1 b = wmsb w2 b. -Proof. - intros. - assert (sz1 = sz2) by (apply eq_sigT_fst in H; auto); subst. - destruct_existT; reflexivity. -Qed. - -Lemma destruct_word_S: forall sz (w: word (S sz)), - exists v b, w = WS b v. -Proof. - intros. - refine (match w with - | WO => _ - | WS b v => _ - end); unfold IDProp; eauto. -Qed. - -Lemma induct_word_S: forall (P : forall n : nat, word (S n) -> Prop), - (forall b, P 0 (WS b WO)) -> - (forall b b0 n (w : word n), P n (WS b0 w) -> P (S n) (WS b (WS b0 w))) -> - forall (n : nat) (w : word (S n)), P n w. -Proof. - induction n; intros. - - destruct (destruct_word_S w) as [v [b E]]. subst w. - rewrite (word0 v). - apply H. - - destruct (destruct_word_S w) as [v [b E]]. subst w. - destruct (destruct_word_S v) as [w [b0 E]]. subst v. - apply H0. - apply IHn. -Qed. - -Lemma wmsb_ws: - forall sz (w: word (S sz)) b a, wmsb (WS b w) a = wmsb w a. -Proof. - intros. cbn. - destruct (destruct_word_S w) as [v [c E]]. - rewrite E. - reflexivity. -Qed. - -Lemma wmsb_extz: - forall sz (w: word sz) n, - wmsb (extz w n) false = wmsb w false. -Proof. - induction n; intros; auto. -Qed. - -Lemma wmsb_default: - forall sz (w: word sz) b1 b2, - sz <> 0 -> wmsb w b1 = wmsb w b2. -Proof. - dependent induction w; intros; intuition idtac. -Qed. - -Lemma wmsb_nat_cast: - forall sz1 (w: word sz1) sz2 (Hsz: sz1 = sz2) b, - wmsb w b = wmsb (nat_cast word Hsz w) b. -Proof. - destruct sz1; intros. - - subst sz2. reflexivity. - - destruct sz2; [discriminate|]. - destruct (destruct_word_S w) as [v [b0 E]]. subst w. - pose proof (eq_add_S sz1 sz2 Hsz) as Hsz'. - subst sz2. - rewrite nat_cast_eq_rect. - f_equal. - erewrite (WS_eq_rect _ _ _ eq_refl). - reflexivity. -Qed. - -Lemma wmsb_eq_rect: - forall sz1 (w: word sz1) sz2 (Hsz: sz1 = sz2) b, - wmsb w b = wmsb (eq_rect _ word w _ Hsz) b. -Proof. - intros. rewrite <- nat_cast_eq_rect. apply wmsb_nat_cast. -Qed. - -Local Arguments nat_cast: simpl never. - -Lemma nat_cast_inj: forall sz sz' (p: sz = sz') (w1 w2: word sz), - nat_cast word p w1 = nat_cast word p w2 -> - w1 = w2. -Proof. - intros. destruct p. rewrite? nat_cast_same in H. assumption. -Qed. - -Lemma wtl_nat_cast_WS: forall n m (q: n = m) (p: S n = S m) (w: word n) (b: bool), - wtl (nat_cast word p (WS b w)) = - nat_cast word q w. -Proof. - intros n m. destruct q. intros. - rewrite nat_cast_same. - transitivity (wtl (WS b w)); [|reflexivity]. - f_equal. - rewrite <- nat_cast_same. - apply nat_cast_proof_irrel. -Qed. - -Lemma wmsb_split2': forall sz (w: word (S sz)) b, - wmsb w b = negb (weqb (split2 sz 1 (nat_cast _ (eq_sym (Nat.add_1_r sz)) w)) (natToWord _ 0)). -Proof. - apply (induct_word_S (fun sz w => forall b, wmsb w b = - negb (weqb (split2 sz 1 (nat_cast _ (eq_sym (Nat.add_1_r sz)) w)) (natToWord _ 0)))); - intros. - - destruct b; reflexivity. - - cbn in *. rewrite (H false). repeat f_equal. - clear. - apply (nat_cast_inj (Nat.add_1_r n)). - erewrite wtl_nat_cast_WS. - reflexivity. -Qed. - -Lemma wmsb_split2: - forall sz (w: word (sz + 1)) b, - wmsb w b = if weq (split2 _ 1 w) (natToWord _ 0) then false else true. -Proof. - intros. - pose proof (@wmsb_split2' sz). specialize (H (nat_cast _ (Nat.add_1_r sz) w) b). - simpl in H. - rewrite nat_cast_fuse in H. - rewrite <- (nat_cast_proof_irrel word _ _ eq_refl) in H. - rewrite nat_cast_same in H. - destruct (weq (split2 sz 1 w) $ (0)). - - rewrite e in H. simpl in H. rewrite <- H. clear. - apply wmsb_nat_cast. - - simpl in n. apply weqb_ne in n. rewrite n in H. simpl in H. rewrite <- H. clear. - apply wmsb_nat_cast. -Qed. - -Lemma wmsb_true_split2_wones: - forall sz (w: word (sz + 1)) b, - wmsb w b = true -> - wones 1 = split2 sz 1 w. -Proof. - intros. - pose proof (wmsb_split2 _ w b). - destruct (weq _ _). - - rewrite H in H0; discriminate. - - clear -n. - remember (split2 sz 1 w) as ww; clear Heqww w. - destruct (destruct_word_S ww) as [w [b E]]. subst ww. - rewrite (word0 w) in *. clear w. simpl in *. destruct b; congruence. -Qed. - -Lemma wmsb_false_split2_wzero: - forall sz (w: word (sz + 1)) b, - wmsb w b = false -> - wzero 1 = split2 sz 1 w. -Proof. - intros. - pose proof (wmsb_split2 _ w b). - destruct (weq _ _); auto. - rewrite H in H0; discriminate. -Qed. - -Lemma wmsb_split1_sext: - forall sz (w: word (sz + 1)), - wmsb w false = wmsb (split1 _ 1 w) false -> - exists sw, sext sw 1 = w. -Proof. - unfold sext; intros. - pose proof (combine_split _ _ w) as Hw. - rewrite <-Hw; rewrite <-Hw in H at 2; clear Hw. - rewrite split1_combine in H. - exists (split1 sz 1 w). - destruct (wmsb (split1 sz 1 w) false). - - rewrite <-wmsb_true_split2_wones with (b:= false) by assumption. - reflexivity. - - rewrite <-wmsb_false_split2_wzero with (b:= false) by assumption. - reflexivity. -Qed. - -Lemma wmsb_combine_WO: - forall sz (w: word sz) b, - wmsb (combine w WO) b = wmsb w b. -Proof. - dependent induction w; cbn; intros; auto. -Qed. - -Lemma wmsb_combine: - forall sz1 sz2 (w1: word sz1) (w2: word sz2) b1 b2, - sz2 <> 0 -> - wmsb (combine w1 w2) b1 = wmsb w2 b2. -Proof. - dependent induction w1; cbn; intros. - - auto using wmsb_default. - - auto using IHw1. -Qed. - -Lemma wmsb_combine_existT: (* Note: not axiom free *) - forall sz (w: word sz) sz1 (w1: word sz1) sz2 (w2: word sz2) b1 b2, - sz2 <> 0 -> - existT word _ w = existT word _ (combine w1 w2) -> - wmsb w b1 = wmsb w2 b2. -Proof. - intros. - pose proof (eq_sigT_fst H0); subst. - destruct_existT. - auto using wmsb_combine. -Qed. - -Lemma wmsb_zext: - forall sz (w: word sz) b n, n <> 0 -> wmsb (zext w n) b = false. -Proof. - destruct n; cbn; intros; [elim H; reflexivity|]. - unfold zext. - erewrite wmsb_combine with (b2:= false) by discriminate. - apply wmsb_wzero. -Qed. - -Lemma wordToN_zext: - forall sz (w: word sz) n, - wordToN (zext w n) = wordToN w. -Proof. - dependent induction w; cbn; intros. - - induction n; cbn; intros; [reflexivity|]. - unfold wzero in IHn; rewrite IHn; reflexivity. - - rewrite IHw; reflexivity. -Qed. - -Lemma wordToNat_zext: - forall sz (w: word sz) n, - wordToNat (zext w n) = wordToNat w. -Proof. - dependent induction w; cbn; intros. - - induction n; cbn; intros; [reflexivity|]. - unfold wzero in IHn; rewrite IHn; reflexivity. - - rewrite IHw; reflexivity. -Qed. - -Lemma zext_wordToNat_equal_Z: - forall sz (w: word sz) n, - n <> 0 -> wordToZ (zext w n) = Z.of_nat (wordToNat w). -Proof. - unfold wordToZ, zext; intros. - rewrite wmsb_combine with (b2:= false) by assumption. - rewrite wmsb_wzero. - replace (combine w (wzero n)) with (zext w n) by reflexivity. - rewrite wordToN_zext. - rewrite wordToN_nat. - rewrite <-nat_N_Z. - unfold Z.of_N; reflexivity. -Qed. - -Lemma wordToN_WS_0: - forall sz (w: word sz), wordToN w~0 = (2 * wordToN w)%N. -Proof. reflexivity. Qed. - -Lemma wordToN_WS_1: - forall sz (w: word sz), wordToN w~1 = (2 * wordToN w + 1)%N. -Proof. - intros; cbn. - unfold N.succ_double. - destruct (wordToN w); reflexivity. -Qed. - -Lemma NToWord_WS_0: - forall sz n, NToWord (S sz) (2 * n) = (NToWord sz n)~0. -Proof. - destruct n; intros; [reflexivity|]. - replace (2 * N.pos p)%N with (N.pos (p~0)) by reflexivity. - reflexivity. -Qed. - -Lemma NToWord_WS_1: - forall sz n, NToWord (S sz) (2 * n + 1) = (NToWord sz n)~1. -Proof. - destruct n; intros; [reflexivity|]. - replace (2 * N.pos p)%N with (N.pos (p~0)) by reflexivity. - reflexivity. -Qed. - -Lemma wneg_WS_0: - forall sz (w: word sz), wneg w~0 = (wneg w)~0. -Proof. - unfold wneg; intros. - rewrite wordToN_WS_0. - replace (Npow2 (S sz)) with (2 * Npow2 sz)%N by reflexivity. - rewrite <-N.mul_sub_distr_l. - apply NToWord_WS_0. -Qed. - -Lemma NToWord_wordToN: - forall sz (w: word sz), NToWord sz (wordToN w) = w. -Proof. - intros. - rewrite wordToN_nat, NToWord_nat. - rewrite Nat2N.id. - apply natToWord_wordToNat. -Qed. - -Lemma roundTripN_0: - forall sz, wordToN (NToWord sz 0) = 0%N. -Proof. - intros. - rewrite wordToN_nat, NToWord_nat. - rewrite roundTrip_0; reflexivity. -Qed. - -Lemma wordToN_NToWord: - forall sz n, - exists k, wordToN (NToWord sz n) = (n - k * Npow2 sz)%N /\ (k * Npow2 sz <= n)%N. -Proof. - intros. - rewrite wordToN_nat, NToWord_nat. - pose proof (wordToNat_natToWord sz (N.to_nat n)). - destruct H as [k [? ?]]. - exists (N.of_nat k). - split. - - apply N2Nat.inj. - rewrite Nat2N.id, N2Nat.inj_sub, N2Nat.inj_mul. - rewrite Nat2N.id. - rewrite Npow2_nat. - assumption. - - rewrite nat_compare_le, Nat2N.inj_compare in H0. - rewrite Nat2N.inj_mul, <-Npow2_nat in H0. - do 2 rewrite N2Nat.id in H0. - assumption. -Qed. - -Lemma wordToN_NToWord_2: - forall sz n, (n < Npow2 sz)%N -> wordToN (NToWord sz n) = n. -Proof. - intros. - rewrite wordToN_nat, NToWord_nat. - rewrite wordToNat_natToWord_2. - - apply N2Nat.id. - - rewrite <-Npow2_nat. - apply Nlt_out; auto. -Qed. - -Lemma wordToN_bound: - forall sz (w: word sz), (wordToN w < Npow2 sz)%N. -Proof. - intros. - rewrite wordToN_nat. - apply Nlt_in. - rewrite Npow2_nat, Nat2N.id. - apply wordToNat_bound. -Qed. - -Lemma wordToN_plus: forall sz (a b: word sz), - (wordToN a + wordToN b < Npow2 sz)%N -> - wordToN (a ^+ b) = (wordToN a + wordToN b)%N. -Proof. - intros. unfold wplus, wordBin. - rewrite wordToN_NToWord_2 by assumption. - reflexivity. -Qed. - -Lemma wordToN_mult: forall sz (a b: word sz), - (wordToN a * wordToN b < Npow2 sz)%N -> - wordToN (a ^* b) = (wordToN a * wordToN b)%N. -Proof. - intros. unfold wmult, wordBin. - rewrite wordToN_NToWord_2 by assumption. - reflexivity. -Qed. - -Lemma wnot_def: - forall sz (w: word sz), wnot w = NToWord sz (Npow2 sz - wordToN w - 1). -Proof. - dependent induction w; cbn; [reflexivity|]. - destruct b; cbn. - - rewrite IHw; clear IHw. - rewrite <-NToWord_WS_0. - f_equal. - destruct (Npow2 n); [reflexivity|]. - destruct (wordToN w). - + change (N.pos p~0) with (2 * N.pos p)%N. - do 2 rewrite N.mul_sub_distr_l. - do 2 rewrite <-N.sub_add_distr. - reflexivity. - + change (N.pos p~0) with (2 * N.pos p)%N. - change (N.pos p0~0) with (2 * N.pos p0)%N. - rewrite <-N.add_1_l. - do 2 rewrite N.mul_sub_distr_l. - do 2 rewrite <-N.sub_add_distr. - rewrite N.add_comm with (n:= 1%N). - rewrite <-N.add_assoc. - reflexivity. - - rewrite IHw; clear IHw. - rewrite <-NToWord_WS_1. - f_equal. - pose proof (wordToN_bound w). - remember (Npow2 n) as pn; destruct pn; - [exfalso; eapply Npow2_not_zero; eauto|clear Heqpn]. - destruct (wordToN w). - + change (N.pos p~0) with (2 * N.pos p)%N. - do 2 rewrite N.mul_sub_distr_l. - do 2 rewrite <-N.sub_add_distr. - destruct p; cbn; reflexivity. - + change (N.pos p~0) with (2 * N.pos p)%N. - change (N.pos p0~0) with (2 * N.pos p0)%N. - rewrite N.mul_sub_distr_l. - rewrite <-N.mul_sub_distr_l with (n:= N.pos p). - assert (exists pp, N.pos p - N.pos p0 = N.pos pp)%N. - { apply N.sub_gt in H. - destruct (N.pos p - N.pos p0)%N; [intuition idtac|]. - eexists; reflexivity. - } - destruct H0; rewrite H0. - destruct x; cbn; reflexivity. -Qed. - -Lemma wneg_wnot: - forall sz (w: word sz), wnot w = wneg w ^- (natToWord _ 1). -Proof. - unfold wneg; intros. - rewrite wnot_def. - - destruct (weq w (wzero _)); subst. - - - rewrite wordToN_nat. - unfold wzero; rewrite roundTrip_0; cbn. - rewrite N.sub_0_r. - do 2 rewrite NToWord_nat. - rewrite Npow2_nat, natToWord_pow2, N2Nat.inj_sub. - change (N.to_nat 1%N) with 1. - rewrite Npow2_nat. - apply wordToNat_inj. - rewrite wordToNat_natToWord_2 by (pose proof (zero_lt_pow2 sz); omega). - unfold wminus. - rewrite wplus_unit, <-wones_wneg_one. - apply eq_sym, wones_pow2_minus_one. - - - pose proof (wordToN_bound w). - assert (Npow2 sz - wordToN w < Npow2 sz)%N. - { apply N.sub_lt. - { apply N.lt_le_incl; auto. } - { assert (wordToN w <> 0)%N. - { replace 0%N with (wordToN (wzero sz)). - { intro Hx; elim n. - apply wordToN_inj; auto. - } - { rewrite wordToN_nat. - unfold wzero; rewrite roundTrip_0; reflexivity. - } - } - nomega. - } - } - apply N.sub_gt in H. - remember (Npow2 sz - wordToN w)%N as p; clear Heqp. - do 2 rewrite NToWord_nat. - rewrite N2Nat.inj_sub. - change (N.to_nat 1%N) with 1. - assert (N.to_nat p < pow2 sz)%nat - by (rewrite <-Npow2_nat; apply Nlt_out; auto); clear H0. - assert (N.to_nat p <> 0) - by (change 0 with (N.to_nat 0%N); intro Hx; elim H; apply N2Nat.inj; auto); clear H. - apply wordToNat_inj. - rewrite <-wordToNat_natToWord_pred. - + do 2 rewrite wordToNat_natToWord_2 by omega. - omega. - + intro Hx; elim H0. - apply natToWord_inj with (sz:= sz); try omega. - assumption. -Qed. - -Lemma wzero_wneg: - forall n, wneg (wzero n) = wzero n. -Proof. - intros. - pose proof (wminus_inv (wzero n)). - rewrite wplus_unit in H; auto. -Qed. - -Lemma pow2_wneg: - forall sz, wneg (natToWord (S sz) (pow2 sz)) = natToWord (S sz) (pow2 sz). -Proof. - unfold wneg; intros. - rewrite <-Npow2_nat, <-NToWord_nat. - rewrite wordToN_NToWord_2 - by (apply Nlt_in; do 2 rewrite Npow2_nat; - pose proof (zero_lt_pow2 sz); simpl; omega). - rewrite Npow2_S. - f_equal; nomega. -Qed. - -Lemma wneg_WS_1: - forall sz (w: word sz), wneg w~1 = (wnot w)~1. -Proof. - intros. - apply wordToN_inj. - simpl; rewrite wnot_def. - unfold wneg. - rewrite wordToN_NToWord_2 - by (apply N.sub_lt; [apply N.lt_le_incl, wordToN_bound|nomega]). - rewrite wordToN_NToWord_2. - - rewrite wordToN_WS_1. - change (Npow2 (S sz)) with (2 * Npow2 sz)%N. - rewrite N.sub_add_distr. - rewrite <-N.mul_sub_distr_l. - assert (Npow2 sz - wordToN w <> 0)%N - by (pose proof (wordToN_bound w); nomega). - remember (Npow2 sz - wordToN w)%N as n; clear Heqn. - destruct n; [intuition idtac|]. - remember (N.pos p - 1)%N as pp; destruct pp. - + apply eq_sym, N.sub_0_le in Heqpp. - apply N.le_1_r in Heqpp; destruct Heqpp; [discriminate|]. - rewrite H0; reflexivity. - + change (N.pos p0~0) with (2 * N.pos p0)%N. - rewrite Heqpp. - rewrite <-N.add_1_r. - rewrite N.mul_sub_distr_l. - clear; destruct p; cbn; reflexivity. - - rewrite <-N.sub_add_distr. - apply N.sub_lt; [|nomega]. - pose proof (wordToN_bound w). - apply N.le_succ_l in H. - rewrite N.add_1_r; assumption. -Qed. - -Lemma wordToZ_WS_0: - forall sz (w: word sz), wordToZ w~0 = (2 * wordToZ w)%Z. -Proof. - dependent destruction w; [reflexivity|]. - unfold wordToZ. - rewrite wmsb_ws. - destruct (wmsb (WS b w) false). - - rewrite wneg_WS_0. - rewrite wordToN_WS_0. - destruct (wordToN (wneg (WS b w))); cbn; omega. - - rewrite wordToN_WS_0. - destruct (wordToN (WS b w)); cbn; omega. -Qed. - -Lemma wordToZ_WS_1: - forall sz (w: word (S sz)), wordToZ w~1 = (2 * wordToZ w + 1)%Z. -Proof. - intros. destruct (destruct_word_S w) as [v [b E]]. rewrite E. clear w E. rename v into w. - unfold wordToZ. - rewrite wmsb_ws. - remember (wmsb (WS b w) false) as msb. - destruct msb. - - rewrite wneg_WS_1. - rewrite wordToN_WS_1. - rewrite wnot_def. - unfold wneg. - - assert (Npow2 (S sz) - wordToN (WS b w) <> 0)%N. - { pose proof (wordToN_bound (WS b w)); nomega. } - assert (Npow2 (S sz) - wordToN (WS b w) < Npow2 (S sz))%N. - { apply N.sub_lt. - { apply N.lt_le_incl, wordToN_bound. } - { assert (wordToN (WS b w) <> 0)%N. - { replace 0%N with (wordToN (wzero (S sz))). - { intro Hx. - apply wordToN_inj in Hx. - rewrite Hx in Heqmsb. - rewrite wmsb_wzero in Heqmsb; discriminate. - } - { rewrite wordToN_nat. - unfold wzero; rewrite roundTrip_0; reflexivity. - } - } - nomega. - } - } - remember (Npow2 (S sz) - wordToN (WS b w))%N as n; clear Heqn. - - rewrite wordToN_NToWord_2 by nomega. - rewrite wordToN_NToWord_2 by nomega. - destruct n; [intuition idtac|]. - destruct p; cbn; reflexivity. - - - rewrite wordToN_WS_1. - destruct (wordToN (WS b w)); cbn; omega. -Qed. - -Lemma wordToZ_WS_1': - forall sz (w: word (sz + 1)), wordToZ w~1 = (2 * wordToZ w + 1)%Z. -Proof. - intro sz. - replace (sz + 1) with (S sz) by omega. - intros. - apply wordToZ_WS_1. -Qed. - -Lemma wordToZ_inj: - forall sz (w1 w2: word sz), - wordToZ w1 = wordToZ w2 -> w1 = w2. -Proof. - unfold wordToZ; intros. - remember (wmsb w1 false) as msb1. - remember (wmsb w2 false) as msb2. - destruct msb1, msb2. - - remember (wordToN (wneg w1)) as wn1. - remember (wordToN (wneg w2)) as wn2. - destruct wn1, wn2; try discriminate. - + assert (wneg w1 = wneg w2). - { apply wordToN_inj. - rewrite <-Heqwn1, <-Heqwn2; reflexivity. - } - rewrite <-wneg_idempotent with (w:= w1). - rewrite <-wneg_idempotent with (w:= w2). - rewrite H0; reflexivity. - + inversion H; subst; clear H. - assert (wneg w1 = wneg w2). - { apply wordToN_inj. - rewrite <-Heqwn1, <-Heqwn2; reflexivity. - } - rewrite <-wneg_idempotent with (w:= w1). - rewrite <-wneg_idempotent with (w:= w2). - rewrite H; reflexivity. - - remember (wordToN (wneg w1)) as wn1. - remember (wordToN w2) as wn2. - destruct wn1, wn2; try discriminate. - rewrite <-wordToN_wzero with (sz:= sz) in Heqwn1, Heqwn2. - apply wordToN_inj in Heqwn1. - apply wordToN_inj in Heqwn2. - assert (w1 = wzero sz). - { rewrite <-wneg_idempotent with (w:= w1), <-Heqwn1. - apply wzero_wneg. - } - subst; reflexivity. - - remember (wordToN w1) as wn1. - remember (wordToN (wneg w2)) as wn2. - destruct wn1, wn2; try discriminate. - rewrite <-wordToN_wzero with (sz:= sz) in Heqwn1, Heqwn2. - apply wordToN_inj in Heqwn1. - apply wordToN_inj in Heqwn2. - assert (w2 = wzero sz). - { rewrite <-wneg_idempotent with (w:= w2), <-Heqwn2. - apply wzero_wneg. - } - subst; reflexivity. - - remember (wordToN w1) as wn1. - remember (wordToN w2) as wn2. - destruct wn1, wn2; try discriminate. - + rewrite <-wordToN_wzero with (sz:= sz) in Heqwn1, Heqwn2. - rewrite Heqwn1 in Heqwn2. - apply wordToN_inj in Heqwn2; auto. - + inversion H; subst; clear H. - rewrite Heqwn1 in Heqwn2. - apply wordToN_inj in Heqwn2; auto. -Qed. - -Lemma wordToZ_wones: - forall sz, sz <> 0 -> wordToZ (wones sz) = (-1)%Z. -Proof. - induction sz; intros; [elim H; reflexivity|]. - simpl; destruct sz; [reflexivity|]. - rewrite wordToZ_WS_1. - rewrite IHsz by discriminate. - reflexivity. -Qed. - -Lemma wordToNat_eq_rect: - forall sz (w: word sz) nsz Hsz, - wordToNat (eq_rect _ word w nsz Hsz) = wordToNat w. -Proof. - intros; subst; simpl; reflexivity. -Qed. - -Lemma wordToNat_existT: - forall sz1 (w1: word sz1) sz2 (w2: word sz2) (Hsz: sz1 = sz2), - wordToNat w1 = wordToNat w2 -> - existT word _ w1 = existT word _ w2. -Proof. - intros; subst. - apply wordToNat_inj in H; subst. - reflexivity. -Qed. - -Lemma existT_wordToNat: (* Note: not axiom free *) - forall sz1 (w1: word sz1) sz2 (w2: word sz2), - existT word _ w1 = existT word _ w2 -> - wordToNat w1 = wordToNat w2. -Proof. - intros. - pose proof (eq_sigT_fst H); subst. - destruct_existT; reflexivity. -Qed. - -Lemma wordToZ_eq_rect: - forall sz (w: word sz) nsz Hsz, - wordToZ (eq_rect _ word w nsz Hsz) = wordToZ w. -Proof. - intros; subst; simpl; reflexivity. -Qed. - -Lemma wordToZ_existT: - forall sz1 (w1: word sz1) sz2 (w2: word sz2) (Hsz: sz1 = sz2), - wordToZ w1 = wordToZ w2 -> - existT word _ w1 = existT word _ w2. -Proof. - intros; subst. - apply wordToZ_inj in H; subst. - reflexivity. -Qed. - -Lemma existT_wordToZ: (* Note: not axiom free *) - forall sz1 (w1: word sz1) sz2 (w2: word sz2), - existT word _ w1 = existT word _ w2 -> - wordToZ w1 = wordToZ w2. -Proof. - intros. - pose proof (eq_sigT_fst H); subst. - destruct_existT. - reflexivity. -Qed. - -Lemma wplus_WS_0: - forall sz (w1 w2: word sz) b, WS b (w1 ^+ w2) = WS b w1 ^+ w2~0. -Proof. - intros. - unfold wplus, wordBin; intros. - rewrite wordToN_WS_0. - destruct b. - - rewrite wordToN_WS_1. - rewrite <-N.add_assoc. - rewrite N.add_comm with (n:= 1%N). - rewrite N.add_assoc. - rewrite <-N.mul_add_distr_l. - apply eq_sym, NToWord_WS_1. - - rewrite wordToN_WS_0. - rewrite <-N.mul_add_distr_l. - apply eq_sym, NToWord_WS_0. -Qed. - -Corollary wplus_WS_0': - forall sz (w1 w2: word sz) b, WS b (w1 ^+ w2) = w1~0 ^+ WS b w2. -Proof. - intros. - rewrite wplus_comm with (x:= w1). - rewrite wplus_comm with (x:= w1~0). - apply wplus_WS_0. -Qed. - -Lemma wpow2_pow2: - forall sz, wordToNat (wpow2 sz) = pow2 sz. -Proof. - induction sz; simpl; intros; [reflexivity|]. - rewrite IHsz. - omega. -Qed. - -Lemma wpow2_Npow2: - forall sz, wordToN (wpow2 sz) = Npow2 sz. -Proof. - induction sz; simpl; intros; [reflexivity|]. - rewrite IHsz; reflexivity. -Qed. - -Lemma wpow2_wneg: - forall sz, wneg (wpow2 sz) = wpow2 sz. -Proof. - induction sz; simpl; intros; [reflexivity|]. - rewrite wneg_WS_0. - rewrite IHsz; reflexivity. -Qed. - -Lemma wpow2_wmsb: - forall sz, wmsb (wpow2 sz) false = true. -Proof. - induction sz; simpl; intros; auto. -Qed. - -Lemma wmsb_wnot: - forall sz (w: word (S sz)) b1 b2, - wmsb (wnot w) b1 = negb (wmsb w b2). -Proof. - apply (induct_word_S (fun sz w => forall b1 b2, wmsb (wnot w) b1 = negb (wmsb w b2))); intros. - - reflexivity. - - simpl. apply (H true true). -Qed. - -Lemma wmsb_wneg_true: - forall sz (w: word (S sz)), - w <> wpow2 sz -> - forall b1 b2, - wmsb w b1 = true -> - wmsb (wneg w) b2 = false. -Proof. - apply (induct_word_S (fun sz w => w <> wpow2 sz -> forall b1 b2, wmsb w b1 = true -> - wmsb (^~ w) b2 = false)); intros; - [simpl in *; subst; elim H; reflexivity|]. - destruct b. - - rewrite wneg_WS_1. - rewrite wmsb_ws. - rewrite wmsb_wnot with (b2:= false). - simpl; apply negb_false_iff; assumption. - - rewrite wneg_WS_0. - eapply H with (b1 := false); eauto. - intro Hx. elim H0. - clear -Hx. - simpl; rewrite Hx; reflexivity. -Qed. - -Lemma wmsb_wneg_false: - forall sz (w: word (S sz)), - wordToNat w <> 0 -> - forall b1 b2, - wmsb w b1 = false -> - wmsb (wneg w) b2 = true. -Proof. - apply (induct_word_S (fun sz w => #w <> 0 -> forall b1 b2, wmsb w b1 = false -> - wmsb (^~ w) b2 = true)); intros; - [simpl in *; subst; elim H; reflexivity|]. - destruct b. - - rewrite wneg_WS_1. - rewrite wmsb_ws. - rewrite wmsb_ws in H1. - rewrite wmsb_wnot with (b2:= false). - apply negb_true_iff; assumption. - - rewrite wneg_WS_0. - eapply H with (b1:= false); eauto. - intro Hx; elim H0. - clear -Hx. - simpl in *; omega. -Qed. - -Lemma zext_WO_wzero: - forall n, zext WO n = wzero n. -Proof. - reflexivity. -Qed. - -Lemma wmsb_wneg_zext: (* Note: not axiom free *) - forall sz (w: word sz) b n, - n <> 0 -> wordToNat w <> 0 -> - wmsb (wneg (zext w n)) b = true. -Proof. - intros. - dependent destruction w; [elim H0; reflexivity|]. - apply wmsb_wneg_false with (b1:= false). - - rewrite <-wordToNat_zext with (n:= n0) in H0. - assumption. - - apply wmsb_zext; assumption. -Qed. - -Lemma wminus_WS_pos: - forall sz (w1 w2: word (S sz)), - wordToZ (WS true w1 ^- WS false w2) = - (2 * wordToZ (w1 ^- w2) + 1)%Z. -Proof. - unfold wminus; intros. - cbn. - rewrite wneg_WS_0. - rewrite <-wplus_WS_0. - rewrite wordToZ_WS_1. - reflexivity. -Qed. - -Lemma wminus_WS_pos': - forall sz (w1 w2: word (sz + 1)), - wordToZ (WS true w1 ^- WS false w2) = - (2 * wordToZ (w1 ^- w2) + 1)%Z. -Proof. - intro sz. - replace (sz + 1) with (S sz) by omega. - intros. - apply wminus_WS_pos. -Qed. - -Lemma wtl_combine: - forall (x: word 1) sz (y: word sz), - wtl (combine x y) = y. -Proof. - intros. - destruct (destruct_word_S x) as [v [b E]]. subst x. - rewrite (word0 v). - reflexivity. -Qed. - -Lemma extz_combine: - forall sz (w: word sz) n, extz w n = combine (natToWord n 0) w. -Proof. - reflexivity. -Qed. - -Lemma combine_assoc_existT: - forall sz1 (w1: word sz1) sz2 (w2: word sz2) sz3 (w3: word sz3), - existT word (sz1 + (sz2 + sz3)) (combine w1 (combine w2 w3)) = - existT word (sz1 + sz2 + sz3) (combine (combine w1 w2) w3). -Proof. - intros; apply EqdepFacts.eq_sigT_sig_eq. - assert (Hsz: sz1 + (sz2 + sz3) = sz1 + sz2 + sz3) by omega. - exists Hsz. - rewrite (combine_assoc w1 w2 w3 Hsz). - reflexivity. -Qed. - -Lemma sext_combine: (* Note: not axiom free *) - forall sz n (w: word (sz + n)) sz1 (w1: word sz1) - sz2 (Hsz2: sz2 <> 0) (w2: word sz2), - existT word _ w = existT word _ (combine w1 (sext w2 n)) -> - exists sw, w = sext sw n /\ existT word _ sw = existT word _ (combine w1 w2). -Proof. - intros; unfold sext in H. - remember (wmsb w2 false) as msb2; destruct msb2. - - rewrite combine_assoc_existT in H. - assert (sz = sz1 + sz2) by (apply eq_sigT_fst in H; omega); subst. - destruct_existT. - exists (combine w1 w2). - split; [|reflexivity]. - unfold sext. - dependent destruction w2; [discriminate|]. - rewrite wmsb_combine with (b2:= false) by discriminate. - rewrite <-Heqmsb2. - reflexivity. - - rewrite combine_assoc_existT in H. - assert (sz = sz1 + sz2) by (apply eq_sigT_fst in H; omega); subst. - destruct_existT. - exists (combine w1 w2). - split; [|reflexivity]. - unfold sext. - dependent destruction w2; [intuition idtac|]. - rewrite wmsb_combine with (b2:= false) by discriminate. - rewrite <-Heqmsb2. - reflexivity. -Qed. - -Lemma wplus_wzero_1: - forall sz (w: word sz), w ^+ (wzero _) = w. -Proof. - unfold wplus, wordBin; intros. - rewrite wordToN_wzero. - rewrite N.add_0_r. - apply NToWord_wordToN. -Qed. - -Lemma wplus_wzero_2: - forall sz (w: word sz), (wzero _) ^+ w = w. -Proof. - unfold wplus, wordBin; intros. - rewrite wordToN_wzero. - rewrite N.add_0_l. - apply NToWord_wordToN. -Qed. - -Lemma combine_wplus_1: - forall sl (w1: word sl) su (w2 w3: word su), - combine w1 (w2 ^+ w3) = combine w1 w2 ^+ extz w3 sl. -Proof. - dependent induction w1; intros; [reflexivity|]. - cbn; rewrite IHw1. - rewrite <-wplus_WS_0. - rewrite extz_combine; reflexivity. -Qed. - -Lemma combine_wplus_2: - forall sl (w1: word sl) su (w2 w3: word su), - combine w1 (w2 ^+ w3) = extz w2 sl ^+ combine w1 w3. -Proof. - intros. - rewrite wplus_comm. - rewrite combine_wplus_1. - apply wplus_comm. -Qed. - -Lemma existT_wplus: - forall sz (w1 w2: word sz) sz' (w3 w4: word sz'), - existT word _ w1 = existT word _ w3 -> - existT word _ w2 = existT word _ w4 -> - existT word _ (w1 ^+ w2) = existT word _ (w3 ^+ w4). -Proof. - intros. - rewrite eq_sigT_sig_eq in H; destruct H as [Hsz1 ?]. - rewrite eq_sigT_sig_eq in H0; destruct H0 as [Hsz2 ?]. - subst; do 2 rewrite <-(eq_rect_eq_dec eq_nat_dec). - reflexivity. -Qed. - -Lemma existT_wminus: - forall sz (w1 w2: word sz) sz' (w3 w4: word sz'), - existT word _ w1 = existT word _ w3 -> - existT word _ w2 = existT word _ w4 -> - existT word _ (w1 ^- w2) = existT word _ (w3 ^- w4). -Proof. - intros. - rewrite eq_sigT_sig_eq in H; destruct H as [Hsz1 ?]. - rewrite eq_sigT_sig_eq in H0; destruct H0 as [Hsz2 ?]. - subst; do 2 rewrite <-(eq_rect_eq_dec eq_nat_dec). - reflexivity. -Qed. - - -Lemma existT_sext: - forall sz1 (w1: word sz1) sz2 (w2: word sz2) n, - existT word _ w1 = existT word _ w2 -> - existT word _ (sext w1 n) = existT word _ (sext w2 n). -Proof. - intros; inversion H; reflexivity. -Qed. - -Lemma existT_extz: - forall sz1 (w1: word sz1) sz2 (w2: word sz2) n, - existT word _ w1 = existT word _ w2 -> - existT word _ (extz w1 n) = existT word _ (extz w2 n). -Proof. - intros; inversion H; reflexivity. -Qed. - -Lemma existT_wrshifta: - forall sz1 (w1: word sz1) sz2 (w2: word sz2) n, - existT word _ w1 = existT word _ w2 -> - existT word _ (wrshifta w1 n) = existT word _ (wrshifta w2 n). -Proof. - intros; inversion H; reflexivity. -Qed. - -Lemma existT_wlshift: - forall sz1 (w1: word sz1) sz2 (w2: word sz2) n, - existT word _ w1 = existT word _ w2 -> - existT word _ (wlshift w1 n) = existT word _ (wlshift w2 n). -Proof. - intros; inversion H; reflexivity. -Qed. - -Lemma eq_rect_wplus: - forall sz (w1 w2: word sz) sz' Hsz, - eq_rect sz word (w1 ^+ w2) sz' Hsz = - (eq_rect sz word w1 sz' Hsz) ^+ (eq_rect sz word w2 sz' Hsz). -Proof. - intros; subst. - eq_rect_simpl; reflexivity. -Qed. - -Lemma eq_rect_2: - forall sz (pa: word sz) sz' Heq1 Heq2, - eq_rect sz' word (eq_rect sz word pa sz' Heq1) sz Heq2 = pa. -Proof. - intros; subst. - do 2 rewrite <-(eq_rect_eq_dec eq_nat_dec). - reflexivity. -Qed. - -Lemma wzero_eq_rect: - forall sz1 sz2 Heq, - eq_rect sz1 word (wzero sz1) sz2 Heq = wzero sz2. -Proof. - intros; subst. - apply eq_sym, (eq_rect_eq_dec eq_nat_dec). -Qed. - -Lemma wrshifta_0: - forall sz (w: word sz), wrshifta w 0 = w. -Proof. - unfold wrshifta; intros; simpl. - unfold eq_rec_r, eq_rec. - unfold sext. - destruct (wmsb w false). - - cbn; rewrite combine_n_0. - rewrite eq_rect_2; reflexivity. - - cbn; rewrite combine_n_0. - rewrite eq_rect_2; reflexivity. -Qed. - -Lemma wrshifta_WO: - forall n, wrshifta WO n = WO. -Proof. - unfold wrshifta; cbn; intros. - unfold eq_rec_r, eq_rec. - rewrite wzero_eq_rect. - rewrite <-combine_wzero. - rewrite split2_combine. - reflexivity. -Qed. - -Lemma split2_WO: - forall n w, split2 n 0 w = WO. -Proof. - induction n; cbn; intros; auto. -Qed. - -Lemma sext_wzero: - forall sz n, sext (wzero sz) n = wzero (sz + n). -Proof. - unfold sext; intros. - rewrite wmsb_wzero. - apply combine_wzero. -Qed. - -Lemma wrshifta_wzero: - forall sz n, wrshifta (wzero sz) n = wzero _. -Proof. - intros. - unfold wrshifta; cbn. - rewrite sext_wzero. - unfold eq_rec_r, eq_rec. - rewrite wzero_eq_rect. - rewrite <-combine_wzero. - rewrite split2_combine. - reflexivity. -Qed. - -Lemma extz_sext: - forall sz (w: word sz) n1 n2, - existT word _ (extz (sext w n1) n2) = - existT word _ (sext (extz w n2) n1). -Proof. - dependent destruction w; cbn; intros. - - unfold wzero, extz, sext. - rewrite combine_wzero. - rewrite combine_wzero. - rewrite wmsb_wzero. - rewrite combine_wzero. - replace (n2 + 0 + n1) with (n2 + n1) by omega. - reflexivity. - - unfold wzero, extz, sext. - rewrite wmsb_combine with (b2:= false) by discriminate. - destruct (wmsb (WS b w) false); - try (rewrite <-combine_assoc_existT; reflexivity). -Qed. - -Lemma sext_WS: - forall sz (w: word (S sz)) b n, - sext (WS b w) n = WS b (sext w n). -Proof. - unfold sext; intros. - rewrite wmsb_ws. - destruct (wmsb w false); reflexivity. -Qed. - -Lemma sext_wordToZ: - forall sz n (w: word sz), - wordToZ (sext w n) = wordToZ w. -Proof. - dependent induction w; cbn; intros; [apply wordToZ_wzero|]. - dependent destruction w. - - unfold sext; simpl. - destruct b; cbn. - + rewrite wordToZ_wones by discriminate. - reflexivity. - + rewrite wordToZ_wzero; reflexivity. - - remember (WS b0 w) as ww; clear Heqww. - rewrite sext_WS. - destruct b. - + change (S n0 + n) with (S (n0 + n)) in *. - repeat rewrite wordToZ_WS_1. - rewrite IHw. - reflexivity. - + change (S n0 + n) with (S (n0 + n)) in *. - repeat rewrite wordToZ_WS_0. - rewrite IHw. - reflexivity. -Qed. - -Lemma sext_natToWord': forall sz1 sz2 n, - (2 * n < pow2 sz1)%nat -> - sext (natToWord sz1 n) sz2 = natToWord (sz1 + sz2) n. -Proof. - induction sz1; intros. - - simpl. unfold sext. simpl. unfold wzero. unfold pow2 in *. - assert (n=0) by omega. subst n. reflexivity. - - unfold sext in *. - assert (@wmsb (S sz1) (natToWord (S sz1) n) false = false) as E by - (apply wmsb_0_natToWord; assumption). - rewrite E. clear E. - simpl. unfold natToWord. f_equal. fold natToWord. - specialize (IHsz1 sz2 (Nat.div2 n)). - rewrite <- IHsz1. - + assert (@wmsb sz1 (natToWord sz1 (Nat.div2 n)) false = false) as E. { - destruct sz1. - - reflexivity. - - apply wmsb_0_natToWord. unfold pow2 in *. fold pow2 in *. - assert ((2 * Nat.div2 n <= n)%nat) by apply two_times_div2_bound. omega. - } - rewrite E. clear E. reflexivity. - + replace (pow2 (S sz1)) with (2 * (pow2 sz1)) in H. - * assert ((2 * Nat.div2 n <= n)%nat) by apply two_times_div2_bound. omega. - * reflexivity. -Qed. - -Lemma sext_natToWord: forall sz2 sz1 sz n (e: sz1 + sz2 = sz), - (2 * n < pow2 sz1)%nat -> - eq_rect (sz1 + sz2) word (sext (natToWord sz1 n) sz2) sz e = natToWord sz n. -Proof. - intros. rewrite sext_natToWord' by assumption. rewrite e. reflexivity. -Qed. - -Lemma sext_wneg_natToWord'': forall sz1 sz2 n, - pow2 sz1 <= 2 * n < pow2 (S sz1) -> - sext (natToWord sz1 n) sz2 = natToWord (sz1 + sz2) (pow2 (sz1+sz2) - (pow2 sz1 - n)). -Proof. - induction sz1; intros. - - unfold pow2 in H. omega. (* contradiction *) - - unfold sext in *. - assert (@wmsb (S sz1) (natToWord (S sz1) n) false = true) as E. { - apply wmsb_1. - rewrite wordToNat_natToWord_idempotent'; - (unfold pow2 in *; fold pow2 in *; omega). - } - rewrite E. - match goal with - | |- _ = $ ?a => remember a as b - end. - simpl. unfold natToWord. f_equal. - + subst b. rewrite mod2sub. - * rewrite mod2sub. - { replace (S sz1 + sz2) with (S (sz1 + sz2)) by omega. - simpl. - do 2 rewrite mod2_pow2_twice. - do 2 rewrite Bool.xorb_false_l. - reflexivity. - } - simpl in *. omega. - * rewrite pow2_add_mul in *. unfold pow2 in *. fold pow2 in *. - apply Nat.le_trans with (m := 2 * pow2 sz1); [omega|]. - rewrite <- mult_assoc. - apply mult_le_compat_l. - rewrite <- Nat.mul_1_r at 1. - apply mult_le_compat_l. - apply one_le_pow2. - + fold natToWord. - specialize (IHsz1 sz2 (Nat.div2 n)). - assert (Nat.div2 b = pow2 (sz1 + sz2) - (pow2 sz1 - (Nat.div2 n))) as D2. { - rewrite minus_minus. - - subst b. replace (S sz1 + sz2) with (S (sz1 + sz2)) by omega. - unfold pow2. fold pow2. - rewrite minus_minus. - * rewrite <- Nat.mul_sub_distr_l. - rewrite <- (Nat.add_comm n). - rewrite div2_plus_2. - apply Nat.add_comm. - * rewrite pow2_add_mul. clear IHsz1. unfold pow2 in *. fold pow2 in *. - split; [omega|]. - apply mult_le_compat_l. - rewrite <- Nat.mul_1_r at 1. - apply mult_le_compat_l. - apply one_le_pow2. - - unfold pow2 in H. fold pow2 in H. - split. - * pose proof (@div2_compat_lt_l (pow2 sz1) n) as P. omega. - * rewrite pow2_add_mul. clear IHsz1. - rewrite <- Nat.mul_1_r at 1. - apply mult_le_compat_l. - apply one_le_pow2. - } - rewrite D2. - destruct sz1 as [|sz1']. - * simpl in H. assert (n=1) by omega. subst n. simpl in D2. simpl. - apply wones_natToWord. - * assert (n <= S (2 * Nat.div2 n))%nat. { - destruct (even_odd_destruct n) as [[m C]|[m C]]; subst n. - - rewrite Nat.div2_double. constructor. constructor. - - replace (2 * m + 1) with (S (2 * m)) by omega. rewrite Nat.div2_succ_double. - constructor. - } - rewrite <- IHsz1. - { assert (@wmsb (S sz1') (natToWord (S sz1') (Nat.div2 n)) false = true) as F. { - apply wmsb_1_natToWord. - unfold pow2 in *. fold pow2 in *. - assert (2 * Nat.div2 n <= n)%nat by apply two_times_div2_bound. - clear -H H0 H1. - omega. } - { rewrite F. reflexivity. } - } - { assert (2 * Nat.div2 n <= n)%nat by apply two_times_div2_bound. - clear -H H0 H1. - unfold pow2 in *. fold pow2 in *. - omega. } -Qed. - -Lemma sext_wneg_natToWord': forall sz1 sz2 n, - (2 * n < pow2 sz1)%nat -> - sext (wneg (natToWord sz1 n)) sz2 = wneg (natToWord (sz1 + sz2) n). -Proof. - intros. rewrite wneg_alt. unfold wnegN. - destruct n as [|n]. - - rewrite roundTrip_0. rewrite Nat.sub_0_r. rewrite natToWord_pow2. - unfold sext. - assert (wmsb (natToWord sz1 0) false = false) as W. { - destruct sz1. - + simpl. reflexivity. - + apply wmsb_0_natToWord. assumption. - } - rewrite W. - rewrite combine_wzero. - symmetry. - apply wneg_zero'. - - rewrite sext_wneg_natToWord''. - + rewrite wneg_alt. unfold wnegN. - rewrite wordToNat_natToWord_idempotent' by omega. - rewrite wordToNat_natToWord_idempotent'. - * replace (pow2 sz1 - (pow2 sz1 - S n)) with (S n) by omega. - reflexivity. - * rewrite pow2_add_mul. - apply Nat.le_trans with (m := pow2 sz1); [omega|]. - rewrite <- Nat.mul_1_r at 1. - apply mult_le_compat_l. - apply one_le_pow2. - + rewrite wordToNat_natToWord_idempotent' by omega. - simpl. omega. -Qed. - -Lemma sext_wneg_natToWord: forall sz2 sz1 sz n (e: sz1 + sz2 = sz), - (2 * n < pow2 sz1)%nat -> - eq_rect (sz1 + sz2) word (sext (wneg (natToWord sz1 n)) sz2) sz e = wneg (natToWord sz n). -Proof. - intros. rewrite sext_wneg_natToWord' by assumption. rewrite e. reflexivity. -Qed. - -Lemma wordToNat_split1: - forall sz1 sz2 (w: word (sz1 + sz2)), - wordToNat (split1 _ _ w) = - Nat.modulo (wordToNat w) (pow2 sz1). -Proof. - induction sz1; intros; [reflexivity|]. - destruct (destruct_word_S w) as [v [b E]]. - match type of v with - | word ?x => change x with (sz1 + sz2) in * - end. - subst w. rename v into w. - simpl; rewrite IHsz1. - pose proof (zero_lt_pow2 sz1). - destruct b. - - change (pow2 sz1 + (pow2 sz1 + 0)) with (2 * pow2 sz1). - replace (S (wordToNat w * 2)) with (1 + 2 * wordToNat w) by omega. - rewrite Nat.add_mod by omega. - rewrite Nat.mul_mod_distr_l; [|omega|discriminate]. - rewrite Nat.mod_1_l by omega. - rewrite Nat.mul_comm with (n:= 2). - change (1 + wordToNat w mod pow2 sz1 * 2) with (S (wordToNat w mod pow2 sz1 * 2)). - apply eq_sym, Nat.mod_small. - assert (pow2 sz1 <> 0) by omega. - pose proof (Nat.mod_upper_bound (wordToNat w) (pow2 sz1) H0). - omega. - - change (pow2 sz1 + (pow2 sz1 + 0)) with (2 * pow2 sz1). - rewrite Nat.mul_comm with (n:= 2). - rewrite Nat.mul_mod_distr_r; [|omega|discriminate]. - reflexivity. -Qed. - -Lemma wordToNat_split2: - forall sz1 sz2 (w: word (sz1 + sz2)), - wordToNat (split2 _ _ w) = - Nat.div (wordToNat w) (pow2 sz1). -Proof. - induction sz1; intros; - [rewrite Nat.div_1_r; reflexivity|]. - destruct (destruct_word_S w) as [v [b E]]. - match type of v with - | word ?x => change x with (sz1 + sz2) in * - end. - subst w. rename v into w. - change (split2 (S sz1) sz2 (WS b w)) - with (split2 sz1 sz2 w). - rewrite IHsz1. - destruct b. - - unfold pow2; fold pow2. - replace (@wordToNat (S sz1 + sz2) w~1) - with (1 + 2 * wordToNat w) by (simpl; omega). - rewrite <-Nat.div_div; - [|discriminate|pose proof (zero_lt_pow2 sz1); omega]. - rewrite Nat.mul_comm, Nat.div_add by discriminate. - rewrite Nat.div_small with (b := 2) by omega. - reflexivity. - - unfold pow2; fold pow2. - replace (@wordToNat (S sz1 + sz2) w~0) - with (2 * wordToNat w) by (simpl; omega). - rewrite Nat.div_mul_cancel_l; - [|pose proof (zero_lt_pow2 sz1); omega|discriminate]. - reflexivity. -Qed. - -Lemma wordToNat_wrshifta: - forall sz (w: word sz) n, - wordToNat (wrshifta w n) = - Nat.div (wordToNat (sext w n)) (pow2 n). -Proof. - unfold wrshifta; intros. - rewrite wordToNat_split2. - unfold eq_rec_r, eq_rec. - rewrite wordToNat_eq_rect. - reflexivity. -Qed. - -Lemma wordToNat_combine: - forall sz1 (w1: word sz1) sz2 (w2: word sz2), - wordToNat (combine w1 w2) = - wordToNat w1 + pow2 sz1 * wordToNat w2. -Proof. - dependent induction w1; intros; [simpl; omega|]. - unfold pow2; fold pow2. - rewrite Nat.mul_comm with (n:= 2). (* to avoid [simpl] *) - simpl; destruct b. - - rewrite IHw1; simpl. - rewrite Nat.mul_comm with (n:= pow2 n * 2). - rewrite Nat.mul_assoc. - rewrite <-Nat.mul_add_distr_r. - rewrite Nat.mul_comm with (n:= pow2 n). - reflexivity. - - rewrite IHw1. - rewrite Nat.mul_comm with (n:= pow2 n * 2). - rewrite Nat.mul_assoc. - rewrite <-Nat.mul_add_distr_r. - rewrite Nat.mul_comm with (n:= pow2 n). - reflexivity. -Qed. - -Lemma wordToNat_wlshift: - forall sz (w: word sz) n, - wordToNat (wlshift w n) = - Nat.mul (Nat.modulo (wordToNat w) (pow2 (sz - n))) (pow2 n). -Proof. - intros; destruct (le_dec n sz). - - - unfold wlshift; intros. - rewrite wordToNat_split1. - unfold eq_rec_r, eq_rec. - rewrite wordToNat_eq_rect. - rewrite wordToNat_combine. - rewrite wordToNat_wzero; simpl. - replace (pow2 sz) with (pow2 (sz - n + n)) by (f_equal; omega). - rewrite pow2_add_mul. - rewrite Nat.mul_comm with (n:= pow2 (sz - n)). - rewrite Nat.mul_mod_distr_l; - [|pose proof (zero_lt_pow2 (sz - n)); omega - |pose proof (zero_lt_pow2 n); omega]. - apply Nat.mul_comm. - - - assert (n > sz)%nat by omega. - rewrite wlshift_gt by assumption. - replace (sz - n) with 0 by omega. - rewrite wordToNat_wzero; simpl; reflexivity. -Qed. - -Lemma wordToNat_extz: - forall sz (w: word sz) n, - wordToNat (extz w n) = pow2 n * wordToNat w. -Proof. - unfold extz; intros. - rewrite wordToNat_combine. - rewrite wordToNat_wzero. - reflexivity. -Qed. - -Lemma extz_is_mult_pow2: forall sz n d, - extz (natToWord sz n) d = natToWord (d + sz) (pow2 d * n). -Proof. - intros. induction d. - - unfold extz. - rewrite combine_0_n. - simpl. - f_equal. - omega. - - unfold extz in *. - change (pow2 (S d) * n) with (2 * pow2 d * n). - rewrite <- Nat.mul_assoc. - change ((S d) + sz) with (S (d + sz)) in *. - rewrite <- natToWord_times2. - simpl. - fold natToWord. - f_equal. - exact IHd. -Qed. - -Lemma extz_is_mult_pow2_neg: forall sz n d, - extz (wneg (natToWord sz n)) d = wneg (natToWord (d + sz) (pow2 d * n)). -Proof. - intros. induction d. - - unfold extz. - rewrite combine_0_n. - simpl. - f_equal. f_equal. - omega. - - unfold extz in *. - change (pow2 (S d) * n) with (2 * pow2 d * n). - rewrite <- Nat.mul_assoc. - change ((S d) + sz) with (S (d + sz)) in *. - rewrite <- natToWord_times2. - simpl. - fold natToWord. - f_equal. - rewrite wneg_WS_0. - f_equal. - exact IHd. -Qed. - -Lemma wordToNat_sext_bypass: - forall sz1 (w1: word sz1) sz2 (w2: word sz2) (Hsz: sz1 = sz2) n, - wordToNat w1 = wordToNat w2 -> - wordToNat (sext w1 n) = wordToNat (sext w2 n). -Proof. - intros; subst. - apply wordToNat_inj in H; subst. - reflexivity. -Qed. - -Lemma combine_sext: - forall sz1 (w1: word sz1) sz2 (w2: word (S sz2)) n, - existT word _ (combine w1 (sext w2 n)) = - existT word _ (sext (combine w1 w2) n). -Proof. - unfold sext; intros. - rewrite wmsb_combine with (b2:= false) by discriminate. - destruct (wmsb w2 false); apply combine_assoc_existT. -Qed. - -Lemma extz_extz: - forall sz (w: word sz) n1 n2, - existT word _ (extz (extz w n1) n2) = - existT word _ (extz w (n2 + n1)). -Proof. - unfold extz; cbn; intros. - rewrite combine_assoc_existT. - rewrite combine_wzero. - reflexivity. -Qed. - -Lemma wrshifta_extz_sext: (* Note: not axiom free *) - forall sz (w: word sz) n1 n2, - existT word _ (wrshifta (extz w (n1 + n2)) n1) = - existT word _ (sext (extz w n2) n1). -Proof. - intros. - rewrite <-extz_sext. - apply wordToNat_existT; [omega|]. - rewrite wordToNat_wrshifta. - - replace (wordToNat (sext (extz w (n1 + n2)) n1)) - with (wordToNat (sext (extz (extz w n2) n1) n1)). - - replace (wordToNat (sext (extz (extz w n2) n1) n1)) - with (wordToNat (extz (sext (extz w n2) n1) n1)) - by apply existT_wordToNat, extz_sext. - do 2 rewrite wordToNat_extz. - rewrite Nat.mul_comm, Nat.div_mul - by (pose proof (zero_lt_pow2 n1); omega). - replace (wordToNat (sext (extz w n2) n1)) - with (wordToNat (extz (sext w n1) n2)) - by apply existT_wordToNat, extz_sext. - rewrite wordToNat_extz. - reflexivity. - - apply wordToNat_sext_bypass; [omega|]. - apply existT_wordToNat. - apply extz_extz. -Qed. - -Lemma wordToNat_sext_modulo: - forall sz (w: word sz) n, - Nat.modulo (wordToNat (sext w n)) (pow2 sz) = wordToNat w. -Proof. - unfold sext; intros. - pose proof (zero_lt_pow2 sz). - destruct (wmsb w false). - - rewrite wordToNat_combine. - rewrite Nat.mul_comm, Nat.mod_add by omega. - apply Nat.mod_small. - apply wordToNat_bound. - - rewrite wordToNat_combine. - rewrite Nat.mul_comm, Nat.mod_add by omega. - apply Nat.mod_small. - apply wordToNat_bound. -Qed. - -Lemma wlshift_sext_extz: - forall sz (w: word sz) n, - existT word _ (wlshift (sext w n) n) = - existT word _ (extz w n). -Proof. - intros; apply wordToNat_existT; [omega|]. - rewrite wordToNat_wlshift. - rewrite wordToNat_extz. - replace (sz + n - n) with sz by omega. - rewrite wordToNat_sext_modulo. - apply Nat.mul_comm. -Qed. - -Lemma wlshift_combine_extz: - forall sn sl (wl: word sl) ssu (wu: word (ssu + sn)), - existT word (sl + (ssu + sn)) (wlshift (combine wl wu) sn) = - existT word (sn + (sl + ssu)) (extz (combine wl (split1 ssu _ wu)) sn). -Proof. - intros; apply wordToNat_existT; [omega|]. - rewrite wordToNat_wlshift. - rewrite wordToNat_combine. - rewrite wordToNat_extz. - rewrite wordToNat_combine. - rewrite wordToNat_split1. - - replace (sl + (ssu + sn) - sn) with (sl + ssu) by omega. - rewrite Nat.mul_comm; f_equal. - rewrite pow2_add_mul. - pose proof (zero_lt_pow2 sl). - pose proof (zero_lt_pow2 ssu). - rewrite Nat.mod_mul_r; try omega. - rewrite Nat.mul_comm with (n:= pow2 sl) at 1. - rewrite Nat.mod_add; [|omega]. - rewrite Nat.mod_small by apply wordToNat_bound. - do 3 f_equal. - rewrite Nat.mul_comm, Nat.div_add; [|omega]. - rewrite Nat.div_small by apply wordToNat_bound. - reflexivity. -Qed. - -Lemma extz_sext_eq_rect: - forall sz (w: word sz) n1 n2 nsz Hnsz1, - exists Hnsz2, - eq_rect (n2 + (sz + n1)) word (extz (sext w n1) n2) nsz Hnsz1 = - eq_rect (n2 + sz + n1) word (sext (extz w n2) n1) nsz Hnsz2. -Proof. - intros; subst; simpl. - assert (Hsz: n2 + sz + n1 = n2 + (sz + n1)) by omega. - exists Hsz. - pose proof (extz_sext w n1 n2). - pose proof (eq_sigT_snd H). - rewrite <-H0. - eq_rect_simpl. - reflexivity. -Qed. - -Lemma sext_zero: - forall n m, sext (natToWord n 0) m = natToWord _ 0. -Proof. - unfold sext; intros. - rewrite wmsb_wzero. - rewrite combine_wzero. - reflexivity. -Qed. - -Lemma sext_split1: - forall sz (w: word sz) n, - split1 sz _ (sext w n) = w. -Proof. - unfold sext; intros. - destruct (wmsb w false); apply split1_combine. -Qed. - -Lemma sext_sext: - forall sz (w: word sz) n1 n2, - existT word _ (sext w (n1 + n2)) = existT word _ (sext (sext w n1) n2). -Proof. - unfold sext; intros. - remember (wmsb w false) as wmsb; destruct wmsb. - - destruct n1 as [|n1]. - + cbn; rewrite wmsb_combine_WO, <-Heqwmsb. - rewrite <-combine_assoc_existT. - reflexivity. - + rewrite wmsb_combine with (b2:= false) by discriminate. - rewrite wmsb_wones. - rewrite <-combine_assoc_existT. - rewrite combine_wones. - reflexivity. - - destruct n1 as [|n1]. - + cbn; rewrite wmsb_combine_WO, <-Heqwmsb. - rewrite <-combine_assoc_existT. - reflexivity. - + rewrite wmsb_combine with (b2:= false) by discriminate. - rewrite wmsb_wzero. - rewrite <-combine_assoc_existT. - rewrite combine_wzero. - reflexivity. -Qed. - -Lemma wneg_wordToN: - forall sz (w: word sz), - wordToN w <> 0%N -> - wordToN (wneg w) = (Npow2 sz - wordToN w)%N. -Proof. - unfold wneg; intros. - rewrite wordToN_NToWord_2. - - reflexivity. - - pose proof (wordToN_bound w). - nomega. -Qed. - -Lemma Nmul_two: - forall n, (n + n = 2 * n)%N. -Proof. - intros. - destruct n; simpl; auto. - rewrite Pos.add_diag. - reflexivity. -Qed. - -Lemma wmsb_false_bound: - forall sz (w: word (S sz)), - wmsb w false = false -> (wordToN w < Npow2 sz)%N. -Proof. - apply (induct_word_S (fun sz w => wmsb w false = false -> (wordToN w < Npow2 sz)%N)); - [simpl; intros; subst; nomega|]. - intros; rewrite Npow2_S, Nmul_two. - specialize (H H0). - destruct b. - - rewrite wordToN_WS_1. - rewrite N.add_comm. - apply N.mul_2_mono_l; auto. - - rewrite wordToN_WS_0. - apply N.mul_lt_mono_pos_l; [nomega|]. - assumption. -Qed. - -Lemma wmsb_true_bound: - forall sz (w: word (S sz)), - wmsb w false = true -> (Npow2 sz <= wordToN w)%N. -Proof. - apply (induct_word_S (fun sz w => wmsb w false = true -> (Npow2 sz <= wordToN w)%N)); - [simpl; intros; subst; reflexivity|]. - intros; rewrite Npow2_S, Nmul_two. - specialize (H H0). - destruct b. - - rewrite wordToN_WS_1. - apply N.mul_le_mono_nonneg_l with (p:= 2%N) in H; [|compute; discriminate]. - rewrite N.add_1_r. - apply N.le_le_succ_r. - assumption. - - rewrite wordToN_WS_0. - apply N.mul_le_mono_nonneg_l; [compute; discriminate|]. - assumption. -Qed. - -Lemma ZToWord_wordToZ: - forall sz (w: word sz), ZToWord sz (wordToZ w) = w. -Proof. - unfold ZToWord, wordToZ; intros. - remember (wmsb w false) as msb; destruct msb. - - remember (wordToN (wneg w)) as ww. - destruct ww. - + assert (wneg w = wzero _). - { apply wordToN_inj; rewrite <-Heqww. - rewrite wordToN_nat. - rewrite roundTrip_0. - reflexivity. - } - rewrite wzero'_def. - rewrite <-wneg_idempotent, H. - apply eq_sym, wzero_wneg. - + assert (wneg w = NToWord _ (N.pos p)). - { apply wordToN_inj; rewrite Heqww. - rewrite NToWord_wordToN. - reflexivity. - } - rewrite <-wneg_idempotent, H. - reflexivity. - - remember (wordToN w) as ww. - destruct ww. - + assert (w = wzero _); subst. - { apply wordToN_inj; rewrite <-Heqww. - rewrite wordToN_nat. - rewrite roundTrip_0. - reflexivity. - } - apply wzero'_def. - + assert (w = NToWord _ (N.pos p)); subst. - { apply wordToN_inj; rewrite Heqww. - rewrite NToWord_wordToN. - reflexivity. - } - reflexivity. -Qed. - -Lemma wordToZ_ZToWord: - forall z sz, - (- Z.of_nat (pow2 sz) <= z < Z.of_nat (pow2 sz))%Z -> - wordToZ (ZToWord (S sz) z) = z. -Proof. - unfold wordToZ, ZToWord; intros. - destruct z. - - rewrite wmsb_wzero'. - rewrite wordToN_wzero'. - reflexivity. - - - rewrite posToWord_nat. - remember (wmsb (natToWord (S sz) (Pos.to_nat p)) false) as msb. - destruct msb. - + exfalso. - simpl in H; destruct H. - apply eq_sym, wmsb_true_bound in Heqmsb. - rewrite <-positive_N_nat, <-NToWord_nat in Heqmsb. - rewrite <-positive_nat_Z in H0. - apply Nat2Z.inj_lt in H0. - rewrite <-positive_N_nat, <-Npow2_nat in H0. - apply Nlt_in in H0. - pose proof (wordToN_NToWord (S sz) (N.pos p)). - destruct H1 as [k [? ?]]. - rewrite H1 in Heqmsb. - assert (N.pos p - k * Npow2 (S sz) <= N.pos p)%N by apply N.le_sub_l. - assert (Npow2 sz <= N.pos p)%N by (etransitivity; eassumption). - apply N.le_ngt in H4; auto. - + rewrite wordToN_nat, wordToNat_natToWord_2. - * rewrite positive_nat_N; reflexivity. - * rewrite <-Npow2_nat, <-positive_N_nat. - apply Nlt_out. - destruct H. - rewrite <-N2Z.inj_pos, <-N_nat_Z in H0. - apply Nat2Z.inj_lt in H0. - rewrite <-Npow2_nat in H0. - apply Nlt_in. - rewrite Npow2_S, N2Nat.inj_add. - omega. - - - rewrite wneg_idempotent. - rewrite posToWord_nat. - remember (wmsb (wneg (natToWord (S sz) (Pos.to_nat p))) false) as msb. - destruct msb. - + rewrite wordToN_nat, wordToNat_natToWord_2. - * rewrite positive_nat_N; reflexivity. - * rewrite <-Npow2_nat, <-positive_N_nat. - apply Nlt_out. - destruct H. - apply Z.opp_le_mono in H. - rewrite Pos2Z.opp_neg, Z.opp_involutive in H. - rewrite <-N2Z.inj_pos, <-N_nat_Z in H. - apply Nat2Z.inj_le in H. - rewrite <-Npow2_nat in H. - apply Nlt_in. - rewrite Npow2_S, N2Nat.inj_add. - assert (N.to_nat (Npow2 sz) > 0)%nat by (rewrite Npow2_nat; apply pow2_zero). - omega. - + exfalso. - simpl in H. - apply eq_sym, wmsb_false_bound in Heqmsb. - rewrite wneg_wordToN in Heqmsb. - * rewrite Npow2_S in Heqmsb. - rewrite <-N.add_0_r in Heqmsb. - rewrite <-N.add_sub_assoc in Heqmsb. - { apply N.add_lt_mono_l in Heqmsb. - exfalso; eapply N.nlt_0_r; eauto. - } - { destruct H. - apply Z.opp_le_mono in H. - rewrite Pos2Z.opp_neg, Z.opp_involutive in H. - rewrite <-N2Z.inj_pos, <-N_nat_Z in H. - apply Nat2Z.inj_le in H. - rewrite positive_N_nat in H. - rewrite <-positive_N_nat, <-NToWord_nat. - pose proof (wordToN_NToWord (S sz) (N.pos p)). - destruct H1 as [k [? ?]]; rewrite H1. - etransitivity; [apply N.le_sub_l|]. - rewrite <-Npow2_nat in H. - rewrite <-positive_N_nat in H. - unfold N.le; rewrite N2Nat.inj_compare. - apply nat_compare_le; auto. - } - * intro Hx. - replace 0%N with (wordToN (wzero (S sz))) in Hx by apply wordToN_wzero. - apply wordToN_inj in Hx. - assert (wordToNat (natToWord (S sz) (Pos.to_nat p)) = 0) - by (rewrite Hx; apply wordToNat_wzero). - rewrite wordToNat_natToWord_2 in H0. - { clear -H0. - induction p; simpl in H0; try discriminate. - elim IHp; rewrite Pos2Nat.inj_xO in H0; omega. - } - { destruct H. - apply Z.opp_le_mono in H. - rewrite Pos2Z.opp_neg, Z.opp_involutive in H. - rewrite <-N2Z.inj_pos, <-N_nat_Z in H. - apply Nat2Z.inj_le in H. - rewrite positive_N_nat in H. - simpl. - pose proof (pow2_zero sz). - omega. - } -Qed. - -Lemma wordToZ_wordToN: - forall sz (w: word sz), - wordToZ w = (Z.of_N (wordToN w) - Z.of_N (if wmsb w false then Npow2 sz else 0))%Z. -Proof. - unfold wordToZ; intros. - remember (wmsb w false) as msb; destruct msb; - [|simpl; rewrite Z.sub_0_r; reflexivity]. - destruct (weq w (wzero _)); subst; - [rewrite wmsb_wzero in Heqmsb; discriminate|]. - rewrite wneg_wordToN. - - pose proof (wordToN_bound w). - replace (Z.of_N (wordToN w) - Z.of_N (Npow2 sz))%Z - with (- (Z.of_N (Npow2 sz) - Z.of_N (wordToN w)))%Z by omega. - rewrite <-N2Z.inj_sub by (apply N.lt_le_incl; assumption). - clear; destruct (Npow2 sz - wordToN w)%N; reflexivity. - - intro Hx; elim n. - rewrite <-wordToN_wzero with (sz:= sz) in Hx. - apply wordToN_inj in Hx; auto. -Qed. - -Lemma ZToWord_Z_of_N: - forall sz n, - ZToWord sz (Z.of_N n) = NToWord sz n. -Proof. - unfold ZToWord, NToWord; intros. - destruct n; reflexivity. -Qed. - -Lemma ZToWord_Z_of_nat: forall sz x, ZToWord sz (Z.of_nat x) = natToWord sz x. -Proof. - intros. - rewrite <- nat_N_Z. - rewrite ZToWord_Z_of_N. - rewrite NToWord_nat. - rewrite Nnat.Nat2N.id. - reflexivity. -Qed. - -Lemma natToWord_Z_to_nat: forall sz n, - (0 <= n)%Z -> - natToWord sz (Z.to_nat n) = ZToWord sz n. -Proof. - intros. rewrite <- ZToWord_Z_of_nat. - rewrite Z2Nat.id by assumption. - reflexivity. -Qed. - -Lemma ZToWord_sz0: forall z, ZToWord 0 z = $0. -Proof. - intros. unfold ZToWord. destruct z; try rewrite posToWord_sz0; reflexivity. -Qed. - -Lemma natToWord_pow2_add: - forall sz n, - natToWord sz (n + pow2 sz) = natToWord sz n. -Proof. - induction sz; intros; [reflexivity|]. - unfold natToWord, pow2; fold natToWord pow2. - rewrite drop_mod2_add, div2_plus_2, IHsz. - reflexivity. -Qed. - -Lemma nat_add_pow2_wzero: - forall sz n1 n2, - n1 + n2 = pow2 sz -> - natToWord sz n1 ^+ natToWord sz n2 = wzero sz. -Proof. - intros. - rewrite <-natToWord_plus, H. - rewrite natToWord_pow2. - reflexivity. -Qed. - -Lemma Npos_Npow2_wzero: - forall sz p1 p2, - N.pos (p1 + p2) = Npow2 sz -> - posToWord sz p1 ^+ posToWord sz p2 = wzero sz. -Proof. - intros. - do 2 rewrite posToWord_nat. - assert (Pos.to_nat p1 + Pos.to_nat p2 = pow2 sz). - { rewrite <-Pos2Nat.inj_add, <-Npow2_nat. - rewrite <-positive_N_nat. - rewrite H; reflexivity. - } - apply nat_add_pow2_wzero; auto. -Qed. - -Lemma ZToWord_Npow2_sub: - forall sz z, - ZToWord sz (z - Z.of_N (Npow2 sz)) = ZToWord sz z. -Proof. - unfold ZToWord; intros. - remember (z - Z.of_N (Npow2 sz))%Z as zz. - destruct z. - - destruct zz. - + assert (Z.of_N (Npow2 sz) = 0)%Z by omega. - change 0%Z with (Z.of_N 0%N) in H. - apply N2Z.inj in H. - exfalso; eapply Npow2_not_zero; eauto. - + pose proof (N2Z.is_nonneg (Npow2 sz)). - destruct (Z.of_N (Npow2 sz)); simpl in Heqzz, H; - try discriminate. - pose proof (Pos2Z.neg_is_neg p0); omega. - + assert (Z.of_N (Npow2 sz) = Z.pos p). - { rewrite Z.sub_0_l, <-Pos2Z.opp_pos in Heqzz. - apply Z.opp_inj in Heqzz; auto. - } - rewrite <-N2Z.inj_pos in H. - apply N2Z.inj in H. - rewrite posToWord_nat, <-positive_N_nat, <-H. - rewrite Npow2_nat, natToWord_pow2. - rewrite wzero_wneg. - apply eq_sym, wzero'_def. - - - destruct zz. - + assert (Z.of_N (Npow2 sz) = Z.pos p) by omega. - rewrite <-N2Z.inj_pos in H. - apply N2Z.inj in H. - rewrite posToWord_nat, <-positive_N_nat, <-H. - rewrite Npow2_nat, natToWord_pow2. - apply wzero'_def. - + assert (Z.pos p = Z.pos p0 + Z.of_N (Npow2 sz))%Z by omega. - do 2 rewrite <-N2Z.inj_pos in H. - rewrite <-N2Z.inj_add in H. - apply N2Z.inj in H. - apply eq_sym. - do 2 rewrite posToWord_nat, <-positive_N_nat. - rewrite H, N2Nat.inj_add, Npow2_nat. - apply natToWord_pow2_add. - + assert (Z.pos p - Z.neg p0 = Z.of_N (Npow2 sz))%Z by omega. - simpl in H. - remember (Npow2 sz) as n; destruct n; - [exfalso; eapply Npow2_not_zero; eauto|]. - rewrite N2Z.inj_pos in H; inversion H; subst; clear H. - apply eq_sym, sub_0_eq. - rewrite wminus_def, wneg_idempotent. - apply Npos_Npow2_wzero; auto. - - - destruct zz. - + assert (Z.neg p = Z.of_N (Npow2 sz))%Z by omega. - pose proof (N2Z.is_nonneg (Npow2 sz)). - rewrite <-H in H0. - pose proof (Pos2Z.neg_is_neg p); omega. - + assert (Z.neg p = Z.pos p0 + Z.of_N (Npow2 sz))%Z by omega. - pose proof (N2Z.is_nonneg (Npow2 sz)). - destruct (Z.of_N (Npow2 sz)); simpl in H; - try discriminate. - pose proof (Pos2Z.neg_is_neg p1); omega. - + assert (Pos.to_nat p0 = Pos.to_nat p + pow2 sz). - { rewrite <-Npow2_nat. - do 2 rewrite <-positive_N_nat. - rewrite <-N2Nat.inj_add. - f_equal. - pose proof (N2Z.is_nonneg (Npow2 sz)). - remember (Z.of_N (Npow2 sz)) as z; destruct z. - { change 0%Z with (Z.of_N 0) in Heqz. - apply N2Z.inj in Heqz. - exfalso; eapply Npow2_not_zero; eauto. - } - { simpl in Heqzz; inversion Heqzz; subst. - rewrite <-N2Z.inj_pos in Heqz. - apply N2Z.inj in Heqz. - rewrite <-Heqz. - reflexivity. - } - { pose proof (Zlt_neg_0 p1); omega. } - } - f_equal. - do 2 rewrite posToWord_nat. - rewrite H. - apply natToWord_pow2_add. -Qed. - -Lemma wplus_wplusZ: - forall sz (w1 w2: word sz), - w1 ^+ w2 = wplusZ w1 w2. -Proof. - unfold wplus, wplusZ, wordBin, wordBinZ; intros. - do 2 rewrite wordToZ_wordToN. - match goal with - | [ |- context[(?z1 - ?z2 + (?z3 - ?z4))%Z] ] => - replace (z1 - z2 + (z3 - z4))%Z with (z1 + z3 - z2 - z4)%Z by omega - end. - rewrite <-N2Z.inj_add. - destruct (wmsb w1 false); destruct (wmsb w2 false). - - simpl; do 2 rewrite ZToWord_Npow2_sub. - apply eq_sym, ZToWord_Z_of_N. - - simpl; rewrite Z.sub_0_r, ZToWord_Npow2_sub. - apply eq_sym, ZToWord_Z_of_N. - - simpl; rewrite Z.sub_0_r, ZToWord_Npow2_sub. - apply eq_sym, ZToWord_Z_of_N. - - simpl; do 2 rewrite Z.sub_0_r. - apply eq_sym, ZToWord_Z_of_N. -Qed. - -Lemma ZToWord_Npow2_sub_k : forall (sz : nat) (z : Z) (k: nat), - ZToWord sz (z - Z.of_nat k * Z.of_N (Npow2 sz)) = ZToWord sz z. -Proof. - intros. induction k. - - simpl. f_equal. omega. - - rewrite <- IHk. - replace (z - Z.of_nat (S k) * Z.of_N (Npow2 sz))%Z - with ((z - Z.of_nat k * Z.of_N (Npow2 sz)) - Z.of_N (Npow2 sz))%Z by nia. - apply ZToWord_Npow2_sub. -Qed. - -Lemma ZToWord_Npow2_add_k : forall (sz : nat) (z : Z) (k: nat), - ZToWord sz (z + Z.of_nat k * Z.of_N (Npow2 sz)) = ZToWord sz z. -Proof. - intros. - replace z with (z + Z.of_nat k * Z.of_N (Npow2 sz) - Z.of_nat k * Z.of_N (Npow2 sz))%Z at 2 - by omega. - symmetry. - apply ZToWord_Npow2_sub_k. -Qed. - -Lemma ZToWord_Npow2_sub_z : forall (sz : nat) (z : Z) (k: Z), - ZToWord sz (z - k * Z.of_N (Npow2 sz)) = ZToWord sz z. -Proof. - intros. destruct k. - - simpl. f_equal. omega. - - rewrite <- positive_nat_Z. apply ZToWord_Npow2_sub_k. - - rewrite <- Pos2Z.opp_pos. - replace (z - - Z.pos p * Z.of_N (Npow2 sz))%Z - with (z + Z.pos p * Z.of_N (Npow2 sz))%Z by nia. - rewrite <- positive_nat_Z. apply ZToWord_Npow2_add_k. -Qed. - -Lemma wordToZ_ZToWord': forall sz w, - exists k, wordToZ (ZToWord sz w) = (w - k * Z.of_N (Npow2 sz))%Z. -Proof. - intros. - destruct sz. - - simpl. exists w%Z. rewrite ZToWord_sz0. rewrite wordToZ_wzero. omega. - - exists ((w + Z.of_nat (pow2 sz)) / Z.of_N (Npow2 (S sz)))%Z. - erewrite <- ZToWord_Npow2_sub_z. - rewrite wordToZ_ZToWord. - + reflexivity. - + replace w with ((- Z.of_nat (pow2 sz)) + (w + Z.of_nat (pow2 sz)))%Z at 1 3 by omega. - rewrite <- Z.add_sub_assoc. - replace (Z.of_N (Npow2 (S sz))) with (2 * Z.of_nat (pow2 sz))%Z. - * remember (Z.of_nat (pow2 sz)) as M. - assert (M > 0)%Z. { - subst. destruct (pow2 sz) eqn: E. - - exfalso. eapply pow2_ne_zero. exact E. - - simpl. constructor. - } - rewrite <- Zdiv.Zmod_eq_full by omega. - pose proof (Zdiv.Z_mod_lt (w + M) (2 * M)). omega. - * rewrite <- Npow2_nat. rewrite N_nat_Z. - rewrite Npow2_S. rewrite N2Z.inj_add. omega. -Qed. - -Lemma ZToWord_plus: forall sz a b, ZToWord sz (a + b) = ZToWord sz a ^+ ZToWord sz b. -Proof. - destruct sz as [|sz]; intros n m; intuition. - rewrite wplus_wplusZ. - unfold wplusZ, wordBinZ. - destruct (wordToZ_ZToWord' (S sz) n) as [k1 D1]. - destruct (wordToZ_ZToWord' (S sz) m) as [k2 D2]. - rewrite D1. - rewrite D2. - replace (n - k1 * Z.of_N (Npow2 (S sz)) + (m - k2 * Z.of_N (Npow2 (S sz))))%Z - with (n + m - (k1 + k2) * Z.of_N (Npow2 (S sz)))%Z by nia. - symmetry. - apply ZToWord_Npow2_sub_z. -Qed. - -Lemma else_0_to_ex_N: forall (b: bool) (a: N), - exists k, (if b then a else 0%N) = (k * a)%N. -Proof. - intros. destruct b. - - exists 1%N. nia. - - exists 0%N. reflexivity. -Qed. - -Local Lemma wmultZ_helper: forall a b k1 k2 p, - ((a - k1 * p) * (b - k2 * p) = a * b - (k1 * b + k2 * a - k1 * k2 * p) * p)%Z. -Proof. intros. nia. Qed. - -Lemma wmult_wmultZ: forall (sz : nat) (w1 w2 : word sz), w1 ^* w2 = wmultZ w1 w2. -Proof. - unfold wmultZ, wmult, wordBinZ, wordBin. intros. - do 2 rewrite wordToZ_wordToN. - destruct (else_0_to_ex_N (wmsb w1 false) (Npow2 sz)) as [k1 E1]. rewrite E1. clear E1. - destruct (else_0_to_ex_N (wmsb w2 false) (Npow2 sz)) as [k2 E2]. rewrite E2. clear E2. - do 2 rewrite N2Z.inj_mul. - rewrite wmultZ_helper. - rewrite <- N2Z.inj_mul. - rewrite ZToWord_Npow2_sub_z. - rewrite ZToWord_Z_of_N. - reflexivity. -Qed. - -Lemma ZToWord_mult: forall sz a b, ZToWord sz (a * b) = ZToWord sz a ^* ZToWord sz b. -Proof. - intros. rewrite wmult_wmultZ. unfold wmultZ, wordBinZ. - destruct (wordToZ_ZToWord' sz a) as [k1 D1]. rewrite D1. clear D1. - destruct (wordToZ_ZToWord' sz b) as [k2 D2]. rewrite D2. clear D2. - rewrite wmultZ_helper. - symmetry. - apply ZToWord_Npow2_sub_z. -Qed. - -Lemma ZToWord_0: forall sz, ZToWord sz 0 = wzero sz. -Proof. - intros. unfold ZToWord. apply wzero'_def. -Qed. - -Lemma wordToZ_wplus_bound: - forall sz (w1 w2: word (S sz)), - (- Z.of_nat (pow2 sz) <= wordToZ w1 + wordToZ w2 < Z.of_nat (pow2 sz))%Z -> - (wordToZ w1 + wordToZ w2 = wordToZ (w1 ^+ w2))%Z. -Proof. - intros. - rewrite wplus_wplusZ. - unfold wplusZ, wordBinZ. - remember (wordToZ w1 + wordToZ w2)%Z as z; clear Heqz. - apply eq_sym, wordToZ_ZToWord; assumption. -Qed. - -Lemma wordToZ_wplus_bound': - forall sz (w1 w2: word sz), - sz <> 0 -> - (- Z.of_nat (pow2 (pred sz)) <= wordToZ w1 + wordToZ w2 < Z.of_nat (pow2 (pred sz)))%Z -> - (wordToZ w1 + wordToZ w2 = wordToZ (w1 ^+ w2))%Z. -Proof. - intros. - destruct sz; [exfalso; auto|clear H]. - apply wordToZ_wplus_bound; auto. -Qed. - -Lemma wordToZ_size': - forall sz (w: word (S sz)), - (- Z.of_nat (pow2 sz) <= wordToZ w < Z.of_nat (pow2 sz))%Z. -Proof. - unfold wordToZ; intros. - remember (wmsb w false) as msb; destruct msb. - - destruct (weq w (wpow2 _)). - + subst; rewrite wpow2_wneg. - rewrite wpow2_Npow2. - remember (Npow2 sz) as np. - destruct np; [exfalso; eapply Npow2_not_zero; eauto|]. - split. - * rewrite <-Pos2Z.opp_pos, <-N2Z.inj_pos. - rewrite Heqnp. - rewrite <-Npow2_nat. - rewrite N_nat_Z. - reflexivity. - * etransitivity. - { apply Pos2Z.neg_is_neg. } - { change 0%Z with (Z.of_nat 0). - apply Nat2Z.inj_lt. - apply zero_lt_pow2. - } - + assert (wordToN (wneg w) < Npow2 sz)%N. - { apply wmsb_false_bound. - eapply wmsb_wneg_true; eauto. - } - remember (wordToN (wneg w)) as ww; clear Heqww. - destruct ww; simpl. - * split; try omega. - change 0%Z with (Z.of_nat 0). - apply Nat2Z.inj_lt. - apply zero_lt_pow2. - * split. - { rewrite <-Pos2Z.opp_pos, <-N2Z.inj_pos. - rewrite <-Npow2_nat. - rewrite N_nat_Z. - rewrite <-Z.opp_le_mono. - apply N2Z.inj_le. - apply N.lt_le_incl. - assumption. - } - { etransitivity. - { apply Pos2Z.neg_is_neg. } - { change 0%Z with (Z.of_nat 0). - apply Nat2Z.inj_lt. - apply zero_lt_pow2. - } - } - - apply eq_sym, wmsb_false_bound in Heqmsb. - destruct (wordToN w); simpl. - * split; try omega. - change 0%Z with (Z.of_nat 0). - apply Nat2Z.inj_lt. - apply zero_lt_pow2. - * split. - { etransitivity. - { apply Z.opp_nonpos_nonneg. - change 0%Z with (Z.of_nat 0). - apply Nat2Z.inj_le. - pose proof (zero_lt_pow2 sz); omega. - } - { pose proof (Pos2Z.is_pos p); omega. } - } - { rewrite <-N2Z.inj_pos. - rewrite <-Npow2_nat. - rewrite N_nat_Z. - apply N2Z.inj_lt. - assumption. - } -Qed. - -Lemma wordToZ_size: - forall sz (w: word (S sz)), - (Z.abs (wordToZ w) <= Z.of_nat (pow2 sz))%Z. -Proof. - intros. - pose proof (wordToZ_size' w). - destruct H. - apply Z.abs_le. - split; omega. -Qed. - -Lemma wneg_wzero: - forall sz (w: word sz), wneg w = wzero sz -> w = wzero sz. -Proof. - intros. - pose proof (wminus_inv w). - rewrite H in H0. - rewrite wplus_comm, wplus_unit in H0; subst. - reflexivity. -Qed. - -Lemma wmsb_false_pos: - forall sz (w: word sz), - wmsb w false = false <-> (wordToZ w >= 0)%Z. -Proof. - unfold wordToZ; split; intros. - - rewrite H. - destruct (wordToN w). - + omega. - + pose proof (Zgt_pos_0 p); omega. - - remember (wmsb w false) as b; destruct b; auto. - remember (wordToN (wneg w)) as n; destruct n. - + replace 0%N with (wordToN (wzero sz)) in Heqn. - * apply wordToN_inj in Heqn. - apply eq_sym, wneg_wzero in Heqn; subst. - rewrite wmsb_wzero in Heqb; discriminate. - * rewrite <-wzero'_def. - apply wordToN_wzero'. - + exfalso; pose proof (Zlt_neg_0 p); omega. -Qed. - -Lemma wmsb_true_neg: - forall sz (w: word sz), - wmsb w false = true <-> (wordToZ w < 0)%Z. -Proof. - unfold wordToZ; split; intros. - - rewrite H. - remember (wordToN (wneg w)) as n; destruct n. - + replace 0%N with (wordToN (wzero sz)) in Heqn. - * apply wordToN_inj in Heqn. - apply eq_sym, wneg_wzero in Heqn; subst. - rewrite wmsb_wzero in H; discriminate. - * rewrite <-wzero'_def. - apply wordToN_wzero'. - + pose proof (Zlt_neg_0 p); omega. - - remember (wmsb w false) as b; destruct b; auto. - remember (wordToN w) as n; destruct n. - + omega. - + pose proof (Zgt_pos_0 p); omega. -Qed. - -Lemma wordToZ_distr_diff_wmsb: - forall sz (w1 w2: word sz), - wmsb w1 false = negb (wmsb w2 false) -> - wordToZ (w1 ^+ w2) = (wordToZ w1 + wordToZ w2)%Z. -Proof. - intros. - destruct sz; - [rewrite (shatter_word w1), (shatter_word w2); reflexivity|]. - eapply eq_sym, wordToZ_wplus_bound. - pose proof (wordToZ_size' w1). - pose proof (wordToZ_size' w2). - remember (wmsb w1 false) as msb1; destruct msb1. - - apply eq_sym, wmsb_true_neg in Heqmsb1. - apply eq_sym, negb_true_iff, wmsb_false_pos in H. - destruct H0, H1. - split; omega. - - apply eq_sym, wmsb_false_pos in Heqmsb1. - apply eq_sym, negb_false_iff, wmsb_true_neg in H. - destruct H0, H1. - split; omega. -Qed. - -Lemma sext_wplus_wordToZ_distr: - forall sz (w1 w2: word sz) n, - n <> 0 -> wordToZ (sext w1 n ^+ sext w2 n) = - (wordToZ (sext w1 n) + wordToZ (sext w2 n))%Z. -Proof. - intros. - destruct n; [exfalso; auto|clear H]. - apply eq_sym, wordToZ_wplus_bound'; [omega|]. - - do 2 rewrite sext_wordToZ. - destruct sz. - - rewrite (shatter_word w1), (shatter_word w2). - cbn; split; try (pose proof (pow2_zero n); omega). - - replace (pred (S sz + S n)) with (S (sz + n)) by omega. - pose proof (wordToZ_size' w1); destruct H. - pose proof (wordToZ_size' w2); destruct H1. - split. - + rewrite pow2_S_z. - etransitivity; [|apply Z.add_le_mono; eassumption]. - rewrite <-Z.add_diag, Z.opp_add_distr. - apply Z.add_le_mono; - rewrite <-Z.opp_le_mono; apply Nat2Z.inj_le, pow2_le; omega. - + rewrite pow2_S_z. - eapply Z.lt_le_trans; [apply Z.add_lt_mono; eassumption|]. - rewrite <-Z.add_diag. - apply Z.add_le_mono; apply Nat2Z.inj_le, pow2_le; omega. -Qed. - -Lemma sext_wplus_wordToZ_distr_existT: (* Note: not axiom free *) - forall sz (w1 w2: word sz) ssz (sw1 sw2: word ssz) n, - existT word _ w1 = existT word _ (sext sw1 n) -> - existT word _ w2 = existT word _ (sext sw2 n) -> - n <> 0 -> wordToZ (w1 ^+ w2) = (wordToZ w1 + wordToZ w2)%Z. -Proof. - intros. - assert (sz = ssz + n) by (apply eq_sigT_fst in H; auto); subst. - destruct_existT. - apply sext_wplus_wordToZ_distr; auto. -Qed. - -Lemma split1_existT: (* Note: not axiom free *) - forall n sz1 (w1: word (n + sz1)) sz2 (w2: word (n + sz2)), - existT word _ w1 = existT word _ w2 -> - split1 n _ w1 = split1 n _ w2. -Proof. - intros. - assert (sz1 = sz2) by (apply eq_sigT_fst in H; omega); subst. - destruct_existT. - reflexivity. -Qed. - -Lemma word_combinable: - forall sz1 sz2 (w: word (sz1 + sz2)), - exists w1 w2, w = combine w1 w2. -Proof. - intros. - exists (split1 _ _ w), (split2 _ _ w). - apply eq_sym, combine_split. -Qed. - -Lemma split1_combine_existT: (* Note: not axiom free *) - forall sz n (w: word (n + sz)) sl (wl: word (n + sl)) su (wu: word su), - existT word _ w = existT word _ (combine wl wu) -> - split1 n _ w = split1 n _ wl. -Proof. - intros. - pose proof (word_combinable _ _ w). - destruct H0 as [? [? ?]]; subst. - pose proof (word_combinable _ _ wl). - destruct H0 as [? [? ?]]; subst. - assert (sz = sl + su) by (apply eq_sigT_fst in H; omega); subst. - pose proof (word_combinable _ _ x0). - destruct H0 as [? [? ?]]; subst. - do 2 rewrite split1_combine. - rewrite combine_assoc_existT in H. - destruct_existT. - assert (split1 _ _ (split1 _ _ (combine (combine x x3) x4)) = - split1 _ _ (split1 _ _ (combine (combine x1 x2) wu))) - by (rewrite H; reflexivity). - repeat rewrite split1_combine in H0. - assumption. -Qed. - -Lemma extz_pow2_wordToZ: - forall sz (w: word sz) n, - wordToZ (extz w n) = (wordToZ w * Z.of_nat (pow2 n))%Z. -Proof. - induction n; [cbn; omega|]. - rewrite pow2_S_z. - change (wordToZ (extz w (S n))) with (wordToZ (combine (natToWord n 0) w)~0). - rewrite wordToZ_WS_0. - unfold extz, wzero in IHn. - rewrite IHn. - rewrite Z.mul_assoc. - rewrite Z.mul_comm with (n:= 2%Z). - apply eq_sym, Z.mul_assoc. -Qed. - -Lemma extz_wneg: - forall sz (w: word sz) n, - extz (wneg w) n = wneg (extz w n). -Proof. - induction n; intros; [reflexivity|]. - cbn; rewrite wneg_WS_0. - unfold extz, wzero in IHn. - rewrite IHn. - reflexivity. -Qed. - -Lemma wneg_wordToZ: - forall sz (w: word (S sz)), - w <> wpow2 sz -> - wordToZ (wneg w) = (- wordToZ w)%Z. -Proof. - intros. - assert (wordToZ (wneg w) + wordToZ w = 0)%Z. - { destruct (weq w (wzero _)). - { subst; rewrite wzero_wneg, wordToZ_wzero. - reflexivity. - } - { rewrite <-wordToZ_distr_diff_wmsb. - { rewrite wplus_comm, wminus_inv. - apply wordToZ_wzero. - } - { remember (wmsb w false) as msb; destruct msb. - { eapply wmsb_wneg_true; eauto. } - { eapply wmsb_wneg_false; eauto. - intro Hx; elim n. - apply wordToNat_inj. - rewrite wordToNat_wzero, Hx; reflexivity. - } - } - } - } - omega. -Qed. - -Lemma wneg_wordToZ': - forall sz (w: word (S sz)) z, - w <> wpow2 sz -> - (z + wordToZ (wneg w))%Z = (z - wordToZ w)%Z. -Proof. - intros. - rewrite wneg_wordToZ by assumption. - omega. -Qed. - -Lemma wneg_wplus_distr: - forall sz (w1 w2: word sz), - wneg (w1 ^+ w2) = wneg w1 ^+ wneg w2. -Proof. - intros. - apply wplus_cancel with (c:= w1 ^+ w2). - rewrite wplus_comm, wminus_inv. - rewrite wplus_comm, wplus_assoc. - rewrite <-wplus_assoc with (x:= w1). - rewrite wplus_comm with (x:= w2). - rewrite wplus_assoc. - rewrite wminus_inv. - rewrite wplus_wzero_2. - rewrite wminus_inv. - reflexivity. -Qed. - -Lemma wminus_wneg: - forall sz (w1 w2: word sz), - wneg (w1 ^- w2) = w2 ^- w1. -Proof. - unfold wminus; intros. - rewrite wneg_wplus_distr. - rewrite wneg_idempotent. - apply wplus_comm. -Qed. - -Lemma wminus_wordToZ: - forall sz (w1 w2: word (S sz)), - w2 ^- w1 <> wpow2 sz -> - wordToZ (w1 ^- w2) = (- wordToZ (w2 ^- w1))%Z. -Proof. - intros. - rewrite <-wneg_idempotent with (w:= w1 ^- w2). - rewrite wminus_wneg. - rewrite wneg_wordToZ by assumption. - reflexivity. -Qed. - -Lemma wminus_wordToZ': - forall sz (w1 w2: word (sz + 1)), - existT word _ (w2 ^- w1) <> existT word _ (wpow2 sz) -> - wordToZ (w1 ^- w2) = (- wordToZ (w2 ^- w1))%Z. -Proof. - intro sz. - replace (sz + 1) with (S sz) by omega. - intros. - apply wminus_wordToZ. - intro Hx; elim H. - rewrite Hx; reflexivity. -Qed. - -Lemma wminus_wminusZ: forall (sz : nat) (w1 w2 : word sz), w1 ^- w2 = wminusZ w1 w2. -Proof. - unfold wminusZ, wminus, wordBinZ. intros. rewrite <- Z.add_opp_r. - rewrite wplus_wplusZ. unfold wplusZ, wordBinZ. - destruct sz. - - do 2 rewrite ZToWord_sz0. reflexivity. - - destruct (weq w2 (wpow2 sz)). - + subst. rewrite wpow2_wneg. - replace (wordToZ w1 + - wordToZ (wpow2 sz))%Z - with (wordToZ w1 + wordToZ (wpow2 sz) - 2 * wordToZ (wpow2 sz))%Z by omega. - replace (2 * wordToZ (wpow2 sz))%Z with (- 1 * Z.of_N (Npow2 (S sz)))%Z. - * symmetry. apply ZToWord_Npow2_sub_z. - * rewrite wordToZ_wordToN. - rewrite wpow2_wmsb. - rewrite wpow2_Npow2. - rewrite Npow2_S. - rewrite N2Z.inj_add. - omega. - + rewrite wneg_wordToZ by assumption. reflexivity. -Qed. - -Local Lemma wminusZ_helper: forall a b k1 k2 p, - ((a - k1 * p) - (b - k2 * p) = a - b - (k1 - k2) * p)%Z. -Proof. intros. nia. Qed. - -Lemma ZToWord_minus: forall sz a b, ZToWord sz (a - b) = ZToWord sz a ^- ZToWord sz b. -Proof. - intros. rewrite wminus_wminusZ. unfold wminusZ, wordBinZ. - destruct (wordToZ_ZToWord' sz a) as [k1 D1]. rewrite D1. clear D1. - destruct (wordToZ_ZToWord' sz b) as [k2 D2]. rewrite D2. clear D2. - rewrite wminusZ_helper. - symmetry. - apply ZToWord_Npow2_sub_z. -Qed. - -Lemma extz_zero: - forall sz n, extz (natToWord sz 0) n = wzero _. -Proof. - unfold wzero; intros. - rewrite extz_combine. - apply combine_zero. -Qed. - -Lemma sext_eq_rect: - forall sz (w: word sz) n nsz Hsz1, - exists Hsz2, - eq_rect (sz + n) word (sext w n) (nsz + n) Hsz1 = - sext (eq_rect sz word w nsz Hsz2) n. -Proof. - intros. - assert (Hsz: sz = nsz) by omega. - exists Hsz. - subst; simpl. - eq_rect_simpl. - reflexivity. -Qed. - -Lemma wmsb_sext: - forall sz (w: word sz) n, - wmsb (sext w n) false = wmsb w false. -Proof. - unfold sext; intros. - remember (wmsb w false) as ww; destruct ww. - - destruct n; cbn. - + rewrite wmsb_combine_WO; auto. - + rewrite wmsb_combine with (b2:= false) by discriminate; cbn. - clear; induction n; cbn; auto. - - destruct n; cbn. - + rewrite wmsb_combine_WO; auto. - + rewrite wmsb_combine with (b2:= false) by discriminate; cbn. - clear; induction n; cbn; auto. -Qed. - -Lemma wmsb_wlshift_sext: (* Note: not axiom free *) - forall sz (w: word sz) n, - wmsb (sext w n) false = wmsb (wlshift (sext w n) n) false. -Proof. - intros. - pose proof (wlshift_sext_extz w n). - apply wmsb_existT with (b:= false) in H. - rewrite H. - rewrite wmsb_sext. - rewrite wmsb_extz. - reflexivity. -Qed. - -Lemma wordToZ_wordToNat_pos: - forall sz (w: word sz), - wmsb w false = false -> - Z.of_nat (wordToNat w) = wordToZ w. -Proof. - unfold wordToZ; intros. - rewrite H. - rewrite <-wordToN_to_nat. - destruct (wordToN w). - - reflexivity. - - simpl; apply positive_nat_Z. -Qed. - -Corollary wmsb_Zabs_pos: - forall sz (w: word sz), - wmsb w false = false -> Z.abs (wordToZ w) = wordToZ w. -Proof. - intros. - apply wmsb_false_pos in H. - unfold Z.abs. - destruct (wordToZ w); auto. - pose proof (Zlt_neg_0 p); omega. -Qed. - -Corollary wmsb_Zabs_neg: - forall sz (w: word sz), - wmsb w false = true -> (Z.abs (wordToZ w) = - wordToZ w)%Z. -Proof. - intros. - apply wmsb_true_neg in H. - unfold Z.abs. - destruct (wordToZ w); auto. - pose proof (Zgt_pos_0 p); omega. -Qed. - -Lemma wordToN_combine: - forall sz1 (w1: word sz1) sz2 (w2: word sz2), - wordToN (combine w1 w2) = (wordToN w1 + Npow2 sz1 * wordToN w2)%N. -Proof. - intros. - repeat rewrite wordToN_nat. - rewrite pow2_N. - rewrite <-Nat2N.inj_mul, <-Nat2N.inj_add. - rewrite wordToNat_combine; reflexivity. -Qed. - -Lemma word_exists_bound: - forall sz z, - (- Z.of_nat (pow2 sz) <= z < Z.of_nat (pow2 sz))%Z -> - exists w: word (S sz), wordToZ w = z. -Proof. - intros. - exists (ZToWord (S sz) z). - apply wordToZ_ZToWord; assumption. -Qed. - -Lemma sext_size: - forall sz n (w: word (sz + n)), - sz <> 0 -> - (- Z.of_nat (pow2 (sz - 1)) <= wordToZ w < Z.of_nat (pow2 (sz - 1)))%Z -> - exists sw, w = sext sw n. -Proof. - intros. - destruct sz; [exfalso; auto|clear H]. - simpl in *. - replace (sz - 0) with sz in H0 by omega. - apply word_exists_bound in H0. - destruct H0 as [sw ?]. - exists sw. - apply wordToZ_inj. - change (S (sz + n)) with (S sz + n). - rewrite sext_wordToZ. - auto. -Qed. - -Lemma wordToZ_combine_WO: - forall sz (w: word sz), - wordToZ (combine w WO) = wordToZ w. -Proof. - dependent induction w; [reflexivity|]. - simpl; destruct b. - - destruct n; [rewrite (shatter_word w); reflexivity|]. - change (S n + 0) with (S (n + 0)) in *. - do 2 rewrite wordToZ_WS_1. - rewrite IHw; reflexivity. - - do 2 rewrite wordToZ_WS_0. - rewrite IHw; reflexivity. -Qed. - -Lemma combine_WO: - forall sz (w: word sz), - combine w WO = eq_rect _ word w _ (Nat.add_comm 0 sz). -Proof. - intros. - apply wordToZ_inj. - rewrite wordToZ_eq_rect. - apply wordToZ_combine_WO. -Qed. - -Lemma zext_zero: - forall sz (w: word sz), - zext w 0 = eq_rect _ word w _ (Nat.add_comm 0 sz). -Proof. - unfold zext; intros. - apply combine_WO. -Qed. - -Lemma wmsb_false_wordToNat_eq: - forall sz (w: word (S sz)), - wmsb w false = false -> - wordToNat w = wordToNat (split1 sz _ (eq_rect _ word w _ (Nat.add_comm 1 sz))). -Proof. - intros. - remember (eq_rect _ word w _ (Nat.add_comm 1 sz)) as ww. - assert (wmsb ww false = false) by (subst; rewrite <-wmsb_eq_rect; assumption). - replace (wordToNat w) with (wordToNat ww) by (subst; rewrite wordToNat_eq_rect; reflexivity). - clear Heqww H w. - apply wmsb_false_split2_wzero in H0. - rewrite <-combine_split with (w:= ww) at 1. - rewrite wordToNat_combine. - rewrite <-H0. - cbn; omega. -Qed. - -Lemma wordToZ_bound_weakened: - forall z n, (Z.abs z < n)%Z -> (- n <= z < n)%Z. -Proof. - intros. - apply Z.abs_lt in H. - omega. -Qed. - -Lemma zext_size: - forall sz n (w: word (sz + n)), - (- Z.of_nat (pow2 sz) <= wordToZ w < Z.of_nat (pow2 sz))%Z -> - wmsb w false = false -> - exists sw, w = zext sw n. -Proof. - intros. - destruct n. - - exists (eq_rect _ word w _ (Nat.add_comm _ _)). - rewrite zext_zero. - apply eq_sym, eq_rect_2. - - apply word_exists_bound in H. - destruct H as [ssw ?]. - assert (wmsb ssw false = false). - { apply wmsb_false_pos; apply wmsb_false_pos in H0. - rewrite H; assumption. - } - eexists. - apply wordToZ_inj. - rewrite zext_wordToNat_equal_Z by discriminate. - rewrite <-H. - rewrite <-wordToZ_wordToNat_pos by assumption. - rewrite wmsb_false_wordToNat_eq by assumption. - reflexivity. -Qed. - -Lemma zext_size_1: (* Note: not axiom free *) - forall sz (w: word (sz + 1)), - wmsb w false = false -> - exists sw, w = zext sw 1. -Proof. - intros. - apply zext_size; auto. - generalize dependent w. - replace (sz + 1) with (S sz) by omega. - intros. - unfold wordToZ. - rewrite H. - apply wmsb_false_bound in H. - remember (wordToN w) as n; destruct n; simpl. - - split. - + omega. - + pose proof (pow2_zero sz); omega. - - rewrite <-N2Z.inj_pos. - rewrite <-N_nat_Z. - split; [omega|]. - apply inj_lt. - rewrite <-Npow2_nat. - apply Nlt_out; auto. -Qed. - -Lemma sext_wplus_exist: - forall sz (w1 w2: word sz) n, - exists w: word (S sz), - existT word _ (sext w1 (S n) ^+ sext w2 (S n)) = - existT word _ (sext w n). -Proof. - intros; eexists. - apply wordToZ_existT; [omega|]. - rewrite sext_wplus_wordToZ_distr by discriminate. - do 3 rewrite sext_wordToZ. - assert (- Z.of_nat (pow2 sz) <= wordToZ w1 + wordToZ w2 < Z.of_nat (pow2 sz))%Z. - { clear n. - dependent destruction w1. - { rewrite (shatter_word w2); cbn; omega. } - { remember (WS b w1) as ww1; clear Heqww1 w1 b. - pose proof (wordToZ_size' ww1). - pose proof (wordToZ_size' w2). - destruct H, H0. - split. - { simpl; do 2 rewrite Nat2Z.inj_add; omega. } - { simpl; do 2 rewrite Nat2Z.inj_add; omega. } - } - } - apply wordToZ_ZToWord in H. - rewrite <-H. - reflexivity. -Qed. - -(* Don't allow simpl to expand out these functions *) -Arguments natToWord : simpl never. -Arguments weq : simpl never. - -(* Making wlt_dec opaque is necessary to prevent the [exact H] in the - * example below from blowing up.. - *) -Global Opaque wlt_dec. -Definition test_wlt_f (a : nat) (b : nat) : nat := - if wlt_dec (natToWord 64 a) $0 then 0 else 0. -Theorem test_wlt_f_example: forall x y z, test_wlt_f x y = 0 -> test_wlt_f x z = 0. -Proof. - intros. - exact H. -Qed. - -Lemma wordToNat_eq1: forall sz (a b: word sz), a = b -> wordToNat a = wordToNat b. -Proof. - intros; subst; reflexivity. -Qed. - -Lemma wordToNat_eq2: forall sz (a b: word sz), wordToNat a = wordToNat b -> a = b. -Proof. - intros. - rewrite <- natToWord_wordToNat with (w := a). - rewrite <- natToWord_wordToNat with (w := b). - rewrite H. - reflexivity. -Qed. - -Lemma wordToNat_lt1: forall sz (a b: word sz), a < b -> (wordToNat a < wordToNat b)%nat. -Proof. - intros. - pre_nomega. - repeat rewrite wordToN_to_nat in H. - assumption. -Qed. - -Lemma wordToNat_lt2: forall sz (a b: word sz), (wordToNat a < wordToNat b)%nat -> a < b. -Proof. - intros. - pre_nomega. - repeat rewrite wordToN_to_nat. - assumption. -Qed. - -Lemma wordToNat_gt1: forall sz (a b: word sz), a > b -> (wordToNat a > wordToNat b)%nat. -Proof. - intros. - pre_nomega. - repeat rewrite wordToN_to_nat in H. - assumption. -Qed. - -Lemma wordToNat_gt2: forall sz (a b: word sz), (wordToNat a > wordToNat b)%nat -> a > b. -Proof. - intros. - pre_nomega. - repeat rewrite wordToN_to_nat. - assumption. -Qed. - -Lemma wordToNat_le1: forall sz (a b: word sz), a <= b -> (wordToNat a <= wordToNat b)%nat. -Proof. - intros. - pre_nomega. - repeat rewrite wordToN_to_nat in H. - assumption. -Qed. - -Lemma wordToNat_le2: forall sz (a b: word sz), (wordToNat a <= wordToNat b)%nat -> a <= b. -Proof. - intros. - pre_nomega. - repeat rewrite wordToN_to_nat. - assumption. -Qed. - -Lemma wordToNat_ge1: forall sz (a b: word sz), a >= b -> (wordToNat a >= wordToNat b)%nat. -Proof. - intros. - pre_nomega. - repeat rewrite wordToN_to_nat in H. - assumption. -Qed. - -Lemma wordToNat_ge2: forall sz (a b: word sz), (wordToNat a >= wordToNat b)%nat -> a >= b. -Proof. - intros. - pre_nomega. - repeat rewrite wordToN_to_nat. - assumption. -Qed. - -Lemma wordToNat_neq1: forall sz (a b: word sz), a <> b -> wordToNat a <> wordToNat b. -Proof. - unfold not. - intros. - apply wordToNat_eq2 in H0. - tauto. -Qed. - -Lemma wordToNat_neq2: forall sz (a b: word sz), wordToNat a <> wordToNat b -> a <> b. -Proof. - unfold not. - intros. - subst. - tauto. -Qed. - -Lemma wordToNat_wplus': forall sz (a b: word sz), - (#a + #b < pow2 sz)%nat -> - #(a ^+ b) = #a + #b. -Proof. - intros. - rewrite <-? wordToN_to_nat in *. - rewrite <-? Nnat.N2Nat.inj_add in *. - rewrite <- Npow2_nat in *. - apply Nlt_in in H. - rewrite wordToN_plus by assumption. - reflexivity. -Qed. - -Lemma wordToNat_wmult': forall sz (a b: word sz), - (#a * #b < pow2 sz)%nat -> - #(a ^* b) = #a * #b. -Proof. - intros. - rewrite <-? wordToN_to_nat in *. - rewrite <-? Nnat.N2Nat.inj_mul in *. - rewrite <- Npow2_nat in *. - apply Nlt_in in H. - rewrite wordToN_mult by assumption. - reflexivity. -Qed. - -Lemma wordNotNot: forall sz (a b: word sz), (a <> b -> False) -> a = b. -Proof. - intros. - destruct (weq a b); subst; tauto. -Qed. - -Ltac pre_word_omega := - unfold wzero, wone in *; - repeat match goal with - | H: @eq ?T ?a ?b |- _ => - match T with - | word ?sz => - apply (@wordToNat_eq1 sz a b) in H; - rewrite ?roundTrip_0, ?roundTrip_1, ?wones_pow2_minus_one in H; - simpl in H - end - | |- @eq ?T ?a ?b => - match T with - | word ?sz => - apply (@wordToNat_eq2 sz a b); - rewrite ?roundTrip_0, ?roundTrip_1, ?wones_pow2_minus_one; - simpl - end - | H: ?a < ?b |- _ => - apply wordToNat_lt1 in H; - rewrite ?roundTrip_0, ?roundTrip_1, ?wones_pow2_minus_one in H; - simpl in H - | |- ?a < ?b => - apply wordToNat_lt2; - rewrite ?roundTrip_0, ?roundTrip_1, ?wones_pow2_minus_one; - simpl - | H: ?a > ?b |- _ => - apply wordToNat_gt1 in H; - rewrite ?roundTrip_0, ?roundTrip_1, ?wones_pow2_minus_one in H; - simpl in H - | |- ?a > ?b => - apply wordToNat_gt2; - rewrite ?roundTrip_0, ?roundTrip_1, ?wones_pow2_minus_one; - simpl - | H: ?a <= ?b |- _ => - apply wordToNat_le1 in H; - rewrite ?roundTrip_0, ?roundTrip_1, ?wones_pow2_minus_one in H; - simpl in H - | |- ?a <= ?b => - apply wordToNat_le2; - rewrite ?roundTrip_0, ?roundTrip_1, ?wones_pow2_minus_one; - simpl - | H: ?a > ?b -> False |- _ => - apply wordToNat_le1 in H; - rewrite ?roundTrip_0, ?roundTrip_1, ?wones_pow2_minus_one in H; - simpl in H - | |- ?a > ?b -> False => - apply wordToNat_le2; - rewrite ?roundTrip_0, ?roundTrip_1, ?wones_pow2_minus_one; - simpl - | H: ?a < ?b -> False |- _ => - apply wordToNat_ge1 in H; - rewrite ?roundTrip_0, ?roundTrip_1, ?wones_pow2_minus_one in H; - simpl in H - | |- ?a < ?b -> False => - apply wordToNat_ge2; - rewrite ?roundTrip_0, ?roundTrip_1, ?wones_pow2_minus_one; - simpl - | H: not (@eq ?T ?a ?b) |- _ => - match T with - | word ?sz => - apply (@wordToNat_neq1 sz a b) in H; - rewrite ?roundTrip_0, ?roundTrip_1, ?wones_pow2_minus_one in H; - simpl in H - end - | |- not (@eq ?T ?a ?b) => - match T with - | word ?sz => - apply (@wordToNat_neq2 sz a b); - rewrite ?roundTrip_0, ?roundTrip_1, ?wones_pow2_minus_one; - simpl - end - | H: @eq ?T ?a ?b -> False |- _ => - match T with - | word ?sz => - apply (@wordToNat_neq1 sz a b) in H; - rewrite ?roundTrip_0, ?roundTrip_1, ?wones_pow2_minus_one in H; - simpl in H - end - | |- @eq ?T ?a ?b -> False => - match T with - | word ?sz => - apply (@wordToNat_neq2 sz a b); - rewrite ?roundTrip_0, ?roundTrip_1, ?wones_pow2_minus_one; - simpl - end - | H: (@eq ?T ?a ?b -> False) -> False |- _ => - match T with - | word ?sz => - apply (@wordNotNot sz a b) in H - end - | H: (not (@eq ?T ?a ?b)) -> False |- _ => - match T with - | word ?sz => - apply (@wordNotNot sz a b) in H - end - | H: not (@eq ?T ?a ?b -> False) |- _ => - match T with - | word ?sz => - apply (@wordNotNot sz a b) in H - end - | H: not (not (@eq ?T ?a ?b)) |- _ => - match T with - | word ?sz => - apply (@wordNotNot sz a b) in H - end - end. - - -Ltac word_omega := pre_word_omega; omega. - - - -Lemma word_le_ge_eq sz (w1 w2: word sz): w1 <= w2 -> w1 >= w2 -> w1 = w2. -Proof. - intros; word_omega. -Qed. - -Lemma word_le_zero sz (w: word sz): w <= wzero sz -> w = wzero sz. -Proof. - intros; word_omega. -Qed. - -Close Scope word_scope. - -Open Scope word_scope. -Local Open Scope nat. - -Lemma wzero_wones: forall sz, sz >= 1 -> - natToWord sz 0 <> wones sz. -Proof. - intros. - unfold not. - intros. - pose proof (f_equal (@wordToNat sz) H0) as sth. - unfold wzero in *. - rewrite roundTrip_0 in *. - rewrite wones_pow2_minus_one in sth. - destruct sz; [omega | ]. - pose proof (NatLib.one_lt_pow2 sz). - omega. -Qed. - -Lemma wzero_wplus: forall sz w, wzero sz ^+ w = w. -Proof. - intros. - unfold wzero. - apply wplus_unit. -Qed. - -Lemma wordToNat_nonZero sz (w: word sz): - w <> wzero sz -> wordToNat w > 0. -Proof. - induction w; simpl; unfold wzero; simpl; intros. - - tauto. - - destruct b. - + omega. - + assert (sth: w <> (natToWord n 0)). - { intro. - subst. - tauto. - } - assert (sth2: wordToNat w <> 0). - { intro sth3. - specialize (IHw sth). - omega. - } - omega. -Qed. - -Lemma split2_pow2: forall sz n, - 2 ^ sz <= n < 2 ^ S sz -> - wordToNat (split2 sz 1 (natToWord (sz + 1) n)) = 1. -Proof. - intros. - rewrite wordToNat_split2. - simpl in *. - rewrite Nat.add_0_r in *. - (* pose proof (wordToNat_natToWord sz n). *) - rewrite wordToNat_natToWord_bound with (bound := wones _). - - destruct H. - assert (sth: pow2 sz <> 0) by omega. - pose proof (Nat.div_le_mono _ _ (pow2 sz) sth H) as sth2. - rewrite Nat.div_same in sth2 by auto. - apply Nat.lt_le_pred in H0. - pose proof (Nat.div_le_mono _ _ (pow2 sz) sth H0) as sth3. - rewrite <- Nat.sub_1_r in sth3. - assert (sth4: pow2 sz = 1 * pow2 sz) by omega. - rewrite sth4 in sth3 at 2. - assert (sth5: 1 * pow2 sz + pow2 sz - 1 = 1 * pow2 sz + (pow2 sz - 1)) by omega. - rewrite sth5 in sth3. - rewrite Nat.div_add_l in sth3 by omega. - rewrite Nat.div_small with (a := pow2 sz - 1) in sth3 by omega. - omega. - - rewrite wones_pow2_minus_one. - assert (sth: sz + 1 = S sz) by omega. - rewrite sth. - simpl. - omega. -Qed. - -Lemma combine_wones_WO sz: - forall w, w <> wzero sz -> split2 sz 1 (combine (wones sz) ($ 0) ^+ combine w ($ 0)) = WO~1. -Proof. - intros. - match goal with - | |- split2 _ _ (?a ^+ ?b) = _ => - rewrite <- (@natToWord_wordToNat _ a); - rewrite <- (@natToWord_wordToNat _ b) - end. - rewrite <- natToWord_plus. - rewrite ?wordToNat_combine. - simpl. - rewrite wones_pow2_minus_one. - pose proof (wordToNat_bound w) as sth. - pose proof (wordToNat_nonZero H). - assert (sth2: 2^sz <= 2 ^ sz - 1 + wordToNat w < 2 ^ (S sz)). { - pose proof (pow2_zero sz) as sth3. - split; simpl; omega. - } - apply split2_pow2 in sth2. - rewrite Nat.mul_0_r. - rewrite ?Nat.add_0_r. - apply (f_equal (natToWord 1)) in sth2. - rewrite natToWord_wordToNat in sth2. - assumption. -Qed. - -Lemma wordToNat_plus sz (w1 w2: word sz): - natToWord sz (wordToNat w1 + wordToNat w2) = w1 ^+ w2. -Proof. - rewrite natToWord_plus. - rewrite ?natToWord_wordToNat. - auto. -Qed. - -Lemma wordToNat_natToWord_eqn sz: - forall n, - wordToNat (natToWord sz n) = n mod (pow2 sz). -Proof. - intros. - pose proof (wordToNat_natToWord sz n). - destruct H as [? [? ?]]. - rewrite H. - assert (sth: pow2 sz * x = x * pow2 sz) by (apply Nat.mul_comm). - rewrite <- sth in *. - clear sth. - pose proof (wordToNat_bound (natToWord sz n)). - apply (Nat.mod_unique n (pow2 sz) x (n - pow2 sz * x)); try omega. -Qed. - -Lemma mod_factor a b c: - b <> 0 -> - c <> 0 -> - (a mod (b * c)) mod b = a mod b. -Proof. - intros. - pose proof (Nat.mod_mul_r a _ _ H H0). - rewrite H1. - rewrite Nat.add_mod_idemp_l by auto. - rewrite Nat.add_mod by auto. - assert (sth: b * ((a/b) mod c) = (a/b) mod c * b) by (apply Nat.mul_comm). - rewrite sth. - rewrite Nat.mod_mul by auto. - rewrite Nat.add_0_r. - rewrite Nat.mod_mod by auto. - auto. -Qed. - -Lemma split1_combine_wplus sz1 sz2 (w11 w21: word sz1) (w12 w22: word sz2): - split1 _ _ (combine w11 w12 ^+ combine w21 w22) = w11 ^+ w21. -Proof. - rewrite <- natToWord_wordToNat at 1. - rewrite wordToNat_split1. - rewrite <- wordToNat_plus. - rewrite ?wordToNat_combine. - assert (sth: #w11 + pow2 sz1 * #w12 + (#w21 + pow2 sz1 * #w22) = #w11 + #w21 + pow2 sz1 * (#w12 + #w22)) by ring. - rewrite wordToNat_natToWord_eqn. - rewrite sth. - rewrite Nat.pow_add_r. - assert (pow2 sz1 <> 0) by (pose proof (pow2_zero sz1); intro; omega). - assert (pow2 sz2 <> 0) by (pose proof (pow2_zero sz2); intro; omega). - rewrite mod_factor by auto. - rewrite Nat.add_mod by auto. - assert (sth2: pow2 sz1 * (# w12 + #w22) = (#w12 + #w22) * pow2 sz1) by ring. - rewrite sth2. - rewrite Nat.mod_mul by auto. - rewrite Nat.add_0_r. - rewrite Nat.mod_mod by auto. - rewrite <- wordToNat_natToWord_eqn. - rewrite natToWord_wordToNat. - rewrite natToWord_plus. - rewrite ?natToWord_wordToNat. - auto. -Qed. - -Lemma div_2 a b: - b <> 0 -> - a < b * 2 -> - a >= b -> - a / b = 1. -Proof. - intros. - assert (sth: b * 1 <= a) by omega. - pose proof (Nat.div_le_lower_bound a b 1 H sth). - pose proof (Nat.div_lt_upper_bound a b 2 H H0). - omega. -Qed. - -Lemma mod_sub a b: - b <> 0 -> - a < b * 2 -> - a >= b -> - a mod b = a - b. -Proof. - intros. - rewrite Nat.mod_eq; auto. - repeat f_equal. - rewrite div_2 by auto. - rewrite Nat.mul_1_r; auto. -Qed. - -Lemma wordToNat_wneg_non_0 sz: forall (a: word sz), - a <> natToWord _ 0 -> - # (wneg a) = pow2 sz - #a. -Proof. - intros. - unfold wneg. - rewrite pow2_N. - rewrite NToWord_nat. - rewrite Nnat.N2Nat.inj_sub. - rewrite wordToN_to_nat. - rewrite Nnat.Nat2N.id. - simpl. - rewrite wordToNat_natToWord_idempotent'; auto. - assert (#a <> 0) by word_omega. - pose proof (pow2_zero sz). - omega. -Qed. - -Lemma wordToNat_wnot sz: forall (a: word sz), - # (wnot a) = pow2 sz - #a - 1. -Proof. - intros. - rewrite wnot_def. - rewrite pow2_N. - rewrite NToWord_nat. - rewrite Nnat.N2Nat.inj_sub. - rewrite Nnat.N2Nat.inj_sub. - rewrite wordToN_to_nat. - rewrite Nnat.Nat2N.id. - simpl. - rewrite wordToNat_natToWord_idempotent'; auto. - pose proof (pow2_zero sz). - unfold Pos.to_nat; simpl. - omega. -Qed. - -Lemma wzero_wor: forall sz w, w ^| wzero sz = w. -Proof. - intros. - rewrite wor_comm. - rewrite wor_wzero. - auto. -Qed. - -Lemma bool_prop1: forall a b, a && negb (a && b) = a && negb b. -Proof. - destruct a, b; simpl; auto. -Qed. - -Lemma wordToNat_wplus sz (w1 w2: word sz): - #(w1 ^+ w2) = (#w1 + #w2) mod (pow2 sz). -Proof. - rewrite <- (natToWord_wordToNat w1) at 1. - rewrite <- (natToWord_wordToNat w2) at 1. - rewrite <- natToWord_plus. - rewrite wordToNat_natToWord_eqn. - auto. -Qed. - -Lemma wordToNat_wmult : forall (sz : nat) (w1 w2 : word sz), - #(w1 ^* w2) = (#w1 * #w2) mod pow2 sz. -Proof using . - clear. intros. - rewrite <- (natToWord_wordToNat w1) at 1. - rewrite <- (natToWord_wordToNat w2) at 1. - rewrite <- natToWord_mult. - rewrite wordToNat_natToWord_eqn. - reflexivity. -Qed. - -Lemma wor_r_wzero_1 sz: (* Note: not axiom free *) - forall w1 w2, - w1 ^| w2 = natToWord sz 0 -> - w2 = natToWord sz 0. -Proof. - induction w1; simpl; auto; intros. - pose proof (shatter_word w2) as sth. - simpl in sth. - rewrite sth in *. - unfold wor in H. - simpl in H. - unfold natToWord in H. - unfold natToWord. - fold (natToWord n (Nat.div2 0)) in *. - unfold Nat.div2, mod2 in *. - inversion H. - destruct_existT. - rewrite (IHw1 _ H2). - f_equal. - destruct b, (whd w2); auto. -Qed. - -Lemma wor_r_wzero_2 sz: (* Note: not axiom free *) - forall w1 w2, - w1 ^| w2 = natToWord sz 0 -> - w1 = natToWord sz 0. -Proof. - induction w1; simpl; auto; intros. - pose proof (shatter_word w2) as sth. - simpl in sth. - rewrite sth in *. - unfold wor in H. - simpl in H. - unfold natToWord in H. - unfold natToWord. - fold (natToWord n (Nat.div2 0)) in *. - unfold Nat.div2, mod2 in *. - inversion H. - destruct_existT. - rewrite (IHw1 _ H2). - f_equal. - destruct b, (whd w2); auto. -Qed. - -Fixpoint countLeadingZerosWord ni no: word ni -> word no := - match ni return word ni -> word no with - | 0 => fun _ => $ 0 - | S m => fun e => - if (weq (split2 m 1 (nat_cast (fun n => word n) (eq_sym (Nat.add_1_r m)) e)) WO~0) - then $ 1 ^+ @countLeadingZerosWord m no (split1 m 1 (nat_cast (fun n => word n) (eq_sym (Nat.add_1_r m)) e)) - else $ 0 - end. - - -Lemma countLeadingZerosWord_le_len no ni: - ni < pow2 no -> - forall w: word ni, (countLeadingZerosWord no w <= natToWord _ ni)%word. -Proof. - induction ni; simpl; auto; intros. - - word_omega. - - match goal with - | |- ((if ?P then _ else _) <= _)%word => destruct P; simpl; auto - end; [| word_omega]. - assert (sth: ni < pow2 no) by omega. - specialize (IHni sth). - assert (sth1: natToWord no (S ni) = natToWord no (1 + ni)) by auto. - rewrite sth1. - rewrite natToWord_plus. - match goal with - | |- ((_ ^+ countLeadingZerosWord no ?P) <= _)%word => specialize (IHni P) - end. - match goal with - | |- (?a ^+ ?b <= ?c ^+ ?d)%word => - rewrite (wplus_comm a b); rewrite (wplus_comm c d) - end. - pre_word_omega. - assert (sth2: no > 0). { - destruct no; [|omega]. - destruct ni; simpl in *; try omega. - } - rewrite <- ?(@natplus1_wordplus1_eq _ _ (wones no)); auto. - + pre_word_omega. - rewrite wordToNat_natToWord_eqn. - rewrite Nat.mod_small; auto. - + pre_word_omega. - rewrite wordToNat_natToWord_eqn in IHni. - rewrite Nat.mod_small in IHni; auto. -Qed. - -Lemma countLeadingZerosWord_le_len_nat no ni: - ni < pow2 no -> - forall w: word ni, #(countLeadingZerosWord no w) <= ni. -Proof. - intros H w. - pose proof (countLeadingZerosWord_le_len H w) as sth. - pre_word_omega. - rewrite wordToNat_natToWord_idempotent' in * by assumption. - assumption. -Qed. - - -Lemma wordToNat_zero sz: forall (w: word sz), #w = 0 -> w = natToWord _ 0. -Proof. - intros. - apply (f_equal (natToWord sz)) in H. - rewrite natToWord_wordToNat in H. - auto. -Qed. - -Lemma wordToNat_notZero sz: forall (w: word sz), #w <> 0 -> w <> natToWord _ 0. -Proof. - intros. - intro. - subst. - pose proof (wordToNat_wzero sz); unfold wzero in *. - tauto. -Qed. - - -Lemma natToWord_nzero sz x: - 0 < x -> - x < pow2 sz -> - natToWord sz x <> natToWord sz 0. -Proof. - intros. - pre_word_omega. - rewrite wordToNat_natToWord_idempotent'; omega. -Qed. - -Lemma pow2_lt_pow2_S: - forall n, pow2 n < pow2 (n+1). -Proof. - induction n; simpl; omega. -Qed. - -Lemma combine_shiftl_plus_n n x: - x < pow2 n -> - (combine (natToWord n x) WO~1) = (natToWord (n + 1) (pow2 n)) ^+ natToWord (n + 1) x. -Proof. - intros. - apply wordToNat_eq2. - rewrite ?wordToNat_combine. - rewrite ?wordToNat_natToWord_idempotent'; simpl; auto. - rewrite <- wordToNat_plus. - pose proof (pow2_lt_pow2_S n) as sth. - rewrite ?wordToNat_natToWord_idempotent'; simpl; try omega. - rewrite ?wordToNat_natToWord_idempotent'; simpl; try omega. - apply Nat.lt_add_lt_sub_l. - rewrite Nat.add_1_r. - simpl. - omega. -Qed. - -Lemma combine_natToWord_wzero n: - forall x, - x < pow2 n -> - combine (natToWord n x) (natToWord 1 0) = natToWord (n+1) x. -Proof. - intros. - apply wordToNat_eq2. - rewrite ?wordToNat_combine. - simpl. - rewrite Nat.mul_0_r. - rewrite Nat.add_0_r. - pose proof (pow2_lt_pow2_S n) as sth2. - rewrite ?wordToNat_natToWord_idempotent' by omega. - reflexivity. -Qed. - -Lemma word_cancel_l sz (a b c: word sz): - a = b -> c ^+ a = c ^+ b. -Proof. - intro H; rewrite H; reflexivity. -Qed. - - -Lemma word_cancel_r sz (a b c: word sz): - a = b -> a ^+ c = b ^+ c. -Proof. - intro H; rewrite H; reflexivity. -Qed. - -Lemma word_cancel_m sz (a b c a' b': word sz): - a ^+ a' = b ^+ b'-> a ^+ c ^+ a' = b ^+ c ^+ b'. -Proof. - intros. - assert (sth: a ^+ c ^+ a' = a ^+ a'^+ c ). - rewrite <- wplus_assoc. - rewrite wplus_comm with (y := a'). - rewrite wplus_assoc. - reflexivity. - rewrite sth. - rewrite H. - rewrite <- wplus_assoc. - rewrite wplus_comm with (x := b'). - rewrite wplus_assoc. - reflexivity. -Qed. - -Lemma move_wplus_wminus sz (a b c: word sz): - a ^+ b = c <-> a = c ^- b. -Proof. - split; intro. - + rewrite <- H. - rewrite wminus_def. - rewrite <- wplus_assoc. - rewrite wminus_inv. - rewrite wplus_wzero_1. - reflexivity. - + rewrite H. - rewrite wminus_def. - rewrite <- wplus_assoc. - rewrite wplus_comm with (x:= ^~b). - rewrite wminus_inv. - rewrite wplus_wzero_1. - reflexivity. -Qed. - -Lemma move_wplus_pow2 sz (w1 w2: word (S sz)): - w1 = w2 ^+ $(pow2 sz) <-> - w1 ^+ $(pow2 sz) = w2. -Proof. - split. - + intro. - apply move_wplus_wminus. - rewrite wminus_def. - rewrite pow2_wneg. - assumption. - + intro. - apply move_wplus_wminus in H. - rewrite <- pow2_wneg. - assumption. -Qed. - -Lemma move_wminus_pow2 sz (w1 w2: word (S sz)): - w1 = w2 ^- $(pow2 sz) <-> - w1 ^- $(pow2 sz) = w2. -Proof. - split. - + intro. - apply <- move_wplus_wminus. - rewrite pow2_wneg. - assumption. - + intro. - apply move_wplus_wminus. - rewrite <- pow2_wneg. - rewrite <- wminus_def. - assumption. -Qed. - -Lemma pow2_wzero sz : - $(pow2 sz) = wzero sz. -Proof. - apply wordToNat_eq2. - rewrite wordToNat_natToWord_eqn. - rewrite Nat.mod_same. - rewrite wordToNat_wzero; auto. - pose proof (zero_lt_pow2 sz) as sth. - omega. -Qed. - -Lemma pow2_wplus_wzero sz: - $(pow2 sz) ^+ $(pow2 sz) = wzero (sz + 1). -Proof. - apply wordToNat_eq2. - rewrite <- natToWord_plus. - rewrite <- mul2_add. - assert (pow2_1_mul: pow2 1 = 2) by auto. - rewrite <- pow2_1_mul at 2. - rewrite <- pow2_add_mul. - rewrite pow2_wzero; auto. -Qed. - -Lemma wplus_wplus_pow2 sz (x1 x2 y1 y2: word (sz + 1)): - x1 = y1 ^+ $(pow2 sz) -> - x2 = y2 ^+ $(pow2 sz) -> - x1 ^+ x2 = y1 ^+ y2. -Proof. - intros. - rewrite H. - rewrite <- wplus_assoc. - rewrite wplus_comm. - rewrite wplus_comm in H0. - rewrite H0. - rewrite wplus_assoc. - rewrite pow2_wplus_wzero. - rewrite wzero_wplus. - rewrite wplus_comm. - reflexivity. -Qed. - - - -Lemma wlt_meaning sz (w1 w2: word sz): - (w1 < w2)%word <-> #w1 < #w2. -Proof. - pose proof (@wordToNat_gt1 sz w2 w1). - pose proof (@wordToNat_gt2 sz w2 w1). - tauto. -Qed. - -Lemma combine_wplus sz (w1 w2: word sz): - #w1 + #w2 < pow2 sz -> - forall sz' (w': word sz'), - combine (w1 ^+ w2) w' = combine w1 w' ^+ combine w2 ($ 0). -Proof. - intros. - pre_word_omega. - rewrite wordToNat_wplus in *. - rewrite ?wordToNat_combine. - rewrite wordToNat_natToWord_idempotent' by (apply pow2_zero). - rewrite Nat.mul_0_r, Nat.add_0_r. - rewrite wordToNat_wplus. - rewrite Nat.mod_small by assumption. - assert (sth: #w1 + #w2 + pow2 sz * #w' = #w1 + pow2 sz * #w' + #w2) by ring. - rewrite <- sth; clear sth. - rewrite Nat.mod_small; auto. - rewrite Nat.pow_add_r. - assert (sth: pow2 sz' = 1 + (pow2 sz' - 1)) by (pose proof (pow2_zero sz'); omega). - rewrite sth; clear sth. - rewrite Nat.mul_add_distr_l. - rewrite Nat.mul_1_r. - pose proof (wordToNat_bound w'). - pose proof (pow2_zero sz). - apply Nat.lt_le_pred in H0. - rewrite pred_of_minus in H0. - pose proof (mult_le_compat_l _ _ (pow2 sz) H0). - omega. -Qed. - -Lemma word1_neq (w: word 1): - w <> WO~0 -> - w <> WO~1 -> - False. -Proof. - shatter_word w; intros. - destruct x; tauto. -Qed. - -Lemma combine_1 sz: - sz > 1 -> - natToWord (sz + 1) 1 = combine ($ 1) WO~0. -Proof. - intros. - rewrite <- natToWord_wordToNat. - f_equal. - rewrite wordToNat_combine; simpl. - rewrite Nat.mul_0_r, Nat.add_0_r. - rewrite wordToNat_natToWord_idempotent'; auto. - destruct sz; simpl; try omega. - pose proof (pow2_zero sz). - omega. -Qed. - -Lemma wordToNat_cast ni no (pf: ni = no): - forall w, - #w = #(match pf in _ = Y return _ Y with - | eq_refl => w - end). -Proof. - destruct pf; intros; auto. -Qed. - - -Lemma countLeadingZerosWord_lt_len no ni: - ni < pow2 no -> - forall w: word ni, - w <> wzero ni -> - (countLeadingZerosWord no w < natToWord _ ni)%word. -Proof. - induction ni; auto; intros. - - shatter_word w. - tauto. - - unfold countLeadingZerosWord; fold countLeadingZerosWord. - rewrite nat_cast_cast. - match goal with - | |- ((if ?P then _ else _) < _)%word => destruct P; simpl; auto - end. - + assert (sth: ni < pow2 no) by omega. - specialize (IHni sth). - assert (sth1: natToWord no (S ni) = natToWord no (1 + ni)) by auto. - rewrite sth1. - rewrite natToWord_plus. - match goal with - | |- ((_ ^+ countLeadingZerosWord no ?P) < _)%word => specialize (IHni P) - end. - match goal with - | |- (?a ^+ ?b < ?c ^+ ?d)%word => - rewrite (wplus_comm a b); rewrite (wplus_comm c d) - end. - pre_word_omega. - assert (sth2: no > 0). { - destruct no; [|omega]. - destruct ni; simpl in *; try omega. - } - apply wordToNat_zero in e. - match type of IHni with - | split1 ni 1 ?P <> _ -> _ => - assert (sth3: #P <> 0) by (rewrite <- wordToNat_cast; auto); - apply wordToNat_notZero in sth3; - rewrite <- (combine_split ni 1 P) in sth3 - end. - rewrite e in *. - match type of sth3 with - | combine ?P _ <> _ => destruct (weq P (natToWord _ 0)); - [rewrite e0 in *; rewrite combine_zero in sth3; tauto|] - end. - specialize (IHni n). - rewrite <- ?(@natplus1_wordplus1_eq _ _ (wones no)); auto. - * pre_word_omega. - omega. - * pre_word_omega. - rewrite wordToNat_natToWord_eqn. - rewrite Nat.mod_small; auto. - * pre_word_omega. - rewrite wordToNat_natToWord_eqn in IHni. - rewrite Nat.mod_small in IHni; auto. - + pre_word_omega. - rewrite wordToNat_natToWord_idempotent'; auto; try omega. -Qed. - - -Fixpoint countLeadingZerosWord_nat ni: word ni -> nat := - match ni return word ni -> nat with - | 0 => fun _ => 0 - | S m => fun e => - if (weq (split2 m 1 (nat_cast (fun n => word n) (eq_sym (Nat.add_1_r m)) e)) WO~0) - then 1 + @countLeadingZerosWord_nat m (split1 m 1 (nat_cast (fun n => word n) (eq_sym (Nat.add_1_r m)) e)) - else 0 - end. - -Lemma countLeadingZerosWord_nat_correct ni: - forall no (w: word ni), - ni < pow2 no -> - #(countLeadingZerosWord no w) = countLeadingZerosWord_nat w. -Proof. - induction ni; intros; simpl; auto. - - rewrite ?wordToNat_natToWord_idempotent'; auto. - - match goal with - | |- # (if ?P then _ else _) = if ?P then _ else _ => destruct P - end. - + rewrite <- wordToNat_plus. - rewrite ?wordToNat_natToWord_idempotent'; try omega. - * simpl;f_equal. - rewrite IHni; auto. - * rewrite ?wordToNat_natToWord_idempotent'; try omega. - match goal with - | |- 1 + #(countLeadingZerosWord no ?x) < _ => pose proof (@countLeadingZerosWord_le_len_nat no ni ltac:(omega) x) as sth - end. - omega. - + rewrite roundTrip_0; auto. -Qed. - -Lemma countLeadingZerosWord_nat_le_len ni (w: word ni): - countLeadingZerosWord_nat w <= ni. -Proof. - induction ni; simpl; auto; intros. - match goal with - | |- ((if ?P then _ else _) <= _) => destruct P; simpl; auto - end. - apply Le.le_n_S. - eapply IHni. -Qed. - -Lemma countLeadingZerosWord_enough_size ni no no' (pf: ni < pow2 no) (pf': ni < pow2 no'): forall (w: word ni), - #(countLeadingZerosWord no w) = - #(countLeadingZerosWord no' w). -Proof. - intros. - rewrite ?countLeadingZerosWord_nat_correct; auto. -Qed. - -(* Usually this kind of lemmas would need a guarantee that "(wordToN a mod wordToN b)%N" - does not overflow, but fortunately this can never overflow. - And also, we don't need to prevent b from being 0. *) -Lemma wordToN_mod: forall sz (a b: word sz), - wordToN (a ^% b) = (wordToN a mod wordToN b)%N. -Proof. - intros. unfold wmod, wordBin. - rewrite wordToN_NToWord_2; [ reflexivity | ]. - destruct (wordToN b) eqn: E. - - unfold N.modulo, N.div_eucl. destruct (wordToN a) eqn: F; simpl. - + apply Npow2_pos. - + rewrite <- F. apply wordToN_bound. - - eapply N.lt_trans. - + apply N.mod_upper_bound. congruence. - + rewrite <- E. apply wordToN_bound. -Qed. - -Lemma N_to_Z_to_nat: forall (a: N), Z.to_nat (Z.of_N a) = N.to_nat a. -Proof. - intros. rewrite <- (N2Z.id a) at 2. - rewrite Z_N_nat. reflexivity. -Qed. - -Section ThisShouldBeInCoqLibrary. - - Lemma N2Nat_inj_mod: forall (a b: N), - (b <> 0)%N -> - N.to_nat (a mod b)%N = (N.to_nat a) mod (N.to_nat b). - Proof. - intros. - rewrite <-? N_to_Z_to_nat. - rewrite N2Z.inj_mod by assumption. - apply Nat2Z.inj. - rewrite Zdiv.mod_Zmod. - - rewrite? Z2Nat.id; try apply N2Z.is_nonneg. - + reflexivity. - + pose proof (Z.mod_pos_bound (Z.of_N a) (Z.of_N b)) as Q. - destruct Q as [Q _]. - * destruct b; try contradiction. simpl. constructor. - * exact Q. - - destruct b; try contradiction. simpl. - pose proof (Pos2Nat.is_pos p) as Q. omega. - Qed. - - Lemma Nat2Z_inj_pow: forall n m : nat, - Z.of_nat (n ^ m) = (Z.of_nat n ^ Z.of_nat m)%Z. - Proof. - intros. induction m. - - reflexivity. - - rewrite Nat2Z.inj_succ. - rewrite Z.pow_succ_r by (apply Nat2Z.is_nonneg). - rewrite <- IHm. - rewrite <- Nat2Z.inj_mul. - reflexivity. - Qed. - - Lemma Z2Nat_inj_pow: forall n m : Z, - (0 <= n)%Z -> - (0 <= m)%Z -> - Z.to_nat (n ^ m) = Z.to_nat n ^ Z.to_nat m. - Proof. - intros. - pose proof (Nat2Z_inj_pow (Z.to_nat n) (Z.to_nat m)) as P. - rewrite? Z2Nat.id in P by assumption. - rewrite <- P. - apply Nat2Z.id. - Qed. - -End ThisShouldBeInCoqLibrary. - -Lemma wordToNat_mod: forall sz (a b: word sz), - b <> $0 -> - #(a ^% b) = #a mod #b. -Proof. - intros. - rewrite <-? wordToN_to_nat in *. - rewrite <-? N2Nat_inj_mod in *. - - rewrite wordToN_mod by assumption. - reflexivity. - - intro. apply H. replace 0%N with (wordToN (natToWord sz 0)) in H0. - + apply wordToN_inj. exact H0. - + erewrite <- wordToN_wzero. reflexivity. -Qed. - -Lemma wlshift_mul_pow2: forall sz n (a: word sz), - wlshift a n = a ^* $ (pow2 n). -Proof. - intros. - apply wordToNat_inj. - unfold wlshift. - rewrite? wordToNat_split1. - unfold eq_rec_r, eq_rec. - rewrite? wordToNat_eq_rect. - rewrite? wordToNat_combine. - rewrite? wordToNat_wzero. - rewrite wordToNat_wmult. - rewrite wordToNat_natToWord_eqn. - rewrite Nat.add_0_l. - rewrite Nat.mul_mod_idemp_r by (apply pow2_ne_zero). - rewrite Nat.mul_comm. - reflexivity. -Qed. - -Lemma wlshift_mul_Zpow2: forall sz n (a: word sz), - (0 <= n)%Z -> - wlshift a (Z.to_nat n) = a ^* ZToWord sz (2 ^ n). -Proof. - intros. rewrite wlshift_mul_pow2. f_equal. - change 2 with (Z.to_nat 2). - rewrite <- Z2Nat_inj_pow by omega. - apply natToWord_Z_to_nat. - apply Z.pow_nonneg. - omega. -Qed. - -Lemma wlshift_distr_plus: forall sz n (a b: word sz), - wlshift (a ^+ b) n = wlshift a n ^+ wlshift b n. -Proof. - intros. - rewrite? wlshift_mul_pow2. - apply wmult_plus_distr. -Qed. - -Lemma wlshift'_distr_plus: forall sz n (a b: word sz), - wlshift' (a ^+ b) n = wlshift' a n ^+ wlshift' b n. -Proof. - intros. rewrite? wlshift_alt. apply wlshift_distr_plus. -Qed. - -Lemma wlshift_iter: forall sz n1 n2 (a: word sz), - wlshift (wlshift a n1) n2 = wlshift a (n1 + n2). -Proof. - intros. rewrite? wlshift_mul_pow2. - rewrite <- wmult_assoc. - rewrite <- natToWord_mult. - do 2 f_equal. - symmetry. - apply Nat.pow_add_r. -Qed. - -Lemma wlshift'_iter: forall sz n1 n2 (a: word sz), - wlshift' (wlshift' a n1) n2 = wlshift' a (n1 + n2). -Proof. - intros. rewrite? wlshift_alt. apply wlshift_iter. -Qed. - -Lemma wlshift_zero: forall sz n, wlshift $0 n = natToWord sz 0. -Proof. - intros. - apply wordToNat_inj. - unfold wlshift. - rewrite? wordToNat_split1. - unfold eq_rec_r, eq_rec. - rewrite? wordToNat_eq_rect. - rewrite? wordToNat_combine. - rewrite? wordToNat_wzero. - rewrite Nat.mul_0_r. - change (0 + 0) with 0. - rewrite Nat.mod_0_l by (apply pow2_ne_zero). - reflexivity. -Qed. - -Lemma wlshift'_zero: forall sz n, wlshift' $0 n = natToWord sz 0. -Proof. - intros. rewrite? wlshift_alt. apply wlshift_zero. -Qed. - -Lemma sext_natToWord_nat_cast: forall sz2 sz1 sz n (e: sz1 + sz2 = sz), - 2 * n < pow2 sz1 -> - nat_cast word e (sext (natToWord sz1 n) sz2) = natToWord sz n. -Proof. - intros. rewrite nat_cast_eq_rect. apply sext_natToWord. assumption. -Qed. - -Lemma sext_neg_natToWord_nat_cast: forall sz2 sz1 sz n (e: sz1 + sz2 = sz), - 2 * n < pow2 sz1 -> - nat_cast word e (sext (wneg (natToWord sz1 n)) sz2) = wneg (natToWord sz n). -Proof. - intros. rewrite nat_cast_eq_rect. apply sext_wneg_natToWord. assumption. -Qed. - -Lemma sext0: forall sz0 sz (v: word sz) (e: sz0 = 0), - sext v sz0 = nat_cast word (eq_ind_r (fun sz0 : nat => sz = sz + sz0) (plus_n_O sz) e) v. -Proof. - intros. subst. - unfold sext. - destruct (wmsb v false) eqn: E; - simpl; rewrite combine_n_0; rewrite <- nat_cast_eq_rect; apply nat_cast_proof_irrel. -Qed. - -Lemma wordToN_wordToZ: forall (sz : nat) (w : word sz), - wordToN w = Z.to_N (wordToZ w + Z.of_N (if wmsb w false then Npow2 sz else 0%N)). -Proof. - intros. - rewrite (wordToZ_wordToN w). - remember (if wmsb w false then Npow2 sz else 0%N) as c; clear Heqc. - rewrite Z.sub_add. - symmetry. - apply N2Z.id. -Qed. - -Lemma uwordToZ_ZToWord_0: forall (z : Z) (sz : nat), - (0 <= z < Z.of_N (Npow2 sz))%Z -> - uwordToZ (ZToWord sz z) = z. -Proof. - intros. - unfold uwordToZ. - pose proof (Z2N.id _ (proj1 H)). - remember (Z.to_N z) as n; clear Heqn. subst z. - apply proj2 in H. - f_equal. - rewrite ZToWord_Z_of_N. - apply wordToN_NToWord_2. - apply N2Z.inj_lt. - assumption. -Qed. - -Lemma uwordToZ_ZToWord: forall (z : Z) (sz : nat), - (0 <= z < 2 ^ (Z.of_nat sz))%Z -> - uwordToZ (ZToWord sz z) = z. -Proof. - intros. apply uwordToZ_ZToWord_0. - intuition idtac. - change 2%Z with (Z.of_nat 2) in H1. - rewrite <- Nat2Z_inj_pow in H1. - rewrite <- N_nat_Z. - rewrite Npow2_nat. - assumption. -Qed. - -Lemma wordToN_neq_0: forall sz (b : word sz), - b <> $0 -> - wordToN b <> 0%N. -Proof. - intros. - intro C. - apply H. - apply wordToN_inj. - erewrite <- wordToN_wzero in C. - unfold wzero in C. - exact C. -Qed. - -(* These counterexamples will hopefully be found by users who use commands - such as "Search ((_ ^+ _) ^% _)" *) -Lemma wmod_plus_distr_does_not_hold: ~ forall sz (a b m: word sz), - m <> $0 -> - (a ^+ b) ^% m = ((a ^% m) ^+ (b ^% m)) ^% m. -Proof. - intro C. - specialize (C 4 $9 $11 $7). cbv in C. - match type of C with (?A -> _) => assert A by (intro; discriminate) end. - specialize (C H). discriminate. -Qed. - -Lemma wmul_mod_distr_does_not_hold: ~ forall sz (a b n: word sz), - n <> $0 -> - (a ^* b) ^% n = ((a ^% n) ^* (b ^% n)) ^% n. -Proof. - intro C. - specialize (C 4 $9 $11 $7). cbv in C. - match type of C with (?A -> _) => assert A by (intro; discriminate) end. - specialize (C H). discriminate. -Qed. - -Lemma Nmod_0_r: forall a : N, (a mod 0)%N = a. -Proof. - intros. destruct a; reflexivity. -Qed. - -Lemma wordToN_0: forall sz, - wordToN (natToWord sz 0) = 0%N. -Proof. - intros. change (natToWord sz 0) with (wzero sz). - apply wordToN_wzero. -Qed. - -Lemma NToWord_0: forall sz, - NToWord sz 0 = $ (0). -Proof. - intros. change 0%nat with (N.to_nat 0). - apply NToWord_nat. -Qed. - -Lemma wmod_0_r: forall sz (a: word sz), a ^% $0 = a. -Proof. - intros. unfold wmod, wordBin. - rewrite wordToN_0. - rewrite Nmod_0_r. - apply NToWord_wordToN. -Qed. - -Lemma wordToN_NToWord_eqn: forall sz (n : N), - wordToN (NToWord sz n) = (n mod Npow2 sz)%N. -Proof. - intros. - pose proof (Npow2_not_zero sz). - apply Nnat.N2Nat.inj. - rewrite wordToN_to_nat. - rewrite N2Nat_inj_mod by assumption. - rewrite Npow2_nat. - rewrite <- wordToNat_natToWord_eqn. - rewrite <- NToWord_nat. - reflexivity. -Qed. - -Lemma Nminus_mod_idemp_r: forall a b n : N, - (n <> 0)%N -> - (b <= a)%N -> - ((a - b mod n) mod n)%N = ((a - b) mod n)%N. -Proof. - intros. - apply N2Z.inj. - rewrite? N2Z.inj_mod by assumption. - pose proof (N.mod_le b n H). - rewrite N2Z.inj_sub by (eapply N.le_trans; eassumption). - rewrite N2Z.inj_sub by assumption. - rewrite? N2Z.inj_mod by assumption. - apply Zdiv.Zminus_mod_idemp_r. -Qed. - -Lemma drop_sub_N: forall sz (n k : N), - (k * Npow2 sz <= n)%N -> - NToWord sz (n - k * Npow2 sz) = NToWord sz n. -Proof. - intros. - apply wordToN_inj. - pose proof (Npow2_not_zero sz). - do 2 rewrite wordToN_NToWord_eqn. - rewrite <- Nminus_mod_idemp_r by assumption. - rewrite N.mod_mul by assumption. - rewrite N.sub_0_r. - reflexivity. -Qed. - -Lemma wmod_divides: forall sz (a b: word sz), - a ^% b = $0 -> - exists k, a = b ^* k. -Proof. - intros. destruct (weq b $0). - - subst b. rewrite wmod_0_r in *. subst a. exists (natToWord sz 0). - symmetry. apply wmult_neut_r. - - unfold wmod, wmult, wordBin in *. - pose proof (N.mod_divides (wordToN a) (wordToN b)) as P. - apply wordToN_neq_0 in n. - specialize (P n). - destruct P as [ [k P] _]. - + apply (f_equal (@wordToN sz)) in H. - rewrite wordToN_NToWord_2 in H. - * rewrite H. apply wordToN_0. - * pose proof (wordToN_bound a). remember (wordToN a) as c. clear Heqc a. - pose proof (wordToN_bound b). remember (wordToN b) as d. clear Heqd b. - pose proof (N.mod_upper_bound c d n). - nomega. - + exists (NToWord sz (k - k / (Npow2 sz) * Npow2 sz)). - rewrite wordToN_NToWord_2. - { rewrite N.mul_sub_distr_l. - rewrite N.mul_assoc. - rewrite drop_sub_N. - - rewrite <- P. symmetry. apply NToWord_wordToN. - - rewrite <- N.mul_assoc. - rewrite <- (N.mul_comm (Npow2 sz)). - apply N.mul_le_mono_l. - apply (N.mul_div_le k (Npow2 sz)). - apply Npow2_not_zero. - } - { rewrite <- N.mul_comm. rewrite <- N.mod_eq by (apply Npow2_not_zero). - apply N.mod_upper_bound. apply Npow2_not_zero. } -Qed. - -Lemma wmod_divides_other_direction_does_not_hold: ~ forall sz (a b: word sz), - b <> $0 -> - (exists k, a = b ^* k) -> - a ^% b = $0. -Proof. - intro C. specialize (C 4 $14 $5). - match type of C with (?A -> _) => assert A by (intro; discriminate) end. - specialize (C H). - match type of C with (?A -> _) => assert A as B end. - - exists (natToWord 4 6). reflexivity. - - specialize (C B). cbv in C. discriminate. -Qed. - -Lemma wmod_mul_does_not_hold: ~ forall sz (a b: word sz), - b <> $0 -> - (a ^* b) ^% b = $0. -Proof. - intro C. - specialize (C 4 $6 $5). - match type of C with (?A -> _) => assert A by (intro; discriminate) end. - specialize (C H). - cbv in C. - discriminate. -Qed. - -Lemma wmult_plus_distr_l: forall (sz : nat) (x y z : word sz), - z ^* (x ^+ y) = z ^* x ^+ z ^* y. -Proof. - intros. rewrite! (wmult_comm z). - apply wmult_plus_distr. -Qed. - -Lemma wmod_same: forall sz (a: word sz), a ^% a = $0. -Proof. - intros. destruct (weq a $0). - - subst a. rewrite wmod_0_r in *. reflexivity. - - unfold wmod, wordBin. apply wordToN_neq_0 in n. rewrite N.mod_same by assumption. - apply NToWord_0. -Qed. - -Lemma wmod_0_l: forall sz (m: word sz), - $0 ^% m = $0. -Proof. - intros. unfold wmod, wordBin. - rewrite wordToN_0. - destruct (N.eq_dec (wordToN m) 0%N). - - rewrite e. change (0 mod 0)%N with 0%N. apply NToWord_0. - - rewrite N.mod_0_l by assumption. apply NToWord_0. -Qed. - -Lemma wmod_plus_distr: forall sz (a b m: word sz), - (exists k, (wordToN m * k)%N = Npow2 sz) -> - (a ^+ b) ^% m = ((a ^% m) ^+ (b ^% m)) ^% m. -Proof. - intros. destruct H as [k E]. - assert (wordToN m <> 0%N) as H. { - intro C. rewrite C in E. simpl in E. symmetry in E. - apply Npow2_not_zero in E. - assumption. - } - unfold wplus, wmod, wordBin. - pose proof (wordToN_bound a). remember (wordToN a) as c. clear Heqc a. - pose proof (wordToN_bound b). remember (wordToN b) as d. clear Heqd b. - pose proof (wordToN_bound m). remember (wordToN m) as n. clear Heqn m. - pose proof (N.mod_upper_bound c n H). - pose proof (N.mod_upper_bound d n H). - rewrite (@wordToN_NToWord_2 sz (c mod n)) by nomega. - rewrite (@wordToN_NToWord_2 sz (d mod n)) by nomega. - repeat match goal with - | |- context [wordToN (NToWord ?sz ?n)] => - let k := fresh "k" in - let E := fresh "E" in - let B := fresh "B" in - destruct (wordToN_NToWord sz n) as [ k [E B] ]; - rewrite E in *; clear E - end. - rewrite <- E in *. - rewrite <- Nminus_mod_idemp_r by assumption. - rewrite <- (@Nminus_mod_idemp_r (c mod n + d mod n)) by assumption. - rewrite (N.mul_comm n k). - do 2 rewrite N.mul_assoc. - do 2 rewrite N.mod_mul by assumption. - do 2 rewrite N.sub_0_r. - f_equal. - apply N.add_mod. - assumption. -Qed. - -Lemma wmod_mul: forall sz (a b: word sz), - (exists k, (wordToN b * k)%N = Npow2 sz) -> - (a ^* b) ^% b = $0. -Proof. - intros. destruct H as [k E]. - assert (wordToN b <> 0%N) as H. { - intro C. rewrite C in E. simpl in E. symmetry in E. - apply Npow2_not_zero in E. - assumption. - } - unfold wmult, wmod, wordBin. - pose proof (wordToN_bound a). remember (wordToN a) as c. clear Heqc a. - pose proof (wordToN_bound b). remember (wordToN b) as d. clear Heqd b. - pose proof (N.mod_upper_bound c d H). - repeat match goal with - | |- context [wordToN (NToWord ?sz ?n)] => - let k := fresh "k" in - let E := fresh "E" in - let B := fresh "B" in - destruct (wordToN_NToWord sz n) as [ k [E B] ]; - rewrite E in *; clear E - end. - rewrite <- E in *. - rewrite <- Nminus_mod_idemp_r by assumption. - rewrite (N.mul_comm d k). - rewrite N.mul_assoc. - rewrite N.mod_mul by assumption. - rewrite N.sub_0_r. - rewrite N.mul_mod by assumption. - rewrite N.mod_same by assumption. - rewrite N.mul_0_r. - rewrite N.mod_0_l by assumption. - apply NToWord_0. -Qed. - -Local Close Scope nat. -Close Scope word_scope. diff --git a/snapshots/coq-riscv/bbv/theories/WordScope.v b/snapshots/coq-riscv/bbv/theories/WordScope.v deleted file mode 100644 index 5d30fdab..00000000 --- a/snapshots/coq-riscv/bbv/theories/WordScope.v +++ /dev/null @@ -1,10 +0,0 @@ -(* Word.v defines notations for words by first opening word_scope, and then closing it again, - to prevent notation clashes. - It does, however, bind word_scope to the type word, so whenever an expression of type word - is expected, it is parsed with notations enabled, but when the expected type is unknown, - word notations don't work by default. - If you want to enable them even for unknown expected types, you can import this file - instead of Word.v. *) - -Require Export bbv.Word. -Open Scope word_scope. diff --git a/snapshots/coq-riscv/bbv/theories/ZLib.v b/snapshots/coq-riscv/bbv/theories/ZLib.v deleted file mode 100644 index 4530df5c..00000000 --- a/snapshots/coq-riscv/bbv/theories/ZLib.v +++ /dev/null @@ -1,25 +0,0 @@ -Require Import Coq.ZArith.BinInt. -Require Import Coq.omega.Omega. - -Local Open Scope Z_scope. - - -Lemma mod2_cases: forall (n: Z), n mod 2 = 0 \/ n mod 2 = 1. -Proof. - intros. pose proof (Z.mod_pos_bound n 2). omega. -Qed. - -Lemma div_mul_undo: forall a b, - b <> 0 -> - a mod b = 0 -> - a / b * b = a. -Proof. - intros. - pose proof Z.div_mul_cancel_l as A. specialize (A a 1 b). - replace (b * 1) with b in A by omega. - rewrite Z.div_1_r in A. - rewrite Z.mul_comm. - rewrite <- Z.divide_div_mul_exact; try assumption. - - apply A; congruence. - - apply Z.mod_divide; assumption. -Qed. diff --git a/snapshots/coq-riscv/build b/snapshots/coq-riscv/build deleted file mode 100755 index 4d89f5d5..00000000 --- a/snapshots/coq-riscv/build +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/bash - -if [ ! -d bbv ]; then - echo Run clean from the coq-riscv directory - exit 1 -fi - -set -ex -cd bbv -make -cd ../sail/lib/coq -make -cd ../../riscv -coqc -R ../../bbv/theories bbv -R ../lib/coq Sail riscv_extras.v -coqc -R ../../bbv/theories bbv -R ../lib/coq Sail riscv_types.v -coqc -R ../../bbv/theories bbv -R ../lib/coq Sail riscv.v diff --git a/snapshots/coq-riscv/clean b/snapshots/coq-riscv/clean deleted file mode 100755 index 9b161fd2..00000000 --- a/snapshots/coq-riscv/clean +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/bash - -if [ ! -d bbv ]; then - echo Run clean from the coq-riscv directory - exit 1 -fi - -set -ex -rm -f sail/riscv/*.vo -cd sail/lib/coq -make clean -cd ../../../bbv -make clean diff --git a/snapshots/coq-riscv/sail/lib/coq/.gitignore b/snapshots/coq-riscv/sail/lib/coq/.gitignore deleted file mode 100644 index 1aa62803..00000000 --- a/snapshots/coq-riscv/sail/lib/coq/.gitignore +++ /dev/null @@ -1 +0,0 @@ -deps \ No newline at end of file diff --git a/snapshots/coq-riscv/sail/lib/coq/Makefile b/snapshots/coq-riscv/sail/lib/coq/Makefile deleted file mode 100644 index 99321aae..00000000 --- a/snapshots/coq-riscv/sail/lib/coq/Makefile +++ /dev/null @@ -1,24 +0,0 @@ -BBV_DIR=../../../bbv/theories - -SRC=Sail2_prompt_monad.v Sail2_prompt.v Sail2_impl_base.v Sail2_instr_kinds.v Sail2_operators_bitlists.v Sail2_operators_mwords.v Sail2_operators.v Sail2_values.v Sail2_state_monad.v Sail2_state.v Sail2_string.v - -COQ_LIBS = -R . Sail -R "$(BBV_DIR)" bbv - -TARGETS=$(SRC:.v=.vo) - -.PHONY: all clean *.ide - -all: $(TARGETS) -clean: - rm -f -- $(TARGETS) $(TARGETS:.vo=.glob) $(TARGETS:%.vo=.%.aux) deps - -%.vo: %.v - coqc $(COQ_LIBS) $< - -%.ide: %.v - coqide $(COQ_LIBS) $< - -deps: $(SRC) - coqdep $(COQ_LIBS) $(SRC) > deps - --include deps diff --git a/snapshots/coq-riscv/sail/lib/coq/Sail2_impl_base.v b/snapshots/coq-riscv/sail/lib/coq/Sail2_impl_base.v deleted file mode 100644 index 464c2902..00000000 --- a/snapshots/coq-riscv/sail/lib/coq/Sail2_impl_base.v +++ /dev/null @@ -1,1103 +0,0 @@ -(*========================================================================*) -(* Sail *) -(* *) -(* Copyright (c) 2013-2017 *) -(* Kathyrn Gray *) -(* Shaked Flur *) -(* Stephen Kell *) -(* Gabriel Kerneis *) -(* Robert Norton-Wright *) -(* Christopher Pulte *) -(* Peter Sewell *) -(* Alasdair Armstrong *) -(* Brian Campbell *) -(* Thomas Bauereiss *) -(* Anthony Fox *) -(* Jon French *) -(* Dominic Mulligan *) -(* Stephen Kell *) -(* Mark Wassell *) -(* *) -(* All rights reserved. *) -(* *) -(* This software was developed by the University of Cambridge Computer *) -(* Laboratory as part of the Rigorous Engineering of Mainstream Systems *) -(* (REMS) project, funded by EPSRC grant EP/K008528/1. *) -(* *) -(* Redistribution and use in source and binary forms, with or without *) -(* modification, are permitted provided that the following conditions *) -(* are met: *) -(* 1. Redistributions of source code must retain the above copyright *) -(* notice, this list of conditions and the following disclaimer. *) -(* 2. Redistributions in binary form must reproduce the above copyright *) -(* notice, this list of conditions and the following disclaimer in *) -(* the documentation and/or other materials provided with the *) -(* distribution. *) -(* *) -(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *) -(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *) -(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *) -(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *) -(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *) -(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *) -(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *) -(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *) -(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *) -(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *) -(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *) -(* SUCH DAMAGE. *) -(*========================================================================*) - -Require Import Sail2_instr_kinds. - -(* -class ( EnumerationType 'a ) - val toNat : 'a -> nat -end - - -val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> ordering -let ~{ocaml} enumeration_typeCompare e1 e2 = - compare (toNat e1) (toNat e2) -let inline {ocaml} enumeration_typeCompare = defaultCompare - - -default_instance forall 'a. EnumerationType 'a => (Ord 'a) - let compare = enumeration_typeCompare - let (<) r1 r2 = (enumeration_typeCompare r1 r2) = LT - let (<=) r1 r2 = (enumeration_typeCompare r1 r2) <> GT - let (>) r1 r2 = (enumeration_typeCompare r1 r2) = GT - let (>=) r1 r2 = (enumeration_typeCompare r1 r2) <> LT -end - - - -(* maybe isn't a member of type Ord - this should be in the Lem standard library*) -instance forall 'a. Ord 'a => (Ord (maybe 'a)) - let compare = maybeCompare compare - let (<) r1 r2 = (maybeCompare compare r1 r2) = LT - let (<=) r1 r2 = (maybeCompare compare r1 r2) <> GT - let (>) r1 r2 = (maybeCompare compare r1 r2) = GT - let (>=) r1 r2 = (maybeCompare compare r1 r2) <> LT -end - -type word8 = nat (* bounded at a byte, for when lem supports it*) - -type end_flag = - | E_big_endian - | E_little_endian - -type bit = - | Bitc_zero - | Bitc_one - -type bit_lifted = - | Bitl_zero - | Bitl_one - | Bitl_undef (* used for modelling h/w arch unspecified bits *) - | Bitl_unknown (* used for interpreter analysis exhaustive execution *) - -type direction = - | D_increasing - | D_decreasing - -let dir_of_bool is_inc = if is_inc then D_increasing else D_decreasing -let bool_of_dir = function - | D_increasing -> true - | D_decreasing -> false - end - -(* at some point this should probably not mention bit_lifted anymore *) -type register_value = <| - rv_bits: list bit_lifted (* MSB first, smallest index number *); - rv_dir: direction; - rv_start: nat ; - rv_start_internal: nat; - (*when dir is increasing, rv_start = rv_start_internal. - Otherwise, tells interpreter how to reconstruct a proper decreasing value*) - |> - -type byte_lifted = Byte_lifted of list bit_lifted (* of length 8 *) (*MSB first everywhere*) - -type instruction_field_value = list bit - -type byte = Byte of list bit (* of length 8 *) (*MSB first everywhere*) - -type address_lifted = Address_lifted of list byte_lifted (* of length 8 for 64bit machines*) * maybe integer -(* for both values of end_flag, MSBy first *) - -type memory_byte = byte_lifted (* of length 8 *) (*MSB first everywhere*) - -type memory_value = list memory_byte -(* the list is of length >=1 *) -(* the head of the list is the byte stored at the lowest address; -when calling a Sail function with a wmv effect, the least significant 8 -bits of the bit vector passed to the function will be interpreted as -the lowest address byte; similarly, when calling a Sail function with -rmem effect, the lowest address byte will be placed in the least -significant 8 bits of the bit vector returned by the function; this -behaviour is consistent with little-endian. *) - - -(* not sure which of these is more handy yet *) -type address = Address of list byte (* of length 8 *) * integer -(* type address = Address of integer *) - -type opcode = Opcode of list byte (* of length 4 *) - -(** typeclass instantiations *) - -instance (EnumerationType bit) - let toNat = function - | Bitc_zero -> 0 - | Bitc_one -> 1 - end -end - -instance (EnumerationType bit_lifted) - let toNat = function - | Bitl_zero -> 0 - | Bitl_one -> 1 - | Bitl_undef -> 2 - | Bitl_unknown -> 3 - end -end - -let ~{ocaml} byte_liftedCompare (Byte_lifted b1) (Byte_lifted b2) = compare b1 b2 -let inline {ocaml} byte_liftedCompare = defaultCompare - -let ~{ocaml} byte_liftedLess b1 b2 = byte_liftedCompare b1 b2 = LT -let ~{ocaml} byte_liftedLessEq b1 b2 = byte_liftedCompare b1 b2 <> GT -let ~{ocaml} byte_liftedGreater b1 b2 = byte_liftedCompare b1 b2 = GT -let ~{ocaml} byte_liftedGreaterEq b1 b2 = byte_liftedCompare b1 b2 <> LT - -let inline {ocaml} byte_liftedLess = defaultLess -let inline {ocaml} byte_liftedLessEq = defaultLessEq -let inline {ocaml} byte_liftedGreater = defaultGreater -let inline {ocaml} byte_liftedGreaterEq = defaultGreaterEq - -instance (Ord byte_lifted) - let compare = byte_liftedCompare - let (<) = byte_liftedLess - let (<=) = byte_liftedLessEq - let (>) = byte_liftedGreater - let (>=) = byte_liftedGreaterEq -end - -let ~{ocaml} byteCompare (Byte b1) (Byte b2) = compare b1 b2 -let inline {ocaml} byteCompare = defaultCompare - -let ~{ocaml} byteLess b1 b2 = byteCompare b1 b2 = LT -let ~{ocaml} byteLessEq b1 b2 = byteCompare b1 b2 <> GT -let ~{ocaml} byteGreater b1 b2 = byteCompare b1 b2 = GT -let ~{ocaml} byteGreaterEq b1 b2 = byteCompare b1 b2 <> LT - -let inline {ocaml} byteLess = defaultLess -let inline {ocaml} byteLessEq = defaultLessEq -let inline {ocaml} byteGreater = defaultGreater -let inline {ocaml} byteGreaterEq = defaultGreaterEq - -instance (Ord byte) - let compare = byteCompare - let (<) = byteLess - let (<=) = byteLessEq - let (>) = byteGreater - let (>=) = byteGreaterEq -end - - - - - -let ~{ocaml} opcodeCompare (Opcode o1) (Opcode o2) = - compare o1 o2 -let {ocaml} opcodeCompare = defaultCompare - -let ~{ocaml} opcodeLess b1 b2 = opcodeCompare b1 b2 = LT -let ~{ocaml} opcodeLessEq b1 b2 = opcodeCompare b1 b2 <> GT -let ~{ocaml} opcodeGreater b1 b2 = opcodeCompare b1 b2 = GT -let ~{ocaml} opcodeGreaterEq b1 b2 = opcodeCompare b1 b2 <> LT - -let inline {ocaml} opcodeLess = defaultLess -let inline {ocaml} opcodeLessEq = defaultLessEq -let inline {ocaml} opcodeGreater = defaultGreater -let inline {ocaml} opcodeGreaterEq = defaultGreaterEq - -instance (Ord opcode) - let compare = opcodeCompare - let (<) = opcodeLess - let (<=) = opcodeLessEq - let (>) = opcodeGreater - let (>=) = opcodeGreaterEq -end - -let addressCompare (Address b1 i1) (Address b2 i2) = compare i1 i2 -(* this cannot be defaultCompare for OCaml because addresses contain big ints *) - -let addressLess b1 b2 = addressCompare b1 b2 = LT -let addressLessEq b1 b2 = addressCompare b1 b2 <> GT -let addressGreater b1 b2 = addressCompare b1 b2 = GT -let addressGreaterEq b1 b2 = addressCompare b1 b2 <> LT - -instance (SetType address) - let setElemCompare = addressCompare -end - -instance (Ord address) - let compare = addressCompare - let (<) = addressLess - let (<=) = addressLessEq - let (>) = addressGreater - let (>=) = addressGreaterEq -end - -let {coq; ocaml} addressEqual a1 a2 = (addressCompare a1 a2) = EQ -let inline {hol; isabelle} addressEqual = unsafe_structural_equality - -let {coq; ocaml} addressInequal a1 a2 = not (addressEqual a1 a2) -let inline {hol; isabelle} addressInequal = unsafe_structural_inequality - -instance (Eq address) - let (=) = addressEqual - let (<>) = addressInequal -end - -let ~{ocaml} directionCompare d1 d2 = - match (d1, d2) with - | (D_decreasing, D_increasing) -> GT - | (D_increasing, D_decreasing) -> LT - | _ -> EQ - end -let inline {ocaml} directionCompare = defaultCompare - -let ~{ocaml} directionLess b1 b2 = directionCompare b1 b2 = LT -let ~{ocaml} directionLessEq b1 b2 = directionCompare b1 b2 <> GT -let ~{ocaml} directionGreater b1 b2 = directionCompare b1 b2 = GT -let ~{ocaml} directionGreaterEq b1 b2 = directionCompare b1 b2 <> LT - -let inline {ocaml} directionLess = defaultLess -let inline {ocaml} directionLessEq = defaultLessEq -let inline {ocaml} directionGreater = defaultGreater -let inline {ocaml} directionGreaterEq = defaultGreaterEq - -instance (Ord direction) - let compare = directionCompare - let (<) = directionLess - let (<=) = directionLessEq - let (>) = directionGreater - let (>=) = directionGreaterEq -end - -instance (Show direction) - let show = function D_increasing -> "D_increasing" | D_decreasing -> "D_decreasing" end -end - -let ~{ocaml} register_valueCompare rv1 rv2 = - compare (rv1.rv_bits, rv1.rv_dir, rv1.rv_start, rv1.rv_start_internal) - (rv2.rv_bits, rv2.rv_dir, rv2.rv_start, rv2.rv_start_internal) -let inline {ocaml} register_valueCompare = defaultCompare - -let ~{ocaml} register_valueLess b1 b2 = register_valueCompare b1 b2 = LT -let ~{ocaml} register_valueLessEq b1 b2 = register_valueCompare b1 b2 <> GT -let ~{ocaml} register_valueGreater b1 b2 = register_valueCompare b1 b2 = GT -let ~{ocaml} register_valueGreaterEq b1 b2 = register_valueCompare b1 b2 <> LT - -let inline {ocaml} register_valueLess = defaultLess -let inline {ocaml} register_valueLessEq = defaultLessEq -let inline {ocaml} register_valueGreater = defaultGreater -let inline {ocaml} register_valueGreaterEq = defaultGreaterEq - -instance (Ord register_value) - let compare = register_valueCompare - let (<) = register_valueLess - let (<=) = register_valueLessEq - let (>) = register_valueGreater - let (>=) = register_valueGreaterEq -end - -let address_liftedCompare (Address_lifted b1 i1) (Address_lifted b2 i2) = - compare (i1,b1) (i2,b2) -(* this cannot be defaultCompare for OCaml because address_lifteds contain big - ints *) - -let address_liftedLess b1 b2 = address_liftedCompare b1 b2 = LT -let address_liftedLessEq b1 b2 = address_liftedCompare b1 b2 <> GT -let address_liftedGreater b1 b2 = address_liftedCompare b1 b2 = GT -let address_liftedGreaterEq b1 b2 = address_liftedCompare b1 b2 <> LT - -instance (Ord address_lifted) - let compare = address_liftedCompare - let (<) = address_liftedLess - let (<=) = address_liftedLessEq - let (>) = address_liftedGreater - let (>=) = address_liftedGreaterEq -end - -(* Registers *) -type slice = (nat * nat) - -type reg_name = - (* do we really need this here if ppcmem already has this information by itself? *) -| Reg of string * nat * nat * direction -(*Name of the register, accessing the entire register, the start and size of this register, and its direction *) - -| Reg_slice of string * nat * direction * slice -(* Name of the register, accessing from the bit indexed by the first -to the bit indexed by the second integer of the slice, inclusive. For -machineDef* the first is a smaller number or equal to the second, adjusted -to reflect the correct span direction in the interpreter side. *) - -| Reg_field of string * nat * direction * string * slice -(*Name of the register, start and direction, and name of the field of the register -accessed. The slice specifies where this field is in the register*) - -| Reg_f_slice of string * nat * direction * string * slice * slice -(* The first four components are as in Reg_field; the final slice -specifies a part of the field, indexed w.r.t. the register as a whole *) - -let register_base_name : reg_name -> string = function - | Reg s _ _ _ -> s - | Reg_slice s _ _ _ -> s - | Reg_field s _ _ _ _ -> s - | Reg_f_slice s _ _ _ _ _ -> s - end - -let slice_of_reg_name : reg_name -> slice = function - | Reg _ start width D_increasing -> (start, start + width -1) - | Reg _ start width D_decreasing -> (start - width - 1, start) - | Reg_slice _ _ _ sl -> sl - | Reg_field _ _ _ _ sl -> sl - | Reg_f_slice _ _ _ _ _ sl -> sl - end - -let width_of_reg_name (r: reg_name) : nat = - let width_of_slice (i, j) = (* j - i + 1 in *) - - (integerFromNat j) - (integerFromNat i) + 1 - $> abs $> natFromInteger - in - match r with - | Reg _ _ width _ -> width - | Reg_slice _ _ _ sl -> width_of_slice sl - | Reg_field _ _ _ _ sl -> width_of_slice sl - | Reg_f_slice _ _ _ _ _ sl -> width_of_slice sl - end - -let reg_name_non_empty_intersection (r: reg_name) (r': reg_name) : bool = - register_base_name r = register_base_name r' && - let (i1, i2) = slice_of_reg_name r in - let (i1', i2') = slice_of_reg_name r' in - i1' <= i2 && i2' >= i1 - -let reg_nameCompare r1 r2 = - compare (register_base_name r1,slice_of_reg_name r1) - (register_base_name r2,slice_of_reg_name r2) - -let reg_nameLess b1 b2 = reg_nameCompare b1 b2 = LT -let reg_nameLessEq b1 b2 = reg_nameCompare b1 b2 <> GT -let reg_nameGreater b1 b2 = reg_nameCompare b1 b2 = GT -let reg_nameGreaterEq b1 b2 = reg_nameCompare b1 b2 <> LT - -instance (Ord reg_name) - let compare = reg_nameCompare - let (<) = reg_nameLess - let (<=) = reg_nameLessEq - let (>) = reg_nameGreater - let (>=) = reg_nameGreaterEq -end - -let {coq;ocaml} reg_nameEqual a1 a2 = (reg_nameCompare a1 a2) = EQ -let {hol;isabelle} reg_nameEqual = unsafe_structural_equality -let {coq;ocaml} reg_nameInequal a1 a2 = not (reg_nameEqual a1 a2) -let {hol;isabelle} reg_nameInequal = unsafe_structural_inequality - -instance (Eq reg_name) - let (=) = reg_nameEqual - let (<>) = reg_nameInequal -end - -instance (SetType reg_name) - let setElemCompare = reg_nameCompare -end - -let direction_of_reg_name r = match r with - | Reg _ _ _ d -> d - | Reg_slice _ _ d _ -> d - | Reg_field _ _ d _ _ -> d - | Reg_f_slice _ _ d _ _ _ -> d - end - -let start_of_reg_name r = match r with - | Reg _ start _ _ -> start - | Reg_slice _ start _ _ -> start - | Reg_field _ start _ _ _ -> start - | Reg_f_slice _ start _ _ _ _ -> start -end - -(* Data structures for building up instructions *) - -(* read_kind, write_kind, barrier_kind, trans_kind and instruction_kind have - been moved to sail_instr_kinds.lem. This removes the dependency of the - shallow embedding on the rest of sail_impl_base.lem, and helps avoid name - clashes between the different monad types. *) - -type event = - | E_read_mem of read_kind * address_lifted * nat * maybe (list reg_name) - | E_read_memt of read_kind * address_lifted * nat * maybe (list reg_name) - | E_write_mem of write_kind * address_lifted * nat * maybe (list reg_name) * memory_value * maybe (list reg_name) - | E_write_ea of write_kind * address_lifted * nat * maybe (list reg_name) - | E_excl_res - | E_write_memv of maybe address_lifted * memory_value * maybe (list reg_name) - | E_write_memvt of maybe address_lifted * (bit_lifted * memory_value) * maybe (list reg_name) - | E_barrier of barrier_kind - | E_footprint - | E_read_reg of reg_name - | E_write_reg of reg_name * register_value - | E_escape - | E_error of string - - -let eventCompare e1 e2 = - match (e1,e2) with - | (E_read_mem rk1 v1 i1 tr1, E_read_mem rk2 v2 i2 tr2) -> - compare (rk1, (v1,i1,tr1)) (rk2,(v2, i2, tr2)) - | (E_read_memt rk1 v1 i1 tr1, E_read_memt rk2 v2 i2 tr2) -> - compare (rk1, (v1,i1,tr1)) (rk2,(v2, i2, tr2)) - | (E_write_mem wk1 v1 i1 tr1 v1' tr1', E_write_mem wk2 v2 i2 tr2 v2' tr2') -> - compare ((wk1,v1,i1),(tr1,v1',tr1')) ((wk2,v2,i2),(tr2,v2',tr2')) - | (E_write_ea wk1 a1 i1 tr1, E_write_ea wk2 a2 i2 tr2) -> - compare (wk1, (a1, i1, tr1)) (wk2, (a2, i2, tr2)) - | (E_excl_res, E_excl_res) -> EQ - | (E_write_memv _ mv1 tr1, E_write_memv _ mv2 tr2) -> compare (mv1,tr1) (mv2,tr2) - | (E_write_memvt _ mv1 tr1, E_write_memvt _ mv2 tr2) -> compare (mv1,tr1) (mv2,tr2) - | (E_barrier bk1, E_barrier bk2) -> compare bk1 bk2 - | (E_read_reg r1, E_read_reg r2) -> compare r1 r2 - | (E_write_reg r1 v1, E_write_reg r2 v2) -> compare (r1,v1) (r2,v2) - | (E_error s1, E_error s2) -> compare s1 s2 - | (E_escape,E_escape) -> EQ - | (E_read_mem _ _ _ _, _) -> LT - | (E_write_mem _ _ _ _ _ _, _) -> LT - | (E_write_ea _ _ _ _, _) -> LT - | (E_excl_res, _) -> LT - | (E_write_memv _ _ _, _) -> LT - | (E_barrier _, _) -> LT - | (E_read_reg _, _) -> LT - | (E_write_reg _ _, _) -> LT - | _ -> GT - end - -let eventLess b1 b2 = eventCompare b1 b2 = LT -let eventLessEq b1 b2 = eventCompare b1 b2 <> GT -let eventGreater b1 b2 = eventCompare b1 b2 = GT -let eventGreaterEq b1 b2 = eventCompare b1 b2 <> LT - -instance (Ord event) - let compare = eventCompare - let (<) = eventLess - let (<=) = eventLessEq - let (>) = eventGreater - let (>=) = eventGreaterEq -end - -instance (SetType event) - let setElemCompare = compare -end - - -(* the address_lifted types should go away here and be replaced by address *) -type with_aux 'o = 'o * maybe ((unit -> (string * string)) * ((list (reg_name * register_value)) -> list event)) -type outcome 'a 'e = - (* Request to read memory, value is location to read, integer is size to read, - followed by registers that were used in computing that size *) - | Read_mem of (read_kind * address_lifted * nat) * (memory_value -> with_aux (outcome 'a 'e)) - (* Tell the system a write is imminent, at address lifted, of size nat *) - | Write_ea of (write_kind * address_lifted * nat) * (with_aux (outcome 'a 'e)) - (* Request the result of store-exclusive *) - | Excl_res of (bool -> with_aux (outcome 'a 'e)) - (* Request to write memory at last signalled address. Memory value should be 8 - times the size given in ea signal *) - | Write_memv of memory_value * (bool -> with_aux (outcome 'a 'e)) - (* Request a memory barrier *) - | Barrier of barrier_kind * with_aux (outcome 'a 'e) - (* Tell the system to dynamically recalculate dependency footprint *) - | Footprint of with_aux (outcome 'a 'e) - (* Request to read register, will track dependency when mode.track_values *) - | Read_reg of reg_name * (register_value -> with_aux (outcome 'a 'e)) - (* Request to write register *) - | Write_reg of (reg_name * register_value) * with_aux (outcome 'a 'e) - | Escape of maybe string - (*Result of a failed assert with possible error message to report*) - | Fail of maybe string - (* Exception of type 'e *) - | Exception of 'e - | Internal of (maybe string * maybe (unit -> string)) * with_aux (outcome 'a 'e) - | Done of 'a - | Error of string - -type outcome_s 'a 'e = with_aux (outcome 'a 'e) -(* first string : output of instruction_stack_to_string - second string: output of local_variables_to_string *) - -(** operations and coercions on basic values *) - -val word8_to_bitls : word8 -> list bit_lifted -val bitls_to_word8 : list bit_lifted -> word8 - -val integer_of_word8_list : list word8 -> integer -val word8_list_of_integer : integer -> integer -> list word8 - -val concretizable_bitl : bit_lifted -> bool -val concretizable_bytl : byte_lifted -> bool -val concretizable_bytls : list byte_lifted -> bool - -let concretizable_bitl = function - | Bitl_zero -> true - | Bitl_one -> true - | Bitl_undef -> false - | Bitl_unknown -> false -end - -let concretizable_bytl (Byte_lifted bs) = List.all concretizable_bitl bs -let concretizable_bytls = List.all concretizable_bytl - -(* constructing values *) - -val build_register_value : list bit_lifted -> direction -> nat -> nat -> register_value -let build_register_value bs dir width start_index = - <| rv_bits = bs; - rv_dir = dir; (* D_increasing for Power, D_decreasing for ARM *) - rv_start_internal = start_index; - rv_start = if dir = D_increasing - then start_index - else (start_index+1) - width; (* Smaller index, as in Power, for external interaction *) - |> - -val register_value : bit_lifted -> direction -> nat -> nat -> register_value -let register_value b dir width start_index = - build_register_value (List.replicate width b) dir width start_index - -val register_value_zeros : direction -> nat -> nat -> register_value -let register_value_zeros dir width start_index = - register_value Bitl_zero dir width start_index - -val register_value_ones : direction -> nat -> nat -> register_value -let register_value_ones dir width start_index = - register_value Bitl_one dir width start_index - -val register_value_for_reg : reg_name -> list bit_lifted -> register_value -let register_value_for_reg r bs : register_value = - let () = ensure (width_of_reg_name r = List.length bs) - ("register_value_for_reg (\"" ^ show (register_base_name r) ^ "\") length mismatch: " - ^ show (width_of_reg_name r) ^ " vs " ^ show (List.length bs)) - in - let (j1, j2) = slice_of_reg_name r in - let d = direction_of_reg_name r in - <| rv_bits = bs; - rv_dir = d; - rv_start_internal = if d = D_increasing then j1 else (start_of_reg_name r) - j1; - rv_start = j1; - |> - -val byte_lifted_undef : byte_lifted -let byte_lifted_undef = Byte_lifted (List.replicate 8 Bitl_undef) - -val byte_lifted_unknown : byte_lifted -let byte_lifted_unknown = Byte_lifted (List.replicate 8 Bitl_unknown) - -val memory_value_unknown : nat (*the number of bytes*) -> memory_value -let memory_value_unknown (width:nat) : memory_value = - List.replicate width byte_lifted_unknown - -val memory_value_undef : nat (*the number of bytes*) -> memory_value -let memory_value_undef (width:nat) : memory_value = - List.replicate width byte_lifted_undef - -val match_endianness : forall 'a. end_flag -> list 'a -> list 'a -let match_endianness endian l = - match endian with - | E_little_endian -> List.reverse l - | E_big_endian -> l - end - -(* lengths *) - -val memory_value_length : memory_value -> nat -let memory_value_length (mv:memory_value) = List.length mv - - -(* aux fns *) - -val maybe_all : forall 'a. list (maybe 'a) -> maybe (list 'a) -let rec maybe_all' xs acc = - match xs with - | [] -> Just (List.reverse acc) - | Nothing :: _ -> Nothing - | (Just y)::xs' -> maybe_all' xs' (y::acc) - end -let maybe_all xs = maybe_all' xs [] - -(** coercions *) - -(* bits and bytes *) - -let bit_to_bool = function (* TODO: rename bool_of_bit *) - | Bitc_zero -> false - | Bitc_one -> true -end - - -val bit_lifted_of_bit : bit -> bit_lifted -let bit_lifted_of_bit b = - match b with - | Bitc_zero -> Bitl_zero - | Bitc_one -> Bitl_one - end - -val bit_of_bit_lifted : bit_lifted -> maybe bit -let bit_of_bit_lifted bl = - match bl with - | Bitl_zero -> Just Bitc_zero - | Bitl_one -> Just Bitc_one - | Bitl_undef -> Nothing - | Bitl_unknown -> Nothing - end - - -val byte_lifted_of_byte : byte -> byte_lifted -let byte_lifted_of_byte (Byte bs) : byte_lifted = Byte_lifted (List.map bit_lifted_of_bit bs) - -val byte_of_byte_lifted : byte_lifted -> maybe byte -let byte_of_byte_lifted bl = - match bl with - | Byte_lifted bls -> - match maybe_all (List.map bit_of_bit_lifted bls) with - | Nothing -> Nothing - | Just bs -> Just (Byte bs) - end - end - - -val bytes_of_bits : list bit -> list byte (*assumes (length bits) mod 8 = 0*) -let rec bytes_of_bits bits = match bits with - | [] -> [] - | b0::b1::b2::b3::b4::b5::b6::b7::bits -> - (Byte [b0;b1;b2;b3;b4;b5;b6;b7])::(bytes_of_bits bits) - | _ -> failwith "bytes_of_bits not given bits divisible by 8" -end - -val byte_lifteds_of_bit_lifteds : list bit_lifted -> list byte_lifted (*assumes (length bits) mod 8 = 0*) -let rec byte_lifteds_of_bit_lifteds bits = match bits with - | [] -> [] - | b0::b1::b2::b3::b4::b5::b6::b7::bits -> - (Byte_lifted [b0;b1;b2;b3;b4;b5;b6;b7])::(byte_lifteds_of_bit_lifteds bits) - | _ -> failwith "byte_lifteds of bit_lifteds not given bits divisible by 8" -end - - -val byte_of_memory_byte : memory_byte -> maybe byte -let byte_of_memory_byte = byte_of_byte_lifted - -val memory_byte_of_byte : byte -> memory_byte -let memory_byte_of_byte = byte_lifted_of_byte - - -(* to and from nat *) - -(* this natFromBoolList could move to the Lem word.lem library *) -val natFromBoolList : list bool -> nat -let rec natFromBoolListAux (acc : nat) (bl : list bool) = - match bl with - | [] -> acc - | (true :: bl') -> natFromBoolListAux ((acc * 2) + 1) bl' - | (false :: bl') -> natFromBoolListAux (acc * 2) bl' - end -let natFromBoolList bl = - natFromBoolListAux 0 (List.reverse bl) - - -val nat_of_bit_list : list bit -> nat -let nat_of_bit_list b = - natFromBoolList (List.reverse (List.map bit_to_bool b)) - (* natFromBoolList takes a list with LSB first, for consistency with rest of Lem word library, so we reverse it. twice. *) - - -(* to and from integer *) - -val integer_of_bit_list : list bit -> integer -let integer_of_bit_list b = - integerFromBoolList (false,(List.reverse (List.map bit_to_bool b))) - (* integerFromBoolList takes a list with LSB first, so we reverse it *) - -val bit_list_of_integer : nat -> integer -> list bit -let bit_list_of_integer len b = - List.map (fun b -> if b then Bitc_one else Bitc_zero) - (reverse (boolListFrombitSeq len (bitSeqFromInteger Nothing b))) - -val integer_of_byte_list : list byte -> integer -let integer_of_byte_list bytes = integer_of_bit_list (List.concatMap (fun (Byte bs) -> bs) bytes) - -val byte_list_of_integer : nat -> integer -> list byte -let byte_list_of_integer (len:nat) (a:integer):list byte = - let bits = bit_list_of_integer (len * 8) a in bytes_of_bits bits - - -val integer_of_address : address -> integer -let integer_of_address (a:address):integer = - match a with - | Address bs i -> i - end - -val address_of_integer : integer -> address -let address_of_integer (i:integer):address = - Address (byte_list_of_integer 8 i) i - -(* to and from signed-integer *) - -val signed_integer_of_bit_list : list bit -> integer -let signed_integer_of_bit_list b = - match b with - | [] -> failwith "empty bit list" - | Bitc_zero :: b' -> - integerFromBoolList (false,(List.reverse (List.map bit_to_bool b))) - | Bitc_one :: b' -> - let b'_val = integerFromBoolList (false,(List.reverse (List.map bit_to_bool b'))) in - (* integerFromBoolList takes a list with LSB first, so we reverse it *) - let msb_val = integerPow 2 ((List.length b) - 1) in - b'_val - msb_val - end - - -(* regarding a list of int as a list of bytes in memory, MSB lowest-address first, convert to an integer *) -val integer_address_of_int_list : list int -> integer -let rec integerFromIntListAux (acc: integer) (is: list int) = - match is with - | [] -> acc - | (i :: is') -> integerFromIntListAux ((acc * 256) + integerFromInt i) is' - end -let integer_address_of_int_list (is: list int) = - integerFromIntListAux 0 is - -val address_of_byte_list : list byte -> address -let address_of_byte_list bs = - if List.length bs <> 8 then failwith "address_of_byte_list given list not of length 8" else - Address bs (integer_of_byte_list bs) - -let address_of_byte_lifted_list bls = - match maybe_all (List.map byte_of_byte_lifted bls) with - | Nothing -> Nothing - | Just bs -> Just (address_of_byte_list bs) - end - -(* operations on addresses *) - -val add_address_nat : address -> nat -> address -let add_address_nat (a:address) (i:nat) : address = - address_of_integer ((integer_of_address a) + (integerFromNat i)) - -val clear_low_order_bits_of_address : address -> address -let clear_low_order_bits_of_address a = - match a with - | Address [b0;b1;b2;b3;b4;b5;b6;b7] i -> - match b7 with - | Byte [bt0;bt1;bt2;bt3;bt4;bt5;bt6;bt7] -> - let b7' = Byte [bt0;bt1;bt2;bt3;bt4;bt5;Bitc_zero;Bitc_zero] in - let bytes = [b0;b1;b2;b3;b4;b5;b6;b7'] in - Address bytes (integer_of_byte_list bytes) - | _ -> failwith "Byte does not contain 8 bits" - end - | _ -> failwith "Address does not contain 8 bytes" - end - - - -val byte_list_of_memory_value : end_flag -> memory_value -> maybe (list byte) -let byte_list_of_memory_value endian mv = - match_endianness endian mv - $> List.map byte_of_memory_byte - $> maybe_all - - -val integer_of_memory_value : end_flag -> memory_value -> maybe integer -let integer_of_memory_value endian (mv:memory_value):maybe integer = - match byte_list_of_memory_value endian mv with - | Just bs -> Just (integer_of_byte_list bs) - | Nothing -> Nothing - end - -val memory_value_of_integer : end_flag -> nat -> integer -> memory_value -let memory_value_of_integer endian (len:nat) (i:integer):memory_value = - List.map byte_lifted_of_byte (byte_list_of_integer len i) - $> match_endianness endian - - -val integer_of_register_value : register_value -> maybe integer -let integer_of_register_value (rv:register_value):maybe integer = - match maybe_all (List.map bit_of_bit_lifted rv.rv_bits) with - | Nothing -> Nothing - | Just bs -> Just (integer_of_bit_list bs) - end - -(* NOTE: register_value_for_reg_of_integer might be easier to use *) -val register_value_of_integer : nat -> nat -> direction -> integer -> register_value -let register_value_of_integer (len:nat) (start:nat) (dir:direction) (i:integer):register_value = - let bs = bit_list_of_integer len i in - build_register_value (List.map bit_lifted_of_bit bs) dir len start - -val register_value_for_reg_of_integer : reg_name -> integer -> register_value -let register_value_for_reg_of_integer (r: reg_name) (i:integer) : register_value = - register_value_of_integer (width_of_reg_name r) (start_of_reg_name r) (direction_of_reg_name r) i - -(* *) - -val opcode_of_bytes : byte -> byte -> byte -> byte -> opcode -let opcode_of_bytes b0 b1 b2 b3 : opcode = Opcode [b0;b1;b2;b3] - -val register_value_of_address : address -> direction -> register_value -let register_value_of_address (Address bytes _) dir : register_value = - let bits = List.concatMap (fun (Byte bs) -> List.map bit_lifted_of_bit bs) bytes in - <| rv_bits = bits; - rv_dir = dir; - rv_start = 0; - rv_start_internal = if dir = D_increasing then 0 else (List.length bits) - 1 - |> - -val register_value_of_memory_value : memory_value -> direction -> register_value -let register_value_of_memory_value bytes dir : register_value = - let bitls = List.concatMap (fun (Byte_lifted bs) -> bs) bytes in - <| rv_bits = bitls; - rv_dir = dir; - rv_start = 0; - rv_start_internal = if dir = D_increasing then 0 else (List.length bitls) - 1 - |> - -val memory_value_of_register_value: register_value -> memory_value -let memory_value_of_register_value r = - (byte_lifteds_of_bit_lifteds r.rv_bits) - -val address_lifted_of_register_value : register_value -> maybe address_lifted -(* returning Nothing iff the register value is not 64 bits wide, but -allowing Bitl_undef and Bitl_unknown *) -let address_lifted_of_register_value (rv:register_value) : maybe address_lifted = - if List.length rv.rv_bits <> 64 then Nothing - else - Just (Address_lifted (byte_lifteds_of_bit_lifteds rv.rv_bits) - (if List.all concretizable_bitl rv.rv_bits - then match (maybe_all (List.map bit_of_bit_lifted rv.rv_bits)) with - | (Just(bits)) -> Just (integer_of_bit_list bits) - | Nothing -> Nothing end - else Nothing)) - -val address_of_address_lifted : address_lifted -> maybe address -(* returning Nothing iff the address contains any Bitl_undef or Bitl_unknown *) -let address_of_address_lifted (al:address_lifted): maybe address = - match al with - | Address_lifted bls (Just i)-> - match maybe_all ((List.map byte_of_byte_lifted) bls) with - | Nothing -> Nothing - | Just bs -> Just (Address bs i) - end - | _ -> Nothing -end - -val address_of_register_value : register_value -> maybe address -(* returning Nothing iff the register value is not 64 bits wide, or contains Bitl_undef or Bitl_unknown *) -let address_of_register_value (rv:register_value) : maybe address = - match address_lifted_of_register_value rv with - | Nothing -> Nothing - | Just al -> - match address_of_address_lifted al with - | Nothing -> Nothing - | Just a -> Just a - end - end - -let address_of_memory_value (endian: end_flag) (mv:memory_value) : maybe address = - match byte_list_of_memory_value endian mv with - | Nothing -> Nothing - | Just bs -> - if List.length bs <> 8 then Nothing else - Just (address_of_byte_list bs) - end - -val byte_of_int : int -> byte -let byte_of_int (i:int) : byte = - Byte (bit_list_of_integer 8 (integerFromInt i)) - -val memory_byte_of_int : int -> memory_byte -let memory_byte_of_int (i:int) : memory_byte = - memory_byte_of_byte (byte_of_int i) - -(* -val int_of_memory_byte : int -> maybe memory_byte -let int_of_memory_byte (mb:memory_byte) : int = - failwith "TODO" -*) - - - -val memory_value_of_address_lifted : end_flag -> address_lifted -> memory_value -let memory_value_of_address_lifted endian (Address_lifted bs _ :address_lifted) = - match_endianness endian bs - -val byte_list_of_address : address -> list byte -let byte_list_of_address (Address bs _) : list byte = bs - -val memory_value_of_address : end_flag -> address -> memory_value -let memory_value_of_address endian (Address bs _) = - match_endianness endian bs - $> List.map byte_lifted_of_byte - -val byte_list_of_opcode : opcode -> list byte -let byte_list_of_opcode (Opcode bs) : list byte = bs - -(** ****************************************** *) -(** show type class instantiations *) -(** ****************************************** *) - -(* matching printing_functions.ml *) -val stringFromReg_name : reg_name -> string -let stringFromReg_name r = - let norm_sl start dir (first,second) = (first,second) - (* match dir with - | D_increasing -> (first,second) - | D_decreasing -> (start - first, start - second) - end *) - in - match r with - | Reg s start size dir -> s - | Reg_slice s start dir sl -> - let (first,second) = norm_sl start dir sl in - s ^ "[" ^ show first ^ (if (first = second) then "" else ".." ^ (show second)) ^ "]" - | Reg_field s start dir f sl -> - let (first,second) = norm_sl start dir sl in - s ^ "." ^ f ^ " (" ^ (show start) ^ ", " ^ (show dir) ^ ", " ^ (show first) ^ ", " ^ (show second) ^ ")" - | Reg_f_slice s start dir f (first1,second1) (first,second) -> - let (first,second) = - match dir with - | D_increasing -> (first,second) - | D_decreasing -> (start - first, start - second) - end in - s ^ "." ^ f ^ "]" ^ show first ^ (if (first = second) then "" else ".." ^ (show second)) ^ "]" - end - -instance (Show reg_name) - let show = stringFromReg_name -end - - -(* hex pp of integers, adapting the Lem string_extra.lem code *) -val stringFromNaturalHexHelper : natural -> list char -> list char -let rec stringFromNaturalHexHelper n acc = - if n = 0 then - acc - else - stringFromNaturalHexHelper (n / 16) (String_extra.chr (natFromNatural (let nd = n mod 16 in if nd <=9 then nd + 48 else nd - 10 + 97)) :: acc) - -val stringFromNaturalHex : natural -> string -let (*~{ocaml;hol}*) stringFromNaturalHex n = - if n = 0 then "0" else toString (stringFromNaturalHexHelper n []) - -val stringFromIntegerHex : integer -> string -let (*~{ocaml}*) stringFromIntegerHex i = - if i < 0 then - "-" ^ stringFromNaturalHex (naturalFromInteger i) - else - stringFromNaturalHex (naturalFromInteger i) - - -let stringFromAddress (Address bs i) = - let i' = integer_of_byte_list bs in - if i=i' then -(*TODO: ideally this should be made to match the src/pp.ml pp_address; the following very roughly matches what's used in the ppcmem UI, enough to make exceptions readable *) - if i < 65535 then - show i - else - stringFromIntegerHex i - else - "stringFromAddress bytes and integer mismatch" - -instance (Show address) - let show = stringFromAddress -end - -let stringFromByte_lifted bl = - match byte_of_byte_lifted bl with - | Nothing -> "u?" - | Just (Byte bits) -> - let i = integer_of_bit_list bits in - show i - end - -instance (Show byte_lifted) - let show = stringFromByte_lifted -end - -(* possible next instruction address options *) -type nia = - | NIA_successor - | NIA_concrete_address of address - | NIA_indirect_address - -let niaCompare n1 n2 = match (n1,n2) with - | (NIA_successor, NIA_successor) -> EQ - | (NIA_successor, _) -> LT - | (_, NIA_successor) -> GT - | (NIA_concrete_address a1, NIA_concrete_address a2) -> compare a1 a2 - | (NIA_concrete_address _, _) -> LT - | (_, NIA_concrete_address _) -> GT - | (NIA_indirect_address, NIA_indirect_address) -> EQ - (* | (NIA_indirect_address, _) -> LT - | (_, NIA_indirect_address) -> GT *) - end - -instance (Ord nia) - let compare = niaCompare - let (<) n1 n2 = (niaCompare n1 n2) = LT - let (<=) n1 n2 = (niaCompare n1 n2) <> GT - let (>) n1 n2 = (niaCompare n1 n2) = GT - let (>=) n1 n2 = (niaCompare n1 n2) <> LT -end - -let stringFromNia = function - | NIA_successor -> "NIA_successor" - | NIA_concrete_address a -> "NIA_concrete_address " ^ show a - | NIA_indirect_address -> "NIA_indirect_address" -end - -instance (Show nia) - let show = stringFromNia -end - -type dia = - | DIA_none - | DIA_concrete_address of address - | DIA_register of reg_name - -let diaCompare d1 d2 = match (d1, d2) with - | (DIA_none, DIA_none) -> EQ - | (DIA_none, _) -> LT - | (DIA_concrete_address a1, DIA_none) -> GT - | (DIA_concrete_address a1, DIA_concrete_address a2) -> compare a1 a2 - | (DIA_concrete_address a1, _) -> LT - | (DIA_register r1, DIA_register r2) -> compare r1 r2 - | (DIA_register _, _) -> GT -end - -instance (Ord dia) - let compare = diaCompare - let (<) n1 n2 = (diaCompare n1 n2) = LT - let (<=) n1 n2 = (diaCompare n1 n2) <> GT - let (>) n1 n2 = (diaCompare n1 n2) = GT - let (>=) n1 n2 = (diaCompare n1 n2) <> LT -end - -let stringFromDia = function - | DIA_none -> "DIA_none" - | DIA_concrete_address a -> "DIA_concrete_address " ^ show a - | DIA_register r -> "DIA_delayed_register " ^ show r -end - -instance (Show dia) - let show = stringFromDia -end -*) diff --git a/snapshots/coq-riscv/sail/lib/coq/Sail2_instr_kinds.v b/snapshots/coq-riscv/sail/lib/coq/Sail2_instr_kinds.v deleted file mode 100644 index eadc567a..00000000 --- a/snapshots/coq-riscv/sail/lib/coq/Sail2_instr_kinds.v +++ /dev/null @@ -1,302 +0,0 @@ -(*========================================================================*) -(* Sail *) -(* *) -(* Copyright (c) 2013-2017 *) -(* Kathyrn Gray *) -(* Shaked Flur *) -(* Stephen Kell *) -(* Gabriel Kerneis *) -(* Robert Norton-Wright *) -(* Christopher Pulte *) -(* Peter Sewell *) -(* Alasdair Armstrong *) -(* Brian Campbell *) -(* Thomas Bauereiss *) -(* Anthony Fox *) -(* Jon French *) -(* Dominic Mulligan *) -(* Stephen Kell *) -(* Mark Wassell *) -(* *) -(* All rights reserved. *) -(* *) -(* This software was developed by the University of Cambridge Computer *) -(* Laboratory as part of the Rigorous Engineering of Mainstream Systems *) -(* (REMS) project, funded by EPSRC grant EP/K008528/1. *) -(* *) -(* Redistribution and use in source and binary forms, with or without *) -(* modification, are permitted provided that the following conditions *) -(* are met: *) -(* 1. Redistributions of source code must retain the above copyright *) -(* notice, this list of conditions and the following disclaimer. *) -(* 2. Redistributions in binary form must reproduce the above copyright *) -(* notice, this list of conditions and the following disclaimer in *) -(* the documentation and/or other materials provided with the *) -(* distribution. *) -(* *) -(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *) -(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *) -(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *) -(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *) -(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *) -(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *) -(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *) -(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *) -(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *) -(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *) -(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *) -(* SUCH DAMAGE. *) -(*========================================================================*) - - -(* - -class ( EnumerationType 'a ) - val toNat : 'a -> nat -end - - -val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> ordering -let ~{ocaml} enumeration_typeCompare e1 e2 := - compare (toNat e1) (toNat e2) -let inline {ocaml} enumeration_typeCompare := defaultCompare - - -default_instance forall 'a. EnumerationType 'a => (Ord 'a) - let compare := enumeration_typeCompare - let (<) r1 r2 := (enumeration_typeCompare r1 r2) = LT - let (<=) r1 r2 := (enumeration_typeCompare r1 r2) <> GT - let (>) r1 r2 := (enumeration_typeCompare r1 r2) = GT - let (>=) r1 r2 := (enumeration_typeCompare r1 r2) <> LT -end -*) - -(* Data structures for building up instructions *) - -(* careful: changes in the read/write/barrier kinds have to be - reflected in deep_shallow_convert *) -Inductive read_kind := - (* common reads *) - | Read_plain - (* Power reads *) - | Read_reserve - (* AArch64 reads *) - | Read_acquire | Read_exclusive | Read_exclusive_acquire | Read_stream - (* RISC-V reads *) - | Read_RISCV_acquire | Read_RISCV_strong_acquire - | Read_RISCV_reserved | Read_RISCV_reserved_acquire - | Read_RISCV_reserved_strong_acquire - (* x86 reads *) - | Read_X86_locked (* the read part of a lock'd instruction (rmw) *) -. -(* -instance (Show read_kind) - let show := function - | Read_plain -> "Read_plain" - | Read_reserve -> "Read_reserve" - | Read_acquire -> "Read_acquire" - | Read_exclusive -> "Read_exclusive" - | Read_exclusive_acquire -> "Read_exclusive_acquire" - | Read_stream -> "Read_stream" - | Read_RISCV_acquire -> "Read_RISCV_acquire" - | Read_RISCV_strong_acquire -> "Read_RISCV_strong_acquire" - | Read_RISCV_reserved -> "Read_RISCV_reserved" - | Read_RISCV_reserved_acquire -> "Read_RISCV_reserved_acquire" - | Read_RISCV_reserved_strong_acquire -> "Read_RISCV_reserved_strong_acquire" - | Read_X86_locked -> "Read_X86_locked" - end -end -*) -Inductive write_kind := - (* common writes *) - | Write_plain - (* Power writes *) - | Write_conditional - (* AArch64 writes *) - | Write_release | Write_exclusive | Write_exclusive_release - (* RISC-V *) - | Write_RISCV_release | Write_RISCV_strong_release - | Write_RISCV_conditional | Write_RISCV_conditional_release - | Write_RISCV_conditional_strong_release - (* x86 writes *) - | Write_X86_locked (* the write part of a lock'd instruction (rmw) *) -. -(* -instance (Show write_kind) - let show := function - | Write_plain -> "Write_plain" - | Write_conditional -> "Write_conditional" - | Write_release -> "Write_release" - | Write_exclusive -> "Write_exclusive" - | Write_exclusive_release -> "Write_exclusive_release" - | Write_RISCV_release -> "Write_RISCV_release" - | Write_RISCV_strong_release -> "Write_RISCV_strong_release" - | Write_RISCV_conditional -> "Write_RISCV_conditional" - | Write_RISCV_conditional_release -> "Write_RISCV_conditional_release" - | Write_RISCV_conditional_strong_release -> "Write_RISCV_conditional_strong_release" - | Write_X86_locked -> "Write_X86_locked" - end -end -*) -Inductive barrier_kind := - (* Power barriers *) - Barrier_Sync | Barrier_LwSync | Barrier_Eieio | Barrier_Isync - (* AArch64 barriers *) - | Barrier_DMB | Barrier_DMB_ST | Barrier_DMB_LD | Barrier_DSB - | Barrier_DSB_ST | Barrier_DSB_LD | Barrier_ISB - (* | Barrier_TM_COMMIT*) - (* MIPS barriers *) - | Barrier_MIPS_SYNC - (* RISC-V barriers *) - | Barrier_RISCV_rw_rw - | Barrier_RISCV_r_rw - | Barrier_RISCV_r_r - | Barrier_RISCV_rw_w - | Barrier_RISCV_w_w - | Barrier_RISCV_w_rw - | Barrier_RISCV_rw_r - | Barrier_RISCV_r_w - | Barrier_RISCV_w_r - | Barrier_RISCV_i - (* X86 *) - | Barrier_x86_MFENCE. - -(* -instance (Show barrier_kind) - let show := function - | Barrier_Sync -> "Barrier_Sync" - | Barrier_LwSync -> "Barrier_LwSync" - | Barrier_Eieio -> "Barrier_Eieio" - | Barrier_Isync -> "Barrier_Isync" - | Barrier_DMB -> "Barrier_DMB" - | Barrier_DMB_ST -> "Barrier_DMB_ST" - | Barrier_DMB_LD -> "Barrier_DMB_LD" - | Barrier_DSB -> "Barrier_DSB" - | Barrier_DSB_ST -> "Barrier_DSB_ST" - | Barrier_DSB_LD -> "Barrier_DSB_LD" - | Barrier_ISB -> "Barrier_ISB" - | Barrier_TM_COMMIT -> "Barrier_TM_COMMIT" - | Barrier_MIPS_SYNC -> "Barrier_MIPS_SYNC" - | Barrier_RISCV_rw_rw -> "Barrier_RISCV_rw_rw" - | Barrier_RISCV_r_rw -> "Barrier_RISCV_r_rw" - | Barrier_RISCV_r_r -> "Barrier_RISCV_r_r" - | Barrier_RISCV_rw_w -> "Barrier_RISCV_rw_w" - | Barrier_RISCV_w_w -> "Barrier_RISCV_w_w" - | Barrier_RISCV_i -> "Barrier_RISCV_i" - | Barrier_x86_MFENCE -> "Barrier_x86_MFENCE" - end -end*) - -Inductive trans_kind := - (* AArch64 *) - | Transaction_start | Transaction_commit | Transaction_abort. -(* -instance (Show trans_kind) - let show := function - | Transaction_start -> "Transaction_start" - | Transaction_commit -> "Transaction_commit" - | Transaction_abort -> "Transaction_abort" - end -end*) - -Inductive instruction_kind := - | IK_barrier : barrier_kind -> instruction_kind - | IK_mem_read : read_kind -> instruction_kind - | IK_mem_write : write_kind -> instruction_kind - | IK_mem_rmw : (read_kind * write_kind) -> instruction_kind - | IK_branch : unit -> instruction_kind (* this includes conditional-branch (multiple nias, none of which is NIA_indirect_address), - indirect/computed-branch (single nia of kind NIA_indirect_address) - and branch/jump (single nia of kind NIA_concrete_address) *) - | IK_trans : trans_kind -> instruction_kind - | IK_simple : unit -> instruction_kind. - -(* -instance (Show instruction_kind) - let show := function - | IK_barrier barrier_kind -> "IK_barrier " ^ (show barrier_kind) - | IK_mem_read read_kind -> "IK_mem_read " ^ (show read_kind) - | IK_mem_write write_kind -> "IK_mem_write " ^ (show write_kind) - | IK_mem_rmw (r, w) -> "IK_mem_rmw " ^ (show r) ^ " " ^ (show w) - | IK_branch -> "IK_branch" - | IK_trans trans_kind -> "IK_trans " ^ (show trans_kind) - | IK_simple -> "IK_simple" - end -end -*) - -Definition read_is_exclusive r := -match r with - | Read_plain => false - | Read_reserve => true - | Read_acquire => false - | Read_exclusive => true - | Read_exclusive_acquire => true - | Read_stream => false - | Read_RISCV_acquire => false - | Read_RISCV_strong_acquire => false - | Read_RISCV_reserved => true - | Read_RISCV_reserved_acquire => true - | Read_RISCV_reserved_strong_acquire => true - | Read_X86_locked => true -end. - - -(* -instance (EnumerationType read_kind) - let toNat := function - | Read_plain -> 0 - | Read_reserve -> 1 - | Read_acquire -> 2 - | Read_exclusive -> 3 - | Read_exclusive_acquire -> 4 - | Read_stream -> 5 - | Read_RISCV_acquire -> 6 - | Read_RISCV_strong_acquire -> 7 - | Read_RISCV_reserved -> 8 - | Read_RISCV_reserved_acquire -> 9 - | Read_RISCV_reserved_strong_acquire -> 10 - | Read_X86_locked -> 11 - end -end - -instance (EnumerationType write_kind) - let toNat := function - | Write_plain -> 0 - | Write_conditional -> 1 - | Write_release -> 2 - | Write_exclusive -> 3 - | Write_exclusive_release -> 4 - | Write_RISCV_release -> 5 - | Write_RISCV_strong_release -> 6 - | Write_RISCV_conditional -> 7 - | Write_RISCV_conditional_release -> 8 - | Write_RISCV_conditional_strong_release -> 9 - | Write_X86_locked -> 10 - end -end - -instance (EnumerationType barrier_kind) - let toNat := function - | Barrier_Sync -> 0 - | Barrier_LwSync -> 1 - | Barrier_Eieio ->2 - | Barrier_Isync -> 3 - | Barrier_DMB -> 4 - | Barrier_DMB_ST -> 5 - | Barrier_DMB_LD -> 6 - | Barrier_DSB -> 7 - | Barrier_DSB_ST -> 8 - | Barrier_DSB_LD -> 9 - | Barrier_ISB -> 10 - | Barrier_TM_COMMIT -> 11 - | Barrier_MIPS_SYNC -> 12 - | Barrier_RISCV_rw_rw -> 13 - | Barrier_RISCV_r_rw -> 14 - | Barrier_RISCV_r_r -> 15 - | Barrier_RISCV_rw_w -> 16 - | Barrier_RISCV_w_w -> 17 - | Barrier_RISCV_i -> 18 - | Barrier_x86_MFENCE -> 19 - end -end -*) diff --git a/snapshots/coq-riscv/sail/lib/coq/Sail2_operators.v b/snapshots/coq-riscv/sail/lib/coq/Sail2_operators.v deleted file mode 100644 index ab02c4a8..00000000 --- a/snapshots/coq-riscv/sail/lib/coq/Sail2_operators.v +++ /dev/null @@ -1,232 +0,0 @@ -Require Import Sail2_values. -Require List. -Import List.ListNotations. - -(*** Bit vector operations *) - -Section Bitvectors. -Context {a b c} `{Bitvector a} `{Bitvector b} `{Bitvector c}. - -(*val concat_bv : forall 'a 'b 'c. Bitvector 'a, Bitvector 'b, Bitvector 'c => 'a -> 'b -> 'c*) -Definition concat_bv (l : a) (r : b) : list bitU := bits_of l ++ bits_of r. - -(*val cons_bv : forall 'a 'b 'c. Bitvector 'a, Bitvector 'b => bitU -> 'a -> 'b*) -Definition cons_bv b' (v : a) : list bitU := b' :: bits_of v. - -Definition cast_unit_bv b : list bitU := [b]. -Definition bv_of_bit len b : list bitU := extz_bits len [b]. - -(*Definition most_significant v := match bits_of v with - | cons b _ => b - | _ => failwith "most_significant applied to empty vector" - end. - -Definition get_max_representable_in sign (n : integer) : integer := - if (n = 64) then match sign with | true -> max_64 | false -> max_64u end - else if (n=32) then match sign with | true -> max_32 | false -> max_32u end - else if (n=8) then max_8 - else if (n=5) then max_5 - else match sign with | true -> integerPow 2 ((natFromInteger n) -1) - | false -> integerPow 2 (natFromInteger n) - end - -Definition get_min_representable_in _ (n : integer) : integer := - if n = 64 then min_64 - else if n = 32 then min_32 - else if n = 8 then min_8 - else if n = 5 then min_5 - else 0 - (integerPow 2 (natFromInteger n)) - -val arith_op_bv_int : forall 'a 'b. Bitvector 'a => - (integer -> integer -> integer) -> bool -> 'a -> integer -> 'a*) -Definition arith_op_bv_int {a} `{Bitvector a} (op : Z -> Z -> Z) (sign : bool) (l : a) (r : Z) : a := - let r' := of_int (length l) r in - arith_op_bv op sign l r'. - -(*val arith_op_int_bv : forall 'a 'b. Bitvector 'a => - (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a*) -Definition arith_op_int_bv {a} `{Bitvector a} (op : Z -> Z -> Z) (sign : bool) (l : Z) (r : a) : a := - let l' := of_int (length r) l in - arith_op_bv op sign l' r. -(* -Definition add_bv_int := arith_op_bv_int Zplus false 1. -Definition sadd_bv_int := arith_op_bv_int Zplus true 1. -Definition sub_bv_int := arith_op_bv_int Zminus false 1. -Definition mult_bv_int := arith_op_bv_int Zmult false 2. -Definition smult_bv_int := arith_op_bv_int Zmult true 2. - -(*val arith_op_int_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b => - (integer -> integer -> integer) -> bool -> integer -> integer -> 'a -> 'b -Definition arith_op_int_bv op sign size l r := - let r' = int_of_bv sign r in - let n = op l r' in - of_int (size * length r) n - -Definition add_int_bv = arith_op_int_bv integerAdd false 1 -Definition sadd_int_bv = arith_op_int_bv integerAdd true 1 -Definition sub_int_bv = arith_op_int_bv integerMinus false 1 -Definition mult_int_bv = arith_op_int_bv integerMult false 2 -Definition smult_int_bv = arith_op_int_bv integerMult true 2 - -Definition arith_op_bv_bit op sign (size : integer) l r := - let l' = int_of_bv sign l in - let n = op l' (match r with | B1 -> (1 : integer) | _ -> 0 end) in - of_int (size * length l) n - -Definition add_bv_bit := arith_op_bv_bit integerAdd false 1 -Definition sadd_bv_bit := arith_op_bv_bit integerAdd true 1 -Definition sub_bv_bit := arith_op_bv_bit integerMinus true 1 - -val arith_op_overflow_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b => - (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> ('b * bitU * bitU) -Definition arith_op_overflow_bv op sign size l r := - let len := length l in - let act_size := len * size in - let (l_sign,r_sign) := (int_of_bv sign l,int_of_bv sign r) in - let (l_unsign,r_unsign) := (int_of_bv false l,int_of_bv false r) in - let n := op l_sign r_sign in - let n_unsign := op l_unsign r_unsign in - let correct_size := of_int act_size n in - let one_more_size_u := bits_of_int (act_size + 1) n_unsign in - let overflow := - if n <= get_max_representable_in sign len && - n >= get_min_representable_in sign len - then B0 else B1 in - let c_out := most_significant one_more_size_u in - (correct_size,overflow,c_out) - -Definition add_overflow_bv := arith_op_overflow_bv integerAdd false 1 -Definition add_overflow_bv_signed := arith_op_overflow_bv integerAdd true 1 -Definition sub_overflow_bv := arith_op_overflow_bv integerMinus false 1 -Definition sub_overflow_bv_signed := arith_op_overflow_bv integerMinus true 1 -Definition mult_overflow_bv := arith_op_overflow_bv integerMult false 2 -Definition mult_overflow_bv_signed := arith_op_overflow_bv integerMult true 2 - -val arith_op_overflow_bv_bit : forall 'a 'b. Bitvector 'a, Bitvector 'b => - (integer -> integer -> integer) -> bool -> integer -> 'a -> bitU -> ('b * bitU * bitU) -Definition arith_op_overflow_bv_bit op sign size l r_bit := - let act_size := length l * size in - let l' := int_of_bv sign l in - let l_u := int_of_bv false l in - let (n,nu,changed) := match r_bit with - | B1 -> (op l' 1, op l_u 1, true) - | B0 -> (l',l_u,false) - | BU -> failwith "arith_op_overflow_bv_bit applied to undefined bit" - end in - let correct_size := of_int act_size n in - let one_larger := bits_of_int (act_size + 1) nu in - let overflow := - if changed - then - if n <= get_max_representable_in sign act_size && n >= get_min_representable_in sign act_size - then B0 else B1 - else B0 in - (correct_size,overflow,most_significant one_larger) - -Definition add_overflow_bv_bit := arith_op_overflow_bv_bit integerAdd false 1 -Definition add_overflow_bv_bit_signed := arith_op_overflow_bv_bit integerAdd true 1 -Definition sub_overflow_bv_bit := arith_op_overflow_bv_bit integerMinus false 1 -Definition sub_overflow_bv_bit_signed := arith_op_overflow_bv_bit integerMinus true 1 - -type shift := LL_shift | RR_shift | RR_shift_arith | LL_rot | RR_rot - -val shift_op_bv : forall 'a. Bitvector 'a => shift -> 'a -> integer -> 'a -Definition shift_op_bv op v n := - match op with - | LL_shift -> - of_bits (get_bits true v n (length v - 1) ++ repeat [B0] n) - | RR_shift -> - of_bits (repeat [B0] n ++ get_bits true v 0 (length v - n - 1)) - | RR_shift_arith -> - of_bits (repeat [most_significant v] n ++ get_bits true v 0 (length v - n - 1)) - | LL_rot -> - of_bits (get_bits true v n (length v - 1) ++ get_bits true v 0 (n - 1)) - | RR_rot -> - of_bits (get_bits false v 0 (n - 1) ++ get_bits false v n (length v - 1)) - end - -Definition shiftl_bv := shift_op_bv LL_shift (*"<<"*) -Definition shiftr_bv := shift_op_bv RR_shift (*">>"*) -Definition arith_shiftr_bv := shift_op_bv RR_shift_arith -Definition rotl_bv := shift_op_bv LL_rot (*"<<<"*) -Definition rotr_bv := shift_op_bv LL_rot (*">>>"*) - -Definition shiftl_mword w n := Machine_word.shiftLeft w (natFromInteger n) -Definition shiftr_mword w n := Machine_word.shiftRight w (natFromInteger n) -Definition rotl_mword w n := Machine_word.rotateLeft (natFromInteger n) w -Definition rotr_mword w n := Machine_word.rotateRight (natFromInteger n) w - -Definition rec arith_op_no0 (op : integer -> integer -> integer) l r := - if r = 0 - then Nothing - else Just (op l r) - -val arith_op_bv_no0 : forall 'a 'b. Bitvector 'a, Bitvector 'b => - (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> 'b -Definition arith_op_bv_no0 op sign size l r := - let act_size := length l * size in - let (l',r') := (int_of_bv sign l,int_of_bv sign r) in - let n := arith_op_no0 op l' r' in - let (representable,n') := - match n with - | Just n' -> - (n' <= get_max_representable_in sign act_size && - n' >= get_min_representable_in sign act_size, n') - | _ -> (false,0) - end in - if representable then (of_int act_size n') else (of_bits (repeat [BU] act_size)) - -Definition mod_bv := arith_op_bv_no0 hardware_mod false 1 -Definition quot_bv := arith_op_bv_no0 hardware_quot false 1 -Definition quot_bv_signed := arith_op_bv_no0 hardware_quot true 1 - -Definition mod_mword := Machine_word.modulo -Definition quot_mword := Machine_word.unsignedDivide -Definition quot_mword_signed := Machine_word.signedDivide - -Definition arith_op_bv_int_no0 op sign size l r := - arith_op_bv_no0 op sign size l (of_int (length l) r) - -Definition quot_bv_int := arith_op_bv_int_no0 hardware_quot false 1 -Definition mod_bv_int := arith_op_bv_int_no0 hardware_mod false 1 -*) -Definition replicate_bits_bv {a b} `{Bitvector a} `{Bitvector b} (v : a) count : b := of_bits (repeat (bits_of v) count). -Import List. -Import ListNotations. -Definition duplicate_bit_bv {a} `{Bitvector a} bit len : a := replicate_bits_bv [bit] len. - -(*val eq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*) -Definition eq_bv {A} `{Bitvector A} (l : A) r := (unsigned l =? unsigned r). - -(*val neq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*) -Definition neq_bv (l : a) (r :a) : bool := (negb (unsigned l =? unsigned r)). -(* -val ucmp_bv : forall 'a. Bitvector 'a => (integer -> integer -> bool) -> 'a -> 'a -> bool -Definition ucmp_bv cmp l r := cmp (unsigned l) (unsigned r) - -val scmp_bv : forall 'a. Bitvector 'a => (integer -> integer -> bool) -> 'a -> 'a -> bool -Definition scmp_bv cmp l r := cmp (signed l) (signed r) - -Definition ult_bv := ucmp_bv (<) -Definition slt_bv := scmp_bv (<) -Definition ugt_bv := ucmp_bv (>) -Definition sgt_bv := scmp_bv (>) -Definition ulteq_bv := ucmp_bv (<=) -Definition slteq_bv := scmp_bv (<=) -Definition ugteq_bv := ucmp_bv (>=) -Definition sgteq_bv := scmp_bv (>=) -*) - -(*val get_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*)*) -Definition get_slice_int_bv {a} `{Bitvector a} len n lo : a := - let hi := lo + len - 1 in - let bs := bools_of_int (hi + 1) n in - of_bools (subrange_list false bs hi lo). - -(*val set_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a -> integer -Definition set_slice_int_bv {a} `{Bitvector a} len n lo (v : a) := - let hi := lo + len - 1 in - let bs := bits_of_int (hi + 1) n in - maybe_failwith (signed_of_bits (update_subrange_list false bs hi lo (bits_of v))).*) - -End Bitvectors. diff --git a/snapshots/coq-riscv/sail/lib/coq/Sail2_operators_bitlists.v b/snapshots/coq-riscv/sail/lib/coq/Sail2_operators_bitlists.v deleted file mode 100644 index dbd8215c..00000000 --- a/snapshots/coq-riscv/sail/lib/coq/Sail2_operators_bitlists.v +++ /dev/null @@ -1,182 +0,0 @@ -Require Import Sail2_values. -Require Import Sail2_operators. - -(* - -(* Specialisation of operators to bit lists *) - -val access_vec_inc : list bitU -> integer -> bitU -let access_vec_inc = access_bv_inc - -val access_vec_dec : list bitU -> integer -> bitU -let access_vec_dec = access_bv_dec - -val update_vec_inc : list bitU -> integer -> bitU -> list bitU -let update_vec_inc = update_bv_inc - -val update_vec_dec : list bitU -> integer -> bitU -> list bitU -let update_vec_dec = update_bv_dec - -val subrange_vec_inc : list bitU -> integer -> integer -> list bitU -let subrange_vec_inc = subrange_bv_inc - -val subrange_vec_dec : list bitU -> integer -> integer -> list bitU -let subrange_vec_dec = subrange_bv_dec - -val update_subrange_vec_inc : list bitU -> integer -> integer -> list bitU -> list bitU -let update_subrange_vec_inc = update_subrange_bv_inc - -val update_subrange_vec_dec : list bitU -> integer -> integer -> list bitU -> list bitU -let update_subrange_vec_dec = update_subrange_bv_dec - -val extz_vec : integer -> list bitU -> list bitU -let extz_vec = extz_bv - -val exts_vec : integer -> list bitU -> list bitU -let exts_vec = exts_bv - -val concat_vec : list bitU -> list bitU -> list bitU -let concat_vec = concat_bv - -val cons_vec : bitU -> list bitU -> list bitU -let cons_vec = cons_bv - -val bool_of_vec : mword ty1 -> bitU -let bool_of_vec = bool_of_bv - -val cast_unit_vec : bitU -> mword ty1 -let cast_unit_vec = cast_unit_bv - -val vec_of_bit : integer -> bitU -> list bitU -let vec_of_bit = bv_of_bit - -val msb : list bitU -> bitU -let msb = most_significant - -val int_of_vec : bool -> list bitU -> integer -let int_of_vec = int_of_bv - -val string_of_vec : list bitU -> string -let string_of_vec = string_of_bv - -val and_vec : list bitU -> list bitU -> list bitU -val or_vec : list bitU -> list bitU -> list bitU -val xor_vec : list bitU -> list bitU -> list bitU -val not_vec : list bitU -> list bitU -let and_vec = and_bv -let or_vec = or_bv -let xor_vec = xor_bv -let not_vec = not_bv - -val add_vec : list bitU -> list bitU -> list bitU -val sadd_vec : list bitU -> list bitU -> list bitU -val sub_vec : list bitU -> list bitU -> list bitU -val mult_vec : list bitU -> list bitU -> list bitU -val smult_vec : list bitU -> list bitU -> list bitU -let add_vec = add_bv -let sadd_vec = sadd_bv -let sub_vec = sub_bv -let mult_vec = mult_bv -let smult_vec = smult_bv - -val add_vec_int : list bitU -> integer -> list bitU -val sadd_vec_int : list bitU -> integer -> list bitU -val sub_vec_int : list bitU -> integer -> list bitU -val mult_vec_int : list bitU -> integer -> list bitU -val smult_vec_int : list bitU -> integer -> list bitU -let add_vec_int = add_bv_int -let sadd_vec_int = sadd_bv_int -let sub_vec_int = sub_bv_int -let mult_vec_int = mult_bv_int -let smult_vec_int = smult_bv_int - -val add_int_vec : integer -> list bitU -> list bitU -val sadd_int_vec : integer -> list bitU -> list bitU -val sub_int_vec : integer -> list bitU -> list bitU -val mult_int_vec : integer -> list bitU -> list bitU -val smult_int_vec : integer -> list bitU -> list bitU -let add_int_vec = add_int_bv -let sadd_int_vec = sadd_int_bv -let sub_int_vec = sub_int_bv -let mult_int_vec = mult_int_bv -let smult_int_vec = smult_int_bv - -val add_vec_bit : list bitU -> bitU -> list bitU -val sadd_vec_bit : list bitU -> bitU -> list bitU -val sub_vec_bit : list bitU -> bitU -> list bitU -let add_vec_bit = add_bv_bit -let sadd_vec_bit = sadd_bv_bit -let sub_vec_bit = sub_bv_bit - -val add_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) -val add_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) -val sub_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) -val sub_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) -val mult_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) -val mult_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) -let add_overflow_vec = add_overflow_bv -let add_overflow_vec_signed = add_overflow_bv_signed -let sub_overflow_vec = sub_overflow_bv -let sub_overflow_vec_signed = sub_overflow_bv_signed -let mult_overflow_vec = mult_overflow_bv -let mult_overflow_vec_signed = mult_overflow_bv_signed - -val add_overflow_vec_bit : list bitU -> bitU -> (list bitU * bitU * bitU) -val add_overflow_vec_bit_signed : list bitU -> bitU -> (list bitU * bitU * bitU) -val sub_overflow_vec_bit : list bitU -> bitU -> (list bitU * bitU * bitU) -val sub_overflow_vec_bit_signed : list bitU -> bitU -> (list bitU * bitU * bitU) -let add_overflow_vec_bit = add_overflow_bv_bit -let add_overflow_vec_bit_signed = add_overflow_bv_bit_signed -let sub_overflow_vec_bit = sub_overflow_bv_bit -let sub_overflow_vec_bit_signed = sub_overflow_bv_bit_signed - -val shiftl : list bitU -> integer -> list bitU -val shiftr : list bitU -> integer -> list bitU -val arith_shiftr : list bitU -> integer -> list bitU -val rotl : list bitU -> integer -> list bitU -val rotr : list bitU -> integer -> list bitU -let shiftl = shiftl_bv -let shiftr = shiftr_bv -let arith_shiftr = arith_shiftr_bv -let rotl = rotl_bv -let rotr = rotr_bv - -val mod_vec : list bitU -> list bitU -> list bitU -val quot_vec : list bitU -> list bitU -> list bitU -val quot_vec_signed : list bitU -> list bitU -> list bitU -let mod_vec = mod_bv -let quot_vec = quot_bv -let quot_vec_signed = quot_bv_signed - -val mod_vec_int : list bitU -> integer -> list bitU -val quot_vec_int : list bitU -> integer -> list bitU -let mod_vec_int = mod_bv_int -let quot_vec_int = quot_bv_int - -val replicate_bits : list bitU -> integer -> list bitU -let replicate_bits = replicate_bits_bv - -val duplicate : bitU -> integer -> list bitU -let duplicate = duplicate_bit_bv - -val eq_vec : list bitU -> list bitU -> bool -val neq_vec : list bitU -> list bitU -> bool -val ult_vec : list bitU -> list bitU -> bool -val slt_vec : list bitU -> list bitU -> bool -val ugt_vec : list bitU -> list bitU -> bool -val sgt_vec : list bitU -> list bitU -> bool -val ulteq_vec : list bitU -> list bitU -> bool -val slteq_vec : list bitU -> list bitU -> bool -val ugteq_vec : list bitU -> list bitU -> bool -val sgteq_vec : list bitU -> list bitU -> bool -let eq_vec = eq_bv -let neq_vec = neq_bv -let ult_vec = ult_bv -let slt_vec = slt_bv -let ugt_vec = ugt_bv -let sgt_vec = sgt_bv -let ulteq_vec = ulteq_bv -let slteq_vec = slteq_bv -let ugteq_vec = ugteq_bv -let sgteq_vec = sgteq_bv -*) diff --git a/snapshots/coq-riscv/sail/lib/coq/Sail2_operators_mwords.v b/snapshots/coq-riscv/sail/lib/coq/Sail2_operators_mwords.v deleted file mode 100644 index 5f9c15f4..00000000 --- a/snapshots/coq-riscv/sail/lib/coq/Sail2_operators_mwords.v +++ /dev/null @@ -1,461 +0,0 @@ -Require Import Sail2_values. -Require Import Sail2_operators. -Require Import Sail2_prompt_monad. -Require Import Sail2_prompt. -Require Import bbv.Word. -Require bbv.BinNotation. -Require Import Arith. -Require Import ZArith. -Require Import Omega. -Require Import Eqdep_dec. - -Module Z_eq_dec. -Definition U := Z. -Definition eq_dec := Z.eq_dec. -End Z_eq_dec. -Module ZEqdep := DecidableEqDep (Z_eq_dec). - -Fixpoint cast_positive (T : positive -> Type) (p q : positive) : T p -> p = q -> T q. -refine ( -match p, q with -| xH, xH => fun x _ => x -| xO p', xO q' => fun x e => cast_positive (fun x => T (xO x)) p' q' x _ -| xI p', xI q' => fun x e => cast_positive (fun x => T (xI x)) p' q' x _ -| _, _ => _ -end); congruence. -Defined. - -Definition cast_T {T : Z -> Type} {m n} : forall (x : T m) (eq : m = n), T n. -refine (match m,n with -| Z0, Z0 => fun x _ => x -| Zneg p1, Zneg p2 => fun x e => cast_positive (fun p => T (Zneg p)) p1 p2 x _ -| Zpos p1, Zpos p2 => fun x e => cast_positive (fun p => T (Zpos p)) p1 p2 x _ -| _,_ => _ -end); congruence. -Defined. - -Lemma cast_positive_refl : forall p T x (e : p = p), - cast_positive T p p x e = x. -induction p. -* intros. simpl. rewrite IHp; auto. -* intros. simpl. rewrite IHp; auto. -* reflexivity. -Qed. - -Lemma cast_T_refl {T : Z -> Type} {m} {H:m = m} (x : T m) : cast_T x H = x. -destruct m. -* reflexivity. -* simpl. rewrite cast_positive_refl. reflexivity. -* simpl. rewrite cast_positive_refl. reflexivity. -Qed. - -Definition autocast {T : Z -> Type} {m n} (x : T m) `{H:ArithFact (m = n)} : T n := - cast_T x (use_ArithFact H). - -Definition autocast_m {rv e m n} (x : monad rv (mword m) e) `{H:ArithFact (m = n)} : monad rv (mword n) e := - x >>= fun x => returnm (cast_T x (use_ArithFact H)). - -Definition cast_word {m n} (x : Word.word m) (eq : m = n) : Word.word n := - DepEqNat.nat_cast _ eq x. - -Lemma cast_word_refl {m} {H:m = m} (x : word m) : cast_word x H = x. -rewrite (UIP_refl_nat _ H). -apply nat_cast_same. -Qed. - -Definition mword_of_nat {m} : Word.word m -> mword (Z.of_nat m). -refine (match m return word m -> mword (Z.of_nat m) with -| O => fun x => x -| S m' => fun x => nat_cast _ _ x -end). -rewrite SuccNat2Pos.id_succ. -reflexivity. -Defined. - -Definition cast_to_mword {m n} (x : Word.word m) : Z.of_nat m = n -> mword n. -refine (match n return Z.of_nat m = n -> mword n with -| Z0 => fun _ => WO -| Zpos p => fun eq => cast_T (mword_of_nat x) eq -| Zneg p => _ -end). -intro eq. -exfalso. destruct m; simpl in *; congruence. -Defined. - -(* -(* Specialisation of operators to machine words *) - -val access_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU*) -Definition access_vec_inc {a} : mword a -> Z -> bitU := access_mword_inc. - -(*val access_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU*) -Definition access_vec_dec {a} : mword a -> Z -> bitU := access_mword_dec. - -(*val update_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU -> mword 'a*) -(* TODO: probably ought to use a monadic version instead, but using bad default for - type compatibility just now *) -Definition update_vec_inc {a} (w : mword a) i b : mword a := - opt_def w (update_mword_inc w i b). - -(*val update_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU -> mword 'a*) -Definition update_vec_dec {a} (w : mword a) i b : mword a := opt_def w (update_mword_dec w i b). - -Lemma subrange_lemma0 {n m o} `{ArithFact (0 <= o)} `{ArithFact (o <= m < n)} : (Z.to_nat o <= Z.to_nat m < Z.to_nat n)%nat. -intros. -unwrap_ArithFacts. -split. -+ apply Z2Nat.inj_le; omega. -+ apply Z2Nat.inj_lt; omega. -Qed. -Lemma subrange_lemma1 {n m o} : (o <= m < n -> n = m + 1 + (n - (m + 1)))%nat. -intros. omega. -Qed. -Lemma subrange_lemma2 {n m o} : (o <= m < n -> m+1 = o+(m-o+1))%nat. -omega. -Qed. -Lemma subrange_lemma3 {n m o} `{ArithFact (0 <= o)} `{ArithFact (o <= m < n)} : - Z.of_nat (Z.to_nat m - Z.to_nat o + 1)%nat = m - o + 1. -unwrap_ArithFacts. -rewrite Nat2Z.inj_add. -rewrite Nat2Z.inj_sub. -repeat rewrite Z2Nat.id; try omega. -reflexivity. -apply Z2Nat.inj_le; omega. -Qed. - -Definition subrange_vec_dec {n} (v : mword n) m o `{ArithFact (0 <= o)} `{ArithFact (o <= m < n)} : mword (m - o + 1) := - let n := Z.to_nat n in - let m := Z.to_nat m in - let o := Z.to_nat o in - let prf : (o <= m < n)%nat := subrange_lemma0 in - let w := get_word v in - cast_to_mword (split2 o (m-o+1) - (cast_word (split1 (m+1) (n-(m+1)) (cast_word w (subrange_lemma1 prf))) - (subrange_lemma2 prf))) subrange_lemma3. - -Definition subrange_vec_inc {n} (v : mword n) m o `{ArithFact (0 <= m)} `{ArithFact (m <= o < n)} : mword (o - m + 1) := autocast (subrange_vec_dec v (n-1-m) (n-1-o)). - -(* TODO: get rid of bogus default *) -Parameter dummy_vector : forall {n} `{ArithFact (n >= 0)}, mword n. - -(*val update_subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*) -Definition update_subrange_vec_inc {a b} (v : mword a) i j (w : mword b) : mword a := - opt_def dummy_vector (of_bits (update_subrange_bv_inc v i j w)). - -(*val update_subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*) -Definition update_subrange_vec_dec {a b} (v : mword a) i j (w : mword b) : mword a := - opt_def dummy_vector (of_bits (update_subrange_bv_dec v i j w)). - -Lemma mword_nonneg {a} : mword a -> a >= 0. -destruct a; -auto using Z.le_ge, Zle_0_pos with zarith. -destruct 1. -Qed. - -(*val extz_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*) -Definition extz_vec {a b} `{ArithFact (b >= a)} (n : Z) (v : mword a) : mword b. -refine (cast_to_mword (Word.zext (get_word v) (Z.to_nat (b - a))) _). -unwrap_ArithFacts. -assert (a >= 0). { apply mword_nonneg. assumption. } -rewrite <- Z2Nat.inj_add; try omega. -rewrite Zplus_minus. -apply Z2Nat.id. -auto with zarith. -Defined. - -(*val exts_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*) -Definition exts_vec {a b} `{ArithFact (b >= a)} (n : Z) (v : mword a) : mword b. -refine (cast_to_mword (Word.sext (get_word v) (Z.to_nat (b - a))) _). -unwrap_ArithFacts. -assert (a >= 0). { apply mword_nonneg. assumption. } -rewrite <- Z2Nat.inj_add; try omega. -rewrite Zplus_minus. -apply Z2Nat.id. -auto with zarith. -Defined. - -Definition zero_extend {a} (v : mword a) (n : Z) `{ArithFact (n >= a)} : mword n := extz_vec n v. - -Definition sign_extend {a} (v : mword a) (n : Z) `{ArithFact (n >= a)} : mword n := exts_vec n v. - -Lemma truncate_eq {m n} : m >= 0 -> m <= n -> (Z.to_nat n = Z.to_nat m + (Z.to_nat n - Z.to_nat m))%nat. -intros. -assert ((Z.to_nat m <= Z.to_nat n)%nat). -{ apply Z2Nat.inj_le; omega. } -omega. -Qed. - -Definition vector_truncate {n} (v : mword n) (m : Z) `{ArithFact (m >= 0)} `{ArithFact (m <= n)} : mword m := - cast_to_mword (Word.split1 _ _ (cast_word (get_word v) (ltac:(unwrap_ArithFacts; apply truncate_eq; auto) : Z.to_nat n = Z.to_nat m + (Z.to_nat n - Z.to_nat m))%nat)) (ltac:(unwrap_ArithFacts; apply Z2Nat.id; omega) : Z.of_nat (Z.to_nat m) = m). - -Lemma concat_eq {a b} : a >= 0 -> b >= 0 -> Z.of_nat (Z.to_nat b + Z.to_nat a)%nat = a + b. -intros. -rewrite Nat2Z.inj_add. -rewrite Z2Nat.id; auto with zarith. -rewrite Z2Nat.id; auto with zarith. -Qed. - - -(*val concat_vec : forall 'a 'b 'c. Size 'a, Size 'b, Size 'c => mword 'a -> mword 'b -> mword 'c*) -Definition concat_vec {a b} (v : mword a) (w : mword b) : mword (a + b) := - cast_to_mword (Word.combine (get_word w) (get_word v)) (ltac:(solve [auto using concat_eq, mword_nonneg with zarith]) : Z.of_nat (Z.to_nat b + Z.to_nat a)%nat = a + b). - -(*val cons_vec : forall 'a 'b 'c. Size 'a, Size 'b => bitU -> mword 'a -> mword 'b*) -(*Definition cons_vec {a b} : bitU -> mword a -> mword b := cons_bv.*) - -(*val bool_of_vec : mword ty1 -> bitU -Definition bool_of_vec := bool_of_bv - -val cast_unit_vec : bitU -> mword ty1 -Definition cast_unit_vec := cast_unit_bv - -val vec_of_bit : forall 'a. Size 'a => integer -> bitU -> mword 'a -Definition vec_of_bit := bv_of_bit*) - -Require Import bbv.NatLib. - -Lemma Npow2_pow {n} : (2 ^ (N.of_nat n) = Npow2 n)%N. -induction n. -* reflexivity. -* rewrite Nnat.Nat2N.inj_succ. - rewrite N.pow_succ_r'. - rewrite IHn. - rewrite Npow2_S. - rewrite Word.Nmul_two. - reflexivity. -Qed. - -Program Definition uint {a} (x : mword a) : {z : Z & ArithFact (0 <= z /\ z <= 2 ^ a - 1)} := - existT _ (Z.of_N (Word.wordToN (get_word x))) _. -Next Obligation. -constructor. -constructor. -* apply N2Z.is_nonneg. -* assert (2 ^ a - 1 = Z.of_N (2 ^ (Z.to_N a) - 1)). { - rewrite N2Z.inj_sub. - * rewrite N2Z.inj_pow. - rewrite Z2N.id; auto. - destruct a; auto with zarith. destruct x. - * apply N.le_trans with (m := (2^0)%N); auto using N.le_refl. - apply N.pow_le_mono_r. - inversion 1. - apply N.le_0_l. - } - rewrite H. - apply N2Z.inj_le. - rewrite N.sub_1_r. - apply N.lt_le_pred. - rewrite <- Z_nat_N. - rewrite Npow2_pow. - apply Word.wordToN_bound. -Defined. - -Lemma Zpow_pow2 {n} : 2 ^ Z.of_nat n = Z.of_nat (pow2 n). -induction n. -* reflexivity. -* rewrite pow2_S_z. - rewrite Nat2Z.inj_succ. - rewrite Z.pow_succ_r; auto with zarith. -Qed. - -Program Definition sint {a} `{ArithFact (a > 0)} (x : mword a) : {z : Z & ArithFact (-(2^(a-1)) <= z /\ z <= 2 ^ (a-1) - 1)} := - existT _ (Word.wordToZ (get_word x)) _. -Next Obligation. -destruct H. -destruct a; try inversion fact. -constructor. -generalize (get_word x). -rewrite <- positive_nat_Z. -destruct (Pos2Nat.is_succ p) as [n eq]. -rewrite eq. -rewrite Nat2Z.id. -intro w. -destruct (Word.wordToZ_size' w) as [LO HI]. -replace 1 with (Z.of_nat 1); auto. -rewrite <- Nat2Z.inj_sub; auto with arith. -simpl. -rewrite <- minus_n_O. -rewrite Zpow_pow2. -rewrite Z.sub_1_r. -rewrite <- Z.lt_le_pred. -auto. -Defined. - -Lemma length_list_pos : forall {A} {l:list A}, length_list l >= 0. -unfold length_list. -auto with zarith. -Qed. -Hint Resolve length_list_pos : sail. - -Definition vec_of_bits (l:list bitU) : mword (length_list l) := opt_def dummy_vector (of_bits l). -(* - -val msb : forall 'a. Size 'a => mword 'a -> bitU -Definition msb := most_significant - -val int_of_vec : forall 'a. Size 'a => bool -> mword 'a -> integer -Definition int_of_vec := int_of_bv - -val string_of_vec : forall 'a. Size 'a => mword 'a -> string*) -Definition string_of_bits {n} (w : mword n) : string := string_of_bv w. -Definition with_word' {n} (P : Type -> Type) : (forall n, Word.word n -> P (Word.word n)) -> mword n -> P (mword n) := fun f w => @with_word n _ (f (Z.to_nat n)) w. -Definition word_binop {n} (f : forall n, Word.word n -> Word.word n -> Word.word n) : mword n -> mword n -> mword n := with_word' (fun x => x -> x) f. -Definition word_unop {n} (f : forall n, Word.word n -> Word.word n) : mword n -> mword n := with_word' (fun x => x) f. - - -(* -val and_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a -val or_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a -val xor_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a -val not_vec : forall 'a. Size 'a => mword 'a -> mword 'a*) -Definition and_vec {n} : mword n -> mword n -> mword n := word_binop Word.wand. -Definition or_vec {n} : mword n -> mword n -> mword n := word_binop Word.wor. -Definition xor_vec {n} : mword n -> mword n -> mword n := word_binop Word.wxor. -Definition not_vec {n} : mword n -> mword n := word_unop Word.wnot. - -(*val add_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a -val sadd_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a -val sub_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a -val mult_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b -val smult_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b*) -Definition add_vec {n} : mword n -> mword n -> mword n := word_binop Word.wplus. -(*Definition sadd_vec {n} : mword n -> mword n -> mword n := sadd_bv w.*) -Definition sub_vec {n} : mword n -> mword n -> mword n := word_binop Word.wminus. -Definition mult_vec {n m} `{ArithFact (m >= n)} (l : mword n) (r : mword n) : mword m := - word_binop Word.wmult (zero_extend l _) (zero_extend r _). -Definition mults_vec {n m} `{ArithFact (m >= n)} (l : mword n) (r : mword n) : mword m := - word_binop Word.wmult (sign_extend l _) (sign_extend r _). - -(*val add_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a -val sadd_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a -val sub_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a -val mult_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b -val smult_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) -Definition add_vec_int {a} (l : mword a) (r : Z) : mword a := arith_op_bv_int Z.add false l r. -Definition sadd_vec_int {a} (l : mword a) (r : Z) : mword a := arith_op_bv_int Z.add true l r. -Definition sub_vec_int {a} (l : mword a) (r : Z) : mword a := arith_op_bv_int Z.sub false l r. -(*Definition mult_vec_int {a b} : mword a -> Z -> mword b := mult_bv_int. -Definition smult_vec_int {a b} : mword a -> Z -> mword b := smult_bv_int.*) - -(*val add_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a -val sadd_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a -val sub_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a -val mult_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b -val smult_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b -Definition add_int_vec := add_int_bv -Definition sadd_int_vec := sadd_int_bv -Definition sub_int_vec := sub_int_bv -Definition mult_int_vec := mult_int_bv -Definition smult_int_vec := smult_int_bv - -val add_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> mword 'a -val sadd_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> mword 'a -val sub_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> mword 'a -Definition add_vec_bit := add_bv_bit -Definition sadd_vec_bit := sadd_bv_bit -Definition sub_vec_bit := sub_bv_bit - -val add_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU) -val add_overflow_vec_signed : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU) -val sub_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU) -val sub_overflow_vec_signed : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU) -val mult_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU) -val mult_overflow_vec_signed : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU) -Definition add_overflow_vec := add_overflow_bv -Definition add_overflow_vec_signed := add_overflow_bv_signed -Definition sub_overflow_vec := sub_overflow_bv -Definition sub_overflow_vec_signed := sub_overflow_bv_signed -Definition mult_overflow_vec := mult_overflow_bv -Definition mult_overflow_vec_signed := mult_overflow_bv_signed - -val add_overflow_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU) -val add_overflow_vec_bit_signed : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU) -val sub_overflow_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU) -val sub_overflow_vec_bit_signed : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU) -Definition add_overflow_vec_bit := add_overflow_bv_bit -Definition add_overflow_vec_bit_signed := add_overflow_bv_bit_signed -Definition sub_overflow_vec_bit := sub_overflow_bv_bit -Definition sub_overflow_vec_bit_signed := sub_overflow_bv_bit_signed - -val shiftl : forall 'a. Size 'a => mword 'a -> integer -> mword 'a -val shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a -val arith_shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a -val rotl : forall 'a. Size 'a => mword 'a -> integer -> mword 'a -val rotr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) -(* TODO: check/redefine behaviour on out-of-range n *) -Definition shiftl {a} (v : mword a) n : mword a := with_word (P := id) (fun w => Word.wlshift w (Z.to_nat n)) v. -Definition shiftr {a} (v : mword a) n : mword a := with_word (P := id) (fun w => Word.wrshift w (Z.to_nat n)) v. -Definition arith_shiftr {a} (v : mword a) n : mword a := with_word (P := id) (fun w => Word.wrshifta w (Z.to_nat n)) v. -(* -Definition rotl := rotl_bv -Definition rotr := rotr_bv - -val mod_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a -val quot_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a -val quot_vec_signed : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a -Definition mod_vec := mod_bv -Definition quot_vec := quot_bv -Definition quot_vec_signed := quot_bv_signed - -val mod_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a -val quot_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a -Definition mod_vec_int := mod_bv_int -Definition quot_vec_int := quot_bv_int - -val replicate_bits : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) -Fixpoint replicate_bits_aux {a} (w : Word.word a) (n : nat) : Word.word (n * a) := -match n with -| O => Word.WO -| S m => Word.combine w (replicate_bits_aux w m) -end. -Lemma replicate_ok {n a} `{ArithFact (n >= 0)} `{ArithFact (a >= 0)} : - Z.of_nat (Z.to_nat n * Z.to_nat a) = a * n. -destruct H. destruct H0. -rewrite <- Z2Nat.id; auto with zarith. -rewrite Z2Nat.inj_mul; auto with zarith. -rewrite Nat.mul_comm. reflexivity. -Qed. -Definition replicate_bits {a} (w : mword a) (n : Z) `{ArithFact (n >= 0)} : mword (a * n) := - cast_to_mword (replicate_bits_aux (get_word w) (Z.to_nat n)) replicate_ok. - -(*val duplicate : forall 'a. Size 'a => bitU -> integer -> mword 'a -Definition duplicate := duplicate_bit_bv - -val eq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool -val neq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool -val ult_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool -val slt_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool -val ugt_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool -val sgt_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool -val ulteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool -val slteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool -val ugteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool -val sgteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool*) -Definition eq_vec {n} (x : mword n) (y : mword n) : bool := Word.weqb (get_word x) (get_word y). -Definition neq_vec {n} (x : mword n) (y : mword n) : bool := negb (eq_vec x y). -(*Definition ult_vec := ult_bv. -Definition slt_vec := slt_bv. -Definition ugt_vec := ugt_bv. -Definition sgt_vec := sgt_bv. -Definition ulteq_vec := ulteq_bv. -Definition slteq_vec := slteq_bv. -Definition ugteq_vec := ugteq_bv. -Definition sgteq_vec := sgteq_bv. - -*) - -Program Fixpoint reverse_endianness_word {n} (bits : word n) : word n := - match n with - | S (S (S (S (S (S (S (S m))))))) => - combine - (reverse_endianness_word (split2 8 m bits)) - (split1 8 m bits) - | _ => bits - end. -Next Obligation. -omega. -Qed. - -Definition reverse_endianness {n} (bits : mword n) := with_word (P := id) reverse_endianness_word bits. - -Definition get_slice_int {a} `{ArithFact (a >= 0)} : Z -> Z -> Z -> mword a := get_slice_int_bv. diff --git a/snapshots/coq-riscv/sail/lib/coq/Sail2_prompt.v b/snapshots/coq-riscv/sail/lib/coq/Sail2_prompt.v deleted file mode 100644 index a0ef467e..00000000 --- a/snapshots/coq-riscv/sail/lib/coq/Sail2_prompt.v +++ /dev/null @@ -1,129 +0,0 @@ -(*Require Import Sail_impl_base*) -Require Import Sail2_values. -Require Import Sail2_prompt_monad. - -Require Import List. -Import ListNotations. -(* - -val iter_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e -let rec iter_aux i f xs = match xs with - | x :: xs -> f i x >> iter_aux (i + 1) f xs - | [] -> return () - end - -declare {isabelle} termination_argument iter_aux = automatic - -val iteri : forall 'rv 'a 'e. (integer -> 'a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e -let iteri f xs = iter_aux 0 f xs - -val iter : forall 'rv 'a 'e. ('a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e -let iter f xs = iteri (fun _ x -> f x) xs - -val foreachM : forall 'a 'rv 'vars 'e. - list 'a -> 'vars -> ('a -> 'vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e*) -Fixpoint foreachM {a rv Vars e} (l : list a) (vars : Vars) (body : a -> Vars -> monad rv Vars e) : monad rv Vars e := -match l with -| [] => returnm vars -| (x :: xs) => - body x vars >>= fun vars => - foreachM xs vars body -end. - -Fixpoint foreach_ZM_up' {rv e Vars} from to step off n `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e := - if sumbool_of_bool (from + off <=? to) then - match n with - | O => returnm vars - | S n => body (from + off) _ vars >>= fun vars => foreach_ZM_up' from to step (off + step) n vars body - end - else returnm vars. - -Fixpoint foreach_ZM_down' {rv e Vars} from to step off n `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e := - if sumbool_of_bool (to <=? from + off) then - match n with - | O => returnm vars - | S n => body (from + off) _ vars >>= fun vars => foreach_ZM_down' from to step (off - step) n vars body - end - else returnm vars. - -Definition foreach_ZM_up {rv e Vars} from to step vars body `{ArithFact (0 < step)} := - foreach_ZM_up' (rv := rv) (e := e) (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body. -Definition foreach_ZM_down {rv e Vars} from to step vars body `{ArithFact (0 < step)} := - foreach_ZM_down' (rv := rv) (e := e) (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body. - -(*declare {isabelle} termination_argument foreachM = automatic*) - -(*val and_boolM : forall 'rv 'e. monad 'rv bool 'e -> monad 'rv bool 'e -> monad 'rv bool 'e*) -Definition and_boolM {rv E} (l : monad rv bool E) (r : monad rv bool E) : monad rv bool E := - l >>= (fun l => if l then r else returnm false). - -(*val or_boolM : forall 'rv 'e. monad 'rv bool 'e -> monad 'rv bool 'e -> monad 'rv bool 'e*) -Definition or_boolM {rv E} (l : monad rv bool E) (r : monad rv bool E) : monad rv bool E := - l >>= (fun l => if l then returnm true else r). - -(*val bool_of_bitU_fail : forall 'rv 'e. bitU -> monad 'rv bool 'e*) -Definition bool_of_bitU_fail {rv E} (b : bitU) : monad rv bool E := -match b with - | B0 => returnm false - | B1 => returnm true - | BU => Fail "bool_of_bitU" -end. - -(*val bool_of_bitU_oracle : forall 'rv 'e. bitU -> monad 'rv bool 'e*) -Definition bool_of_bitU_oracle {rv E} (b : bitU) : monad rv bool E := -match b with - | B0 => returnm false - | B1 => returnm true - | BU => undefined_bool tt -end. - - -(*val whileM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) -> - ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e -let rec whileM vars cond body = - cond vars >>= fun cond_val -> - if cond_val then - body vars >>= fun vars -> whileM vars cond body - else return vars - -val untilM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) -> - ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e -let rec untilM vars cond body = - body vars >>= fun vars -> - cond vars >>= fun cond_val -> - if cond_val then return vars else untilM vars cond body - -(*let write_two_regs r1 r2 vec = - let is_inc = - let is_inc_r1 = is_inc_of_reg r1 in - let is_inc_r2 = is_inc_of_reg r2 in - let () = ensure (is_inc_r1 = is_inc_r2) - "write_two_regs called with vectors of different direction" in - is_inc_r1 in - - let (size_r1 : integer) = size_of_reg r1 in - let (start_vec : integer) = get_start vec in - let size_vec = length vec in - let r1_v = - if is_inc - then slice vec start_vec (size_r1 - start_vec - 1) - else slice vec start_vec (start_vec - size_r1 - 1) in - let r2_v = - if is_inc - then slice vec (size_r1 - start_vec) (size_vec - start_vec) - else slice vec (start_vec - size_r1) (start_vec - size_vec) in - write_reg r1 r1_v >> write_reg r2 r2_v*) - -*) - -(* If we need to build an existential after a monadic operation, assume that - we can do it entirely from the type. *) - -Definition build_ex_m {rv e} {T:Type} (x:monad rv T e) {P:T -> Prop} `{H:forall x, ArithFact (P x)} : monad rv {x : T & ArithFact (P x)} e := - x >>= fun y => returnm (existT _ y (H y)). - -Definition projT1_m {rv e} {P:Z -> Prop} (x: monad rv {x : Z & P x} e) : monad rv Z e := - x >>= fun y => returnm (projT1 y). - -Definition derive_m {rv e} {P Q:Z -> Prop} (x : monad rv {x : Z & P x} e) `{forall x, ArithFact (P x) -> ArithFact (Q x)} : monad rv {x : Z & (ArithFact (Q x))} e := - x >>= fun y => returnm (build_ex (projT1 y)). diff --git a/snapshots/coq-riscv/sail/lib/coq/Sail2_prompt_monad.v b/snapshots/coq-riscv/sail/lib/coq/Sail2_prompt_monad.v deleted file mode 100644 index 2715b5e7..00000000 --- a/snapshots/coq-riscv/sail/lib/coq/Sail2_prompt_monad.v +++ /dev/null @@ -1,247 +0,0 @@ -Require Import String. -(*Require Import Sail_impl_base*) -Require Import Sail2_instr_kinds. -Require Import Sail2_values. - - - -Definition register_name := string. -Definition address := list bitU. - -Inductive monad regval a e := - | Done : a -> monad regval a e - (* Read a number : bytes from memory, returned in little endian order *) - | Read_mem : read_kind -> address -> nat -> (list memory_byte -> monad regval a e) -> monad regval a e - (* Read the tag : a memory address *) - | Read_tag : address -> (bitU -> monad regval a e) -> monad regval a e - (* Tell the system a write is imminent, at address lifted, : size nat *) - | Write_ea : write_kind -> address -> nat -> monad regval a e -> monad regval a e - (* Request the result : store-exclusive *) - | Excl_res : (bool -> monad regval a e) -> monad regval a e - (* Request to write memory at last signalled address. Memory value should be 8 - times the size given in ea signal, given in little endian order *) - | Write_memv : list memory_byte -> (bool -> monad regval a e) -> monad regval a e - (* Request to write the tag at last signalled address. *) - | Write_tag : address -> bitU -> (bool -> monad regval a e) -> monad regval a e - (* Tell the system to dynamically recalculate dependency footprint *) - | Footprint : monad regval a e -> monad regval a e - (* Request a memory barrier *) - | Barrier : barrier_kind -> monad regval a e -> monad regval a e - (* Request to read register, will track dependency when mode.track_values *) - | Read_reg : register_name -> (regval -> monad regval a e) -> monad regval a e - (* Request to write register *) - | Write_reg : register_name -> regval -> monad regval a e -> monad regval a e - | Undefined : (bool -> monad regval a e) -> monad regval a e - (*Result : a failed assert with possible error message to report*) - | Fail : string -> monad regval a e - | Error : string -> monad regval a e - (* Exception : type e *) - | Exception : e -> monad regval a e. - (* TODO: Reading/writing tags *) - -Arguments Done [_ _ _]. -Arguments Read_mem [_ _ _]. -Arguments Read_tag [_ _ _]. -Arguments Write_ea [_ _ _]. -Arguments Excl_res [_ _ _]. -Arguments Write_memv [_ _ _]. -Arguments Write_tag [_ _ _]. -Arguments Footprint [_ _ _]. -Arguments Barrier [_ _ _]. -Arguments Read_reg [_ _ _]. -Arguments Write_reg [_ _ _]. -Arguments Undefined [_ _ _]. -Arguments Fail [_ _ _]. -Arguments Error [_ _ _]. -Arguments Exception [_ _ _]. - -(*val return : forall rv a e. a -> monad rv a e*) -Definition returnm {rv A E} (a : A) : monad rv A E := Done a. - -(*val bind : forall rv a b e. monad rv a e -> (a -> monad rv b e) -> monad rv b e*) -Fixpoint bind {rv A B E} (m : monad rv A E) (f : A -> monad rv B E) := match m with - | Done a => f a - | Read_mem rk a sz k => Read_mem rk a sz (fun v => bind (k v) f) - | Read_tag a k => Read_tag a (fun v => bind (k v) f) - | Write_memv descr k => Write_memv descr (fun v => bind (k v) f) - | Write_tag a t k => Write_tag a t (fun v => bind (k v) f) - | Read_reg descr k => Read_reg descr (fun v => bind (k v) f) - | Excl_res k => Excl_res (fun v => bind (k v) f) - | Undefined k => Undefined (fun v => bind (k v) f) - | Write_ea wk a sz k => Write_ea wk a sz (bind k f) - | Footprint k => Footprint (bind k f) - | Barrier bk k => Barrier bk (bind k f) - | Write_reg r v k => Write_reg r v (bind k f) - | Fail descr => Fail descr - | Error descr => Error descr - | Exception e => Exception e -end. - -Notation "m >>= f" := (bind m f) (at level 50, left associativity). -(*val (>>) : forall rv b e. monad rv unit e -> monad rv b e -> monad rv b e*) -Definition bind0 {rv A E} (m : monad rv unit E) (n : monad rv A E) := - m >>= fun (_ : unit) => n. -Notation "m >> n" := (bind0 m n) (at level 50, left associativity). - -(*val exit : forall rv a e. unit -> monad rv a e*) -Definition exit {rv A E} (_ : unit) : monad rv A E := Fail "exit". - -(*val undefined_bool : forall 'rv 'e. unit -> monad 'rv bool 'e*) -Definition undefined_bool {rv e} (_:unit) : monad rv bool e := Undefined returnm. - -(*val assert_exp : forall rv e. bool -> string -> monad rv unit e*) -Definition assert_exp {rv E} (exp :bool) msg : monad rv unit E := - if exp then Done tt else Fail msg. - -Definition assert_exp' {rv E} (exp :bool) msg : monad rv (exp = true) E := - if exp return monad rv (exp = true) E then Done eq_refl else Fail msg. -Definition bindH {rv A P E} (m : monad rv P E) (n : monad rv A E) := - m >>= fun (H : P) => n. -Notation "m >>> n" := (bindH m n) (at level 50, left associativity). - -(*val throw : forall rv a e. e -> monad rv a e*) -Definition throw {rv A E} e : monad rv A E := Exception e. - -(*val try_catch : forall rv a e1 e2. monad rv a e1 -> (e1 -> monad rv a e2) -> monad rv a e2*) -Fixpoint try_catch {rv A E1 E2} (m : monad rv A E1) (h : E1 -> monad rv A E2) := match m with - | Done a => Done a - | Read_mem rk a sz k => Read_mem rk a sz (fun v => try_catch (k v) h) - | Read_tag a k => Read_tag a (fun v => try_catch (k v) h) - | Write_memv descr k => Write_memv descr (fun v => try_catch (k v) h) - | Write_tag a t k => Write_tag a t (fun v => try_catch (k v) h) - | Read_reg descr k => Read_reg descr (fun v => try_catch (k v) h) - | Excl_res k => Excl_res (fun v => try_catch (k v) h) - | Undefined k => Undefined (fun v => try_catch (k v) h) - | Write_ea wk a sz k => Write_ea wk a sz (try_catch k h) - | Footprint k => Footprint (try_catch k h) - | Barrier bk k => Barrier bk (try_catch k h) - | Write_reg r v k => Write_reg r v (try_catch k h) - | Fail descr => Fail descr - | Error descr => Error descr - | Exception e => h e -end. - -(* For early return, we abuse exceptions by throwing and catching - the return value. The exception type is "either r e", where "inr e" - represents a proper exception and "inl r" an early return : value "r". *) -Definition monadR rv a r e := monad rv a (sum r e). - -(*val early_return : forall rv a r e. r -> monadR rv a r e*) -Definition early_return {rv A R E} (r : R) : monadR rv A R E := throw (inl r). - -(*val catch_early_return : forall rv a e. monadR rv a a e -> monad rv a e*) -Definition catch_early_return {rv A E} (m : monadR rv A A E) := - try_catch m - (fun r => match r with - | inl a => returnm a - | inr e => throw e - end). - -(* Lift to monad with early return by wrapping exceptions *) -(*val liftR : forall rv a r e. monad rv a e -> monadR rv a r e*) -Definition liftR {rv A R E} (m : monad rv A E) : monadR rv A R E := - try_catch m (fun e => throw (inr e)). - -(* Catch exceptions in the presence : early returns *) -(*val try_catchR : forall rv a r e1 e2. monadR rv a r e1 -> (e1 -> monadR rv a r e2) -> monadR rv a r e2*) -Definition try_catchR {rv A R E1 E2} (m : monadR rv A R E1) (h : E1 -> monadR rv A R E2) := - try_catch m - (fun r => match r with - | inl r => throw (inl r) - | inr e => h e - end). - -(*val maybe_fail : forall 'rv 'a 'e. string -> maybe 'a -> monad 'rv 'a 'e*) -Definition maybe_fail {rv A E} msg (x : option A) : monad rv A E := -match x with - | Some a => returnm a - | None => Fail msg -end. - -(*val read_mem_bytes : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv (list memory_byte) 'e*) -Definition read_mem_bytes {rv A E} rk (addr : mword A) sz : monad rv (list memory_byte) E := - Read_mem rk (bits_of addr) (Z.to_nat sz) returnm. - -(*val read_mem : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv 'b 'e*) -Definition read_mem {rv A B E} `{ArithFact (B >= 0)} rk (addr : mword A) sz : monad rv (mword B) E := - bind - (read_mem_bytes rk addr sz) - (fun bytes => - maybe_fail "bits_of_mem_bytes" (of_bits (bits_of_mem_bytes bytes))). - -(*val read_tag : forall rv a e. Bitvector a => a -> monad rv bitU e*) -Definition read_tag {rv a e} `{Bitvector a} (addr : a) : monad rv bitU e := - Read_tag (bits_of addr) returnm. - -(*val excl_result : forall rv e. unit -> monad rv bool e*) -Definition excl_result {rv e} (_:unit) : monad rv bool e := - let k successful := (returnm successful) in - Excl_res k. - -Definition write_mem_ea {rv a E} `{Bitvector a} wk (addr: a) sz : monad rv unit E := - Write_ea wk (bits_of addr) (Z.to_nat sz) (Done tt). - -Definition write_mem_val {rv a e} `{Bitvector a} (v : a) : monad rv bool e := match mem_bytes_of_bits v with - | Some v => Write_memv v returnm - | None => Fail "write_mem_val" -end. - -(*val write_tag : forall rv a e. Bitvector 'a => 'a -> bitU -> monad rv bool e*) -Definition write_tag {rv a e} (addr : mword a) (b : bitU) : monad rv bool e := Write_tag (bits_of addr) b returnm. - -Definition read_reg {s rv a e} (reg : register_ref s rv a) : monad rv a e := - let k v := - match reg.(of_regval) v with - | Some v => Done v - | None => Error "read_reg: unrecognised value" - end - in - Read_reg reg.(name) k. - -(* TODO -val read_reg_range : forall s r rv a e. Bitvector a => register_ref s rv r -> integer -> integer -> monad rv a e -Definition read_reg_range reg i j := - read_reg_aux of_bits (external_reg_slice reg (natFromInteger i,natFromInteger j)) - -Definition read_reg_bit reg i := - read_reg_aux (fun v -> v) (external_reg_slice reg (natFromInteger i,natFromInteger i)) >>= fun v -> - returnm (extract_only_element v) - -Definition read_reg_field reg regfield := - read_reg_aux (external_reg_field_whole reg regfield) - -Definition read_reg_bitfield reg regfield := - read_reg_aux (external_reg_field_whole reg regfield) >>= fun v -> - returnm (extract_only_element v)*) - -Definition reg_deref {s rv a e} := @read_reg s rv a e. - -(*Parameter write_reg : forall {s rv a e}, register_ref s rv a -> a -> monad rv unit e.*) -Definition write_reg {s rv a e} (reg : register_ref s rv a) (v : a) : monad rv unit e := - Write_reg reg.(name) (reg.(regval_of) v) (Done tt). - -(* TODO -Definition write_reg reg v := - write_reg_aux (external_reg_whole reg) v -Definition write_reg_range reg i j v := - write_reg_aux (external_reg_slice reg (natFromInteger i,natFromInteger j)) v -Definition write_reg_pos reg i v := - let iN := natFromInteger i in - write_reg_aux (external_reg_slice reg (iN,iN)) [v] -Definition write_reg_bit := write_reg_pos -Definition write_reg_field reg regfield v := - write_reg_aux (external_reg_field_whole reg regfield.field_name) v -Definition write_reg_field_bit reg regfield bit := - write_reg_aux (external_reg_field_whole reg regfield.field_name) - (Vector [bit] 0 (is_inc_of_reg reg)) -Definition write_reg_field_range reg regfield i j v := - write_reg_aux (external_reg_field_slice reg regfield.field_name (natFromInteger i,natFromInteger j)) v -Definition write_reg_field_pos reg regfield i v := - write_reg_field_range reg regfield i i [v] -Definition write_reg_field_bit := write_reg_field_pos*) - -(*val barrier : forall rv e. barrier_kind -> monad rv unit e*) -Definition barrier {rv e} bk : monad rv unit e := Barrier bk (Done tt). - -(*val footprint : forall rv e. unit -> monad rv unit e*) -Definition footprint {rv e} (_ : unit) : monad rv unit e := Footprint (Done tt). diff --git a/snapshots/coq-riscv/sail/lib/coq/Sail2_state.v b/snapshots/coq-riscv/sail/lib/coq/Sail2_state.v deleted file mode 100644 index 1d5cb342..00000000 --- a/snapshots/coq-riscv/sail/lib/coq/Sail2_state.v +++ /dev/null @@ -1,69 +0,0 @@ -(*Require Import Sail_impl_base*) -Require Import Sail2_values. -Require Import Sail2_prompt_monad. -Require Import Sail2_prompt. -Require Import Sail2_state_monad. -(* -(* State monad wrapper around prompt monad *) - -val liftState : forall 'regval 'regs 'a 'e. register_accessors 'regs 'regval -> monad 'regval 'a 'e -> monadS 'regs 'a 'e -let rec liftState ra s = match s with - | (Done a) -> returnS a - | (Read_mem rk a sz k) -> bindS (read_mem_bytesS rk a sz) (fun v -> liftState ra (k v)) - | (Read_tag t k) -> bindS (read_tagS t) (fun v -> liftState ra (k v)) - | (Write_memv a k) -> bindS (write_mem_bytesS a) (fun v -> liftState ra (k v)) - | (Write_tagv t k) -> bindS (write_tagS t) (fun v -> liftState ra (k v)) - | (Read_reg r k) -> bindS (read_regvalS ra r) (fun v -> liftState ra (k v)) - | (Excl_res k) -> bindS (excl_resultS ()) (fun v -> liftState ra (k v)) - | (Undefined k) -> bindS (undefined_boolS ()) (fun v -> liftState ra (k v)) - | (Write_ea wk a sz k) -> seqS (write_mem_eaS wk a sz) (liftState ra k) - | (Write_reg r v k) -> seqS (write_regvalS ra r v) (liftState ra k) - | (Footprint k) -> liftState ra k - | (Barrier _ k) -> liftState ra k - | (Fail descr) -> failS descr - | (Error descr) -> failS descr - | (Exception e) -> throwS e -end - - -val iterS_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e -let rec iterS_aux i f xs = match xs with - | x :: xs -> f i x >>$ iterS_aux (i + 1) f xs - | [] -> returnS () - end - -declare {isabelle} termination_argument iterS_aux = automatic - -val iteriS : forall 'rv 'a 'e. (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e -let iteriS f xs = iterS_aux 0 f xs - -val iterS : forall 'rv 'a 'e. ('a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e -let iterS f xs = iteriS (fun _ x -> f x) xs - -val foreachS : forall 'a 'rv 'vars 'e. - list 'a -> 'vars -> ('a -> 'vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e -let rec foreachS xs vars body = match xs with - | [] -> returnS vars - | x :: xs -> - body x vars >>$= fun vars -> - foreachS xs vars body -end - -declare {isabelle} termination_argument foreachS = automatic - - -val whileS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) -> - ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e -let rec whileS vars cond body s = - (cond vars >>$= (fun cond_val s' -> - if cond_val then - (body vars >>$= (fun vars s'' -> whileS vars cond body s'')) s' - else returnS vars s')) s - -val untilS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) -> - ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e -let rec untilS vars cond body s = - (body vars >>$= (fun vars s' -> - (cond vars >>$= (fun cond_val s'' -> - if cond_val then returnS vars s'' else untilS vars cond body s'')) s')) s -*) diff --git a/snapshots/coq-riscv/sail/lib/coq/Sail2_state_monad.v b/snapshots/coq-riscv/sail/lib/coq/Sail2_state_monad.v deleted file mode 100644 index c48db31b..00000000 --- a/snapshots/coq-riscv/sail/lib/coq/Sail2_state_monad.v +++ /dev/null @@ -1,253 +0,0 @@ -Require Import Sail2_instr_kinds. -Require Import Sail2_values. -(* -(* 'a is result type *) - -type memstate = map integer memory_byte -type tagstate = map integer bitU -(* type regstate = map string (vector bitU) *) - -type sequential_state 'regs = - <| regstate : 'regs; - memstate : memstate; - tagstate : tagstate; - write_ea : maybe (write_kind * integer * integer); - last_exclusive_operation_was_load : bool|> - -val init_state : forall 'regs. 'regs -> sequential_state 'regs -let init_state regs = - <| regstate = regs; - memstate = Map.empty; - tagstate = Map.empty; - write_ea = Nothing; - last_exclusive_operation_was_load = false |> - -type ex 'e = - | Failure of string - | Throw of 'e - -type result 'a 'e = - | Value of 'a - | Ex of (ex 'e) - -(* State, nondeterminism and exception monad with result value type 'a - and exception type 'e. *) -type monadS 'regs 'a 'e = sequential_state 'regs -> list (result 'a 'e * sequential_state 'regs) - -val returnS : forall 'regs 'a 'e. 'a -> monadS 'regs 'a 'e -let returnS a s = [(Value a,s)] - -val bindS : forall 'regs 'a 'b 'e. monadS 'regs 'a 'e -> ('a -> monadS 'regs 'b 'e) -> monadS 'regs 'b 'e -let bindS m f (s : sequential_state 'regs) = - List.concatMap (function - | (Value a, s') -> f a s' - | (Ex e, s') -> [(Ex e, s')] - end) (m s) - -val seqS: forall 'regs 'b 'e. monadS 'regs unit 'e -> monadS 'regs 'b 'e -> monadS 'regs 'b 'e -let seqS m n = bindS m (fun (_ : unit) -> n) - -let inline (>>$=) = bindS -let inline (>>$) = seqS - -val chooseS : forall 'regs 'a 'e. list 'a -> monadS 'regs 'a 'e -let chooseS xs s = List.map (fun x -> (Value x, s)) xs - -val readS : forall 'regs 'a 'e. (sequential_state 'regs -> 'a) -> monadS 'regs 'a 'e -let readS f = (fun s -> returnS (f s) s) - -val updateS : forall 'regs 'e. (sequential_state 'regs -> sequential_state 'regs) -> monadS 'regs unit 'e -let updateS f = (fun s -> returnS () (f s)) - -val failS : forall 'regs 'a 'e. string -> monadS 'regs 'a 'e -let failS msg s = [(Ex (Failure msg), s)] - -val exitS : forall 'regs 'e 'a. unit -> monadS 'regs 'a 'e -let exitS () = failS "exit" - -val throwS : forall 'regs 'a 'e. 'e -> monadS 'regs 'a 'e -let throwS e s = [(Ex (Throw e), s)] - -val try_catchS : forall 'regs 'a 'e1 'e2. monadS 'regs 'a 'e1 -> ('e1 -> monadS 'regs 'a 'e2) -> monadS 'regs 'a 'e2 -let try_catchS m h s = - List.concatMap (function - | (Value a, s') -> returnS a s' - | (Ex (Throw e), s') -> h e s' - | (Ex (Failure msg), s') -> [(Ex (Failure msg), s')] - end) (m s) - -val assert_expS : forall 'regs 'e. bool -> string -> monadS 'regs unit 'e -let assert_expS exp msg = if exp then returnS () else failS msg - -(* For early return, we abuse exceptions by throwing and catching - the return value. The exception type is "either 'r 'e", where "Right e" - represents a proper exception and "Left r" an early return of value "r". *) -type monadSR 'regs 'a 'r 'e = monadS 'regs 'a (either 'r 'e) - -val early_returnS : forall 'regs 'a 'r 'e. 'r -> monadSR 'regs 'a 'r 'e -let early_returnS r = throwS (Left r) - -val catch_early_returnS : forall 'regs 'a 'e. monadSR 'regs 'a 'a 'e -> monadS 'regs 'a 'e -let catch_early_returnS m = - try_catchS m - (function - | Left a -> returnS a - | Right e -> throwS e - end) - -(* Lift to monad with early return by wrapping exceptions *) -val liftSR : forall 'a 'r 'regs 'e. monadS 'regs 'a 'e -> monadSR 'regs 'a 'r 'e -let liftSR m = try_catchS m (fun e -> throwS (Right e)) - -(* Catch exceptions in the presence of early returns *) -val try_catchSR : forall 'regs 'a 'r 'e1 'e2. monadSR 'regs 'a 'r 'e1 -> ('e1 -> monadSR 'regs 'a 'r 'e2) -> monadSR 'regs 'a 'r 'e2 -let try_catchSR m h = - try_catchS m - (function - | Left r -> throwS (Left r) - | Right e -> h e - end) - -val read_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> monadS 'regs bitU 'e -let read_tagS addr = - readS (fun s -> fromMaybe B0 (Map.lookup (unsigned addr) s.tagstate)) - -(* Read bytes from memory and return in little endian order *) -val read_mem_bytesS : forall 'regs 'e 'a. Bitvector 'a => read_kind -> 'a -> nat -> monadS 'regs (list memory_byte) 'e -let read_mem_bytesS read_kind addr sz = - let addr = unsigned addr in - let sz = integerFromNat sz in - let addrs = index_list addr (addr+sz-1) 1 in - let read_byte s addr = Map.lookup addr s.memstate in - readS (fun s -> just_list (List.map (read_byte s) addrs)) >>$= (function - | Just mem_val -> - updateS (fun s -> - if read_is_exclusive read_kind - then <| s with last_exclusive_operation_was_load = true |> - else s) >>$ - returnS mem_val - | Nothing -> failS "read_memS" - end) - -val read_memS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monadS 'regs 'b 'e -let read_memS rk a sz = - read_mem_bytesS rk a (natFromInteger sz) >>$= (fun bytes -> - returnS (bits_of_mem_bytes bytes)) - -val excl_resultS : forall 'regs 'e. unit -> monadS 'regs bool 'e -let excl_resultS () = - readS (fun s -> s.last_exclusive_operation_was_load) >>$= (fun excl_load -> - updateS (fun s -> <| s with last_exclusive_operation_was_load = false |>) >>$ - chooseS (if excl_load then [false; true] else [false])) - -val write_mem_eaS : forall 'regs 'e 'a. Bitvector 'a => write_kind -> 'a -> nat -> monadS 'regs unit 'e -let write_mem_eaS write_kind addr sz = - let addr = unsigned addr in - let sz = integerFromNat sz in - updateS (fun s -> <| s with write_ea = Just (write_kind, addr, sz) |>) - -(* Write little-endian list of bytes to previously announced address *) -val write_mem_bytesS : forall 'regs 'e. list memory_byte -> monadS 'regs bool 'e -let write_mem_bytesS v = - readS (fun s -> s.write_ea) >>$= (function - | Nothing -> failS "write ea has not been announced yet" - | Just (_, addr, sz) -> - let addrs = index_list addr (addr+sz-1) 1 in - (*let v = external_mem_value (bits_of v) in*) - let a_v = List.zip addrs v in - let write_byte mem (addr, v) = Map.insert addr v mem in - updateS (fun s -> - <| s with memstate = List.foldl write_byte s.memstate a_v |>) >>$ - returnS true - end) - -val write_mem_valS : forall 'regs 'e 'a. Bitvector 'a => 'a -> monadS 'regs bool 'e -let write_mem_valS v = match mem_bytes_of_bits v with - | Just v -> write_mem_bytesS v - | Nothing -> failS "write_mem_val" -end - -val write_tagS : forall 'regs 'e. bitU -> monadS 'regs bool 'e -let write_tagS t = - readS (fun s -> s.write_ea) >>$= (function - | Nothing -> failS "write ea has not been announced yet" - | Just (_, addr, _) -> - (*let taddr = addr / cap_alignment in*) - updateS (fun s -> <| s with tagstate = Map.insert addr t s.tagstate |>) >>$ - returnS true - end) - -val read_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> monadS 'regs 'a 'e -let read_regS reg = readS (fun s -> reg.read_from s.regstate) - -(* TODO -let read_reg_range reg i j state = - let v = slice (get_reg state (name_of_reg reg)) i j in - [(Value (vec_to_bvec v),state)] -let read_reg_bit reg i state = - let v = access (get_reg state (name_of_reg reg)) i in - [(Value v,state)] -let read_reg_field reg regfield = - let (i,j) = register_field_indices reg regfield in - read_reg_range reg i j -let read_reg_bitfield reg regfield = - let (i,_) = register_field_indices reg regfield in - read_reg_bit reg i *) - -val read_regvalS : forall 'regs 'rv 'e. - register_accessors 'regs 'rv -> string -> monadS 'regs 'rv 'e -let read_regvalS (read, _) reg = - readS (fun s -> read reg s.regstate) >>$= (function - | Just v -> returnS v - | Nothing -> failS ("read_regvalS " ^ reg) - end) - -val write_regvalS : forall 'regs 'rv 'e. - register_accessors 'regs 'rv -> string -> 'rv -> monadS 'regs unit 'e -let write_regvalS (_, write) reg v = - readS (fun s -> write reg v s.regstate) >>$= (function - | Just rs' -> updateS (fun s -> <| s with regstate = rs' |>) - | Nothing -> failS ("write_regvalS " ^ reg) - end) - -val write_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> 'a -> monadS 'regs unit 'e -let write_regS reg v = - updateS (fun s -> <| s with regstate = reg.write_to v s.regstate |>) - -(* TODO -val update_reg : forall 'regs 'rv 'a 'b 'e. register_ref 'regs 'rv 'a -> ('a -> 'b -> 'a) -> 'b -> monadS 'regs unit 'e -let update_reg reg f v state = - let current_value = get_reg state reg in - let new_value = f current_value v in - [(Value (), set_reg state reg new_value)] - -let write_reg_field reg regfield = update_reg reg regfield.set_field - -val update_reg_range : forall 'regs 'rv 'a 'b. Bitvector 'a, Bitvector 'b => register_ref 'regs 'rv 'a -> integer -> integer -> 'a -> 'b -> 'a -let update_reg_range reg i j reg_val new_val = set_bits (reg.is_inc) reg_val i j (bits_of new_val) -let write_reg_range reg i j = update_reg reg (update_reg_range reg i j) - -let update_reg_pos reg i reg_val x = update_list reg.is_inc reg_val i x -let write_reg_pos reg i = update_reg reg (update_reg_pos reg i) - -let update_reg_bit reg i reg_val bit = set_bit (reg.is_inc) reg_val i (to_bitU bit) -let write_reg_bit reg i = update_reg reg (update_reg_bit reg i) - -let update_reg_field_range regfield i j reg_val new_val = - let current_field_value = regfield.get_field reg_val in - let new_field_value = set_bits (regfield.field_is_inc) current_field_value i j (bits_of new_val) in - regfield.set_field reg_val new_field_value -let write_reg_field_range reg regfield i j = update_reg reg (update_reg_field_range regfield i j) - -let update_reg_field_pos regfield i reg_val x = - let current_field_value = regfield.get_field reg_val in - let new_field_value = update_list regfield.field_is_inc current_field_value i x in - regfield.set_field reg_val new_field_value -let write_reg_field_pos reg regfield i = update_reg reg (update_reg_field_pos regfield i) - -let update_reg_field_bit regfield i reg_val bit = - let current_field_value = regfield.get_field reg_val in - let new_field_value = set_bit (regfield.field_is_inc) current_field_value i (to_bitU bit) in - regfield.set_field reg_val new_field_value -let write_reg_field_bit reg regfield i = update_reg reg (update_reg_field_bit regfield i)*) -*) diff --git a/snapshots/coq-riscv/sail/lib/coq/Sail2_string.v b/snapshots/coq-riscv/sail/lib/coq/Sail2_string.v deleted file mode 100644 index c8bf5f9f..00000000 --- a/snapshots/coq-riscv/sail/lib/coq/Sail2_string.v +++ /dev/null @@ -1,162 +0,0 @@ -Require Import Sail2_values. - -Definition string_sub (s : string) (start : Z) (len : Z) : string := - String.substring (Z.to_nat start) (Z.to_nat len) s. - -Definition string_startswith s expected := - let prefix := String.substring 0 (String.length expected) s in - generic_eq prefix expected. - -Definition string_drop s (n : {n : Z & ArithFact (n >= 0)}) := - let n := Z.to_nat (projT1 n) in - String.substring n (String.length s - n) s. - -Definition string_length s : {n : Z & ArithFact (n >= 0)} := - build_ex (Z.of_nat (String.length s)). - -Definition string_append := String.append. - -Local Open Scope char_scope. -Local Definition hex_char (c : Ascii.ascii) : option Z := -match c with -| "0" => Some 0 -| "1" => Some 1 -| "2" => Some 2 -| "3" => Some 3 -| "4" => Some 4 -| "5" => Some 5 -| "6" => Some 6 -| "7" => Some 7 -| "8" => Some 8 -| "9" => Some 9 -| "a" => Some 10 -| "b" => Some 11 -| "c" => Some 12 -| "d" => Some 13 -| "e" => Some 14 -| "f" => Some 15 -| _ => None -end. -Local Close Scope char_scope. -Local Fixpoint more_digits (s : string) (base : Z) (acc : Z) (len : nat) : Z * nat := -match s with -| EmptyString => (acc, len) -| String "_" t => more_digits t base acc (S len) -| String h t => - match hex_char h with - | None => (acc, len) - | Some i => - if i = 0)}) := -match s with -| EmptyString => None -| String h t => - match hex_char h with - | None => None - | Some i => - if i = 0)}) := -match s with -| EmptyString => None -| String "0" (String ("x"|"X") t) => int_of t 16 2 -| String "0" (String ("o"|"O") t) => int_of t 8 2 -| String "0" (String ("b"|"B") t) => int_of t 2 2 -| String "0" (String "u" t) => int_of t 10 2 -| String "-" t => - match int_of t 10 1 with - | None => None - | Some (i,len) => Some (-i,len) - end -| _ => int_of s 10 0 -end. - -Definition maybe_int_of_string (s : string) : option Z := -match maybe_int_of_prefix s with -| None => None -| Some (i,len) => - if projT1 len =? projT1 (string_length s) - then Some i - else None -end. - -Fixpoint n_leading_spaces (s:string) : nat := - match s with - | EmptyString => 0 - | String " " t => S (n_leading_spaces t) - | _ => 0 - end. - -Definition opt_spc_matches_prefix s : option (unit * {n : Z & ArithFact (n >= 0)}) := - Some (tt, build_ex (Z.of_nat (n_leading_spaces s))). - -Definition spc_matches_prefix s : option (unit * {n : Z & ArithFact (n >= 0)}) := - match n_leading_spaces s with - | O => None - | S n => Some (tt, build_ex (Z.of_nat (S n))) - end. - -Definition hex_bits_n_matches_prefix sz `{ArithFact (sz >= 0)} s : option (mword sz * {n : Z & ArithFact (n >= 0)}) := - match maybe_int_of_prefix s with - | None => None - | Some (n, len) => - if andb (0 <=? n) (n acc -| S limit' => - let (d,m) := N.div_eucl n 10 in - let acc := String (Ascii.ascii_of_N (m + zero)) acc in - if N.ltb 0 d then string_of_N limit' d acc else acc -end. -Local Fixpoint pos_limit p := -match p with -| xH => S O -| xI p | xO p => S (pos_limit p) -end. -Definition string_of_int (z : Z) : string := -match z with -| Z0 => "0" -| Zpos p => string_of_N (pos_limit p) (Npos p) "" -| Zneg p => String "-" (string_of_N (pos_limit p) (Npos p) "") -end. - - diff --git a/snapshots/coq-riscv/sail/lib/coq/Sail2_values.v b/snapshots/coq-riscv/sail/lib/coq/Sail2_values.v deleted file mode 100644 index eaf75840..00000000 --- a/snapshots/coq-riscv/sail/lib/coq/Sail2_values.v +++ /dev/null @@ -1,1688 +0,0 @@ -(* Version of sail_values.lem that uses Lems machine words library *) - -(*Require Import Sail_impl_base*) -Require Export ZArith. -Require Import Ascii. -Require Export String. -Require Import bbv.Word. -Require Export List. -Require Export Sumbool. -Require Export DecidableClass. -Import ListNotations. - -Open Scope Z. - -(* Constraint solving basics. A HintDb which unfolding hints and lemmata - can be added to, and a typeclass to wrap constraint arguments in to - trigger automatic solving. *) -Create HintDb sail. -Class ArithFact (P : Prop) := { fact : P }. -Lemma use_ArithFact {P} `(ArithFact P) : P. -apply fact. -Defined. - -Definition build_ex {T:Type} (n:T) {P:T -> Prop} `{H:ArithFact (P n)} : {x : T & ArithFact (P x)} := - existT _ n H. - -Definition generic_eq {T:Type} (x y:T) `{Decidable (x = y)} := Decidable_witness. -Definition generic_neq {T:Type} (x y:T) `{Decidable (x = y)} := negb Decidable_witness. -Lemma generic_eq_true {T} {x y:T} `{Decidable (x = y)} : generic_eq x y = true -> x = y. -apply Decidable_spec. -Qed. -Lemma generic_eq_false {T} {x y:T} `{Decidable (x = y)} : generic_eq x y = false -> x <> y. -unfold generic_eq. -intros H1 H2. -rewrite <- Decidable_spec in H2. -congruence. -Qed. -Lemma generic_neq_true {T} {x y:T} `{Decidable (x = y)} : generic_neq x y = true -> x <> y. -unfold generic_neq. -intros H1 H2. -rewrite <- Decidable_spec in H2. -destruct Decidable_witness; simpl in *; -congruence. -Qed. -Lemma generic_neq_false {T} {x y:T} `{Decidable (x = y)} : generic_neq x y = false -> x = y. -unfold generic_neq. -intro H1. -rewrite <- Decidable_spec. -destruct Decidable_witness; simpl in *; -congruence. -Qed. -Instance Decidable_eq_from_dec {T:Type} (eqdec: forall x y : T, {x = y} + {x <> y}) : - forall (x y : T), Decidable (eq x y) := { - Decidable_witness := proj1_sig (bool_of_sumbool (eqdec x y)) -}. -destruct (eqdec x y); simpl; split; congruence. -Defined. - -Instance Decidable_eq_string : forall (x y : string), Decidable (x = y) := - Decidable_eq_from_dec String.string_dec. - - -(* Project away range constraints in comparisons *) -Definition ltb_range_l {lo hi} (l : {x & ArithFact (lo <= x /\ x <= hi)}) r := Z.ltb (projT1 l) r. -Definition leb_range_l {lo hi} (l : {x & ArithFact (lo <= x /\ x <= hi)}) r := Z.leb (projT1 l) r. -Definition gtb_range_l {lo hi} (l : {x & ArithFact (lo <= x /\ x <= hi)}) r := Z.gtb (projT1 l) r. -Definition geb_range_l {lo hi} (l : {x & ArithFact (lo <= x /\ x <= hi)}) r := Z.geb (projT1 l) r. -Definition ltb_range_r {lo hi} l (r : {x & ArithFact (lo <= x /\ x <= hi)}) := Z.ltb l (projT1 r). -Definition leb_range_r {lo hi} l (r : {x & ArithFact (lo <= x /\ x <= hi)}) := Z.leb l (projT1 r). -Definition gtb_range_r {lo hi} l (r : {x & ArithFact (lo <= x /\ x <= hi)}) := Z.gtb l (projT1 r). -Definition geb_range_r {lo hi} l (r : {x & ArithFact (lo <= x /\ x <= hi)}) := Z.geb l (projT1 r). - -Definition ii := Z. -Definition nn := nat. - -(*val pow : Z -> Z -> Z*) -Definition pow m n := m ^ n. - -Program Definition pow2 n : {z : Z & ArithFact (2 ^ n <= z <= 2 ^ n)} := existT _ (pow 2 n) _. -Next Obligation. -constructor. -unfold pow. -auto using Z.le_refl. -Qed. - -(* -Definition inline lt := (<) -Definition inline gt := (>) -Definition inline lteq := (<=) -Definition inline gteq := (>=) - -val eq : forall a. Eq a => a -> a -> bool -Definition inline eq l r := (l = r) - -val neq : forall a. Eq a => a -> a -> bool*) -Definition neq l r := (negb (l =? r)). (* Z only *) - -(*let add_int l r := integerAdd l r -Definition add_signed l r := integerAdd l r -Definition sub_int l r := integerMinus l r -Definition mult_int l r := integerMult l r -Definition div_int l r := integerDiv l r -Definition div_nat l r := natDiv l r -Definition power_int_nat l r := integerPow l r -Definition power_int_int l r := integerPow l (Z.to_nat r) -Definition negate_int i := integerNegate i -Definition min_int l r := integerMin l r -Definition max_int l r := integerMax l r - -Definition add_real l r := realAdd l r -Definition sub_real l r := realMinus l r -Definition mult_real l r := realMult l r -Definition div_real l r := realDiv l r -Definition negate_real r := realNegate r -Definition abs_real r := realAbs r -Definition power_real b e := realPowInteger b e*) - -Definition print_endline (_ : string) : unit := tt. -Definition prerr_endline (_ : string) : unit := tt. -Definition prerr (_ : string) : unit := tt. -Definition print_int (_ : string) (_ : Z) : unit := tt. -Definition prerr_int (_ : string) (_ : Z) : unit := tt. -Definition putchar (_ : Z) : unit := tt. - -Definition shl_int := Z.shiftl. -Definition shr_int := Z.shiftr. - -(* -Definition or_bool l r := (l || r) -Definition and_bool l r := (l && r) -Definition xor_bool l r := xor l r -*) -Definition append_list {A:Type} (l : list A) r := l ++ r. -Definition length_list {A:Type} (xs : list A) := Z.of_nat (List.length xs). -Definition take_list {A:Type} n (xs : list A) := firstn (Z.to_nat n) xs. -Definition drop_list {A:Type} n (xs : list A) := skipn (Z.to_nat n) xs. -(* -val repeat : forall a. list a -> Z -> list a*) -Fixpoint repeat' {a} (xs : list a) n := - match n with - | O => [] - | S n => xs ++ repeat' xs n - end. -Lemma repeat'_length {a} {xs : list a} {n : nat} : List.length (repeat' xs n) = (n * List.length xs)%nat. -induction n. -* reflexivity. -* simpl. - rewrite app_length. - auto with arith. -Qed. -Definition repeat {a} (xs : list a) (n : Z) := - if n <=? 0 then [] - else repeat' xs (Z.to_nat n). -Lemma repeat_length {a} {xs : list a} {n : Z} (H : n >= 0) : length_list (repeat xs n) = n * length_list xs. -unfold length_list, repeat. -destruct n. -+ reflexivity. -+ simpl (List.length _). - rewrite repeat'_length. - rewrite Nat2Z.inj_mul. - rewrite positive_nat_Z. - reflexivity. -+ exfalso. - auto with zarith. -Qed. - -(*declare {isabelle} termination_argument repeat = automatic - -Definition duplicate_to_list bit length := repeat [bit] length - -Fixpoint replace bs (n : Z) b' := match bs with - | [] => [] - | b :: bs => - if n = 0 then b' :: bs - else b :: replace bs (n - 1) b' - end -declare {isabelle} termination_argument replace = automatic - -Definition upper n := n - -(* Modulus operation corresponding to quot below -- result - has sign of dividend. *) -Definition hardware_mod (a: Z) (b:Z) : Z := - let m := (abs a) mod (abs b) in - if a < 0 then ~m else m - -(* There are different possible answers for integer divide regarding -rounding behaviour on negative operands. Positive operands always -round down so derive the one we want (trucation towards zero) from -that *) -Definition hardware_quot (a:Z) (b:Z) : Z := - let q := (abs a) / (abs b) in - if ((a<0) = (b<0)) then - q (* same sign -- result positive *) - else - ~q (* different sign -- result negative *) - -Definition max_64u := (integerPow 2 64) - 1 -Definition max_64 := (integerPow 2 63) - 1 -Definition min_64 := 0 - (integerPow 2 63) -Definition max_32u := (4294967295 : Z) -Definition max_32 := (2147483647 : Z) -Definition min_32 := (0 - 2147483648 : Z) -Definition max_8 := (127 : Z) -Definition min_8 := (0 - 128 : Z) -Definition max_5 := (31 : Z) -Definition min_5 := (0 - 32 : Z) -*) - -(* just_list takes a list of maybes and returns Some xs if all elements have - a value, and None if one of the elements is None. *) -(*val just_list : forall a. list (option a) -> option (list a)*) -Fixpoint just_list {A} (l : list (option A)) := match l with - | [] => Some [] - | (x :: xs) => - match (x, just_list xs) with - | (Some x, Some xs) => Some (x :: xs) - | (_, _) => None - end - end. -(*declare {isabelle} termination_argument just_list = automatic - -lemma just_list_spec: - ((forall xs. (just_list xs = None) <-> List.elem None xs) && - (forall xs es. (just_list xs = Some es) <-> (xs = List.map Some es)))*) - -Lemma just_list_length {A} : forall (l : list (option A)) (l' : list A), - Some l' = just_list l -> List.length l = List.length l'. -induction l. -* intros. - simpl in H. - inversion H. - reflexivity. -* intros. - destruct a; simplify_eq H. - simpl in *. - destruct (just_list l); simplify_eq H. - intros. - subst. - simpl. - f_equal. - apply IHl. - reflexivity. -Qed. - -Lemma just_list_length_Z {A} : forall (l : list (option A)) l', Some l' = just_list l -> length_list l = length_list l'. -unfold length_list. -intros. -f_equal. -auto using just_list_length. -Qed. - -Fixpoint member_Z_list (x : Z) (l : list Z) : bool := -match l with -| [] => false -| h::t => if x =? h then true else member_Z_list x t -end. - -Lemma member_Z_list_In {x l} : member_Z_list x l = true <-> In x l. -induction l. -* simpl. split. congruence. tauto. -* simpl. destruct (x =? a) eqn:H. - + rewrite Z.eqb_eq in H. subst. tauto. - + rewrite Z.eqb_neq in H. split. - - intro Heq. right. apply IHl. assumption. - - intros [bad | good]. congruence. apply IHl. assumption. -Qed. - -(*** Bits *) -Inductive bitU := B0 | B1 | BU. - -Definition showBitU b := -match b with - | B0 => "O" - | B1 => "I" - | BU => "U" -end%string. - -Definition bitU_char b := -match b with -| B0 => "0" -| B1 => "1" -| BU => "?" -end%char. - -(*instance (Show bitU) - let show := showBitU -end*) - -Class BitU (a : Type) : Type := { - to_bitU : a -> bitU; - of_bitU : bitU -> a -}. - -Instance bitU_BitU : (BitU bitU) := { - to_bitU b := b; - of_bitU b := b -}. - -Definition bool_of_bitU bu := match bu with - | B0 => Some false - | B1 => Some true - | BU => None - end. - -Definition bitU_of_bool (b : bool) := if b then B1 else B0. - -(*Instance bool_BitU : (BitU bool) := { - to_bitU := bitU_of_bool; - of_bitU := bool_of_bitU -}.*) - -Definition cast_bit_bool := bool_of_bitU. -(* -Definition bit_lifted_of_bitU bu := match bu with - | B0 => Bitl_zero - | B1 => Bitl_one - | BU => Bitl_undef - end. - -Definition bitU_of_bit := function - | Bitc_zero => B0 - | Bitc_one => B1 - end. - -Definition bit_of_bitU := function - | B0 => Bitc_zero - | B1 => Bitc_one - | BU => failwith "bit_of_bitU: BU" - end. - -Definition bitU_of_bit_lifted := function - | Bitl_zero => B0 - | Bitl_one => B1 - | Bitl_undef => BU - | Bitl_unknown => failwith "bitU_of_bit_lifted Bitl_unknown" - end. -*) -Definition not_bit b := -match b with - | B1 => B0 - | B0 => B1 - | BU => BU - end. - -(*val is_one : Z -> bitU*) -Definition is_one (i : Z) := - if i =? 1 then B1 else B0. - -Definition binop_bit op x y := - match (x, y) with - | (BU,_) => BU (*Do we want to do this or to respect | of I and & of B0 rules?*) - | (_,BU) => BU (*Do we want to do this or to respect | of I and & of B0 rules?*) - | (x,y) => bitU_of_bool (op (bool_of_bitU x) (bool_of_bitU y)) - end. - -(*val and_bit : bitU -> bitU -> bitU -Definition and_bit := binop_bit (&&) - -val or_bit : bitU -> bitU -> bitU -Definition or_bit := binop_bit (||) - -val xor_bit : bitU -> bitU -> bitU -Definition xor_bit := binop_bit xor - -val (&.) : bitU -> bitU -> bitU -Definition inline (&.) x y := and_bit x y - -val (|.) : bitU -> bitU -> bitU -Definition inline (|.) x y := or_bit x y - -val (+.) : bitU -> bitU -> bitU -Definition inline (+.) x y := xor_bit x y -*) - -(*** Bool lists ***) - -(*val bools_of_nat_aux : integer -> natural -> list bool -> list bool*) -Fixpoint bools_of_nat_aux len (x : nat) (acc : list bool) : list bool := - match len with - | O => acc - | S len' => bools_of_nat_aux len' (x / 2) ((if x mod 2 =? 1 then true else false) :: acc) - end %nat. - (*else (if x mod 2 = 1 then true else false) :: bools_of_nat_aux (x / 2)*) -(*declare {isabelle} termination_argument bools_of_nat_aux = automatic*) -Definition bools_of_nat len n := bools_of_nat_aux (Z.to_nat len) n [] (*List.reverse (bools_of_nat_aux n)*). - -(*val nat_of_bools_aux : natural -> list bool -> natural*) -Fixpoint nat_of_bools_aux (acc : nat) (bs : list bool) : nat := - match bs with - | [] => acc - | true :: bs => nat_of_bools_aux ((2 * acc) + 1) bs - | false :: bs => nat_of_bools_aux (2 * acc) bs -end. -(*declare {isabelle; hol} termination_argument nat_of_bools_aux = automatic*) -Definition nat_of_bools bs := nat_of_bools_aux 0 bs. - -(*val unsigned_of_bools : list bool -> integer*) -Definition unsigned_of_bools bs := Z.of_nat (nat_of_bools bs). - -(*val signed_of_bools : list bool -> integer*) -Definition signed_of_bools bs := - match bs with - | true :: _ => 0 - (1 + (unsigned_of_bools (List.map negb bs))) - | false :: _ => unsigned_of_bools bs - | [] => 0 (* Treat empty list as all zeros *) - end. - -(*val int_of_bools : bool -> list bool -> integer*) -Definition int_of_bools (sign : bool) bs := if sign then signed_of_bools bs else unsigned_of_bools bs. - -(*val pad_list : forall 'a. 'a -> list 'a -> integer -> list 'a*) -Fixpoint pad_list_nat {a} (x : a) (xs : list a) n := - match n with - | O => xs - | S n' => pad_list_nat x (x :: xs) n' - end. -(*declare {isabelle} termination_argument pad_list = automatic*) -Definition pad_list {a} x xs n := @pad_list_nat a x xs (Z.to_nat n). - -Definition ext_list {a} pad len (xs : list a) := - let longer := len - (Z.of_nat (List.length xs)) in - if longer ext_list true len bs - | _ => ext_list false len bs - end. - -Fixpoint add_one_bool_ignore_overflow_aux bits := match bits with - | [] => [] - | false :: bits => true :: bits - | true :: bits => false :: add_one_bool_ignore_overflow_aux bits -end. -(*declare {isabelle; hol} termination_argument add_one_bool_ignore_overflow_aux = automatic*) - -Definition add_one_bool_ignore_overflow bits := - List.rev (add_one_bool_ignore_overflow_aux (List.rev bits)). - -(*let bool_list_of_int n = - let bs_abs = false :: bools_of_nat (naturalFromInteger (abs n)) in - if n >= (0 : integer) then bs_abs - else add_one_bool_ignore_overflow (List.map not bs_abs) -let bools_of_int len n = exts_bools len (bool_list_of_int n)*) -Definition bools_of_int len n := - let bs_abs := bools_of_nat len (Z.abs_nat n) in - if n >=? 0 then bs_abs - else add_one_bool_ignore_overflow (List.map negb bs_abs). - -(*** Bit lists ***) - -(*val bits_of_nat_aux : natural -> list bitU*) -Fixpoint bits_of_nat_aux n x := - match n,x with - | O,_ => [] - | _,O => [] - | S n, S _ => (if x mod 2 =? 1 then B1 else B0) :: bits_of_nat_aux n (x / 2) - end%nat. -(**declare {isabelle} termination_argument bits_of_nat_aux = automatic*) -Definition bits_of_nat n := List.rev (bits_of_nat_aux n n). - -(*val nat_of_bits_aux : natural -> list bitU -> natural*) -Fixpoint nat_of_bits_aux acc bs := match bs with - | [] => Some acc - | B1 :: bs => nat_of_bits_aux ((2 * acc) + 1) bs - | B0 :: bs => nat_of_bits_aux (2 * acc) bs - | BU :: bs => None -end%nat. -(*declare {isabelle} termination_argument nat_of_bits_aux = automatic*) -Definition nat_of_bits bits := nat_of_bits_aux 0 bits. - -Definition not_bits := List.map not_bit. - -Definition binop_bits op bsl bsr := - List.fold_right (fun '(bl, br) acc => binop_bit op bl br :: acc) [] (List.combine bsl bsr). -(* -Definition and_bits := binop_bits (&&) -Definition or_bits := binop_bits (||) -Definition xor_bits := binop_bits xor - -val unsigned_of_bits : list bitU -> Z*) -Definition unsigned_of_bits bits := -match just_list (List.map bool_of_bitU bits) with -| Some bs => Some (unsigned_of_bools bs) -| None => None -end. - -(*val signed_of_bits : list bitU -> Z*) -Definition signed_of_bits bits := - match just_list (List.map bool_of_bitU bits) with - | Some bs => Some (signed_of_bools bs) - | None => None - end. - -(*val int_of_bits : bool -> list bitU -> maybe integer*) -Definition int_of_bits (sign : bool) bs := - if sign then signed_of_bits bs else unsigned_of_bits bs. - -(*val pad_bitlist : bitU -> list bitU -> Z -> list bitU*) -Fixpoint pad_bitlist_nat (b : bitU) bits n := -match n with -| O => bits -| S n' => pad_bitlist_nat b (b :: bits) n' -end. -Definition pad_bitlist b bits n := pad_bitlist_nat b bits (Z.to_nat n). (* Negative n will come out as 0 *) -(* if n <= 0 then bits else pad_bitlist b (b :: bits) (n - 1). -declare {isabelle} termination_argument pad_bitlist = automatic*) - -Definition ext_bits pad len bits := - let longer := len - (Z.of_nat (List.length bits)) in - if longer undefined_list_bitU (*failwith "exts_bits: undefined bit"*) - | B1 :: _ => ext_bits B1 len bits - | _ => ext_bits B0 len bits - end. - -Fixpoint add_one_bit_ignore_overflow_aux bits := match bits with - | [] => [] - | B0 :: bits => B1 :: bits - | B1 :: bits => B0 :: add_one_bit_ignore_overflow_aux bits - | BU :: _ => undefined_list_bitU (*failwith "add_one_bit_ignore_overflow: undefined bit"*) -end. -(*declare {isabelle} termination_argument add_one_bit_ignore_overflow_aux = automatic*) - -Definition add_one_bit_ignore_overflow bits := - rev (add_one_bit_ignore_overflow_aux (rev bits)). - -Definition bitlist_of_int n := - let bits_abs := B0 :: bits_of_nat (Z.abs_nat n) in - if n >=? 0 then bits_abs - else add_one_bit_ignore_overflow (not_bits bits_abs). - -Definition bits_of_int len n := exts_bits len (bitlist_of_int n). - -(*val arith_op_bits : - (integer -> integer -> integer) -> bool -> list bitU -> list bitU -> list bitU*) -Definition arith_op_bits (op : Z -> Z -> Z) (sign : bool) l r := - match (int_of_bits sign l, int_of_bits sign r) with - | (Some li, Some ri) => bits_of_int (length_list l) (op li ri) - | (_, _) => repeat [BU] (length_list l) - end. - - -Definition char_of_nibble x := - match x with - | (B0, B0, B0, B0) => Some "0"%char - | (B0, B0, B0, B1) => Some "1"%char - | (B0, B0, B1, B0) => Some "2"%char - | (B0, B0, B1, B1) => Some "3"%char - | (B0, B1, B0, B0) => Some "4"%char - | (B0, B1, B0, B1) => Some "5"%char - | (B0, B1, B1, B0) => Some "6"%char - | (B0, B1, B1, B1) => Some "7"%char - | (B1, B0, B0, B0) => Some "8"%char - | (B1, B0, B0, B1) => Some "9"%char - | (B1, B0, B1, B0) => Some "A"%char - | (B1, B0, B1, B1) => Some "B"%char - | (B1, B1, B0, B0) => Some "C"%char - | (B1, B1, B0, B1) => Some "D"%char - | (B1, B1, B1, B0) => Some "E"%char - | (B1, B1, B1, B1) => Some "F"%char - | _ => None - end. - -Fixpoint hexstring_of_bits bs := match bs with - | b1 :: b2 :: b3 :: b4 :: bs => - let n := char_of_nibble (b1, b2, b3, b4) in - let s := hexstring_of_bits bs in - match (n, s) with - | (Some n, Some s) => Some (String n s) - | _ => None - end - | [] => Some EmptyString - | _ => None - end%string. - -Fixpoint binstring_of_bits bs := match bs with - | b :: bs => String (bitU_char b) (binstring_of_bits bs) - | [] => EmptyString - end. - -Definition show_bitlist bs := - match hexstring_of_bits bs with - | Some s => String "0" (String "x" s) - | None => String "0" (String "b" (binstring_of_bits bs)) - end. - -(*** List operations *) -(* -Definition inline (^^) := append_list - -val subrange_list_inc : forall a. list a -> Z -> Z -> list a*) -Definition subrange_list_inc {A} (xs : list A) i j := - let toJ := firstn (Z.to_nat j + 1) xs in - let fromItoJ := skipn (Z.to_nat i) toJ in - fromItoJ. - -(*val subrange_list_dec : forall a. list a -> Z -> Z -> list a*) -Definition subrange_list_dec {A} (xs : list A) i j := - let top := (length_list xs) - 1 in - subrange_list_inc xs (top - i) (top - j). - -(*val subrange_list : forall a. bool -> list a -> Z -> Z -> list a*) -Definition subrange_list {A} (is_inc : bool) (xs : list A) i j := - if is_inc then subrange_list_inc xs i j else subrange_list_dec xs i j. - -Definition splitAt {A} n (l : list A) := (firstn n l, skipn n l). - -(*val update_subrange_list_inc : forall a. list a -> Z -> Z -> list a -> list a*) -Definition update_subrange_list_inc {A} (xs : list A) i j xs' := - let (toJ,suffix) := splitAt (Z.to_nat j + 1) xs in - let (prefix,_fromItoJ) := splitAt (Z.to_nat i) toJ in - prefix ++ xs' ++ suffix. - -(*val update_subrange_list_dec : forall a. list a -> Z -> Z -> list a -> list a*) -Definition update_subrange_list_dec {A} (xs : list A) i j xs' := - let top := (length_list xs) - 1 in - update_subrange_list_inc xs (top - i) (top - j) xs'. - -(*val update_subrange_list : forall a. bool -> list a -> Z -> Z -> list a -> list a*) -Definition update_subrange_list {A} (is_inc : bool) (xs : list A) i j xs' := - if is_inc then update_subrange_list_inc xs i j xs' else update_subrange_list_dec xs i j xs'. - -Open Scope nat. -Fixpoint nth_in_range {A} (n:nat) (l:list A) : n < length l -> A. -refine - (match n, l with - | O, h::_ => fun _ => h - | S m, _::t => fun H => nth_in_range A m t _ - | _,_ => fun H => _ - end). -exfalso. inversion H. -exfalso. inversion H. -simpl in H. omega. -Defined. - -Lemma nth_in_range_is_nth : forall A n (l : list A) d (H : n < length l), - nth_in_range n l H = nth n l d. -intros until d. revert n. -induction l; intros n H. -* inversion H. -* destruct n. - + reflexivity. - + apply IHl. -Qed. - -Lemma nth_Z_nat {A} {n} {xs : list A} : - (0 <= n)%Z -> (n < length_list xs)%Z -> Z.to_nat n < length xs. -unfold length_list. -intros nonneg bounded. -rewrite Z2Nat.inj_lt in bounded; auto using Zle_0_nat. -rewrite Nat2Z.id in bounded. -assumption. -Qed. - -(* -Lemma nth_top_aux {A} {n} {xs : list A} : Z.to_nat n < length xs -> let top := ((length_list xs) - 1)%Z in Z.to_nat (top - n)%Z < length xs. -unfold length_list. -generalize (length xs). -intro n0. -rewrite <- (Nat2Z.id n0). -intro H. -apply Z2Nat.inj_lt. -* omega. -*) - -Close Scope nat. - -(*val access_list_inc : forall a. list a -> Z -> a*) -Definition access_list_inc {A} (xs : list A) n `{ArithFact (0 <= n)} `{ArithFact (n < length_list xs)} := nth_in_range (Z.to_nat n) xs (nth_Z_nat (use_ArithFact _) (use_ArithFact _)). - -(*val access_list_dec : forall a. list a -> Z -> a*) -Definition access_list_dec {A} (xs : list A) n `{ArithFact (0 <= n)} `{ArithFact (n < length_list xs)} : A. -refine ( - let top := (length_list xs) - 1 in - @access_list_inc A xs (top - n) _ _). -constructor. apply use_ArithFact in H. apply use_ArithFact in H0. omega. -constructor. apply use_ArithFact in H. apply use_ArithFact in H0. omega. -Defined. - -(*val access_list : forall a. bool -> list a -> Z -> a*) -Definition access_list {A} (is_inc : bool) (xs : list A) n `{ArithFact (0 <= n)} `{ArithFact (n < length_list xs)} := - if is_inc then access_list_inc xs n else access_list_dec xs n. - -Definition access_list_opt_inc {A} (xs : list A) n := nth_error xs (Z.to_nat n). - -(*val access_list_dec : forall a. list a -> Z -> a*) -Definition access_list_opt_dec {A} (xs : list A) n := - let top := (length_list xs) - 1 in - access_list_opt_inc xs (top - n). - -(*val access_list : forall a. bool -> list a -> Z -> a*) -Definition access_list_opt {A} (is_inc : bool) (xs : list A) n := - if is_inc then access_list_opt_inc xs n else access_list_opt_dec xs n. - -Definition list_update {A} (xs : list A) n x := firstn n xs ++ x :: skipn (S n) xs. - -(*val update_list_inc : forall a. list a -> Z -> a -> list a*) -Definition update_list_inc {A} (xs : list A) n x := list_update xs (Z.to_nat n) x. - -(*val update_list_dec : forall a. list a -> Z -> a -> list a*) -Definition update_list_dec {A} (xs : list A) n x := - let top := (length_list xs) - 1 in - update_list_inc xs (top - n) x. - -(*val update_list : forall a. bool -> list a -> Z -> a -> list a*) -Definition update_list {A} (is_inc : bool) (xs : list A) n x := - if is_inc then update_list_inc xs n x else update_list_dec xs n x. - -(*Definition extract_only_element := function - | [] => failwith "extract_only_element called for empty list" - | [e] => e - | _ => failwith "extract_only_element called for list with more elements" -end*) - -(*** Machine words *) - -Definition mword (n : Z) := - match n with - | Zneg _ => False - | Z0 => word 0 - | Zpos p => word (Pos.to_nat p) - end. - -Definition get_word {n} : mword n -> word (Z.to_nat n) := - match n with - | Zneg _ => fun x => match x with end - | Z0 => fun x => x - | Zpos p => fun x => x - end. - -Definition with_word {n} {P : Type -> Type} : (word (Z.to_nat n) -> P (word (Z.to_nat n))) -> mword n -> P (mword n) := -match n with -| Zneg _ => fun f w => match w with end -| Z0 => fun f w => f w -| Zpos _ => fun f w => f w -end. - -Program Definition to_word {n} : n >= 0 -> word (Z.to_nat n) -> mword n := - match n with - | Zneg _ => fun H _ => _ - | Z0 => fun _ w => w - | Zpos _ => fun _ w => w - end. - -(*val length_mword : forall a. mword a -> Z*) -Definition length_mword {n} (w : mword n) := n. - -(*val slice_mword_dec : forall a b. mword a -> Z -> Z -> mword b*) -(*Definition slice_mword_dec w i j := word_extract (Z.to_nat i) (Z.to_nat j) w. - -val slice_mword_inc : forall a b. mword a -> Z -> Z -> mword b -Definition slice_mword_inc w i j := - let top := (length_mword w) - 1 in - slice_mword_dec w (top - i) (top - j) - -val slice_mword : forall a b. bool -> mword a -> Z -> Z -> mword b -Definition slice_mword is_inc w i j := if is_inc then slice_mword_inc w i j else slice_mword_dec w i j - -val update_slice_mword_dec : forall a b. mword a -> Z -> Z -> mword b -> mword a -Definition update_slice_mword_dec w i j w' := word_update w (Z.to_nat i) (Z.to_nat j) w' - -val update_slice_mword_inc : forall a b. mword a -> Z -> Z -> mword b -> mword a -Definition update_slice_mword_inc w i j w' := - let top := (length_mword w) - 1 in - update_slice_mword_dec w (top - i) (top - j) w' - -val update_slice_mword : forall a b. bool -> mword a -> Z -> Z -> mword b -> mword a -Definition update_slice_mword is_inc w i j w' := - if is_inc then update_slice_mword_inc w i j w' else update_slice_mword_dec w i j w' - -val access_mword_dec : forall a. mword a -> Z -> bitU*) -Parameter undefined_bit : bool. -Definition getBit {n} := -match n with -| O => fun (w : word O) i => undefined_bit -| S n => fun (w : word (S n)) i => wlsb (wrshift w i) -end. - -Definition access_mword_dec {m} (w : mword m) n := bitU_of_bool (getBit (get_word w) (Z.to_nat n)). - -(*val access_mword_inc : forall a. mword a -> Z -> bitU*) -Definition access_mword_inc {m} (w : mword m) n := - let top := (length_mword w) - 1 in - access_mword_dec w (top - n). - -(*Parameter access_mword : forall {a}, bool -> mword a -> Z -> bitU.*) -Definition access_mword {a} (is_inc : bool) (w : mword a) n := - if is_inc then access_mword_inc w n else access_mword_dec w n. - -Definition setBit {n} := -match n with -| O => fun (w : word O) i b => w -| S n => fun (w : word (S n)) i (b : bool) => - let bit : word (S n) := wlshift (natToWord _ 1) i in - let mask : word (S n) := wnot bit in - let masked := wand mask w in - if b then masked else wor masked bit -end. - -(*val update_mword_bool_dec : forall 'a. mword 'a -> integer -> bool -> mword 'a*) -Definition update_mword_bool_dec {a} (w : mword a) n b : mword a := - with_word (P := id) (fun w => setBit w (Z.to_nat n) b) w. -Definition update_mword_dec {a} (w : mword a) n b := - match bool_of_bitU b with - | Some bl => Some (update_mword_bool_dec w n bl) - | None => None - end. - -(*val update_mword_inc : forall a. mword a -> Z -> bitU -> mword a*) -Definition update_mword_inc {a} (w : mword a) n b := - let top := (length_mword w) - 1 in - update_mword_dec w (top - n) b. - -(*Parameter update_mword : forall {a}, bool -> mword a -> Z -> bitU -> mword a.*) -Definition update_mword {a} (is_inc : bool) (w : mword a) n b := - if is_inc then update_mword_inc w n b else update_mword_dec w n b. - -(*val int_of_mword : forall 'a. bool -> mword 'a -> integer*) -Definition int_of_mword {a} `{ArithFact (a >= 0)} (sign : bool) (w : mword a) := - if sign then wordToZ (get_word w) else Z.of_N (wordToN (get_word w)). - - -(*val mword_of_int : forall a. Size a => Z -> Z -> mword a -Definition mword_of_int len n := - let w := wordFromInteger n in - if (length_mword w = len) then w else failwith "unexpected word length" -*) -Program Definition mword_of_int {len} `{H:ArithFact (len >= 0)} n : mword len := -match len with -| Zneg _ => _ -| Z0 => ZToWord 0 n -| Zpos p => ZToWord (Pos.to_nat p) n -end. -Next Obligation. -destruct H. -auto. -Defined. -(* -(* Translating between a type level number (itself n) and an integer *) - -Definition size_itself_int x := Z.of_nat (size_itself x) - -(* NB: the corresponding sail type is forall n. atom(n) -> itself(n), - the actual integer is ignored. *) - -val make_the_value : forall n. Z -> itself n -Definition inline make_the_value x := the_value -*) - -Fixpoint bitlistFromWord_rev {n} w := -match w with -| WO => [] -| WS b w => b :: bitlistFromWord_rev w -end. -Definition bitlistFromWord {n} w := - List.rev (@bitlistFromWord_rev n w). - -Fixpoint wordFromBitlist_rev l : word (length l) := -match l with -| [] => WO -| b::t => WS b (wordFromBitlist_rev t) -end. -Definition wordFromBitlist l : word (length l) := - nat_cast _ (List.rev_length l) (wordFromBitlist_rev (List.rev l)). - -Local Open Scope nat. - -Fixpoint nat_diff {T : nat -> Type} n m {struct n} : -forall - (lt : forall p, T n -> T (n + p)) - (eq : T m -> T m) - (gt : forall p, T (m + p) -> T m), T n -> T m := -(match n, m return (forall p, T n -> T (n + p)) -> (T m -> T m) -> (forall p, T (m + p) -> T m) -> T n -> T m with -| O, O => fun lt eq gt => eq -| S n', O => fun lt eq gt => gt _ -| O, S m' => fun lt eq gt => lt _ -| S n', S m' => @nat_diff (fun x => T (S x)) n' m' -end). - -Definition fit_bbv_word {n m} : word n -> word m := -nat_diff n m - (fun p w => nat_cast _ (Nat.add_comm _ _) (extz w p)) - (fun w => w) - (fun p w => split2 _ _ (nat_cast _ (Nat.add_comm _ _) w)). - -Local Close Scope nat. - -(*** Bitvectors *) - -Class Bitvector (a:Type) : Type := { - bits_of : a -> list bitU; - of_bits : list bitU -> option a; - of_bools : list bool -> a; - (* The first parameter specifies the desired length of the bitvector *) - of_int : Z -> Z -> a; - length : a -> Z; - unsigned : a -> option Z; - signed : a -> option Z; - arith_op_bv : (Z -> Z -> Z) -> bool -> a -> a -> a -}. - -Instance bitlist_Bitvector {a : Type} `{BitU a} : (Bitvector (list a)) := { - bits_of v := List.map to_bitU v; - of_bits v := Some (List.map of_bitU v); - of_bools v := List.map of_bitU (List.map bitU_of_bool v); - of_int len n := List.map of_bitU (bits_of_int len n); - length := length_list; - unsigned v := unsigned_of_bits (List.map to_bitU v); - signed v := signed_of_bits (List.map to_bitU v); - arith_op_bv op sign l r := List.map of_bitU (arith_op_bits op sign (List.map to_bitU l) (List.map to_bitU r)) -}. - -Class ReasonableSize (a : Z) : Prop := { - isPositive : a >= 0 -}. - -(* Omega doesn't know about In, but can handle disjunctions. *) -Ltac unfold_In := -repeat match goal with -| H:context [member_Z_list _ _ = true] |- _ => rewrite member_Z_list_In in H -| H:context [In ?x (?y :: ?t)] |- _ => change (In x (y :: t)) with (y = x \/ In x t) in H -| H:context [In ?x []] |- _ => change (In x []) with False in H -end. - -(* Definitions in the context that involve proof for other constraints can - break some of the constraint solving tactics, so prune definition bodies - down to integer types. *) -Ltac not_Z ty := match ty with Z => fail 1 | _ => idtac end. -Ltac clear_non_Z_defns := - repeat match goal with H := _ : ?X |- _ => not_Z X; clearbody H end. -Ltac clear_irrelevant_defns := -repeat match goal with X := _ |- _ => - match goal with |- context[X] => idtac end || - match goal with _ : context[X] |- _ => idtac end || clear X -end. - -Lemma ArithFact_mword (a : Z) (w : mword a) : ArithFact (a >= 0). -constructor. -destruct a. -auto with zarith. -auto using Z.le_ge, Zle_0_pos. -destruct w. -Qed. -Ltac unwrap_ArithFacts := - repeat match goal with H:(ArithFact _) |- _ => let H' := fresh H in case H as [H']; clear H end. -Ltac unbool_comparisons := - repeat match goal with - | H:context [Z.geb _ _] |- _ => rewrite Z.geb_leb in H - | H:context [Z.gtb _ _] |- _ => rewrite Z.gtb_ltb in H - | H:context [Z.leb _ _ = true] |- _ => rewrite Z.leb_le in H - | H:context [Z.ltb _ _ = true] |- _ => rewrite Z.ltb_lt in H - | H:context [Z.eqb _ _ = true] |- _ => rewrite Z.eqb_eq in H - | H:context [Z.leb _ _ = false] |- _ => rewrite Z.leb_gt in H - | H:context [Z.ltb _ _ = false] |- _ => rewrite Z.ltb_ge in H - | H:context [Z.eqb _ _ = false] |- _ => rewrite Z.eqb_neq in H - | H:context [orb _ _ = true] |- _ => rewrite Bool.orb_true_iff in H - | H:context [orb _ _ = false] |- _ => rewrite Bool.orb_false_iff in H - | H:context [andb _ _ = true] |- _ => rewrite Bool.andb_true_iff in H - | H:context [andb _ _ = false] |- _ => rewrite Bool.andb_false_iff in H - | H:context [negb _ = true] |- _ => rewrite Bool.negb_true_iff in H - | H:context [negb _ = false] |- _ => rewrite Bool.negb_false_iff in H - | H:context [generic_eq _ _ = true] |- _ => apply generic_eq_true in H - | H:context [generic_eq _ _ = false] |- _ => apply generic_eq_false in H - | H:context [generic_neq _ _ = true] |- _ => apply generic_neq_true in H - | H:context [generic_neq _ _ = false] |- _ => apply generic_neq_false in H - end. - -(* Split up dependent pairs to get at proofs of properties *) -Ltac extract_properties := - (* Properties of local definitions *) - repeat match goal with H := (projT1 ?X) |- _ => - let x := fresh "x" in - let Hx := fresh "Hx" in - destruct X as [x Hx] in *; - change (projT1 (existT _ x Hx)) with x in *; unfold H in * end; - (* Properties in the goal *) - repeat match goal with |- context [projT1 ?X] => - let x := fresh "x" in - let Hx := fresh "Hx" in - destruct X as [x Hx] in *; - change (projT1 (existT _ x Hx)) with x in * end; - (* Properties with proofs embedded by build_ex; uses revert/generalize - rather than destruct because it seemed to be more efficient, but - some experimentation would be needed to be sure. - repeat ( - match goal with H:context [@build_ex ?T ?n ?P ?prf] |- _ => - let x := fresh "x" in - let zz := constr:(@build_ex T n P prf) in - revert dependent H(*; generalize zz; intros*) - end; - match goal with |- context [@build_ex ?T ?n ?P ?prf] => - let x := fresh "x" in - let zz := constr:(@build_ex T n P prf) in - generalize zz as x - end; - intros).*) - repeat match goal with _:context [projT1 ?X] |- _ => - let x := fresh "x" in - let Hx := fresh "Hx" in - destruct X as [x Hx] in *; - change (projT1 (existT _ x Hx)) with x in * end. -(* TODO: hyps, too? *) -Ltac reduce_list_lengths := - repeat match goal with |- context [length_list ?X] => - let r := (eval cbn in (length_list X)) in - change (length_list X) with r - end. -(* TODO: can we restrict this to concrete terms? *) -Ltac reduce_pow := - repeat match goal with H:context [Z.pow ?X ?Y] |- _ => - let r := (eval cbn in (Z.pow X Y)) in - change (Z.pow X Y) with r in H - end; - repeat match goal with |- context [Z.pow ?X ?Y] => - let r := (eval cbn in (Z.pow X Y)) in - change (Z.pow X Y) with r - end. -Ltac dump_context := - repeat match goal with - | H:=?X |- _ => idtac H ":=" X; fail - | H:?X |- _ => idtac H ":" X; fail end; - match goal with |- ?X => idtac "Goal:" X end. -Ltac split_cases := - repeat match goal with - |- context [match ?X with _ => _ end] => destruct X - end. -Ltac prepare_for_solver := -(*dump_context;*) - clear_irrelevant_defns; - clear_non_Z_defns; - autounfold with sail in * |- *; (* You can add Hint Unfold ... : sail to let omega see through fns *) - split_cases; - extract_properties; - repeat match goal with w:mword ?n |- _ => apply ArithFact_mword in w end; - unwrap_ArithFacts; - unfold_In; - unbool_comparisons; - reduce_list_lengths; - reduce_pow. - -Lemma trivial_range {x : Z} : ArithFact (x <= x /\ x <= x). -constructor. -auto with zarith. -Qed. - -Lemma ArithFact_self_proof {P} : forall x : {y : Z & ArithFact (P y)}, ArithFact (P (projT1 x)). -intros [x H]. -exact H. -Qed. - -Ltac fill_in_evar_eq := - match goal with |- ArithFact (?x = ?y) => - (is_evar x || is_evar y); - (* compute to allow projections to remove proofs that might not be allowed in the evar *) -(* Disabled because cbn may reduce definitions, even after clearbody - let x := eval cbn in x in - let y := eval cbn in y in*) - idtac "Warning: unknown equality constraint"; constructor; exact (eq_refl _ : x = y) end. - -Ltac solve_arithfact := -(* Attempt a simple proof first to avoid lengthy preparation steps (especially - as the large proof terms can upset subsequent proofs). *) -intros; (* To solve implications for derive_m *) -try (exact trivial_range); -try fill_in_evar_eq; -try match goal with |- context [projT1 ?X] => apply (ArithFact_self_proof X) end; -try (constructor; omega); -prepare_for_solver; -(*dump_context;*) - solve - [ match goal with |- ArithFact (?x _) => is_evar x; idtac "Warning: unknown constraint"; constructor; exact (I : (fun _ => True) _) end - | apply ArithFact_mword; assumption - | constructor; omega with Z - (* The datatypes hints give us some list handling, esp In *) - | constructor; eauto 3 with datatypes zarith sail - | constructor; idtac "Unable to solve constraint"; dump_context; fail - ]. -(* Add an indirection so that you can redefine run_solver to fail to get - slow running constraints into proof mode. *) -Ltac run_solver := solve_arithfact. -Hint Extern 0 (ArithFact _) => run_solver : typeclass_instances. - -Hint Unfold length_mword : sail. - -Definition neq_atom (x : Z) (y : Z) : bool := negb (Z.eqb x y). -Hint Unfold neq_atom : sail. - -Lemma ReasonableSize_witness (a : Z) (w : mword a) : ReasonableSize a. -constructor. -destruct a. -auto with zarith. -auto using Z.le_ge, Zle_0_pos. -destruct w. -Qed. - -Hint Extern 0 (ReasonableSize ?A) => (unwrap_ArithFacts; solve [apply ReasonableSize_witness; assumption | constructor; omega]) : typeclass_instances. - -Definition to_range (x : Z) : {y : Z & ArithFact (x <= y <= x)} := build_ex x. - - - -Instance mword_Bitvector {a : Z} `{ArithFact (a >= 0)} : (Bitvector (mword a)) := { - bits_of v := List.map bitU_of_bool (bitlistFromWord (get_word v)); - of_bits v := option_map (fun bl => to_word isPositive (fit_bbv_word (wordFromBitlist bl))) (just_list (List.map bool_of_bitU v)); - of_bools v := to_word isPositive (fit_bbv_word (wordFromBitlist v)); - of_int len z := mword_of_int z; (* cheat a little *) - length v := a; - unsigned v := Some (Z.of_N (wordToN (get_word v))); - signed v := Some (wordToZ (get_word v)); - arith_op_bv op sign l r := mword_of_int (op (int_of_mword sign l) (int_of_mword sign r)) -}. - -Section Bitvector_defs. -Context {a b} `{Bitvector a} `{Bitvector b}. - -Definition opt_def {a} (def:a) (v:option a) := -match v with -| Some x => x -| None => def -end. - -(* The Lem version is partial, but lets go with BU here to avoid constraints for now *) -Definition access_bv_inc (v : a) n := opt_def BU (access_list_opt_inc (bits_of v) n). -Definition access_bv_dec (v : a) n := opt_def BU (access_list_opt_dec (bits_of v) n). - -Definition update_bv_inc (v : a) n b := update_list true (bits_of v) n b. -Definition update_bv_dec (v : a) n b := update_list false (bits_of v) n b. - -Definition subrange_bv_inc (v : a) i j := subrange_list true (bits_of v) i j. -Definition subrange_bv_dec (v : a) i j := subrange_list true (bits_of v) i j. - -Definition update_subrange_bv_inc (v : a) i j (v' : b) := update_subrange_list true (bits_of v) i j (bits_of v'). -Definition update_subrange_bv_dec (v : a) i j (v' : b) := update_subrange_list false (bits_of v) i j (bits_of v'). - -(*val extz_bv : forall a b. Bitvector a, Bitvector b => Z -> a -> b*) -Definition extz_bv n (v : a) : option b := of_bits (extz_bits n (bits_of v)). - -(*val exts_bv : forall a b. Bitvector a, Bitvector b => Z -> a -> b*) -Definition exts_bv n (v : a) : option b := of_bits (exts_bits n (bits_of v)). - -(*val string_of_bv : forall a. Bitvector a => a -> string *) -Definition string_of_bv v := show_bitlist (bits_of v). - -End Bitvector_defs. - -(*** Bytes and addresses *) - -Definition memory_byte := list bitU. - -(*val byte_chunks : forall a. list a -> option (list (list a))*) -Fixpoint byte_chunks {a} (bs : list a) := match bs with - | [] => Some [] - | a::b::c::d::e::f::g::h::rest => - match byte_chunks rest with - | None => None - | Some rest => Some ([a;b;c;d;e;f;g;h] :: rest) - end - | _ => None -end. -(*declare {isabelle} termination_argument byte_chunks = automatic*) - -Section BytesBits. -Context {a} `{Bitvector a}. - -(*val bytes_of_bits : forall a. Bitvector a => a -> option (list memory_byte)*) -Definition bytes_of_bits (bs : a) := byte_chunks (bits_of bs). - -(*val bits_of_bytes : forall a. Bitvector a => list memory_byte -> a*) -Definition bits_of_bytes (bs : list memory_byte) : list bitU := List.concat (List.map bits_of bs). - -Definition mem_bytes_of_bits (bs : a) := option_map (@rev (list bitU)) (bytes_of_bits bs). -Definition bits_of_mem_bytes (bs : list memory_byte) := bits_of_bytes (List.rev bs). - -End BytesBits. - -(*val bitv_of_byte_lifteds : list Sail_impl_base.byte_lifted -> list bitU -Definition bitv_of_byte_lifteds v := - foldl (fun x (Byte_lifted y) => x ++ (List.map bitU_of_bit_lifted y)) [] v - -val bitv_of_bytes : list Sail_impl_base.byte -> list bitU -Definition bitv_of_bytes v := - foldl (fun x (Byte y) => x ++ (List.map bitU_of_bit y)) [] v - -val byte_lifteds_of_bitv : list bitU -> list byte_lifted -Definition byte_lifteds_of_bitv bits := - let bits := List.map bit_lifted_of_bitU bits in - byte_lifteds_of_bit_lifteds bits - -val bytes_of_bitv : list bitU -> list byte -Definition bytes_of_bitv bits := - let bits := List.map bit_of_bitU bits in - bytes_of_bits bits - -val bit_lifteds_of_bitUs : list bitU -> list bit_lifted -Definition bit_lifteds_of_bitUs bits := List.map bit_lifted_of_bitU bits - -val bit_lifteds_of_bitv : list bitU -> list bit_lifted -Definition bit_lifteds_of_bitv v := bit_lifteds_of_bitUs v - - -val address_lifted_of_bitv : list bitU -> address_lifted -Definition address_lifted_of_bitv v := - let byte_lifteds := byte_lifteds_of_bitv v in - let maybe_address_integer := - match (maybe_all (List.map byte_of_byte_lifted byte_lifteds)) with - | Some bs => Some (integer_of_byte_list bs) - | _ => None - end in - Address_lifted byte_lifteds maybe_address_integer - -val bitv_of_address_lifted : address_lifted -> list bitU -Definition bitv_of_address_lifted (Address_lifted bs _) := bitv_of_byte_lifteds bs - -val address_of_bitv : list bitU -> address -Definition address_of_bitv v := - let bytes := bytes_of_bitv v in - address_of_byte_list bytes*) - -Fixpoint reverse_endianness_list (bits : list bitU) := - match bits with - | _ :: _ :: _ :: _ :: _ :: _ :: _ :: _ :: t => - reverse_endianness_list t ++ firstn 8 bits - | _ => bits - end. - -(*** Registers *) - -Definition register_field := string. -Definition register_field_index : Type := string * (Z * Z). (* name, start and end *) - -Inductive register := - | Register : string * (* name *) - Z * (* length *) - Z * (* start index *) - bool * (* is increasing *) - list register_field_index - -> register - | UndefinedRegister : Z -> register (* length *) - | RegisterPair : register * register -> register. - -Record register_ref regstate regval a := - { name : string; - (*is_inc : bool;*) - read_from : regstate -> a; - write_to : a -> regstate -> regstate; - of_regval : regval -> option a; - regval_of : a -> regval }. -Notation "{[ r 'with' 'name' := e ]}" := ({| name := e; read_from := read_from r; write_to := write_to r; of_regval := of_regval r; regval_of := regval_of r |}). -Notation "{[ r 'with' 'read_from' := e ]}" := ({| read_from := e; name := name r; write_to := write_to r; of_regval := of_regval r; regval_of := regval_of r |}). -Notation "{[ r 'with' 'write_to' := e ]}" := ({| write_to := e; name := name r; read_from := read_from r; of_regval := of_regval r; regval_of := regval_of r |}). -Notation "{[ r 'with' 'of_regval' := e ]}" := ({| of_regval := e; name := name r; read_from := read_from r; write_to := write_to r; regval_of := regval_of r |}). -Notation "{[ r 'with' 'regval_of' := e ]}" := ({| regval_of := e; name := name r; read_from := read_from r; write_to := write_to r; of_regval := of_regval r |}). -Arguments name [_ _ _]. -Arguments read_from [_ _ _]. -Arguments write_to [_ _ _]. -Arguments of_regval [_ _ _]. -Arguments regval_of [_ _ _]. - -(* Register accessors: pair of functions for reading and writing register values *) -Definition register_accessors regstate regval : Type := - ((string -> regstate -> option regval) * - (string -> regval -> regstate -> option regstate)). - -Record field_ref regtype a := - { field_name : string; - field_start : Z; - field_is_inc : bool; - get_field : regtype -> a; - set_field : regtype -> a -> regtype }. -Arguments field_name [_ _]. -Arguments field_start [_ _]. -Arguments field_is_inc [_ _]. -Arguments get_field [_ _]. -Arguments set_field [_ _]. - -(* -(*let name_of_reg := function - | Register name _ _ _ _ => name - | UndefinedRegister _ => failwith "name_of_reg UndefinedRegister" - | RegisterPair _ _ => failwith "name_of_reg RegisterPair" -end - -Definition size_of_reg := function - | Register _ size _ _ _ => size - | UndefinedRegister size => size - | RegisterPair _ _ => failwith "size_of_reg RegisterPair" -end - -Definition start_of_reg := function - | Register _ _ start _ _ => start - | UndefinedRegister _ => failwith "start_of_reg UndefinedRegister" - | RegisterPair _ _ => failwith "start_of_reg RegisterPair" -end - -Definition is_inc_of_reg := function - | Register _ _ _ is_inc _ => is_inc - | UndefinedRegister _ => failwith "is_inc_of_reg UndefinedRegister" - | RegisterPair _ _ => failwith "in_inc_of_reg RegisterPair" -end - -Definition dir_of_reg := function - | Register _ _ _ is_inc _ => dir_of_bool is_inc - | UndefinedRegister _ => failwith "dir_of_reg UndefinedRegister" - | RegisterPair _ _ => failwith "dir_of_reg RegisterPair" -end - -Definition size_of_reg_nat reg := Z.to_nat (size_of_reg reg) -Definition start_of_reg_nat reg := Z.to_nat (start_of_reg reg) - -val register_field_indices_aux : register -> register_field -> option (Z * Z) -Fixpoint register_field_indices_aux register rfield := - match register with - | Register _ _ _ _ rfields => List.lookup rfield rfields - | RegisterPair r1 r2 => - let m_indices := register_field_indices_aux r1 rfield in - if isSome m_indices then m_indices else register_field_indices_aux r2 rfield - | UndefinedRegister _ => None - end - -val register_field_indices : register -> register_field -> Z * Z -Definition register_field_indices register rfield := - match register_field_indices_aux register rfield with - | Some indices => indices - | None => failwith "Invalid register/register-field combination" - end - -Definition register_field_indices_nat reg regfield= - let (i,j) := register_field_indices reg regfield in - (Z.to_nat i,Z.to_nat j)*) - -(*let rec external_reg_value reg_name v := - let (internal_start, external_start, direction) := - match reg_name with - | Reg _ start size dir => - (start, (if dir = D_increasing then start else (start - (size +1))), dir) - | Reg_slice _ reg_start dir (slice_start, _) => - ((if dir = D_increasing then slice_start else (reg_start - slice_start)), - slice_start, dir) - | Reg_field _ reg_start dir _ (slice_start, _) => - ((if dir = D_increasing then slice_start else (reg_start - slice_start)), - slice_start, dir) - | Reg_f_slice _ reg_start dir _ _ (slice_start, _) => - ((if dir = D_increasing then slice_start else (reg_start - slice_start)), - slice_start, dir) - end in - let bits := bit_lifteds_of_bitv v in - <| rv_bits := bits; - rv_dir := direction; - rv_start := external_start; - rv_start_internal := internal_start |> - -val internal_reg_value : register_value -> list bitU -Definition internal_reg_value v := - List.map bitU_of_bit_lifted v.rv_bits - (*(Z.of_nat v.rv_start_internal) - (v.rv_dir = D_increasing)*) - - -Definition external_slice (d:direction) (start:nat) ((i,j):(nat*nat)) := - match d with - (*This is the case the thread/concurrecny model expects, so no change needed*) - | D_increasing => (i,j) - | D_decreasing => let slice_i = start - i in - let slice_j = (i - j) + slice_i in - (slice_i,slice_j) - end *) - -(* TODO -Definition external_reg_whole r := - Reg (r.name) (Z.to_nat r.start) (Z.to_nat r.size) (dir_of_bool r.is_inc) - -Definition external_reg_slice r (i,j) := - let start := Z.to_nat r.start in - let dir := dir_of_bool r.is_inc in - Reg_slice (r.name) start dir (external_slice dir start (i,j)) - -Definition external_reg_field_whole reg rfield := - let (m,n) := register_field_indices_nat reg rfield in - let start := start_of_reg_nat reg in - let dir := dir_of_reg reg in - Reg_field (name_of_reg reg) start dir rfield (external_slice dir start (m,n)) - -Definition external_reg_field_slice reg rfield (i,j) := - let (m,n) := register_field_indices_nat reg rfield in - let start := start_of_reg_nat reg in - let dir := dir_of_reg reg in - Reg_f_slice (name_of_reg reg) start dir rfield - (external_slice dir start (m,n)) - (external_slice dir start (i,j))*) - -(*val external_mem_value : list bitU -> memory_value -Definition external_mem_value v := - byte_lifteds_of_bitv v $> List.reverse - -val internal_mem_value : memory_value -> list bitU -Definition internal_mem_value bytes := - List.reverse bytes $> bitv_of_byte_lifteds*) - - -val foreach : forall a vars. - (list a) -> vars -> (a -> vars -> vars) -> vars*) -Fixpoint foreach {a Vars} (l : list a) (vars : Vars) (body : a -> Vars -> Vars) : Vars := -match l with -| [] => vars -| (x :: xs) => foreach xs (body x vars) body -end. - -(*declare {isabelle} termination_argument foreach = automatic - -val index_list : Z -> Z -> Z -> list Z*) -Fixpoint index_list' from to step n := - if orb (andb (step >? 0) (from <=? to)) (andb (step [] - | S n => from :: index_list' (from + step) to step n - end - else []. - -Definition index_list from to step := - if orb (andb (step >? 0) (from <=? to)) (andb (step Vars -> Vars) : Vars := - if orb (andb (step >? 0) (from <=? to)) (andb (step vars - | S n => let vars := body from vars in foreach_Z' (from + step) to step n vars body - end - else vars. - -Definition foreach_Z {Vars} from to step vars body := - foreach_Z' (Vars := Vars) from to step (S (Z.abs_nat (from - to))) vars body. - -Fixpoint foreach_Z_up' {Vars} from to step off n `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> Vars) {struct n} : Vars := - if sumbool_of_bool (from + off <=? to) then - match n with - | O => vars - | S n => let vars := body (from + off) _ vars in foreach_Z_up' from to step (off + step) n vars body - end - else vars. - -Fixpoint foreach_Z_down' {Vars} from to step off n `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> Vars) {struct n} : Vars := - if sumbool_of_bool (to <=? from + off) then - match n with - | O => vars - | S n => let vars := body (from + off) _ vars in foreach_Z_down' from to step (off - step) n vars body - end - else vars. - -Definition foreach_Z_up {Vars} from to step vars body `{ArithFact (0 < step)} := - foreach_Z_up' (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body. -Definition foreach_Z_down {Vars} from to step vars body `{ArithFact (0 < step)} := - foreach_Z_down' (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body. - -(*val while : forall vars. vars -> (vars -> bool) -> (vars -> vars) -> vars -Fixpoint while vars cond body := - if cond vars then while (body vars) cond body else vars - -val until : forall vars. vars -> (vars -> bool) -> (vars -> vars) -> vars -Fixpoint until vars cond body := - let vars := body vars in - if cond vars then vars else until (body vars) cond body - - -Definition assert' b msg_opt := - let msg := match msg_opt with - | Some msg => msg - | None => "unspecified error" - end in - if b then () else failwith msg - -(* convert numbers unsafely to naturals *) - -class (ToNatural a) val toNatural : a -> natural end -(* eta-expanded for Isabelle output, otherwise it breaks *) -instance (ToNatural Z) let toNatural := (fun n => naturalFromInteger n) end -instance (ToNatural int) let toNatural := (fun n => naturalFromInt n) end -instance (ToNatural nat) let toNatural := (fun n => naturalFromNat n) end -instance (ToNatural natural) let toNatural := (fun n => n) end - -Definition toNaturalFiveTup (n1,n2,n3,n4,n5) := - (toNatural n1, - toNatural n2, - toNatural n3, - toNatural n4, - toNatural n5) - -(* Let the following types be generated by Sail per spec, using either bitlists - or machine words as bitvector representation *) -(*type regfp := - | RFull of (string) - | RSlice of (string * Z * Z) - | RSliceBit of (string * Z) - | RField of (string * string) - -type niafp := - | NIAFP_successor - | NIAFP_concrete_address of vector bitU - | NIAFP_indirect_address - -(* only for MIPS *) -type diafp := - | DIAFP_none - | DIAFP_concrete of vector bitU - | DIAFP_reg of regfp - -Definition regfp_to_reg (reg_info : string -> option string -> (nat * nat * direction * (nat * nat))) := function - | RFull name => - let (start,length,direction,_) := reg_info name None in - Reg name start length direction - | RSlice (name,i,j) => - let i = Z.to_nat i in - let j = Z.to_nat j in - let (start,length,direction,_) = reg_info name None in - let slice = external_slice direction start (i,j) in - Reg_slice name start direction slice - | RSliceBit (name,i) => - let i = Z.to_nat i in - let (start,length,direction,_) = reg_info name None in - let slice = external_slice direction start (i,i) in - Reg_slice name start direction slice - | RField (name,field_name) => - let (start,length,direction,span) = reg_info name (Some field_name) in - let slice = external_slice direction start span in - Reg_field name start direction field_name slice -end - -Definition niafp_to_nia reginfo = function - | NIAFP_successor => NIA_successor - | NIAFP_concrete_address v => NIA_concrete_address (address_of_bitv v) - | NIAFP_indirect_address => NIA_indirect_address -end - -Definition diafp_to_dia reginfo = function - | DIAFP_none => DIA_none - | DIAFP_concrete v => DIA_concrete_address (address_of_bitv v) - | DIAFP_reg r => DIA_register (regfp_to_reg reginfo r) -end -*) -*) - -(* Arithmetic functions which return proofs that match the expected Sail - types in smt.sail. *) - -Definition div_with_eq n m : {o : Z & ArithFact (o = Z.quot n m)} := build_ex (Z.quot n m). -Definition mod_with_eq n m : {o : Z & ArithFact (o = Z.rem n m)} := build_ex (Z.rem n m). -Definition abs_with_eq n : {o : Z & ArithFact (o = Z.abs n)} := build_ex (Z.abs n). - -(* Similarly, for ranges (currently in MIPS) *) - -Definition eq_range {n m o p} (l : {l & ArithFact (n <= l <= m)}) (r : {r & ArithFact (o <= r <= p)}) : bool := - (projT1 l) =? (projT1 r). -Definition add_range {n m o p} (l : {l & ArithFact (n <= l <= m)}) (r : {r & ArithFact (o <= r <= p)}) - : {x & ArithFact (n+o <= x <= m+p)} := - build_ex ((projT1 l) + (projT1 r)). -Definition sub_range {n m o p} (l : {l & ArithFact (n <= l <= m)}) (r : {r & ArithFact (o <= r <= p)}) - : {x & ArithFact (n-p <= x <= m-o)} := - build_ex ((projT1 l) - (projT1 r)). -Definition negate_range {n m} (l : {l : Z & ArithFact (n <= l <= m)}) - : {x : Z & ArithFact ((- m) <= x <= (- n))} := - build_ex (- (projT1 l)). - -Definition min_atom (a : Z) (b : Z) : {c : Z & ArithFact (c = a \/ c = b /\ c <= a /\ c <= b)} := - build_ex (Z.min a b). -Definition max_atom (a : Z) (b : Z) : {c : Z & ArithFact (c = a \/ c = b /\ c >= a /\ c >= b)} := - build_ex (Z.max a b). - - -(*** Generic vectors *) - -Definition vec (T:Type) (n:Z) := { l : list T & length_list l = n }. -Definition vec_length {T n} (v : vec T n) := n. -Definition vec_access_dec {T n} (v : vec T n) m `{ArithFact (0 <= m < n)} : T := - access_list_dec (projT1 v) m. -Definition vec_access_inc {T n} (v : vec T n) m `{ArithFact (0 <= m < n)} : T := - access_list_inc (projT1 v) m. - -Program Definition vec_init {T} (t : T) (n : Z) `{ArithFact (n >= 0)} : vec T n := - existT _ (repeat [t] n) _. -Next Obligation. -rewrite repeat_length; auto using fact. -unfold length_list. -simpl. -auto with zarith. -Qed. - -Lemma skipn_length {A n} {l: list A} : (n <= List.length l -> List.length (skipn n l) = List.length l - n)%nat. -revert l. -induction n. -* simpl. auto with arith. -* intros l H. - destruct l. - + inversion H. - + simpl in H. - simpl. - rewrite IHn; auto with arith. -Qed. -Lemma update_list_inc_length {T} {l:list T} {m x} : 0 <= m < length_list l -> length_list (update_list_inc l m x) = length_list l. -unfold update_list_inc, list_update, length_list. -intro H. -f_equal. -assert ((0 <= Z.to_nat m < Datatypes.length l)%nat). -{ destruct H as [H1 H2]. - split. - + change 0%nat with (Z.to_nat 0). - apply Z2Nat.inj_le; auto with zarith. - + rewrite <- Nat2Z.id. - apply Z2Nat.inj_lt; auto with zarith. -} -rewrite app_length. -rewrite firstn_length_le; only 2:omega. -cbn -[skipn]. -rewrite skipn_length; -omega. -Qed. - -Program Definition vec_update_dec {T n} (v : vec T n) m t `{ArithFact (0 <= m < n)} : vec T n := existT _ (update_list_dec (projT1 v) m t) _. -Next Obligation. -unfold update_list_dec. -rewrite update_list_inc_length. -+ destruct v. apply e. -+ destruct H. - destruct v. simpl (projT1 _). rewrite e. - omega. -Qed. - -Program Definition vec_update_inc {T n} (v : vec T n) m t `{ArithFact (0 <= m < n)} : vec T n := existT _ (update_list_inc (projT1 v) m t) _. -Next Obligation. -rewrite update_list_inc_length. -+ destruct v. apply e. -+ destruct H. - destruct v. simpl (projT1 _). rewrite e. - omega. -Qed. - -Program Definition vec_map {S T} (f : S -> T) {n} (v : vec S n) : vec T n := existT _ (List.map f (projT1 v)) _. -Next Obligation. -destruct v as [l H]. -cbn. -unfold length_list. -rewrite map_length. -apply H. -Qed. - -Program Definition just_vec {A n} (v : vec (option A) n) : option (vec A n) := - match just_list (projT1 v) with - | None => None - | Some v' => Some (existT _ v' _) - end. -Next Obligation. -rewrite <- (just_list_length_Z _ _ Heq_anonymous). -destruct v. -assumption. -Qed. - -Definition list_of_vec {A n} (v : vec A n) : list A := projT1 v. - -Program Definition vec_of_list {A} n (l : list A) : option (vec A n) := - if sumbool_of_bool (n =? length_list l) then Some (existT _ l _) else None. -Next Obligation. -symmetry. -apply Z.eqb_eq. -assumption. -Qed. - -Definition vec_of_list_len {A} (l : list A) : vec A (length_list l) := existT _ l (eq_refl _). - -Definition map_bind {A B} (f : A -> option B) (a : option A) : option B := -match a with -| Some a' => f a' -| None => None -end. - -Definition sub_nat (x : {x : Z & ArithFact (x >= 0)}) (y : {y : Z & ArithFact (y >= 0)}) : - {z : Z & ArithFact (z >= 0)} := - let z := projT1 x - projT1 y in - if sumbool_of_bool (z >=? 0) then build_ex z else build_ex 0. diff --git a/snapshots/coq-riscv/sail/lib/coq/_CoqProject b/snapshots/coq-riscv/sail/lib/coq/_CoqProject deleted file mode 100644 index 9f5d26b8..00000000 --- a/snapshots/coq-riscv/sail/lib/coq/_CoqProject +++ /dev/null @@ -1,2 +0,0 @@ --R . Sail --R ../../../bbv/theories bbv diff --git a/snapshots/coq-riscv/sail/riscv/coq.patch b/snapshots/coq-riscv/sail/riscv/coq.patch deleted file mode 100644 index 9ee0fc71..00000000 --- a/snapshots/coq-riscv/sail/riscv/coq.patch +++ /dev/null @@ -1,328 +0,0 @@ ---- riscv.v.plain 2018-09-06 11:57:47.900156894 +0100 -+++ riscv.v 2018-09-06 11:57:50.244172679 +0100 -@@ -8383,14 +8383,16 @@ - returnm ((EXTZ 56 (shiftl (_get_Satp64_PPN satp64) PAGESIZE_BITS)) - : mword 56). - --Fixpoint walk39 (vaddr : mword 39) (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) (ptb : mword 56) '(existT _ level _ : {n : Z & ArithFact (n >= -- 0)}) (global : bool) -+Hint Unfold PAGESIZE_BITS : sail. -+Hint Unfold SV39_LEVEL_BITS : sail. -+ -+Fixpoint walk39 (vaddr : mword 39) (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) (ptb : mword 56) (level : nat) (global : bool) - : M (PTW_Result) := - let va := Mk_SV39_Vaddr vaddr in - let pt_ofs : paddr39 := - shiftl - (EXTZ 56 -- (subrange_vec_dec (shiftr (_get_SV39_Vaddr_VPNi va) (Z.mul level SV39_LEVEL_BITS)) -+ (subrange_vec_dec (shiftr (_get_SV39_Vaddr_VPNi va) (Z.mul (Z.of_nat level) SV39_LEVEL_BITS)) - (projT1 (sub_range (build_ex SV39_LEVEL_BITS) (build_ex 1))) 0)) PTE39_LOG_SIZE in - let pte_addr := add_vec ptb pt_ofs in - phys_mem_read Data (EXTZ 64 pte_addr) 8 false false false >>= fun w__0 : MemoryOpResult (mword (8 * 8)) => -@@ -8403,27 +8405,27 @@ - let is_global := orb global (eq_vec (_get_PTE_Bits_G pattr) ((bool_to_bits true) : mword 1)) in - (if ((isInvalidPTE pbits)) then returnm ((PTW_Failure (PTW_Invalid_PTE)) : PTW_Result ) - else if ((isPTEPtr pbits)) then -- (if sumbool_of_bool ((Z.eqb level 0)) then -+ (match level with O => - returnm ((PTW_Failure - (PTW_Invalid_PTE)) - : PTW_Result ) -- else -+ | S level' => - (walk39 vaddr ac priv mxr do_sum - (EXTZ 56 (shiftl (_get_SV39_PTE_PPNi pte) PAGESIZE_BITS)) -- (build_ex (projT1 (sub_range (build_ex level) (build_ex 1)))) is_global) -- : M (PTW_Result)) -+ level' is_global) -+ : M (PTW_Result) end) - : M (PTW_Result) - else - checkPTEPermission ac priv mxr do_sum pattr >>= fun w__3 : bool => - returnm ((if ((negb w__3)) then PTW_Failure (PTW_No_Permission) -- else if sumbool_of_bool ((Z.gtb level 0)) then -+ else if sumbool_of_bool (Nat.ltb O level) then - let mask := - sub_vec_int - (shiftl - (xor_vec (_get_SV39_PTE_PPNi pte) - (xor_vec (_get_SV39_PTE_PPNi pte) - (EXTZ 44 (vec_of_bits [B1] : mword 1)))) -- (Z.mul level SV39_LEVEL_BITS)) 1 in -+ (Z.mul (Z.of_nat level) SV39_LEVEL_BITS)) 1 in - if ((neq_vec (and_vec (_get_SV39_PTE_PPNi pte) mask) - (EXTZ 44 (vec_of_bits [B0] : mword 1)))) then - PTW_Failure -@@ -8433,12 +8435,12 @@ - or_vec (_get_SV39_PTE_PPNi pte) - (and_vec (EXTZ 44 (_get_SV39_Vaddr_VPNi va)) mask) in - PTW_Success -- (concat_vec ppn (_get_SV39_Vaddr_PgOfs va), pte, pte_addr, build_ex level, -+ (concat_vec ppn (_get_SV39_Vaddr_PgOfs va), pte, pte_addr, build_ex (Z.of_nat level), - is_global) - else - PTW_Success - (concat_vec (_get_SV39_PTE_PPNi pte) (_get_SV39_Vaddr_PgOfs va), pte, -- pte_addr, build_ex level, is_global)) -+ pte_addr, build_ex (Z.of_nat level), is_global)) - : PTW_Result)) - : M (PTW_Result) - end) -@@ -8564,7 +8566,7 @@ - : M (TR39_Result) - | None => - curPTB39 tt >>= fun w__6 : mword 56 => -- walk39 vAddr ac priv mxr do_sum w__6 (build_ex level) false >>= fun w__7 : PTW_Result => -+ walk39 vAddr ac priv mxr do_sum w__6 (Z.to_nat level) false >>= fun w__7 : PTW_Result => - (match w__7 with - | PTW_Failure (f) => returnm ((TR39_Failure (f)) : TR39_Result ) - | PTW_Success (pAddr,pte,pteAddr,(existT _ level _),global) => -@@ -12339,138 +12341,144 @@ - returnm (true - : bool). - --Fixpoint execute (merge_var : ast) --: M (bool) := -- match merge_var with -+Definition expand_ast (i : ast) : ast := -+match i with - | C_ADDI4SPN (rdc,nzimm) => - let imm : bits 12 := - concat_vec (vec_of_bits [B0;B0] : mword 2) - (concat_vec nzimm (vec_of_bits [B0;B0] : mword 2)) in - let rd := creg2reg_bits rdc in -- (execute (ITYPE (imm, sp, rd, RISCV_ADDI))) -- : M (bool) -+ ( (ITYPE (imm, sp, rd, RISCV_ADDI))) -+ - | C_LW (uimm,rsc,rdc) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in - let rd := creg2reg_bits rdc in - let rs := creg2reg_bits rsc in -- (execute (LOAD (imm, rs, rd, false, WORD, false, false))) -- : M (bool) -+ ( (LOAD (imm, rs, rd, false, WORD, false, false))) -+ - | C_LD (uimm,rsc,rdc) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in - let rd := creg2reg_bits rdc in - let rs := creg2reg_bits rsc in -- (execute (LOAD (imm, rs, rd, false, DOUBLE, false, false))) -- : M (bool) -+ ( (LOAD (imm, rs, rd, false, DOUBLE, false, false))) -+ - | C_SW (uimm,rsc1,rsc2) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in - let rs1 := creg2reg_bits rsc1 in - let rs2 := creg2reg_bits rsc2 in -- (execute (STORE (imm, rs2, rs1, WORD, false, false))) -- : M (bool) -+ ( (STORE (imm, rs2, rs1, WORD, false, false))) -+ - | C_SD (uimm,rsc1,rsc2) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in - let rs1 := creg2reg_bits rsc1 in - let rs2 := creg2reg_bits rsc2 in -- (execute (STORE (imm, rs2, rs1, DOUBLE, false, false))) -- : M (bool) -+ ( (STORE (imm, rs2, rs1, DOUBLE, false, false))) -+ - | C_ADDI (nzi,rsd) => - let imm : bits 12 := EXTS 12 nzi in -- (execute (ITYPE (imm, rsd, rsd, RISCV_ADDI))) -- : M (bool) -+ ( (ITYPE (imm, rsd, rsd, RISCV_ADDI))) -+ - | C_JAL (imm) => -- (execute (RISCV_JAL (EXTS 21 (concat_vec imm (vec_of_bits [B0] : mword 1)), ra))) : M (bool) -+ ( (RISCV_JAL (EXTS 21 (concat_vec imm (vec_of_bits [B0] : mword 1)), ra))) - | C_LI (imm,rd) => - let imm : bits 12 := EXTS 12 imm in -- (execute (ITYPE (imm, zreg, rd, RISCV_ADDI))) -- : M (bool) -+ ( (ITYPE (imm, zreg, rd, RISCV_ADDI))) -+ - | C_ADDI16SP (imm) => - let imm : bits 12 := EXTS 12 (concat_vec imm (vec_of_bits [B0;B0;B0;B0] : mword 4)) in -- (execute (ITYPE (imm, sp, sp, RISCV_ADDI))) -- : M (bool) -+ ( (ITYPE (imm, sp, sp, RISCV_ADDI))) -+ - | C_LUI (imm,rd) => - let res : bits 20 := EXTS 20 imm in -- (execute (UTYPE (res, rd, RISCV_LUI))) -- : M (bool) -+ ( (UTYPE (res, rd, RISCV_LUI))) -+ - | C_SRLI (shamt,rsd) => - let rsd := creg2reg_bits rsd in -- (execute (SHIFTIOP (shamt, rsd, rsd, RISCV_SRLI))) -- : M (bool) -+ ( (SHIFTIOP (shamt, rsd, rsd, RISCV_SRLI))) -+ - | C_SRAI (shamt,rsd) => - let rsd := creg2reg_bits rsd in -- (execute (SHIFTIOP (shamt, rsd, rsd, RISCV_SRAI))) -- : M (bool) -+ ( (SHIFTIOP (shamt, rsd, rsd, RISCV_SRAI))) -+ - | C_ANDI (imm,rsd) => - let rsd := creg2reg_bits rsd in -- (execute (ITYPE (EXTS 12 imm, rsd, rsd, RISCV_ANDI))) -- : M (bool) -+ ( (ITYPE (EXTS 12 imm, rsd, rsd, RISCV_ANDI))) -+ - | C_SUB (rsd,rs2) => - let rsd := creg2reg_bits rsd in - let rs2 := creg2reg_bits rs2 in -- (execute (RTYPE (rs2, rsd, rsd, RISCV_SUB))) -- : M (bool) -+ ( (RTYPE (rs2, rsd, rsd, RISCV_SUB))) -+ - | C_XOR (rsd,rs2) => - let rsd := creg2reg_bits rsd in - let rs2 := creg2reg_bits rs2 in -- (execute (RTYPE (rs2, rsd, rsd, RISCV_XOR))) -- : M (bool) -+ ( (RTYPE (rs2, rsd, rsd, RISCV_XOR))) -+ - | C_OR (rsd,rs2) => - let rsd := creg2reg_bits rsd in - let rs2 := creg2reg_bits rs2 in -- (execute (RTYPE (rs2, rsd, rsd, RISCV_OR))) -- : M (bool) -+ ( (RTYPE (rs2, rsd, rsd, RISCV_OR))) -+ - | C_AND (rsd,rs2) => - let rsd := creg2reg_bits rsd in - let rs2 := creg2reg_bits rs2 in -- (execute (RTYPE (rs2, rsd, rsd, RISCV_AND))) -- : M (bool) -+ ( (RTYPE (rs2, rsd, rsd, RISCV_AND))) -+ - | C_SUBW (rsd,rs2) => - let rsd := creg2reg_bits rsd in - let rs2 := creg2reg_bits rs2 in -- (execute (RTYPEW (rs2, rsd, rsd, RISCV_SUBW))) -- : M (bool) -+ ( (RTYPEW (rs2, rsd, rsd, RISCV_SUBW))) -+ - | C_ADDW (rsd,rs2) => - let rsd := creg2reg_bits rsd in - let rs2 := creg2reg_bits rs2 in -- (execute (RTYPEW (rs2, rsd, rsd, RISCV_ADDW))) -- : M (bool) -+ ( (RTYPEW (rs2, rsd, rsd, RISCV_ADDW))) -+ - | C_J (imm) => -- (execute (RISCV_JAL (EXTS 21 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg))) -- : M (bool) -+ ( (RISCV_JAL (EXTS 21 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg))) -+ - | C_BEQZ (imm,rs) => -- (execute -+ ( - (BTYPE - (EXTS 13 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg, creg2reg_bits rs, - RISCV_BEQ))) -- : M (bool) -+ - | C_BNEZ (imm,rs) => -- (execute -+ ( - (BTYPE - (EXTS 13 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg, creg2reg_bits rs, - RISCV_BNE))) -- : M (bool) -- | C_SLLI (shamt,rsd) => (execute (SHIFTIOP (shamt, rsd, rsd, RISCV_SLLI))) : M (bool) -+ -+ | C_SLLI (shamt,rsd) => ( (SHIFTIOP (shamt, rsd, rsd, RISCV_SLLI))) - | C_LWSP (uimm,rd) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in -- (execute (LOAD (imm, sp, rd, false, WORD, false, false))) -- : M (bool) -+ ( (LOAD (imm, sp, rd, false, WORD, false, false))) -+ - | C_LDSP (uimm,rd) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in -- (execute (LOAD (imm, sp, rd, false, DOUBLE, false, false))) -- : M (bool) -+ ( (LOAD (imm, sp, rd, false, DOUBLE, false, false))) -+ - | C_SWSP (uimm,rs2) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in -- (execute (STORE (imm, rs2, sp, WORD, false, false))) -- : M (bool) -+ ( (STORE (imm, rs2, sp, WORD, false, false))) -+ - | C_SDSP (uimm,rs2) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in -- (execute (STORE (imm, rs2, sp, DOUBLE, false, false))) -- : M (bool) -+ ( (STORE (imm, rs2, sp, DOUBLE, false, false))) -+ - | C_JR (rs1) => -- (execute (RISCV_JALR (EXTZ 12 (vec_of_bits [B0] : mword 1), rs1, zreg))) : M (bool) -+ ( (RISCV_JALR (EXTZ 12 (vec_of_bits [B0] : mword 1), rs1, zreg))) - | C_JALR (rs1) => -- (execute (RISCV_JALR (EXTZ 12 (vec_of_bits [B0] : mword 1), rs1, ra))) : M (bool) -- | C_MV (rd,rs2) => (execute (RTYPE (rs2, zreg, rd, RISCV_ADD))) : M (bool) -- | C_ADD (rsd,rs2) => (execute (RTYPE (rs2, rsd, rsd, RISCV_ADD))) : M (bool) -+ ( (RISCV_JALR (EXTZ 12 (vec_of_bits [B0] : mword 1), rs1, ra))) -+ | C_MV (rd,rs2) => ( (RTYPE (rs2, zreg, rd, RISCV_ADD))) -+ | C_ADD (rsd,rs2) => ( (RTYPE (rs2, rsd, rsd, RISCV_ADD))) -+| i => i -+end. -+ -+Fixpoint execute (merge_var : ast) -+: M (bool) := -+let merge_var := expand_ast merge_var in -+ match merge_var with - | UTYPE (imm,rd,op) => (execute_UTYPE imm rd op) : M (bool) - | RISCV_JAL (imm,rd) => (execute_RISCV_JAL imm rd) : M (bool) - | RISCV_JALR (imm,rs1,rd) => (execute_RISCV_JALR imm rs1 rd) : M (bool) -@@ -12510,6 +12518,7 @@ - | THREAD_START (arg0) => returnm ((execute_THREAD_START arg0) : bool) - | ILLEGAL (s) => (execute_ILLEGAL s) : M (bool) - | C_ILLEGAL (arg0) => (execute_C_ILLEGAL arg0) : M (bool) -+| _ => Fail "Unexpanded instruction" - end. - - Definition assembly_forwards (arg_ : ast) -@@ -12772,7 +12781,7 @@ - | _ => exit tt : M (string) - end) - : M (string). -- -+(* - Definition assembly_backwards (arg_ : string) - : M (ast) := - let _stringappend_756_ := arg_ in -@@ -27038,7 +27047,7 @@ - : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= 0)}))). -- -+*) - Definition encdec_forwards (arg_ : ast) - : M (mword 32) := - (match arg_ with -@@ -29126,7 +29135,7 @@ - : M ((bool * bool)) - end) - : M ((bool * bool)). -- -+(* - Definition loop '(tt : unit) - : M (unit) := - let insns_per_tick := plat_insns_per_tick tt in -@@ -29173,7 +29182,7 @@ - returnm (i, step_no))) >>= fun '(i, step_no) => - returnm (tt - : unit). -- -+*) - Definition read_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 11)} - : read_kind := - let p0_ := arg_ in diff --git a/snapshots/coq-riscv/sail/riscv/riscv.v b/snapshots/coq-riscv/sail/riscv/riscv.v deleted file mode 100644 index 21350812..00000000 --- a/snapshots/coq-riscv/sail/riscv/riscv.v +++ /dev/null @@ -1,30457 +0,0 @@ -(*Generated by Sail from riscv.*) -Require Import Sail2_instr_kinds. -Require Import Sail2_values. -Require Import Sail2_string. -Require Import Sail2_operators_mwords. -Require Import Sail2_prompt_monad. -Require Import Sail2_prompt. -Require Import Sail2_state. -Require Import riscv_types. -Require Import riscv_extras. -Import ListNotations. -Open Scope string. -Open Scope bool. -Section Content. - -Definition eq_unit (g__22 : unit) (g__23 : unit) : bool := true. - - - -Definition neq_range {n : Z} {m : Z} {o : Z} {p : Z} '(existT _ x _ : {rangevar : Z & ArithFact (n <= - rangevar /\ - rangevar <= m)}) '(existT _ y _ : {rangevar : Z & ArithFact (o <= rangevar /\ rangevar <= p)}) -: bool := - negb (eq_range (build_ex x) (build_ex y)). - -Definition neq_int (x : Z) (y : Z) : bool := negb (Z.eqb x y). - -Definition neq_bool (x : bool) (y : bool) : bool := negb (Bool.eqb x y). - -Axiom eq_real : forall (_ : real) (_ : real) , bool. - -Axiom lteq_real : forall (_ : real) (_ : real) , bool. - -Axiom lt_real : forall (_ : real) (_ : real) , bool. - -Axiom gteq_real : forall (_ : real) (_ : real) , bool. - -Axiom gt_real : forall (_ : real) (_ : real) , bool. - -Definition spc_forwards '(tt : unit) : string := " ". - -Definition spc_backwards (s : string) : unit := tt. - -Definition opt_spc_forwards '(tt : unit) : string := "". - -Definition opt_spc_backwards (s : string) : unit := tt. - -Definition def_spc_forwards '(tt : unit) : string := " ". - -Definition def_spc_backwards (s : string) : unit := tt. - -Axiom vcons : forall {n : Z} {a : Type} (_ : a) (_ : vec a n) , vec a (n + 1). - -Axiom vector_concat : forall {n : Z} {m : Z} {a : Type} (_ : vec a n) (_ : vec a m) , vec a (n + m). - -Definition neq_vec {n : Z} (x : mword n) (y : mword n) : bool := negb (eq_vec x y). - - - -Axiom __raw_SetSlice_int : forall (w : Z) (_ : Z) (_ : Z) (_ : bits w) , Z. - -Definition __GetSlice_int (n : Z) (m : Z) (o : Z) `{ArithFact (n >= 0)} -: mword n := - get_slice_int n m o. - -Axiom __raw_SetSlice_bits : forall (n : Z) (w : Z) (_ : bits n) (_ : Z) (_ : bits w) , bits n. - -Axiom __raw_GetSlice_bits : forall - -(n : Z) (w : Z) (_ : bits n) (_ : Z) -`{ArithFact (w >= 0)}, -bits w. - -Axiom __SignExtendSlice : forall {m : Z} (_ : bits m) (_ : Z) (_ : Z) , bits m. - -Axiom __ZeroExtendSlice : forall {m : Z} (_ : bits m) (_ : Z) (_ : Z) , bits m. - -Definition cast_unit_vec (b : bitU) -: M (mword 1) := - (match b with - | B0 => returnm ((vec_of_bits [B0] : mword 1) : mword 1) - | B1 => returnm ((vec_of_bits [B1] : mword 1) : mword 1) - | _ => exit tt : M (mword 1) - end) - : M (mword 1). - -Axiom DecStr : forall (_ : Z) , string. - -Axiom HexStr : forall (_ : Z) , string. - -Axiom real_power : forall (_ : real) (_ : Z) , real. - -Axiom add_real : forall (_ : real) (_ : real) , real. - -Axiom sub_real : forall (_ : real) (_ : real) , real. - -Axiom negate_real : forall (_ : real) , real. - -Axiom mult_real : forall (_ : real) (_ : real) , real. - -Axiom Sqrt : forall (_ : real) , real. - -Axiom RoundDown : forall (_ : real) , Z. - -Axiom RoundUp : forall (_ : real) , Z. - -Axiom abs_real : forall (_ : real) , real. - -Axiom quotient_nat : forall - -(_ : {n : Z & ArithFact (n >= 0)}) (_ : {n : Z & ArithFact (n >= 0)}) -, -{n : Z & ArithFact (n >= 0)}. - -Axiom quotient_real : forall (_ : real) (_ : real) , real. - -Axiom quotient : forall (_ : Z) (_ : Z) , Z. - -Axiom quot_round_zero : forall (_ : Z) (_ : Z) , Z. - -Axiom rem_round_zero : forall (_ : Z) (_ : Z) , Z. - -Axiom modulus : forall (_ : Z) (_ : Z) , Z. - -Axiom Real : forall (_ : Z) , real. - -Axiom min_nat : forall - -(_ : {n : Z & ArithFact (n >= 0)}) (_ : {n : Z & ArithFact (n >= 0)}) -, -{n : Z & ArithFact (n >= 0)}. - -Axiom max_nat : forall - -(_ : {n : Z & ArithFact (n >= 0)}) (_ : {n : Z & ArithFact (n >= 0)}) -, -{n : Z & ArithFact (n >= 0)}. - -Definition __RISCV_write (addr : mword 64) (width : Z) (data : mword (8 * width)) -: M (bool) := - (write_ram 64 width - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) addr data) - : M (bool). - -Axiom __TraceMemoryWrite : forall {m : Z} (n : Z) (_ : bits m) (_ : bits (8 * n)) , unit. - -Definition __RISCV_read (addr : mword 64) (width : Z) (aq : bool) (rl : bool) (res : bool) `{ArithFact (width >= - 0)} -: M (option (mword (8 * width))) := - (match (aq, rl, res) with - | (false, false, false) => - read_ram 64 width - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) addr >>= fun w__0 : mword (8 * width) => - returnm ((Some - (w__0)) - : option (mword (8 * width))) - | (true, false, false) => - read_ram 64 width - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) addr >>= fun w__1 : mword (8 * width) => - returnm ((Some - (w__1)) - : option (mword (8 * width))) - | (true, true, false) => - read_ram 64 width - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) addr >>= fun w__2 : mword (8 * width) => - returnm ((Some - (w__2)) - : option (mword (8 * width))) - | (false, false, true) => - read_ram 64 width - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) addr >>= fun w__3 : mword (8 * width) => - returnm ((Some - (w__3)) - : option (mword (8 * width))) - | (true, false, true) => - read_ram 64 width - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) addr >>= fun w__4 : mword (8 * width) => - returnm ((Some - (w__4)) - : option (mword (8 * width))) - | (true, true, true) => - read_ram 64 width - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) addr >>= fun w__5 : mword (8 * width) => - returnm ((Some - (w__5)) - : option (mword (8 * width))) - | (false, true, false) => returnm (None : option (mword (8 * width))) - | (false, true, true) => returnm (None : option (mword (8 * width))) - end) - : M (option (mword (8 * width))). - -Axiom __TraceMemoryRead : forall {m : Z} (n : Z) (_ : bits m) (_ : bits (8 * n)) , unit. - -Definition ex_nat '(existT _ n _ : {n : Z & ArithFact (n >= 0)}) -: {syn_n : Z & ArithFact (syn_n >= 0)} := - build_ex(n). - -Definition ex_int (n : Z) : {syn_n : Z & ArithFact (True)} := build_ex(n). - -Definition coerce_int_nat (x : Z) -: M ({n : Z & ArithFact (n >= 0)}) := - assert_exp' (x >=? 0) "" >>= fun _ => returnm (build_ex (x : Z)). - -Definition EXTS {n : Z} (m__tv : Z) (v : mword n) `{ArithFact (m__tv >= n)} -: mword m__tv := - sign_extend v m__tv. - -Definition EXTZ {n : Z} (m__tv : Z) (v : mword n) `{ArithFact (m__tv >= n)} -: mword m__tv := - zero_extend v m__tv. - -Definition zopz0zI_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= (0 + 1))} -: bool := - Z.ltb (projT1 (sint x)) (projT1 (sint y)). - -Definition zopz0zKzJ_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= (0 + 1))} -: bool := - Z.geb (projT1 (sint x)) (projT1 (sint y)). - -Definition zopz0zI_u {n : Z} (x : mword n) (y : mword n) -: bool := - Z.ltb (projT1 (uint x)) (projT1 (uint y)). - -Definition zopz0zKzJ_u {n : Z} (x : mword n) (y : mword n) -: bool := - Z.geb (projT1 (uint x)) (projT1 (uint y)). - -Definition zopz0zIzJ_u {n : Z} (x : mword n) (y : mword n) -: bool := - Z.leb (projT1 (uint x)) (projT1 (uint y)). - -Definition bool_to_bits (x : bool) -: mword 1 := - if (x) then (vec_of_bits [B1] : mword 1) - else (vec_of_bits [B0] : mword 1). - -Definition bit_to_bool (b : bitU) -: M (bool) := - (match b with - | B1 => returnm (true : bool) - | B0 => returnm (false : bool) - | _ => exit tt : M (bool) - end) - : M (bool). - -Definition vector64 (n : Z) : mword 64 := get_slice_int 64 n 0. - -Definition to_bits (l : Z) (n : Z) `{ArithFact (l >= 0)} : mword l := get_slice_int l n 0. - -Axiom vector_update_subrange_inc : forall -{n : Z} -(_ : mword n) (m : Z) (o : Z) (_ : mword (o - (m - 1))) -, -mword n. - -Definition shift_right_arith64 (v : mword 64) (shift : mword 6) -: mword 64 := - let v128 : bits 128 := EXTS 128 v in - subrange_vec_dec (shift_bits_right v128 shift) 63 0. - -Definition shift_right_arith32 (v : mword 32) (shift : mword 5) -: mword 32 := - let v64 : bits 64 := EXTS 64 v in - subrange_vec_dec (shift_bits_right v64 shift) 31 0. - -Definition xlen := 64. -Hint Unfold xlen : sail. -Definition xlen_max_unsigned := projT1 (sub_range (build_ex (projT1 (pow2 xlen))) (build_ex 1)). -Hint Unfold xlen_max_unsigned : sail. -Definition xlen_max_signed := -projT1 (sub_range (build_ex (projT1 (pow2 (projT1 (sub_range (build_ex xlen) (build_ex 1)))))) - (build_ex 1)). -Hint Unfold xlen_max_signed : sail. -Definition xlen_min_signed := -projT1 (sub_range (build_ex 0) - (build_ex (projT1 (pow2 (projT1 (sub_range (build_ex xlen) (build_ex 1))))))). -Hint Unfold xlen_min_signed : sail. -Definition regbits_to_regno (b : mword 5) -: {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)} := - build_ex(let 'r := projT1 (uint b) in - r). - -Definition creg2reg_bits (creg : mword 3) -: mword 5 := - concat_vec (vec_of_bits [B0;B1] : mword 2) creg. - -Definition zreg : regbits := (vec_of_bits [B0;B0;B0;B0;B0] : mword 5). -Hint Unfold zreg : sail. -Definition ra : regbits := (vec_of_bits [B0;B0;B0;B0;B1] : mword 5). -Hint Unfold ra : sail. -Definition sp : regbits := (vec_of_bits [B0;B0;B0;B1;B0] : mword 5). -Hint Unfold sp : sail. -Definition rX (r : Z) `{ArithFact (0 <= r /\ (r + 1) <= 32)} -: M (mword 64) := - let p0_ := r in - (if sumbool_of_bool ((Z.eqb p0_ 0)) then - returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) - : mword 64) - else if sumbool_of_bool ((Z.eqb p0_ 1)) then (read_reg x1_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 2)) then (read_reg x2_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 3)) then (read_reg x3_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 4)) then (read_reg x4_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 5)) then (read_reg x5_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 6)) then (read_reg x6_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 7)) then (read_reg x7_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 8)) then (read_reg x8_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 9)) then (read_reg x9_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 10)) then (read_reg x10_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 11)) then (read_reg x11_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 12)) then (read_reg x12_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 13)) then (read_reg x13_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 14)) then (read_reg x14_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 15)) then (read_reg x15_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 16)) then (read_reg x16_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 17)) then (read_reg x17_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 18)) then (read_reg x18_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 19)) then (read_reg x19_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 20)) then (read_reg x20_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 21)) then (read_reg x21_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 22)) then (read_reg x22_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 23)) then (read_reg x23_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 24)) then (read_reg x24_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 25)) then (read_reg x25_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 26)) then (read_reg x26_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 27)) then (read_reg x27_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 28)) then (read_reg x28_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 29)) then (read_reg x29_ref : M (mword 64)) : M (xlenbits) - else if sumbool_of_bool ((Z.eqb p0_ 30)) then (read_reg x30_ref : M (mword 64)) : M (xlenbits) - else (read_reg x31_ref : M (mword 64)) : M (xlenbits)) - : M (mword 64). - -Definition wX (r : Z) (v : mword 64) `{ArithFact (0 <= r /\ (r + 1) <= 32)} -: M (unit) := - let p0_ := r in - (if sumbool_of_bool ((Z.eqb p0_ 0)) then returnm (tt : unit) - else if sumbool_of_bool ((Z.eqb p0_ 1)) then write_reg x1_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 2)) then write_reg x2_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 3)) then write_reg x3_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 4)) then write_reg x4_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 5)) then write_reg x5_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 6)) then write_reg x6_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 7)) then write_reg x7_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 8)) then write_reg x8_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 9)) then write_reg x9_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 10)) then write_reg x10_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 11)) then write_reg x11_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 12)) then write_reg x12_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 13)) then write_reg x13_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 14)) then write_reg x14_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 15)) then write_reg x15_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 16)) then write_reg x16_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 17)) then write_reg x17_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 18)) then write_reg x18_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 19)) then write_reg x19_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 20)) then write_reg x20_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 21)) then write_reg x21_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 22)) then write_reg x22_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 23)) then write_reg x23_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 24)) then write_reg x24_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 25)) then write_reg x25_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 26)) then write_reg x26_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 27)) then write_reg x27_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 28)) then write_reg x28_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 29)) then write_reg x29_ref v : M (unit) - else if sumbool_of_bool ((Z.eqb p0_ 30)) then write_reg x30_ref v : M (unit) - else write_reg x31_ref v : M (unit)) >> - returnm ((if sumbool_of_bool ((neq_atom r 0)) then - print_endline - (String.append "x" - (String.append (string_of_int r) (String.append " <- " (string_of_bits v)))) - else tt) - : unit). - -Definition reg_name_abi (r : mword 5) -: string := - let b__0 := r in - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "zero" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "ra" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "sp" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "gp" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B1;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "tp" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B1;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "t0" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B1;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "t1" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B1;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "t2" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "fp" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B0;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s1" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B0;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "a0" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B0;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "a1" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B1;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "a2" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B1;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "a3" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B1;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "a4" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B1;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "a5" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "a6" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B0;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "a7" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B0;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s2" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B0;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s3" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B1;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s4" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B1;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s5" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B1;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s6" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B1;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s7" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s8" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B0;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s9" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B0;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s10" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B0;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s11" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B1;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "t3" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B1;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "t4" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B1;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "t5" - else "t6". - -Definition Architecture_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} -: Architecture := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then RV32 - else if sumbool_of_bool ((Z.eqb p0_ 1)) then RV64 - else RV128. - -Definition num_of_Architecture (arg_ : Architecture) -: {e : Z & ArithFact (0 <= e /\ e <= 2)} := - build_ex(match arg_ with | RV32 => 0 | RV64 => 1 | RV128 => 2 end). - -Definition architecture (a : mword 2) -: option Architecture := - let b__0 := a in - if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then Some (RV32) - else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then Some (RV64) - else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then Some (RV128) - else None. - -Definition arch_to_bits (a : Architecture) -: mword 2 := - match a with - | RV32 => (vec_of_bits [B0;B1] : mword 2) - | RV64 => (vec_of_bits [B1;B0] : mword 2) - | RV128 => (vec_of_bits [B1;B1] : mword 2) - end. - -Definition Privilege_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} -: Privilege := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then User - else if sumbool_of_bool ((Z.eqb p0_ 1)) then Supervisor - else Machine. - -Definition num_of_Privilege (arg_ : Privilege) -: {e : Z & ArithFact (0 <= e /\ e <= 2)} := - build_ex(match arg_ with | User => 0 | Supervisor => 1 | Machine => 2 end). - -Definition privLevel_to_bits (p : Privilege) -: mword 2 := - match p with - | User => (vec_of_bits [B0;B0] : mword 2) - | Supervisor => (vec_of_bits [B0;B1] : mword 2) - | Machine => (vec_of_bits [B1;B1] : mword 2) - end. - -Definition privLevel_of_bits (p : mword 2) -: Privilege := - let b__0 := p in - if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then User - else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then Supervisor - else Machine. - -Definition privLevel_to_str (p : Privilege) -: string := - match p with | User => "U" | Supervisor => "S" | Machine => "M" end. - -Definition AccessType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} -: AccessType := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then Read - else if sumbool_of_bool ((Z.eqb p0_ 1)) then Write - else if sumbool_of_bool ((Z.eqb p0_ 2)) then ReadWrite - else Execute. - -Definition num_of_AccessType (arg_ : AccessType) -: {e : Z & ArithFact (0 <= e /\ e <= 3)} := - build_ex(match arg_ with | Read => 0 | Write => 1 | ReadWrite => 2 | Execute => 3 end). - -Definition accessType_to_str (a : AccessType) -: string := - match a with | Read => "R" | Write => "W" | ReadWrite => "RW" | Execute => "X" end. - -Definition ReadType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 1)} -: ReadType := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then Instruction - else Data. - -Definition num_of_ReadType (arg_ : ReadType) -: {e : Z & ArithFact (0 <= e /\ e <= 1)} := - build_ex(match arg_ with | Instruction => 0 | Data => 1 end). - -Definition readType_to_str (r : ReadType) -: string := - match r with | Instruction => "I" | Data => "D" end. - -Definition word_width_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} -: word_width := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then BYTE - else if sumbool_of_bool ((Z.eqb p0_ 1)) then HALF - else if sumbool_of_bool ((Z.eqb p0_ 2)) then WORD - else DOUBLE. - -Definition num_of_word_width (arg_ : word_width) -: {e : Z & ArithFact (0 <= e /\ e <= 3)} := - build_ex(match arg_ with | BYTE => 0 | HALF => 1 | WORD => 2 | DOUBLE => 3 end). - -Definition InterruptType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 8)} -: InterruptType := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then I_U_Software - else if sumbool_of_bool ((Z.eqb p0_ 1)) then I_S_Software - else if sumbool_of_bool ((Z.eqb p0_ 2)) then I_M_Software - else if sumbool_of_bool ((Z.eqb p0_ 3)) then I_U_Timer - else if sumbool_of_bool ((Z.eqb p0_ 4)) then I_S_Timer - else if sumbool_of_bool ((Z.eqb p0_ 5)) then I_M_Timer - else if sumbool_of_bool ((Z.eqb p0_ 6)) then I_U_External - else if sumbool_of_bool ((Z.eqb p0_ 7)) then I_S_External - else I_M_External. - -Definition num_of_InterruptType (arg_ : InterruptType) -: {e : Z & ArithFact (0 <= e /\ e <= 8)} := - build_ex(match arg_ with - | I_U_Software => 0 - | I_S_Software => 1 - | I_M_Software => 2 - | I_U_Timer => 3 - | I_S_Timer => 4 - | I_M_Timer => 5 - | I_U_External => 6 - | I_S_External => 7 - | I_M_External => 8 - end). - -Definition interruptType_to_bits (i : InterruptType) -: mword 4 := - match i with - | I_U_Software => (vec_of_bits [B0;B0;B0;B0] : mword 4) - | I_S_Software => (vec_of_bits [B0;B0;B0;B1] : mword 4) - | I_M_Software => (vec_of_bits [B0;B0;B1;B1] : mword 4) - | I_U_Timer => (vec_of_bits [B0;B1;B0;B0] : mword 4) - | I_S_Timer => (vec_of_bits [B0;B1;B0;B1] : mword 4) - | I_M_Timer => (vec_of_bits [B0;B1;B1;B1] : mword 4) - | I_U_External => (vec_of_bits [B1;B0;B0;B0] : mword 4) - | I_S_External => (vec_of_bits [B1;B0;B0;B1] : mword 4) - | I_M_External => (vec_of_bits [B1;B0;B1;B1] : mword 4) - end. - -Definition ExceptionType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 15)} -: ExceptionType := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then E_Fetch_Addr_Align - else if sumbool_of_bool ((Z.eqb p0_ 1)) then E_Fetch_Access_Fault - else if sumbool_of_bool ((Z.eqb p0_ 2)) then E_Illegal_Instr - else if sumbool_of_bool ((Z.eqb p0_ 3)) then E_Breakpoint - else if sumbool_of_bool ((Z.eqb p0_ 4)) then E_Load_Addr_Align - else if sumbool_of_bool ((Z.eqb p0_ 5)) then E_Load_Access_Fault - else if sumbool_of_bool ((Z.eqb p0_ 6)) then E_SAMO_Addr_Align - else if sumbool_of_bool ((Z.eqb p0_ 7)) then E_SAMO_Access_Fault - else if sumbool_of_bool ((Z.eqb p0_ 8)) then E_U_EnvCall - else if sumbool_of_bool ((Z.eqb p0_ 9)) then E_S_EnvCall - else if sumbool_of_bool ((Z.eqb p0_ 10)) then E_Reserved_10 - else if sumbool_of_bool ((Z.eqb p0_ 11)) then E_M_EnvCall - else if sumbool_of_bool ((Z.eqb p0_ 12)) then E_Fetch_Page_Fault - else if sumbool_of_bool ((Z.eqb p0_ 13)) then E_Load_Page_Fault - else if sumbool_of_bool ((Z.eqb p0_ 14)) then E_Reserved_14 - else E_SAMO_Page_Fault. - -Definition num_of_ExceptionType (arg_ : ExceptionType) -: {e : Z & ArithFact (0 <= e /\ e <= 15)} := - build_ex(match arg_ with - | E_Fetch_Addr_Align => 0 - | E_Fetch_Access_Fault => 1 - | E_Illegal_Instr => 2 - | E_Breakpoint => 3 - | E_Load_Addr_Align => 4 - | E_Load_Access_Fault => 5 - | E_SAMO_Addr_Align => 6 - | E_SAMO_Access_Fault => 7 - | E_U_EnvCall => 8 - | E_S_EnvCall => 9 - | E_Reserved_10 => 10 - | E_M_EnvCall => 11 - | E_Fetch_Page_Fault => 12 - | E_Load_Page_Fault => 13 - | E_Reserved_14 => 14 - | E_SAMO_Page_Fault => 15 - end). - -Definition exceptionType_to_bits (e : ExceptionType) -: mword 4 := - match e with - | E_Fetch_Addr_Align => (vec_of_bits [B0;B0;B0;B0] : mword 4) - | E_Fetch_Access_Fault => (vec_of_bits [B0;B0;B0;B1] : mword 4) - | E_Illegal_Instr => (vec_of_bits [B0;B0;B1;B0] : mword 4) - | E_Breakpoint => (vec_of_bits [B0;B0;B1;B1] : mword 4) - | E_Load_Addr_Align => (vec_of_bits [B0;B1;B0;B0] : mword 4) - | E_Load_Access_Fault => (vec_of_bits [B0;B1;B0;B1] : mword 4) - | E_SAMO_Addr_Align => (vec_of_bits [B0;B1;B1;B0] : mword 4) - | E_SAMO_Access_Fault => (vec_of_bits [B0;B1;B1;B1] : mword 4) - | E_U_EnvCall => (vec_of_bits [B1;B0;B0;B0] : mword 4) - | E_S_EnvCall => (vec_of_bits [B1;B0;B0;B1] : mword 4) - | E_Reserved_10 => (vec_of_bits [B1;B0;B1;B0] : mword 4) - | E_M_EnvCall => (vec_of_bits [B1;B0;B1;B1] : mword 4) - | E_Fetch_Page_Fault => (vec_of_bits [B1;B1;B0;B0] : mword 4) - | E_Load_Page_Fault => (vec_of_bits [B1;B1;B0;B1] : mword 4) - | E_Reserved_14 => (vec_of_bits [B1;B1;B1;B0] : mword 4) - | E_SAMO_Page_Fault => (vec_of_bits [B1;B1;B1;B1] : mword 4) - end. - -Definition exceptionType_to_str (e : ExceptionType) -: string := - match e with - | E_Fetch_Addr_Align => "misaligned-fetch" - | E_Fetch_Access_Fault => "fetch-access-fault" - | E_Illegal_Instr => "illegal-instruction" - | E_Breakpoint => "breakpoint" - | E_Load_Addr_Align => "misaligned-load" - | E_Load_Access_Fault => "load-access-fault" - | E_SAMO_Addr_Align => "misaliged-store/amo" - | E_SAMO_Access_Fault => "store/amo-access-fault" - | E_U_EnvCall => "u-call" - | E_S_EnvCall => "s-call" - | E_Reserved_10 => "reserved-0" - | E_M_EnvCall => "m-call" - | E_Fetch_Page_Fault => "fetch-page-fault" - | E_Load_Page_Fault => "load-page-fault" - | E_Reserved_14 => "reserved-1" - | E_SAMO_Page_Fault => "store/amo-page-fault" - end. - -Definition not_implemented {a : Type} (message : string) -: M (a) := - (throw (Error_not_implemented - (message))) - : M (a). - -Definition internal_error {a : Type} (s : string) -: M (a) := - assert_exp' false s >>= fun _ => (throw (Error_internal_error (tt))) : M (a). - -Definition TrapVectorMode_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} -: TrapVectorMode := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then TV_Direct - else if sumbool_of_bool ((Z.eqb p0_ 1)) then TV_Vector - else TV_Reserved. - -Definition num_of_TrapVectorMode (arg_ : TrapVectorMode) -: {e : Z & ArithFact (0 <= e /\ e <= 2)} := - build_ex(match arg_ with | TV_Direct => 0 | TV_Vector => 1 | TV_Reserved => 2 end). - -Definition trapVectorMode_of_bits (m : mword 2) -: TrapVectorMode := - let b__0 := m in - if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then TV_Direct - else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then TV_Vector - else TV_Reserved. - -Definition ExtStatus_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} -: ExtStatus := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then Off - else if sumbool_of_bool ((Z.eqb p0_ 1)) then Initial - else if sumbool_of_bool ((Z.eqb p0_ 2)) then Clean - else Dirty. - -Definition num_of_ExtStatus (arg_ : ExtStatus) -: {e : Z & ArithFact (0 <= e /\ e <= 3)} := - build_ex(match arg_ with | Off => 0 | Initial => 1 | Clean => 2 | Dirty => 3 end). - -Definition extStatus_to_bits (e : ExtStatus) -: mword 2 := - match e with - | Off => (vec_of_bits [B0;B0] : mword 2) - | Initial => (vec_of_bits [B0;B1] : mword 2) - | Clean => (vec_of_bits [B1;B0] : mword 2) - | Dirty => (vec_of_bits [B1;B1] : mword 2) - end. - -Definition extStatus_of_bits (e : mword 2) -: ExtStatus := - let b__0 := e in - if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then Off - else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then Initial - else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then Clean - else Dirty. - -Definition SATPMode_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} -: SATPMode := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then Sbare - else if sumbool_of_bool ((Z.eqb p0_ 1)) then Sv32 - else Sv39. - -Definition num_of_SATPMode (arg_ : SATPMode) -: {e : Z & ArithFact (0 <= e /\ e <= 2)} := - build_ex(match arg_ with | Sbare => 0 | Sv32 => 1 | Sv39 => 2 end). - -Definition satpMode_of_bits (a : Architecture) (m : mword 4) -: option SATPMode := - match (a, m) with - | (g__19, b__0) => - if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0] : mword 4))) then Some (Sbare) - else - match (g__19, b__0) with - | (RV32, b__0) => - if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1] : mword 4))) then Some (Sv32) - else match (RV32, b__0) with | (g__20, g__21) => None end - | (RV64, b__0) => - if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0] : mword 4))) then Some (Sv39) - else match (RV64, b__0) with | (g__20, g__21) => None end - | (g__20, g__21) => None - end - end. - -Definition uop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 1)} -: uop := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_LUI - else RISCV_AUIPC. - -Definition num_of_uop (arg_ : uop) -: {e : Z & ArithFact (0 <= e /\ e <= 1)} := - build_ex(match arg_ with | RISCV_LUI => 0 | RISCV_AUIPC => 1 end). - -Definition bop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 5)} -: bop := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_BEQ - else if sumbool_of_bool ((Z.eqb p0_ 1)) then RISCV_BNE - else if sumbool_of_bool ((Z.eqb p0_ 2)) then RISCV_BLT - else if sumbool_of_bool ((Z.eqb p0_ 3)) then RISCV_BGE - else if sumbool_of_bool ((Z.eqb p0_ 4)) then RISCV_BLTU - else RISCV_BGEU. - -Definition num_of_bop (arg_ : bop) -: {e : Z & ArithFact (0 <= e /\ e <= 5)} := - build_ex(match arg_ with - | RISCV_BEQ => 0 - | RISCV_BNE => 1 - | RISCV_BLT => 2 - | RISCV_BGE => 3 - | RISCV_BLTU => 4 - | RISCV_BGEU => 5 - end). - -Definition iop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 5)} -: iop := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_ADDI - else if sumbool_of_bool ((Z.eqb p0_ 1)) then RISCV_SLTI - else if sumbool_of_bool ((Z.eqb p0_ 2)) then RISCV_SLTIU - else if sumbool_of_bool ((Z.eqb p0_ 3)) then RISCV_XORI - else if sumbool_of_bool ((Z.eqb p0_ 4)) then RISCV_ORI - else RISCV_ANDI. - -Definition num_of_iop (arg_ : iop) -: {e : Z & ArithFact (0 <= e /\ e <= 5)} := - build_ex(match arg_ with - | RISCV_ADDI => 0 - | RISCV_SLTI => 1 - | RISCV_SLTIU => 2 - | RISCV_XORI => 3 - | RISCV_ORI => 4 - | RISCV_ANDI => 5 - end). - -Definition sop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} -: sop := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_SLLI - else if sumbool_of_bool ((Z.eqb p0_ 1)) then RISCV_SRLI - else RISCV_SRAI. - -Definition num_of_sop (arg_ : sop) -: {e : Z & ArithFact (0 <= e /\ e <= 2)} := - build_ex(match arg_ with | RISCV_SLLI => 0 | RISCV_SRLI => 1 | RISCV_SRAI => 2 end). - -Definition rop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 9)} -: rop := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_ADD - else if sumbool_of_bool ((Z.eqb p0_ 1)) then RISCV_SUB - else if sumbool_of_bool ((Z.eqb p0_ 2)) then RISCV_SLL - else if sumbool_of_bool ((Z.eqb p0_ 3)) then RISCV_SLT - else if sumbool_of_bool ((Z.eqb p0_ 4)) then RISCV_SLTU - else if sumbool_of_bool ((Z.eqb p0_ 5)) then RISCV_XOR - else if sumbool_of_bool ((Z.eqb p0_ 6)) then RISCV_SRL - else if sumbool_of_bool ((Z.eqb p0_ 7)) then RISCV_SRA - else if sumbool_of_bool ((Z.eqb p0_ 8)) then RISCV_OR - else RISCV_AND. - -Definition num_of_rop (arg_ : rop) -: {e : Z & ArithFact (0 <= e /\ e <= 9)} := - build_ex(match arg_ with - | RISCV_ADD => 0 - | RISCV_SUB => 1 - | RISCV_SLL => 2 - | RISCV_SLT => 3 - | RISCV_SLTU => 4 - | RISCV_XOR => 5 - | RISCV_SRL => 6 - | RISCV_SRA => 7 - | RISCV_OR => 8 - | RISCV_AND => 9 - end). - -Definition ropw_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 4)} -: ropw := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_ADDW - else if sumbool_of_bool ((Z.eqb p0_ 1)) then RISCV_SUBW - else if sumbool_of_bool ((Z.eqb p0_ 2)) then RISCV_SLLW - else if sumbool_of_bool ((Z.eqb p0_ 3)) then RISCV_SRLW - else RISCV_SRAW. - -Definition num_of_ropw (arg_ : ropw) -: {e : Z & ArithFact (0 <= e /\ e <= 4)} := - build_ex(match arg_ with - | RISCV_ADDW => 0 - | RISCV_SUBW => 1 - | RISCV_SLLW => 2 - | RISCV_SRLW => 3 - | RISCV_SRAW => 4 - end). - -Definition sopw_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} -: sopw := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_SLLIW - else if sumbool_of_bool ((Z.eqb p0_ 1)) then RISCV_SRLIW - else RISCV_SRAIW. - -Definition num_of_sopw (arg_ : sopw) -: {e : Z & ArithFact (0 <= e /\ e <= 2)} := - build_ex(match arg_ with | RISCV_SLLIW => 0 | RISCV_SRLIW => 1 | RISCV_SRAIW => 2 end). - -Definition amoop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 8)} -: amoop := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then AMOSWAP - else if sumbool_of_bool ((Z.eqb p0_ 1)) then AMOADD - else if sumbool_of_bool ((Z.eqb p0_ 2)) then AMOXOR - else if sumbool_of_bool ((Z.eqb p0_ 3)) then AMOAND - else if sumbool_of_bool ((Z.eqb p0_ 4)) then AMOOR - else if sumbool_of_bool ((Z.eqb p0_ 5)) then AMOMIN - else if sumbool_of_bool ((Z.eqb p0_ 6)) then AMOMAX - else if sumbool_of_bool ((Z.eqb p0_ 7)) then AMOMINU - else AMOMAXU. - -Definition num_of_amoop (arg_ : amoop) -: {e : Z & ArithFact (0 <= e /\ e <= 8)} := - build_ex(match arg_ with - | AMOSWAP => 0 - | AMOADD => 1 - | AMOXOR => 2 - | AMOAND => 3 - | AMOOR => 4 - | AMOMIN => 5 - | AMOMAX => 6 - | AMOMINU => 7 - | AMOMAXU => 8 - end). - -Definition csrop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} -: csrop := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then CSRRW - else if sumbool_of_bool ((Z.eqb p0_ 1)) then CSRRS - else CSRRC. - -Definition num_of_csrop (arg_ : csrop) -: {e : Z & ArithFact (0 <= e /\ e <= 2)} := - build_ex(match arg_ with | CSRRW => 0 | CSRRS => 1 | CSRRC => 2 end). - -Definition reg_name_forwards (arg_ : mword 5) -: string := - let b__0 := arg_ in - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "zero" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "ra" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "sp" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "gp" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B1;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "tp" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B1;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "t0" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B1;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "t1" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B1;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "t2" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "fp" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B0;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s1" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B0;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "a0" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B0;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "a1" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B1;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "a2" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B1;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "a3" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B1;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "a4" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B1;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "a5" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "a6" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B0;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "a7" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B0;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s2" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B0;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s3" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B1;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s4" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B1;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s5" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B1;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s6" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B1;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s7" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s8" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B0;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s9" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B0;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s10" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B0;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "s11" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B1;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "t3" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B1;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "t4" - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B1;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - "t5" - else "t6". - -Definition reg_name_backwards (arg_ : string) -: M (mword 5) := - (match arg_ with - | "zero" => returnm ((vec_of_bits [B0;B0;B0;B0;B0] : mword 5) : mword 5) - | "ra" => returnm ((vec_of_bits [B0;B0;B0;B0;B1] : mword 5) : mword 5) - | "sp" => returnm ((vec_of_bits [B0;B0;B0;B1;B0] : mword 5) : mword 5) - | "gp" => returnm ((vec_of_bits [B0;B0;B0;B1;B1] : mword 5) : mword 5) - | "tp" => returnm ((vec_of_bits [B0;B0;B1;B0;B0] : mword 5) : mword 5) - | "t0" => returnm ((vec_of_bits [B0;B0;B1;B0;B1] : mword 5) : mword 5) - | "t1" => returnm ((vec_of_bits [B0;B0;B1;B1;B0] : mword 5) : mword 5) - | "t2" => returnm ((vec_of_bits [B0;B0;B1;B1;B1] : mword 5) : mword 5) - | "fp" => returnm ((vec_of_bits [B0;B1;B0;B0;B0] : mword 5) : mword 5) - | "s1" => returnm ((vec_of_bits [B0;B1;B0;B0;B1] : mword 5) : mword 5) - | "a0" => returnm ((vec_of_bits [B0;B1;B0;B1;B0] : mword 5) : mword 5) - | "a1" => returnm ((vec_of_bits [B0;B1;B0;B1;B1] : mword 5) : mword 5) - | "a2" => returnm ((vec_of_bits [B0;B1;B1;B0;B0] : mword 5) : mword 5) - | "a3" => returnm ((vec_of_bits [B0;B1;B1;B0;B1] : mword 5) : mword 5) - | "a4" => returnm ((vec_of_bits [B0;B1;B1;B1;B0] : mword 5) : mword 5) - | "a5" => returnm ((vec_of_bits [B0;B1;B1;B1;B1] : mword 5) : mword 5) - | "a6" => returnm ((vec_of_bits [B1;B0;B0;B0;B0] : mword 5) : mword 5) - | "a7" => returnm ((vec_of_bits [B1;B0;B0;B0;B1] : mword 5) : mword 5) - | "s2" => returnm ((vec_of_bits [B1;B0;B0;B1;B0] : mword 5) : mword 5) - | "s3" => returnm ((vec_of_bits [B1;B0;B0;B1;B1] : mword 5) : mword 5) - | "s4" => returnm ((vec_of_bits [B1;B0;B1;B0;B0] : mword 5) : mword 5) - | "s5" => returnm ((vec_of_bits [B1;B0;B1;B0;B1] : mword 5) : mword 5) - | "s6" => returnm ((vec_of_bits [B1;B0;B1;B1;B0] : mword 5) : mword 5) - | "s7" => returnm ((vec_of_bits [B1;B0;B1;B1;B1] : mword 5) : mword 5) - | "s8" => returnm ((vec_of_bits [B1;B1;B0;B0;B0] : mword 5) : mword 5) - | "s9" => returnm ((vec_of_bits [B1;B1;B0;B0;B1] : mword 5) : mword 5) - | "s10" => returnm ((vec_of_bits [B1;B1;B0;B1;B0] : mword 5) : mword 5) - | "s11" => returnm ((vec_of_bits [B1;B1;B0;B1;B1] : mword 5) : mword 5) - | "t3" => returnm ((vec_of_bits [B1;B1;B1;B0;B0] : mword 5) : mword 5) - | "t4" => returnm ((vec_of_bits [B1;B1;B1;B0;B1] : mword 5) : mword 5) - | "t5" => returnm ((vec_of_bits [B1;B1;B1;B1;B0] : mword 5) : mword 5) - | "t6" => returnm ((vec_of_bits [B1;B1;B1;B1;B1] : mword 5) : mword 5) - | _ => exit tt : M (mword 5) - end) - : M (mword 5). - -Definition reg_name_forwards_matches (arg_ : mword 5) -: bool := - let b__0 := arg_ in - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B1;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B1;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B1;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B1;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B0;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B0;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B0;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B1;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B1;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B1;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B1;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B0;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B0;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B0;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B1;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B1;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B1;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B1;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B0;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B0;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B0;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B1;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B1;B0;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B1;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B1;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else false. - -Definition reg_name_backwards_matches (arg_ : string) -: bool := - match arg_ with - | "zero" => true - | "ra" => true - | "sp" => true - | "gp" => true - | "tp" => true - | "t0" => true - | "t1" => true - | "t2" => true - | "fp" => true - | "s1" => true - | "a0" => true - | "a1" => true - | "a2" => true - | "a3" => true - | "a4" => true - | "a5" => true - | "a6" => true - | "a7" => true - | "s2" => true - | "s3" => true - | "s4" => true - | "s5" => true - | "s6" => true - | "s7" => true - | "s8" => true - | "s9" => true - | "s10" => true - | "s11" => true - | "t3" => true - | "t4" => true - | "t5" => true - | "t6" => true - | _ => false - end. - -Definition reg_name_matches_prefix (arg_ : string) -: option ((mword 5 * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1319_ := arg_ in - if ((andb (string_startswith _stringappend_1319_ "zero") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "zero")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "zero")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B0;B0] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "ra") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "ra")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "ra")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B0;B1] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "sp") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "sp")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "sp")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B1;B0] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "gp") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "gp")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "gp")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B1;B1] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "tp") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "tp")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "tp")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B0;B0] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "t0") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "t0")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "t0")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B0;B1] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "t1") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "t1")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "t1")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B0] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "t2") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "t2")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "t2")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "fp") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "fp")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "fp")))) with - | s_ => - Some - (((vec_of_bits [B0;B1;B0;B0;B0] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "s1") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s1")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s1")))) with - | s_ => - Some - (((vec_of_bits [B0;B1;B0;B0;B1] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "a0") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "a0")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "a0")))) with - | s_ => - Some - (((vec_of_bits [B0;B1;B0;B1;B0] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "a1") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "a1")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "a1")))) with - | s_ => - Some - (((vec_of_bits [B0;B1;B0;B1;B1] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "a2") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "a2")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "a2")))) with - | s_ => - Some - (((vec_of_bits [B0;B1;B1;B0;B0] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "a3") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "a3")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "a3")))) with - | s_ => - Some - (((vec_of_bits [B0;B1;B1;B0;B1] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "a4") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "a4")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "a4")))) with - | s_ => - Some - (((vec_of_bits [B0;B1;B1;B1;B0] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "a5") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "a5")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "a5")))) with - | s_ => - Some - (((vec_of_bits [B0;B1;B1;B1;B1] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "a6") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "a6")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "a6")))) with - | s_ => - Some - (((vec_of_bits [B1;B0;B0;B0;B0] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "a7") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "a7")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "a7")))) with - | s_ => - Some - (((vec_of_bits [B1;B0;B0;B0;B1] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "s2") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s2")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s2")))) with - | s_ => - Some - (((vec_of_bits [B1;B0;B0;B1;B0] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "s3") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s3")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s3")))) with - | s_ => - Some - (((vec_of_bits [B1;B0;B0;B1;B1] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "s4") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s4")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s4")))) with - | s_ => - Some - (((vec_of_bits [B1;B0;B1;B0;B0] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "s5") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s5")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s5")))) with - | s_ => - Some - (((vec_of_bits [B1;B0;B1;B0;B1] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "s6") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s6")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s6")))) with - | s_ => - Some - (((vec_of_bits [B1;B0;B1;B1;B0] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "s7") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s7")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s7")))) with - | s_ => - Some - (((vec_of_bits [B1;B0;B1;B1;B1] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "s8") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s8")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s8")))) with - | s_ => - Some - (((vec_of_bits [B1;B1;B0;B0;B0] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "s9") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s9")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s9")))) with - | s_ => - Some - (((vec_of_bits [B1;B1;B0;B0;B1] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "s10") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s10")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s10")))) with - | s_ => - Some - (((vec_of_bits [B1;B1;B0;B1;B0] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "s11") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s11")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "s11")))) with - | s_ => - Some - (((vec_of_bits [B1;B1;B0;B1;B1] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "t3") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "t3")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "t3")))) with - | s_ => - Some - (((vec_of_bits [B1;B1;B1;B0;B0] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "t4") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "t4")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "t4")))) with - | s_ => - Some - (((vec_of_bits [B1;B1;B1;B0;B1] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "t5") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "t5")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "t5")))) with - | s_ => - Some - (((vec_of_bits [B1;B1;B1;B1;B0] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1319_ "t6") - (match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "t6")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1319_ (build_ex (projT1 (string_length "t6")))) with - | s_ => - Some - (((vec_of_bits [B1;B1;B1;B1;B1] : mword 5), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else None. - -Definition sep_forwards (arg_ : unit) -: string := - match arg_ with - | tt => - string_append (opt_spc_forwards tt) - (string_append "," (string_append (def_spc_forwards tt) "")) - end. - -Definition sep_backwards (arg_ : string) -: M (unit) := - let _stringappend_1314_ := arg_ in - (match (opt_spc_matches_prefix _stringappend_1314_) with - | Some (tt,(existT _ _stringappend_1315_ _)) => returnm (tt, build_ex _stringappend_1315_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_1315_ _) => - let _stringappend_1316_ := string_drop _stringappend_1314_ (build_ex _stringappend_1315_) in - let _stringappend_1317_ := - string_drop _stringappend_1316_ (build_ex (projT1 (string_length ","))) in - (match (opt_spc_matches_prefix _stringappend_1317_) with - | Some (tt,(existT _ _stringappend_1318_ _)) => returnm (tt, build_ex _stringappend_1318_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_1318_ _) => - (match (string_drop _stringappend_1317_ (build_ex _stringappend_1318_)) with - | "" => returnm (tt : unit) - | _ => exit tt : M (unit) - end) - : M (unit). - -Definition sep_forwards_matches (arg_ : unit) : bool := match arg_ with | tt => true end. - -Definition sep_backwards_matches (arg_ : string) -: M (bool) := - let _stringappend_1309_ := arg_ in - (if ((match (opt_spc_matches_prefix _stringappend_1309_) with - | Some (tt,(existT _ _stringappend_1310_ _)) => - let _stringappend_1311_ := - string_drop _stringappend_1309_ (build_ex _stringappend_1310_) in - if ((andb (string_startswith _stringappend_1311_ ",") - (let _stringappend_1312_ := - string_drop _stringappend_1311_ (build_ex (projT1 (string_length ","))) in - if ((match (opt_spc_matches_prefix _stringappend_1312_) with - | Some (tt,(existT _ _stringappend_1313_ _)) => - match (string_drop _stringappend_1312_ (build_ex _stringappend_1313_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false))) then - true - else false - | None => false - end)) then - (match (opt_spc_matches_prefix _stringappend_1309_) with - | Some (tt,(existT _ _stringappend_1310_ _)) => returnm (tt, build_ex _stringappend_1310_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_1310_ _) => - let _stringappend_1311_ := string_drop _stringappend_1309_ (build_ex _stringappend_1310_) in - let _stringappend_1312_ := - string_drop _stringappend_1311_ (build_ex (projT1 (string_length ","))) in - (match (opt_spc_matches_prefix _stringappend_1312_) with - | Some (tt,(existT _ _stringappend_1313_ _)) => returnm (tt, build_ex _stringappend_1313_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_1313_ _) => - (match (string_drop _stringappend_1312_ (build_ex _stringappend_1313_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else returnm (false : bool)) - : M (bool). - -Definition sep_matches_prefix (arg_ : string) -: M (option ((unit * {n : Z & ArithFact (n >= 0)}))) := - let _stringappend_1304_ := arg_ in - (if ((match (opt_spc_matches_prefix _stringappend_1304_) with - | Some (tt,(existT _ _stringappend_1305_ _)) => - let _stringappend_1306_ := - string_drop _stringappend_1304_ (build_ex _stringappend_1305_) in - if ((andb (string_startswith _stringappend_1306_ ",") - (let _stringappend_1307_ := - string_drop _stringappend_1306_ (build_ex (projT1 (string_length ","))) in - if ((match (opt_spc_matches_prefix _stringappend_1307_) with - | Some (tt,(existT _ _stringappend_1308_ _)) => - match (string_drop _stringappend_1307_ (build_ex _stringappend_1308_)) with - | s_ => true - end - | None => false - end)) then - true - else false))) then - true - else false - | None => false - end)) then - (match (opt_spc_matches_prefix _stringappend_1304_) with - | Some (tt,(existT _ _stringappend_1305_ _)) => returnm (tt, build_ex _stringappend_1305_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_1305_ _) => - let _stringappend_1306_ := string_drop _stringappend_1304_ (build_ex _stringappend_1305_) in - let _stringappend_1307_ := - string_drop _stringappend_1306_ (build_ex (projT1 (string_length ","))) in - (match (opt_spc_matches_prefix _stringappend_1307_) with - | Some (tt,(existT _ _stringappend_1308_ _)) => returnm (tt, build_ex _stringappend_1308_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_1308_ _) => - returnm ((match (string_drop _stringappend_1307_ (build_ex _stringappend_1308_)) with - | s_ => - Some - ((tt, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end) - : option ((unit * {n : Z & ArithFact (n >= 0)}))) - else returnm (None : option ((unit * {n : Z & ArithFact (n >= 0)})))) - : M (option ((unit * {n : Z & ArithFact (n >= 0)}))). - -Definition bool_bits_forwards (arg_ : bool) -: mword 1 := - match arg_ with - | true => (vec_of_bits [B1] : mword 1) - | false => (vec_of_bits [B0] : mword 1) - end. - -Definition bool_bits_backwards (arg_ : mword 1) -: bool := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true - else false. - -Definition bool_bits_forwards_matches (arg_ : bool) -: bool := - match arg_ with | true => true | false => true end. - -Definition bool_bits_backwards_matches (arg_ : mword 1) -: bool := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true - else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true - else false. - -Definition bool_not_bits_forwards (arg_ : bool) -: mword 1 := - match arg_ with - | true => (vec_of_bits [B0] : mword 1) - | false => (vec_of_bits [B1] : mword 1) - end. - -Definition bool_not_bits_backwards (arg_ : mword 1) -: bool := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true - else false. - -Definition bool_not_bits_forwards_matches (arg_ : bool) -: bool := - match arg_ with | true => true | false => true end. - -Definition bool_not_bits_backwards_matches (arg_ : mword 1) -: bool := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true - else if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true - else false. - -Definition size_bits_forwards (arg_ : word_width) -: mword 2 := - match arg_ with - | BYTE => (vec_of_bits [B0;B0] : mword 2) - | HALF => (vec_of_bits [B0;B1] : mword 2) - | WORD => (vec_of_bits [B1;B0] : mword 2) - | DOUBLE => (vec_of_bits [B1;B1] : mword 2) - end. - -Definition size_bits_backwards (arg_ : mword 2) -: word_width := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then BYTE - else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then HALF - else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then WORD - else DOUBLE. - -Definition size_bits_forwards_matches (arg_ : word_width) -: bool := - match arg_ with | BYTE => true | HALF => true | WORD => true | DOUBLE => true end. - -Definition size_bits_backwards_matches (arg_ : mword 2) -: bool := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then true - else false. - -Definition size_mnemonic_forwards (arg_ : word_width) -: string := - match arg_ with | BYTE => "b" | HALF => "h" | WORD => "w" | DOUBLE => "d" end. - -Definition size_mnemonic_backwards (arg_ : string) -: M (word_width) := - (match arg_ with - | "b" => returnm (BYTE : word_width) - | "h" => returnm (HALF : word_width) - | "w" => returnm (WORD : word_width) - | "d" => returnm (DOUBLE : word_width) - | _ => exit tt : M (word_width) - end) - : M (word_width). - -Definition size_mnemonic_forwards_matches (arg_ : word_width) -: bool := - match arg_ with | BYTE => true | HALF => true | WORD => true | DOUBLE => true end. - -Definition size_mnemonic_backwards_matches (arg_ : string) -: bool := - match arg_ with | "b" => true | "h" => true | "w" => true | "d" => true | _ => false end. - -Definition size_mnemonic_matches_prefix (arg_ : string) -: option ((word_width * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1300_ := arg_ in - if ((andb (string_startswith _stringappend_1300_ "b") - (match (string_drop _stringappend_1300_ (build_ex (projT1 (string_length "b")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1300_ (build_ex (projT1 (string_length "b")))) with - | s_ => - Some - ((BYTE, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1300_ "h") - (match (string_drop _stringappend_1300_ (build_ex (projT1 (string_length "h")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1300_ (build_ex (projT1 (string_length "h")))) with - | s_ => - Some - ((HALF, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1300_ "w") - (match (string_drop _stringappend_1300_ (build_ex (projT1 (string_length "w")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1300_ (build_ex (projT1 (string_length "w")))) with - | s_ => - Some - ((WORD, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1300_ "d") - (match (string_drop _stringappend_1300_ (build_ex (projT1 (string_length "d")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1300_ (build_ex (projT1 (string_length "d")))) with - | s_ => - Some - ((DOUBLE, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition Mk_Misa (v : mword 64) : Misa := {| Misa_Misa_chunk_0 := (subrange_vec_dec v 63 0) |}. - -Definition _get_Misa_bits (v : Misa) : mword 64 := subrange_vec_dec v.(Misa_Misa_chunk_0) 63 0. - -Definition _set_Misa_bits (r_ref : register_ref regstate register_value Misa) (v : mword 64) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_bits (v : Misa) (x : mword 64) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. - -Definition _get_Misa_MXL (v : Misa) : mword 2 := subrange_vec_dec v.(Misa_Misa_chunk_0) 63 62. - -Definition _set_Misa_MXL (r_ref : register_ref regstate register_value Misa) (v : mword 2) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 63 62 (subrange_vec_dec v 1 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_MXL (v : Misa) (x : mword 2) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 63 62 (subrange_vec_dec x 1 0)) ]}. - -Definition _get_Misa_Z (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 25 25. - -Definition _set_Misa_Z (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 25 25 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_Z (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 25 25 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_Y (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 24 24. - -Definition _set_Misa_Y (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 24 24 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_Y (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 24 24 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_X (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 23 23. - -Definition _set_Misa_X (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 23 23 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_X (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 23 23 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_W (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 22 22. - -Definition _set_Misa_W (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_W (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_V (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 21 21. - -Definition _set_Misa_V (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 21 21 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_V (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 21 21 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_U (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 20 20. - -Definition _set_Misa_U (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 20 20 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_U (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 20 20 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_T (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 19 19. - -Definition _set_Misa_T (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 19 19 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_T (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 19 19 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_S (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 18 18. - -Definition _set_Misa_S (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 18 18 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_S (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 18 18 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_R (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 17 17. - -Definition _set_Misa_R (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 17 17 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_R (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 17 17 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_Q (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 16 16. - -Definition _set_Misa_Q (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 16 16 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_Q (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 16 16 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_P (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 15 15. - -Definition _set_Misa_P (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 15 15 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_P (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 15 15 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_O (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 14 14. - -Definition _set_Misa_O (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 14 14 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_O (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 14 14 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_N (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 13 13. - -Definition _set_Misa_N (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 13 13 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_N (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 13 13 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_M (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 12 12. - -Definition _set_Misa_M (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 12 12 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_M (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 12 12 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_L (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 11 11. - -Definition _set_Misa_L (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 11 11 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_L (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 11 11 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_K (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 10 10. - -Definition _set_Misa_K (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 10 10 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_K (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 10 10 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_J (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 9 9. - -Definition _set_Misa_J (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 9 9 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_J (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 9 9 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_I (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 8 8. - -Definition _set_Misa_I (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_I (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_H (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 7 7. - -Definition _set_Misa_H (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_H (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_G (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 6 6. - -Definition _set_Misa_G (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_G (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_F (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 5 5. - -Definition _set_Misa_F (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_F (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_E (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 4 4. - -Definition _set_Misa_E (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_E (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_D (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 3 3. - -Definition _set_Misa_D (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_D (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_C (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 2 2. - -Definition _set_Misa_C (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_C (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_B (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 1 1. - -Definition _set_Misa_B (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_B (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Misa_A (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 0 0. - -Definition _set_Misa_A (r_ref : register_ref regstate register_value Misa) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} - : Misa in - write_reg r_ref r - : M (unit). - -Definition _update_Misa_A (v : Misa) (x : mword 1) -: Misa := - {[ v with - Misa_Misa_chunk_0 := - (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. - -Definition legalize_misa (m : Misa) (v : mword 64) -: M (Misa) := - let v := Mk_Misa v in - and_boolM (returnm ((eq_vec (_get_Misa_C v) ((bool_to_bits false) : mword 1)) : bool)) - ((read_reg nextPC_ref : M (mword 64)) >>= fun w__0 : xlenbits => - bit_to_bool (access_vec_dec w__0 1) >>= fun w__1 : bool => - returnm ((Bool.eqb (w__1 : bool) true) - : bool)) >>= fun w__2 : bool => - returnm ((if (w__2) then m - else _update_Misa_C m (_get_Misa_C v)) - : Misa). - -Definition Mk_Mstatus (v : mword 64) -: Mstatus := - {| Mstatus_Mstatus_chunk_0 := (subrange_vec_dec v 63 0) |}. - -Definition _get_Mstatus_bits (v : Mstatus) -: mword 64 := - subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 63 0. - -Definition _set_Mstatus_bits (r_ref : register_ref regstate register_value Mstatus) (v : mword 64) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} - : Mstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Mstatus_bits (v : Mstatus) (x : mword 64) -: Mstatus := - {[ v with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. - -Definition _get_Mstatus_SD (v : Mstatus) -: mword 1 := - subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 63 63. - -Definition _set_Mstatus_SD (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 63 63 (subrange_vec_dec v 0 0)) ]} - : Mstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Mstatus_SD (v : Mstatus) (x : mword 1) -: Mstatus := - {[ v with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 63 63 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Mstatus_SXL (v : Mstatus) -: mword 2 := - subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 35 34. - -Definition _set_Mstatus_SXL (r_ref : register_ref regstate register_value Mstatus) (v : mword 2) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 35 34 (subrange_vec_dec v 1 0)) ]} - : Mstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Mstatus_SXL (v : Mstatus) (x : mword 2) -: Mstatus := - {[ v with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 35 34 (subrange_vec_dec x 1 0)) ]}. - -Definition _get_Mstatus_UXL (v : Mstatus) -: mword 2 := - subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 33 32. - -Definition _set_Mstatus_UXL (r_ref : register_ref regstate register_value Mstatus) (v : mword 2) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 33 32 (subrange_vec_dec v 1 0)) ]} - : Mstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Mstatus_UXL (v : Mstatus) (x : mword 2) -: Mstatus := - {[ v with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 33 32 (subrange_vec_dec x 1 0)) ]}. - -Definition _get_Mstatus_TSR (v : Mstatus) -: mword 1 := - subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 22 22. - -Definition _set_Mstatus_TSR (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]} - : Mstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Mstatus_TSR (v : Mstatus) (x : mword 1) -: Mstatus := - {[ v with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Mstatus_TW (v : Mstatus) -: mword 1 := - subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 21 21. - -Definition _set_Mstatus_TW (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 21 21 (subrange_vec_dec v 0 0)) ]} - : Mstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Mstatus_TW (v : Mstatus) (x : mword 1) -: Mstatus := - {[ v with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 21 21 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Mstatus_TVM (v : Mstatus) -: mword 1 := - subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 20 20. - -Definition _set_Mstatus_TVM (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 20 20 (subrange_vec_dec v 0 0)) ]} - : Mstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Mstatus_TVM (v : Mstatus) (x : mword 1) -: Mstatus := - {[ v with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 20 20 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Mstatus_MXR (v : Mstatus) -: mword 1 := - subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 19 19. - -Definition _set_Mstatus_MXR (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 19 19 (subrange_vec_dec v 0 0)) ]} - : Mstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Mstatus_MXR (v : Mstatus) (x : mword 1) -: Mstatus := - {[ v with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 19 19 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Mstatus_SUM (v : Mstatus) -: mword 1 := - subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 18 18. - -Definition _set_Mstatus_SUM (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 18 18 (subrange_vec_dec v 0 0)) ]} - : Mstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Mstatus_SUM (v : Mstatus) (x : mword 1) -: Mstatus := - {[ v with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 18 18 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Mstatus_MPRV (v : Mstatus) -: mword 1 := - subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 17 17. - -Definition _set_Mstatus_MPRV (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 17 17 (subrange_vec_dec v 0 0)) ]} - : Mstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Mstatus_MPRV (v : Mstatus) (x : mword 1) -: Mstatus := - {[ v with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 17 17 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Mstatus_XS (v : Mstatus) -: mword 2 := - subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 16 15. - -Definition _set_Mstatus_XS (r_ref : register_ref regstate register_value Mstatus) (v : mword 2) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 16 15 (subrange_vec_dec v 1 0)) ]} - : Mstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Mstatus_XS (v : Mstatus) (x : mword 2) -: Mstatus := - {[ v with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 16 15 (subrange_vec_dec x 1 0)) ]}. - -Definition _get_Mstatus_FS (v : Mstatus) -: mword 2 := - subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 14 13. - -Definition _set_Mstatus_FS (r_ref : register_ref regstate register_value Mstatus) (v : mword 2) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 14 13 (subrange_vec_dec v 1 0)) ]} - : Mstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Mstatus_FS (v : Mstatus) (x : mword 2) -: Mstatus := - {[ v with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 14 13 (subrange_vec_dec x 1 0)) ]}. - -Definition _get_Mstatus_MPP (v : Mstatus) -: mword 2 := - subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 12 11. - -Definition _set_Mstatus_MPP (r_ref : register_ref regstate register_value Mstatus) (v : mword 2) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 12 11 (subrange_vec_dec v 1 0)) ]} - : Mstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Mstatus_MPP (v : Mstatus) (x : mword 2) -: Mstatus := - {[ v with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 12 11 (subrange_vec_dec x 1 0)) ]}. - -Definition _get_Mstatus_SPP (v : Mstatus) -: mword 1 := - subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 8 8. - -Definition _set_Mstatus_SPP (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} - : Mstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Mstatus_SPP (v : Mstatus) (x : mword 1) -: Mstatus := - {[ v with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Mstatus_MPIE (v : Mstatus) -: mword 1 := - subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 7 7. - -Definition _set_Mstatus_MPIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} - : Mstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Mstatus_MPIE (v : Mstatus) (x : mword 1) -: Mstatus := - {[ v with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Mstatus_SPIE (v : Mstatus) -: mword 1 := - subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 5 5. - -Definition _set_Mstatus_SPIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} - : Mstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Mstatus_SPIE (v : Mstatus) (x : mword 1) -: Mstatus := - {[ v with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Mstatus_UPIE (v : Mstatus) -: mword 1 := - subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 4 4. - -Definition _set_Mstatus_UPIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} - : Mstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Mstatus_UPIE (v : Mstatus) (x : mword 1) -: Mstatus := - {[ v with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Mstatus_MIE (v : Mstatus) -: mword 1 := - subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 3 3. - -Definition _set_Mstatus_MIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]} - : Mstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Mstatus_MIE (v : Mstatus) (x : mword 1) -: Mstatus := - {[ v with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Mstatus_SIE (v : Mstatus) -: mword 1 := - subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 1 1. - -Definition _set_Mstatus_SIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} - : Mstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Mstatus_SIE (v : Mstatus) (x : mword 1) -: Mstatus := - {[ v with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Mstatus_UIE (v : Mstatus) -: mword 1 := - subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 0 0. - -Definition _set_Mstatus_UIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} - : Mstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Mstatus_UIE (v : Mstatus) (x : mword 1) -: Mstatus := - {[ v with - Mstatus_Mstatus_chunk_0 := - (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. - -Definition legalize_mstatus (o : Mstatus) (v : mword 64) -: Mstatus := - let m : Mstatus := Mk_Mstatus v in - let m := _update_Mstatus_XS m (extStatus_to_bits Off) in - let m := - _update_Mstatus_SD m - ((bool_to_bits - (orb - (eq_vec ((extStatus_to_bits (extStatus_of_bits (_get_Mstatus_FS m))) : mword 2) - ((extStatus_to_bits Dirty) - : mword 2)) - (eq_vec ((extStatus_to_bits (extStatus_of_bits (_get_Mstatus_XS m))) : mword 2) - ((extStatus_to_bits Dirty) - : mword 2)))) - : mword 1) in - let m := _update_Mstatus_SXL m (_get_Mstatus_SXL o) in - let m := _update_Mstatus_UXL m (_get_Mstatus_UXL o) in - let m := _update_Mstatus_UPIE m ((bool_to_bits false) : mword 1) in - _update_Mstatus_UIE m ((bool_to_bits false) : mword 1). - -Definition cur_Architecture '(tt : unit) -: M (Architecture) := - read_reg cur_privilege_ref >>= fun w__0 : Privilege => - match w__0 with - | Machine => read_reg misa_ref >>= fun w__1 : Misa => returnm ((_get_Misa_MXL w__1) : mword 2) - | Supervisor => - read_reg mstatus_ref >>= fun w__2 : Mstatus => returnm ((_get_Mstatus_SXL w__2) : mword 2) - | User => - read_reg mstatus_ref >>= fun w__3 : Mstatus => returnm ((_get_Mstatus_UXL w__3) : mword 2) - end >>= fun a : arch_xlen => - (match (architecture a) with - | Some (a) => returnm (a : Architecture) - | None => (internal_error "Invalid current architecture") : M (Architecture) - end) - : M (Architecture). - -Definition in32BitMode '(tt : unit) -: M (bool) := - cur_Architecture tt >>= fun w__0 : Architecture => returnm ((generic_eq w__0 RV32) : bool). - -Definition haveAtomics '(tt : unit) -: M (bool) := - read_reg misa_ref >>= fun w__0 : Misa => - returnm ((eq_vec (_get_Misa_A w__0) ((bool_to_bits true) : mword 1)) - : bool). - -Definition haveRVC '(tt : unit) -: M (bool) := - read_reg misa_ref >>= fun w__0 : Misa => - returnm ((eq_vec (_get_Misa_C w__0) ((bool_to_bits true) : mword 1)) - : bool). - -Definition haveMulDiv '(tt : unit) -: M (bool) := - read_reg misa_ref >>= fun w__0 : Misa => - returnm ((eq_vec (_get_Misa_M w__0) ((bool_to_bits true) : mword 1)) - : bool). - -Definition haveFP '(tt : unit) -: M (bool) := - (or_boolM - (read_reg misa_ref >>= fun w__0 : Misa => - returnm ((eq_vec (_get_Misa_F w__0) ((bool_to_bits true) : mword 1)) - : bool)) - (read_reg misa_ref >>= fun w__1 : Misa => - returnm ((eq_vec (_get_Misa_D w__1) ((bool_to_bits true) : mword 1)) - : bool))) - : M (bool). - -Definition Mk_Minterrupts (v : mword 64) -: Minterrupts := - {| Minterrupts_Minterrupts_chunk_0 := (subrange_vec_dec v 63 0) |}. - -Definition _get_Minterrupts_bits (v : Minterrupts) -: mword 64 := - subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 63 0. - -Definition _set_Minterrupts_bits (r_ref : register_ref regstate register_value Minterrupts) (v : mword 64) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Minterrupts_Minterrupts_chunk_0 := - (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} - : Minterrupts in - write_reg r_ref r - : M (unit). - -Definition _update_Minterrupts_bits (v : Minterrupts) (x : mword 64) -: Minterrupts := - {[ v with - Minterrupts_Minterrupts_chunk_0 := - (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. - -Definition _get_Minterrupts_MEI (v : Minterrupts) -: mword 1 := - subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 11 11. - -Definition _set_Minterrupts_MEI (r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Minterrupts_Minterrupts_chunk_0 := - (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 11 11 (subrange_vec_dec v 0 0)) ]} - : Minterrupts in - write_reg r_ref r - : M (unit). - -Definition _update_Minterrupts_MEI (v : Minterrupts) (x : mword 1) -: Minterrupts := - {[ v with - Minterrupts_Minterrupts_chunk_0 := - (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 11 11 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Minterrupts_SEI (v : Minterrupts) -: mword 1 := - subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 9 9. - -Definition _set_Minterrupts_SEI (r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Minterrupts_Minterrupts_chunk_0 := - (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 9 9 (subrange_vec_dec v 0 0)) ]} - : Minterrupts in - write_reg r_ref r - : M (unit). - -Definition _update_Minterrupts_SEI (v : Minterrupts) (x : mword 1) -: Minterrupts := - {[ v with - Minterrupts_Minterrupts_chunk_0 := - (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 9 9 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Minterrupts_UEI (v : Minterrupts) -: mword 1 := - subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 8 8. - -Definition _set_Minterrupts_UEI (r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Minterrupts_Minterrupts_chunk_0 := - (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} - : Minterrupts in - write_reg r_ref r - : M (unit). - -Definition _update_Minterrupts_UEI (v : Minterrupts) (x : mword 1) -: Minterrupts := - {[ v with - Minterrupts_Minterrupts_chunk_0 := - (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Minterrupts_MTI (v : Minterrupts) -: mword 1 := - subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 7 7. - -Definition _set_Minterrupts_MTI (r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Minterrupts_Minterrupts_chunk_0 := - (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} - : Minterrupts in - write_reg r_ref r - : M (unit). - -Definition _update_Minterrupts_MTI (v : Minterrupts) (x : mword 1) -: Minterrupts := - {[ v with - Minterrupts_Minterrupts_chunk_0 := - (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Minterrupts_STI (v : Minterrupts) -: mword 1 := - subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 5 5. - -Definition _set_Minterrupts_STI (r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Minterrupts_Minterrupts_chunk_0 := - (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} - : Minterrupts in - write_reg r_ref r - : M (unit). - -Definition _update_Minterrupts_STI (v : Minterrupts) (x : mword 1) -: Minterrupts := - {[ v with - Minterrupts_Minterrupts_chunk_0 := - (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Minterrupts_UTI (v : Minterrupts) -: mword 1 := - subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 4 4. - -Definition _set_Minterrupts_UTI (r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Minterrupts_Minterrupts_chunk_0 := - (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} - : Minterrupts in - write_reg r_ref r - : M (unit). - -Definition _update_Minterrupts_UTI (v : Minterrupts) (x : mword 1) -: Minterrupts := - {[ v with - Minterrupts_Minterrupts_chunk_0 := - (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Minterrupts_MSI (v : Minterrupts) -: mword 1 := - subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 3 3. - -Definition _set_Minterrupts_MSI (r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Minterrupts_Minterrupts_chunk_0 := - (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]} - : Minterrupts in - write_reg r_ref r - : M (unit). - -Definition _update_Minterrupts_MSI (v : Minterrupts) (x : mword 1) -: Minterrupts := - {[ v with - Minterrupts_Minterrupts_chunk_0 := - (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Minterrupts_SSI (v : Minterrupts) -: mword 1 := - subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 1 1. - -Definition _set_Minterrupts_SSI (r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Minterrupts_Minterrupts_chunk_0 := - (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} - : Minterrupts in - write_reg r_ref r - : M (unit). - -Definition _update_Minterrupts_SSI (v : Minterrupts) (x : mword 1) -: Minterrupts := - {[ v with - Minterrupts_Minterrupts_chunk_0 := - (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Minterrupts_USI (v : Minterrupts) -: mword 1 := - subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 0 0. - -Definition _set_Minterrupts_USI (r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Minterrupts_Minterrupts_chunk_0 := - (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} - : Minterrupts in - write_reg r_ref r - : M (unit). - -Definition _update_Minterrupts_USI (v : Minterrupts) (x : mword 1) -: Minterrupts := - {[ v with - Minterrupts_Minterrupts_chunk_0 := - (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. - -Definition legalize_mip (o : Minterrupts) (v : mword 64) -: Minterrupts := - let v := Mk_Minterrupts v in - let m := _update_Minterrupts_SEI o (_get_Minterrupts_SEI v) in - let m := _update_Minterrupts_STI m (_get_Minterrupts_STI v) in - _update_Minterrupts_SSI m (_get_Minterrupts_SSI v). - -Definition legalize_mie (o : Minterrupts) (v : mword 64) -: Minterrupts := - let v := Mk_Minterrupts v in - let m := _update_Minterrupts_MEI o (_get_Minterrupts_MEI v) in - let m := _update_Minterrupts_MTI m (_get_Minterrupts_MTI v) in - let m := _update_Minterrupts_MSI m (_get_Minterrupts_MSI v) in - let m := _update_Minterrupts_SEI m (_get_Minterrupts_SEI v) in - let m := _update_Minterrupts_STI m (_get_Minterrupts_STI v) in - _update_Minterrupts_SSI m (_get_Minterrupts_SSI v). - -Definition legalize_mideleg (o : Minterrupts) (v : mword 64) -: Minterrupts := - let m := Mk_Minterrupts v in - let m := _update_Minterrupts_MEI m ((bool_to_bits false) : mword 1) in - let m := _update_Minterrupts_MTI m ((bool_to_bits false) : mword 1) in - _update_Minterrupts_MSI m ((bool_to_bits false) : mword 1). - -Definition Mk_Medeleg (v : mword 64) -: Medeleg := - {| Medeleg_Medeleg_chunk_0 := (subrange_vec_dec v 63 0) |}. - -Definition _get_Medeleg_bits (v : Medeleg) -: mword 64 := - subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 63 0. - -Definition _set_Medeleg_bits (r_ref : register_ref regstate register_value Medeleg) (v : mword 64) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} - : Medeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Medeleg_bits (v : Medeleg) (x : mword 64) -: Medeleg := - {[ v with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. - -Definition _get_Medeleg_SAMO_Page_Fault (v : Medeleg) -: mword 1 := - subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 15 15. - -Definition _set_Medeleg_SAMO_Page_Fault (r_ref : register_ref regstate register_value Medeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 15 15 (subrange_vec_dec v 0 0)) ]} - : Medeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Medeleg_SAMO_Page_Fault (v : Medeleg) (x : mword 1) -: Medeleg := - {[ v with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 15 15 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Medeleg_Load_Page_Fault (v : Medeleg) -: mword 1 := - subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 13 13. - -Definition _set_Medeleg_Load_Page_Fault (r_ref : register_ref regstate register_value Medeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 13 13 (subrange_vec_dec v 0 0)) ]} - : Medeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Medeleg_Load_Page_Fault (v : Medeleg) (x : mword 1) -: Medeleg := - {[ v with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 13 13 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Medeleg_Fetch_Page_Fault (v : Medeleg) -: mword 1 := - subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 12 12. - -Definition _set_Medeleg_Fetch_Page_Fault (r_ref : register_ref regstate register_value Medeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 12 12 (subrange_vec_dec v 0 0)) ]} - : Medeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Medeleg_Fetch_Page_Fault (v : Medeleg) (x : mword 1) -: Medeleg := - {[ v with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 12 12 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Medeleg_MEnvCall (v : Medeleg) -: mword 1 := - subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 10 10. - -Definition _set_Medeleg_MEnvCall (r_ref : register_ref regstate register_value Medeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 10 10 (subrange_vec_dec v 0 0)) ]} - : Medeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Medeleg_MEnvCall (v : Medeleg) (x : mword 1) -: Medeleg := - {[ v with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 10 10 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Medeleg_SEnvCall (v : Medeleg) -: mword 1 := - subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 9 9. - -Definition _set_Medeleg_SEnvCall (r_ref : register_ref regstate register_value Medeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 9 9 (subrange_vec_dec v 0 0)) ]} - : Medeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Medeleg_SEnvCall (v : Medeleg) (x : mword 1) -: Medeleg := - {[ v with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 9 9 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Medeleg_UEnvCall (v : Medeleg) -: mword 1 := - subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 8 8. - -Definition _set_Medeleg_UEnvCall (r_ref : register_ref regstate register_value Medeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} - : Medeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Medeleg_UEnvCall (v : Medeleg) (x : mword 1) -: Medeleg := - {[ v with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Medeleg_SAMO_Access_Fault (v : Medeleg) -: mword 1 := - subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 7 7. - -Definition _set_Medeleg_SAMO_Access_Fault (r_ref : register_ref regstate register_value Medeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} - : Medeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Medeleg_SAMO_Access_Fault (v : Medeleg) (x : mword 1) -: Medeleg := - {[ v with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Medeleg_SAMO_Addr_Align (v : Medeleg) -: mword 1 := - subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 6 6. - -Definition _set_Medeleg_SAMO_Addr_Align (r_ref : register_ref regstate register_value Medeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]} - : Medeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Medeleg_SAMO_Addr_Align (v : Medeleg) (x : mword 1) -: Medeleg := - {[ v with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Medeleg_Load_Access_Fault (v : Medeleg) -: mword 1 := - subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 5 5. - -Definition _set_Medeleg_Load_Access_Fault (r_ref : register_ref regstate register_value Medeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} - : Medeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Medeleg_Load_Access_Fault (v : Medeleg) (x : mword 1) -: Medeleg := - {[ v with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Medeleg_Load_Addr_Align (v : Medeleg) -: mword 1 := - subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 4 4. - -Definition _set_Medeleg_Load_Addr_Align (r_ref : register_ref regstate register_value Medeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} - : Medeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Medeleg_Load_Addr_Align (v : Medeleg) (x : mword 1) -: Medeleg := - {[ v with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Medeleg_Breakpoint (v : Medeleg) -: mword 1 := - subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 3 3. - -Definition _set_Medeleg_Breakpoint (r_ref : register_ref regstate register_value Medeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]} - : Medeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Medeleg_Breakpoint (v : Medeleg) (x : mword 1) -: Medeleg := - {[ v with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Medeleg_Illegal_Instr (v : Medeleg) -: mword 1 := - subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 2 2. - -Definition _set_Medeleg_Illegal_Instr (r_ref : register_ref regstate register_value Medeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]} - : Medeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Medeleg_Illegal_Instr (v : Medeleg) (x : mword 1) -: Medeleg := - {[ v with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Medeleg_Fetch_Access_Fault (v : Medeleg) -: mword 1 := - subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 1 1. - -Definition _set_Medeleg_Fetch_Access_Fault (r_ref : register_ref regstate register_value Medeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} - : Medeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Medeleg_Fetch_Access_Fault (v : Medeleg) (x : mword 1) -: Medeleg := - {[ v with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Medeleg_Fetch_Addr_Align (v : Medeleg) -: mword 1 := - subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 0 0. - -Definition _set_Medeleg_Fetch_Addr_Align (r_ref : register_ref regstate register_value Medeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} - : Medeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Medeleg_Fetch_Addr_Align (v : Medeleg) (x : mword 1) -: Medeleg := - {[ v with - Medeleg_Medeleg_chunk_0 := - (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. - -Definition legalize_medeleg (o : Medeleg) (v : mword 64) -: Medeleg := - let m := Mk_Medeleg v in - _update_Medeleg_MEnvCall m ((bool_to_bits false) : mword 1). - -Definition Mk_Mtvec (v : mword 64) -: Mtvec := - {| Mtvec_Mtvec_chunk_0 := (subrange_vec_dec v 63 0) |}. - -Definition _get_Mtvec_bits (v : Mtvec) : mword 64 := subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 63 0. - -Definition _set_Mtvec_bits (r_ref : register_ref regstate register_value Mtvec) (v : mword 64) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mtvec_Mtvec_chunk_0 := - (update_subrange_vec_dec r.(Mtvec_Mtvec_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} - : Mtvec in - write_reg r_ref r - : M (unit). - -Definition _update_Mtvec_bits (v : Mtvec) (x : mword 64) -: Mtvec := - {[ v with - Mtvec_Mtvec_chunk_0 := - (update_subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. - -Definition _get_Mtvec_Base (v : Mtvec) : mword 62 := subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 63 2. - -Definition _set_Mtvec_Base (r_ref : register_ref regstate register_value Mtvec) (v : mword 62) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mtvec_Mtvec_chunk_0 := - (update_subrange_vec_dec r.(Mtvec_Mtvec_chunk_0) 63 2 (subrange_vec_dec v 61 0)) ]} - : Mtvec in - write_reg r_ref r - : M (unit). - -Definition _update_Mtvec_Base (v : Mtvec) (x : mword 62) -: Mtvec := - {[ v with - Mtvec_Mtvec_chunk_0 := - (update_subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 63 2 (subrange_vec_dec x 61 0)) ]}. - -Definition _get_Mtvec_Mode (v : Mtvec) : mword 2 := subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 1 0. - -Definition _set_Mtvec_Mode (r_ref : register_ref regstate register_value Mtvec) (v : mword 2) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mtvec_Mtvec_chunk_0 := - (update_subrange_vec_dec r.(Mtvec_Mtvec_chunk_0) 1 0 (subrange_vec_dec v 1 0)) ]} - : Mtvec in - write_reg r_ref r - : M (unit). - -Definition _update_Mtvec_Mode (v : Mtvec) (x : mword 2) -: Mtvec := - {[ v with - Mtvec_Mtvec_chunk_0 := - (update_subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 1 0 (subrange_vec_dec x 1 0)) ]}. - -Definition legalize_tvec (o : Mtvec) (v : mword 64) -: Mtvec := - let v := Mk_Mtvec v in - match (trapVectorMode_of_bits (_get_Mtvec_Mode v)) with - | TV_Direct => v - | TV_Vector => v - | _ => _update_Mtvec_Mode v (_get_Mtvec_Mode o) - end. - -Definition Mk_Mcause (v : mword 64) -: Mcause := - {| Mcause_Mcause_chunk_0 := (subrange_vec_dec v 63 0) |}. - -Definition _get_Mcause_bits (v : Mcause) -: mword 64 := - subrange_vec_dec v.(Mcause_Mcause_chunk_0) 63 0. - -Definition _set_Mcause_bits (r_ref : register_ref regstate register_value Mcause) (v : mword 64) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mcause_Mcause_chunk_0 := - (update_subrange_vec_dec r.(Mcause_Mcause_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} - : Mcause in - write_reg r_ref r - : M (unit). - -Definition _update_Mcause_bits (v : Mcause) (x : mword 64) -: Mcause := - {[ v with - Mcause_Mcause_chunk_0 := - (update_subrange_vec_dec v.(Mcause_Mcause_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. - -Definition _get_Mcause_IsInterrupt (v : Mcause) -: mword 1 := - subrange_vec_dec v.(Mcause_Mcause_chunk_0) 63 63. - -Definition _set_Mcause_IsInterrupt (r_ref : register_ref regstate register_value Mcause) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mcause_Mcause_chunk_0 := - (update_subrange_vec_dec r.(Mcause_Mcause_chunk_0) 63 63 (subrange_vec_dec v 0 0)) ]} - : Mcause in - write_reg r_ref r - : M (unit). - -Definition _update_Mcause_IsInterrupt (v : Mcause) (x : mword 1) -: Mcause := - {[ v with - Mcause_Mcause_chunk_0 := - (update_subrange_vec_dec v.(Mcause_Mcause_chunk_0) 63 63 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Mcause_Cause (v : Mcause) -: mword 63 := - subrange_vec_dec v.(Mcause_Mcause_chunk_0) 62 0. - -Definition _set_Mcause_Cause (r_ref : register_ref regstate register_value Mcause) (v : mword 63) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Mcause_Mcause_chunk_0 := - (update_subrange_vec_dec r.(Mcause_Mcause_chunk_0) 62 0 (subrange_vec_dec v 62 0)) ]} - : Mcause in - write_reg r_ref r - : M (unit). - -Definition _update_Mcause_Cause (v : Mcause) (x : mword 63) -: Mcause := - {[ v with - Mcause_Mcause_chunk_0 := - (update_subrange_vec_dec v.(Mcause_Mcause_chunk_0) 62 0 (subrange_vec_dec x 62 0)) ]}. - -Definition tvec_addr (m : Mtvec) (c : Mcause) -: option (mword 64) := - let base : xlenbits := concat_vec (_get_Mtvec_Base m) (vec_of_bits [B0;B0] : mword 2) in - match (trapVectorMode_of_bits (_get_Mtvec_Mode m)) with - | TV_Direct => Some (base) - | TV_Vector => - if ((eq_vec (_get_Mcause_IsInterrupt c) ((bool_to_bits true) : mword 1))) then - Some - (add_vec base - (shift_bits_left (EXTZ 64 (_get_Mcause_Cause c)) (vec_of_bits [B1;B0] : mword 2))) - else Some (base) - | TV_Reserved => None - end. - -Definition legalize_xepc (v : mword 64) -: M (mword 64) := - haveRVC tt >>= fun w__0 : bool => - returnm ((and_vec v - (EXTS 64 - (if (w__0) then (vec_of_bits [B1;B1;B0] : mword 3) - else (vec_of_bits [B1;B0;B0] : mword 3)))) - : mword 64). - -Definition pc_alignment_mask '(tt : unit) -: M (mword 64) := - read_reg misa_ref >>= fun w__0 : Misa => - returnm ((not_vec - (EXTZ 64 - (if ((eq_vec (_get_Misa_C w__0) ((bool_to_bits true) : mword 1))) then - (vec_of_bits [B0;B0] : mword 2) - else (vec_of_bits [B1;B0] : mword 2)))) - : mword 64). - -Definition Mk_Counteren (v : mword 32) -: Counteren := - {| Counteren_Counteren_chunk_0 := (subrange_vec_dec v 31 0) |}. - -Definition _get_Counteren_bits (v : Counteren) -: mword 32 := - subrange_vec_dec v.(Counteren_Counteren_chunk_0) 31 0. - -Definition _set_Counteren_bits (r_ref : register_ref regstate register_value Counteren) (v : mword 32) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Counteren_Counteren_chunk_0 := - (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]} - : Counteren in - write_reg r_ref r - : M (unit). - -Definition _update_Counteren_bits (v : Counteren) (x : mword 32) -: Counteren := - {[ v with - Counteren_Counteren_chunk_0 := - (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}. - -Definition _get_Counteren_HPM (v : Counteren) -: mword 29 := - subrange_vec_dec v.(Counteren_Counteren_chunk_0) 31 3. - -Definition _set_Counteren_HPM (r_ref : register_ref regstate register_value Counteren) (v : mword 29) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Counteren_Counteren_chunk_0 := - (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 31 3 (subrange_vec_dec v 28 0)) ]} - : Counteren in - write_reg r_ref r - : M (unit). - -Definition _update_Counteren_HPM (v : Counteren) (x : mword 29) -: Counteren := - {[ v with - Counteren_Counteren_chunk_0 := - (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 31 3 (subrange_vec_dec x 28 0)) ]}. - -Definition _get_Counteren_IR (v : Counteren) -: mword 1 := - subrange_vec_dec v.(Counteren_Counteren_chunk_0) 2 2. - -Definition _set_Counteren_IR (r_ref : register_ref regstate register_value Counteren) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Counteren_Counteren_chunk_0 := - (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]} - : Counteren in - write_reg r_ref r - : M (unit). - -Definition _update_Counteren_IR (v : Counteren) (x : mword 1) -: Counteren := - {[ v with - Counteren_Counteren_chunk_0 := - (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Counteren_TM (v : Counteren) -: mword 1 := - subrange_vec_dec v.(Counteren_Counteren_chunk_0) 1 1. - -Definition _set_Counteren_TM (r_ref : register_ref regstate register_value Counteren) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Counteren_Counteren_chunk_0 := - (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} - : Counteren in - write_reg r_ref r - : M (unit). - -Definition _update_Counteren_TM (v : Counteren) (x : mword 1) -: Counteren := - {[ v with - Counteren_Counteren_chunk_0 := - (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Counteren_CY (v : Counteren) -: mword 1 := - subrange_vec_dec v.(Counteren_Counteren_chunk_0) 0 0. - -Definition _set_Counteren_CY (r_ref : register_ref regstate register_value Counteren) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Counteren_Counteren_chunk_0 := - (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} - : Counteren in - write_reg r_ref r - : M (unit). - -Definition _update_Counteren_CY (v : Counteren) (x : mword 1) -: Counteren := - {[ v with - Counteren_Counteren_chunk_0 := - (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. - -Definition legalize_mcounteren (c : Counteren) (v : mword 64) -: M (Counteren) := - cast_unit_vec (access_vec_dec v 2) >>= fun w__0 : mword 1 => - let c := _update_Counteren_IR c (w__0 : mword 1) in - cast_unit_vec (access_vec_dec v 1) >>= fun w__1 : mword 1 => - let c := _update_Counteren_TM c (w__1 : mword 1) in - cast_unit_vec (access_vec_dec v 0) >>= fun w__2 : mword 1 => - let c := _update_Counteren_CY c (w__2 : mword 1) in - returnm (c - : Counteren). - -Definition legalize_scounteren (c : Counteren) (v : mword 64) -: M (Counteren) := - cast_unit_vec (access_vec_dec v 2) >>= fun w__0 : mword 1 => - let c := _update_Counteren_IR c (w__0 : mword 1) in - cast_unit_vec (access_vec_dec v 1) >>= fun w__1 : mword 1 => - let c := _update_Counteren_TM c (w__1 : mword 1) in - cast_unit_vec (access_vec_dec v 0) >>= fun w__2 : mword 1 => - let c := _update_Counteren_CY c (w__2 : mword 1) in - returnm (c - : Counteren). - -Definition retire_instruction '(tt : unit) -: M (unit) := - read_reg minstret_written_ref >>= fun w__0 : bool => - (if ((Bool.eqb w__0 true)) then write_reg minstret_written_ref false : M (unit) - else - (read_reg minstret_ref : M (mword 64)) >>= fun w__1 : xlenbits => - write_reg minstret_ref (add_vec_int w__1 1) - : M (unit)) - : M (unit). - -Definition Mk_Sstatus (v : mword 64) -: Sstatus := - {| Sstatus_Sstatus_chunk_0 := (subrange_vec_dec v 63 0) |}. - -Definition _get_Sstatus_bits (v : Sstatus) -: mword 64 := - subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 63 0. - -Definition _set_Sstatus_bits (r_ref : register_ref regstate register_value Sstatus) (v : mword 64) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} - : Sstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Sstatus_bits (v : Sstatus) (x : mword 64) -: Sstatus := - {[ v with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. - -Definition _get_Sstatus_SD (v : Sstatus) -: mword 1 := - subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 63 63. - -Definition _set_Sstatus_SD (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 63 63 (subrange_vec_dec v 0 0)) ]} - : Sstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Sstatus_SD (v : Sstatus) (x : mword 1) -: Sstatus := - {[ v with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 63 63 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Sstatus_UXL (v : Sstatus) -: mword 2 := - subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 33 32. - -Definition _set_Sstatus_UXL (r_ref : register_ref regstate register_value Sstatus) (v : mword 2) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 33 32 (subrange_vec_dec v 1 0)) ]} - : Sstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Sstatus_UXL (v : Sstatus) (x : mword 2) -: Sstatus := - {[ v with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 33 32 (subrange_vec_dec x 1 0)) ]}. - -Definition _get_Sstatus_MXR (v : Sstatus) -: mword 1 := - subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 19 19. - -Definition _set_Sstatus_MXR (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 19 19 (subrange_vec_dec v 0 0)) ]} - : Sstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Sstatus_MXR (v : Sstatus) (x : mword 1) -: Sstatus := - {[ v with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 19 19 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Sstatus_SUM (v : Sstatus) -: mword 1 := - subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 18 18. - -Definition _set_Sstatus_SUM (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 18 18 (subrange_vec_dec v 0 0)) ]} - : Sstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Sstatus_SUM (v : Sstatus) (x : mword 1) -: Sstatus := - {[ v with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 18 18 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Sstatus_XS (v : Sstatus) -: mword 2 := - subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 16 15. - -Definition _set_Sstatus_XS (r_ref : register_ref regstate register_value Sstatus) (v : mword 2) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 16 15 (subrange_vec_dec v 1 0)) ]} - : Sstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Sstatus_XS (v : Sstatus) (x : mword 2) -: Sstatus := - {[ v with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 16 15 (subrange_vec_dec x 1 0)) ]}. - -Definition _get_Sstatus_FS (v : Sstatus) -: mword 2 := - subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 14 13. - -Definition _set_Sstatus_FS (r_ref : register_ref regstate register_value Sstatus) (v : mword 2) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 14 13 (subrange_vec_dec v 1 0)) ]} - : Sstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Sstatus_FS (v : Sstatus) (x : mword 2) -: Sstatus := - {[ v with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 14 13 (subrange_vec_dec x 1 0)) ]}. - -Definition _get_Sstatus_SPP (v : Sstatus) -: mword 1 := - subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 8 8. - -Definition _set_Sstatus_SPP (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} - : Sstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Sstatus_SPP (v : Sstatus) (x : mword 1) -: Sstatus := - {[ v with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Sstatus_SPIE (v : Sstatus) -: mword 1 := - subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 5 5. - -Definition _set_Sstatus_SPIE (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} - : Sstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Sstatus_SPIE (v : Sstatus) (x : mword 1) -: Sstatus := - {[ v with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Sstatus_UPIE (v : Sstatus) -: mword 1 := - subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 4 4. - -Definition _set_Sstatus_UPIE (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} - : Sstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Sstatus_UPIE (v : Sstatus) (x : mword 1) -: Sstatus := - {[ v with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Sstatus_SIE (v : Sstatus) -: mword 1 := - subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 1 1. - -Definition _set_Sstatus_SIE (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} - : Sstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Sstatus_SIE (v : Sstatus) (x : mword 1) -: Sstatus := - {[ v with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Sstatus_UIE (v : Sstatus) -: mword 1 := - subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 0 0. - -Definition _set_Sstatus_UIE (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} - : Sstatus in - write_reg r_ref r - : M (unit). - -Definition _update_Sstatus_UIE (v : Sstatus) (x : mword 1) -: Sstatus := - {[ v with - Sstatus_Sstatus_chunk_0 := - (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. - -Definition lower_mstatus (m : Mstatus) -: Sstatus := - let s := Mk_Sstatus (EXTZ 64 (vec_of_bits [B0] : mword 1)) in - let s := _update_Sstatus_SD s (_get_Mstatus_SD m) in - let s := _update_Sstatus_UXL s (_get_Mstatus_UXL m) in - let s := _update_Sstatus_MXR s (_get_Mstatus_MXR m) in - let s := _update_Sstatus_SUM s (_get_Mstatus_SUM m) in - let s := _update_Sstatus_XS s (_get_Mstatus_XS m) in - let s := _update_Sstatus_FS s (_get_Mstatus_FS m) in - let s := _update_Sstatus_SPP s (_get_Mstatus_SPP m) in - let s := _update_Sstatus_SPIE s (_get_Mstatus_SPIE m) in - let s := _update_Sstatus_UPIE s (_get_Mstatus_UPIE m) in - let s := _update_Sstatus_SIE s (_get_Mstatus_SIE m) in - _update_Sstatus_UIE s (_get_Mstatus_UIE m). - -Definition lift_sstatus (m : Mstatus) (s : Sstatus) -: Mstatus := - let m := _update_Mstatus_SD m (_get_Sstatus_SD s) in - let m := _update_Mstatus_MXR m (_get_Sstatus_MXR s) in - let m := _update_Mstatus_SUM m (_get_Sstatus_SUM s) in - let m := _update_Mstatus_XS m (_get_Sstatus_XS s) in - let m := _update_Mstatus_FS m (_get_Sstatus_FS s) in - let m := _update_Mstatus_SPP m (_get_Sstatus_SPP s) in - let m := _update_Mstatus_SPIE m (_get_Sstatus_SPIE s) in - let m := _update_Mstatus_UPIE m (_get_Sstatus_UPIE s) in - let m := _update_Mstatus_SIE m (_get_Sstatus_SIE s) in - _update_Mstatus_UIE m (_get_Sstatus_UIE s). - -Definition legalize_sstatus (m : Mstatus) (v : mword 64) -: Mstatus := - lift_sstatus m (Mk_Sstatus v). - -Definition Mk_Sedeleg (v : mword 64) -: Sedeleg := - {| Sedeleg_Sedeleg_chunk_0 := (subrange_vec_dec v 63 0) |}. - -Definition _get_Sedeleg_bits (v : Sedeleg) -: mword 64 := - subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 63 0. - -Definition _set_Sedeleg_bits (r_ref : register_ref regstate register_value Sedeleg) (v : mword 64) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sedeleg_Sedeleg_chunk_0 := - (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} - : Sedeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Sedeleg_bits (v : Sedeleg) (x : mword 64) -: Sedeleg := - {[ v with - Sedeleg_Sedeleg_chunk_0 := - (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. - -Definition _get_Sedeleg_UEnvCall (v : Sedeleg) -: mword 1 := - subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 8 8. - -Definition _set_Sedeleg_UEnvCall (r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sedeleg_Sedeleg_chunk_0 := - (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} - : Sedeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Sedeleg_UEnvCall (v : Sedeleg) (x : mword 1) -: Sedeleg := - {[ v with - Sedeleg_Sedeleg_chunk_0 := - (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Sedeleg_SAMO_Access_Fault (v : Sedeleg) -: mword 1 := - subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 7 7. - -Definition _set_Sedeleg_SAMO_Access_Fault (r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sedeleg_Sedeleg_chunk_0 := - (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} - : Sedeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Sedeleg_SAMO_Access_Fault (v : Sedeleg) (x : mword 1) -: Sedeleg := - {[ v with - Sedeleg_Sedeleg_chunk_0 := - (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Sedeleg_SAMO_Addr_Align (v : Sedeleg) -: mword 1 := - subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 6 6. - -Definition _set_Sedeleg_SAMO_Addr_Align (r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sedeleg_Sedeleg_chunk_0 := - (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]} - : Sedeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Sedeleg_SAMO_Addr_Align (v : Sedeleg) (x : mword 1) -: Sedeleg := - {[ v with - Sedeleg_Sedeleg_chunk_0 := - (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Sedeleg_Load_Access_Fault (v : Sedeleg) -: mword 1 := - subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 5 5. - -Definition _set_Sedeleg_Load_Access_Fault (r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sedeleg_Sedeleg_chunk_0 := - (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} - : Sedeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Sedeleg_Load_Access_Fault (v : Sedeleg) (x : mword 1) -: Sedeleg := - {[ v with - Sedeleg_Sedeleg_chunk_0 := - (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Sedeleg_Load_Addr_Align (v : Sedeleg) -: mword 1 := - subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 4 4. - -Definition _set_Sedeleg_Load_Addr_Align (r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sedeleg_Sedeleg_chunk_0 := - (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} - : Sedeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Sedeleg_Load_Addr_Align (v : Sedeleg) (x : mword 1) -: Sedeleg := - {[ v with - Sedeleg_Sedeleg_chunk_0 := - (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Sedeleg_Breakpoint (v : Sedeleg) -: mword 1 := - subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 3 3. - -Definition _set_Sedeleg_Breakpoint (r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sedeleg_Sedeleg_chunk_0 := - (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]} - : Sedeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Sedeleg_Breakpoint (v : Sedeleg) (x : mword 1) -: Sedeleg := - {[ v with - Sedeleg_Sedeleg_chunk_0 := - (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Sedeleg_Illegal_Instr (v : Sedeleg) -: mword 1 := - subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 2 2. - -Definition _set_Sedeleg_Illegal_Instr (r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sedeleg_Sedeleg_chunk_0 := - (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]} - : Sedeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Sedeleg_Illegal_Instr (v : Sedeleg) (x : mword 1) -: Sedeleg := - {[ v with - Sedeleg_Sedeleg_chunk_0 := - (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Sedeleg_Fetch_Access_Fault (v : Sedeleg) -: mword 1 := - subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 1 1. - -Definition _set_Sedeleg_Fetch_Access_Fault (r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sedeleg_Sedeleg_chunk_0 := - (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} - : Sedeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Sedeleg_Fetch_Access_Fault (v : Sedeleg) (x : mword 1) -: Sedeleg := - {[ v with - Sedeleg_Sedeleg_chunk_0 := - (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Sedeleg_Fetch_Addr_Align (v : Sedeleg) -: mword 1 := - subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 0 0. - -Definition _set_Sedeleg_Fetch_Addr_Align (r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sedeleg_Sedeleg_chunk_0 := - (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} - : Sedeleg in - write_reg r_ref r - : M (unit). - -Definition _update_Sedeleg_Fetch_Addr_Align (v : Sedeleg) (x : mword 1) -: Sedeleg := - {[ v with - Sedeleg_Sedeleg_chunk_0 := - (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. - -Definition legalize_sedeleg (s : Sedeleg) (v : mword 64) -: Sedeleg := - Mk_Sedeleg (EXTZ 64 (subrange_vec_dec v 8 0)). - -Definition Mk_Sinterrupts (v : mword 64) -: Sinterrupts := - {| Sinterrupts_Sinterrupts_chunk_0 := (subrange_vec_dec v 63 0) |}. - -Definition _get_Sinterrupts_bits (v : Sinterrupts) -: mword 64 := - subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 63 0. - -Definition _set_Sinterrupts_bits (r_ref : register_ref regstate register_value Sinterrupts) (v : mword 64) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sinterrupts_Sinterrupts_chunk_0 := - (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} - : Sinterrupts in - write_reg r_ref r - : M (unit). - -Definition _update_Sinterrupts_bits (v : Sinterrupts) (x : mword 64) -: Sinterrupts := - {[ v with - Sinterrupts_Sinterrupts_chunk_0 := - (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. - -Definition _get_Sinterrupts_SEI (v : Sinterrupts) -: mword 1 := - subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 9 9. - -Definition _set_Sinterrupts_SEI (r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sinterrupts_Sinterrupts_chunk_0 := - (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 9 9 (subrange_vec_dec v 0 0)) ]} - : Sinterrupts in - write_reg r_ref r - : M (unit). - -Definition _update_Sinterrupts_SEI (v : Sinterrupts) (x : mword 1) -: Sinterrupts := - {[ v with - Sinterrupts_Sinterrupts_chunk_0 := - (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 9 9 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Sinterrupts_UEI (v : Sinterrupts) -: mword 1 := - subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 8 8. - -Definition _set_Sinterrupts_UEI (r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sinterrupts_Sinterrupts_chunk_0 := - (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} - : Sinterrupts in - write_reg r_ref r - : M (unit). - -Definition _update_Sinterrupts_UEI (v : Sinterrupts) (x : mword 1) -: Sinterrupts := - {[ v with - Sinterrupts_Sinterrupts_chunk_0 := - (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Sinterrupts_STI (v : Sinterrupts) -: mword 1 := - subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 5 5. - -Definition _set_Sinterrupts_STI (r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sinterrupts_Sinterrupts_chunk_0 := - (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} - : Sinterrupts in - write_reg r_ref r - : M (unit). - -Definition _update_Sinterrupts_STI (v : Sinterrupts) (x : mword 1) -: Sinterrupts := - {[ v with - Sinterrupts_Sinterrupts_chunk_0 := - (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Sinterrupts_UTI (v : Sinterrupts) -: mword 1 := - subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 4 4. - -Definition _set_Sinterrupts_UTI (r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sinterrupts_Sinterrupts_chunk_0 := - (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} - : Sinterrupts in - write_reg r_ref r - : M (unit). - -Definition _update_Sinterrupts_UTI (v : Sinterrupts) (x : mword 1) -: Sinterrupts := - {[ v with - Sinterrupts_Sinterrupts_chunk_0 := - (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Sinterrupts_SSI (v : Sinterrupts) -: mword 1 := - subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 1 1. - -Definition _set_Sinterrupts_SSI (r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sinterrupts_Sinterrupts_chunk_0 := - (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} - : Sinterrupts in - write_reg r_ref r - : M (unit). - -Definition _update_Sinterrupts_SSI (v : Sinterrupts) (x : mword 1) -: Sinterrupts := - {[ v with - Sinterrupts_Sinterrupts_chunk_0 := - (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_Sinterrupts_USI (v : Sinterrupts) -: mword 1 := - subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 0 0. - -Definition _set_Sinterrupts_USI (r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Sinterrupts_Sinterrupts_chunk_0 := - (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} - : Sinterrupts in - write_reg r_ref r - : M (unit). - -Definition _update_Sinterrupts_USI (v : Sinterrupts) (x : mword 1) -: Sinterrupts := - {[ v with - Sinterrupts_Sinterrupts_chunk_0 := - (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. - -Definition lower_mip (m : Minterrupts) (d : Minterrupts) -: Sinterrupts := - let s : Sinterrupts := Mk_Sinterrupts (EXTZ 64 (vec_of_bits [B0] : mword 1)) in - let s := _update_Sinterrupts_SEI s (and_vec (_get_Minterrupts_SEI m) (_get_Minterrupts_SEI d)) in - let s := _update_Sinterrupts_STI s (and_vec (_get_Minterrupts_STI m) (_get_Minterrupts_STI d)) in - let s := _update_Sinterrupts_SSI s (and_vec (_get_Minterrupts_SSI m) (_get_Minterrupts_SSI d)) in - let s := _update_Sinterrupts_UEI s (and_vec (_get_Minterrupts_UEI m) (_get_Minterrupts_UEI d)) in - let s := _update_Sinterrupts_UTI s (and_vec (_get_Minterrupts_UTI m) (_get_Minterrupts_UTI d)) in - _update_Sinterrupts_USI s (and_vec (_get_Minterrupts_USI m) (_get_Minterrupts_USI d)). - -Definition lower_mie (m : Minterrupts) (d : Minterrupts) -: Sinterrupts := - let s : Sinterrupts := Mk_Sinterrupts (EXTZ 64 (vec_of_bits [B0] : mword 1)) in - let s := _update_Sinterrupts_SEI s (and_vec (_get_Minterrupts_SEI m) (_get_Minterrupts_SEI d)) in - let s := _update_Sinterrupts_STI s (and_vec (_get_Minterrupts_STI m) (_get_Minterrupts_STI d)) in - let s := _update_Sinterrupts_SSI s (and_vec (_get_Minterrupts_SSI m) (_get_Minterrupts_SSI d)) in - let s := _update_Sinterrupts_UEI s (and_vec (_get_Minterrupts_UEI m) (_get_Minterrupts_UEI d)) in - let s := _update_Sinterrupts_UTI s (and_vec (_get_Minterrupts_UTI m) (_get_Minterrupts_UTI d)) in - _update_Sinterrupts_USI s (and_vec (_get_Minterrupts_USI m) (_get_Minterrupts_USI d)). - -Definition lift_sip (o : Minterrupts) (d : Minterrupts) (s : Sinterrupts) -: Minterrupts := - let m : Minterrupts := o in - let m := _update_Minterrupts_SSI m (and_vec (_get_Sinterrupts_SSI s) (_get_Minterrupts_SSI d)) in - let m := _update_Minterrupts_UEI m (and_vec (_get_Minterrupts_UEI m) (_get_Minterrupts_UEI d)) in - _update_Minterrupts_USI m (and_vec (_get_Minterrupts_USI m) (_get_Minterrupts_USI d)). - -Definition legalize_sip (m : Minterrupts) (d : Minterrupts) (v : mword 64) -: Minterrupts := - lift_sip m d (Mk_Sinterrupts v). - -Definition lift_sie (o : Minterrupts) (d : Minterrupts) (s : Sinterrupts) -: Minterrupts := - let m : Minterrupts := o in - let m := - if ((eq_vec (_get_Minterrupts_SEI d) ((bool_to_bits true) : mword 1))) then - _update_Minterrupts_SEI m (_get_Sinterrupts_SEI s) - else m in - let m := - if ((eq_vec (_get_Minterrupts_STI d) ((bool_to_bits true) : mword 1))) then - _update_Minterrupts_STI m (_get_Sinterrupts_STI s) - else m in - let m := - if ((eq_vec (_get_Minterrupts_SSI d) ((bool_to_bits true) : mword 1))) then - _update_Minterrupts_SSI m (_get_Sinterrupts_SSI s) - else m in - let m := - if ((eq_vec (_get_Minterrupts_UEI d) ((bool_to_bits true) : mword 1))) then - _update_Minterrupts_UEI m (_get_Sinterrupts_UEI s) - else m in - let m := - if ((eq_vec (_get_Minterrupts_UTI d) ((bool_to_bits true) : mword 1))) then - _update_Minterrupts_UTI m (_get_Sinterrupts_UTI s) - else m in - if ((eq_vec (_get_Minterrupts_USI d) ((bool_to_bits true) : mword 1))) then - _update_Minterrupts_USI m (_get_Sinterrupts_USI s) - else m. - -Definition legalize_sie (m : Minterrupts) (d : Minterrupts) (v : mword 64) -: Minterrupts := - lift_sie m d (Mk_Sinterrupts v). - -Definition Mk_Satp64 (v : mword 64) -: Satp64 := - {| Satp64_Satp64_chunk_0 := (subrange_vec_dec v 63 0) |}. - -Definition _get_Satp64_bits (v : Satp64) -: mword 64 := - subrange_vec_dec v.(Satp64_Satp64_chunk_0) 63 0. - -Definition _set_Satp64_bits (r_ref : register_ref regstate register_value Satp64) (v : mword 64) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Satp64_Satp64_chunk_0 := - (update_subrange_vec_dec r.(Satp64_Satp64_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} - : Satp64 in - write_reg r_ref r - : M (unit). - -Definition _update_Satp64_bits (v : Satp64) (x : mword 64) -: Satp64 := - {[ v with - Satp64_Satp64_chunk_0 := - (update_subrange_vec_dec v.(Satp64_Satp64_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. - -Definition _get_Satp64_Mode (v : Satp64) -: mword 4 := - subrange_vec_dec v.(Satp64_Satp64_chunk_0) 63 60. - -Definition _set_Satp64_Mode (r_ref : register_ref regstate register_value Satp64) (v : mword 4) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Satp64_Satp64_chunk_0 := - (update_subrange_vec_dec r.(Satp64_Satp64_chunk_0) 63 60 (subrange_vec_dec v 3 0)) ]} - : Satp64 in - write_reg r_ref r - : M (unit). - -Definition _update_Satp64_Mode (v : Satp64) (x : mword 4) -: Satp64 := - {[ v with - Satp64_Satp64_chunk_0 := - (update_subrange_vec_dec v.(Satp64_Satp64_chunk_0) 63 60 (subrange_vec_dec x 3 0)) ]}. - -Definition _get_Satp64_Asid (v : Satp64) -: mword 16 := - subrange_vec_dec v.(Satp64_Satp64_chunk_0) 59 44. - -Definition _set_Satp64_Asid (r_ref : register_ref regstate register_value Satp64) (v : mword 16) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Satp64_Satp64_chunk_0 := - (update_subrange_vec_dec r.(Satp64_Satp64_chunk_0) 59 44 (subrange_vec_dec v 15 0)) ]} - : Satp64 in - write_reg r_ref r - : M (unit). - -Definition _update_Satp64_Asid (v : Satp64) (x : mword 16) -: Satp64 := - {[ v with - Satp64_Satp64_chunk_0 := - (update_subrange_vec_dec v.(Satp64_Satp64_chunk_0) 59 44 (subrange_vec_dec x 15 0)) ]}. - -Definition _get_Satp64_PPN (v : Satp64) -: mword 44 := - subrange_vec_dec v.(Satp64_Satp64_chunk_0) 43 0. - -Definition _set_Satp64_PPN (r_ref : register_ref regstate register_value Satp64) (v : mword 44) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - Satp64_Satp64_chunk_0 := - (update_subrange_vec_dec r.(Satp64_Satp64_chunk_0) 43 0 (subrange_vec_dec v 43 0)) ]} - : Satp64 in - write_reg r_ref r - : M (unit). - -Definition _update_Satp64_PPN (v : Satp64) (x : mword 44) -: Satp64 := - {[ v with - Satp64_Satp64_chunk_0 := - (update_subrange_vec_dec v.(Satp64_Satp64_chunk_0) 43 0 (subrange_vec_dec x 43 0)) ]}. - -Definition legalize_satp (a : Architecture) (o : mword 64) (v : mword 64) -: mword 64 := - let s := Mk_Satp64 v in - match (satpMode_of_bits a (_get_Satp64_Mode s)) with - | None => o - | Some (Sv32) => o - | Some (_) => _get_Satp64_bits s - end. - -Definition csr_name (csr : mword 12) -: string := - let b__0 := csr in - if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then "ustatus" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then - "uie" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then - "utvec" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then - "fflags" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - "frm" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then - "fcsr" - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - "cycle" - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then - "time" - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - "instret" - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - "cycleh" - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then - "timeh" - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - "instreth" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - "sstatus" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - "sedeleg" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then - "sideleg" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then - "sie" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then - "stvec" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then - "scounteren" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then - "sscratch" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then - "sepc" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then - "scause" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then - "stval" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then - "sip" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - "satp" - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then - "mvendorid" - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then - "marchid" - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then - "mimpid" - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then - "mhartid" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - "mstatus" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then - "misa" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - "medeleg" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then - "mideleg" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then - "mie" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then - "mtvec" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then - "mcounteren" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then - "mscratch" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then - "mepc" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then - "mcause" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then - "mtval" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then - "mip" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then - "pmpcfg0" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then - "pmpaddr0" - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - "mcycle" - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - "minstret" - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - "mcycleh" - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - "minstreth" - else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then - "tselect" - else "UNKNOWN". - -Definition csr_name_map_forwards (arg_ : mword 12) -: string := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then "ustatus" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then - "uie" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then - "utvec" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then - "uscratch" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then - "uepc" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then - "ucause" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then - "utval" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then - "uip" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then - "fflags" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - "frm" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then - "fcsr" - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - "cycle" - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then - "time" - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - "instret" - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - "cycleh" - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then - "timeh" - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - "instreth" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - "sstatus" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - "sedeleg" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then - "sideleg" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then - "sie" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then - "stvec" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then - "scounteren" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then - "sscratch" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then - "sepc" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then - "scause" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then - "stval" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then - "sip" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - "satp" - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then - "mvendorid" - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then - "marchid" - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then - "mimpid" - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then - "mhartid" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - "mstatus" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then - "misa" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - "medeleg" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then - "mideleg" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then - "mie" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then - "mtvec" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then - "mcounteren" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then - "mscratch" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then - "mepc" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then - "mcause" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then - "mtval" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then - "mip" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then - "pmpcfg0" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then - "pmpcfg1" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then - "pmpcfg2" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12))) then - "pmpcfg3" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then - "pmpaddr0" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12))) then - "pmpaddr1" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12))) then - "pmpaddr2" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12))) then - "pmpaddr3" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12))) then - "pmpaddr4" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12))) then - "pmpaddr5" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12))) then - "pmpaddr6" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12))) then - "pmpaddr7" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12))) then - "pmpaddr8" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12))) then - "pmpaddr9" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12))) then - "pmpaddr10" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12))) then - "pmpaddr11" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12))) then - "pmpaddr12" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12))) then - "pmpaddr13" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12))) then - "pmpaddr14" - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12))) then - "pmpaddr15" - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - "mcycle" - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - "minstret" - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - "mcycleh" - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - "minstreth" - else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then - "tselect" - else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then - "tdata1" - else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then - "tdata2" - else "tdata3". - -Definition csr_name_map_backwards (arg_ : string) -: M (mword 12) := - (match arg_ with - | "ustatus" => - returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) : mword 12) - | "uie" => returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12) : mword 12) - | "utvec" => - returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12) : mword 12) - | "uscratch" => - returnm ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12) : mword 12) - | "uepc" => - returnm ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12) : mword 12) - | "ucause" => - returnm ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12) : mword 12) - | "utval" => - returnm ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12) : mword 12) - | "uip" => returnm ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12) : mword 12) - | "fflags" => - returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12) : mword 12) - | "frm" => returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12) : mword 12) - | "fcsr" => - returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) : mword 12) - | "cycle" => - returnm ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) : mword 12) - | "time" => - returnm ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12) : mword 12) - | "instret" => - returnm ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12) : mword 12) - | "cycleh" => - returnm ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) : mword 12) - | "timeh" => - returnm ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12) : mword 12) - | "instreth" => - returnm ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12) : mword 12) - | "sstatus" => - returnm ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) : mword 12) - | "sedeleg" => - returnm ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12) : mword 12) - | "sideleg" => - returnm ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) : mword 12) - | "sie" => returnm ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12) : mword 12) - | "stvec" => - returnm ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12) : mword 12) - | "scounteren" => - returnm ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12) : mword 12) - | "sscratch" => - returnm ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12) : mword 12) - | "sepc" => - returnm ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12) : mword 12) - | "scause" => - returnm ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12) : mword 12) - | "stval" => - returnm ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12) : mword 12) - | "sip" => returnm ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12) : mword 12) - | "satp" => - returnm ((vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) : mword 12) - | "mvendorid" => - returnm ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12) : mword 12) - | "marchid" => - returnm ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12) : mword 12) - | "mimpid" => - returnm ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12) : mword 12) - | "mhartid" => - returnm ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12) : mword 12) - | "mstatus" => - returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) : mword 12) - | "misa" => - returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12) : mword 12) - | "medeleg" => - returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12) : mword 12) - | "mideleg" => - returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) : mword 12) - | "mie" => returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12) : mword 12) - | "mtvec" => - returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12) : mword 12) - | "mcounteren" => - returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12) : mword 12) - | "mscratch" => - returnm ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12) : mword 12) - | "mepc" => - returnm ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12) : mword 12) - | "mcause" => - returnm ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12) : mword 12) - | "mtval" => - returnm ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12) : mword 12) - | "mip" => returnm ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12) : mword 12) - | "pmpcfg0" => - returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12) : mword 12) - | "pmpcfg1" => - returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12) : mword 12) - | "pmpcfg2" => - returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12) : mword 12) - | "pmpcfg3" => - returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12) : mword 12) - | "pmpaddr0" => - returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12) : mword 12) - | "pmpaddr1" => - returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12) : mword 12) - | "pmpaddr2" => - returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12) : mword 12) - | "pmpaddr3" => - returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12) : mword 12) - | "pmpaddr4" => - returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12) : mword 12) - | "pmpaddr5" => - returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12) : mword 12) - | "pmpaddr6" => - returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12) : mword 12) - | "pmpaddr7" => - returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12) : mword 12) - | "pmpaddr8" => - returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12) : mword 12) - | "pmpaddr9" => - returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12) : mword 12) - | "pmpaddr10" => - returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12) : mword 12) - | "pmpaddr11" => - returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12) : mword 12) - | "pmpaddr12" => - returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12) : mword 12) - | "pmpaddr13" => - returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12) : mword 12) - | "pmpaddr14" => - returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12) : mword 12) - | "pmpaddr15" => - returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12) : mword 12) - | "mcycle" => - returnm ((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) : mword 12) - | "minstret" => - returnm ((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12) : mword 12) - | "mcycleh" => - returnm ((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) : mword 12) - | "minstreth" => - returnm ((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12) : mword 12) - | "tselect" => - returnm ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12) : mword 12) - | "tdata1" => - returnm ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12) : mword 12) - | "tdata2" => - returnm ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12) : mword 12) - | "tdata3" => - returnm ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12) : mword 12) - | _ => exit tt : M (mword 12) - end) - : M (mword 12). - -Definition csr_name_map_forwards_matches (arg_ : mword 12) -: bool := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12))) then true - else false. - -Definition csr_name_map_backwards_matches (arg_ : string) -: bool := - match arg_ with - | "ustatus" => true - | "uie" => true - | "utvec" => true - | "uscratch" => true - | "uepc" => true - | "ucause" => true - | "utval" => true - | "uip" => true - | "fflags" => true - | "frm" => true - | "fcsr" => true - | "cycle" => true - | "time" => true - | "instret" => true - | "cycleh" => true - | "timeh" => true - | "instreth" => true - | "sstatus" => true - | "sedeleg" => true - | "sideleg" => true - | "sie" => true - | "stvec" => true - | "scounteren" => true - | "sscratch" => true - | "sepc" => true - | "scause" => true - | "stval" => true - | "sip" => true - | "satp" => true - | "mvendorid" => true - | "marchid" => true - | "mimpid" => true - | "mhartid" => true - | "mstatus" => true - | "misa" => true - | "medeleg" => true - | "mideleg" => true - | "mie" => true - | "mtvec" => true - | "mcounteren" => true - | "mscratch" => true - | "mepc" => true - | "mcause" => true - | "mtval" => true - | "mip" => true - | "pmpcfg0" => true - | "pmpcfg1" => true - | "pmpcfg2" => true - | "pmpcfg3" => true - | "pmpaddr0" => true - | "pmpaddr1" => true - | "pmpaddr2" => true - | "pmpaddr3" => true - | "pmpaddr4" => true - | "pmpaddr5" => true - | "pmpaddr6" => true - | "pmpaddr7" => true - | "pmpaddr8" => true - | "pmpaddr9" => true - | "pmpaddr10" => true - | "pmpaddr11" => true - | "pmpaddr12" => true - | "pmpaddr13" => true - | "pmpaddr14" => true - | "pmpaddr15" => true - | "mcycle" => true - | "minstret" => true - | "mcycleh" => true - | "minstreth" => true - | "tselect" => true - | "tdata1" => true - | "tdata2" => true - | "tdata3" => true - | _ => false - end. - -Definition csr_name_map_matches_prefix (arg_ : string) -: option ((mword 12 * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1227_ := arg_ in - if ((andb (string_startswith _stringappend_1227_ "ustatus") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "ustatus")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "ustatus")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "uie") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "uie")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "uie")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "utvec") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "utvec")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "utvec")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "uscratch") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "uscratch")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "uscratch")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "uepc") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "uepc")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "uepc")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "ucause") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "ucause")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "ucause")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "utval") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "utval")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "utval")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "uip") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "uip")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "uip")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "fflags") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "fflags")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "fflags")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "frm") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "frm")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "frm")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "fcsr") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "fcsr")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "fcsr")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "cycle") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "cycle")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "cycle")))) with - | s_ => - Some - (((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "time") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "time")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "time")))) with - | s_ => - Some - (((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "instret") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "instret")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "instret")))) with - | s_ => - Some - (((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "cycleh") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "cycleh")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "cycleh")))) with - | s_ => - Some - (((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "timeh") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "timeh")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "timeh")))) with - | s_ => - Some - (((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "instreth") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "instreth")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "instreth")))) with - | s_ => - Some - (((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "sstatus") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "sstatus")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "sstatus")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "sedeleg") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "sedeleg")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "sedeleg")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "sideleg") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "sideleg")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "sideleg")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "sie") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "sie")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "sie")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "stvec") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "stvec")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "stvec")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "scounteren") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "scounteren")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "scounteren")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "sscratch") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "sscratch")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "sscratch")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "sepc") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "sepc")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "sepc")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "scause") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "scause")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "scause")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "stval") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "stval")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "stval")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "sip") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "sip")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "sip")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "satp") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "satp")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "satp")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "mvendorid") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "mvendorid")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mvendorid")))) with - | s_ => - Some - (((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "marchid") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "marchid")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "marchid")))) with - | s_ => - Some - (((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "mimpid") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mimpid")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mimpid")))) with - | s_ => - Some - (((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "mhartid") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mhartid")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mhartid")))) with - | s_ => - Some - (((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "mstatus") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mstatus")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mstatus")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "misa") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "misa")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "misa")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "medeleg") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "medeleg")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "medeleg")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "mideleg") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mideleg")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mideleg")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "mie") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mie")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mie")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "mtvec") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mtvec")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mtvec")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "mcounteren") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "mcounteren")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mcounteren")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "mscratch") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "mscratch")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mscratch")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "mepc") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mepc")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mepc")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "mcause") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mcause")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mcause")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "mtval") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mtval")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mtval")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "mip") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mip")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mip")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "pmpcfg0") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpcfg0")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpcfg0")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "pmpcfg1") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpcfg1")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpcfg1")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "pmpcfg2") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpcfg2")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpcfg2")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "pmpcfg3") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpcfg3")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpcfg3")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "pmpaddr0") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "pmpaddr0")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpaddr0")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "pmpaddr1") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "pmpaddr1")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpaddr1")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "pmpaddr2") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "pmpaddr2")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpaddr2")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "pmpaddr3") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "pmpaddr3")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpaddr3")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "pmpaddr4") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "pmpaddr4")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpaddr4")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "pmpaddr5") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "pmpaddr5")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpaddr5")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "pmpaddr6") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "pmpaddr6")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpaddr6")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "pmpaddr7") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "pmpaddr7")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpaddr7")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "pmpaddr8") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "pmpaddr8")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpaddr8")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "pmpaddr9") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "pmpaddr9")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpaddr9")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "pmpaddr10") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "pmpaddr10")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpaddr10")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "pmpaddr11") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "pmpaddr11")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpaddr11")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "pmpaddr12") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "pmpaddr12")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpaddr12")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "pmpaddr13") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "pmpaddr13")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpaddr13")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "pmpaddr14") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "pmpaddr14")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpaddr14")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "pmpaddr15") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "pmpaddr15")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "pmpaddr15")))) with - | s_ => - Some - (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "mcycle") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mcycle")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mcycle")))) with - | s_ => - Some - (((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "minstret") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "minstret")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "minstret")))) with - | s_ => - Some - (((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "mcycleh") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mcycleh")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "mcycleh")))) with - | s_ => - Some - (((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "minstreth") - (match (string_drop _stringappend_1227_ - (build_ex (projT1 (string_length "minstreth")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "minstreth")))) with - | s_ => - Some - (((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "tselect") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "tselect")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "tselect")))) with - | s_ => - Some - (((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "tdata1") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "tdata1")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "tdata1")))) with - | s_ => - Some - (((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "tdata2") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "tdata2")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "tdata2")))) with - | s_ => - Some - (((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else if ((andb (string_startswith _stringappend_1227_ "tdata3") - (match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "tdata3")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1227_ (build_ex (projT1 (string_length "tdata3")))) with - | s_ => - Some - (((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end - else None. - -Definition csrAccess (csr : mword 12) : mword 2 := subrange_vec_dec csr 11 10. - -Definition csrPriv (csr : mword 12) : mword 2 := subrange_vec_dec csr 9 8. - -Definition is_CSR_defined (csr : mword 12) (p : Privilege) -: bool := - let b__0 := csr in - if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then - eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2) - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then - eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2) - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then - eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2) - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then - eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then - eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then - eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then - eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then - eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then - eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then - eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then - eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then - eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then - eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then - eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then - eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then - false - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - orb (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2)) - (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Supervisor) : mword 2)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - orb (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2)) - (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Supervisor) : mword 2)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then - orb (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2)) - (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Supervisor) : mword 2)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then - orb (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2)) - (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Supervisor) : mword 2)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then - orb (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2)) - (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Supervisor) : mword 2)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then - orb (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2)) - (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Supervisor) : mword 2)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then - orb (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2)) - (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Supervisor) : mword 2)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then - orb (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2)) - (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Supervisor) : mword 2)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then - orb (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2)) - (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Supervisor) : mword 2)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then - orb (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2)) - (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Supervisor) : mword 2)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then - orb (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2)) - (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Supervisor) : mword 2)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - orb (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2)) - (eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Supervisor) : mword 2)) - else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then - eq_vec ((privLevel_to_bits p) : mword 2) ((privLevel_to_bits Machine) : mword 2) - else false. - -Definition check_CSR_access (csrrw : mword 2) (csrpr : mword 2) (p : Privilege) (isWrite : bool) -: bool := - andb (negb (andb (Bool.eqb isWrite true) (eq_vec csrrw (vec_of_bits [B1;B1] : mword 2)))) - (zopz0zKzJ_u (privLevel_to_bits p) csrpr). - -Definition check_TVM_SATP (csr : mword 12) (p : Privilege) -: M (bool) := - and_boolM - (returnm ((eq_vec csr (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12)) - : bool)) - ((and_boolM - (returnm ((eq_vec ((privLevel_to_bits p) : mword 2) - ((privLevel_to_bits Supervisor) - : mword 2)) - : bool)) - (read_reg mstatus_ref >>= fun w__0 : Mstatus => - returnm ((eq_vec (_get_Mstatus_TVM w__0) ((bool_to_bits true) : mword 1)) - : bool))) - : M (bool)) >>= fun w__2 : bool => - returnm ((negb w__2) - : bool). - -Definition check_Counteren (csr : mword 12) (p : Privilege) -: M (bool) := - (match (csr, p) with - | (b__0, Supervisor) => - (if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - read_reg mcounteren_ref >>= fun w__0 : Counteren => - returnm ((eq_vec (_get_Counteren_CY w__0) ((bool_to_bits true) : mword 1)) - : bool) - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then - read_reg mcounteren_ref >>= fun w__1 : Counteren => - returnm ((eq_vec (_get_Counteren_TM w__1) ((bool_to_bits true) : mword 1)) - : bool) - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - read_reg mcounteren_ref >>= fun w__2 : Counteren => - returnm ((eq_vec (_get_Counteren_IR w__2) ((bool_to_bits true) : mword 1)) - : bool) - else - returnm ((match (b__0, Supervisor) with - | (g__17, g__18) => - if ((andb - (zopz0zIzJ_u - (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) csr) - (zopz0zIzJ_u csr - (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : mword 12)))) - then - false - else true - end) - : bool)) - : M (bool) - | (b__3, User) => - (if ((eq_vec b__3 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - read_reg scounteren_ref >>= fun w__6 : Counteren => - returnm ((eq_vec (_get_Counteren_CY w__6) ((bool_to_bits true) : mword 1)) - : bool) - else if ((eq_vec b__3 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then - read_reg scounteren_ref >>= fun w__7 : Counteren => - returnm ((eq_vec (_get_Counteren_TM w__7) ((bool_to_bits true) : mword 1)) - : bool) - else if ((eq_vec b__3 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - read_reg scounteren_ref >>= fun w__8 : Counteren => - returnm ((eq_vec (_get_Counteren_IR w__8) ((bool_to_bits true) : mword 1)) - : bool) - else - returnm ((match (b__3, User) with - | (g__17, g__18) => - if ((andb - (zopz0zIzJ_u - (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) csr) - (zopz0zIzJ_u csr - (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : mword 12)))) - then - false - else true - end) - : bool)) - : M (bool) - | (g__17, g__18) => - returnm ((if ((andb - (zopz0zIzJ_u (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) - csr) - (zopz0zIzJ_u csr - (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : mword 12)))) then - false - else true) - : bool) - end) - : M (bool). - -Definition check_CSR (csr : mword 12) (p : Privilege) (isWrite : bool) -: M (bool) := - (and_boolM (returnm ((is_CSR_defined csr p) : bool)) - ((and_boolM (returnm ((check_CSR_access (csrAccess csr) (csrPriv csr) p isWrite) : bool)) - ((and_boolM ((check_TVM_SATP csr p) : M (bool)) ((check_Counteren csr p) : M (bool))) - : M (bool))) - : M (bool))) - : M (bool). - -Axiom load_reservation : forall (_ : xlenbits) , unit. - -Axiom match_reservation : forall (_ : xlenbits) , M (bool). - -Axiom cancel_reservation : forall (_ : unit) , unit. - -Definition exception_delegatee (e : ExceptionType) (p : Privilege) -: M (Privilege) := - let 'idx := projT1 (num_of_ExceptionType e) in - read_reg medeleg_ref >>= fun w__0 : Medeleg => - let super := access_vec_dec (_get_Medeleg_bits w__0) idx in - read_reg sedeleg_ref >>= fun w__1 : Sedeleg => - let user := access_vec_dec (_get_Sedeleg_bits w__1) idx in - and_boolM - (read_reg misa_ref >>= fun w__2 : Misa => - returnm ((eq_vec (_get_Misa_S w__2) ((bool_to_bits true) : mword 1)) - : bool)) ((bit_to_bool super) : M (bool)) >>= fun w__4 : bool => - let deleg := if (w__4) then Supervisor else Machine in - returnm ((if ((zopz0zI_u (privLevel_to_bits deleg) (privLevel_to_bits p))) then p - else deleg) - : Privilege). - -Definition findPendingInterrupt (ip : mword 64) -: option InterruptType := - let ip := Mk_Minterrupts ip in - if ((eq_vec (_get_Minterrupts_MEI ip) ((bool_to_bits true) : mword 1))) then Some (I_M_External) - else if ((eq_vec (_get_Minterrupts_MSI ip) ((bool_to_bits true) : mword 1))) then - Some - (I_M_Software) - else if ((eq_vec (_get_Minterrupts_MTI ip) ((bool_to_bits true) : mword 1))) then - Some - (I_M_Timer) - else if ((eq_vec (_get_Minterrupts_SEI ip) ((bool_to_bits true) : mword 1))) then - Some - (I_S_External) - else if ((eq_vec (_get_Minterrupts_SSI ip) ((bool_to_bits true) : mword 1))) then - Some - (I_S_Software) - else if ((eq_vec (_get_Minterrupts_STI ip) ((bool_to_bits true) : mword 1))) then - Some - (I_S_Timer) - else if ((eq_vec (_get_Minterrupts_UEI ip) ((bool_to_bits true) : mword 1))) then - Some - (I_U_External) - else if ((eq_vec (_get_Minterrupts_USI ip) ((bool_to_bits true) : mword 1))) then - Some - (I_U_Software) - else if ((eq_vec (_get_Minterrupts_UTI ip) ((bool_to_bits true) : mword 1))) then - Some - (I_U_Timer) - else None. - -Definition curInterrupt (priv : Privilege) (pend : Minterrupts) (enbl : Minterrupts) (delg : Minterrupts) -: M (option ((InterruptType * Privilege))) := - let en_mip : xlenbits := and_vec (_get_Minterrupts_bits pend) (_get_Minterrupts_bits enbl) in - (if ((eq_vec en_mip (EXTZ 64 (vec_of_bits [B0] : mword 1)))) then - returnm (None - : option ((InterruptType * Privilege))) - else - or_boolM - (returnm ((neq_vec ((privLevel_to_bits priv) : mword 2) - ((privLevel_to_bits Machine) - : mword 2)) - : bool)) - ((and_boolM - (returnm ((eq_vec ((privLevel_to_bits priv) : mword 2) - ((privLevel_to_bits Machine) - : mword 2)) - : bool)) - (read_reg mstatus_ref >>= fun w__0 : Mstatus => - returnm ((eq_vec (_get_Mstatus_MIE w__0) ((bool_to_bits true) : mword 1)) - : bool))) - : M (bool)) >>= fun eff_mie => - or_boolM - (returnm ((eq_vec ((privLevel_to_bits priv) : mword 2) - ((privLevel_to_bits User) - : mword 2)) - : bool)) - ((and_boolM - (returnm ((eq_vec ((privLevel_to_bits priv) : mword 2) - ((privLevel_to_bits Supervisor) - : mword 2)) - : bool)) - (read_reg mstatus_ref >>= fun w__2 : Mstatus => - returnm ((eq_vec (_get_Mstatus_SIE w__2) ((bool_to_bits true) : mword 1)) - : bool))) - : M (bool)) >>= fun eff_sie => - let eff_mip := and_vec en_mip (not_vec (_get_Minterrupts_bits delg)) in - let eff_sip := and_vec en_mip (_get_Minterrupts_bits delg) in - (if ((andb eff_mie (neq_vec eff_mip (EXTZ 64 (vec_of_bits [B0] : mword 1))))) then - (match (findPendingInterrupt eff_mip) with - | Some (i) => - let r := (i, Machine) in - returnm ((Some - (r)) - : option ((InterruptType * Privilege))) - | None => - (internal_error - (String.append "non-zero eff_mip=" - (String.append (string_of_bits eff_mip) ", but nothing pending"))) - : M (option ((InterruptType * Privilege))) - end) - : M (option ((InterruptType * Privilege))) - else if ((andb eff_sie (neq_vec eff_sip (EXTZ 64 (vec_of_bits [B0] : mword 1))))) then - (match (findPendingInterrupt eff_sip) with - | Some (i) => - let r := (i, Supervisor) in - returnm ((Some - (r)) - : option ((InterruptType * Privilege))) - | None => - (internal_error - (String.append "non-zero eff_sip=" - (String.append (string_of_bits eff_sip) ", but nothing pending"))) - : M (option ((InterruptType * Privilege))) - end) - : M (option ((InterruptType * Privilege))) - else - let p := - if ((eq_vec (_get_Minterrupts_MTI pend) ((bool_to_bits true) : mword 1))) then "1" - else "0" in - let e := - if ((eq_vec (_get_Minterrupts_MTI enbl) ((bool_to_bits true) : mword 1))) then "1" - else "0" in - let d := - if ((eq_vec (_get_Minterrupts_MTI delg) ((bool_to_bits true) : mword 1))) then "1" - else "0" in - let '_ := - (print_endline - (String.append " MTI: pend=" - (String.append p - (String.append " enbl=" (String.append e (String.append " delg=" d)))))) - : unit in - let eff_mip := and_vec en_mip (not_vec (_get_Minterrupts_bits delg)) in - let eff_sip := and_vec en_mip (_get_Minterrupts_bits delg) in - read_reg mstatus_ref >>= fun w__8 : Mstatus => - read_reg mstatus_ref >>= fun w__9 : Mstatus => - read_reg mstatus_ref >>= fun w__10 : Mstatus => - let '_ := - (print_endline - (String.append "mstatus=" - (String.append (string_of_bits (_get_Mstatus_bits w__8)) - (String.append " mie,sie=" - (String.append (string_of_bits (_get_Mstatus_MIE w__9)) - (String.append "," - (String.append (string_of_bits (_get_Mstatus_SIE w__10)) - (String.append " en_mip=" - (String.append (string_of_bits en_mip) - (String.append " eff_mip=" - (String.append (string_of_bits eff_mip) - (String.append " eff_sip=" (string_of_bits eff_sip))))))))))))) - : unit in - returnm (None - : option ((InterruptType * Privilege)))) - : M (option ((InterruptType * Privilege)))) - : M (option ((InterruptType * Privilege))). - -Definition tval (excinfo : option (mword 64)) -: mword 64 := - match excinfo with | Some (e) => e | None => EXTZ 64 (vec_of_bits [B0] : mword 1) end. - -Definition handle_trap (del_priv : Privilege) (intr : bool) (c : mword 4) (pc : mword 64) (info : option (mword 64)) -: M (mword 64) := - let '_ := - (print_endline - (String.append "handling " - (String.append (if (intr) then "int#" else "exc#") - (String.append (string_of_bits c) - (String.append " at priv " - (String.append ((privLevel_to_str del_priv) : string) - (String.append " with tval " (string_of_bits (tval info))))))))) - : unit in - (match del_priv with - | Machine => - _set_Mcause_IsInterrupt mcause_ref ((bool_to_bits intr) : mword 1) >> - _set_Mcause_Cause mcause_ref (EXTZ 63 c) >> - read_reg mstatus_ref >>= fun w__0 : Mstatus => - _set_Mstatus_MPIE mstatus_ref (_get_Mstatus_MIE w__0) >> - _set_Mstatus_MIE mstatus_ref ((bool_to_bits false) : mword 1) >> - read_reg cur_privilege_ref >>= fun w__1 : Privilege => - _set_Mstatus_MPP mstatus_ref (privLevel_to_bits w__1) >> - write_reg mtval_ref (tval info) >> - write_reg mepc_ref pc >> - write_reg cur_privilege_ref del_priv >> - read_reg mstatus_ref >>= fun w__2 : Mstatus => - read_reg mstatus_ref >>= fun w__3 : Mstatus => - let '_ := - (print_endline - (String.append "CSR mstatus <- " - (String.append (string_of_bits (_get_Mstatus_bits w__2)) - (String.append " (input: " - (String.append (string_of_bits (_get_Mstatus_bits w__3)) ")"))))) - : unit in - let '_ := (cancel_reservation tt) : unit in - read_reg mtvec_ref >>= fun w__4 : Mtvec => - read_reg mcause_ref >>= fun w__5 : Mcause => - (match (tvec_addr w__4 w__5) with - | Some (epc) => returnm (epc : mword 64) - | None => (internal_error "Invalid mtvec mode") : M (mword 64) - end) - : M (mword 64) - | Supervisor => - _set_Mcause_IsInterrupt scause_ref ((bool_to_bits intr) : mword 1) >> - _set_Mcause_Cause scause_ref (EXTZ 63 c) >> - read_reg mstatus_ref >>= fun w__8 : Mstatus => - _set_Mstatus_SPIE mstatus_ref (_get_Mstatus_SIE w__8) >> - _set_Mstatus_SIE mstatus_ref ((bool_to_bits false) : mword 1) >> - read_reg cur_privilege_ref >>= fun w__9 : Privilege => - match w__9 with - | User => returnm ((bool_to_bits false) : mword 1) - | Supervisor => returnm ((bool_to_bits true) : mword 1) - | Machine => (internal_error "invalid privilege for s-mode trap") : M (mword 1) - end >>= fun w__11 : mword 1 => - _set_Mstatus_SPP mstatus_ref w__11 >> - write_reg stval_ref (tval info) >> - write_reg sepc_ref pc >> - write_reg cur_privilege_ref del_priv >> - read_reg mstatus_ref >>= fun w__12 : Mstatus => - read_reg mstatus_ref >>= fun w__13 : Mstatus => - let '_ := - (print_endline - (String.append "CSR mstatus <- " - (String.append (string_of_bits (_get_Mstatus_bits w__12)) - (String.append " (input: " - (String.append (string_of_bits (_get_Mstatus_bits w__13)) ")"))))) - : unit in - let '_ := (cancel_reservation tt) : unit in - read_reg stvec_ref >>= fun w__14 : Mtvec => - read_reg scause_ref >>= fun w__15 : Mcause => - (match (tvec_addr w__14 w__15) with - | Some (epc) => returnm (epc : mword 64) - | None => (internal_error "Invalid stvec mode") : M (mword 64) - end) - : M (mword 64) - | User => (internal_error "the N extension is currently unsupported") : M (mword 64) - end) - : M (mword 64). - -Definition handle_exception (cur_priv : Privilege) (ctl : ctl_result) (pc : mword 64) -: M (mword 64) := - (match (cur_priv, ctl) with - | (_, CTL_TRAP (e)) => - exception_delegatee e.(sync_exception_trap) cur_priv >>= fun del_priv => - let '_ := - (print_endline - (String.append "trapping from " - (String.append ((privLevel_to_str cur_priv) : string) - (String.append " to " - (String.append ((privLevel_to_str del_priv) : string) - (String.append " to handle " - ((exceptionType_to_str e.(sync_exception_trap)) - : string))))))) - : unit in - (handle_trap del_priv false ((exceptionType_to_bits e.(sync_exception_trap)) : mword 4) pc - e.(sync_exception_excinfo)) - : M (mword 64) - | (_, CTL_MRET (tt)) => - read_reg cur_privilege_ref >>= fun prev_priv => - read_reg mstatus_ref >>= fun w__1 : Mstatus => - _set_Mstatus_MIE mstatus_ref (_get_Mstatus_MPIE w__1) >> - _set_Mstatus_MPIE mstatus_ref ((bool_to_bits true) : mword 1) >> - read_reg mstatus_ref >>= fun w__2 : Mstatus => - write_reg cur_privilege_ref (privLevel_of_bits (_get_Mstatus_MPP w__2)) >> - _set_Mstatus_MPP mstatus_ref (privLevel_to_bits User) >> - read_reg mstatus_ref >>= fun w__3 : Mstatus => - read_reg mstatus_ref >>= fun w__4 : Mstatus => - let '_ := - (print_endline - (String.append "CSR mstatus <- " - (String.append (string_of_bits (_get_Mstatus_bits w__3)) - (String.append " (input: " - (String.append (string_of_bits (_get_Mstatus_bits w__4)) ")"))))) - : unit in - read_reg cur_privilege_ref >>= fun w__5 : Privilege => - let '_ := - (print_endline - (String.append "ret-ing from " - (String.append ((privLevel_to_str prev_priv) : string) - (String.append " to " ((privLevel_to_str w__5) : string))))) - : unit in - let '_ := (cancel_reservation tt) : unit in - (read_reg mepc_ref : M (mword 64)) >>= fun w__6 : xlenbits => - pc_alignment_mask tt >>= fun w__7 : mword 64 => returnm ((and_vec w__6 w__7) : mword 64) - | (_, CTL_SRET (tt)) => - read_reg cur_privilege_ref >>= fun prev_priv => - read_reg mstatus_ref >>= fun w__8 : Mstatus => - _set_Mstatus_SIE mstatus_ref (_get_Mstatus_SPIE w__8) >> - _set_Mstatus_SPIE mstatus_ref ((bool_to_bits true) : mword 1) >> - read_reg mstatus_ref >>= fun w__9 : Mstatus => - write_reg - cur_privilege_ref - (if ((eq_vec (_get_Mstatus_SPP w__9) ((bool_to_bits true) : mword 1))) then Supervisor - else User) >> - _set_Mstatus_SPP mstatus_ref ((bool_to_bits false) : mword 1) >> - read_reg mstatus_ref >>= fun w__10 : Mstatus => - read_reg mstatus_ref >>= fun w__11 : Mstatus => - let '_ := - (print_endline - (String.append "CSR mstatus <- " - (String.append (string_of_bits (_get_Mstatus_bits w__10)) - (String.append " (input: " - (String.append (string_of_bits (_get_Mstatus_bits w__11)) ")"))))) - : unit in - read_reg cur_privilege_ref >>= fun w__12 : Privilege => - let '_ := - (print_endline - (String.append "ret-ing from " - (String.append ((privLevel_to_str prev_priv) : string) - (String.append " to " ((privLevel_to_str w__12) : string))))) - : unit in - let '_ := (cancel_reservation tt) : unit in - (read_reg sepc_ref : M (mword 64)) >>= fun w__13 : xlenbits => - pc_alignment_mask tt >>= fun w__14 : mword 64 => returnm ((and_vec w__13 w__14) : mword 64) - end) - : M (mword 64). - -Definition handle_mem_exception (addr : mword 64) (e : ExceptionType) -: M (unit) := - let t : sync_exception := - {| sync_exception_trap := e; - sync_exception_excinfo := (Some (addr)) |} in - read_reg cur_privilege_ref >>= fun w__0 : Privilege => - (read_reg PC_ref : M (mword 64)) >>= fun w__1 : xlenbits => - handle_exception w__0 (CTL_TRAP (t)) w__1 >>= fun w__2 : mword 64 => - write_reg nextPC_ref w__2 - : M (unit). - -Definition handle_decode_exception (instbits : mword 64) -: M (unit) := - let t : sync_exception := - {| sync_exception_trap := E_Illegal_Instr; - sync_exception_excinfo := (Some (instbits)) |} in - read_reg cur_privilege_ref >>= fun w__0 : Privilege => - (read_reg PC_ref : M (mword 64)) >>= fun w__1 : xlenbits => - handle_exception w__0 (CTL_TRAP (t)) w__1 >>= fun w__2 : mword 64 => - write_reg nextPC_ref w__2 - : M (unit). - -Definition handle_interrupt (i : InterruptType) (del_priv : Privilege) -: M (unit) := - (read_reg PC_ref : M (mword 64)) >>= fun w__0 : xlenbits => - handle_trap del_priv true ((interruptType_to_bits i) : mword 4) w__0 None >>= fun w__1 : mword 64 => - write_reg nextPC_ref w__1 - : M (unit). - -Definition handle_illegal '(tt : unit) -: M (unit) := - let t : sync_exception := - {| sync_exception_trap := E_Illegal_Instr; - sync_exception_excinfo := None |} in - read_reg cur_privilege_ref >>= fun w__0 : Privilege => - (read_reg PC_ref : M (mword 64)) >>= fun w__1 : xlenbits => - handle_exception w__0 (CTL_TRAP (t)) w__1 >>= fun w__2 : mword 64 => - write_reg nextPC_ref w__2 - : M (unit). - -Definition init_sys '(tt : unit) -: M (unit) := - write_reg cur_privilege_ref Machine >> - write_reg mhartid_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> - _set_Misa_MXL misa_ref (arch_to_bits RV64) >> - _set_Misa_A misa_ref ((bool_to_bits true) : mword 1) >> - _set_Misa_C misa_ref ((bool_to_bits true) : mword 1) >> - _set_Misa_I misa_ref ((bool_to_bits true) : mword 1) >> - _set_Misa_M misa_ref ((bool_to_bits true) : mword 1) >> - _set_Misa_U misa_ref ((bool_to_bits true) : mword 1) >> - _set_Misa_S misa_ref ((bool_to_bits true) : mword 1) >> - read_reg misa_ref >>= fun w__0 : Misa => - _set_Mstatus_SXL mstatus_ref (_get_Misa_MXL w__0) >> - read_reg misa_ref >>= fun w__1 : Misa => - _set_Mstatus_UXL mstatus_ref (_get_Misa_MXL w__1) >> - _set_Mstatus_SD mstatus_ref ((bool_to_bits false) : mword 1) >> - _set_Minterrupts_bits mip_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> - _set_Minterrupts_bits mie_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> - _set_Minterrupts_bits mideleg_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> - _set_Medeleg_bits medeleg_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> - _set_Mtvec_bits mtvec_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> - _set_Mcause_bits mcause_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> - write_reg mepc_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> - write_reg mtval_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> - write_reg mscratch_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> - write_reg mcycle_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> - write_reg mtime_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> - _set_Counteren_bits mcounteren_ref (EXTZ 32 (vec_of_bits [B0] : mword 1)) >> - write_reg minstret_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> - write_reg minstret_written_ref false >> - read_reg mstatus_ref >>= fun w__2 : Mstatus => - returnm ((print_endline - (String.append "CSR mstatus <- " - (String.append (string_of_bits (_get_Mstatus_bits w__2)) - (String.append " (input: " - (String.append - (string_of_bits ((EXTZ 64 (vec_of_bits [B0] : mword 1)) : xlenbits)) - ")"))))) - : unit). - -Axiom plat_ram_base : forall (_ : unit) , xlenbits. - -Axiom plat_ram_size : forall (_ : unit) , xlenbits. - -Axiom plat_enable_dirty_update : forall (_ : unit) , bool. - -Axiom plat_enable_misaligned_access : forall (_ : unit) , bool. - -Axiom plat_rom_base : forall (_ : unit) , xlenbits. - -Axiom plat_rom_size : forall (_ : unit) , xlenbits. - -Axiom plat_clint_base : forall (_ : unit) , xlenbits. - -Axiom plat_clint_size : forall (_ : unit) , xlenbits. - -Axiom plat_htif_tohost : forall (_ : unit) , xlenbits. - -Definition phys_mem_segments '(tt : unit) -: list ((mword 64 * mword 64)) := - (plat_rom_base tt, plat_rom_size tt) :: (plat_ram_base tt, plat_ram_size tt) :: []. - -Definition within_phys_mem (addr : mword 64) (width : Z) -: bool := - if ((andb (zopz0zIzJ_u (plat_ram_base tt) addr) - (zopz0zIzJ_u (add_vec_int addr width) (add_vec (plat_ram_base tt) (plat_ram_size tt))))) - then - true - else if ((andb (zopz0zIzJ_u (plat_rom_base tt) addr) - (zopz0zIzJ_u (add_vec_int addr width) (add_vec (plat_rom_base tt) (plat_rom_size tt))))) - then - true - else false. - -Definition within_clint (addr : mword 64) (width : Z) -: bool := - andb (zopz0zIzJ_u (plat_clint_base tt) addr) - (zopz0zIzJ_u (add_vec_int addr width) (add_vec (plat_clint_base tt) (plat_clint_size tt))). - -Definition within_htif_writable (addr : mword 64) (width : Z) -: bool := - eq_vec (plat_htif_tohost tt) addr. - -Definition within_htif_readable (addr : mword 64) (width : Z) -: bool := - eq_vec (plat_htif_tohost tt) addr. - -Axiom plat_insns_per_tick : forall (_ : unit) , Z. - -Definition MSIP_BASE : xlenbits := -(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64). -Hint Unfold MSIP_BASE : sail. -Definition MTIMECMP_BASE : xlenbits := -(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64). -Hint Unfold MTIMECMP_BASE : sail. -Definition MTIME_BASE : xlenbits := -(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0; - B0] - : mword 64). -Hint Unfold MTIME_BASE : sail. -Definition clint_load (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} -: M (MemoryOpResult (mword (8 * width))) := - let addr := sub_vec addr (plat_clint_base tt) in - (if sumbool_of_bool ((andb (eq_vec addr MSIP_BASE) (orb (Z.eqb width 8) (Z.eqb width 4)))) then - read_reg mip_ref >>= fun w__0 : Minterrupts => - let '_ := - (print_endline - (String.append "clint[" - (String.append (string_of_bits addr) - (String.append "] -> " (string_of_bits (_get_Minterrupts_MSI w__0)))))) - : unit in - read_reg mip_ref >>= fun w__1 : Minterrupts => - returnm ((MemValue - (autocast (zero_extend (_get_Minterrupts_MSI w__1) (Z.mul 8 width)))) - : MemoryOpResult (mword (8 * width))) - else if sumbool_of_bool ((andb (eq_vec addr MTIMECMP_BASE) (Z.eqb width 8))) then - (read_reg mtimecmp_ref : M (mword 64)) >>= fun w__2 : xlenbits => - let '_ := - (print_endline - (String.append "clint[" - (String.append (string_of_bits addr) (String.append "] -> " (string_of_bits w__2))))) - : unit in - (read_reg mtimecmp_ref : M (mword 64)) >>= fun w__3 : xlenbits => - returnm ((MemValue - (autocast (autocast (zero_extend w__3 64)))) - : MemoryOpResult (mword (8 * width))) - else if sumbool_of_bool ((andb (eq_vec addr MTIME_BASE) (Z.eqb width 8))) then - (read_reg mtime_ref : M (mword 64)) >>= fun w__4 : xlenbits => - let '_ := - (print_endline - (String.append "clint[" - (String.append (string_of_bits addr) (String.append "] -> " (string_of_bits w__4))))) - : unit in - (read_reg mtime_ref : M (mword 64)) >>= fun w__5 : xlenbits => - returnm ((MemValue - (autocast (autocast (zero_extend w__5 64)))) - : MemoryOpResult (mword (8 * width))) - else - let '_ := - (print_endline - (String.append "clint[" (String.append (string_of_bits addr) "] -> "))) - : unit in - returnm ((MemException - (E_Load_Access_Fault)) - : MemoryOpResult (mword (8 * width)))) - : M (MemoryOpResult (mword (8 * width))). - -Definition clint_dispatch '(tt : unit) -: M (unit) := - (read_reg mtime_ref : M (mword 64)) >>= fun w__0 : xlenbits => - let '_ := (print_endline (String.append "clint::tick mtime <- " (string_of_bits w__0))) : unit in - _set_Minterrupts_MTI mip_ref ((bool_to_bits false) : mword 1) >> - (read_reg mtimecmp_ref : M (mword 64)) >>= fun w__1 : xlenbits => - (read_reg mtime_ref : M (mword 64)) >>= fun w__2 : xlenbits => - (if ((zopz0zIzJ_u w__1 w__2)) then - (read_reg mtime_ref : M (mword 64)) >>= fun w__3 : xlenbits => - let '_ := - (print_endline (String.append " clint timer pending at mtime " (string_of_bits w__3))) - : unit in - (_set_Minterrupts_MTI mip_ref ((bool_to_bits true) : mword 1)) - : M (unit) - else returnm (tt : unit)) - : M (unit). - -Definition clint_store (addr : mword 64) (width : Z) (data : mword (8 * width)) `{ArithFact (width >= - (0 + 1))} -: M (MemoryOpResult bool) := - let addr := sub_vec addr (plat_clint_base tt) in - (if sumbool_of_bool ((andb (eq_vec addr MSIP_BASE) (orb (Z.eqb width 8) (Z.eqb width 4)))) then - cast_unit_vec (access_vec_dec data 0) >>= fun w__0 : mword 1 => - let '_ := - (print_endline - (String.append "clint[" - (String.append (string_of_bits addr) - (String.append "] <- " - (String.append (string_of_bits data) - (String.append " (mip.MSI <- " - (String.append (string_of_bits (w__0 : mword 1)) ")"))))))) - : unit in - cast_unit_vec (access_vec_dec data 0) >>= fun w__1 : mword 1 => - _set_Minterrupts_MSI mip_ref - ((bool_to_bits (eq_vec (w__1 : mword 1) (vec_of_bits [B1] : mword 1))) - : mword 1) >> - clint_dispatch tt >> returnm ((MemValue (true)) : MemoryOpResult bool) - else if sumbool_of_bool ((andb (eq_vec addr MTIMECMP_BASE) (Z.eqb width 8))) then - let '_ := - (print_endline - (String.append "clint[" - (String.append (string_of_bits addr) - (String.append "] <- " (String.append (string_of_bits data) " (mtimecmp)"))))) - : unit in - write_reg mtimecmp_ref (zero_extend data 64) >> - clint_dispatch tt >> returnm ((MemValue (true)) : MemoryOpResult bool) - else - let '_ := - (print_endline - (String.append "clint[" - (String.append (string_of_bits addr) - (String.append "] <- " (String.append (string_of_bits data) " ()"))))) - : unit in - returnm ((MemException - (E_SAMO_Access_Fault)) - : MemoryOpResult bool)) - : M (MemoryOpResult bool). - -Definition tick_clock '(tt : unit) -: M (unit) := - (read_reg mcycle_ref : M (mword 64)) >>= fun w__0 : xlenbits => - write_reg mcycle_ref (add_vec_int w__0 1) >> - (read_reg mtime_ref : M (mword 64)) >>= fun w__1 : xlenbits => - write_reg mtime_ref (add_vec_int w__1 1) >> (clint_dispatch tt) : M (unit). - -Axiom plat_term_write : forall (_ : bits 8) , unit. - -Axiom plat_term_read : forall (_ : unit) , bits 8. - -Definition Mk_htif_cmd (v : mword 64) -: htif_cmd := - {| htif_cmd_htif_cmd_chunk_0 := (subrange_vec_dec v 63 0) |}. - -Definition _get_htif_cmd_bits (v : htif_cmd) -: mword 64 := - subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 63 0. - -Definition _set_htif_cmd_bits (r_ref : register_ref regstate register_value htif_cmd) (v : mword 64) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - htif_cmd_htif_cmd_chunk_0 := - (update_subrange_vec_dec r.(htif_cmd_htif_cmd_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} - : htif_cmd in - write_reg r_ref r - : M (unit). - -Definition _update_htif_cmd_bits (v : htif_cmd) (x : mword 64) -: htif_cmd := - {[ v with - htif_cmd_htif_cmd_chunk_0 := - (update_subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. - -Definition _get_htif_cmd_device (v : htif_cmd) -: mword 8 := - subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 63 56. - -Definition _set_htif_cmd_device (r_ref : register_ref regstate register_value htif_cmd) (v : mword 8) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - htif_cmd_htif_cmd_chunk_0 := - (update_subrange_vec_dec r.(htif_cmd_htif_cmd_chunk_0) 63 56 (subrange_vec_dec v 7 0)) ]} - : htif_cmd in - write_reg r_ref r - : M (unit). - -Definition _update_htif_cmd_device (v : htif_cmd) (x : mword 8) -: htif_cmd := - {[ v with - htif_cmd_htif_cmd_chunk_0 := - (update_subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 63 56 (subrange_vec_dec x 7 0)) ]}. - -Definition _get_htif_cmd_cmd (v : htif_cmd) -: mword 8 := - subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 55 48. - -Definition _set_htif_cmd_cmd (r_ref : register_ref regstate register_value htif_cmd) (v : mword 8) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - htif_cmd_htif_cmd_chunk_0 := - (update_subrange_vec_dec r.(htif_cmd_htif_cmd_chunk_0) 55 48 (subrange_vec_dec v 7 0)) ]} - : htif_cmd in - write_reg r_ref r - : M (unit). - -Definition _update_htif_cmd_cmd (v : htif_cmd) (x : mword 8) -: htif_cmd := - {[ v with - htif_cmd_htif_cmd_chunk_0 := - (update_subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 55 48 (subrange_vec_dec x 7 0)) ]}. - -Definition _get_htif_cmd_payload (v : htif_cmd) -: mword 48 := - subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 47 0. - -Definition _set_htif_cmd_payload (r_ref : register_ref regstate register_value htif_cmd) (v : mword 48) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - htif_cmd_htif_cmd_chunk_0 := - (update_subrange_vec_dec r.(htif_cmd_htif_cmd_chunk_0) 47 0 (subrange_vec_dec v 47 0)) ]} - : htif_cmd in - write_reg r_ref r - : M (unit). - -Definition _update_htif_cmd_payload (v : htif_cmd) (x : mword 48) -: htif_cmd := - {[ v with - htif_cmd_htif_cmd_chunk_0 := - (update_subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 47 0 (subrange_vec_dec x 47 0)) ]}. - -Definition htif_load (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} -: M (MemoryOpResult (mword (8 * width))) := - (read_reg htif_tohost_ref : M (mword 64)) >>= fun w__0 : xlenbits => - let '_ := - (print_endline - (String.append "htif[" - (String.append (string_of_bits addr) (String.append "] -> " (string_of_bits w__0))))) - : unit in - (if sumbool_of_bool ((Z.eqb width 8)) then - (read_reg htif_tohost_ref : M (mword 64)) >>= fun w__1 : xlenbits => - returnm ((MemValue - (autocast (autocast (zero_extend w__1 64)))) - : MemoryOpResult (mword (8 * width))) - else returnm ((MemException (E_Load_Access_Fault)) : MemoryOpResult (mword (8 * width)))) - : M (MemoryOpResult (mword (8 * width))). - -Definition htif_store (addr : mword 64) (width : Z) (data : mword (8 * width)) `{ArithFact ((0 + 1) <= - width /\ - width <= 8)} -: M (MemoryOpResult bool) := - let '_ := - (print_endline - (String.append "htif[" - (String.append (string_of_bits addr) (String.append "] <- " (string_of_bits data))))) - : unit in - let cbits : xlenbits := EXTZ 64 data in - write_reg htif_tohost_ref cbits >> - let cmd := Mk_htif_cmd cbits in - let b__0 := _get_htif_cmd_device cmd in - (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8))) then - let '_ := - (print_endline - (String.append "htif-syscall-proxy cmd: " (string_of_bits (_get_htif_cmd_payload cmd)))) - : unit in - cast_unit_vec (access_vec_dec (_get_htif_cmd_payload cmd) 0) >>= fun w__0 : mword 1 => - (if ((eq_vec (w__0 : mword 1) (vec_of_bits [B1] : mword 1))) then - write_reg htif_done_ref true >> - write_reg - htif_exit_code_ref - ((shift_bits_right (zero_extend (_get_htif_cmd_payload cmd) xlen) - (vec_of_bits [B0;B1] : mword 2)) - : xlenbits) - : M (unit) - else returnm (tt : unit)) - : M (unit) - else - returnm ((if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : mword 8))) then - let '_ := - (print_endline - (String.append "htif-term cmd: " (string_of_bits (_get_htif_cmd_payload cmd)))) - : unit in - let b__2 := _get_htif_cmd_cmd cmd in - if ((eq_vec b__2 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8))) then tt - else if ((eq_vec b__2 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : mword 8))) then - plat_term_write (subrange_vec_dec (_get_htif_cmd_payload cmd) 7 0) - else print_endline (String.append "Unknown term cmd: " (string_of_bits b__2)) - else print_endline (String.append "htif-???? cmd: " (string_of_bits data))) - : unit)) >> - returnm ((MemValue - (true)) - : MemoryOpResult bool). - -Definition htif_tick '(tt : unit) -: M (unit) := - (read_reg htif_tohost_ref : M (mword 64)) >>= fun w__0 : xlenbits => - let '_ := (print_endline (String.append "htif::tick " (string_of_bits w__0))) : unit in - write_reg htif_tohost_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) - : M (unit). - -Definition within_mmio_readable (addr : mword 64) (width : Z) -: bool := - orb (within_clint addr width) (andb (within_htif_readable addr width) (Z.leb 1 width)). - -Definition within_mmio_writable (addr : mword 64) (width : Z) -: bool := - orb (within_clint addr width) (andb (within_htif_writable addr width) (Z.leb width 8)). - -Definition mmio_read (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} -: M (MemoryOpResult (mword (8 * width))) := - (if ((within_clint addr width)) then - (clint_load addr width) - : M (MemoryOpResult (mword (8 * width))) - else if sumbool_of_bool ((andb (within_htif_readable addr width) (Z.leb 1 width))) then - (htif_load addr width) - : M (MemoryOpResult (mword (8 * width))) - else returnm ((MemException (E_Load_Access_Fault)) : MemoryOpResult (mword (8 * width)))) - : M (MemoryOpResult (mword (8 * width))). - -Definition mmio_write (addr : mword 64) (width : Z) (data : mword (8 * width)) `{ArithFact (width >= - (0 + 1))} -: M (MemoryOpResult bool) := - (if ((within_clint addr width)) then (clint_store addr width data) : M (MemoryOpResult bool) - else if sumbool_of_bool ((andb (within_htif_writable addr width) (Z.leb width 8))) then - (htif_store addr width data) - : M (MemoryOpResult bool) - else returnm ((MemException (E_SAMO_Access_Fault)) : MemoryOpResult bool)) - : M (MemoryOpResult bool). - -Definition init_platform '(tt : unit) -: M (unit) := - write_reg htif_tohost_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> - write_reg htif_done_ref false >> - write_reg htif_exit_code_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) - : M (unit). - -Definition tick_platform '(tt : unit) -: M (unit) := - let '_ := (cancel_reservation tt) : unit in - (htif_tick tt) - : M (unit). - -Definition is_aligned_addr (addr : mword 64) (width : Z) -: bool := - Z.eqb - (projT1 ((build_ex (projT1 (ex_int (modulus (projT1 (uint addr)) width)))) - : {syn_n : Z & ArithFact (True)})) 0. - -Definition phys_mem_read (t : ReadType) (addr : mword 64) (width : Z) (aq : bool) (rl : bool) (res : bool) `{ArithFact (width >= - 0)} -: M (MemoryOpResult (mword (8 * width))) := - __RISCV_read addr width aq rl res >>= fun w__0 : option (mword (8 * width)) => - returnm ((match (t, w__0) with - | (Instruction, None) => MemException (E_Fetch_Access_Fault) - | (Data, None) => MemException (E_Load_Access_Fault) - | (_, Some (v)) => - let '_ := - (print_endline - (String.append "mem[" - (String.append ((readType_to_str t) : string) - (String.append "," - (String.append (string_of_bits addr) - (String.append "] -> " (string_of_bits v))))))) - : unit in - MemValue - (v) - end) - : MemoryOpResult (mword (8 * width))). - -Definition checked_mem_read (t : ReadType) (addr : mword 64) (width : Z) `{ArithFact (width >= - (0 + 1))} -: M (MemoryOpResult (mword (8 * width))) := - (if ((andb (generic_eq ((readType_to_str t) : string) ((readType_to_str Data) : string)) - (within_mmio_readable addr width))) then - (mmio_read addr width) - : M (MemoryOpResult (mword (8 * width))) - else if ((within_phys_mem addr width)) then - (phys_mem_read t addr width false false false) - : M (MemoryOpResult (mword (8 * width))) - else returnm ((MemException (E_Load_Access_Fault)) : MemoryOpResult (mword (8 * width)))) - : M (MemoryOpResult (mword (8 * width))). - -Definition MEMr (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} -: M (MemoryOpResult (mword (8 * width))) := - (checked_mem_read Data addr width) - : M (MemoryOpResult (mword (8 * width))). - -Definition MEMr_acquire (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} -: M (MemoryOpResult (mword (8 * width))) := - (checked_mem_read Data addr width) - : M (MemoryOpResult (mword (8 * width))). - -Definition MEMr_strong_acquire (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} -: M (MemoryOpResult (mword (8 * width))) := - (checked_mem_read Data addr width) - : M (MemoryOpResult (mword (8 * width))). - -Definition MEMr_reserved (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} -: M (MemoryOpResult (mword (8 * width))) := - (checked_mem_read Data addr width) - : M (MemoryOpResult (mword (8 * width))). - -Definition MEMr_reserved_acquire (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} -: M (MemoryOpResult (mword (8 * width))) := - (checked_mem_read Data addr width) - : M (MemoryOpResult (mword (8 * width))). - -Definition MEMr_reserved_strong_acquire (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} -: M (MemoryOpResult (mword (8 * width))) := - (checked_mem_read Data addr width) - : M (MemoryOpResult (mword (8 * width))). - -Definition mem_read (addr : mword 64) (width : Z) (aq : bool) (rl : bool) (res : bool) `{ArithFact (width >= - (0 + 1))} -: M (MemoryOpResult (mword (8 * width))) := - (if ((andb (orb aq res) (negb (is_aligned_addr addr width)))) then - returnm ((MemException - (E_Load_Addr_Align)) - : MemoryOpResult (mword (8 * width))) - else - (match (aq, rl, res) with - | (false, false, false) => - (checked_mem_read Data addr width) : M (MemoryOpResult (mword (8 * width))) - | (true, false, false) => (MEMr_acquire addr width) : M (MemoryOpResult (mword (8 * width))) - | (false, false, true) => - (MEMr_reserved addr width) : M (MemoryOpResult (mword (8 * width))) - | (true, false, true) => - (MEMr_reserved_acquire addr width) : M (MemoryOpResult (mword (8 * width))) - | (false, true, false) => - (throw (Error_not_implemented ("load.rl"))) : M (MemoryOpResult (mword (8 * width))) - | (true, true, false) => - (MEMr_strong_acquire addr width) : M (MemoryOpResult (mword (8 * width))) - | (false, true, true) => - (throw (Error_not_implemented ("lr.rl"))) : M (MemoryOpResult (mword (8 * width))) - | (true, true, true) => - (MEMr_reserved_strong_acquire addr width) : M (MemoryOpResult (mword (8 * width))) - end) - : M (MemoryOpResult (mword (8 * width)))) - : M (MemoryOpResult (mword (8 * width))). - -Definition mem_write_ea (addr : mword 64) (width : Z) (aq : bool) (rl : bool) (con : bool) -: M (MemoryOpResult unit) := - (if ((andb (orb rl con) (negb (is_aligned_addr addr width)))) then - returnm ((MemException - (E_SAMO_Addr_Align)) - : MemoryOpResult unit) - else - (match (aq, rl, con) with - | (false, false, false) => - MEMea addr width >> returnm ((MemValue (tt)) : MemoryOpResult unit) - | (false, true, false) => - MEMea_release addr width >> returnm ((MemValue (tt)) : MemoryOpResult unit) - | (false, false, true) => - MEMea_conditional addr width >> returnm ((MemValue (tt)) : MemoryOpResult unit) - | (false, true, true) => - MEMea_conditional_release addr width >> returnm ((MemValue (tt)) : MemoryOpResult unit) - | (true, false, false) => - (throw (Error_not_implemented ("store.aq"))) : M (MemoryOpResult unit) - | (true, true, false) => - MEMea_strong_release addr width >> returnm ((MemValue (tt)) : MemoryOpResult unit) - | (true, false, true) => (throw (Error_not_implemented ("sc.aq"))) : M (MemoryOpResult unit) - | (true, true, true) => - MEMea_conditional_strong_release addr width >> - returnm ((MemValue - (tt)) - : MemoryOpResult unit) - end) - : M (MemoryOpResult unit)) - : M (MemoryOpResult unit). - -Definition phys_mem_write (addr : mword 64) (width : Z) (data : mword (8 * width)) -: M (MemoryOpResult bool) := - let '_ := - (print_endline - (String.append "mem[" - (String.append (string_of_bits addr) (String.append "] <- " (string_of_bits data))))) - : unit in - __RISCV_write addr width data >>= fun w__0 : bool => - returnm ((MemValue - (w__0)) - : MemoryOpResult bool). - -Definition checked_mem_write (addr : mword 64) (width : Z) (data : mword (8 * width)) `{ArithFact (width >= - (0 + 1))} -: M (MemoryOpResult bool) := - (if ((within_mmio_writable addr width)) then - (mmio_write addr width data) - : M (MemoryOpResult bool) - else if ((within_phys_mem addr width)) then - (phys_mem_write addr width data) - : M (MemoryOpResult bool) - else returnm ((MemException (E_SAMO_Access_Fault)) : MemoryOpResult bool)) - : M (MemoryOpResult bool). - -Definition MEMval (addr : mword 64) (width : Z) (data : mword (8 * width)) `{ArithFact (width >= - (0 + 1))} -: M (MemoryOpResult bool) := - (checked_mem_write addr width data) - : M (MemoryOpResult bool). - -Definition MEMval_release (addr : mword 64) (width : Z) (data : mword (8 * width)) `{ArithFact (width >= - (0 + 1))} -: M (MemoryOpResult bool) := - (checked_mem_write addr width data) - : M (MemoryOpResult bool). - -Definition MEMval_strong_release (addr : mword 64) (width : Z) (data : mword (8 * width)) `{ArithFact (width >= - (0 + 1))} -: M (MemoryOpResult bool) := - (checked_mem_write addr width data) - : M (MemoryOpResult bool). - -Definition MEMval_conditional (addr : mword 64) (width : Z) (data : mword (8 * width)) `{ArithFact (width >= - (0 + 1))} -: M (MemoryOpResult bool) := - (checked_mem_write addr width data) - : M (MemoryOpResult bool). - -Definition MEMval_conditional_release (addr : mword 64) (width : Z) (data : mword (8 * width)) `{ArithFact (width >= - (0 + 1))} -: M (MemoryOpResult bool) := - (checked_mem_write addr width data) - : M (MemoryOpResult bool). - -Definition MEMval_conditional_strong_release (addr : mword 64) (width : Z) (data : mword (8 * width)) `{ArithFact (width >= - (0 + 1))} -: M (MemoryOpResult bool) := - (checked_mem_write addr width data) - : M (MemoryOpResult bool). - -Definition mem_write_value (addr : mword 64) (width : Z) (value : mword (8 * width)) (aq : bool) (rl : bool) (con : bool) `{ArithFact (width >= - (0 + 1))} -: M (MemoryOpResult bool) := - (if ((andb (orb rl con) (negb (is_aligned_addr addr width)))) then - returnm ((MemException - (E_SAMO_Addr_Align)) - : MemoryOpResult bool) - else - (match (aq, rl, con) with - | (false, false, false) => (checked_mem_write addr width value) : M (MemoryOpResult bool) - | (false, true, false) => (MEMval_release addr width value) : M (MemoryOpResult bool) - | (false, false, true) => (MEMval_conditional addr width value) : M (MemoryOpResult bool) - | (false, true, true) => - (MEMval_conditional_release addr width value) : M (MemoryOpResult bool) - | (true, false, false) => - (throw (Error_not_implemented ("store.aq"))) : M (MemoryOpResult bool) - | (true, true, false) => (MEMval_strong_release addr width value) : M (MemoryOpResult bool) - | (true, false, true) => (throw (Error_not_implemented ("sc.aq"))) : M (MemoryOpResult bool) - | (true, true, true) => - (MEMval_conditional_strong_release addr width value) : M (MemoryOpResult bool) - end) - : M (MemoryOpResult bool)) - : M (MemoryOpResult bool). - -Definition PAGESIZE_BITS := 12. -Hint Unfold PAGESIZE_BITS : sail. -Definition Mk_PTE_Bits (v : mword 8) -: PTE_Bits := - {| PTE_Bits_PTE_Bits_chunk_0 := (subrange_vec_dec v 7 0) |}. - -Definition _get_PTE_Bits_bits (v : PTE_Bits) -: mword 8 := - subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 7 0. - -Definition _set_PTE_Bits_bits (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 8) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - PTE_Bits_PTE_Bits_chunk_0 := - (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 7 0 (subrange_vec_dec v 7 0)) ]} - : PTE_Bits in - write_reg r_ref r - : M (unit). - -Definition _update_PTE_Bits_bits (v : PTE_Bits) (x : mword 8) -: PTE_Bits := - {[ v with - PTE_Bits_PTE_Bits_chunk_0 := - (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}. - -Definition _get_PTE_Bits_D (v : PTE_Bits) -: mword 1 := - subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 7 7. - -Definition _set_PTE_Bits_D (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - PTE_Bits_PTE_Bits_chunk_0 := - (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} - : PTE_Bits in - write_reg r_ref r - : M (unit). - -Definition _update_PTE_Bits_D (v : PTE_Bits) (x : mword 1) -: PTE_Bits := - {[ v with - PTE_Bits_PTE_Bits_chunk_0 := - (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_PTE_Bits_A (v : PTE_Bits) -: mword 1 := - subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 6 6. - -Definition _set_PTE_Bits_A (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - PTE_Bits_PTE_Bits_chunk_0 := - (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]} - : PTE_Bits in - write_reg r_ref r - : M (unit). - -Definition _update_PTE_Bits_A (v : PTE_Bits) (x : mword 1) -: PTE_Bits := - {[ v with - PTE_Bits_PTE_Bits_chunk_0 := - (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_PTE_Bits_G (v : PTE_Bits) -: mword 1 := - subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 5 5. - -Definition _set_PTE_Bits_G (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - PTE_Bits_PTE_Bits_chunk_0 := - (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} - : PTE_Bits in - write_reg r_ref r - : M (unit). - -Definition _update_PTE_Bits_G (v : PTE_Bits) (x : mword 1) -: PTE_Bits := - {[ v with - PTE_Bits_PTE_Bits_chunk_0 := - (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_PTE_Bits_U (v : PTE_Bits) -: mword 1 := - subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 4 4. - -Definition _set_PTE_Bits_U (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - PTE_Bits_PTE_Bits_chunk_0 := - (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} - : PTE_Bits in - write_reg r_ref r - : M (unit). - -Definition _update_PTE_Bits_U (v : PTE_Bits) (x : mword 1) -: PTE_Bits := - {[ v with - PTE_Bits_PTE_Bits_chunk_0 := - (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_PTE_Bits_X (v : PTE_Bits) -: mword 1 := - subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 3 3. - -Definition _set_PTE_Bits_X (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - PTE_Bits_PTE_Bits_chunk_0 := - (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]} - : PTE_Bits in - write_reg r_ref r - : M (unit). - -Definition _update_PTE_Bits_X (v : PTE_Bits) (x : mword 1) -: PTE_Bits := - {[ v with - PTE_Bits_PTE_Bits_chunk_0 := - (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_PTE_Bits_W (v : PTE_Bits) -: mword 1 := - subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 2 2. - -Definition _set_PTE_Bits_W (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - PTE_Bits_PTE_Bits_chunk_0 := - (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]} - : PTE_Bits in - write_reg r_ref r - : M (unit). - -Definition _update_PTE_Bits_W (v : PTE_Bits) (x : mword 1) -: PTE_Bits := - {[ v with - PTE_Bits_PTE_Bits_chunk_0 := - (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_PTE_Bits_R (v : PTE_Bits) -: mword 1 := - subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 1 1. - -Definition _set_PTE_Bits_R (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - PTE_Bits_PTE_Bits_chunk_0 := - (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} - : PTE_Bits in - write_reg r_ref r - : M (unit). - -Definition _update_PTE_Bits_R (v : PTE_Bits) (x : mword 1) -: PTE_Bits := - {[ v with - PTE_Bits_PTE_Bits_chunk_0 := - (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_PTE_Bits_V (v : PTE_Bits) -: mword 1 := - subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 0 0. - -Definition _set_PTE_Bits_V (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - PTE_Bits_PTE_Bits_chunk_0 := - (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} - : PTE_Bits in - write_reg r_ref r - : M (unit). - -Definition _update_PTE_Bits_V (v : PTE_Bits) (x : mword 1) -: PTE_Bits := - {[ v with - PTE_Bits_PTE_Bits_chunk_0 := - (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. - -Definition isPTEPtr (p : mword 8) -: bool := - let a := Mk_PTE_Bits p in - andb (eq_vec (_get_PTE_Bits_R a) ((bool_to_bits false) : mword 1)) - (andb (eq_vec (_get_PTE_Bits_W a) ((bool_to_bits false) : mword 1)) - (eq_vec (_get_PTE_Bits_X a) ((bool_to_bits false) : mword 1))). - -Definition isInvalidPTE (p : mword 8) -: bool := - let a := Mk_PTE_Bits p in - orb (eq_vec (_get_PTE_Bits_V a) ((bool_to_bits false) : mword 1)) - (andb (eq_vec (_get_PTE_Bits_W a) ((bool_to_bits true) : mword 1)) - (eq_vec (_get_PTE_Bits_R a) ((bool_to_bits false) : mword 1))). - -Definition checkPTEPermission (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) (p : PTE_Bits) -: M (bool) := - (match (ac, priv) with - | (Read, User) => - returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits true) : mword 1)) - (orb (eq_vec (_get_PTE_Bits_R p) ((bool_to_bits true) : mword 1)) - (andb (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)) mxr))) - : bool) - | (Write, User) => - returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits true) : mword 1)) - (eq_vec (_get_PTE_Bits_W p) ((bool_to_bits true) : mword 1))) - : bool) - | (ReadWrite, User) => - returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits true) : mword 1)) - (andb (eq_vec (_get_PTE_Bits_W p) ((bool_to_bits true) : mword 1)) - (orb (eq_vec (_get_PTE_Bits_R p) ((bool_to_bits true) : mword 1)) - (andb (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)) mxr)))) - : bool) - | (Execute, User) => - returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits true) : mword 1)) - (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1))) - : bool) - | (Read, Supervisor) => - returnm ((andb (orb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits false) : mword 1)) do_sum) - (orb (eq_vec (_get_PTE_Bits_R p) ((bool_to_bits true) : mword 1)) - (andb (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)) mxr))) - : bool) - | (Write, Supervisor) => - returnm ((andb (orb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits false) : mword 1)) do_sum) - (eq_vec (_get_PTE_Bits_W p) ((bool_to_bits true) : mword 1))) - : bool) - | (ReadWrite, Supervisor) => - returnm ((andb (orb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits false) : mword 1)) do_sum) - (andb (eq_vec (_get_PTE_Bits_W p) ((bool_to_bits true) : mword 1)) - (orb (eq_vec (_get_PTE_Bits_R p) ((bool_to_bits true) : mword 1)) - (andb (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)) mxr)))) - : bool) - | (Execute, Supervisor) => - returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits false) : mword 1)) - (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1))) - : bool) - | (_, Machine) => (internal_error "m-mode mem perm check") : M (bool) - end) - : M (bool). - -Definition update_PTE_Bits (p : PTE_Bits) (a : AccessType) -: option PTE_Bits := - let update_d := - andb - (orb (generic_eq ((accessType_to_str a) : string) ((accessType_to_str Write) : string)) - (generic_eq ((accessType_to_str a) : string) ((accessType_to_str ReadWrite) : string))) - (eq_vec (_get_PTE_Bits_D p) ((bool_to_bits false) : mword 1)) in - let update_a := eq_vec (_get_PTE_Bits_A p) ((bool_to_bits false) : mword 1) in - if ((orb update_d update_a)) then - let np := _update_PTE_Bits_A p ((bool_to_bits true) : mword 1) in - let np := if (update_d) then _update_PTE_Bits_D p ((bool_to_bits true) : mword 1) else np in - Some - (np) - else None. - -Definition PTW_Error_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 4)} -: PTW_Error := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then PTW_Access - else if sumbool_of_bool ((Z.eqb p0_ 1)) then PTW_Invalid_PTE - else if sumbool_of_bool ((Z.eqb p0_ 2)) then PTW_No_Permission - else if sumbool_of_bool ((Z.eqb p0_ 3)) then PTW_Misaligned - else PTW_PTE_Update. - -Definition num_of_PTW_Error (arg_ : PTW_Error) -: {e : Z & ArithFact (0 <= e /\ e <= 4)} := - build_ex(match arg_ with - | PTW_Access => 0 - | PTW_Invalid_PTE => 1 - | PTW_No_Permission => 2 - | PTW_Misaligned => 3 - | PTW_PTE_Update => 4 - end). - -Definition ptw_error_to_str (e : PTW_Error) -: string := - match e with - | PTW_Access => "mem-access-error" - | PTW_Invalid_PTE => "invalid-pte" - | PTW_No_Permission => "no-permission" - | PTW_Misaligned => "misaligned-superpage" - | PTW_PTE_Update => "pte-update-needed" - end. - -Definition translationException (a : AccessType) (f : PTW_Error) -: ExceptionType := - match (a, f) with - | (ReadWrite, PTW_Access) => E_SAMO_Access_Fault - | (ReadWrite, _) => E_SAMO_Page_Fault - | (Read, PTW_Access) => E_Load_Access_Fault - | (Read, _) => E_Load_Page_Fault - | (Write, PTW_Access) => E_SAMO_Access_Fault - | (Write, _) => E_SAMO_Page_Fault - | (Fetch, PTW_Access) => E_Fetch_Access_Fault - | (Fetch, _) => E_Fetch_Page_Fault - end. - -Definition SV39_LEVEL_BITS := 9. -Hint Unfold SV39_LEVEL_BITS : sail. -Definition SV39_LEVELS := 3. -Hint Unfold SV39_LEVELS : sail. -Definition PTE39_LOG_SIZE := 3. -Hint Unfold PTE39_LOG_SIZE : sail. -Definition PTE39_SIZE := 8. -Hint Unfold PTE39_SIZE : sail. -Definition Mk_SV39_Vaddr (v : mword 39) -: SV39_Vaddr := - {| SV39_Vaddr_SV39_Vaddr_chunk_0 := (subrange_vec_dec v 38 0) |}. - -Definition _get_SV39_Vaddr_bits (v : SV39_Vaddr) -: mword 39 := - subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 0. - -Definition _set_SV39_Vaddr_bits (r_ref : register_ref regstate register_value SV39_Vaddr) (v : mword 39) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - SV39_Vaddr_SV39_Vaddr_chunk_0 := - (update_subrange_vec_dec r.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 0 (subrange_vec_dec v 38 0)) ]} - : SV39_Vaddr in - write_reg r_ref r - : M (unit). - -Definition _update_SV39_Vaddr_bits (v : SV39_Vaddr) (x : mword 39) -: SV39_Vaddr := - {[ v with - SV39_Vaddr_SV39_Vaddr_chunk_0 := - (update_subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 0 (subrange_vec_dec x 38 0)) ]}. - -Definition _get_SV39_Vaddr_VPNi (v : SV39_Vaddr) -: mword 27 := - subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 12. - -Definition _set_SV39_Vaddr_VPNi (r_ref : register_ref regstate register_value SV39_Vaddr) (v : mword 27) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - SV39_Vaddr_SV39_Vaddr_chunk_0 := - (update_subrange_vec_dec r.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 12 (subrange_vec_dec v 26 0)) ]} - : SV39_Vaddr in - write_reg r_ref r - : M (unit). - -Definition _update_SV39_Vaddr_VPNi (v : SV39_Vaddr) (x : mword 27) -: SV39_Vaddr := - {[ v with - SV39_Vaddr_SV39_Vaddr_chunk_0 := - (update_subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 12 (subrange_vec_dec x 26 0)) ]}. - -Definition _get_SV39_Vaddr_PgOfs (v : SV39_Vaddr) -: mword 12 := - subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 11 0. - -Definition _set_SV39_Vaddr_PgOfs (r_ref : register_ref regstate register_value SV39_Vaddr) (v : mword 12) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - SV39_Vaddr_SV39_Vaddr_chunk_0 := - (update_subrange_vec_dec r.(SV39_Vaddr_SV39_Vaddr_chunk_0) 11 0 (subrange_vec_dec v 11 0)) ]} - : SV39_Vaddr in - write_reg r_ref r - : M (unit). - -Definition _update_SV39_Vaddr_PgOfs (v : SV39_Vaddr) (x : mword 12) -: SV39_Vaddr := - {[ v with - SV39_Vaddr_SV39_Vaddr_chunk_0 := - (update_subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 11 0 (subrange_vec_dec x 11 0)) ]}. - -Definition Mk_SV39_Paddr (v : mword 56) -: SV39_Paddr := - {| SV39_Paddr_SV39_Paddr_chunk_0 := (subrange_vec_dec v 55 0) |}. - -Definition _get_SV39_Paddr_bits (v : SV39_Paddr) -: mword 56 := - subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 55 0. - -Definition _set_SV39_Paddr_bits (r_ref : register_ref regstate register_value SV39_Paddr) (v : mword 56) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - SV39_Paddr_SV39_Paddr_chunk_0 := - (update_subrange_vec_dec r.(SV39_Paddr_SV39_Paddr_chunk_0) 55 0 (subrange_vec_dec v 55 0)) ]} - : SV39_Paddr in - write_reg r_ref r - : M (unit). - -Definition _update_SV39_Paddr_bits (v : SV39_Paddr) (x : mword 56) -: SV39_Paddr := - {[ v with - SV39_Paddr_SV39_Paddr_chunk_0 := - (update_subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 55 0 (subrange_vec_dec x 55 0)) ]}. - -Definition _get_SV39_Paddr_PPNi (v : SV39_Paddr) -: mword 44 := - subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 55 12. - -Definition _set_SV39_Paddr_PPNi (r_ref : register_ref regstate register_value SV39_Paddr) (v : mword 44) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - SV39_Paddr_SV39_Paddr_chunk_0 := - (update_subrange_vec_dec r.(SV39_Paddr_SV39_Paddr_chunk_0) 55 12 (subrange_vec_dec v 43 0)) ]} - : SV39_Paddr in - write_reg r_ref r - : M (unit). - -Definition _update_SV39_Paddr_PPNi (v : SV39_Paddr) (x : mword 44) -: SV39_Paddr := - {[ v with - SV39_Paddr_SV39_Paddr_chunk_0 := - (update_subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 55 12 (subrange_vec_dec x 43 0)) ]}. - -Definition _get_SV39_Paddr_PgOfs (v : SV39_Paddr) -: mword 12 := - subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 11 0. - -Definition _set_SV39_Paddr_PgOfs (r_ref : register_ref regstate register_value SV39_Paddr) (v : mword 12) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - SV39_Paddr_SV39_Paddr_chunk_0 := - (update_subrange_vec_dec r.(SV39_Paddr_SV39_Paddr_chunk_0) 11 0 (subrange_vec_dec v 11 0)) ]} - : SV39_Paddr in - write_reg r_ref r - : M (unit). - -Definition _update_SV39_Paddr_PgOfs (v : SV39_Paddr) (x : mword 12) -: SV39_Paddr := - {[ v with - SV39_Paddr_SV39_Paddr_chunk_0 := - (update_subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 11 0 (subrange_vec_dec x 11 0)) ]}. - -Definition Mk_SV39_PTE (v : mword 64) -: SV39_PTE := - {| SV39_PTE_SV39_PTE_chunk_0 := (subrange_vec_dec v 63 0) |}. - -Definition _get_SV39_PTE_bits (v : SV39_PTE) -: mword 64 := - subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 63 0. - -Definition _set_SV39_PTE_bits (r_ref : register_ref regstate register_value SV39_PTE) (v : mword 64) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - SV39_PTE_SV39_PTE_chunk_0 := - (update_subrange_vec_dec r.(SV39_PTE_SV39_PTE_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} - : SV39_PTE in - write_reg r_ref r - : M (unit). - -Definition _update_SV39_PTE_bits (v : SV39_PTE) (x : mword 64) -: SV39_PTE := - {[ v with - SV39_PTE_SV39_PTE_chunk_0 := - (update_subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. - -Definition _get_SV39_PTE_PPNi (v : SV39_PTE) -: mword 44 := - subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 53 10. - -Definition _set_SV39_PTE_PPNi (r_ref : register_ref regstate register_value SV39_PTE) (v : mword 44) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - SV39_PTE_SV39_PTE_chunk_0 := - (update_subrange_vec_dec r.(SV39_PTE_SV39_PTE_chunk_0) 53 10 (subrange_vec_dec v 43 0)) ]} - : SV39_PTE in - write_reg r_ref r - : M (unit). - -Definition _update_SV39_PTE_PPNi (v : SV39_PTE) (x : mword 44) -: SV39_PTE := - {[ v with - SV39_PTE_SV39_PTE_chunk_0 := - (update_subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 53 10 (subrange_vec_dec x 43 0)) ]}. - -Definition _get_SV39_PTE_RSW (v : SV39_PTE) -: mword 2 := - subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 9 8. - -Definition _set_SV39_PTE_RSW (r_ref : register_ref regstate register_value SV39_PTE) (v : mword 2) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - SV39_PTE_SV39_PTE_chunk_0 := - (update_subrange_vec_dec r.(SV39_PTE_SV39_PTE_chunk_0) 9 8 (subrange_vec_dec v 1 0)) ]} - : SV39_PTE in - write_reg r_ref r - : M (unit). - -Definition _update_SV39_PTE_RSW (v : SV39_PTE) (x : mword 2) -: SV39_PTE := - {[ v with - SV39_PTE_SV39_PTE_chunk_0 := - (update_subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 9 8 (subrange_vec_dec x 1 0)) ]}. - -Definition _get_SV39_PTE_BITS (v : SV39_PTE) -: mword 8 := - subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 7 0. - -Definition _set_SV39_PTE_BITS (r_ref : register_ref regstate register_value SV39_PTE) (v : mword 8) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - SV39_PTE_SV39_PTE_chunk_0 := - (update_subrange_vec_dec r.(SV39_PTE_SV39_PTE_chunk_0) 7 0 (subrange_vec_dec v 7 0)) ]} - : SV39_PTE in - write_reg r_ref r - : M (unit). - -Definition _update_SV39_PTE_BITS (v : SV39_PTE) (x : mword 8) -: SV39_PTE := - {[ v with - SV39_PTE_SV39_PTE_chunk_0 := - (update_subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}. - -Definition curAsid64 '(tt : unit) -: M (mword 16) := - (read_reg satp_ref : M (mword 64)) >>= fun w__0 : xlenbits => - let satp64 := Mk_Satp64 w__0 in - returnm ((_get_Satp64_Asid satp64) - : mword 16). - -Definition curPTB39 '(tt : unit) -: M (mword 56) := - (read_reg satp_ref : M (mword 64)) >>= fun w__0 : xlenbits => - let satp64 := Mk_Satp64 w__0 in - returnm ((EXTZ 56 (shiftl (_get_Satp64_PPN satp64) PAGESIZE_BITS)) - : mword 56). - -Hint Unfold PAGESIZE_BITS : sail. -Hint Unfold SV39_LEVEL_BITS : sail. - -Fixpoint walk39 (vaddr : mword 39) (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) (ptb : mword 56) (level : nat) (global : bool) -: M (PTW_Result) := - let va := Mk_SV39_Vaddr vaddr in - let pt_ofs : paddr39 := - shiftl - (EXTZ 56 - (subrange_vec_dec (shiftr (_get_SV39_Vaddr_VPNi va) (Z.mul (Z.of_nat level) SV39_LEVEL_BITS)) - (projT1 (sub_range (build_ex SV39_LEVEL_BITS) (build_ex 1))) 0)) PTE39_LOG_SIZE in - let pte_addr := add_vec ptb pt_ofs in - phys_mem_read Data (EXTZ 64 pte_addr) 8 false false false >>= fun w__0 : MemoryOpResult (mword (8 * 8)) => - (match w__0 with - | MemException (_) => returnm ((PTW_Failure (PTW_Access)) : PTW_Result ) - | MemValue (v) => - let pte := Mk_SV39_PTE v in - let pbits := _get_SV39_PTE_BITS pte in - let pattr := Mk_PTE_Bits pbits in - let is_global := orb global (eq_vec (_get_PTE_Bits_G pattr) ((bool_to_bits true) : mword 1)) in - (if ((isInvalidPTE pbits)) then returnm ((PTW_Failure (PTW_Invalid_PTE)) : PTW_Result ) - else if ((isPTEPtr pbits)) then - (match level with O => - returnm ((PTW_Failure - (PTW_Invalid_PTE)) - : PTW_Result ) - | S level' => - (walk39 vaddr ac priv mxr do_sum - (EXTZ 56 (shiftl (_get_SV39_PTE_PPNi pte) PAGESIZE_BITS)) - level' is_global) - : M (PTW_Result) end) - : M (PTW_Result) - else - checkPTEPermission ac priv mxr do_sum pattr >>= fun w__3 : bool => - returnm ((if ((negb w__3)) then PTW_Failure (PTW_No_Permission) - else if sumbool_of_bool (Nat.ltb O level) then - let mask := - sub_vec_int - (shiftl - (xor_vec (_get_SV39_PTE_PPNi pte) - (xor_vec (_get_SV39_PTE_PPNi pte) - (EXTZ 44 (vec_of_bits [B1] : mword 1)))) - (Z.mul (Z.of_nat level) SV39_LEVEL_BITS)) 1 in - if ((neq_vec (and_vec (_get_SV39_PTE_PPNi pte) mask) - (EXTZ 44 (vec_of_bits [B0] : mword 1)))) then - PTW_Failure - (PTW_Misaligned) - else - let ppn := - or_vec (_get_SV39_PTE_PPNi pte) - (and_vec (EXTZ 44 (_get_SV39_Vaddr_VPNi va)) mask) in - PTW_Success - (concat_vec ppn (_get_SV39_Vaddr_PgOfs va), pte, pte_addr, build_ex (Z.of_nat level), - is_global) - else - PTW_Success - (concat_vec (_get_SV39_PTE_PPNi pte) (_get_SV39_Vaddr_PgOfs va), pte, - pte_addr, build_ex (Z.of_nat level), is_global)) - : PTW_Result)) - : M (PTW_Result) - end) - : M (PTW_Result). - -Definition make_TLB39_Entry (asid : mword 16) (global : bool) (vAddr : mword 39) (pAddr : mword 56) (pte : SV39_PTE) '(existT _ level _ : {n : Z & ArithFact (n >= - 0)}) (pteAddr : mword 56) -: M (TLB39_Entry) := - let 'shift := - projT1 ((build_ex (projT1 (add_range (build_ex PAGESIZE_BITS) - (build_ex (Z.mul level SV39_LEVEL_BITS))))) - : {n : Z & ArithFact (n >= 0)}) in - let vAddrMask : vaddr39 := - sub_vec_int - (shiftl (xor_vec vAddr (xor_vec vAddr (EXTZ 39 (vec_of_bits [B1] : mword 1)))) shift) 1 in - let vMatchMask : vaddr39 := not_vec vAddrMask in - (read_reg mcycle_ref : M (mword 64)) >>= fun w__0 : xlenbits => - returnm (({| TLB39_Entry_asid := asid; - TLB39_Entry_global := global; - TLB39_Entry_pte := pte; - TLB39_Entry_pteAddr := pteAddr; - TLB39_Entry_vAddrMask := vAddrMask; - TLB39_Entry_vMatchMask := vMatchMask; - TLB39_Entry_vAddr := (and_vec vAddr vMatchMask); - TLB39_Entry_pAddr := (shiftl (shiftr pAddr shift) shift); - TLB39_Entry_age := w__0 |}) - : TLB39_Entry). - -Definition lookupTLB39 (asid : mword 16) (vaddr : mword 39) -: M (option ((Z * TLB39_Entry))) := - read_reg tlb39_ref >>= fun w__0 : option TLB39_Entry => - returnm ((match w__0 with - | None => None - | Some (e) => - if ((andb (orb e.(TLB39_Entry_global) (eq_vec e.(TLB39_Entry_asid) asid)) - (eq_vec e.(TLB39_Entry_vAddr) (and_vec e.(TLB39_Entry_vMatchMask) vaddr)))) - then - Some - ((0, e)) - else None - end) - : option ((Z * TLB39_Entry))). - -Definition addToTLB39 (asid : mword 16) (vAddr : mword 39) (pAddr : mword 56) (pte : SV39_PTE) (pteAddr : mword 56) '(existT _ level _ : {n : Z & ArithFact (n >= - 0)}) (global : bool) -: M (unit) := - make_TLB39_Entry asid global vAddr pAddr pte (build_ex level) pteAddr >>= fun ent => - write_reg tlb39_ref (Some (ent)) - : M (unit). - -Definition writeTLB39 (idx : Z) (ent : TLB39_Entry) -: M (unit) := - write_reg tlb39_ref (Some (ent)) - : M (unit). - -Definition flushTLB (asid : option (mword 16)) (addr : option (mword 39)) -: M (unit) := - read_reg tlb39_ref >>= fun w__0 : option TLB39_Entry => - let ent : option TLB39_Entry := - match (w__0, asid, addr) with - | (None, _, _) => None - | (Some (e), None, None) => None - | (Some (e), None, Some (a)) => - if ((eq_vec e.(TLB39_Entry_vAddr) (and_vec e.(TLB39_Entry_vMatchMask) a))) then None - else Some (e) - | (Some (e), Some (i), None) => - if ((andb (eq_vec e.(TLB39_Entry_asid) i) (negb e.(TLB39_Entry_global)))) then None - else Some (e) - | (Some (e), Some (i), Some (a)) => - if ((andb (eq_vec e.(TLB39_Entry_asid) i) - (andb (eq_vec e.(TLB39_Entry_vAddr) (and_vec a e.(TLB39_Entry_vMatchMask))) - (negb e.(TLB39_Entry_global))))) then - None - else Some (e) - end in - write_reg tlb39_ref ent - : M (unit). - -Definition translate39 (vAddr : mword 39) (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) '(existT _ level _ : {n : Z & ArithFact (n >= - 0)}) -: M (TR39_Result) := - curAsid64 tt >>= fun asid => - lookupTLB39 asid vAddr >>= fun w__0 : option ((Z * TLB39_Entry)) => - (match w__0 with - | Some (idx,ent) => - let pteBits := Mk_PTE_Bits (_get_SV39_PTE_BITS ent.(TLB39_Entry_pte)) in - checkPTEPermission ac priv mxr do_sum pteBits >>= fun w__1 : bool => - (if ((negb w__1)) then returnm ((TR39_Failure (PTW_No_Permission)) : TR39_Result ) - else - (match (update_PTE_Bits pteBits ac) with - | None => - returnm ((TR39_Address - (or_vec ent.(TLB39_Entry_pAddr) - (EXTZ 56 (and_vec vAddr ent.(TLB39_Entry_vAddrMask))))) - : TR39_Result ) - | Some (pbits) => - (if ((negb (plat_enable_dirty_update tt))) then - returnm ((TR39_Failure - (PTW_PTE_Update)) - : TR39_Result ) - else - let n_ent : TLB39_Entry := ent in - let n_ent := - {[ n_ent with - TLB39_Entry_pte := - (_update_SV39_PTE_BITS ent.(TLB39_Entry_pte) (_get_PTE_Bits_bits pbits)) ]} - : TLB39_Entry in - writeTLB39 idx n_ent >> - checked_mem_write (EXTZ 64 ent.(TLB39_Entry_pteAddr)) 8 - (_get_SV39_PTE_bits ent.(TLB39_Entry_pte)) >>= fun w__2 : MemoryOpResult bool => - match w__2 with - | MemValue (_) => returnm (tt : unit) - | MemException (e) => - (internal_error "invalid physical address in TLB") : M (unit) - end >> - returnm ((TR39_Address - (or_vec ent.(TLB39_Entry_pAddr) - (EXTZ 56 (and_vec vAddr ent.(TLB39_Entry_vAddrMask))))) - : TR39_Result)) - : M (TR39_Result) - end) - : M (TR39_Result)) - : M (TR39_Result) - | None => - curPTB39 tt >>= fun w__6 : mword 56 => - walk39 vAddr ac priv mxr do_sum w__6 (Z.to_nat level) false >>= fun w__7 : PTW_Result => - (match w__7 with - | PTW_Failure (f) => returnm ((TR39_Failure (f)) : TR39_Result ) - | PTW_Success (pAddr,pte,pteAddr,(existT _ level _),global) => - (match (update_PTE_Bits (Mk_PTE_Bits (_get_SV39_PTE_BITS pte)) ac) with - | None => - addToTLB39 asid vAddr pAddr pte pteAddr (build_ex level) global >> - returnm ((TR39_Address - (pAddr)) - : TR39_Result ) - | Some (pbits) => - (if ((negb (plat_enable_dirty_update tt))) then - returnm ((TR39_Failure - (PTW_PTE_Update)) - : TR39_Result ) - else - let w_pte : SV39_PTE := _update_SV39_PTE_BITS pte (_get_PTE_Bits_bits pbits) in - checked_mem_write (EXTZ 64 pteAddr) 8 (_get_SV39_PTE_bits w_pte) >>= fun w__8 : MemoryOpResult bool => - (match w__8 with - | MemValue (_) => - addToTLB39 asid vAddr pAddr w_pte pteAddr (build_ex level) global >> - returnm ((TR39_Address - (pAddr)) - : TR39_Result ) - | MemException (e) => returnm ((TR39_Failure (PTW_Access)) : TR39_Result ) - end) - : M (TR39_Result)) - : M (TR39_Result) - end) - : M (TR39_Result) - end) - : M (TR39_Result) - end) - : M (TR39_Result). - -Definition translationMode (priv : Privilege) -: M (SATPMode) := - (if ((eq_vec ((privLevel_to_bits priv) : mword 2) ((privLevel_to_bits Machine) : mword 2))) - then - returnm (Sbare - : SATPMode) - else - read_reg mstatus_ref >>= fun w__0 : Mstatus => - let arch := architecture (_get_Mstatus_SXL w__0) in - (match arch with - | Some (RV64) => - (read_reg satp_ref : M (mword 64)) >>= fun w__1 : xlenbits => - let mbits : satp_mode := _get_Satp64_Mode (Mk_Satp64 w__1) in - (match (satpMode_of_bits RV64 mbits) with - | Some (m) => returnm (m : SATPMode) - | None => (internal_error "invalid RV64 translation mode in satp") : M (SATPMode) - end) - : M (SATPMode) - | _ => (internal_error "unsupported address translation arch") : M (SATPMode) - end) - : M (SATPMode)) - : M (SATPMode). - -Definition translateAddr (vAddr : mword 64) (ac : AccessType) (rt : ReadType) -: M (TR_Result) := - match rt with - | Instruction => read_reg cur_privilege_ref : M (Privilege) - | Data => - read_reg mstatus_ref >>= fun w__1 : Mstatus => - (if ((eq_vec (_get_Mstatus_MPRV w__1) ((bool_to_bits true) : mword 1))) then - read_reg mstatus_ref >>= fun w__2 : Mstatus => - returnm ((privLevel_of_bits (_get_Mstatus_MPP w__2)) - : Privilege) - else read_reg cur_privilege_ref : M (Privilege)) - : M (Privilege) - end >>= fun effPriv : Privilege => - read_reg mstatus_ref >>= fun w__5 : Mstatus => - let mxr : bool := eq_vec (_get_Mstatus_MXR w__5) ((bool_to_bits true) : mword 1) in - read_reg mstatus_ref >>= fun w__6 : Mstatus => - let do_sum : bool := eq_vec (_get_Mstatus_SUM w__6) ((bool_to_bits true) : mword 1) in - translationMode effPriv >>= fun mode : SATPMode => - (match mode with - | Sbare => returnm ((TR_Address (vAddr)) : TR_Result ) - | SV39 => - translate39 (subrange_vec_dec vAddr 38 0) ac effPriv mxr do_sum - (build_ex (projT1 (sub_range (build_ex SV39_LEVELS) (build_ex 1)))) >>= fun w__7 : TR39_Result => - returnm ((match w__7 with - | TR39_Address (pa) => TR_Address (EXTZ 64 pa) - | TR39_Failure (f) => TR_Failure (translationException ac f) - end) - : TR_Result) - end) - : M (TR_Result). - -Definition encdec_uop_forwards (arg_ : uop) -: mword 7 := - match arg_ with - | RISCV_LUI => (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : mword 7) - | RISCV_AUIPC => (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : mword 7) - end. - -Definition encdec_uop_backwards (arg_ : mword 7) -: uop := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : mword 7))) then RISCV_LUI - else RISCV_AUIPC. - -Definition encdec_uop_forwards_matches (arg_ : uop) -: bool := - match arg_ with | RISCV_LUI => true | RISCV_AUIPC => true end. - -Definition encdec_uop_backwards_matches (arg_ : mword 7) -: bool := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : mword 7))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : mword 7))) then true - else false. - -Definition utype_mnemonic_forwards (arg_ : uop) -: string := - match arg_ with | RISCV_LUI => "lui" | RISCV_AUIPC => "auipc" end. - -Definition utype_mnemonic_backwards (arg_ : string) -: M (uop) := - (match arg_ with - | "lui" => returnm (RISCV_LUI : uop) - | "auipc" => returnm (RISCV_AUIPC : uop) - | _ => exit tt : M (uop) - end) - : M (uop). - -Definition utype_mnemonic_forwards_matches (arg_ : uop) -: bool := - match arg_ with | RISCV_LUI => true | RISCV_AUIPC => true end. - -Definition utype_mnemonic_backwards_matches (arg_ : string) -: bool := - match arg_ with | "lui" => true | "auipc" => true | _ => false end. - -Definition utype_mnemonic_matches_prefix (arg_ : string) -: option ((uop * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1225_ := arg_ in - if ((andb (string_startswith _stringappend_1225_ "lui") - (match (string_drop _stringappend_1225_ (build_ex (projT1 (string_length "lui")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1225_ (build_ex (projT1 (string_length "lui")))) with - | s_ => - Some - ((RISCV_LUI, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1225_ "auipc") - (match (string_drop _stringappend_1225_ (build_ex (projT1 (string_length "auipc")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1225_ (build_ex (projT1 (string_length "auipc")))) with - | s_ => - Some - ((RISCV_AUIPC, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition encdec_bop_forwards (arg_ : bop) -: mword 3 := - match arg_ with - | RISCV_BEQ => (vec_of_bits [B0;B0;B0] : mword 3) - | RISCV_BNE => (vec_of_bits [B0;B0;B1] : mword 3) - | RISCV_BLT => (vec_of_bits [B1;B0;B0] : mword 3) - | RISCV_BGE => (vec_of_bits [B1;B0;B1] : mword 3) - | RISCV_BLTU => (vec_of_bits [B1;B1;B0] : mword 3) - | RISCV_BGEU => (vec_of_bits [B1;B1;B1] : mword 3) - end. - -Definition encdec_bop_backwards (arg_ : mword 3) -: bop := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then RISCV_BEQ - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then RISCV_BNE - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then RISCV_BLT - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then RISCV_BGE - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then RISCV_BLTU - else RISCV_BGEU. - -Definition encdec_bop_forwards_matches (arg_ : bop) -: bool := - match arg_ with - | RISCV_BEQ => true - | RISCV_BNE => true - | RISCV_BLT => true - | RISCV_BGE => true - | RISCV_BLTU => true - | RISCV_BGEU => true - end. - -Definition encdec_bop_backwards_matches (arg_ : mword 3) -: bool := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1] : mword 3))) then true - else false. - -Definition btype_mnemonic_forwards (arg_ : bop) -: string := - match arg_ with - | RISCV_BEQ => "beq" - | RISCV_BNE => "bne" - | RISCV_BLT => "blt" - | RISCV_BGE => "bge" - | RISCV_BLTU => "bltu" - | RISCV_BGEU => "bgeu" - end. - -Definition btype_mnemonic_backwards (arg_ : string) -: M (bop) := - (match arg_ with - | "beq" => returnm (RISCV_BEQ : bop) - | "bne" => returnm (RISCV_BNE : bop) - | "blt" => returnm (RISCV_BLT : bop) - | "bge" => returnm (RISCV_BGE : bop) - | "bltu" => returnm (RISCV_BLTU : bop) - | "bgeu" => returnm (RISCV_BGEU : bop) - | _ => exit tt : M (bop) - end) - : M (bop). - -Definition btype_mnemonic_forwards_matches (arg_ : bop) -: bool := - match arg_ with - | RISCV_BEQ => true - | RISCV_BNE => true - | RISCV_BLT => true - | RISCV_BGE => true - | RISCV_BLTU => true - | RISCV_BGEU => true - end. - -Definition btype_mnemonic_backwards_matches (arg_ : string) -: bool := - match arg_ with - | "beq" => true - | "bne" => true - | "blt" => true - | "bge" => true - | "bltu" => true - | "bgeu" => true - | _ => false - end. - -Definition btype_mnemonic_matches_prefix (arg_ : string) -: option ((bop * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1219_ := arg_ in - if ((andb (string_startswith _stringappend_1219_ "beq") - (match (string_drop _stringappend_1219_ (build_ex (projT1 (string_length "beq")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1219_ (build_ex (projT1 (string_length "beq")))) with - | s_ => - Some - ((RISCV_BEQ, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1219_ "bne") - (match (string_drop _stringappend_1219_ (build_ex (projT1 (string_length "bne")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1219_ (build_ex (projT1 (string_length "bne")))) with - | s_ => - Some - ((RISCV_BNE, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1219_ "blt") - (match (string_drop _stringappend_1219_ (build_ex (projT1 (string_length "blt")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1219_ (build_ex (projT1 (string_length "blt")))) with - | s_ => - Some - ((RISCV_BLT, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1219_ "bge") - (match (string_drop _stringappend_1219_ (build_ex (projT1 (string_length "bge")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1219_ (build_ex (projT1 (string_length "bge")))) with - | s_ => - Some - ((RISCV_BGE, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1219_ "bltu") - (match (string_drop _stringappend_1219_ (build_ex (projT1 (string_length "bltu")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1219_ (build_ex (projT1 (string_length "bltu")))) with - | s_ => - Some - ((RISCV_BLTU, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1219_ "bgeu") - (match (string_drop _stringappend_1219_ (build_ex (projT1 (string_length "bgeu")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1219_ (build_ex (projT1 (string_length "bgeu")))) with - | s_ => - Some - ((RISCV_BGEU, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition encdec_iop_forwards (arg_ : iop) -: mword 3 := - match arg_ with - | RISCV_ADDI => (vec_of_bits [B0;B0;B0] : mword 3) - | RISCV_SLTI => (vec_of_bits [B0;B1;B0] : mword 3) - | RISCV_SLTIU => (vec_of_bits [B0;B1;B1] : mword 3) - | RISCV_XORI => (vec_of_bits [B1;B0;B0] : mword 3) - | RISCV_ORI => (vec_of_bits [B1;B1;B0] : mword 3) - | RISCV_ANDI => (vec_of_bits [B1;B1;B1] : mword 3) - end. - -Definition encdec_iop_backwards (arg_ : mword 3) -: iop := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then RISCV_ADDI - else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then RISCV_SLTI - else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then RISCV_SLTIU - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then RISCV_XORI - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then RISCV_ORI - else RISCV_ANDI. - -Definition encdec_iop_forwards_matches (arg_ : iop) -: bool := - match arg_ with - | RISCV_ADDI => true - | RISCV_SLTI => true - | RISCV_SLTIU => true - | RISCV_XORI => true - | RISCV_ORI => true - | RISCV_ANDI => true - end. - -Definition encdec_iop_backwards_matches (arg_ : mword 3) -: bool := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1] : mword 3))) then true - else false. - -Definition itype_mnemonic_forwards (arg_ : iop) -: string := - match arg_ with - | RISCV_ADDI => "addi" - | RISCV_SLTI => "slti" - | RISCV_SLTIU => "sltiu" - | RISCV_XORI => "xori" - | RISCV_ORI => "ori" - | RISCV_ANDI => "andi" - end. - -Definition itype_mnemonic_backwards (arg_ : string) -: M (iop) := - (match arg_ with - | "addi" => returnm (RISCV_ADDI : iop) - | "slti" => returnm (RISCV_SLTI : iop) - | "sltiu" => returnm (RISCV_SLTIU : iop) - | "xori" => returnm (RISCV_XORI : iop) - | "ori" => returnm (RISCV_ORI : iop) - | "andi" => returnm (RISCV_ANDI : iop) - | _ => exit tt : M (iop) - end) - : M (iop). - -Definition itype_mnemonic_forwards_matches (arg_ : iop) -: bool := - match arg_ with - | RISCV_ADDI => true - | RISCV_SLTI => true - | RISCV_SLTIU => true - | RISCV_XORI => true - | RISCV_ORI => true - | RISCV_ANDI => true - end. - -Definition itype_mnemonic_backwards_matches (arg_ : string) -: bool := - match arg_ with - | "addi" => true - | "slti" => true - | "sltiu" => true - | "xori" => true - | "ori" => true - | "andi" => true - | _ => false - end. - -Definition itype_mnemonic_matches_prefix (arg_ : string) -: option ((iop * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1213_ := arg_ in - if ((andb (string_startswith _stringappend_1213_ "addi") - (match (string_drop _stringappend_1213_ (build_ex (projT1 (string_length "addi")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1213_ (build_ex (projT1 (string_length "addi")))) with - | s_ => - Some - ((RISCV_ADDI, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1213_ "slti") - (match (string_drop _stringappend_1213_ (build_ex (projT1 (string_length "slti")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1213_ (build_ex (projT1 (string_length "slti")))) with - | s_ => - Some - ((RISCV_SLTI, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1213_ "sltiu") - (match (string_drop _stringappend_1213_ (build_ex (projT1 (string_length "sltiu")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1213_ (build_ex (projT1 (string_length "sltiu")))) with - | s_ => - Some - ((RISCV_SLTIU, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1213_ "xori") - (match (string_drop _stringappend_1213_ (build_ex (projT1 (string_length "xori")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1213_ (build_ex (projT1 (string_length "xori")))) with - | s_ => - Some - ((RISCV_XORI, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1213_ "ori") - (match (string_drop _stringappend_1213_ (build_ex (projT1 (string_length "ori")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1213_ (build_ex (projT1 (string_length "ori")))) with - | s_ => - Some - ((RISCV_ORI, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1213_ "andi") - (match (string_drop _stringappend_1213_ (build_ex (projT1 (string_length "andi")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1213_ (build_ex (projT1 (string_length "andi")))) with - | s_ => - Some - ((RISCV_ANDI, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition encdec_sop_forwards (arg_ : sop) -: mword 3 := - match arg_ with - | RISCV_SLLI => (vec_of_bits [B0;B0;B1] : mword 3) - | RISCV_SRLI => (vec_of_bits [B1;B0;B1] : mword 3) - | RISCV_SRAI => (vec_of_bits [B1;B0;B1] : mword 3) - end. - -Definition encdec_sop_backwards (arg_ : mword 3) -: sop := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then RISCV_SLLI - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then RISCV_SRLI - else RISCV_SRAI. - -Definition encdec_sop_forwards_matches (arg_ : sop) -: bool := - match arg_ with | RISCV_SLLI => true | RISCV_SRLI => true | RISCV_SRAI => true end. - -Definition encdec_sop_backwards_matches (arg_ : mword 3) -: bool := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then true - else false. - -Definition shiftiop_mnemonic_forwards (arg_ : sop) -: string := - match arg_ with | RISCV_SLLI => "slli" | RISCV_SRLI => "srli" | RISCV_SRAI => "srai" end. - -Definition shiftiop_mnemonic_backwards (arg_ : string) -: M (sop) := - (match arg_ with - | "slli" => returnm (RISCV_SLLI : sop) - | "srli" => returnm (RISCV_SRLI : sop) - | "srai" => returnm (RISCV_SRAI : sop) - | _ => exit tt : M (sop) - end) - : M (sop). - -Definition shiftiop_mnemonic_forwards_matches (arg_ : sop) -: bool := - match arg_ with | RISCV_SLLI => true | RISCV_SRLI => true | RISCV_SRAI => true end. - -Definition shiftiop_mnemonic_backwards_matches (arg_ : string) -: bool := - match arg_ with | "slli" => true | "srli" => true | "srai" => true | _ => false end. - -Definition shiftiop_mnemonic_matches_prefix (arg_ : string) -: option ((sop * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1210_ := arg_ in - if ((andb (string_startswith _stringappend_1210_ "slli") - (match (string_drop _stringappend_1210_ (build_ex (projT1 (string_length "slli")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1210_ (build_ex (projT1 (string_length "slli")))) with - | s_ => - Some - ((RISCV_SLLI, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1210_ "srli") - (match (string_drop _stringappend_1210_ (build_ex (projT1 (string_length "srli")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1210_ (build_ex (projT1 (string_length "srli")))) with - | s_ => - Some - ((RISCV_SRLI, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1210_ "srai") - (match (string_drop _stringappend_1210_ (build_ex (projT1 (string_length "srai")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1210_ (build_ex (projT1 (string_length "srai")))) with - | s_ => - Some - ((RISCV_SRAI, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition rtype_mnemonic_forwards (arg_ : rop) -: string := - match arg_ with - | RISCV_ADD => "add" - | RISCV_SUB => "sub" - | RISCV_SLL => "sll" - | RISCV_SLT => "slt" - | RISCV_SLTU => "sltu" - | RISCV_XOR => "xor" - | RISCV_SRL => "srl" - | RISCV_SRA => "sra" - | RISCV_OR => "or" - | RISCV_AND => "and" - end. - -Definition rtype_mnemonic_backwards (arg_ : string) -: M (rop) := - (match arg_ with - | "add" => returnm (RISCV_ADD : rop) - | "sub" => returnm (RISCV_SUB : rop) - | "sll" => returnm (RISCV_SLL : rop) - | "slt" => returnm (RISCV_SLT : rop) - | "sltu" => returnm (RISCV_SLTU : rop) - | "xor" => returnm (RISCV_XOR : rop) - | "srl" => returnm (RISCV_SRL : rop) - | "sra" => returnm (RISCV_SRA : rop) - | "or" => returnm (RISCV_OR : rop) - | "and" => returnm (RISCV_AND : rop) - | _ => exit tt : M (rop) - end) - : M (rop). - -Definition rtype_mnemonic_forwards_matches (arg_ : rop) -: bool := - match arg_ with - | RISCV_ADD => true - | RISCV_SUB => true - | RISCV_SLL => true - | RISCV_SLT => true - | RISCV_SLTU => true - | RISCV_XOR => true - | RISCV_SRL => true - | RISCV_SRA => true - | RISCV_OR => true - | RISCV_AND => true - end. - -Definition rtype_mnemonic_backwards_matches (arg_ : string) -: bool := - match arg_ with - | "add" => true - | "sub" => true - | "sll" => true - | "slt" => true - | "sltu" => true - | "xor" => true - | "srl" => true - | "sra" => true - | "or" => true - | "and" => true - | _ => false - end. - -Definition rtype_mnemonic_matches_prefix (arg_ : string) -: option ((rop * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1200_ := arg_ in - if ((andb (string_startswith _stringappend_1200_ "add") - (match (string_drop _stringappend_1200_ (build_ex (projT1 (string_length "add")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1200_ (build_ex (projT1 (string_length "add")))) with - | s_ => - Some - ((RISCV_ADD, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1200_ "sub") - (match (string_drop _stringappend_1200_ (build_ex (projT1 (string_length "sub")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1200_ (build_ex (projT1 (string_length "sub")))) with - | s_ => - Some - ((RISCV_SUB, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1200_ "sll") - (match (string_drop _stringappend_1200_ (build_ex (projT1 (string_length "sll")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1200_ (build_ex (projT1 (string_length "sll")))) with - | s_ => - Some - ((RISCV_SLL, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1200_ "slt") - (match (string_drop _stringappend_1200_ (build_ex (projT1 (string_length "slt")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1200_ (build_ex (projT1 (string_length "slt")))) with - | s_ => - Some - ((RISCV_SLT, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1200_ "sltu") - (match (string_drop _stringappend_1200_ (build_ex (projT1 (string_length "sltu")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1200_ (build_ex (projT1 (string_length "sltu")))) with - | s_ => - Some - ((RISCV_SLTU, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1200_ "xor") - (match (string_drop _stringappend_1200_ (build_ex (projT1 (string_length "xor")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1200_ (build_ex (projT1 (string_length "xor")))) with - | s_ => - Some - ((RISCV_XOR, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1200_ "srl") - (match (string_drop _stringappend_1200_ (build_ex (projT1 (string_length "srl")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1200_ (build_ex (projT1 (string_length "srl")))) with - | s_ => - Some - ((RISCV_SRL, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1200_ "sra") - (match (string_drop _stringappend_1200_ (build_ex (projT1 (string_length "sra")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1200_ (build_ex (projT1 (string_length "sra")))) with - | s_ => - Some - ((RISCV_SRA, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1200_ "or") - (match (string_drop _stringappend_1200_ (build_ex (projT1 (string_length "or")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1200_ (build_ex (projT1 (string_length "or")))) with - | s_ => - Some - ((RISCV_OR, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1200_ "and") - (match (string_drop _stringappend_1200_ (build_ex (projT1 (string_length "and")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1200_ (build_ex (projT1 (string_length "and")))) with - | s_ => - Some - ((RISCV_AND, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition extend_value {n : Z} (is_unsigned : bool) (value : MemoryOpResult (mword (8 * n))) `{ArithFact ((0 + 1) <= - n /\ - n <= 8)} -: MemoryOpResult (mword 64) := - match value with - | MemValue (v) => MemValue (if (is_unsigned) then EXTZ 64 v else (EXTS 64 v) : xlenbits) - | MemException (e) => MemException (e) - end. - -Definition process_load {n : Z} (rd : mword 5) (addr : mword 64) (value : MemoryOpResult (mword (8 * n))) (is_unsigned : bool) `{ArithFact ((0 + 1) <= - n /\ - n <= 8)} -: M (bool) := - (match (extend_value is_unsigned value) with - | MemValue (result) => - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {syn_n : Z & ArithFact (0 <= syn_n /\ (syn_n + 1) <= 32)})) result >> - returnm (true - : bool) - | MemException (e) => handle_mem_exception addr e >> returnm (false : bool) - end) - : M (bool). - -Definition check_misaligned (vaddr : mword 64) (width : word_width) -: M (bool) := - (if ((plat_enable_misaligned_access tt)) then returnm (false : bool) - else - (match width with - | BYTE => returnm (false : bool) - | HALF => - bit_to_bool (access_vec_dec vaddr 0) >>= fun w__0 : bool => - returnm ((Bool.eqb (w__0 : bool) true) - : bool) - | WORD => - (or_boolM - (bit_to_bool (access_vec_dec vaddr 0) >>= fun w__1 : bool => - returnm ((Bool.eqb (w__1 : bool) true) - : bool)) - (bit_to_bool (access_vec_dec vaddr 1) >>= fun w__2 : bool => - returnm ((Bool.eqb (w__2 : bool) true) - : bool))) - : M (bool) - | DOUBLE => - (or_boolM - (bit_to_bool (access_vec_dec vaddr 0) >>= fun w__4 : bool => - returnm ((Bool.eqb (w__4 : bool) true) - : bool)) - ((or_boolM - (bit_to_bool (access_vec_dec vaddr 1) >>= fun w__5 : bool => - returnm ((Bool.eqb (w__5 : bool) true) - : bool)) - (bit_to_bool (access_vec_dec vaddr 2) >>= fun w__6 : bool => - returnm ((Bool.eqb (w__6 : bool) true) - : bool))) - : M (bool))) - : M (bool) - end) - : M (bool)) - : M (bool). - -Definition maybe_aq_forwards (arg_ : bool) -: string := - match arg_ with | true => ".aq" | false => "" end. - -Definition maybe_aq_backwards (arg_ : string) -: M (bool) := - (match arg_ with - | ".aq" => returnm (true : bool) - | "" => returnm (false : bool) - | _ => exit tt : M (bool) - end) - : M (bool). - -Definition maybe_aq_forwards_matches (arg_ : bool) -: bool := - match arg_ with | true => true | false => true end. - -Definition maybe_aq_backwards_matches (arg_ : string) -: bool := - match arg_ with | ".aq" => true | "" => true | _ => false end. - -Definition maybe_aq_matches_prefix (arg_ : string) -: option ((bool * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1198_ := arg_ in - if ((andb (string_startswith _stringappend_1198_ ".aq") - (match (string_drop _stringappend_1198_ (build_ex (projT1 (string_length ".aq")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1198_ (build_ex (projT1 (string_length ".aq")))) with - | s_ => - Some - ((true, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1198_ "") - (match (string_drop _stringappend_1198_ (build_ex (projT1 (string_length "")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1198_ (build_ex (projT1 (string_length "")))) with - | s_ => - Some - ((false, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition maybe_rl_forwards (arg_ : bool) -: string := - match arg_ with | true => ".rl" | false => "" end. - -Definition maybe_rl_backwards (arg_ : string) -: M (bool) := - (match arg_ with - | ".rl" => returnm (true : bool) - | "" => returnm (false : bool) - | _ => exit tt : M (bool) - end) - : M (bool). - -Definition maybe_rl_forwards_matches (arg_ : bool) -: bool := - match arg_ with | true => true | false => true end. - -Definition maybe_rl_backwards_matches (arg_ : string) -: bool := - match arg_ with | ".rl" => true | "" => true | _ => false end. - -Definition maybe_rl_matches_prefix (arg_ : string) -: option ((bool * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1196_ := arg_ in - if ((andb (string_startswith _stringappend_1196_ ".rl") - (match (string_drop _stringappend_1196_ (build_ex (projT1 (string_length ".rl")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1196_ (build_ex (projT1 (string_length ".rl")))) with - | s_ => - Some - ((true, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1196_ "") - (match (string_drop _stringappend_1196_ (build_ex (projT1 (string_length "")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1196_ (build_ex (projT1 (string_length "")))) with - | s_ => - Some - ((false, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition maybe_u_forwards (arg_ : bool) -: string := - match arg_ with | true => "u" | false => "" end. - -Definition maybe_u_backwards (arg_ : string) -: M (bool) := - (match arg_ with - | "u" => returnm (true : bool) - | "" => returnm (false : bool) - | _ => exit tt : M (bool) - end) - : M (bool). - -Definition maybe_u_forwards_matches (arg_ : bool) -: bool := - match arg_ with | true => true | false => true end. - -Definition maybe_u_backwards_matches (arg_ : string) -: bool := - match arg_ with | "u" => true | "" => true | _ => false end. - -Definition maybe_u_matches_prefix (arg_ : string) -: option ((bool * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1194_ := arg_ in - if ((andb (string_startswith _stringappend_1194_ "u") - (match (string_drop _stringappend_1194_ (build_ex (projT1 (string_length "u")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1194_ (build_ex (projT1 (string_length "u")))) with - | s_ => - Some - ((true, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1194_ "") - (match (string_drop _stringappend_1194_ (build_ex (projT1 (string_length "")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1194_ (build_ex (projT1 (string_length "")))) with - | s_ => - Some - ((false, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition shiftw_mnemonic_forwards (arg_ : sop) -: string := - match arg_ with | RISCV_SLLI => "slli" | RISCV_SRLI => "srli" | RISCV_SRAI => "srai" end. - -Definition shiftw_mnemonic_backwards (arg_ : string) -: M (sop) := - (match arg_ with - | "slli" => returnm (RISCV_SLLI : sop) - | "srli" => returnm (RISCV_SRLI : sop) - | "srai" => returnm (RISCV_SRAI : sop) - | _ => exit tt : M (sop) - end) - : M (sop). - -Definition shiftw_mnemonic_forwards_matches (arg_ : sop) -: bool := - match arg_ with | RISCV_SLLI => true | RISCV_SRLI => true | RISCV_SRAI => true end. - -Definition shiftw_mnemonic_backwards_matches (arg_ : string) -: bool := - match arg_ with | "slli" => true | "srli" => true | "srai" => true | _ => false end. - -Definition shiftw_mnemonic_matches_prefix (arg_ : string) -: option ((sop * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1191_ := arg_ in - if ((andb (string_startswith _stringappend_1191_ "slli") - (match (string_drop _stringappend_1191_ (build_ex (projT1 (string_length "slli")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1191_ (build_ex (projT1 (string_length "slli")))) with - | s_ => - Some - ((RISCV_SLLI, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1191_ "srli") - (match (string_drop _stringappend_1191_ (build_ex (projT1 (string_length "srli")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1191_ (build_ex (projT1 (string_length "srli")))) with - | s_ => - Some - ((RISCV_SRLI, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1191_ "srai") - (match (string_drop _stringappend_1191_ (build_ex (projT1 (string_length "srai")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1191_ (build_ex (projT1 (string_length "srai")))) with - | s_ => - Some - ((RISCV_SRAI, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition rtypew_mnemonic_forwards (arg_ : ropw) -: string := - match arg_ with - | RISCV_ADDW => "addw" - | RISCV_SUBW => "subw" - | RISCV_SLLW => "sllw" - | RISCV_SRLW => "srlw" - | RISCV_SRAW => "sraw" - end. - -Definition rtypew_mnemonic_backwards (arg_ : string) -: M (ropw) := - (match arg_ with - | "addw" => returnm (RISCV_ADDW : ropw) - | "subw" => returnm (RISCV_SUBW : ropw) - | "sllw" => returnm (RISCV_SLLW : ropw) - | "srlw" => returnm (RISCV_SRLW : ropw) - | "sraw" => returnm (RISCV_SRAW : ropw) - | _ => exit tt : M (ropw) - end) - : M (ropw). - -Definition rtypew_mnemonic_forwards_matches (arg_ : ropw) -: bool := - match arg_ with - | RISCV_ADDW => true - | RISCV_SUBW => true - | RISCV_SLLW => true - | RISCV_SRLW => true - | RISCV_SRAW => true - end. - -Definition rtypew_mnemonic_backwards_matches (arg_ : string) -: bool := - match arg_ with - | "addw" => true - | "subw" => true - | "sllw" => true - | "srlw" => true - | "sraw" => true - | _ => false - end. - -Definition rtypew_mnemonic_matches_prefix (arg_ : string) -: option ((ropw * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1186_ := arg_ in - if ((andb (string_startswith _stringappend_1186_ "addw") - (match (string_drop _stringappend_1186_ (build_ex (projT1 (string_length "addw")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1186_ (build_ex (projT1 (string_length "addw")))) with - | s_ => - Some - ((RISCV_ADDW, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1186_ "subw") - (match (string_drop _stringappend_1186_ (build_ex (projT1 (string_length "subw")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1186_ (build_ex (projT1 (string_length "subw")))) with - | s_ => - Some - ((RISCV_SUBW, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1186_ "sllw") - (match (string_drop _stringappend_1186_ (build_ex (projT1 (string_length "sllw")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1186_ (build_ex (projT1 (string_length "sllw")))) with - | s_ => - Some - ((RISCV_SLLW, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1186_ "srlw") - (match (string_drop _stringappend_1186_ (build_ex (projT1 (string_length "srlw")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1186_ (build_ex (projT1 (string_length "srlw")))) with - | s_ => - Some - ((RISCV_SRLW, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1186_ "sraw") - (match (string_drop _stringappend_1186_ (build_ex (projT1 (string_length "sraw")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1186_ (build_ex (projT1 (string_length "sraw")))) with - | s_ => - Some - ((RISCV_SRAW, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition shiftiwop_mnemonic_forwards (arg_ : sopw) -: string := - match arg_ with | RISCV_SLLIW => "slliw" | RISCV_SRLIW => "srliw" | RISCV_SRAIW => "sraiw" end. - -Definition shiftiwop_mnemonic_backwards (arg_ : string) -: M (sopw) := - (match arg_ with - | "slliw" => returnm (RISCV_SLLIW : sopw) - | "srliw" => returnm (RISCV_SRLIW : sopw) - | "sraiw" => returnm (RISCV_SRAIW : sopw) - | _ => exit tt : M (sopw) - end) - : M (sopw). - -Definition shiftiwop_mnemonic_forwards_matches (arg_ : sopw) -: bool := - match arg_ with | RISCV_SLLIW => true | RISCV_SRLIW => true | RISCV_SRAIW => true end. - -Definition shiftiwop_mnemonic_backwards_matches (arg_ : string) -: bool := - match arg_ with | "slliw" => true | "srliw" => true | "sraiw" => true | _ => false end. - -Definition shiftiwop_mnemonic_matches_prefix (arg_ : string) -: option ((sopw * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1183_ := arg_ in - if ((andb (string_startswith _stringappend_1183_ "slliw") - (match (string_drop _stringappend_1183_ (build_ex (projT1 (string_length "slliw")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1183_ (build_ex (projT1 (string_length "slliw")))) with - | s_ => - Some - ((RISCV_SLLIW, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1183_ "srliw") - (match (string_drop _stringappend_1183_ (build_ex (projT1 (string_length "srliw")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1183_ (build_ex (projT1 (string_length "srliw")))) with - | s_ => - Some - ((RISCV_SRLIW, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1183_ "sraiw") - (match (string_drop _stringappend_1183_ (build_ex (projT1 (string_length "sraiw")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1183_ (build_ex (projT1 (string_length "sraiw")))) with - | s_ => - Some - ((RISCV_SRAIW, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition encdec_mul_op_forwards (arg0 : bool) (arg1 : bool) (arg2 : bool) -: M (mword 3) := - let arg_ := (arg0, arg1, arg2) in - (match arg_ with - | (false, true, true) => returnm ((vec_of_bits [B0;B0;B0] : mword 3) : mword 3) - | (true, true, true) => returnm ((vec_of_bits [B0;B0;B1] : mword 3) : mword 3) - | (true, true, false) => returnm ((vec_of_bits [B0;B1;B0] : mword 3) : mword 3) - | (true, false, false) => returnm ((vec_of_bits [B0;B1;B1] : mword 3) : mword 3) - | _ => exit tt : M (mword 3) - end) - : M (mword 3). - -Definition encdec_mul_op_backwards (arg_ : mword 3) -: (bool * bool * bool) := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then (false, true, true) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then (true, true, true) - else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then (true, true, false) - else (true, false, false). - -Definition encdec_mul_op_forwards_matches (arg0 : bool) (arg1 : bool) (arg2 : bool) -: bool := - let arg_ := (arg0, arg1, arg2) in - match arg_ with - | (false, true, true) => true - | (true, true, true) => true - | (true, true, false) => true - | (true, false, false) => true - | _ => false - end. - -Definition encdec_mul_op_backwards_matches (arg_ : mword 3) -: bool := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then true - else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then true - else false. - -Definition mul_mnemonic_forwards (arg0 : bool) (arg1 : bool) (arg2 : bool) -: M (string) := - let arg_ := (arg0, arg1, arg2) in - (match arg_ with - | (false, true, true) => returnm ("mul" : string) - | (true, true, true) => returnm ("mulh" : string) - | (true, true, false) => returnm ("mulhsu" : string) - | (true, false, false) => returnm ("mulhu" : string) - | _ => exit tt : M (string) - end) - : M (string). - -Definition mul_mnemonic_backwards (arg_ : string) -: M ((bool * bool * bool)) := - (match arg_ with - | "mul" => returnm (false, true, true) - | "mulh" => returnm (true, true, true) - | "mulhsu" => returnm (true, true, false) - | "mulhu" => returnm (true, false, false) - | _ => exit tt : M ((bool * bool * bool)) - end) - : M ((bool * bool * bool)). - -Definition mul_mnemonic_forwards_matches (arg0 : bool) (arg1 : bool) (arg2 : bool) -: bool := - let arg_ := (arg0, arg1, arg2) in - match arg_ with - | (false, true, true) => true - | (true, true, true) => true - | (true, true, false) => true - | (true, false, false) => true - | _ => false - end. - -Definition mul_mnemonic_backwards_matches (arg_ : string) -: bool := - match arg_ with - | "mul" => true - | "mulh" => true - | "mulhsu" => true - | "mulhu" => true - | _ => false - end. - -Definition mul_mnemonic_matches_prefix (arg_ : string) -: option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1179_ := arg_ in - if ((andb (string_startswith _stringappend_1179_ "mul") - (match (string_drop _stringappend_1179_ (build_ex (projT1 (string_length "mul")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1179_ (build_ex (projT1 (string_length "mul")))) with - | s_ => - Some - (((false, true, true), build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1179_ "mulh") - (match (string_drop _stringappend_1179_ (build_ex (projT1 (string_length "mulh")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1179_ (build_ex (projT1 (string_length "mulh")))) with - | s_ => - Some - (((true, true, true), build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1179_ "mulhsu") - (match (string_drop _stringappend_1179_ (build_ex (projT1 (string_length "mulhsu")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1179_ (build_ex (projT1 (string_length "mulhsu")))) with - | s_ => - Some - (((true, true, false), build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1179_ "mulhu") - (match (string_drop _stringappend_1179_ (build_ex (projT1 (string_length "mulhu")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1179_ (build_ex (projT1 (string_length "mulhu")))) with - | s_ => - Some - (((true, false, false), build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition maybe_not_u_forwards (arg_ : bool) -: string := - match arg_ with | false => "u" | true => "" end. - -Definition maybe_not_u_backwards (arg_ : string) -: M (bool) := - (match arg_ with - | "u" => returnm (false : bool) - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool). - -Definition maybe_not_u_forwards_matches (arg_ : bool) -: bool := - match arg_ with | false => true | true => true end. - -Definition maybe_not_u_backwards_matches (arg_ : string) -: bool := - match arg_ with | "u" => true | "" => true | _ => false end. - -Definition maybe_not_u_matches_prefix (arg_ : string) -: option ((bool * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1177_ := arg_ in - if ((andb (string_startswith _stringappend_1177_ "u") - (match (string_drop _stringappend_1177_ (build_ex (projT1 (string_length "u")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1177_ (build_ex (projT1 (string_length "u")))) with - | s_ => - Some - ((false, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1177_ "") - (match (string_drop _stringappend_1177_ (build_ex (projT1 (string_length "")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1177_ (build_ex (projT1 (string_length "")))) with - | s_ => - Some - ((true, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition bit_maybe_r_forwards (arg_ : mword 1) -: string := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then "r" - else "". - -Definition bit_maybe_r_backwards (arg_ : string) -: M (mword 1) := - (match arg_ with - | "r" => returnm ((vec_of_bits [B1] : mword 1) : mword 1) - | "" => returnm ((vec_of_bits [B0] : mword 1) : mword 1) - | _ => exit tt : M (mword 1) - end) - : M (mword 1). - -Definition bit_maybe_r_forwards_matches (arg_ : mword 1) -: bool := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true - else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true - else false. - -Definition bit_maybe_r_backwards_matches (arg_ : string) -: bool := - match arg_ with | "r" => true | "" => true | _ => false end. - -Definition bit_maybe_r_matches_prefix (arg_ : string) -: option ((mword 1 * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1175_ := arg_ in - if ((andb (string_startswith _stringappend_1175_ "r") - (match (string_drop _stringappend_1175_ (build_ex (projT1 (string_length "r")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1175_ (build_ex (projT1 (string_length "r")))) with - | s_ => - Some - (((vec_of_bits [B1] : mword 1), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1175_ "") - (match (string_drop _stringappend_1175_ (build_ex (projT1 (string_length "")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1175_ (build_ex (projT1 (string_length "")))) with - | s_ => - Some - (((vec_of_bits [B0] : mword 1), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition bit_maybe_w_forwards (arg_ : mword 1) -: string := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then "w" - else "". - -Definition bit_maybe_w_backwards (arg_ : string) -: M (mword 1) := - (match arg_ with - | "w" => returnm ((vec_of_bits [B1] : mword 1) : mword 1) - | "" => returnm ((vec_of_bits [B0] : mword 1) : mword 1) - | _ => exit tt : M (mword 1) - end) - : M (mword 1). - -Definition bit_maybe_w_forwards_matches (arg_ : mword 1) -: bool := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true - else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true - else false. - -Definition bit_maybe_w_backwards_matches (arg_ : string) -: bool := - match arg_ with | "w" => true | "" => true | _ => false end. - -Definition bit_maybe_w_matches_prefix (arg_ : string) -: option ((mword 1 * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1173_ := arg_ in - if ((andb (string_startswith _stringappend_1173_ "w") - (match (string_drop _stringappend_1173_ (build_ex (projT1 (string_length "w")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1173_ (build_ex (projT1 (string_length "w")))) with - | s_ => - Some - (((vec_of_bits [B1] : mword 1), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1173_ "") - (match (string_drop _stringappend_1173_ (build_ex (projT1 (string_length "")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1173_ (build_ex (projT1 (string_length "")))) with - | s_ => - Some - (((vec_of_bits [B0] : mword 1), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition bit_maybe_i_forwards (arg_ : mword 1) -: string := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then "i" - else "". - -Definition bit_maybe_i_backwards (arg_ : string) -: M (mword 1) := - (match arg_ with - | "i" => returnm ((vec_of_bits [B1] : mword 1) : mword 1) - | "" => returnm ((vec_of_bits [B0] : mword 1) : mword 1) - | _ => exit tt : M (mword 1) - end) - : M (mword 1). - -Definition bit_maybe_i_forwards_matches (arg_ : mword 1) -: bool := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true - else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true - else false. - -Definition bit_maybe_i_backwards_matches (arg_ : string) -: bool := - match arg_ with | "i" => true | "" => true | _ => false end. - -Definition bit_maybe_i_matches_prefix (arg_ : string) -: option ((mword 1 * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1171_ := arg_ in - if ((andb (string_startswith _stringappend_1171_ "i") - (match (string_drop _stringappend_1171_ (build_ex (projT1 (string_length "i")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1171_ (build_ex (projT1 (string_length "i")))) with - | s_ => - Some - (((vec_of_bits [B1] : mword 1), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1171_ "") - (match (string_drop _stringappend_1171_ (build_ex (projT1 (string_length "")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1171_ (build_ex (projT1 (string_length "")))) with - | s_ => - Some - (((vec_of_bits [B0] : mword 1), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition bit_maybe_o_forwards (arg_ : mword 1) -: string := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then "o" - else "". - -Definition bit_maybe_o_backwards (arg_ : string) -: M (mword 1) := - (match arg_ with - | "o" => returnm ((vec_of_bits [B1] : mword 1) : mword 1) - | "" => returnm ((vec_of_bits [B0] : mword 1) : mword 1) - | _ => exit tt : M (mword 1) - end) - : M (mword 1). - -Definition bit_maybe_o_forwards_matches (arg_ : mword 1) -: bool := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true - else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true - else false. - -Definition bit_maybe_o_backwards_matches (arg_ : string) -: bool := - match arg_ with | "o" => true | "" => true | _ => false end. - -Definition bit_maybe_o_matches_prefix (arg_ : string) -: option ((mword 1 * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1169_ := arg_ in - if ((andb (string_startswith _stringappend_1169_ "o") - (match (string_drop _stringappend_1169_ (build_ex (projT1 (string_length "o")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1169_ (build_ex (projT1 (string_length "o")))) with - | s_ => - Some - (((vec_of_bits [B1] : mword 1), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1169_ "") - (match (string_drop _stringappend_1169_ (build_ex (projT1 (string_length "")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1169_ (build_ex (projT1 (string_length "")))) with - | s_ => - Some - (((vec_of_bits [B0] : mword 1), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition fence_bits_forwards (arg_ : mword 4) -: string := - match arg_ with - | v__0 => - let i : bits 1 := subrange_vec_dec v__0 3 3 in - let w : bits 1 := subrange_vec_dec v__0 0 0 in - let r : bits 1 := subrange_vec_dec v__0 1 1 in - let o : bits 1 := subrange_vec_dec v__0 2 2 in - let i : bits 1 := subrange_vec_dec v__0 3 3 in - string_append (bit_maybe_i_forwards i) - (string_append (bit_maybe_o_forwards o) - (string_append (bit_maybe_r_forwards r) (string_append (bit_maybe_w_forwards w) ""))) - end. - -Definition fence_bits_backwards (arg_ : string) -: M (mword 4) := - let _stringappend_1161_ := arg_ in - (match (bit_maybe_i_matches_prefix _stringappend_1161_) with - | Some (i,(existT _ _stringappend_1162_ _)) => returnm (i, build_ex _stringappend_1162_) - | _ => exit tt : M ((mword 1 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 1 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(i, existT _ _stringappend_1162_ _) => - let _stringappend_1163_ := string_drop _stringappend_1161_ (build_ex _stringappend_1162_) in - (match (bit_maybe_o_matches_prefix _stringappend_1163_) with - | Some (o,(existT _ _stringappend_1164_ _)) => returnm (o, build_ex _stringappend_1164_) - | _ => exit tt : M ((mword 1 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 1 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(o, existT _ _stringappend_1164_ _) => - let _stringappend_1165_ := string_drop _stringappend_1163_ (build_ex _stringappend_1164_) in - (match (bit_maybe_r_matches_prefix _stringappend_1165_) with - | Some (r,(existT _ _stringappend_1166_ _)) => returnm (r, build_ex _stringappend_1166_) - | _ => exit tt : M ((mword 1 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 1 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(r, existT _ _stringappend_1166_ _) => - let _stringappend_1167_ := string_drop _stringappend_1165_ (build_ex _stringappend_1166_) in - (match (bit_maybe_w_matches_prefix _stringappend_1167_) with - | Some (w,(existT _ _stringappend_1168_ _)) => returnm (w, build_ex _stringappend_1168_) - | _ => exit tt : M ((mword 1 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 1 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(w, existT _ _stringappend_1168_ _) => - (match (string_drop _stringappend_1167_ (build_ex _stringappend_1168_)) with - | "" => - returnm ((concat_vec (i : bits 1) - (concat_vec (o : bits 1) (concat_vec (r : bits 1) (w : bits 1)))) - : mword (1 + 3)) - | _ => exit tt : M (mword 4) - end) - : M (mword 4). - -Definition fence_bits_forwards_matches (arg_ : mword 4) -: bool := - match arg_ with | v__1 => true end. - -Definition fence_bits_backwards_matches (arg_ : string) -: M (bool) := - let _stringappend_1153_ := arg_ in - (if ((match (bit_maybe_i_matches_prefix _stringappend_1153_) with - | Some (i,(existT _ _stringappend_1154_ _)) => - let _stringappend_1155_ := - string_drop _stringappend_1153_ (build_ex _stringappend_1154_) in - if ((match (bit_maybe_o_matches_prefix _stringappend_1155_) with - | Some (o,(existT _ _stringappend_1156_ _)) => - let _stringappend_1157_ := - string_drop _stringappend_1155_ (build_ex _stringappend_1156_) in - if ((match (bit_maybe_r_matches_prefix _stringappend_1157_) with - | Some (r,(existT _ _stringappend_1158_ _)) => - let _stringappend_1159_ := - string_drop _stringappend_1157_ (build_ex _stringappend_1158_) in - if ((match (bit_maybe_w_matches_prefix _stringappend_1159_) with - | Some (w,(existT _ _stringappend_1160_ _)) => - match (string_drop _stringappend_1159_ - (build_ex _stringappend_1160_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false - | None => false - end)) then - (match (bit_maybe_i_matches_prefix _stringappend_1153_) with - | Some (i,(existT _ _stringappend_1154_ _)) => returnm (i, build_ex _stringappend_1154_) - | _ => exit tt : M ((mword 1 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 1 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(i, existT _ _stringappend_1154_ _) => - let _stringappend_1155_ := string_drop _stringappend_1153_ (build_ex _stringappend_1154_) in - (match (bit_maybe_o_matches_prefix _stringappend_1155_) with - | Some (o,(existT _ _stringappend_1156_ _)) => returnm (o, build_ex _stringappend_1156_) - | _ => exit tt : M ((mword 1 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 1 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(o, existT _ _stringappend_1156_ _) => - let _stringappend_1157_ := string_drop _stringappend_1155_ (build_ex _stringappend_1156_) in - (match (bit_maybe_r_matches_prefix _stringappend_1157_) with - | Some (r,(existT _ _stringappend_1158_ _)) => returnm (r, build_ex _stringappend_1158_) - | _ => exit tt : M ((mword 1 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 1 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(r, existT _ _stringappend_1158_ _) => - let _stringappend_1159_ := string_drop _stringappend_1157_ (build_ex _stringappend_1158_) in - (match (bit_maybe_w_matches_prefix _stringappend_1159_) with - | Some (w,(existT _ _stringappend_1160_ _)) => returnm (w, build_ex _stringappend_1160_) - | _ => exit tt : M ((mword 1 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 1 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(w, existT _ _stringappend_1160_ _) => - (match (string_drop _stringappend_1159_ (build_ex _stringappend_1160_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else returnm (false : bool)) - : M (bool). - -Definition fence_bits_matches_prefix (arg_ : string) -: M (option ((mword 4 * {n : Z & ArithFact (n >= 0)}))) := - let _stringappend_1145_ := arg_ in - (if ((match (bit_maybe_i_matches_prefix _stringappend_1145_) with - | Some (i,(existT _ _stringappend_1146_ _)) => - let _stringappend_1147_ := - string_drop _stringappend_1145_ (build_ex _stringappend_1146_) in - if ((match (bit_maybe_o_matches_prefix _stringappend_1147_) with - | Some (o,(existT _ _stringappend_1148_ _)) => - let _stringappend_1149_ := - string_drop _stringappend_1147_ (build_ex _stringappend_1148_) in - if ((match (bit_maybe_r_matches_prefix _stringappend_1149_) with - | Some (r,(existT _ _stringappend_1150_ _)) => - let _stringappend_1151_ := - string_drop _stringappend_1149_ (build_ex _stringappend_1150_) in - if ((match (bit_maybe_w_matches_prefix _stringappend_1151_) with - | Some (w,(existT _ _stringappend_1152_ _)) => - match (string_drop _stringappend_1151_ - (build_ex _stringappend_1152_)) with - | s_ => true - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false - | None => false - end)) then - (match (bit_maybe_i_matches_prefix _stringappend_1145_) with - | Some (i,(existT _ _stringappend_1146_ _)) => returnm (i, build_ex _stringappend_1146_) - | _ => exit tt : M ((mword 1 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 1 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(i, existT _ _stringappend_1146_ _) => - let _stringappend_1147_ := string_drop _stringappend_1145_ (build_ex _stringappend_1146_) in - (match (bit_maybe_o_matches_prefix _stringappend_1147_) with - | Some (o,(existT _ _stringappend_1148_ _)) => returnm (o, build_ex _stringappend_1148_) - | _ => exit tt : M ((mword 1 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 1 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(o, existT _ _stringappend_1148_ _) => - let _stringappend_1149_ := string_drop _stringappend_1147_ (build_ex _stringappend_1148_) in - (match (bit_maybe_r_matches_prefix _stringappend_1149_) with - | Some (r,(existT _ _stringappend_1150_ _)) => returnm (r, build_ex _stringappend_1150_) - | _ => exit tt : M ((mword 1 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 1 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(r, existT _ _stringappend_1150_ _) => - let _stringappend_1151_ := string_drop _stringappend_1149_ (build_ex _stringappend_1150_) in - (match (bit_maybe_w_matches_prefix _stringappend_1151_) with - | Some (w,(existT _ _stringappend_1152_ _)) => returnm (w, build_ex _stringappend_1152_) - | _ => exit tt : M ((mword 1 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 1 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(w, existT _ _stringappend_1152_ _) => - returnm ((match (string_drop _stringappend_1151_ (build_ex _stringappend_1152_)) with - | s_ => - Some - ((concat_vec (i : bits 1) - (concat_vec (o : bits 1) (concat_vec (r : bits 1) (w : bits 1))), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((mword 4 * {n : Z & ArithFact (n >= 0)}))) - else returnm (None : option ((mword 4 * {n : Z & ArithFact (n >= 0)})))) - : M (option ((mword 4 * {n : Z & ArithFact (n >= 0)}))). - -Definition aqrl_str (aq : bool) (rl : bool) -: string := - match (aq, rl) with - | (false, false) => "" - | (false, true) => ".rl" - | (true, false) => ".aq" - | (true, true) => ".aqrl" - end. - -Definition lrsc_width_str (width : word_width) -: string := - match width with | BYTE => ".b" | HALF => ".h" | WORD => ".w" | DOUBLE => ".d" end. - -Definition process_loadres {n : Z} (rd : mword 5) (addr : mword 64) (value : MemoryOpResult (mword (8 * n))) (is_unsigned : bool) `{ArithFact ((0 + 1) <= - n /\ - n <= 8)} -: M (bool) := - (match (extend_value is_unsigned value) with - | MemValue (result) => - let '_ := (load_reservation addr) : unit in - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {syn_n : Z & ArithFact (0 <= syn_n /\ (syn_n + 1) <= 32)})) result >> - returnm (true - : bool) - | MemException (e) => handle_mem_exception addr e >> returnm (false : bool) - end) - : M (bool). - -Definition encdec_amoop_forwards (arg_ : amoop) -: mword 5 := - match arg_ with - | AMOSWAP => (vec_of_bits [B0;B0;B0;B0;B1] : mword 5) - | AMOADD => (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) - | AMOXOR => (vec_of_bits [B0;B0;B1;B0;B0] : mword 5) - | AMOAND => (vec_of_bits [B0;B1;B1;B0;B0] : mword 5) - | AMOOR => (vec_of_bits [B0;B1;B0;B0;B0] : mword 5) - | AMOMIN => (vec_of_bits [B1;B0;B0;B0;B0] : mword 5) - | AMOMAX => (vec_of_bits [B1;B0;B1;B0;B0] : mword 5) - | AMOMINU => (vec_of_bits [B1;B1;B0;B0;B0] : mword 5) - | AMOMAXU => (vec_of_bits [B1;B1;B1;B0;B0] : mword 5) - end. - -Definition encdec_amoop_backwards (arg_ : mword 5) -: amoop := - let b__0 := arg_ in - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B0;B1] : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - AMOSWAP - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - AMOADD - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B1;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - AMOXOR - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B1;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - AMOAND - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - AMOOR - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - AMOMIN - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B1;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - AMOMAX - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - AMOMINU - else AMOMAXU. - -Definition encdec_amoop_forwards_matches (arg_ : amoop) -: bool := - match arg_ with - | AMOSWAP => true - | AMOADD => true - | AMOXOR => true - | AMOAND => true - | AMOOR => true - | AMOMIN => true - | AMOMAX => true - | AMOMINU => true - | AMOMAXU => true - end. - -Definition encdec_amoop_backwards_matches (arg_ : mword 5) -: bool := - let b__0 := arg_ in - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B0;B1] : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B1;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B1;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B1;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B0;B1;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno b__0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B1;B1;B1;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - true - else false. - -Definition amo_mnemonic_forwards (arg_ : amoop) -: string := - match arg_ with - | AMOSWAP => "amoswap" - | AMOADD => "amoadd" - | AMOXOR => "amoxor" - | AMOAND => "amoand" - | AMOOR => "amoor" - | AMOMIN => "amomin" - | AMOMAX => "amomax" - | AMOMINU => "amominu" - | AMOMAXU => "amomaxu" - end. - -Definition amo_mnemonic_backwards (arg_ : string) -: M (amoop) := - (match arg_ with - | "amoswap" => returnm (AMOSWAP : amoop) - | "amoadd" => returnm (AMOADD : amoop) - | "amoxor" => returnm (AMOXOR : amoop) - | "amoand" => returnm (AMOAND : amoop) - | "amoor" => returnm (AMOOR : amoop) - | "amomin" => returnm (AMOMIN : amoop) - | "amomax" => returnm (AMOMAX : amoop) - | "amominu" => returnm (AMOMINU : amoop) - | "amomaxu" => returnm (AMOMAXU : amoop) - | _ => exit tt : M (amoop) - end) - : M (amoop). - -Definition amo_mnemonic_forwards_matches (arg_ : amoop) -: bool := - match arg_ with - | AMOSWAP => true - | AMOADD => true - | AMOXOR => true - | AMOAND => true - | AMOOR => true - | AMOMIN => true - | AMOMAX => true - | AMOMINU => true - | AMOMAXU => true - end. - -Definition amo_mnemonic_backwards_matches (arg_ : string) -: bool := - match arg_ with - | "amoswap" => true - | "amoadd" => true - | "amoxor" => true - | "amoand" => true - | "amoor" => true - | "amomin" => true - | "amomax" => true - | "amominu" => true - | "amomaxu" => true - | _ => false - end. - -Definition amo_mnemonic_matches_prefix (arg_ : string) -: option ((amoop * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1136_ := arg_ in - if ((andb (string_startswith _stringappend_1136_ "amoswap") - (match (string_drop _stringappend_1136_ (build_ex (projT1 (string_length "amoswap")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1136_ (build_ex (projT1 (string_length "amoswap")))) with - | s_ => - Some - ((AMOSWAP, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1136_ "amoadd") - (match (string_drop _stringappend_1136_ (build_ex (projT1 (string_length "amoadd")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1136_ (build_ex (projT1 (string_length "amoadd")))) with - | s_ => - Some - ((AMOADD, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1136_ "amoxor") - (match (string_drop _stringappend_1136_ (build_ex (projT1 (string_length "amoxor")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1136_ (build_ex (projT1 (string_length "amoxor")))) with - | s_ => - Some - ((AMOXOR, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1136_ "amoand") - (match (string_drop _stringappend_1136_ (build_ex (projT1 (string_length "amoand")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1136_ (build_ex (projT1 (string_length "amoand")))) with - | s_ => - Some - ((AMOAND, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1136_ "amoor") - (match (string_drop _stringappend_1136_ (build_ex (projT1 (string_length "amoor")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1136_ (build_ex (projT1 (string_length "amoor")))) with - | s_ => - Some - ((AMOOR, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1136_ "amomin") - (match (string_drop _stringappend_1136_ (build_ex (projT1 (string_length "amomin")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1136_ (build_ex (projT1 (string_length "amomin")))) with - | s_ => - Some - ((AMOMIN, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1136_ "amomax") - (match (string_drop _stringappend_1136_ (build_ex (projT1 (string_length "amomax")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1136_ (build_ex (projT1 (string_length "amomax")))) with - | s_ => - Some - ((AMOMAX, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1136_ "amominu") - (match (string_drop _stringappend_1136_ (build_ex (projT1 (string_length "amominu")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1136_ (build_ex (projT1 (string_length "amominu")))) with - | s_ => - Some - ((AMOMINU, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1136_ "amomaxu") - (match (string_drop _stringappend_1136_ (build_ex (projT1 (string_length "amomaxu")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1136_ (build_ex (projT1 (string_length "amomaxu")))) with - | s_ => - Some - ((AMOMAXU, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition encdec_csrop_forwards (arg_ : csrop) -: mword 2 := - match arg_ with - | CSRRW => (vec_of_bits [B0;B1] : mword 2) - | CSRRS => (vec_of_bits [B1;B0] : mword 2) - | CSRRC => (vec_of_bits [B1;B1] : mword 2) - end. - -Definition encdec_csrop_backwards (arg_ : mword 2) -: csrop := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then CSRRW - else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then CSRRS - else CSRRC. - -Definition encdec_csrop_forwards_matches (arg_ : csrop) -: bool := - match arg_ with | CSRRW => true | CSRRS => true | CSRRC => true end. - -Definition encdec_csrop_backwards_matches (arg_ : mword 2) -: bool := - let b__0 := arg_ in - if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then true - else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then true - else false. - -Definition readCSR (csr : mword 12) -: M (mword 64) := - let b__0 := csr in - (if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then - (read_reg mvendorid_ref : M (mword 64)) - : M (xlenbits) - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then - (read_reg marchid_ref : M (mword 64)) - : M (xlenbits) - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then - (read_reg mimpid_ref : M (mword 64)) - : M (xlenbits) - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then - (read_reg mhartid_ref : M (mword 64)) - : M (xlenbits) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - read_reg mstatus_ref >>= fun w__4 : Mstatus => returnm ((_get_Mstatus_bits w__4) : mword 64) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then - read_reg misa_ref >>= fun w__5 : Misa => returnm ((_get_Misa_bits w__5) : mword 64) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - read_reg medeleg_ref >>= fun w__6 : Medeleg => returnm ((_get_Medeleg_bits w__6) : mword 64) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then - read_reg mideleg_ref >>= fun w__7 : Minterrupts => - returnm ((_get_Minterrupts_bits w__7) - : mword 64) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then - read_reg mie_ref >>= fun w__8 : Minterrupts => - returnm ((_get_Minterrupts_bits w__8) - : mword 64) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then - read_reg mtvec_ref >>= fun w__9 : Mtvec => returnm ((_get_Mtvec_bits w__9) : mword 64) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then - read_reg mcounteren_ref >>= fun w__10 : Counteren => - returnm ((EXTZ 64 (_get_Counteren_bits w__10)) - : mword 64) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then - (read_reg mscratch_ref : M (mword 64)) - : M (xlenbits) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then - (read_reg mepc_ref : M (mword 64)) >>= fun w__12 : xlenbits => - pc_alignment_mask tt >>= fun w__13 : mword 64 => returnm ((and_vec w__12 w__13) : mword 64) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then - read_reg mcause_ref >>= fun w__14 : Mcause => returnm ((_get_Mcause_bits w__14) : mword 64) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then - (read_reg mtval_ref : M (mword 64)) - : M (xlenbits) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then - read_reg mip_ref >>= fun w__16 : Minterrupts => - returnm ((_get_Minterrupts_bits w__16) - : mword 64) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then - (read_reg pmpcfg0_ref : M (mword 64)) - : M (xlenbits) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then - (read_reg pmpaddr0_ref : M (mword 64)) - : M (xlenbits) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - read_reg mstatus_ref >>= fun w__19 : Mstatus => - returnm ((_get_Sstatus_bits (lower_mstatus w__19)) - : mword 64) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - read_reg sedeleg_ref >>= fun w__20 : Sedeleg => - returnm ((_get_Sedeleg_bits w__20) - : mword 64) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then - read_reg sideleg_ref >>= fun w__21 : Sinterrupts => - returnm ((_get_Sinterrupts_bits w__21) - : mword 64) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then - read_reg mie_ref >>= fun w__22 : Minterrupts => - read_reg mideleg_ref >>= fun w__23 : Minterrupts => - returnm ((_get_Sinterrupts_bits (lower_mie w__22 w__23)) - : mword 64) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then - read_reg stvec_ref >>= fun w__24 : Mtvec => returnm ((_get_Mtvec_bits w__24) : mword 64) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then - read_reg scounteren_ref >>= fun w__25 : Counteren => - returnm ((EXTZ 64 (_get_Counteren_bits w__25)) - : mword 64) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then - (read_reg sscratch_ref : M (mword 64)) - : M (xlenbits) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then - (read_reg sepc_ref : M (mword 64)) >>= fun w__27 : xlenbits => - pc_alignment_mask tt >>= fun w__28 : mword 64 => returnm ((and_vec w__27 w__28) : mword 64) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then - read_reg scause_ref >>= fun w__29 : Mcause => returnm ((_get_Mcause_bits w__29) : mword 64) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then - (read_reg stval_ref : M (mword 64)) - : M (xlenbits) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then - read_reg mip_ref >>= fun w__31 : Minterrupts => - read_reg mideleg_ref >>= fun w__32 : Minterrupts => - returnm ((_get_Sinterrupts_bits (lower_mip w__31 w__32)) - : mword 64) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - (read_reg satp_ref : M (mword 64)) - : M (xlenbits) - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - (read_reg mcycle_ref : M (mword 64)) - : M (xlenbits) - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then - (read_reg mtime_ref : M (mword 64)) - : M (xlenbits) - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - (read_reg minstret_ref : M (mword 64)) - : M (xlenbits) - else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then - (read_reg tselect_ref : M (mword 64)) >>= fun w__37 : xlenbits => - returnm ((not_vec w__37) - : mword 64) - else - let '_ := (print_bits "unhandled read to CSR " csr) : unit in - returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) - : mword 64)) >>= fun res : xlenbits => - let '_ := - (print_endline - (String.append "CSR " - (String.append ((csr_name csr) : string) (String.append " -> " (string_of_bits res))))) - : unit in - returnm (res - : mword 64). - -Definition writeCSR (csr : mword 12) (value : mword 64) -: M (unit) := - let b__0 := csr in - (if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - read_reg mstatus_ref >>= fun w__0 : Mstatus => - write_reg mstatus_ref (legalize_mstatus w__0 value) >> - read_reg mstatus_ref >>= fun w__1 : Mstatus => - returnm ((Some - (_get_Mstatus_bits w__1)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then - read_reg misa_ref >>= fun w__2 : Misa => - legalize_misa w__2 value >>= fun w__3 : Misa => - write_reg misa_ref w__3 >> - read_reg misa_ref >>= fun w__4 : Misa => - returnm ((Some - (_get_Misa_bits w__4)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - read_reg medeleg_ref >>= fun w__5 : Medeleg => - write_reg medeleg_ref (legalize_medeleg w__5 value) >> - read_reg medeleg_ref >>= fun w__6 : Medeleg => - returnm ((Some - (_get_Medeleg_bits w__6)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then - read_reg mideleg_ref >>= fun w__7 : Minterrupts => - write_reg mideleg_ref (legalize_mideleg w__7 value) >> - read_reg mideleg_ref >>= fun w__8 : Minterrupts => - returnm ((Some - (_get_Minterrupts_bits w__8)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then - read_reg mie_ref >>= fun w__9 : Minterrupts => - write_reg mie_ref (legalize_mie w__9 value) >> - read_reg mie_ref >>= fun w__10 : Minterrupts => - returnm ((Some - (_get_Minterrupts_bits w__10)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then - read_reg mtvec_ref >>= fun w__11 : Mtvec => - write_reg mtvec_ref (legalize_tvec w__11 value) >> - read_reg mtvec_ref >>= fun w__12 : Mtvec => - returnm ((Some - (_get_Mtvec_bits w__12)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then - read_reg mcounteren_ref >>= fun w__13 : Counteren => - legalize_mcounteren w__13 value >>= fun w__14 : Counteren => - write_reg mcounteren_ref w__14 >> - read_reg mcounteren_ref >>= fun w__15 : Counteren => - returnm ((Some - (EXTZ 64 (_get_Counteren_bits w__15))) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then - write_reg mscratch_ref value >> - (read_reg mscratch_ref : M (mword 64)) >>= fun w__16 : xlenbits => - returnm ((Some - (w__16)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then - legalize_xepc value >>= fun w__17 : mword 64 => - write_reg mepc_ref w__17 >> - (read_reg mepc_ref : M (mword 64)) >>= fun w__18 : xlenbits => - returnm ((Some - (w__18)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then - _set_Mcause_bits mcause_ref value >> - read_reg mcause_ref >>= fun w__19 : Mcause => - returnm ((Some - (_get_Mcause_bits w__19)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then - write_reg mtval_ref value >> - (read_reg mtval_ref : M (mword 64)) >>= fun w__20 : xlenbits => - returnm ((Some - (w__20)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then - read_reg mip_ref >>= fun w__21 : Minterrupts => - write_reg mip_ref (legalize_mip w__21 value) >> - read_reg mip_ref >>= fun w__22 : Minterrupts => - returnm ((Some - (_get_Minterrupts_bits w__22)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then - write_reg pmpcfg0_ref value >> - (read_reg pmpcfg0_ref : M (mword 64)) >>= fun w__23 : xlenbits => - returnm ((Some - (w__23)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then - write_reg pmpaddr0_ref value >> - (read_reg pmpaddr0_ref : M (mword 64)) >>= fun w__24 : xlenbits => - returnm ((Some - (w__24)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - read_reg mstatus_ref >>= fun w__25 : Mstatus => - write_reg mstatus_ref (legalize_sstatus w__25 value) >> - read_reg mstatus_ref >>= fun w__26 : Mstatus => - returnm ((Some - (_get_Mstatus_bits w__26)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - read_reg sedeleg_ref >>= fun w__27 : Sedeleg => - write_reg sedeleg_ref (legalize_sedeleg w__27 value) >> - read_reg sedeleg_ref >>= fun w__28 : Sedeleg => - returnm ((Some - (_get_Sedeleg_bits w__28)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then - _set_Sinterrupts_bits sideleg_ref value >> - read_reg sideleg_ref >>= fun w__29 : Sinterrupts => - returnm ((Some - (_get_Sinterrupts_bits w__29)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then - read_reg mie_ref >>= fun w__30 : Minterrupts => - read_reg mideleg_ref >>= fun w__31 : Minterrupts => - write_reg mie_ref (legalize_sie w__30 w__31 value) >> - read_reg mie_ref >>= fun w__32 : Minterrupts => - returnm ((Some - (_get_Minterrupts_bits w__32)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then - read_reg stvec_ref >>= fun w__33 : Mtvec => - write_reg stvec_ref (legalize_tvec w__33 value) >> - read_reg stvec_ref >>= fun w__34 : Mtvec => - returnm ((Some - (_get_Mtvec_bits w__34)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then - read_reg scounteren_ref >>= fun w__35 : Counteren => - legalize_scounteren w__35 value >>= fun w__36 : Counteren => - write_reg scounteren_ref w__36 >> - read_reg scounteren_ref >>= fun w__37 : Counteren => - returnm ((Some - (EXTZ 64 (_get_Counteren_bits w__37))) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then - write_reg sscratch_ref value >> - (read_reg sscratch_ref : M (mword 64)) >>= fun w__38 : xlenbits => - returnm ((Some - (w__38)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then - legalize_xepc value >>= fun w__39 : mword 64 => - write_reg sepc_ref w__39 >> - (read_reg sepc_ref : M (mword 64)) >>= fun w__40 : xlenbits => - returnm ((Some - (w__40)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then - _set_Mcause_bits scause_ref value >> - read_reg scause_ref >>= fun w__41 : Mcause => - returnm ((Some - (_get_Mcause_bits w__41)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then - write_reg stval_ref value >> - (read_reg stval_ref : M (mword 64)) >>= fun w__42 : xlenbits => - returnm ((Some - (w__42)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then - read_reg mip_ref >>= fun w__43 : Minterrupts => - read_reg mideleg_ref >>= fun w__44 : Minterrupts => - write_reg mip_ref (legalize_sip w__43 w__44 value) >> - read_reg mip_ref >>= fun w__45 : Minterrupts => - returnm ((Some - (_get_Minterrupts_bits w__45)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - cur_Architecture tt >>= fun w__46 : Architecture => - (read_reg satp_ref : M (mword 64)) >>= fun w__47 : xlenbits => - write_reg satp_ref (legalize_satp w__46 w__47 value) >> - (read_reg satp_ref : M (mword 64)) >>= fun w__48 : xlenbits => - returnm ((Some - (w__48)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then - write_reg tselect_ref value >> - (read_reg tselect_ref : M (mword 64)) >>= fun w__49 : xlenbits => - returnm ((Some - (w__49)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then - write_reg mcycle_ref value >> - (read_reg mcycle_ref : M (mword 64)) >>= fun w__50 : xlenbits => - returnm ((Some - (w__50)) - : option (mword 64)) - else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then - write_reg minstret_ref value >> - write_reg minstret_written_ref true >> - (read_reg minstret_ref : M (mword 64)) >>= fun w__51 : xlenbits => - returnm ((Some - (w__51)) - : option (mword 64)) - else returnm (None : option (mword 64))) >>= fun res : option xlenbits => - returnm ((match res with - | Some (v) => - print_endline - (String.append "CSR " - (String.append ((csr_name csr) : string) - (String.append " <- " - (String.append (string_of_bits v) - (String.append " (input: " (String.append (string_of_bits value) ")")))))) - | None => print_bits "unhandled write to CSR " csr - end) - : unit). - -Definition maybe_i_forwards (arg_ : bool) -: string := - match arg_ with | true => "i" | false => "" end. - -Definition maybe_i_backwards (arg_ : string) -: M (bool) := - (match arg_ with - | "i" => returnm (true : bool) - | "" => returnm (false : bool) - | _ => exit tt : M (bool) - end) - : M (bool). - -Definition maybe_i_forwards_matches (arg_ : bool) -: bool := - match arg_ with | true => true | false => true end. - -Definition maybe_i_backwards_matches (arg_ : string) -: bool := - match arg_ with | "i" => true | "" => true | _ => false end. - -Definition maybe_i_matches_prefix (arg_ : string) -: option ((bool * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1134_ := arg_ in - if ((andb (string_startswith _stringappend_1134_ "i") - (match (string_drop _stringappend_1134_ (build_ex (projT1 (string_length "i")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1134_ (build_ex (projT1 (string_length "i")))) with - | s_ => - Some - ((true, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1134_ "") - (match (string_drop _stringappend_1134_ (build_ex (projT1 (string_length "")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1134_ (build_ex (projT1 (string_length "")))) with - | s_ => - Some - ((false, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition csr_mnemonic_forwards (arg_ : csrop) -: string := - match arg_ with | CSRRW => "csrrw" | CSRRS => "csrrs" | CSRRC => "csrrc" end. - -Definition csr_mnemonic_backwards (arg_ : string) -: M (csrop) := - (match arg_ with - | "csrrw" => returnm (CSRRW : csrop) - | "csrrs" => returnm (CSRRS : csrop) - | "csrrc" => returnm (CSRRC : csrop) - | _ => exit tt : M (csrop) - end) - : M (csrop). - -Definition csr_mnemonic_forwards_matches (arg_ : csrop) -: bool := - match arg_ with | CSRRW => true | CSRRS => true | CSRRC => true end. - -Definition csr_mnemonic_backwards_matches (arg_ : string) -: bool := - match arg_ with | "csrrw" => true | "csrrs" => true | "csrrc" => true | _ => false end. - -Definition csr_mnemonic_matches_prefix (arg_ : string) -: option ((csrop * {n : Z & ArithFact (n >= 0)})) := - let _stringappend_1131_ := arg_ in - if ((andb (string_startswith _stringappend_1131_ "csrrw") - (match (string_drop _stringappend_1131_ (build_ex (projT1 (string_length "csrrw")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1131_ (build_ex (projT1 (string_length "csrrw")))) with - | s_ => - Some - ((CSRRW, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1131_ "csrrs") - (match (string_drop _stringappend_1131_ (build_ex (projT1 (string_length "csrrs")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1131_ (build_ex (projT1 (string_length "csrrs")))) with - | s_ => - Some - ((CSRRS, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else if ((andb (string_startswith _stringappend_1131_ "csrrc") - (match (string_drop _stringappend_1131_ (build_ex (projT1 (string_length "csrrc")))) with - | s_ => true - end))) then - match (string_drop _stringappend_1131_ (build_ex (projT1 (string_length "csrrc")))) with - | s_ => - Some - ((CSRRC, build_ex (projT1 (sub_nat (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end - else None. - -Definition decodeCompressed (v__2 : mword 16) -: option ast := - if sumbool_of_bool ((andb - (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B0;B0;B0] : mword 3)) - (andb - (Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno - (subrange_vec_dec v__2 11 7)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)}))) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B1] : mword 2))))) - then - let nzi1 : bits 1 := subrange_vec_dec v__2 12 12 in - let nzi0 : bits 5 := subrange_vec_dec v__2 6 2 in - if sumbool_of_bool ((andb (eq_vec nzi1 (vec_of_bits [B0] : mword 1)) - (Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno nzi0))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)}))))) then - Some - (NOP - (tt)) - else None - else if ((andb (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B0;B0;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B0] : mword 2)))) then - let rd : cregbits := subrange_vec_dec v__2 4 2 in - let nz96 : bits 4 := subrange_vec_dec v__2 10 7 in - let nz54 : bits 2 := subrange_vec_dec v__2 12 11 in - let nz3 : bits 1 := subrange_vec_dec v__2 5 5 in - let nz2 : bits 1 := subrange_vec_dec v__2 6 6 in - let nzimm := (concat_vec nz96 (concat_vec nz54 (concat_vec nz3 nz2))) : bits 8 in - if ((eq_vec nzimm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8))) then None - else Some (C_ADDI4SPN (rd, nzimm)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B0;B1;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B0] : mword 2)))) then - let ui6 : bits 1 := subrange_vec_dec v__2 5 5 in - let ui53 : bits 3 := subrange_vec_dec v__2 12 10 in - let ui2 : bits 1 := subrange_vec_dec v__2 6 6 in - let rs1 : cregbits := subrange_vec_dec v__2 9 7 in - let rd : cregbits := subrange_vec_dec v__2 4 2 in - let uimm := (concat_vec ui6 (concat_vec ui53 ui2)) : bits 5 in - Some - (C_LW - (uimm, rs1, rd)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B0;B1;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B0] : mword 2)))) then - let ui76 : bits 2 := subrange_vec_dec v__2 6 5 in - let ui53 : bits 3 := subrange_vec_dec v__2 12 10 in - let rs1 : cregbits := subrange_vec_dec v__2 9 7 in - let rd : cregbits := subrange_vec_dec v__2 4 2 in - let uimm := (concat_vec ui76 ui53) : bits 5 in - Some - (C_LD - (uimm, rs1, rd)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B1;B1;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B0] : mword 2)))) then - let ui6 : bits 1 := subrange_vec_dec v__2 5 5 in - let ui53 : bits 3 := subrange_vec_dec v__2 12 10 in - let ui2 : bits 1 := subrange_vec_dec v__2 6 6 in - let rs2 : cregbits := subrange_vec_dec v__2 4 2 in - let rs1 : cregbits := subrange_vec_dec v__2 9 7 in - let uimm := (concat_vec ui6 (concat_vec ui53 ui2)) : bits 5 in - Some - (C_SW - (uimm, rs1, rs2)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B1;B1;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B0] : mword 2)))) then - let ui76 : bits 2 := subrange_vec_dec v__2 6 5 in - let ui53 : bits 3 := subrange_vec_dec v__2 12 10 in - let rs2 : bits 3 := subrange_vec_dec v__2 4 2 in - let rs1 : bits 3 := subrange_vec_dec v__2 9 7 in - let uimm := (concat_vec ui76 ui53) : bits 5 in - Some - (C_SD - (uimm, rs1, rs2)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B0;B0;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B1] : mword 2)))) then - let rsd : regbits := subrange_vec_dec v__2 11 7 in - let nzi5 : bits 1 := subrange_vec_dec v__2 12 12 in - let nzi40 : bits 5 := subrange_vec_dec v__2 6 2 in - let nzi := (concat_vec nzi5 nzi40) : bits 6 in - if sumbool_of_bool ((orb (eq_vec nzi (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rsd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno zreg))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)}))))) then - None - else Some (C_ADDI (nzi, rsd)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B0;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B1] : mword 2)))) then - let rsd : regbits := subrange_vec_dec v__2 11 7 in - let imm5 : bits 1 := subrange_vec_dec v__2 12 12 in - let imm40 : bits 5 := subrange_vec_dec v__2 6 2 in - Some - (C_ADDIW - (concat_vec imm5 imm40, rsd)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B0;B1;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B1] : mword 2)))) then - let rd : regbits := subrange_vec_dec v__2 11 7 in - let imm5 : bits 1 := subrange_vec_dec v__2 12 12 in - let imm40 : bits 5 := subrange_vec_dec v__2 6 2 in - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno zreg))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - None - else Some (C_LI (concat_vec imm5 imm40, rd)) - else if sumbool_of_bool ((andb - (eq_vec (subrange_vec_dec v__2 15 13) - (vec_of_bits [B0;B1;B1] : mword 3)) - (andb - (Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno - (subrange_vec_dec v__2 11 7)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)}))) - (eq_vec (subrange_vec_dec v__2 1 0) - (vec_of_bits [B0;B1] : mword 2))))) then - let nzi9 : bits 1 := subrange_vec_dec v__2 12 12 in - let nzi87 : bits 2 := subrange_vec_dec v__2 4 3 in - let nzi6 : bits 1 := subrange_vec_dec v__2 5 5 in - let nzi5 : bits 1 := subrange_vec_dec v__2 2 2 in - let nzi4 : bits 1 := subrange_vec_dec v__2 6 6 in - let nzimm := concat_vec nzi9 (concat_vec nzi87 (concat_vec nzi6 (concat_vec nzi5 nzi4))) in - if ((eq_vec nzimm (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then None - else Some (C_ADDI16SP (nzimm)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B0;B1;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B1] : mword 2)))) then - let rd : regbits := subrange_vec_dec v__2 11 7 in - let imm17 : bits 1 := subrange_vec_dec v__2 12 12 in - let imm1612 : bits 5 := subrange_vec_dec v__2 6 2 in - if sumbool_of_bool ((orb - (Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno zreg))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)}))) - (Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno sp))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)}))))) then - None - else Some (C_LUI (concat_vec imm17 imm1612, rd)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B1;B0;B0] : mword 3)) - (andb (eq_vec (subrange_vec_dec v__2 11 10) (vec_of_bits [B0;B0] : mword 2)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B1] : mword 2))))) then - let rsd : cregbits := subrange_vec_dec v__2 9 7 in - let nzui5 : bits 1 := subrange_vec_dec v__2 12 12 in - let nzui40 : bits 5 := subrange_vec_dec v__2 6 2 in - let shamt : bits 6 := concat_vec nzui5 nzui40 in - if ((eq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then None - else Some (C_SRLI (shamt, rsd)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B1;B0;B0] : mword 3)) - (andb (eq_vec (subrange_vec_dec v__2 11 10) (vec_of_bits [B0;B1] : mword 2)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B1] : mword 2))))) then - let rsd : cregbits := subrange_vec_dec v__2 9 7 in - let nzui5 : bits 1 := subrange_vec_dec v__2 12 12 in - let nzui40 : bits 5 := subrange_vec_dec v__2 6 2 in - let shamt : bits 6 := concat_vec nzui5 nzui40 in - if ((eq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then None - else Some (C_SRAI (shamt, rsd)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B1;B0;B0] : mword 3)) - (andb (eq_vec (subrange_vec_dec v__2 11 10) (vec_of_bits [B1;B0] : mword 2)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B1] : mword 2))))) then - let rsd : cregbits := subrange_vec_dec v__2 9 7 in - let i5 : bits 1 := subrange_vec_dec v__2 12 12 in - let i40 : bits 5 := subrange_vec_dec v__2 6 2 in - Some - (C_ANDI - (concat_vec i5 i40, rsd)) - else if ((andb - (eq_vec (subrange_vec_dec v__2 15 10) (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword 6)) - (andb (eq_vec (subrange_vec_dec v__2 6 5) (vec_of_bits [B0;B0] : mword 2)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B1] : mword 2))))) then - let rsd : cregbits := subrange_vec_dec v__2 9 7 in - let rs2 : cregbits := subrange_vec_dec v__2 4 2 in - Some - (C_SUB - (rsd, rs2)) - else if ((andb - (eq_vec (subrange_vec_dec v__2 15 10) (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword 6)) - (andb (eq_vec (subrange_vec_dec v__2 6 5) (vec_of_bits [B0;B1] : mword 2)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B1] : mword 2))))) then - let rsd : cregbits := subrange_vec_dec v__2 9 7 in - let rs2 : cregbits := subrange_vec_dec v__2 4 2 in - Some - (C_XOR - (rsd, rs2)) - else if ((andb - (eq_vec (subrange_vec_dec v__2 15 10) (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword 6)) - (andb (eq_vec (subrange_vec_dec v__2 6 5) (vec_of_bits [B1;B0] : mword 2)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B1] : mword 2))))) then - let rsd : cregbits := subrange_vec_dec v__2 9 7 in - let rs2 : cregbits := subrange_vec_dec v__2 4 2 in - Some - (C_OR - (rsd, rs2)) - else if ((andb - (eq_vec (subrange_vec_dec v__2 15 10) (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword 6)) - (andb (eq_vec (subrange_vec_dec v__2 6 5) (vec_of_bits [B1;B1] : mword 2)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B1] : mword 2))))) then - let rsd : cregbits := subrange_vec_dec v__2 9 7 in - let rs2 : cregbits := subrange_vec_dec v__2 4 2 in - Some - (C_AND - (rsd, rs2)) - else if ((andb - (eq_vec (subrange_vec_dec v__2 15 10) (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword 6)) - (andb (eq_vec (subrange_vec_dec v__2 6 5) (vec_of_bits [B0;B0] : mword 2)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B1] : mword 2))))) then - let rsd : cregbits := subrange_vec_dec v__2 9 7 in - let rs2 : cregbits := subrange_vec_dec v__2 4 2 in - Some - (C_SUBW - (rsd, rs2)) - else if ((andb - (eq_vec (subrange_vec_dec v__2 15 10) (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword 6)) - (andb (eq_vec (subrange_vec_dec v__2 6 5) (vec_of_bits [B0;B1] : mword 2)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B1] : mword 2))))) then - let rsd : cregbits := subrange_vec_dec v__2 9 7 in - let rs2 : cregbits := subrange_vec_dec v__2 4 2 in - Some - (C_ADDW - (rsd, rs2)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B1] : mword 2)))) then - let i98 : bits 2 := subrange_vec_dec v__2 10 9 in - let i7 : bits 1 := subrange_vec_dec v__2 6 6 in - let i6 : bits 1 := subrange_vec_dec v__2 7 7 in - let i5 : bits 1 := subrange_vec_dec v__2 2 2 in - let i4 : bits 1 := subrange_vec_dec v__2 11 11 in - let i31 : bits 3 := subrange_vec_dec v__2 5 3 in - let i11 : bits 1 := subrange_vec_dec v__2 12 12 in - let i10 : bits 1 := subrange_vec_dec v__2 8 8 in - Some - (C_J - (concat_vec i11 - (concat_vec i10 - (concat_vec i98 (concat_vec i7 (concat_vec i6 (concat_vec i5 (concat_vec i4 i31)))))))) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B1;B1;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B1] : mword 2)))) then - let rs : cregbits := subrange_vec_dec v__2 9 7 in - let i8 : bits 1 := subrange_vec_dec v__2 12 12 in - let i76 : bits 2 := subrange_vec_dec v__2 6 5 in - let i5 : bits 1 := subrange_vec_dec v__2 2 2 in - let i43 : bits 2 := subrange_vec_dec v__2 11 10 in - let i21 : bits 2 := subrange_vec_dec v__2 4 3 in - Some - (C_BEQZ - (concat_vec i8 (concat_vec i76 (concat_vec i5 (concat_vec i43 i21))), rs)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B1;B1;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B0;B1] : mword 2)))) then - let rs : cregbits := subrange_vec_dec v__2 9 7 in - let i8 : bits 1 := subrange_vec_dec v__2 12 12 in - let i76 : bits 2 := subrange_vec_dec v__2 6 5 in - let i5 : bits 1 := subrange_vec_dec v__2 2 2 in - let i43 : bits 2 := subrange_vec_dec v__2 11 10 in - let i21 : bits 2 := subrange_vec_dec v__2 4 3 in - Some - (C_BNEZ - (concat_vec i8 (concat_vec i76 (concat_vec i5 (concat_vec i43 i21))), rs)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B0;B0;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B1;B0] : mword 2)))) then - let rsd : regbits := subrange_vec_dec v__2 11 7 in - let nzui5 : bits 1 := subrange_vec_dec v__2 12 12 in - let nzui40 : bits 5 := subrange_vec_dec v__2 6 2 in - let shamt : bits 6 := concat_vec nzui5 nzui40 in - if sumbool_of_bool ((orb (eq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rsd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno zreg))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)}))))) then - None - else Some (C_SLLI (shamt, rsd)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B0;B1;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B1;B0] : mword 2)))) then - let ui76 : bits 2 := subrange_vec_dec v__2 3 2 in - let ui5 : bits 1 := subrange_vec_dec v__2 12 12 in - let ui42 : bits 3 := subrange_vec_dec v__2 6 4 in - let rd : regbits := subrange_vec_dec v__2 11 7 in - let uimm : bits 6 := concat_vec ui76 (concat_vec ui5 ui42) in - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno zreg))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - None - else Some (C_LWSP (uimm, rd)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B0;B1;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B1;B0] : mword 2)))) then - let ui86 : bits 3 := subrange_vec_dec v__2 4 2 in - let ui5 : bits 1 := subrange_vec_dec v__2 12 12 in - let ui43 : bits 2 := subrange_vec_dec v__2 6 5 in - let rd : regbits := subrange_vec_dec v__2 11 7 in - let uimm : bits 6 := concat_vec ui86 (concat_vec ui5 ui43) in - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno zreg))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - None - else Some (C_LDSP (uimm, rd)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B1;B1;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B1;B0] : mword 2)))) then - let ui76 : bits 2 := subrange_vec_dec v__2 8 7 in - let ui52 : bits 4 := subrange_vec_dec v__2 12 9 in - let rs2 : regbits := subrange_vec_dec v__2 6 2 in - let uimm : bits 6 := concat_vec ui76 ui52 in - Some - (C_SWSP - (uimm, rs2)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 13) (vec_of_bits [B1;B1;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B1;B0] : mword 2)))) then - let ui86 : bits 3 := subrange_vec_dec v__2 9 7 in - let ui53 : bits 3 := subrange_vec_dec v__2 12 10 in - let rs2 : regbits := subrange_vec_dec v__2 6 2 in - let uimm : bits 6 := concat_vec ui86 ui53 in - Some - (C_SDSP - (uimm, rs2)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 12) (vec_of_bits [B1;B0;B0;B0] : mword 4)) - (eq_vec (subrange_vec_dec v__2 6 0) (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : mword 7)))) - then - let rs1 : regbits := subrange_vec_dec v__2 11 7 in - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno zreg))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - None - else Some (C_JR (rs1)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 12) (vec_of_bits [B1;B0;B0;B1] : mword 4)) - (eq_vec (subrange_vec_dec v__2 6 0) (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : mword 7)))) - then - let rs1 : regbits := subrange_vec_dec v__2 11 7 in - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno zreg))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) then - None - else Some (C_JALR (rs1)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 12) (vec_of_bits [B1;B0;B0;B0] : mword 4)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B1;B0] : mword 2)))) then - let rs2 : regbits := subrange_vec_dec v__2 6 2 in - let rd : regbits := subrange_vec_dec v__2 11 7 in - if sumbool_of_bool ((orb - (Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno zreg))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)}))) - (Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno zreg))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)}))))) then - None - else Some (C_MV (rd, rs2)) - else if ((andb (eq_vec (subrange_vec_dec v__2 15 12) (vec_of_bits [B1;B0;B0;B1] : mword 4)) - (eq_vec (subrange_vec_dec v__2 1 0) (vec_of_bits [B1;B0] : mword 2)))) then - let rsd : regbits := subrange_vec_dec v__2 11 7 in - let rs2 : regbits := subrange_vec_dec v__2 6 2 in - if sumbool_of_bool ((orb - (Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rsd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno zreg))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)}))) - (Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno zreg))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)}))))) then - None - else Some (C_ADD (rsd, rs2)) - else if ((eq_vec v__2 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16))) - then - Some - (C_ILLEGAL - (tt)) - else None. - -Definition execute_WFI '(tt : unit) -: M (bool) := - read_reg cur_privilege_ref >>= fun w__0 : Privilege => - (match w__0 with - | Machine => returnm (true : bool) - | Supervisor => - read_reg mstatus_ref >>= fun w__1 : Mstatus => - (if ((eq_vec (_get_Mstatus_TW w__1) ((bool_to_bits true) : mword 1))) then - handle_illegal tt >> returnm (false : bool) - else returnm (true : bool)) - : M (bool) - | User => handle_illegal tt >> returnm (false : bool) - end) - : M (bool). - -Definition execute_UTYPE (imm : mword 20) (rd : mword 5) (op : uop) -: M (bool) := - let off : xlenbits := - EXTS 64 (concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12)) in - match op with - | RISCV_LUI => returnm (off : xlenbits) - | RISCV_AUIPC => - (read_reg PC_ref : M (mword 64)) >>= fun w__0 : xlenbits => - returnm ((add_vec w__0 off) - : mword 64) - end >>= fun ret : xlenbits => - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) ret >> - returnm (true - : bool). - -Definition execute_THREAD_START '(tt : unit) : bool := true. - -Definition execute_STORECON (aq : bool) (rl : bool) (rs2 : mword 5) (rs1 : mword 5) (width : word_width) (rd : mword 5) -: M (bool) := - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun vaddr : xlenbits => - match width with - | BYTE => returnm (true : bool) - | HALF => - cast_unit_vec (access_vec_dec vaddr 0) >>= fun w__0 : mword 1 => - returnm ((eq_vec (w__0 : mword 1) (vec_of_bits [B0] : mword 1)) - : bool) - | WORD => - returnm ((eq_vec (subrange_vec_dec vaddr 1 0) (vec_of_bits [B0;B0] : mword 2)) : bool) - | DOUBLE => - returnm ((eq_vec (subrange_vec_dec vaddr 2 0) (vec_of_bits [B0;B0;B0] : mword 3)) : bool) - end >>= fun aligned : bool => - (if ((negb aligned)) then handle_mem_exception vaddr E_SAMO_Addr_Align >> returnm (false : bool) - else - match_reservation vaddr >>= fun w__1 : bool => - (if ((Bool.eqb w__1 false)) then - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (EXTZ 64 (vec_of_bits [B1] : mword 1)) >> - returnm (true - : bool) - else - translateAddr vaddr Write Data >>= fun w__2 : TR_Result => - (match w__2 with - | TR_Failure (e) => handle_mem_exception vaddr e >> returnm (false : bool) - | TR_Address (addr) => - match width with - | WORD => (mem_write_ea addr 4 aq rl true) : M (MemoryOpResult unit) - | DOUBLE => (mem_write_ea addr 8 aq rl true) : M (MemoryOpResult unit) - | _ => (internal_error "STORECON expected word or double") : M (MemoryOpResult unit) - end >>= fun eares : MemoryOpResult unit => - (match eares with - | MemException (e) => handle_mem_exception addr e >> returnm (false : bool) - | MemValue (_) => - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun rs2_val => - match width with - | WORD => - (mem_write_value addr 4 (subrange_vec_dec rs2_val 31 0) aq rl true) - : M (MemoryOpResult bool) - | DOUBLE => (mem_write_value addr 8 rs2_val aq rl true) : M (MemoryOpResult bool) - | _ => - (internal_error "STORECON expected word or double") : M (MemoryOpResult bool) - end >>= fun res : MemoryOpResult bool => - (match res with - | MemValue (true) => - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> - let '_ := (cancel_reservation tt) : unit in - returnm (true - : bool) - | MemValue (false) => - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (EXTZ 64 (vec_of_bits [B1] : mword 1)) >> - let '_ := (cancel_reservation tt) : unit in - returnm (true - : bool) - | MemException (e) => handle_mem_exception addr e >> returnm (false : bool) - end) - : M (bool) - end) - : M (bool) - end) - : M (bool)) - : M (bool)) - : M (bool). - -Definition execute_STORE (imm : mword 12) (rs2 : mword 5) (rs1 : mword 5) (width : word_width) (aq : bool) (rl : bool) -: M (bool) := - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun w__0 : mword 64 => - let vaddr : xlenbits := add_vec w__0 (EXTS 64 imm) in - check_misaligned vaddr width >>= fun w__1 : bool => - (if (w__1) then handle_mem_exception vaddr E_SAMO_Addr_Align >> returnm (false : bool) - else - translateAddr vaddr Write Data >>= fun w__2 : TR_Result => - (match w__2 with - | TR_Failure (e) => handle_mem_exception vaddr e >> returnm (false : bool) - | TR_Address (addr) => - match width with - | BYTE => (mem_write_ea addr 1 aq rl false) : M (MemoryOpResult unit) - | HALF => (mem_write_ea addr 2 aq rl false) : M (MemoryOpResult unit) - | WORD => (mem_write_ea addr 4 aq rl false) : M (MemoryOpResult unit) - | DOUBLE => (mem_write_ea addr 8 aq rl false) : M (MemoryOpResult unit) - end >>= fun eares : MemoryOpResult unit => - (match eares with - | MemException (e) => handle_mem_exception addr e >> returnm (false : bool) - | MemValue (_) => - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun rs2_val => - match width with - | BYTE => - (mem_write_value addr 1 (subrange_vec_dec rs2_val 7 0) aq rl false) - : M (MemoryOpResult bool) - | HALF => - (mem_write_value addr 2 (subrange_vec_dec rs2_val 15 0) aq rl false) - : M (MemoryOpResult bool) - | WORD => - (mem_write_value addr 4 (subrange_vec_dec rs2_val 31 0) aq rl false) - : M (MemoryOpResult bool) - | DOUBLE => (mem_write_value addr 8 rs2_val aq rl false) : M (MemoryOpResult bool) - end >>= fun res : MemoryOpResult bool => - (match res with - | MemValue (true) => returnm (true : bool) - | MemValue (false) => - (internal_error "store got false from mem_write_value") : M (bool) - | MemException (e) => handle_mem_exception addr e >> returnm (false : bool) - end) - : M (bool) - end) - : M (bool) - end) - : M (bool)) - : M (bool). - -Definition execute_STOP_FETCHING '(tt : unit) : bool := true. - -Definition execute_SRET '(tt : unit) -: M (bool) := - read_reg cur_privilege_ref >>= fun w__0 : Privilege => - match w__0 with - | User => (handle_illegal tt) : M (unit) - | Supervisor => - read_reg mstatus_ref >>= fun w__1 : Mstatus => - (if ((eq_vec (_get_Mstatus_TSR w__1) ((bool_to_bits true) : mword 1))) then - (handle_illegal tt) - : M (unit) - else - read_reg cur_privilege_ref >>= fun w__2 : Privilege => - (read_reg PC_ref : M (mword 64)) >>= fun w__3 : xlenbits => - handle_exception w__2 (CTL_SRET (tt)) w__3 >>= fun w__4 : mword 64 => - write_reg nextPC_ref w__4 - : M (unit)) - : M (unit) - | Machine => - read_reg cur_privilege_ref >>= fun w__5 : Privilege => - (read_reg PC_ref : M (mword 64)) >>= fun w__6 : xlenbits => - handle_exception w__5 (CTL_SRET (tt)) w__6 >>= fun w__7 : mword 64 => - write_reg nextPC_ref w__7 - : M (unit) - end >> - returnm (false - : bool). - -Definition execute_SHIFTW (shamt : mword 5) (rs1 : mword 5) (rd : mword 5) (op : sop) -: M (bool) := - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun w__0 : mword 64 => - let rs1_val := subrange_vec_dec w__0 31 0 in - let result : bits 32 := - match op with - | RISCV_SLLI => shift_bits_left rs1_val shamt - | RISCV_SRLI => shift_bits_right rs1_val shamt - | RISCV_SRAI => shift_right_arith32 rs1_val shamt - end in - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) (EXTS 64 result) >> - returnm (true - : bool). - -Definition execute_SHIFTIWOP (shamt : mword 5) (rs1 : mword 5) (rd : mword 5) (op : sopw) -: M (bool) := - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun rs1_val => - let result : xlenbits := - match op with - | RISCV_SLLIW => EXTS 64 (shift_bits_left (subrange_vec_dec rs1_val 31 0) shamt) - | RISCV_SRLIW => EXTS 64 (shift_bits_right (subrange_vec_dec rs1_val 31 0) shamt) - | RISCV_SRAIW => EXTS 64 (shift_right_arith32 (subrange_vec_dec rs1_val 31 0) shamt) - end in - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) result >> - returnm (true - : bool). - -Definition execute_SHIFTIOP (shamt : mword 6) (rs1 : mword 5) (rd : mword 5) (op : sop) -: M (bool) := - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun rs1_val => - let result : xlenbits := - match op with - | RISCV_SLLI => shift_bits_left rs1_val shamt - | RISCV_SRLI => shift_bits_right rs1_val shamt - | RISCV_SRAI => shift_right_arith64 rs1_val shamt - end in - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) result >> - returnm (true - : bool). - -Definition execute_SFENCE_VMA (rs1 : mword 5) (rs2 : mword 5) -: M (bool) := - read_reg cur_privilege_ref >>= fun w__0 : Privilege => - (if ((eq_vec ((privLevel_to_bits w__0) : mword 2) ((privLevel_to_bits User) : mword 2))) then - handle_illegal tt >> returnm (false : bool) - else - read_reg mstatus_ref >>= fun w__1 : Mstatus => - read_reg mstatus_ref >>= fun w__2 : Mstatus => - let p__16 := (architecture (_get_Mstatus_SXL w__1), _get_Mstatus_TVM w__2) in - (match p__16 with - | (Some (RV64), v_0) => - (if ((eq_vec v_0 ((bool_to_bits true) : mword 1))) then - handle_illegal tt >> returnm (false : bool) - else if ((eq_vec v_0 ((bool_to_bits false) : mword 1))) then - (if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - returnm (None - : option (mword 39)) - else - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun w__3 : mword 64 => - returnm ((Some - (subrange_vec_dec w__3 38 0)) - : option (mword 39))) >>= fun addr : option vaddr39 => - (if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - returnm (None - : option (mword 16)) - else - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun w__4 : mword 64 => - returnm ((Some - (subrange_vec_dec w__4 15 0)) - : option (mword 16))) >>= fun asid : option asid64 => - flushTLB asid addr >> returnm (true : bool) - else - (match (Some (RV64), v_0) with - | (g__14, g__15) => (internal_error "unimplemented sfence architecture") : M (bool) - end) - : M (bool)) - : M (bool) - | (g__14, g__15) => (internal_error "unimplemented sfence architecture") : M (bool) - end) - : M (bool)) - : M (bool). - -Definition execute_RTYPEW (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (op : ropw) -: M (bool) := - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun w__0 : mword 64 => - let rs1_val := subrange_vec_dec w__0 31 0 in - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun w__1 : mword 64 => - let rs2_val := subrange_vec_dec w__1 31 0 in - let result : bits 32 := - match op with - | RISCV_ADDW => add_vec rs1_val rs2_val - | RISCV_SUBW => sub_vec rs1_val rs2_val - | RISCV_SLLW => shift_bits_left rs1_val (subrange_vec_dec rs2_val 4 0) - | RISCV_SRLW => shift_bits_right rs1_val (subrange_vec_dec rs2_val 4 0) - | RISCV_SRAW => shift_right_arith32 rs1_val (subrange_vec_dec rs2_val 4 0) - end in - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) (EXTS 64 result) >> - returnm (true - : bool). - -Definition execute_RTYPE (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (op : rop) -: M (bool) := - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun rs1_val => - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun rs2_val => - let result : xlenbits := - match op with - | RISCV_ADD => add_vec rs1_val rs2_val - | RISCV_SUB => sub_vec rs1_val rs2_val - | RISCV_SLL => shift_bits_left rs1_val (subrange_vec_dec rs2_val 5 0) - | RISCV_SLT => EXTZ 64 ((bool_to_bits (zopz0zI_s rs1_val rs2_val)) : mword 1) - | RISCV_SLTU => EXTZ 64 ((bool_to_bits (zopz0zI_u rs1_val rs2_val)) : mword 1) - | RISCV_XOR => xor_vec rs1_val rs2_val - | RISCV_SRL => shift_bits_right rs1_val (subrange_vec_dec rs2_val 5 0) - | RISCV_SRA => shift_right_arith64 rs1_val (subrange_vec_dec rs2_val 5 0) - | RISCV_OR => or_vec rs1_val rs2_val - | RISCV_AND => and_vec rs1_val rs2_val - end in - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) result >> - returnm (true - : bool). - -Definition execute_RISCV_JALR (imm : mword 12) (rs1 : mword 5) (rd : mword 5) -: M (bool) := - (read_reg nextPC_ref : M (mword 64)) >>= fun w__0 : xlenbits => - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) w__0 >> - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun w__1 : mword 64 => - let newPC : xlenbits := add_vec w__1 (EXTS 64 imm) in - write_reg nextPC_ref (concat_vec (subrange_vec_dec newPC 63 1) (vec_of_bits [B0] : mword 1)) >> - returnm (true - : bool). - -Definition execute_RISCV_JAL (imm : mword 21) (rd : mword 5) -: M (bool) := - (read_reg PC_ref : M (mword 64)) >>= fun pc : xlenbits => - (read_reg nextPC_ref : M (mword 64)) >>= fun w__0 : xlenbits => - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) w__0 >> - let offset : xlenbits := EXTS 64 imm in - write_reg nextPC_ref (add_vec pc offset) >> returnm (true : bool). - -Definition execute_REMW (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (s : bool) -: M (bool) := - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun w__0 : mword 64 => - let rs1_val := subrange_vec_dec w__0 31 0 in - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun w__1 : mword 64 => - let rs2_val := subrange_vec_dec w__1 31 0 in - let rs1_int : Z := if (s) then projT1 (sint rs1_val) else projT1 (uint rs1_val) in - let rs2_int : Z := if (s) then projT1 (sint rs2_val) else projT1 (uint rs2_val) in - let r : Z := - if sumbool_of_bool ((Z.eqb rs2_int 0)) then rs1_int - else rem_round_zero rs1_int rs2_int in - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) (EXTS 64 (to_bits 32 r)) >> - returnm (true - : bool). - -Definition execute_REM (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (s : bool) -: M (bool) := - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun rs1_val => - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun rs2_val => - let rs1_int : Z := if (s) then projT1 (sint rs1_val) else projT1 (uint rs1_val) in - let rs2_int : Z := if (s) then projT1 (sint rs2_val) else projT1 (uint rs2_val) in - let r : Z := - if sumbool_of_bool ((Z.eqb rs2_int 0)) then rs1_int - else rem_round_zero rs1_int rs2_int in - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) (to_bits xlen r) >> - returnm (true - : bool). - -Definition execute_NOP '(tt : unit) : bool := true. - -Definition execute_MULW (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) -: M (bool) := - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun w__0 : mword 64 => - let rs1_val := subrange_vec_dec w__0 31 0 in - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun w__1 : mword 64 => - let rs2_val := subrange_vec_dec w__1 31 0 in - let rs1_int : Z := projT1 (sint rs1_val) in - let rs2_int : Z := projT1 (sint rs2_val) in - let result32 := subrange_vec_dec (to_bits 64 (Z.mul rs1_int rs2_int)) 31 0 in - let result : xlenbits := EXTS 64 result32 in - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) result >> - returnm (true - : bool). - -Definition execute_MUL (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (high : bool) (signed1 : bool) (signed2 : bool) -: M (bool) := - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun rs1_val => - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun rs2_val => - let rs1_int : Z := if (signed1) then projT1 (sint rs1_val) else projT1 (uint rs1_val) in - let rs2_int : Z := if (signed2) then projT1 (sint rs2_val) else projT1 (uint rs2_val) in - let result128 := to_bits 128 (Z.mul rs1_int rs2_int) in - let result := - if (high) then subrange_vec_dec result128 127 64 - else subrange_vec_dec result128 63 0 in - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) result >> - returnm (true - : bool). - -Definition execute_MRET '(tt : unit) -: M (bool) := - read_reg cur_privilege_ref >>= fun w__0 : Privilege => - (if ((eq_vec ((privLevel_to_bits w__0) : mword 2) ((privLevel_to_bits Machine) : mword 2))) - then - read_reg cur_privilege_ref >>= fun w__1 : Privilege => - (read_reg PC_ref : M (mword 64)) >>= fun w__2 : xlenbits => - handle_exception w__1 (CTL_MRET (tt)) w__2 >>= fun w__3 : mword 64 => - write_reg nextPC_ref w__3 - : M (unit) - else (handle_illegal tt) : M (unit)) >> - returnm (false - : bool). - -Definition execute_LOADRES (aq : bool) (rl : bool) (rs1 : mword 5) (width : word_width) (rd : mword 5) -: M (bool) := - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun vaddr : xlenbits => - match width with - | BYTE => returnm (true : bool) - | HALF => - cast_unit_vec (access_vec_dec vaddr 0) >>= fun w__0 : mword 1 => - returnm ((eq_vec (w__0 : mword 1) (vec_of_bits [B0] : mword 1)) - : bool) - | WORD => - returnm ((eq_vec (subrange_vec_dec vaddr 1 0) (vec_of_bits [B0;B0] : mword 2)) : bool) - | DOUBLE => - returnm ((eq_vec (subrange_vec_dec vaddr 2 0) (vec_of_bits [B0;B0;B0] : mword 3)) : bool) - end >>= fun aligned : bool => - (if ((negb aligned)) then handle_mem_exception vaddr E_Load_Addr_Align >> returnm (false : bool) - else - translateAddr vaddr Read Data >>= fun w__1 : TR_Result => - (match w__1 with - | TR_Failure (e) => handle_mem_exception vaddr e >> returnm (false : bool) - | TR_Address (addr) => - (match width with - | WORD => - mem_read addr 4 aq rl true >>= fun w__2 : MemoryOpResult (mword (8 * 4)) => - (process_loadres rd vaddr w__2 false) - : M (bool) - | DOUBLE => - mem_read addr 8 aq rl true >>= fun w__4 : MemoryOpResult (mword (8 * 8)) => - (process_loadres rd vaddr w__4 false) - : M (bool) - | _ => (internal_error "LOADRES expected WORD or DOUBLE") : M (bool) - end) - : M (bool) - end) - : M (bool)) - : M (bool). - -Definition execute_LOAD (imm : mword 12) (rs1 : mword 5) (rd : mword 5) (is_unsigned : bool) (width : word_width) (aq : bool) (rl : bool) -: M (bool) := - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun w__0 : mword 64 => - let vaddr : xlenbits := add_vec w__0 (EXTS 64 imm) in - check_misaligned vaddr width >>= fun w__1 : bool => - (if (w__1) then handle_mem_exception vaddr E_Load_Addr_Align >> returnm (false : bool) - else - translateAddr vaddr Read Data >>= fun w__2 : TR_Result => - (match w__2 with - | TR_Failure (e) => handle_mem_exception vaddr e >> returnm (false : bool) - | TR_Address (addr) => - (match width with - | BYTE => - mem_read addr 1 aq rl false >>= fun w__3 : MemoryOpResult (mword (8 * 1)) => - (process_load rd vaddr w__3 is_unsigned) - : M (bool) - | HALF => - mem_read addr 2 aq rl false >>= fun w__5 : MemoryOpResult (mword (8 * 2)) => - (process_load rd vaddr w__5 is_unsigned) - : M (bool) - | WORD => - mem_read addr 4 aq rl false >>= fun w__7 : MemoryOpResult (mword (8 * 4)) => - (process_load rd vaddr w__7 is_unsigned) - : M (bool) - | DOUBLE => - mem_read addr 8 aq rl false >>= fun w__9 : MemoryOpResult (mword (8 * 8)) => - (process_load rd vaddr w__9 is_unsigned) - : M (bool) - end) - : M (bool) - end) - : M (bool)) - : M (bool). - -Definition execute_ITYPE (imm : mword 12) (rs1 : mword 5) (rd : mword 5) (op : iop) -: M (bool) := - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun rs1_val => - let immext : xlenbits := EXTS 64 imm in - let result : xlenbits := - match op with - | RISCV_ADDI => add_vec rs1_val immext - | RISCV_SLTI => EXTZ 64 ((bool_to_bits (zopz0zI_s rs1_val immext)) : mword 1) - | RISCV_SLTIU => EXTZ 64 ((bool_to_bits (zopz0zI_u rs1_val immext)) : mword 1) - | RISCV_XORI => xor_vec rs1_val immext - | RISCV_ORI => or_vec rs1_val immext - | RISCV_ANDI => and_vec rs1_val immext - end in - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) result >> - returnm (true - : bool). - -Definition execute_ILLEGAL (s : mword 32) -: M (bool) := - handle_illegal tt >> returnm (false : bool). - -Definition execute_FENCEI '(tt : unit) : bool := true. - -Definition execute_FENCE (pred : mword 4) (succ : mword 4) -: M (bool) := - match (pred, succ) with - | (v__132, v__133) => - (if ((andb (eq_vec (subrange_vec_dec v__132 1 0) (vec_of_bits [B1;B1] : mword 2)) - (eq_vec (subrange_vec_dec v__133 1 0) (vec_of_bits [B1;B1] : mword 2)))) then - (MEM_fence_rw_rw tt) - : M (unit) - else if ((andb (eq_vec (subrange_vec_dec v__132 1 0) (vec_of_bits [B1;B0] : mword 2)) - (eq_vec (subrange_vec_dec v__133 1 0) (vec_of_bits [B1;B1] : mword 2)))) then - (MEM_fence_r_rw tt) - : M (unit) - else if ((andb (eq_vec (subrange_vec_dec v__132 1 0) (vec_of_bits [B1;B0] : mword 2)) - (eq_vec (subrange_vec_dec v__133 1 0) (vec_of_bits [B1;B0] : mword 2)))) then - (MEM_fence_r_r tt) - : M (unit) - else if ((andb (eq_vec (subrange_vec_dec v__132 1 0) (vec_of_bits [B1;B1] : mword 2)) - (eq_vec (subrange_vec_dec v__133 1 0) (vec_of_bits [B0;B1] : mword 2)))) then - (MEM_fence_rw_w tt) - : M (unit) - else if ((andb (eq_vec (subrange_vec_dec v__132 1 0) (vec_of_bits [B0;B1] : mword 2)) - (eq_vec (subrange_vec_dec v__133 1 0) (vec_of_bits [B0;B1] : mword 2)))) then - (MEM_fence_w_w tt) - : M (unit) - else if ((andb (eq_vec (subrange_vec_dec v__132 1 0) (vec_of_bits [B0;B1] : mword 2)) - (eq_vec (subrange_vec_dec v__133 1 0) (vec_of_bits [B1;B1] : mword 2)))) then - (MEM_fence_w_rw tt) - : M (unit) - else if ((andb (eq_vec (subrange_vec_dec v__132 1 0) (vec_of_bits [B1;B1] : mword 2)) - (eq_vec (subrange_vec_dec v__133 1 0) (vec_of_bits [B1;B0] : mword 2)))) then - (MEM_fence_rw_r tt) - : M (unit) - else if ((andb (eq_vec (subrange_vec_dec v__132 1 0) (vec_of_bits [B1;B0] : mword 2)) - (eq_vec (subrange_vec_dec v__133 1 0) (vec_of_bits [B0;B1] : mword 2)))) then - (MEM_fence_r_w tt) - : M (unit) - else if ((andb (eq_vec (subrange_vec_dec v__132 1 0) (vec_of_bits [B0;B1] : mword 2)) - (eq_vec (subrange_vec_dec v__133 1 0) (vec_of_bits [B1;B0] : mword 2)))) then - (MEM_fence_w_r tt) - : M (unit) - else - returnm ((if ((andb (eq_vec (subrange_vec_dec v__132 1 0) (vec_of_bits [B0;B0] : mword 2)) - (eq_vec (subrange_vec_dec v__133 1 0) (vec_of_bits [B0;B0] : mword 2)))) - then - tt - else - let '_ := (print_endline "FIXME: unsupported fence") : unit in - tt) - : unit)) - : M (unit) - end >> - returnm (true - : bool). - -Definition execute_ECALL '(tt : unit) -: M (bool) := - read_reg cur_privilege_ref >>= fun w__0 : Privilege => - let t : sync_exception := - {| sync_exception_trap := - (match w__0 with - | User => E_U_EnvCall - | Supervisor => E_S_EnvCall - | Machine => E_M_EnvCall - end); - sync_exception_excinfo := (None : option xlenbits) |} in - read_reg cur_privilege_ref >>= fun w__1 : Privilege => - (read_reg PC_ref : M (mword 64)) >>= fun w__2 : xlenbits => - handle_exception w__1 (CTL_TRAP (t)) w__2 >>= fun w__3 : mword 64 => - write_reg nextPC_ref w__3 >> returnm (false : bool). - -Definition execute_EBREAK '(tt : unit) -: M (bool) := - (read_reg PC_ref : M (mword 64)) >>= fun w__0 : xlenbits => - handle_mem_exception w__0 E_Breakpoint >> returnm (false : bool). - -Definition execute_DIVW (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (s : bool) -: M (bool) := - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun w__0 : mword 64 => - let rs1_val := subrange_vec_dec w__0 31 0 in - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun w__1 : mword 64 => - let rs2_val := subrange_vec_dec w__1 31 0 in - let rs1_int : Z := if (s) then projT1 (sint rs1_val) else projT1 (uint rs1_val) in - let rs2_int : Z := if (s) then projT1 (sint rs2_val) else projT1 (uint rs2_val) in - let q : Z := if sumbool_of_bool ((Z.eqb rs2_int 0)) then -1 else quot_round_zero rs1_int rs2_int in - let q' : Z := - if sumbool_of_bool ((andb s - (Z.gtb q (projT1 (sub_range (build_ex (projT1 (pow2 31))) (build_ex 1)))))) - then - projT1 (sub_range (build_ex 0) - (build_ex (projT1 ((build_ex (projT1 (ex_int (pow 2 31)))) - : {n : Z & ArithFact (True)})))) - else q in - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) (EXTS 64 (to_bits 32 q')) >> - returnm (true - : bool). - -Definition execute_DIV (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (s : bool) -: M (bool) := - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun rs1_val => - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun rs2_val => - let rs1_int : Z := if (s) then projT1 (sint rs1_val) else projT1 (uint rs1_val) in - let rs2_int : Z := if (s) then projT1 (sint rs2_val) else projT1 (uint rs2_val) in - let q : Z := if sumbool_of_bool ((Z.eqb rs2_int 0)) then -1 else quot_round_zero rs1_int rs2_int in - let q' : Z := if sumbool_of_bool ((andb s (Z.gtb q xlen_max_signed))) then xlen_min_signed else q in - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) (to_bits xlen q') >> - returnm (true - : bool). - -Definition execute_C_ILLEGAL '(tt : unit) -: M (bool) := - handle_illegal tt >> returnm (false : bool). - -Definition execute_C_ADDIW (imm : mword 6) (rsd : mword 5) -: M (bool) := - let imm : bits 32 := EXTS 32 imm in - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rsd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun rs_val => - let res : bits 32 := add_vec (subrange_vec_dec rs_val 31 0) imm in - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rsd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) (EXTS 64 res) >> - returnm (true - : bool). - -Definition execute_CSR (csr : mword 12) (rs1 : mword 5) (rd : mword 5) (is_imm : bool) (op : csrop) -: M (bool) := - (if (is_imm) then returnm ((EXTZ 64 rs1) : mword 64) - else - (rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)}))) - : M (mword 64)) >>= fun rs1_val : xlenbits => - let isWrite : bool := - match op with - | CSRRW => true - | _ => - if (is_imm) then neq_range (build_ex (projT1 (uint rs1_val))) (build_ex 0) - else neq_range (build_ex (projT1 (uint rs1))) (build_ex 0) - end in - read_reg cur_privilege_ref >>= fun w__1 : Privilege => - check_CSR csr w__1 isWrite >>= fun w__2 : bool => - (if ((negb w__2)) then handle_illegal tt >> returnm (false : bool) - else - readCSR csr >>= fun csr_val => - (if (isWrite) then - let new_val : xlenbits := - match op with - | CSRRW => rs1_val - | CSRRS => or_vec csr_val rs1_val - | CSRRC => and_vec csr_val (not_vec rs1_val) - end in - (writeCSR csr new_val) - : M (unit) - else returnm (tt : unit)) >> - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) csr_val >> - returnm (true - : bool)) - : M (bool). - -Definition execute_BTYPE (imm : mword 13) (rs2 : mword 5) (rs1 : mword 5) (op : bop) -: M (bool) := - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun rs1_val => - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun rs2_val => - let taken : bool := - match op with - | RISCV_BEQ => eq_vec rs1_val rs2_val - | RISCV_BNE => neq_vec rs1_val rs2_val - | RISCV_BLT => zopz0zI_s rs1_val rs2_val - | RISCV_BGE => zopz0zKzJ_s rs1_val rs2_val - | RISCV_BLTU => zopz0zI_u rs1_val rs2_val - | RISCV_BGEU => zopz0zKzJ_u rs1_val rs2_val - end in - (if (taken) then - (read_reg PC_ref : M (mword 64)) >>= fun w__0 : xlenbits => - write_reg nextPC_ref (add_vec w__0 (EXTS 64 imm)) - : M (unit) - else returnm (tt : unit)) >> - returnm (true - : bool). - -Definition execute_AMO (op : amoop) (aq : bool) (rl : bool) (rs2 : mword 5) (rs1 : mword 5) (width : word_width) (rd : mword 5) -: M (bool) := - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun vaddr : xlenbits => - translateAddr vaddr ReadWrite Data >>= fun w__0 : TR_Result => - (match w__0 with - | TR_Failure (e) => handle_mem_exception vaddr e >> returnm (false : bool) - | TR_Address (addr) => - match width with - | WORD => (mem_write_ea addr 4 (andb aq rl) rl true) : M (MemoryOpResult unit) - | DOUBLE => (mem_write_ea addr 8 (andb aq rl) rl true) : M (MemoryOpResult unit) - | _ => (internal_error "AMO expected WORD or DOUBLE") : M (MemoryOpResult unit) - end >>= fun eares : MemoryOpResult unit => - (match eares with - | MemException (e) => handle_mem_exception addr e >> returnm (false : bool) - | MemValue (_) => - match width with - | WORD => - mem_read addr 4 aq (andb aq rl) true >>= fun w__4 : MemoryOpResult (mword (8 * 4)) => - returnm ((extend_value false w__4) - : MemoryOpResult (mword 64)) - | DOUBLE => - mem_read addr 8 aq (andb aq rl) true >>= fun w__5 : MemoryOpResult (mword (8 * 8)) => - returnm ((extend_value false w__5) - : MemoryOpResult (mword 64)) - | _ => (internal_error "AMO expected WORD or DOUBLE") : M (MemoryOpResult (mword 64)) - end >>= fun rval : MemoryOpResult xlenbits => - (match rval with - | MemException (e) => handle_mem_exception addr e >> returnm (false : bool) - | MemValue (loaded) => - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun rs2_val : xlenbits => - let result : xlenbits := - match op with - | AMOSWAP => rs2_val - | AMOADD => add_vec rs2_val loaded - | AMOXOR => xor_vec rs2_val loaded - | AMOAND => and_vec rs2_val loaded - | AMOOR => or_vec rs2_val loaded - | AMOMIN => vector64 (Z.min (projT1 (sint rs2_val)) (projT1 (sint loaded))) - | AMOMAX => vector64 (Z.max (projT1 (sint rs2_val)) (projT1 (sint loaded))) - | AMOMINU => - vector64 - (projT1 (min_nat (build_ex (projT1 (uint rs2_val))) - (build_ex (projT1 (uint loaded))))) - | AMOMAXU => - vector64 - (projT1 (max_nat (build_ex (projT1 (uint rs2_val))) - (build_ex (projT1 (uint loaded))))) - end in - match width with - | WORD => - (mem_write_value addr 4 (subrange_vec_dec result 31 0) (andb aq rl) rl true) - : M (MemoryOpResult bool) - | DOUBLE => - (mem_write_value addr 8 result (andb aq rl) rl true) : M (MemoryOpResult bool) - | _ => (internal_error "AMO expected WORD or DOUBLE") : M (MemoryOpResult bool) - end >>= fun wval : MemoryOpResult bool => - (match wval with - | MemValue (true) => - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) loaded >> - returnm (true - : bool) - | MemValue (false) => - (internal_error "AMO got false from mem_write_value") : M (bool) - | MemException (e) => handle_mem_exception addr e >> returnm (false : bool) - end) - : M (bool) - end) - : M (bool) - end) - : M (bool) - end) - : M (bool). - -Definition execute_ADDIW (imm : mword 12) (rs1 : mword 5) (rd : mword 5) -: M (bool) := - rX - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) >>= fun w__0 : mword 64 => - let result : xlenbits := add_vec (EXTS 64 imm) w__0 in - wX - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) (EXTS 64 (subrange_vec_dec result 31 0)) >> - returnm (true - : bool). - -Definition expand_ast (i : ast) : ast := -match i with - | C_ADDI4SPN (rdc,nzimm) => - let imm : bits 12 := - concat_vec (vec_of_bits [B0;B0] : mword 2) - (concat_vec nzimm (vec_of_bits [B0;B0] : mword 2)) in - let rd := creg2reg_bits rdc in - ( (ITYPE (imm, sp, rd, RISCV_ADDI))) - - | C_LW (uimm,rsc,rdc) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in - let rd := creg2reg_bits rdc in - let rs := creg2reg_bits rsc in - ( (LOAD (imm, rs, rd, false, WORD, false, false))) - - | C_LD (uimm,rsc,rdc) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in - let rd := creg2reg_bits rdc in - let rs := creg2reg_bits rsc in - ( (LOAD (imm, rs, rd, false, DOUBLE, false, false))) - - | C_SW (uimm,rsc1,rsc2) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in - let rs1 := creg2reg_bits rsc1 in - let rs2 := creg2reg_bits rsc2 in - ( (STORE (imm, rs2, rs1, WORD, false, false))) - - | C_SD (uimm,rsc1,rsc2) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in - let rs1 := creg2reg_bits rsc1 in - let rs2 := creg2reg_bits rsc2 in - ( (STORE (imm, rs2, rs1, DOUBLE, false, false))) - - | C_ADDI (nzi,rsd) => - let imm : bits 12 := EXTS 12 nzi in - ( (ITYPE (imm, rsd, rsd, RISCV_ADDI))) - - | C_JAL (imm) => - ( (RISCV_JAL (EXTS 21 (concat_vec imm (vec_of_bits [B0] : mword 1)), ra))) - | C_LI (imm,rd) => - let imm : bits 12 := EXTS 12 imm in - ( (ITYPE (imm, zreg, rd, RISCV_ADDI))) - - | C_ADDI16SP (imm) => - let imm : bits 12 := EXTS 12 (concat_vec imm (vec_of_bits [B0;B0;B0;B0] : mword 4)) in - ( (ITYPE (imm, sp, sp, RISCV_ADDI))) - - | C_LUI (imm,rd) => - let res : bits 20 := EXTS 20 imm in - ( (UTYPE (res, rd, RISCV_LUI))) - - | C_SRLI (shamt,rsd) => - let rsd := creg2reg_bits rsd in - ( (SHIFTIOP (shamt, rsd, rsd, RISCV_SRLI))) - - | C_SRAI (shamt,rsd) => - let rsd := creg2reg_bits rsd in - ( (SHIFTIOP (shamt, rsd, rsd, RISCV_SRAI))) - - | C_ANDI (imm,rsd) => - let rsd := creg2reg_bits rsd in - ( (ITYPE (EXTS 12 imm, rsd, rsd, RISCV_ANDI))) - - | C_SUB (rsd,rs2) => - let rsd := creg2reg_bits rsd in - let rs2 := creg2reg_bits rs2 in - ( (RTYPE (rs2, rsd, rsd, RISCV_SUB))) - - | C_XOR (rsd,rs2) => - let rsd := creg2reg_bits rsd in - let rs2 := creg2reg_bits rs2 in - ( (RTYPE (rs2, rsd, rsd, RISCV_XOR))) - - | C_OR (rsd,rs2) => - let rsd := creg2reg_bits rsd in - let rs2 := creg2reg_bits rs2 in - ( (RTYPE (rs2, rsd, rsd, RISCV_OR))) - - | C_AND (rsd,rs2) => - let rsd := creg2reg_bits rsd in - let rs2 := creg2reg_bits rs2 in - ( (RTYPE (rs2, rsd, rsd, RISCV_AND))) - - | C_SUBW (rsd,rs2) => - let rsd := creg2reg_bits rsd in - let rs2 := creg2reg_bits rs2 in - ( (RTYPEW (rs2, rsd, rsd, RISCV_SUBW))) - - | C_ADDW (rsd,rs2) => - let rsd := creg2reg_bits rsd in - let rs2 := creg2reg_bits rs2 in - ( (RTYPEW (rs2, rsd, rsd, RISCV_ADDW))) - - | C_J (imm) => - ( (RISCV_JAL (EXTS 21 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg))) - - | C_BEQZ (imm,rs) => - ( - (BTYPE - (EXTS 13 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg, creg2reg_bits rs, - RISCV_BEQ))) - - | C_BNEZ (imm,rs) => - ( - (BTYPE - (EXTS 13 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg, creg2reg_bits rs, - RISCV_BNE))) - - | C_SLLI (shamt,rsd) => ( (SHIFTIOP (shamt, rsd, rsd, RISCV_SLLI))) - | C_LWSP (uimm,rd) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in - ( (LOAD (imm, sp, rd, false, WORD, false, false))) - - | C_LDSP (uimm,rd) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in - ( (LOAD (imm, sp, rd, false, DOUBLE, false, false))) - - | C_SWSP (uimm,rs2) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in - ( (STORE (imm, rs2, sp, WORD, false, false))) - - | C_SDSP (uimm,rs2) => - let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in - ( (STORE (imm, rs2, sp, DOUBLE, false, false))) - - | C_JR (rs1) => - ( (RISCV_JALR (EXTZ 12 (vec_of_bits [B0] : mword 1), rs1, zreg))) - | C_JALR (rs1) => - ( (RISCV_JALR (EXTZ 12 (vec_of_bits [B0] : mword 1), rs1, ra))) - | C_MV (rd,rs2) => ( (RTYPE (rs2, zreg, rd, RISCV_ADD))) - | C_ADD (rsd,rs2) => ( (RTYPE (rs2, rsd, rsd, RISCV_ADD))) -| i => i -end. - -Fixpoint execute (merge_var : ast) -: M (bool) := -let merge_var := expand_ast merge_var in - match merge_var with - | UTYPE (imm,rd,op) => (execute_UTYPE imm rd op) : M (bool) - | RISCV_JAL (imm,rd) => (execute_RISCV_JAL imm rd) : M (bool) - | RISCV_JALR (imm,rs1,rd) => (execute_RISCV_JALR imm rs1 rd) : M (bool) - | BTYPE (imm,rs2,rs1,op) => (execute_BTYPE imm rs2 rs1 op) : M (bool) - | ITYPE (imm,rs1,rd,op) => (execute_ITYPE imm rs1 rd op) : M (bool) - | SHIFTIOP (shamt,rs1,rd,op) => (execute_SHIFTIOP shamt rs1 rd op) : M (bool) - | RTYPE (rs2,rs1,rd,op) => (execute_RTYPE rs2 rs1 rd op) : M (bool) - | LOAD (imm,rs1,rd,is_unsigned,width,aq,rl) => - (execute_LOAD imm rs1 rd is_unsigned width aq rl) : M (bool) - | STORE (imm,rs2,rs1,width,aq,rl) => (execute_STORE imm rs2 rs1 width aq rl) : M (bool) - | ADDIW (imm,rs1,rd) => (execute_ADDIW imm rs1 rd) : M (bool) - | SHIFTW (shamt,rs1,rd,op) => (execute_SHIFTW shamt rs1 rd op) : M (bool) - | RTYPEW (rs2,rs1,rd,op) => (execute_RTYPEW rs2 rs1 rd op) : M (bool) - | SHIFTIWOP (shamt,rs1,rd,op) => (execute_SHIFTIWOP shamt rs1 rd op) : M (bool) - | MUL (rs2,rs1,rd,high,signed1,signed2) => - (execute_MUL rs2 rs1 rd high signed1 signed2) : M (bool) - | DIV (rs2,rs1,rd,s) => (execute_DIV rs2 rs1 rd s) : M (bool) - | REM (rs2,rs1,rd,s) => (execute_REM rs2 rs1 rd s) : M (bool) - | MULW (rs2,rs1,rd) => (execute_MULW rs2 rs1 rd) : M (bool) - | DIVW (rs2,rs1,rd,s) => (execute_DIVW rs2 rs1 rd s) : M (bool) - | REMW (rs2,rs1,rd,s) => (execute_REMW rs2 rs1 rd s) : M (bool) - | FENCE (pred,succ) => (execute_FENCE pred succ) : M (bool) - | FENCEI (arg0) => returnm ((execute_FENCEI arg0) : bool) - | ECALL (arg0) => (execute_ECALL arg0) : M (bool) - | MRET (arg0) => (execute_MRET arg0) : M (bool) - | SRET (arg0) => (execute_SRET arg0) : M (bool) - | EBREAK (arg0) => (execute_EBREAK arg0) : M (bool) - | WFI (arg0) => (execute_WFI arg0) : M (bool) - | SFENCE_VMA (rs1,rs2) => (execute_SFENCE_VMA rs1 rs2) : M (bool) - | LOADRES (aq,rl,rs1,width,rd) => (execute_LOADRES aq rl rs1 width rd) : M (bool) - | STORECON (aq,rl,rs2,rs1,width,rd) => (execute_STORECON aq rl rs2 rs1 width rd) : M (bool) - | AMO (op,aq,rl,rs2,rs1,width,rd) => (execute_AMO op aq rl rs2 rs1 width rd) : M (bool) - | CSR (csr,rs1,rd,is_imm,op) => (execute_CSR csr rs1 rd is_imm op) : M (bool) - | NOP (arg0) => returnm ((execute_NOP arg0) : bool) - | C_ADDIW (imm,rsd) => (execute_C_ADDIW imm rsd) : M (bool) - | STOP_FETCHING (arg0) => returnm ((execute_STOP_FETCHING arg0) : bool) - | THREAD_START (arg0) => returnm ((execute_THREAD_START arg0) : bool) - | ILLEGAL (s) => (execute_ILLEGAL s) : M (bool) - | C_ILLEGAL (arg0) => (execute_C_ILLEGAL arg0) : M (bool) -| _ => Fail "Unexpanded instruction" - end. - -Definition assembly_forwards (arg_ : ast) -: M (string) := - (match arg_ with - | UTYPE (imm,rd,op) => - returnm ((string_append (utype_mnemonic_forwards op) - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) (string_append (string_of_bits imm) ""))))) - : string) - | RISCV_JAL (imm,rd) => - returnm ((string_append "jal" - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) (string_append (string_of_bits imm) ""))))) - : string) - | RISCV_JALR (imm,rs1,rd) => - returnm ((string_append "jalr" - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (sep_forwards tt) - (string_append (string_of_bits imm) ""))))))) - : string) - | BTYPE (imm,rs2,rs1,op) => - returnm ((string_append (btype_mnemonic_forwards op) - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs2) - (string_append (sep_forwards tt) - (string_append (string_of_bits imm) ""))))))) - : string) - | ITYPE (imm,rs1,rd,op) => - returnm ((string_append (itype_mnemonic_forwards op) - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (sep_forwards tt) - (string_append (string_of_bits imm) ""))))))) - : string) - | SHIFTIOP (shamt,rs1,rd,op) => - returnm ((string_append (shiftiop_mnemonic_forwards op) - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (string_of_bits shamt) "")))))) - : string) - | RTYPE (rs2,rs1,rd,op) => - returnm ((string_append (rtype_mnemonic_forwards op) - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs2) ""))))))) - : string) - | LOAD (imm,rs1,rd,is_unsigned,size,aq,rl) => - returnm ((string_append "l" - (string_append (size_mnemonic_forwards size) - (string_append (maybe_u_forwards is_unsigned) - (string_append (maybe_aq_forwards aq) - (string_append (maybe_rl_forwards rl) - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (sep_forwards tt) - (string_append (string_of_bits imm) ""))))))))))) - : string) - | STORE (imm,rs1,rd,size,aq,rl) => - returnm ((string_append "s" - (string_append (size_mnemonic_forwards size) - (string_append (maybe_aq_forwards aq) - (string_append (maybe_rl_forwards rl) - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (sep_forwards tt) - (string_append (string_of_bits imm) "")))))))))) - : string) - | ADDIW (imm,rs1,rd) => - returnm ((string_append "addiw" - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (sep_forwards tt) - (string_append (string_of_bits imm) ""))))))) - : string) - | SHIFTW (shamt,rs1,rd,op) => - returnm ((string_append (shiftw_mnemonic_forwards op) - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (sep_forwards tt) - (string_append (string_of_bits shamt) ""))))))) - : string) - | RTYPEW (rs2,rs1,rd,op) => - returnm ((string_append (rtypew_mnemonic_forwards op) - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs2) ""))))))) - : string) - | SHIFTIWOP (shamt,rs1,rd,op) => - returnm ((string_append (shiftiwop_mnemonic_forwards op) - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (string_of_bits shamt) "")))))) - : string) - | MUL (rs2,rs1,rd,high,signed1,signed2) => - mul_mnemonic_forwards high signed1 signed2 >>= fun w__0 : string => - returnm ((string_append w__0 - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs2) ""))))))) - : string) - | DIV (rs2,rs1,rd,s) => - returnm ((string_append "div" - (string_append (maybe_not_u_forwards s) - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs2) "")))))))) - : string) - | REM (rs2,rs1,rd,s) => - returnm ((string_append "rem" - (string_append (maybe_not_u_forwards s) - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs2) "")))))))) - : string) - | MULW (rs2,rs1,rd) => - returnm ((string_append "mulw" - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs2) ""))))))) - : string) - | DIVW (rs2,rs1,rd,s) => - returnm ((string_append "div" - (string_append (maybe_not_u_forwards s) - (string_append "w" - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs2) ""))))))))) - : string) - | REMW (rs2,rs1,rd,s) => - returnm ((string_append "rem" - (string_append (maybe_not_u_forwards s) - (string_append "w" - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs2) ""))))))))) - : string) - | FENCE (pred,succ) => - returnm ((string_append "fence" - (string_append (spc_forwards tt) - (string_append (fence_bits_forwards pred) - (string_append (sep_forwards tt) - (string_append (fence_bits_forwards succ) ""))))) - : string) - | FENCEI (tt) => returnm ("fence.i" : string) - | ECALL (tt) => returnm ("ecall" : string) - | MRET (tt) => returnm ("mret" : string) - | SRET (tt) => returnm ("sret" : string) - | EBREAK (tt) => returnm ("ebreak" : string) - | WFI (tt) => returnm ("wfi" : string) - | SFENCE_VMA (rs1,rs2) => - returnm ((string_append "sfence.vma" - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (sep_forwards tt) (string_append (reg_name_forwards rs2) ""))))) - : string) - | LOADRES (aq,rl,rs1,size,rd) => - returnm ((string_append "lr." - (string_append (maybe_aq_forwards aq) - (string_append (maybe_rl_forwards rl) - (string_append (size_mnemonic_forwards size) - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs1) "")))))))) - : string) - | STORECON (aq,rl,rs2,rs1,size,rd) => - returnm ((string_append "sc." - (string_append (maybe_aq_forwards aq) - (string_append (maybe_rl_forwards rl) - (string_append (size_mnemonic_forwards size) - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs2) "")))))))))) - : string) - | AMO (op,aq,rl,rs2,rs1,width,rd) => - returnm ((string_append (amo_mnemonic_forwards op) - (string_append "." - (string_append (size_mnemonic_forwards width) - (string_append (maybe_aq_forwards aq) - (string_append (maybe_rl_forwards rl) - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs2) ""))))))))))) - : string) - | CSR (csr,rs1,rd,true,op) => - returnm ((string_append (csr_mnemonic_forwards op) - (string_append "i" - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (string_of_bits rs1) - (string_append (sep_forwards tt) - (string_append (csr_name_map_forwards csr) "")))))))) - : string) - | CSR (csr,rs1,rd,false,op) => - returnm ((string_append (csr_mnemonic_forwards op) - (string_append (spc_forwards tt) - (string_append (reg_name_forwards rd) - (string_append (sep_forwards tt) - (string_append (reg_name_forwards rs1) - (string_append (sep_forwards tt) - (string_append (csr_name_map_forwards csr) ""))))))) - : string) - | ILLEGAL (s) => - returnm ((string_append "illegal" - (string_append (spc_forwards tt) (string_append (string_of_bits s) ""))) - : string) - | _ => exit tt : M (string) - end) - : M (string). -(* -Definition assembly_backwards (arg_ : string) -: M (ast) := - let _stringappend_756_ := arg_ in - match (utype_mnemonic_matches_prefix _stringappend_756_) with - | Some (op,(existT _ _stringappend_757_ _)) => - let _stringappend_758_ := string_drop _stringappend_756_ (build_ex _stringappend_757_) in - match (spc_matches_prefix _stringappend_758_) with - | Some (tt,(existT _ _stringappend_759_ _)) => - let _stringappend_760_ := string_drop _stringappend_758_ (build_ex _stringappend_759_) in - match (reg_name_matches_prefix _stringappend_760_) with - | Some (rd,(existT _ _stringappend_761_ _)) => - let _stringappend_762_ := string_drop _stringappend_760_ (build_ex _stringappend_761_) in - sep_matches_prefix _stringappend_762_ >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__0 with - | Some (tt,(existT _ _stringappend_763_ _)) => - let _stringappend_764_ := - string_drop _stringappend_762_ (build_ex _stringappend_763_) in - if ((match (hex_bits_20_matches_prefix _stringappend_764_) with - | Some (imm,(existT _ _stringappend_765_ _)) => - match (string_drop _stringappend_764_ - (build_ex _stringappend_765_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__1 : bool => - returnm ((if (w__1) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__2 : bool => - returnm ((if (w__2) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__3 : bool => - (if (w__3) then - (match (utype_mnemonic_matches_prefix _stringappend_756_) with - | Some (op,(existT _ _stringappend_757_ _)) => returnm (op, build_ex _stringappend_757_) - | _ => exit tt : M ((uop * {n : Z & ArithFact (n >= 0)})) - end : M ((uop * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_757_ _) => - let _stringappend_758_ := string_drop _stringappend_756_ (build_ex _stringappend_757_) in - (match (spc_matches_prefix _stringappend_758_) with - | Some (tt,(existT _ _stringappend_759_ _)) => returnm (tt, build_ex _stringappend_759_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_759_ _) => - let _stringappend_760_ := string_drop _stringappend_758_ (build_ex _stringappend_759_) in - (match (reg_name_matches_prefix _stringappend_760_) with - | Some (rd,(existT _ _stringappend_761_ _)) => returnm (rd, build_ex _stringappend_761_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_761_ _) => - let _stringappend_762_ := string_drop _stringappend_760_ (build_ex _stringappend_761_) in - sep_matches_prefix _stringappend_762_ >>= fun w__10 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__10 with - | Some (tt,(existT _ _stringappend_763_ _)) => returnm (tt, build_ex _stringappend_763_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_763_ _) => - let _stringappend_764_ := string_drop _stringappend_762_ (build_ex _stringappend_763_) in - (match (hex_bits_20_matches_prefix _stringappend_764_) with - | Some (imm,(existT _ _stringappend_765_ _)) => returnm (imm, build_ex _stringappend_765_) - | _ => exit tt : M ((mword 20 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 20 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_765_ _) => - (match (string_drop _stringappend_764_ (build_ex _stringappend_765_)) with - | "" => returnm ((UTYPE (imm, rd, op)) : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - and_boolM (returnm ((string_startswith _stringappend_756_ "jal") : bool)) - (let _stringappend_767_ := - string_drop _stringappend_756_ (build_ex (projT1 (string_length "jal"))) in - match (spc_matches_prefix _stringappend_767_) with - | Some (tt,(existT _ _stringappend_768_ _)) => - let _stringappend_769_ := string_drop _stringappend_767_ (build_ex _stringappend_768_) in - match (reg_name_matches_prefix _stringappend_769_) with - | Some (rd,(existT _ _stringappend_770_ _)) => - let _stringappend_771_ := string_drop _stringappend_769_ (build_ex _stringappend_770_) in - sep_matches_prefix _stringappend_771_ >>= fun w__17 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__17 with - | Some (tt,(existT _ _stringappend_772_ _)) => - let _stringappend_773_ := - string_drop _stringappend_771_ (build_ex _stringappend_772_) in - if ((match (hex_bits_21_matches_prefix _stringappend_773_) with - | Some (imm,(existT _ _stringappend_774_ _)) => - match (string_drop _stringappend_773_ - (build_ex _stringappend_774_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__18 : bool => - returnm ((if (w__18) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__19 : bool => - returnm ((if (w__19) then true - else false) - : bool)) >>= fun w__20 : bool => - (if (w__20) then - let _stringappend_767_ := - string_drop _stringappend_756_ (build_ex (projT1 (string_length "jal"))) in - (match (spc_matches_prefix _stringappend_767_) with - | Some (tt,(existT _ _stringappend_768_ _)) => returnm (tt, build_ex _stringappend_768_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_768_ _) => - let _stringappend_769_ := string_drop _stringappend_767_ (build_ex _stringappend_768_) in - (match (reg_name_matches_prefix _stringappend_769_) with - | Some (rd,(existT _ _stringappend_770_ _)) => returnm (rd, build_ex _stringappend_770_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_770_ _) => - let _stringappend_771_ := string_drop _stringappend_769_ (build_ex _stringappend_770_) in - sep_matches_prefix _stringappend_771_ >>= fun w__25 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__25 with - | Some (tt,(existT _ _stringappend_772_ _)) => returnm (tt, build_ex _stringappend_772_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_772_ _) => - let _stringappend_773_ := string_drop _stringappend_771_ (build_ex _stringappend_772_) in - (match (hex_bits_21_matches_prefix _stringappend_773_) with - | Some (imm,(existT _ _stringappend_774_ _)) => returnm (imm, build_ex _stringappend_774_) - | _ => exit tt : M ((mword 21 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 21 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_774_ _) => - (match (string_drop _stringappend_773_ (build_ex _stringappend_774_)) with - | "" => returnm ((RISCV_JAL (imm, rd)) : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - and_boolM (returnm ((string_startswith _stringappend_756_ "jalr") : bool)) - (let _stringappend_776_ := - string_drop _stringappend_756_ (build_ex (projT1 (string_length "jalr"))) in - match (spc_matches_prefix _stringappend_776_) with - | Some (tt,(existT _ _stringappend_777_ _)) => - let _stringappend_778_ := string_drop _stringappend_776_ (build_ex _stringappend_777_) in - match (reg_name_matches_prefix _stringappend_778_) with - | Some (rd,(existT _ _stringappend_779_ _)) => - let _stringappend_780_ := - string_drop _stringappend_778_ (build_ex _stringappend_779_) in - sep_matches_prefix _stringappend_780_ >>= fun w__32 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__32 with - | Some (tt,(existT _ _stringappend_781_ _)) => - let _stringappend_782_ := - string_drop _stringappend_780_ (build_ex _stringappend_781_) in - match (reg_name_matches_prefix _stringappend_782_) with - | Some (rs1,(existT _ _stringappend_783_ _)) => - let _stringappend_784_ := - string_drop _stringappend_782_ (build_ex _stringappend_783_) in - sep_matches_prefix _stringappend_784_ >>= fun w__33 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__33 with - | Some (tt,(existT _ _stringappend_785_ _)) => - let _stringappend_786_ := - string_drop _stringappend_784_ - (build_ex _stringappend_785_) in - if ((match (hex_bits_12_matches_prefix _stringappend_786_) with - | Some (imm,(existT _ _stringappend_787_ _)) => - match (string_drop _stringappend_786_ - (build_ex _stringappend_787_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__34 : bool => - returnm ((if (w__34) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__35 : bool => - returnm ((if (w__35) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__36 : bool => - returnm ((if (w__36) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__37 : bool => - returnm ((if (w__37) then true - else false) - : bool)) >>= fun w__38 : bool => - (if (w__38) then - let _stringappend_776_ := - string_drop _stringappend_756_ (build_ex (projT1 (string_length "jalr"))) in - (match (spc_matches_prefix _stringappend_776_) with - | Some (tt,(existT _ _stringappend_777_ _)) => - returnm (tt, build_ex _stringappend_777_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_777_ _) => - let _stringappend_778_ := string_drop _stringappend_776_ (build_ex _stringappend_777_) in - (match (reg_name_matches_prefix _stringappend_778_) with - | Some (rd,(existT _ _stringappend_779_ _)) => - returnm (rd, build_ex _stringappend_779_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_779_ _) => - let _stringappend_780_ := string_drop _stringappend_778_ (build_ex _stringappend_779_) in - sep_matches_prefix _stringappend_780_ >>= fun w__43 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__43 with - | Some (tt,(existT _ _stringappend_781_ _)) => - returnm (tt, build_ex _stringappend_781_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_781_ _) => - let _stringappend_782_ := string_drop _stringappend_780_ (build_ex _stringappend_781_) in - (match (reg_name_matches_prefix _stringappend_782_) with - | Some (rs1,(existT _ _stringappend_783_ _)) => - returnm (rs1, build_ex _stringappend_783_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_783_ _) => - let _stringappend_784_ := string_drop _stringappend_782_ (build_ex _stringappend_783_) in - sep_matches_prefix _stringappend_784_ >>= fun w__48 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__48 with - | Some (tt,(existT _ _stringappend_785_ _)) => - returnm (tt, build_ex _stringappend_785_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_785_ _) => - let _stringappend_786_ := string_drop _stringappend_784_ (build_ex _stringappend_785_) in - (match (hex_bits_12_matches_prefix _stringappend_786_) with - | Some (imm,(existT _ _stringappend_787_ _)) => - returnm (imm, build_ex _stringappend_787_) - | _ => exit tt : M ((mword 12 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_787_ _) => - (match (string_drop _stringappend_786_ (build_ex _stringappend_787_)) with - | "" => returnm ((RISCV_JALR (imm, rs1, rd)) : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - match (btype_mnemonic_matches_prefix _stringappend_756_) with - | Some (op,(existT _ _stringappend_789_ _)) => - let _stringappend_790_ := - string_drop _stringappend_756_ (build_ex _stringappend_789_) in - match (spc_matches_prefix _stringappend_790_) with - | Some (tt,(existT _ _stringappend_791_ _)) => - let _stringappend_792_ := - string_drop _stringappend_790_ (build_ex _stringappend_791_) in - match (reg_name_matches_prefix _stringappend_792_) with - | Some (rs1,(existT _ _stringappend_793_ _)) => - let _stringappend_794_ := - string_drop _stringappend_792_ (build_ex _stringappend_793_) in - sep_matches_prefix _stringappend_794_ >>= fun w__55 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__55 with - | Some (tt,(existT _ _stringappend_795_ _)) => - let _stringappend_796_ := - string_drop _stringappend_794_ (build_ex _stringappend_795_) in - match (reg_name_matches_prefix _stringappend_796_) with - | Some (rs2,(existT _ _stringappend_797_ _)) => - let _stringappend_798_ := - string_drop _stringappend_796_ (build_ex _stringappend_797_) in - sep_matches_prefix _stringappend_798_ >>= fun w__56 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__56 with - | Some (tt,(existT _ _stringappend_799_ _)) => - let _stringappend_800_ := - string_drop _stringappend_798_ - (build_ex _stringappend_799_) in - if ((match (hex_bits_13_matches_prefix - _stringappend_800_) with - | Some (imm,(existT _ _stringappend_801_ _)) => - match (string_drop _stringappend_800_ - (build_ex _stringappend_801_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__57 : bool => - returnm ((if (w__57) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__58 : bool => - returnm ((if (w__58) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__59 : bool => - returnm ((if (w__59) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__60 : bool => - returnm ((if (w__60) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__61 : bool => - (if (w__61) then - (match (btype_mnemonic_matches_prefix _stringappend_756_) with - | Some (op,(existT _ _stringappend_789_ _)) => - returnm (op, build_ex _stringappend_789_) - | _ => exit tt : M ((bop * {n : Z & ArithFact (n >= 0)})) - end : M ((bop * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_789_ _) => - let _stringappend_790_ := - string_drop _stringappend_756_ (build_ex _stringappend_789_) in - (match (spc_matches_prefix _stringappend_790_) with - | Some (tt,(existT _ _stringappend_791_ _)) => - returnm (tt, build_ex _stringappend_791_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_791_ _) => - let _stringappend_792_ := - string_drop _stringappend_790_ (build_ex _stringappend_791_) in - (match (reg_name_matches_prefix _stringappend_792_) with - | Some (rs1,(existT _ _stringappend_793_ _)) => - returnm (rs1, build_ex _stringappend_793_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_793_ _) => - let _stringappend_794_ := - string_drop _stringappend_792_ (build_ex _stringappend_793_) in - sep_matches_prefix _stringappend_794_ >>= fun w__68 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__68 with - | Some (tt,(existT _ _stringappend_795_ _)) => - returnm (tt, build_ex _stringappend_795_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_795_ _) => - let _stringappend_796_ := - string_drop _stringappend_794_ (build_ex _stringappend_795_) in - (match (reg_name_matches_prefix _stringappend_796_) with - | Some (rs2,(existT _ _stringappend_797_ _)) => - returnm (rs2, build_ex _stringappend_797_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs2, existT _ _stringappend_797_ _) => - let _stringappend_798_ := - string_drop _stringappend_796_ (build_ex _stringappend_797_) in - sep_matches_prefix _stringappend_798_ >>= fun w__73 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__73 with - | Some (tt,(existT _ _stringappend_799_ _)) => - returnm (tt, build_ex _stringappend_799_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_799_ _) => - let _stringappend_800_ := - string_drop _stringappend_798_ (build_ex _stringappend_799_) in - (match (hex_bits_13_matches_prefix _stringappend_800_) with - | Some (imm,(existT _ _stringappend_801_ _)) => - returnm (imm, build_ex _stringappend_801_) - | _ => exit tt : M ((mword 13 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 13 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_801_ _) => - (match (string_drop _stringappend_800_ (build_ex _stringappend_801_)) with - | "" => returnm ((BTYPE (imm, rs2, rs1, op)) : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - match (itype_mnemonic_matches_prefix _stringappend_756_) with - | Some (op,(existT _ _stringappend_803_ _)) => - let _stringappend_804_ := - string_drop _stringappend_756_ (build_ex _stringappend_803_) in - match (spc_matches_prefix _stringappend_804_) with - | Some (tt,(existT _ _stringappend_805_ _)) => - let _stringappend_806_ := - string_drop _stringappend_804_ (build_ex _stringappend_805_) in - match (reg_name_matches_prefix _stringappend_806_) with - | Some (rd,(existT _ _stringappend_807_ _)) => - let _stringappend_808_ := - string_drop _stringappend_806_ (build_ex _stringappend_807_) in - sep_matches_prefix _stringappend_808_ >>= fun w__80 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__80 with - | Some (tt,(existT _ _stringappend_809_ _)) => - let _stringappend_810_ := - string_drop _stringappend_808_ (build_ex _stringappend_809_) in - match (reg_name_matches_prefix _stringappend_810_) with - | Some (rs1,(existT _ _stringappend_811_ _)) => - let _stringappend_812_ := - string_drop _stringappend_810_ (build_ex _stringappend_811_) in - sep_matches_prefix _stringappend_812_ >>= fun w__81 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__81 with - | Some (tt,(existT _ _stringappend_813_ _)) => - let _stringappend_814_ := - string_drop _stringappend_812_ - (build_ex _stringappend_813_) in - if ((match (hex_bits_12_matches_prefix - _stringappend_814_) with - | Some (imm,(existT _ _stringappend_815_ _)) => - match (string_drop _stringappend_814_ - (build_ex _stringappend_815_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__82 : bool => - returnm ((if (w__82) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__83 : bool => - returnm ((if (w__83) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__84 : bool => - returnm ((if (w__84) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__85 : bool => - returnm ((if (w__85) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__86 : bool => - (if (w__86) then - (match (itype_mnemonic_matches_prefix _stringappend_756_) with - | Some (op,(existT _ _stringappend_803_ _)) => - returnm (op, build_ex _stringappend_803_) - | _ => exit tt : M ((iop * {n : Z & ArithFact (n >= 0)})) - end : M ((iop * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_803_ _) => - let _stringappend_804_ := - string_drop _stringappend_756_ (build_ex _stringappend_803_) in - (match (spc_matches_prefix _stringappend_804_) with - | Some (tt,(existT _ _stringappend_805_ _)) => - returnm (tt, build_ex _stringappend_805_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_805_ _) => - let _stringappend_806_ := - string_drop _stringappend_804_ (build_ex _stringappend_805_) in - (match (reg_name_matches_prefix _stringappend_806_) with - | Some (rd,(existT _ _stringappend_807_ _)) => - returnm (rd, build_ex _stringappend_807_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_807_ _) => - let _stringappend_808_ := - string_drop _stringappend_806_ (build_ex _stringappend_807_) in - sep_matches_prefix _stringappend_808_ >>= fun w__93 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__93 with - | Some (tt,(existT _ _stringappend_809_ _)) => - returnm (tt, build_ex _stringappend_809_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_809_ _) => - let _stringappend_810_ := - string_drop _stringappend_808_ (build_ex _stringappend_809_) in - (match (reg_name_matches_prefix _stringappend_810_) with - | Some (rs1,(existT _ _stringappend_811_ _)) => - returnm (rs1, build_ex _stringappend_811_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_811_ _) => - let _stringappend_812_ := - string_drop _stringappend_810_ (build_ex _stringappend_811_) in - sep_matches_prefix _stringappend_812_ >>= fun w__98 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__98 with - | Some (tt,(existT _ _stringappend_813_ _)) => - returnm (tt, build_ex _stringappend_813_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_813_ _) => - let _stringappend_814_ := - string_drop _stringappend_812_ (build_ex _stringappend_813_) in - (match (hex_bits_12_matches_prefix _stringappend_814_) with - | Some (imm,(existT _ _stringappend_815_ _)) => - returnm (imm, build_ex _stringappend_815_) - | _ => exit tt : M ((mword 12 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_815_ _) => - (match (string_drop _stringappend_814_ (build_ex _stringappend_815_)) with - | "" => returnm ((ITYPE (imm, rs1, rd, op)) : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - match (shiftiop_mnemonic_matches_prefix _stringappend_756_) with - | Some (op,(existT _ _stringappend_817_ _)) => - let _stringappend_818_ := - string_drop _stringappend_756_ (build_ex _stringappend_817_) in - match (spc_matches_prefix _stringappend_818_) with - | Some (tt,(existT _ _stringappend_819_ _)) => - let _stringappend_820_ := - string_drop _stringappend_818_ (build_ex _stringappend_819_) in - match (reg_name_matches_prefix _stringappend_820_) with - | Some (rd,(existT _ _stringappend_821_ _)) => - let _stringappend_822_ := - string_drop _stringappend_820_ (build_ex _stringappend_821_) in - sep_matches_prefix _stringappend_822_ >>= fun w__105 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__105 with - | Some (tt,(existT _ _stringappend_823_ _)) => - let _stringappend_824_ := - string_drop _stringappend_822_ - (build_ex _stringappend_823_) in - if ((match (reg_name_matches_prefix _stringappend_824_) with - | Some (rs1,(existT _ _stringappend_825_ _)) => - let _stringappend_826_ := - string_drop _stringappend_824_ - (build_ex _stringappend_825_) in - if ((match (hex_bits_6_matches_prefix - _stringappend_826_) with - | Some - (shamt,(existT _ _stringappend_827_ _)) => - match (string_drop _stringappend_826_ - (build_ex _stringappend_827_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__106 : bool => - returnm ((if (w__106) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__107 : bool => - returnm ((if (w__107) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__108 : bool => - (if (w__108) then - (match (shiftiop_mnemonic_matches_prefix _stringappend_756_) with - | Some (op,(existT _ _stringappend_817_ _)) => - returnm (op, build_ex _stringappend_817_) - | _ => exit tt : M ((sop * {n : Z & ArithFact (n >= 0)})) - end : M ((sop * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_817_ _) => - let _stringappend_818_ := - string_drop _stringappend_756_ (build_ex _stringappend_817_) in - (match (spc_matches_prefix _stringappend_818_) with - | Some (tt,(existT _ _stringappend_819_ _)) => - returnm (tt, build_ex _stringappend_819_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_819_ _) => - let _stringappend_820_ := - string_drop _stringappend_818_ (build_ex _stringappend_819_) in - (match (reg_name_matches_prefix _stringappend_820_) with - | Some (rd,(existT _ _stringappend_821_ _)) => - returnm (rd, build_ex _stringappend_821_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_821_ _) => - let _stringappend_822_ := - string_drop _stringappend_820_ (build_ex _stringappend_821_) in - sep_matches_prefix _stringappend_822_ >>= fun w__115 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__115 with - | Some (tt,(existT _ _stringappend_823_ _)) => - returnm (tt, build_ex _stringappend_823_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_823_ _) => - let _stringappend_824_ := - string_drop _stringappend_822_ (build_ex _stringappend_823_) in - (match (reg_name_matches_prefix _stringappend_824_) with - | Some (rs1,(existT _ _stringappend_825_ _)) => - returnm (rs1, build_ex _stringappend_825_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_825_ _) => - let _stringappend_826_ := - string_drop _stringappend_824_ (build_ex _stringappend_825_) in - (match (hex_bits_6_matches_prefix _stringappend_826_) with - | Some (shamt,(existT _ _stringappend_827_ _)) => - returnm (shamt, build_ex _stringappend_827_) - | _ => exit tt : M ((mword 6 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 6 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(shamt, existT _ _stringappend_827_ _) => - (match (string_drop _stringappend_826_ (build_ex _stringappend_827_)) with - | "" => returnm ((SHIFTIOP (shamt, rs1, rd, op)) : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - match (rtype_mnemonic_matches_prefix _stringappend_756_) with - | Some (op,(existT _ _stringappend_829_ _)) => - let _stringappend_830_ := - string_drop _stringappend_756_ (build_ex _stringappend_829_) in - match (spc_matches_prefix _stringappend_830_) with - | Some (tt,(existT _ _stringappend_831_ _)) => - let _stringappend_832_ := - string_drop _stringappend_830_ (build_ex _stringappend_831_) in - match (reg_name_matches_prefix _stringappend_832_) with - | Some (rd,(existT _ _stringappend_833_ _)) => - let _stringappend_834_ := - string_drop _stringappend_832_ (build_ex _stringappend_833_) in - sep_matches_prefix _stringappend_834_ >>= fun w__124 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__124 with - | Some (tt,(existT _ _stringappend_835_ _)) => - let _stringappend_836_ := - string_drop _stringappend_834_ (build_ex _stringappend_835_) in - match (reg_name_matches_prefix _stringappend_836_) with - | Some (rs1,(existT _ _stringappend_837_ _)) => - let _stringappend_838_ := - string_drop _stringappend_836_ (build_ex _stringappend_837_) in - sep_matches_prefix _stringappend_838_ >>= fun w__125 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__125 with - | Some (tt,(existT _ _stringappend_839_ _)) => - let _stringappend_840_ := - string_drop _stringappend_838_ - (build_ex _stringappend_839_) in - if ((match (reg_name_matches_prefix - _stringappend_840_) with - | Some - (rs2,(existT _ _stringappend_841_ _)) => - match (string_drop _stringappend_840_ - (build_ex _stringappend_841_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__126 : bool => - returnm ((if (w__126) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__127 : bool => - returnm ((if (w__127) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__128 : bool => - returnm ((if (w__128) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__129 : bool => - returnm ((if (w__129) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__130 : bool => - (if (w__130) then - (match (rtype_mnemonic_matches_prefix _stringappend_756_) with - | Some (op,(existT _ _stringappend_829_ _)) => - returnm (op, build_ex _stringappend_829_) - | _ => exit tt : M ((rop * {n : Z & ArithFact (n >= 0)})) - end : M ((rop * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_829_ _) => - let _stringappend_830_ := - string_drop _stringappend_756_ (build_ex _stringappend_829_) in - (match (spc_matches_prefix _stringappend_830_) with - | Some (tt,(existT _ _stringappend_831_ _)) => - returnm (tt, build_ex _stringappend_831_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_831_ _) => - let _stringappend_832_ := - string_drop _stringappend_830_ (build_ex _stringappend_831_) in - (match (reg_name_matches_prefix _stringappend_832_) with - | Some (rd,(existT _ _stringappend_833_ _)) => - returnm (rd, build_ex _stringappend_833_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_833_ _) => - let _stringappend_834_ := - string_drop _stringappend_832_ (build_ex _stringappend_833_) in - sep_matches_prefix _stringappend_834_ >>= fun w__137 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__137 with - | Some (tt,(existT _ _stringappend_835_ _)) => - returnm (tt, build_ex _stringappend_835_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_835_ _) => - let _stringappend_836_ := - string_drop _stringappend_834_ (build_ex _stringappend_835_) in - (match (reg_name_matches_prefix _stringappend_836_) with - | Some (rs1,(existT _ _stringappend_837_ _)) => - returnm (rs1, build_ex _stringappend_837_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_837_ _) => - let _stringappend_838_ := - string_drop _stringappend_836_ (build_ex _stringappend_837_) in - sep_matches_prefix _stringappend_838_ >>= fun w__142 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__142 with - | Some (tt,(existT _ _stringappend_839_ _)) => - returnm (tt, build_ex _stringappend_839_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_839_ _) => - let _stringappend_840_ := - string_drop _stringappend_838_ (build_ex _stringappend_839_) in - (match (reg_name_matches_prefix _stringappend_840_) with - | Some (rs2,(existT _ _stringappend_841_ _)) => - returnm (rs2, build_ex _stringappend_841_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs2, existT _ _stringappend_841_ _) => - (match (string_drop _stringappend_840_ (build_ex _stringappend_841_)) with - | "" => returnm ((RTYPE (rs2, rs1, rd, op)) : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - and_boolM (returnm ((string_startswith _stringappend_756_ "l") : bool)) - (let _stringappend_843_ := - string_drop _stringappend_756_ (build_ex (projT1 (string_length "l"))) in - match (size_mnemonic_matches_prefix _stringappend_843_) with - | Some (size,(existT _ _stringappend_844_ _)) => - let _stringappend_845_ := - string_drop _stringappend_843_ (build_ex _stringappend_844_) in - match (maybe_u_matches_prefix _stringappend_845_) with - | Some (is_unsigned,(existT _ _stringappend_846_ _)) => - let _stringappend_847_ := - string_drop _stringappend_845_ (build_ex _stringappend_846_) in - match (maybe_aq_matches_prefix _stringappend_847_) with - | Some (aq,(existT _ _stringappend_848_ _)) => - let _stringappend_849_ := - string_drop _stringappend_847_ (build_ex _stringappend_848_) in - match (maybe_rl_matches_prefix _stringappend_849_) with - | Some (rl,(existT _ _stringappend_850_ _)) => - let _stringappend_851_ := - string_drop _stringappend_849_ (build_ex _stringappend_850_) in - match (spc_matches_prefix _stringappend_851_) with - | Some (tt,(existT _ _stringappend_852_ _)) => - let _stringappend_853_ := - string_drop _stringappend_851_ - (build_ex _stringappend_852_) in - match (reg_name_matches_prefix _stringappend_853_) with - | Some (rd,(existT _ _stringappend_854_ _)) => - let _stringappend_855_ := - string_drop _stringappend_853_ - (build_ex _stringappend_854_) in - sep_matches_prefix _stringappend_855_ >>= fun w__149 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__149 with - | Some (tt,(existT _ _stringappend_856_ _)) => - let _stringappend_857_ := - string_drop _stringappend_855_ - (build_ex _stringappend_856_) in - match (reg_name_matches_prefix _stringappend_857_) with - | Some (rs1,(existT _ _stringappend_858_ _)) => - let _stringappend_859_ := - string_drop _stringappend_857_ - (build_ex _stringappend_858_) in - sep_matches_prefix _stringappend_859_ >>= fun w__150 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__150 with - | Some - (tt,(existT _ _stringappend_860_ _)) => - let _stringappend_861_ := - string_drop _stringappend_859_ - (build_ex _stringappend_860_) in - if ((match (hex_bits_12_matches_prefix - _stringappend_861_) with - | Some - (imm,(existT _ _stringappend_862_ _)) => - match (string_drop - _stringappend_861_ - (build_ex _stringappend_862_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__151 : bool => - returnm ((if (w__151) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__152 : bool => - returnm ((if (w__152) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__153 : bool => - returnm ((if (w__153) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__154 : bool => - returnm ((if (w__154) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__155 : bool => - returnm ((if (w__155) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__156 : bool => - returnm ((if (w__156) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__157 : bool => - returnm ((if (w__157) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__158 : bool => - returnm ((if (w__158) then true - else false) - : bool)) >>= fun w__159 : bool => - (if (w__159) then - let _stringappend_843_ := - string_drop _stringappend_756_ (build_ex (projT1 (string_length "l"))) in - (match (size_mnemonic_matches_prefix _stringappend_843_) with - | Some (size,(existT _ _stringappend_844_ _)) => - returnm (size, build_ex _stringappend_844_) - | _ => exit tt : M ((word_width * {n : Z & ArithFact (n >= 0)})) - end : M ((word_width * {n : Z & ArithFact (n >= 0)}))) >>= fun '(size, existT _ _stringappend_844_ _) => - let _stringappend_845_ := - string_drop _stringappend_843_ (build_ex _stringappend_844_) in - (match (maybe_u_matches_prefix _stringappend_845_) with - | Some (is_unsigned,(existT _ _stringappend_846_ _)) => - returnm (is_unsigned, build_ex _stringappend_846_) - | _ => exit tt : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(is_unsigned, existT _ _stringappend_846_ _) => - let _stringappend_847_ := - string_drop _stringappend_845_ (build_ex _stringappend_846_) in - (match (maybe_aq_matches_prefix _stringappend_847_) with - | Some (aq,(existT _ _stringappend_848_ _)) => - returnm (aq, build_ex _stringappend_848_) - | _ => exit tt : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(aq, existT _ _stringappend_848_ _) => - let _stringappend_849_ := - string_drop _stringappend_847_ (build_ex _stringappend_848_) in - (match (maybe_rl_matches_prefix _stringappend_849_) with - | Some (rl,(existT _ _stringappend_850_ _)) => - returnm (rl, build_ex _stringappend_850_) - | _ => exit tt : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rl, existT _ _stringappend_850_ _) => - let _stringappend_851_ := - string_drop _stringappend_849_ (build_ex _stringappend_850_) in - (match (spc_matches_prefix _stringappend_851_) with - | Some (tt,(existT _ _stringappend_852_ _)) => - returnm (tt, build_ex _stringappend_852_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_852_ _) => - let _stringappend_853_ := - string_drop _stringappend_851_ (build_ex _stringappend_852_) in - (match (reg_name_matches_prefix _stringappend_853_) with - | Some (rd,(existT _ _stringappend_854_ _)) => - returnm (rd, build_ex _stringappend_854_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_854_ _) => - let _stringappend_855_ := - string_drop _stringappend_853_ (build_ex _stringappend_854_) in - sep_matches_prefix _stringappend_855_ >>= fun w__172 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__172 with - | Some (tt,(existT _ _stringappend_856_ _)) => - returnm (tt, build_ex _stringappend_856_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_856_ _) => - let _stringappend_857_ := - string_drop _stringappend_855_ (build_ex _stringappend_856_) in - (match (reg_name_matches_prefix _stringappend_857_) with - | Some (rs1,(existT _ _stringappend_858_ _)) => - returnm (rs1, build_ex _stringappend_858_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_858_ _) => - let _stringappend_859_ := - string_drop _stringappend_857_ (build_ex _stringappend_858_) in - sep_matches_prefix _stringappend_859_ >>= fun w__177 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__177 with - | Some (tt,(existT _ _stringappend_860_ _)) => - returnm (tt, build_ex _stringappend_860_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_860_ _) => - let _stringappend_861_ := - string_drop _stringappend_859_ (build_ex _stringappend_860_) in - (match (hex_bits_12_matches_prefix _stringappend_861_) with - | Some (imm,(existT _ _stringappend_862_ _)) => - returnm (imm, build_ex _stringappend_862_) - | _ => exit tt : M ((mword 12 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_862_ _) => - (match (string_drop _stringappend_861_ (build_ex _stringappend_862_)) with - | "" => - returnm ((LOAD (imm, rs1, rd, is_unsigned, size, aq, rl)) : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - and_boolM (returnm ((string_startswith _stringappend_756_ "s") : bool)) - (let _stringappend_864_ := - string_drop _stringappend_756_ - (build_ex (projT1 (string_length "s"))) in - match (size_mnemonic_matches_prefix _stringappend_864_) with - | Some (size,(existT _ _stringappend_865_ _)) => - let _stringappend_866_ := - string_drop _stringappend_864_ (build_ex _stringappend_865_) in - match (maybe_aq_matches_prefix _stringappend_866_) with - | Some (aq,(existT _ _stringappend_867_ _)) => - let _stringappend_868_ := - string_drop _stringappend_866_ (build_ex _stringappend_867_) in - match (maybe_rl_matches_prefix _stringappend_868_) with - | Some (rl,(existT _ _stringappend_869_ _)) => - let _stringappend_870_ := - string_drop _stringappend_868_ (build_ex _stringappend_869_) in - match (spc_matches_prefix _stringappend_870_) with - | Some (tt,(existT _ _stringappend_871_ _)) => - let _stringappend_872_ := - string_drop _stringappend_870_ - (build_ex _stringappend_871_) in - match (reg_name_matches_prefix _stringappend_872_) with - | Some (rd,(existT _ _stringappend_873_ _)) => - let _stringappend_874_ := - string_drop _stringappend_872_ - (build_ex _stringappend_873_) in - sep_matches_prefix _stringappend_874_ >>= fun w__184 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__184 with - | Some (tt,(existT _ _stringappend_875_ _)) => - let _stringappend_876_ := - string_drop _stringappend_874_ - (build_ex _stringappend_875_) in - match (reg_name_matches_prefix _stringappend_876_) with - | Some (rs1,(existT _ _stringappend_877_ _)) => - let _stringappend_878_ := - string_drop _stringappend_876_ - (build_ex _stringappend_877_) in - sep_matches_prefix _stringappend_878_ >>= fun w__185 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__185 with - | Some - (tt,(existT _ _stringappend_879_ _)) => - let _stringappend_880_ := - string_drop _stringappend_878_ - (build_ex _stringappend_879_) in - if ((match (hex_bits_12_matches_prefix - _stringappend_880_) with - | Some - (imm,(existT _ _stringappend_881_ _)) => - match (string_drop - _stringappend_880_ - (build_ex _stringappend_881_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__186 : bool => - returnm ((if (w__186) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__187 : bool => - returnm ((if (w__187) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__188 : bool => - returnm ((if (w__188) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__189 : bool => - returnm ((if (w__189) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__190 : bool => - returnm ((if (w__190) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__191 : bool => - returnm ((if (w__191) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__192 : bool => - returnm ((if (w__192) then true - else false) - : bool)) >>= fun w__193 : bool => - (if (w__193) then - let _stringappend_864_ := - string_drop _stringappend_756_ - (build_ex (projT1 (string_length "s"))) in - (match (size_mnemonic_matches_prefix _stringappend_864_) with - | Some (size,(existT _ _stringappend_865_ _)) => - returnm (size, build_ex _stringappend_865_) - | _ => exit tt : M ((word_width * {n : Z & ArithFact (n >= 0)})) - end : M ((word_width * {n : Z & ArithFact (n >= 0)}))) >>= fun '(size, existT _ _stringappend_865_ _) => - let _stringappend_866_ := - string_drop _stringappend_864_ (build_ex _stringappend_865_) in - (match (maybe_aq_matches_prefix _stringappend_866_) with - | Some (aq,(existT _ _stringappend_867_ _)) => - returnm (aq, build_ex _stringappend_867_) - | _ => exit tt : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(aq, existT _ _stringappend_867_ _) => - let _stringappend_868_ := - string_drop _stringappend_866_ (build_ex _stringappend_867_) in - (match (maybe_rl_matches_prefix _stringappend_868_) with - | Some (rl,(existT _ _stringappend_869_ _)) => - returnm (rl, build_ex _stringappend_869_) - | _ => exit tt : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rl, existT _ _stringappend_869_ _) => - let _stringappend_870_ := - string_drop _stringappend_868_ (build_ex _stringappend_869_) in - (match (spc_matches_prefix _stringappend_870_) with - | Some (tt,(existT _ _stringappend_871_ _)) => - returnm (tt, build_ex _stringappend_871_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_871_ _) => - let _stringappend_872_ := - string_drop _stringappend_870_ (build_ex _stringappend_871_) in - (match (reg_name_matches_prefix _stringappend_872_) with - | Some (rd,(existT _ _stringappend_873_ _)) => - returnm (rd, build_ex _stringappend_873_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_873_ _) => - let _stringappend_874_ := - string_drop _stringappend_872_ (build_ex _stringappend_873_) in - sep_matches_prefix _stringappend_874_ >>= fun w__204 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__204 with - | Some (tt,(existT _ _stringappend_875_ _)) => - returnm (tt, build_ex _stringappend_875_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_875_ _) => - let _stringappend_876_ := - string_drop _stringappend_874_ (build_ex _stringappend_875_) in - (match (reg_name_matches_prefix _stringappend_876_) with - | Some (rs1,(existT _ _stringappend_877_ _)) => - returnm (rs1, build_ex _stringappend_877_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_877_ _) => - let _stringappend_878_ := - string_drop _stringappend_876_ (build_ex _stringappend_877_) in - sep_matches_prefix _stringappend_878_ >>= fun w__209 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__209 with - | Some (tt,(existT _ _stringappend_879_ _)) => - returnm (tt, build_ex _stringappend_879_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_879_ _) => - let _stringappend_880_ := - string_drop _stringappend_878_ (build_ex _stringappend_879_) in - (match (hex_bits_12_matches_prefix _stringappend_880_) with - | Some (imm,(existT _ _stringappend_881_ _)) => - returnm (imm, build_ex _stringappend_881_) - | _ => exit tt : M ((mword 12 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_881_ _) => - (match (string_drop _stringappend_880_ (build_ex _stringappend_881_)) with - | "" => returnm ((STORE (imm, rs1, rd, size, aq, rl)) : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - and_boolM - (returnm ((string_startswith _stringappend_756_ "addiw") - : bool)) - (let _stringappend_883_ := - string_drop _stringappend_756_ - (build_ex (projT1 (string_length "addiw"))) in - match (spc_matches_prefix _stringappend_883_) with - | Some (tt,(existT _ _stringappend_884_ _)) => - let _stringappend_885_ := - string_drop _stringappend_883_ (build_ex _stringappend_884_) in - match (reg_name_matches_prefix _stringappend_885_) with - | Some (rd,(existT _ _stringappend_886_ _)) => - let _stringappend_887_ := - string_drop _stringappend_885_ (build_ex _stringappend_886_) in - sep_matches_prefix _stringappend_887_ >>= fun w__216 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__216 with - | Some (tt,(existT _ _stringappend_888_ _)) => - let _stringappend_889_ := - string_drop _stringappend_887_ - (build_ex _stringappend_888_) in - match (reg_name_matches_prefix _stringappend_889_) with - | Some (rs1,(existT _ _stringappend_890_ _)) => - let _stringappend_891_ := - string_drop _stringappend_889_ - (build_ex _stringappend_890_) in - sep_matches_prefix _stringappend_891_ >>= fun w__217 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__217 with - | Some - (tt,(existT _ _stringappend_892_ _)) => - let _stringappend_893_ := - string_drop _stringappend_891_ - (build_ex _stringappend_892_) in - if ((match (hex_bits_12_matches_prefix - _stringappend_893_) with - | Some - (imm,(existT _ _stringappend_894_ _)) => - match (string_drop - _stringappend_893_ - (build_ex _stringappend_894_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__218 : bool => - returnm ((if (w__218) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__219 : bool => - returnm ((if (w__219) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__220 : bool => - returnm ((if (w__220) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__221 : bool => - returnm ((if (w__221) then true - else false) - : bool)) >>= fun w__222 : bool => - (if (w__222) then - let _stringappend_883_ := - string_drop _stringappend_756_ - (build_ex (projT1 (string_length "addiw"))) in - (match (spc_matches_prefix _stringappend_883_) with - | Some (tt,(existT _ _stringappend_884_ _)) => - returnm (tt, build_ex _stringappend_884_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_884_ _) => - let _stringappend_885_ := - string_drop _stringappend_883_ (build_ex _stringappend_884_) in - (match (reg_name_matches_prefix _stringappend_885_) with - | Some (rd,(existT _ _stringappend_886_ _)) => - returnm (rd, build_ex _stringappend_886_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_886_ _) => - let _stringappend_887_ := - string_drop _stringappend_885_ (build_ex _stringappend_886_) in - sep_matches_prefix _stringappend_887_ >>= fun w__227 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__227 with - | Some (tt,(existT _ _stringappend_888_ _)) => - returnm (tt, build_ex _stringappend_888_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_888_ _) => - let _stringappend_889_ := - string_drop _stringappend_887_ (build_ex _stringappend_888_) in - (match (reg_name_matches_prefix _stringappend_889_) with - | Some (rs1,(existT _ _stringappend_890_ _)) => - returnm (rs1, build_ex _stringappend_890_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_890_ _) => - let _stringappend_891_ := - string_drop _stringappend_889_ (build_ex _stringappend_890_) in - sep_matches_prefix _stringappend_891_ >>= fun w__232 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__232 with - | Some (tt,(existT _ _stringappend_892_ _)) => - returnm (tt, build_ex _stringappend_892_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_892_ _) => - let _stringappend_893_ := - string_drop _stringappend_891_ (build_ex _stringappend_892_) in - (match (hex_bits_12_matches_prefix _stringappend_893_) with - | Some (imm,(existT _ _stringappend_894_ _)) => - returnm (imm, build_ex _stringappend_894_) - | _ => exit tt : M ((mword 12 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_894_ _) => - (match (string_drop _stringappend_893_ - (build_ex _stringappend_894_)) with - | "" => returnm ((ADDIW (imm, rs1, rd)) : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - match (shiftw_mnemonic_matches_prefix _stringappend_756_) with - | Some (op,(existT _ _stringappend_896_ _)) => - let _stringappend_897_ := - string_drop _stringappend_756_ (build_ex _stringappend_896_) in - match (spc_matches_prefix _stringappend_897_) with - | Some (tt,(existT _ _stringappend_898_ _)) => - let _stringappend_899_ := - string_drop _stringappend_897_ - (build_ex _stringappend_898_) in - match (reg_name_matches_prefix _stringappend_899_) with - | Some (rd,(existT _ _stringappend_900_ _)) => - let _stringappend_901_ := - string_drop _stringappend_899_ - (build_ex _stringappend_900_) in - sep_matches_prefix _stringappend_901_ >>= fun w__239 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__239 with - | Some (tt,(existT _ _stringappend_902_ _)) => - let _stringappend_903_ := - string_drop _stringappend_901_ - (build_ex _stringappend_902_) in - match (reg_name_matches_prefix _stringappend_903_) with - | Some (rs1,(existT _ _stringappend_904_ _)) => - let _stringappend_905_ := - string_drop _stringappend_903_ - (build_ex _stringappend_904_) in - sep_matches_prefix _stringappend_905_ >>= fun w__240 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__240 with - | Some - (tt,(existT _ _stringappend_906_ _)) => - let _stringappend_907_ := - string_drop _stringappend_905_ - (build_ex _stringappend_906_) in - if ((match (hex_bits_5_matches_prefix - _stringappend_907_) with - | Some - (shamt,(existT _ _stringappend_908_ _)) => - match (string_drop - _stringappend_907_ - (build_ex _stringappend_908_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__241 : bool => - returnm ((if (w__241) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__242 : bool => - returnm ((if (w__242) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__243 : bool => - returnm ((if (w__243) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__244 : bool => - returnm ((if (w__244) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__245 : bool => - (if (w__245) then - (match (shiftw_mnemonic_matches_prefix _stringappend_756_) with - | Some (op,(existT _ _stringappend_896_ _)) => - returnm (op, build_ex _stringappend_896_) - | _ => exit tt : M ((sop * {n : Z & ArithFact (n >= 0)})) - end : M ((sop * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_896_ _) => - let _stringappend_897_ := - string_drop _stringappend_756_ (build_ex _stringappend_896_) in - (match (spc_matches_prefix _stringappend_897_) with - | Some (tt,(existT _ _stringappend_898_ _)) => - returnm (tt, build_ex _stringappend_898_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_898_ _) => - let _stringappend_899_ := - string_drop _stringappend_897_ (build_ex _stringappend_898_) in - (match (reg_name_matches_prefix _stringappend_899_) with - | Some (rd,(existT _ _stringappend_900_ _)) => - returnm (rd, build_ex _stringappend_900_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_900_ _) => - let _stringappend_901_ := - string_drop _stringappend_899_ (build_ex _stringappend_900_) in - sep_matches_prefix _stringappend_901_ >>= fun w__252 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__252 with - | Some (tt,(existT _ _stringappend_902_ _)) => - returnm (tt, build_ex _stringappend_902_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_902_ _) => - let _stringappend_903_ := - string_drop _stringappend_901_ (build_ex _stringappend_902_) in - (match (reg_name_matches_prefix _stringappend_903_) with - | Some (rs1,(existT _ _stringappend_904_ _)) => - returnm (rs1, build_ex _stringappend_904_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_904_ _) => - let _stringappend_905_ := - string_drop _stringappend_903_ (build_ex _stringappend_904_) in - sep_matches_prefix _stringappend_905_ >>= fun w__257 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__257 with - | Some (tt,(existT _ _stringappend_906_ _)) => - returnm (tt, build_ex _stringappend_906_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_906_ _) => - let _stringappend_907_ := - string_drop _stringappend_905_ (build_ex _stringappend_906_) in - (match (hex_bits_5_matches_prefix _stringappend_907_) with - | Some (shamt,(existT _ _stringappend_908_ _)) => - returnm (shamt, build_ex _stringappend_908_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(shamt, existT _ _stringappend_908_ _) => - (match (string_drop _stringappend_907_ - (build_ex _stringappend_908_)) with - | "" => returnm ((SHIFTW (shamt, rs1, rd, op)) : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - match (rtypew_mnemonic_matches_prefix _stringappend_756_) with - | Some (op,(existT _ _stringappend_910_ _)) => - let _stringappend_911_ := - string_drop _stringappend_756_ - (build_ex _stringappend_910_) in - match (spc_matches_prefix _stringappend_911_) with - | Some (tt,(existT _ _stringappend_912_ _)) => - let _stringappend_913_ := - string_drop _stringappend_911_ - (build_ex _stringappend_912_) in - match (reg_name_matches_prefix _stringappend_913_) with - | Some (rd,(existT _ _stringappend_914_ _)) => - let _stringappend_915_ := - string_drop _stringappend_913_ - (build_ex _stringappend_914_) in - sep_matches_prefix _stringappend_915_ >>= fun w__264 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__264 with - | Some (tt,(existT _ _stringappend_916_ _)) => - let _stringappend_917_ := - string_drop _stringappend_915_ - (build_ex _stringappend_916_) in - match (reg_name_matches_prefix _stringappend_917_) with - | Some (rs1,(existT _ _stringappend_918_ _)) => - let _stringappend_919_ := - string_drop _stringappend_917_ - (build_ex _stringappend_918_) in - sep_matches_prefix _stringappend_919_ >>= fun w__265 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__265 with - | Some - (tt,(existT _ _stringappend_920_ _)) => - let _stringappend_921_ := - string_drop - _stringappend_919_ - (build_ex _stringappend_920_) in - if ((match (reg_name_matches_prefix - _stringappend_921_) with - | Some - (rs2,(existT _ _stringappend_922_ _)) => - match (string_drop - _stringappend_921_ - (build_ex _stringappend_922_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__266 : bool => - returnm ((if (w__266) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__267 : bool => - returnm ((if (w__267) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__268 : bool => - returnm ((if (w__268) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__269 : bool => - returnm ((if (w__269) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__270 : bool => - (if (w__270) then - (match (rtypew_mnemonic_matches_prefix _stringappend_756_) with - | Some (op,(existT _ _stringappend_910_ _)) => - returnm (op, build_ex _stringappend_910_) - | _ => exit tt : M ((ropw * {n : Z & ArithFact (n >= 0)})) - end : M ((ropw * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_910_ _) => - let _stringappend_911_ := - string_drop _stringappend_756_ - (build_ex _stringappend_910_) in - (match (spc_matches_prefix _stringappend_911_) with - | Some (tt,(existT _ _stringappend_912_ _)) => - returnm (tt, build_ex _stringappend_912_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_912_ _) => - let _stringappend_913_ := - string_drop _stringappend_911_ - (build_ex _stringappend_912_) in - (match (reg_name_matches_prefix _stringappend_913_) with - | Some (rd,(existT _ _stringappend_914_ _)) => - returnm (rd, build_ex _stringappend_914_) - | _ => - exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_914_ _) => - let _stringappend_915_ := - string_drop _stringappend_913_ - (build_ex _stringappend_914_) in - sep_matches_prefix _stringappend_915_ >>= fun w__277 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__277 with - | Some (tt,(existT _ _stringappend_916_ _)) => - returnm (tt, build_ex _stringappend_916_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_916_ _) => - let _stringappend_917_ := - string_drop _stringappend_915_ - (build_ex _stringappend_916_) in - (match (reg_name_matches_prefix _stringappend_917_) with - | Some (rs1,(existT _ _stringappend_918_ _)) => - returnm (rs1, build_ex _stringappend_918_) - | _ => - exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_918_ _) => - let _stringappend_919_ := - string_drop _stringappend_917_ - (build_ex _stringappend_918_) in - sep_matches_prefix _stringappend_919_ >>= fun w__282 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__282 with - | Some (tt,(existT _ _stringappend_920_ _)) => - returnm (tt, build_ex _stringappend_920_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_920_ _) => - let _stringappend_921_ := - string_drop _stringappend_919_ - (build_ex _stringappend_920_) in - (match (reg_name_matches_prefix _stringappend_921_) with - | Some (rs2,(existT _ _stringappend_922_ _)) => - returnm (rs2, build_ex _stringappend_922_) - | _ => - exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs2, existT _ _stringappend_922_ _) => - (match (string_drop _stringappend_921_ - (build_ex _stringappend_922_)) with - | "" => returnm ((RTYPEW (rs2, rs1, rd, op)) : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - match (shiftiwop_mnemonic_matches_prefix _stringappend_756_) with - | Some (op,(existT _ _stringappend_924_ _)) => - let _stringappend_925_ := - string_drop _stringappend_756_ - (build_ex _stringappend_924_) in - match (spc_matches_prefix _stringappend_925_) with - | Some (tt,(existT _ _stringappend_926_ _)) => - let _stringappend_927_ := - string_drop _stringappend_925_ - (build_ex _stringappend_926_) in - match (reg_name_matches_prefix _stringappend_927_) with - | Some (rd,(existT _ _stringappend_928_ _)) => - let _stringappend_929_ := - string_drop _stringappend_927_ - (build_ex _stringappend_928_) in - sep_matches_prefix _stringappend_929_ >>= fun w__289 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__289 with - | Some - (tt,(existT _ _stringappend_930_ _)) => - let _stringappend_931_ := - string_drop _stringappend_929_ - (build_ex _stringappend_930_) in - if ((match (reg_name_matches_prefix - _stringappend_931_) with - | Some - (rs1,(existT _ _stringappend_932_ _)) => - let _stringappend_933_ := - string_drop - _stringappend_931_ - (build_ex _stringappend_932_) in - if ((match (hex_bits_5_matches_prefix - _stringappend_933_) with - | Some - (shamt,(existT _ _stringappend_934_ _)) => - match (string_drop - _stringappend_933_ - (build_ex _stringappend_934_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__290 : bool => - returnm ((if (w__290) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__291 : bool => - returnm ((if (w__291) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__292 : bool => - (if (w__292) then - (match (shiftiwop_mnemonic_matches_prefix - _stringappend_756_) with - | Some (op,(existT _ _stringappend_924_ _)) => - returnm (op, build_ex _stringappend_924_) - | _ => - exit tt : M ((sopw * {n : Z & ArithFact (n >= 0)})) - end : M ((sopw * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_924_ _) => - let _stringappend_925_ := - string_drop _stringappend_756_ - (build_ex _stringappend_924_) in - (match (spc_matches_prefix _stringappend_925_) with - | Some (tt,(existT _ _stringappend_926_ _)) => - returnm (tt, build_ex _stringappend_926_) - | _ => - exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_926_ _) => - let _stringappend_927_ := - string_drop _stringappend_925_ - (build_ex _stringappend_926_) in - (match (reg_name_matches_prefix _stringappend_927_) with - | Some (rd,(existT _ _stringappend_928_ _)) => - returnm (rd, build_ex _stringappend_928_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_928_ _) => - let _stringappend_929_ := - string_drop _stringappend_927_ - (build_ex _stringappend_928_) in - sep_matches_prefix _stringappend_929_ >>= fun w__299 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__299 with - | Some (tt,(existT _ _stringappend_930_ _)) => - returnm (tt, build_ex _stringappend_930_) - | _ => - exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_930_ _) => - let _stringappend_931_ := - string_drop _stringappend_929_ - (build_ex _stringappend_930_) in - (match (reg_name_matches_prefix _stringappend_931_) with - | Some (rs1,(existT _ _stringappend_932_ _)) => - returnm (rs1, build_ex _stringappend_932_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_932_ _) => - let _stringappend_933_ := - string_drop _stringappend_931_ - (build_ex _stringappend_932_) in - (match (hex_bits_5_matches_prefix _stringappend_933_) with - | Some (shamt,(existT _ _stringappend_934_ _)) => - returnm (shamt, build_ex _stringappend_934_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(shamt, existT _ _stringappend_934_ _) => - (match (string_drop _stringappend_933_ - (build_ex _stringappend_934_)) with - | "" => - returnm ((SHIFTIWOP (shamt, rs1, rd, op)) : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - match (mul_mnemonic_matches_prefix _stringappend_756_) with - | Some - ((high, signed1, signed2),(existT _ _stringappend_936_ _)) => - let _stringappend_937_ := - string_drop _stringappend_756_ - (build_ex _stringappend_936_) in - match (spc_matches_prefix _stringappend_937_) with - | Some (tt,(existT _ _stringappend_938_ _)) => - let _stringappend_939_ := - string_drop _stringappend_937_ - (build_ex _stringappend_938_) in - match (reg_name_matches_prefix _stringappend_939_) with - | Some (rd,(existT _ _stringappend_940_ _)) => - let _stringappend_941_ := - string_drop _stringappend_939_ - (build_ex _stringappend_940_) in - sep_matches_prefix _stringappend_941_ >>= fun w__308 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__308 with - | Some (tt,(existT _ _stringappend_942_ _)) => - let _stringappend_943_ := - string_drop _stringappend_941_ - (build_ex _stringappend_942_) in - match (reg_name_matches_prefix - _stringappend_943_) with - | Some (rs1,(existT _ _stringappend_944_ _)) => - let _stringappend_945_ := - string_drop _stringappend_943_ - (build_ex _stringappend_944_) in - sep_matches_prefix _stringappend_945_ >>= fun w__309 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__309 with - | Some - (tt,(existT _ _stringappend_946_ _)) => - let _stringappend_947_ := - string_drop - _stringappend_945_ - (build_ex _stringappend_946_) in - if ((match (reg_name_matches_prefix - _stringappend_947_) with - | Some - (rs2,(existT _ _stringappend_948_ _)) => - match (string_drop - _stringappend_947_ - (build_ex _stringappend_948_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__310 : bool => - returnm ((if (w__310) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__311 : bool => - returnm ((if (w__311) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__312 : bool => - returnm ((if (w__312) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__313 : bool => - returnm ((if (w__313) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__314 : bool => - (if (w__314) then - (match (mul_mnemonic_matches_prefix _stringappend_756_) with - | Some - ((high, signed1, signed2),(existT _ _stringappend_936_ _)) => - returnm ((high, signed1, signed2), build_ex _stringappend_936_) - | _ => - exit tt - : M (((bool * bool * bool) * {n : Z & ArithFact (n >= - 0)})) - end : M (((bool * bool * bool) * {n : Z & ArithFact (n >= - 0)}))) >>= fun '((high, signed1, signed2), existT _ _stringappend_936_ _) => - let _stringappend_937_ := - string_drop _stringappend_756_ - (build_ex _stringappend_936_) in - (match (spc_matches_prefix _stringappend_937_) with - | Some (tt,(existT _ _stringappend_938_ _)) => - returnm (tt, build_ex _stringappend_938_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_938_ _) => - let _stringappend_939_ := - string_drop _stringappend_937_ - (build_ex _stringappend_938_) in - (match (reg_name_matches_prefix _stringappend_939_) with - | Some (rd,(existT _ _stringappend_940_ _)) => - returnm (rd, build_ex _stringappend_940_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_940_ _) => - let _stringappend_941_ := - string_drop _stringappend_939_ - (build_ex _stringappend_940_) in - sep_matches_prefix _stringappend_941_ >>= fun w__321 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__321 with - | Some (tt,(existT _ _stringappend_942_ _)) => - returnm (tt, build_ex _stringappend_942_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_942_ _) => - let _stringappend_943_ := - string_drop _stringappend_941_ - (build_ex _stringappend_942_) in - (match (reg_name_matches_prefix _stringappend_943_) with - | Some (rs1,(existT _ _stringappend_944_ _)) => - returnm (rs1, build_ex _stringappend_944_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_944_ _) => - let _stringappend_945_ := - string_drop _stringappend_943_ - (build_ex _stringappend_944_) in - sep_matches_prefix _stringappend_945_ >>= fun w__326 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__326 with - | Some (tt,(existT _ _stringappend_946_ _)) => - returnm (tt, build_ex _stringappend_946_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_946_ _) => - let _stringappend_947_ := - string_drop _stringappend_945_ - (build_ex _stringappend_946_) in - (match (reg_name_matches_prefix _stringappend_947_) with - | Some (rs2,(existT _ _stringappend_948_ _)) => - returnm (rs2, build_ex _stringappend_948_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs2, existT _ _stringappend_948_ _) => - (match (string_drop _stringappend_947_ - (build_ex _stringappend_948_)) with - | "" => - returnm ((MUL - (rs2, rs1, rd, high, signed1, signed2)) - : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - and_boolM - (returnm ((string_startswith _stringappend_756_ "div") - : bool)) - (let _stringappend_950_ := - string_drop _stringappend_756_ - (build_ex (projT1 (string_length "div"))) in - match (maybe_not_u_matches_prefix _stringappend_950_) with - | Some (s,(existT _ _stringappend_951_ _)) => - let _stringappend_952_ := - string_drop _stringappend_950_ - (build_ex _stringappend_951_) in - match (spc_matches_prefix _stringappend_952_) with - | Some (tt,(existT _ _stringappend_953_ _)) => - let _stringappend_954_ := - string_drop _stringappend_952_ - (build_ex _stringappend_953_) in - match (reg_name_matches_prefix - _stringappend_954_) with - | Some (rd,(existT _ _stringappend_955_ _)) => - let _stringappend_956_ := - string_drop _stringappend_954_ - (build_ex _stringappend_955_) in - sep_matches_prefix _stringappend_956_ >>= fun w__333 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__333 with - | Some (tt,(existT _ _stringappend_957_ _)) => - let _stringappend_958_ := - string_drop _stringappend_956_ - (build_ex _stringappend_957_) in - match (reg_name_matches_prefix - _stringappend_958_) with - | Some - (rs1,(existT _ _stringappend_959_ _)) => - let _stringappend_960_ := - string_drop _stringappend_958_ - (build_ex _stringappend_959_) in - sep_matches_prefix _stringappend_960_ >>= fun w__334 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__334 with - | Some - (tt,(existT _ _stringappend_961_ _)) => - let _stringappend_962_ := - string_drop - _stringappend_960_ - (build_ex _stringappend_961_) in - if ((match (reg_name_matches_prefix - _stringappend_962_) with - | Some - (rs2,(existT _ _stringappend_963_ _)) => - match (string_drop - _stringappend_962_ - (build_ex _stringappend_963_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__335 : bool => - returnm ((if (w__335) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__336 : bool => - returnm ((if (w__336) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__337 : bool => - returnm ((if (w__337) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__338 : bool => - returnm ((if (w__338) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__339 : bool => - returnm ((if (w__339) then true - else false) - : bool)) >>= fun w__340 : bool => - (if (w__340) then - let _stringappend_950_ := - string_drop _stringappend_756_ - (build_ex (projT1 (string_length "div"))) in - (match (maybe_not_u_matches_prefix - _stringappend_950_) with - | Some (s,(existT _ _stringappend_951_ _)) => - returnm (s, build_ex _stringappend_951_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(s, existT _ _stringappend_951_ _) => - let _stringappend_952_ := - string_drop _stringappend_950_ - (build_ex _stringappend_951_) in - (match (spc_matches_prefix _stringappend_952_) with - | Some (tt,(existT _ _stringappend_953_ _)) => - returnm (tt, build_ex _stringappend_953_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_953_ _) => - let _stringappend_954_ := - string_drop _stringappend_952_ - (build_ex _stringappend_953_) in - (match (reg_name_matches_prefix _stringappend_954_) with - | Some (rd,(existT _ _stringappend_955_ _)) => - returnm (rd, build_ex _stringappend_955_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_955_ _) => - let _stringappend_956_ := - string_drop _stringappend_954_ - (build_ex _stringappend_955_) in - sep_matches_prefix _stringappend_956_ >>= fun w__347 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__347 with - | Some (tt,(existT _ _stringappend_957_ _)) => - returnm (tt, build_ex _stringappend_957_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_957_ _) => - let _stringappend_958_ := - string_drop _stringappend_956_ - (build_ex _stringappend_957_) in - (match (reg_name_matches_prefix _stringappend_958_) with - | Some (rs1,(existT _ _stringappend_959_ _)) => - returnm (rs1, build_ex _stringappend_959_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_959_ _) => - let _stringappend_960_ := - string_drop _stringappend_958_ - (build_ex _stringappend_959_) in - sep_matches_prefix _stringappend_960_ >>= fun w__352 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__352 with - | Some (tt,(existT _ _stringappend_961_ _)) => - returnm (tt, build_ex _stringappend_961_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_961_ _) => - let _stringappend_962_ := - string_drop _stringappend_960_ - (build_ex _stringappend_961_) in - (match (reg_name_matches_prefix _stringappend_962_) with - | Some (rs2,(existT _ _stringappend_963_ _)) => - returnm (rs2, build_ex _stringappend_963_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs2, existT _ _stringappend_963_ _) => - (match (string_drop _stringappend_962_ - (build_ex _stringappend_963_)) with - | "" => returnm ((DIV (rs2, rs1, rd, s)) : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - and_boolM - (returnm ((string_startswith _stringappend_756_ - "rem") - : bool)) - (let _stringappend_965_ := - string_drop _stringappend_756_ - (build_ex (projT1 (string_length "rem"))) in - match (maybe_not_u_matches_prefix - _stringappend_965_) with - | Some (s,(existT _ _stringappend_966_ _)) => - let _stringappend_967_ := - string_drop _stringappend_965_ - (build_ex _stringappend_966_) in - match (spc_matches_prefix _stringappend_967_) with - | Some (tt,(existT _ _stringappend_968_ _)) => - let _stringappend_969_ := - string_drop _stringappend_967_ - (build_ex _stringappend_968_) in - match (reg_name_matches_prefix - _stringappend_969_) with - | Some (rd,(existT _ _stringappend_970_ _)) => - let _stringappend_971_ := - string_drop _stringappend_969_ - (build_ex _stringappend_970_) in - sep_matches_prefix _stringappend_971_ >>= fun w__359 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__359 with - | Some - (tt,(existT _ _stringappend_972_ _)) => - let _stringappend_973_ := - string_drop _stringappend_971_ - (build_ex _stringappend_972_) in - match (reg_name_matches_prefix - _stringappend_973_) with - | Some - (rs1,(existT _ _stringappend_974_ _)) => - let _stringappend_975_ := - string_drop _stringappend_973_ - (build_ex _stringappend_974_) in - sep_matches_prefix - _stringappend_975_ >>= fun w__360 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__360 with - | Some - (tt,(existT _ _stringappend_976_ _)) => - let _stringappend_977_ := - string_drop - _stringappend_975_ - (build_ex _stringappend_976_) in - if ((match (reg_name_matches_prefix - _stringappend_977_) with - | Some - (rs2,(existT _ _stringappend_978_ _)) => - match (string_drop - _stringappend_977_ - (build_ex _stringappend_978_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__361 : bool => - returnm ((if (w__361) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__362 : bool => - returnm ((if (w__362) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__363 : bool => - returnm ((if (w__363) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__364 : bool => - returnm ((if (w__364) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__365 : bool => - returnm ((if (w__365) then true - else false) - : bool)) >>= fun w__366 : bool => - (if (w__366) then - let _stringappend_965_ := - string_drop _stringappend_756_ - (build_ex (projT1 (string_length "rem"))) in - (match (maybe_not_u_matches_prefix - _stringappend_965_) with - | Some (s,(existT _ _stringappend_966_ _)) => - returnm (s, build_ex _stringappend_966_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(s, existT _ _stringappend_966_ _) => - let _stringappend_967_ := - string_drop _stringappend_965_ - (build_ex _stringappend_966_) in - (match (spc_matches_prefix _stringappend_967_) with - | Some (tt,(existT _ _stringappend_968_ _)) => - returnm (tt, build_ex _stringappend_968_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_968_ _) => - let _stringappend_969_ := - string_drop _stringappend_967_ - (build_ex _stringappend_968_) in - (match (reg_name_matches_prefix - _stringappend_969_) with - | Some (rd,(existT _ _stringappend_970_ _)) => - returnm (rd, build_ex _stringappend_970_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_970_ _) => - let _stringappend_971_ := - string_drop _stringappend_969_ - (build_ex _stringappend_970_) in - sep_matches_prefix _stringappend_971_ >>= fun w__373 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__373 with - | Some (tt,(existT _ _stringappend_972_ _)) => - returnm (tt, build_ex _stringappend_972_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_972_ _) => - let _stringappend_973_ := - string_drop _stringappend_971_ - (build_ex _stringappend_972_) in - (match (reg_name_matches_prefix - _stringappend_973_) with - | Some (rs1,(existT _ _stringappend_974_ _)) => - returnm (rs1, build_ex _stringappend_974_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_974_ _) => - let _stringappend_975_ := - string_drop _stringappend_973_ - (build_ex _stringappend_974_) in - sep_matches_prefix _stringappend_975_ >>= fun w__378 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__378 with - | Some (tt,(existT _ _stringappend_976_ _)) => - returnm (tt, build_ex _stringappend_976_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_976_ _) => - let _stringappend_977_ := - string_drop _stringappend_975_ - (build_ex _stringappend_976_) in - (match (reg_name_matches_prefix - _stringappend_977_) with - | Some (rs2,(existT _ _stringappend_978_ _)) => - returnm (rs2, build_ex _stringappend_978_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs2, existT _ _stringappend_978_ _) => - (match (string_drop _stringappend_977_ - (build_ex _stringappend_978_)) with - | "" => - returnm ((REM (rs2, rs1, rd, s)) : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - and_boolM - (returnm ((string_startswith _stringappend_756_ - "mulw") - : bool)) - (let _stringappend_980_ := - string_drop _stringappend_756_ - (build_ex (projT1 (string_length "mulw"))) in - match (spc_matches_prefix _stringappend_980_) with - | Some (tt,(existT _ _stringappend_981_ _)) => - let _stringappend_982_ := - string_drop _stringappend_980_ - (build_ex _stringappend_981_) in - match (reg_name_matches_prefix - _stringappend_982_) with - | Some (rd,(existT _ _stringappend_983_ _)) => - let _stringappend_984_ := - string_drop _stringappend_982_ - (build_ex _stringappend_983_) in - sep_matches_prefix _stringappend_984_ >>= fun w__385 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__385 with - | Some - (tt,(existT _ _stringappend_985_ _)) => - let _stringappend_986_ := - string_drop _stringappend_984_ - (build_ex _stringappend_985_) in - match (reg_name_matches_prefix - _stringappend_986_) with - | Some - (rs1,(existT _ _stringappend_987_ _)) => - let _stringappend_988_ := - string_drop _stringappend_986_ - (build_ex _stringappend_987_) in - sep_matches_prefix - _stringappend_988_ >>= fun w__386 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__386 with - | Some - (tt,(existT _ _stringappend_989_ _)) => - let _stringappend_990_ := - string_drop - _stringappend_988_ - (build_ex _stringappend_989_) in - if ((match (reg_name_matches_prefix - _stringappend_990_) with - | Some - (rs2,(existT _ _stringappend_991_ _)) => - match (string_drop - _stringappend_990_ - (build_ex _stringappend_991_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__387 : bool => - returnm ((if (w__387) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__388 : bool => - returnm ((if (w__388) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__389 : bool => - returnm ((if (w__389) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__390 : bool => - returnm ((if (w__390) then true - else false) - : bool)) >>= fun w__391 : bool => - (if (w__391) then - let _stringappend_980_ := - string_drop _stringappend_756_ - (build_ex (projT1 (string_length "mulw"))) in - (match (spc_matches_prefix _stringappend_980_) with - | Some (tt,(existT _ _stringappend_981_ _)) => - returnm (tt, build_ex _stringappend_981_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_981_ _) => - let _stringappend_982_ := - string_drop _stringappend_980_ - (build_ex _stringappend_981_) in - (match (reg_name_matches_prefix - _stringappend_982_) with - | Some (rd,(existT _ _stringappend_983_ _)) => - returnm (rd, build_ex _stringappend_983_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_983_ _) => - let _stringappend_984_ := - string_drop _stringappend_982_ - (build_ex _stringappend_983_) in - sep_matches_prefix _stringappend_984_ >>= fun w__396 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__396 with - | Some (tt,(existT _ _stringappend_985_ _)) => - returnm (tt, build_ex _stringappend_985_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_985_ _) => - let _stringappend_986_ := - string_drop _stringappend_984_ - (build_ex _stringappend_985_) in - (match (reg_name_matches_prefix - _stringappend_986_) with - | Some (rs1,(existT _ _stringappend_987_ _)) => - returnm (rs1, build_ex _stringappend_987_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_987_ _) => - let _stringappend_988_ := - string_drop _stringappend_986_ - (build_ex _stringappend_987_) in - sep_matches_prefix _stringappend_988_ >>= fun w__401 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__401 with - | Some (tt,(existT _ _stringappend_989_ _)) => - returnm (tt, build_ex _stringappend_989_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_989_ _) => - let _stringappend_990_ := - string_drop _stringappend_988_ - (build_ex _stringappend_989_) in - (match (reg_name_matches_prefix - _stringappend_990_) with - | Some (rs2,(existT _ _stringappend_991_ _)) => - returnm (rs2, build_ex _stringappend_991_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs2, existT _ _stringappend_991_ _) => - (match (string_drop _stringappend_990_ - (build_ex _stringappend_991_)) with - | "" => - returnm ((MULW (rs2, rs1, rd)) : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - and_boolM - (returnm ((string_startswith - _stringappend_756_ "div") - : bool)) - (let _stringappend_993_ := - string_drop _stringappend_756_ - (build_ex (projT1 (string_length "div"))) in - match (maybe_not_u_matches_prefix - _stringappend_993_) with - | Some (s,(existT _ _stringappend_994_ _)) => - let _stringappend_995_ := - string_drop _stringappend_993_ - (build_ex _stringappend_994_) in - and_boolM - (returnm ((string_startswith - _stringappend_995_ "w") - : bool)) - (let _stringappend_996_ := - string_drop _stringappend_995_ - (build_ex (projT1 (string_length - "w"))) in - match (spc_matches_prefix - _stringappend_996_) with - | Some - (tt,(existT _ _stringappend_997_ _)) => - let _stringappend_998_ := - string_drop _stringappend_996_ - (build_ex _stringappend_997_) in - match (reg_name_matches_prefix - _stringappend_998_) with - | Some - (rd,(existT _ _stringappend_999_ _)) => - let _stringappend_1000_ := - string_drop _stringappend_998_ - (build_ex _stringappend_999_) in - sep_matches_prefix - _stringappend_1000_ >>= fun w__408 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__408 with - | Some - (tt,(existT _ _stringappend_1001_ _)) => - let _stringappend_1002_ := - string_drop - _stringappend_1000_ - (build_ex _stringappend_1001_) in - match (reg_name_matches_prefix - _stringappend_1002_) with - | Some - (rs1,(existT _ _stringappend_1003_ _)) => - let _stringappend_1004_ := - string_drop - _stringappend_1002_ - (build_ex _stringappend_1003_) in - sep_matches_prefix - _stringappend_1004_ >>= fun w__409 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__409 with - | Some - (tt,(existT _ _stringappend_1005_ _)) => - let _stringappend_1006_ := - string_drop - _stringappend_1004_ - (build_ex _stringappend_1005_) in - if ((match (reg_name_matches_prefix - _stringappend_1006_) with - | Some - (rs2,(existT _ _stringappend_1007_ _)) => - match (string_drop - _stringappend_1006_ - (build_ex _stringappend_1007_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__410 : bool => - returnm ((if (w__410) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__411 : bool => - returnm ((if (w__411) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__412 : bool => - returnm ((if (w__412) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__413 : bool => - returnm ((if (w__413) then true - else false) - : bool)) >>= fun w__414 : bool => - returnm ((if (w__414) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__415 : bool => - returnm ((if (w__415) then true - else false) - : bool)) >>= fun w__416 : bool => - (if (w__416) then - let _stringappend_993_ := - string_drop _stringappend_756_ - (build_ex (projT1 (string_length "div"))) in - (match (maybe_not_u_matches_prefix - _stringappend_993_) with - | Some (s,(existT _ _stringappend_994_ _)) => - returnm (s, build_ex _stringappend_994_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(s, existT _ _stringappend_994_ _) => - let _stringappend_995_ := - string_drop _stringappend_993_ - (build_ex _stringappend_994_) in - let _stringappend_996_ := - string_drop _stringappend_995_ - (build_ex (projT1 (string_length "w"))) in - (match (spc_matches_prefix - _stringappend_996_) with - | Some - (tt,(existT _ _stringappend_997_ _)) => - returnm (tt, build_ex _stringappend_997_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_997_ _) => - let _stringappend_998_ := - string_drop _stringappend_996_ - (build_ex _stringappend_997_) in - (match (reg_name_matches_prefix - _stringappend_998_) with - | Some - (rd,(existT _ _stringappend_999_ _)) => - returnm (rd, build_ex _stringappend_999_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_999_ _) => - let _stringappend_1000_ := - string_drop _stringappend_998_ - (build_ex _stringappend_999_) in - sep_matches_prefix _stringappend_1000_ >>= fun w__423 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__423 with - | Some - (tt,(existT _ _stringappend_1001_ _)) => - returnm (tt, build_ex _stringappend_1001_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1001_ _) => - let _stringappend_1002_ := - string_drop _stringappend_1000_ - (build_ex _stringappend_1001_) in - (match (reg_name_matches_prefix - _stringappend_1002_) with - | Some - (rs1,(existT _ _stringappend_1003_ _)) => - returnm (rs1, build_ex _stringappend_1003_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_1003_ _) => - let _stringappend_1004_ := - string_drop _stringappend_1002_ - (build_ex _stringappend_1003_) in - sep_matches_prefix _stringappend_1004_ >>= fun w__428 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__428 with - | Some - (tt,(existT _ _stringappend_1005_ _)) => - returnm (tt, build_ex _stringappend_1005_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1005_ _) => - let _stringappend_1006_ := - string_drop _stringappend_1004_ - (build_ex _stringappend_1005_) in - (match (reg_name_matches_prefix - _stringappend_1006_) with - | Some - (rs2,(existT _ _stringappend_1007_ _)) => - returnm (rs2, build_ex _stringappend_1007_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs2, existT _ _stringappend_1007_ _) => - (match (string_drop _stringappend_1006_ - (build_ex _stringappend_1007_)) with - | "" => - returnm ((DIVW - (rs2, rs1, rd, s)) - : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - and_boolM - (returnm ((string_startswith - _stringappend_756_ "rem") - : bool)) - (let _stringappend_1009_ := - string_drop _stringappend_756_ - (build_ex (projT1 (string_length - "rem"))) in - match (maybe_not_u_matches_prefix - _stringappend_1009_) with - | Some - (s,(existT _ _stringappend_1010_ _)) => - let _stringappend_1011_ := - string_drop _stringappend_1009_ - (build_ex _stringappend_1010_) in - and_boolM - (returnm ((string_startswith - _stringappend_1011_ "w") - : bool)) - (let _stringappend_1012_ := - string_drop _stringappend_1011_ - (build_ex (projT1 (string_length - "w"))) in - match (spc_matches_prefix - _stringappend_1012_) with - | Some - (tt,(existT _ _stringappend_1013_ _)) => - let _stringappend_1014_ := - string_drop _stringappend_1012_ - (build_ex _stringappend_1013_) in - match (reg_name_matches_prefix - _stringappend_1014_) with - | Some - (rd,(existT _ _stringappend_1015_ _)) => - let _stringappend_1016_ := - string_drop - _stringappend_1014_ - (build_ex _stringappend_1015_) in - sep_matches_prefix - _stringappend_1016_ >>= fun w__435 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__435 with - | Some - (tt,(existT _ _stringappend_1017_ _)) => - let _stringappend_1018_ := - string_drop - _stringappend_1016_ - (build_ex _stringappend_1017_) in - match (reg_name_matches_prefix - _stringappend_1018_) with - | Some - (rs1,(existT _ _stringappend_1019_ _)) => - let _stringappend_1020_ := - string_drop - _stringappend_1018_ - (build_ex _stringappend_1019_) in - sep_matches_prefix - _stringappend_1020_ >>= fun w__436 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__436 with - | Some - (tt,(existT _ _stringappend_1021_ _)) => - let _stringappend_1022_ := - string_drop - _stringappend_1020_ - (build_ex _stringappend_1021_) in - if ((match (reg_name_matches_prefix - _stringappend_1022_) with - | Some - (rs2,(existT _ _stringappend_1023_ _)) => - match (string_drop - _stringappend_1022_ - (build_ex _stringappend_1023_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) - then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__437 : bool => - returnm ((if (w__437) then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__438 : bool => - returnm ((if (w__438) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__439 : bool => - returnm ((if (w__439) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__440 : bool => - returnm ((if (w__440) then true - else false) - : bool)) >>= fun w__441 : bool => - returnm ((if (w__441) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__442 : bool => - returnm ((if (w__442) then true - else false) - : bool)) >>= fun w__443 : bool => - (if (w__443) then - let _stringappend_1009_ := - string_drop _stringappend_756_ - (build_ex (projT1 (string_length - "rem"))) in - (match (maybe_not_u_matches_prefix - _stringappend_1009_) with - | Some - (s,(existT _ _stringappend_1010_ _)) => - returnm (s, build_ex _stringappend_1010_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(s, existT _ _stringappend_1010_ _) => - let _stringappend_1011_ := - string_drop _stringappend_1009_ - (build_ex _stringappend_1010_) in - let _stringappend_1012_ := - string_drop _stringappend_1011_ - (build_ex (projT1 (string_length "w"))) in - (match (spc_matches_prefix - _stringappend_1012_) with - | Some - (tt,(existT _ _stringappend_1013_ _)) => - returnm (tt, build_ex _stringappend_1013_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1013_ _) => - let _stringappend_1014_ := - string_drop _stringappend_1012_ - (build_ex _stringappend_1013_) in - (match (reg_name_matches_prefix - _stringappend_1014_) with - | Some - (rd,(existT _ _stringappend_1015_ _)) => - returnm (rd, build_ex _stringappend_1015_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_1015_ _) => - let _stringappend_1016_ := - string_drop _stringappend_1014_ - (build_ex _stringappend_1015_) in - sep_matches_prefix _stringappend_1016_ >>= fun w__450 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__450 with - | Some - (tt,(existT _ _stringappend_1017_ _)) => - returnm (tt, build_ex _stringappend_1017_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1017_ _) => - let _stringappend_1018_ := - string_drop _stringappend_1016_ - (build_ex _stringappend_1017_) in - (match (reg_name_matches_prefix - _stringappend_1018_) with - | Some - (rs1,(existT _ _stringappend_1019_ _)) => - returnm (rs1, build_ex _stringappend_1019_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_1019_ _) => - let _stringappend_1020_ := - string_drop _stringappend_1018_ - (build_ex _stringappend_1019_) in - sep_matches_prefix _stringappend_1020_ >>= fun w__455 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__455 with - | Some - (tt,(existT _ _stringappend_1021_ _)) => - returnm (tt, build_ex _stringappend_1021_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1021_ _) => - let _stringappend_1022_ := - string_drop _stringappend_1020_ - (build_ex _stringappend_1021_) in - (match (reg_name_matches_prefix - _stringappend_1022_) with - | Some - (rs2,(existT _ _stringappend_1023_ _)) => - returnm (rs2, build_ex _stringappend_1023_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs2, existT _ _stringappend_1023_ _) => - (match (string_drop _stringappend_1022_ - (build_ex _stringappend_1023_)) with - | "" => - returnm ((REMW - (rs2, rs1, rd, s)) - : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - and_boolM - (returnm ((string_startswith - _stringappend_756_ - "fence") - : bool)) - (let _stringappend_1025_ := - string_drop _stringappend_756_ - (build_ex (projT1 (string_length - "fence"))) in - match (spc_matches_prefix - _stringappend_1025_) with - | Some - (tt,(existT _ _stringappend_1026_ _)) => - let _stringappend_1027_ := - string_drop _stringappend_1025_ - (build_ex _stringappend_1026_) in - fence_bits_matches_prefix - _stringappend_1027_ >>= fun w__462 : option ((mword 4 * {n : Z & ArithFact (n >= - 0)})) => - match w__462 with - | Some - (pred,(existT _ _stringappend_1028_ _)) => - let _stringappend_1029_ := - string_drop - _stringappend_1027_ - (build_ex _stringappend_1028_) in - sep_matches_prefix - _stringappend_1029_ >>= fun w__463 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__463 with - | Some - (tt,(existT _ _stringappend_1030_ _)) => - let _stringappend_1031_ := - string_drop - _stringappend_1029_ - (build_ex _stringappend_1030_) in - fence_bits_matches_prefix - _stringappend_1031_ >>= fun w__464 : option ((mword 4 * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__464 with - | Some - (succ,(existT _ _stringappend_1032_ _)) => - match (string_drop - _stringappend_1031_ - (build_ex _stringappend_1032_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__465 : bool => - returnm ((if (w__465) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__466 : bool => - returnm ((if (w__466) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__467 : bool => - returnm ((if (w__467) then true - else false) - : bool)) >>= fun w__468 : bool => - (if (w__468) then - let _stringappend_1025_ := - string_drop _stringappend_756_ - (build_ex (projT1 (string_length - "fence"))) in - (match (spc_matches_prefix - _stringappend_1025_) with - | Some - (tt,(existT _ _stringappend_1026_ _)) => - returnm (tt, build_ex _stringappend_1026_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1026_ _) => - let _stringappend_1027_ := - string_drop _stringappend_1025_ - (build_ex _stringappend_1026_) in - fence_bits_matches_prefix - _stringappend_1027_ >>= fun w__471 : option ((mword 4 * {n : Z & ArithFact (n >= - 0)})) => - (match w__471 with - | Some - (pred,(existT _ _stringappend_1028_ _)) => - returnm (pred, build_ex _stringappend_1028_) - | _ => - exit tt - : M ((mword 4 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 4 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(pred, existT _ _stringappend_1028_ _) => - let _stringappend_1029_ := - string_drop _stringappend_1027_ - (build_ex _stringappend_1028_) in - sep_matches_prefix - _stringappend_1029_ >>= fun w__474 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__474 with - | Some - (tt,(existT _ _stringappend_1030_ _)) => - returnm (tt, build_ex _stringappend_1030_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1030_ _) => - let _stringappend_1031_ := - string_drop _stringappend_1029_ - (build_ex _stringappend_1030_) in - fence_bits_matches_prefix - _stringappend_1031_ >>= fun w__477 : option ((mword 4 * {n : Z & ArithFact (n >= - 0)})) => - (match w__477 with - | Some - (succ,(existT _ _stringappend_1032_ _)) => - returnm (succ, build_ex _stringappend_1032_) - | _ => - exit tt - : M ((mword 4 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 4 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(succ, existT _ _stringappend_1032_ _) => - (match (string_drop - _stringappend_1031_ - (build_ex _stringappend_1032_)) with - | "" => - returnm ((FENCE - (pred, succ)) - : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - (match _stringappend_756_ with - | "fence.i" => - returnm ((FENCEI (tt)) : ast ) - | "ecall" => - returnm ((ECALL (tt)) : ast ) - | "mret" => - returnm ((MRET (tt)) : ast ) - | "sret" => - returnm ((SRET (tt)) : ast ) - | "ebreak" => - returnm ((EBREAK (tt)) : ast ) - | "wfi" => - returnm ((WFI (tt)) : ast ) - | _stringappend_756_ => - and_boolM - (returnm ((string_startswith - _stringappend_756_ - "sfence.vma") - : bool)) - (let _stringappend_1034_ := - string_drop - _stringappend_756_ - (build_ex (projT1 (string_length - "sfence.vma"))) in - match (spc_matches_prefix - _stringappend_1034_) with - | Some - (tt,(existT _ _stringappend_1035_ _)) => - let _stringappend_1036_ := - string_drop - _stringappend_1034_ - (build_ex _stringappend_1035_) in - match (reg_name_matches_prefix - _stringappend_1036_) with - | Some - (rs1,(existT _ _stringappend_1037_ _)) => - let _stringappend_1038_ := - string_drop - _stringappend_1036_ - (build_ex _stringappend_1037_) in - sep_matches_prefix - _stringappend_1038_ >>= fun w__482 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__482 with - | Some - (tt,(existT _ _stringappend_1039_ _)) => - let _stringappend_1040_ := - string_drop - _stringappend_1038_ - (build_ex _stringappend_1039_) in - if ((match (reg_name_matches_prefix - _stringappend_1040_) with - | Some - (rs2,(existT _ _stringappend_1041_ _)) => - match (string_drop - _stringappend_1040_ - (build_ex _stringappend_1041_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__483 : bool => - returnm ((if (w__483) then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__484 : bool => - returnm ((if (w__484) then true - else false) - : bool)) >>= fun w__485 : bool => - (if (w__485) then - let _stringappend_1034_ := - string_drop - _stringappend_756_ - (build_ex (projT1 (string_length - "sfence.vma"))) in - (match (spc_matches_prefix - _stringappend_1034_) with - | Some - (tt,(existT _ _stringappend_1035_ _)) => - returnm (tt, build_ex _stringappend_1035_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1035_ _) => - let _stringappend_1036_ := - string_drop - _stringappend_1034_ - (build_ex _stringappend_1035_) in - (match (reg_name_matches_prefix - _stringappend_1036_) with - | Some - (rs1,(existT _ _stringappend_1037_ _)) => - returnm (rs1, build_ex _stringappend_1037_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_1037_ _) => - let _stringappend_1038_ := - string_drop - _stringappend_1036_ - (build_ex _stringappend_1037_) in - sep_matches_prefix - _stringappend_1038_ >>= fun w__490 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__490 with - | Some - (tt,(existT _ _stringappend_1039_ _)) => - returnm (tt, build_ex _stringappend_1039_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1039_ _) => - let _stringappend_1040_ := - string_drop - _stringappend_1038_ - (build_ex _stringappend_1039_) in - (match (reg_name_matches_prefix - _stringappend_1040_) with - | Some - (rs2,(existT _ _stringappend_1041_ _)) => - returnm (rs2, build_ex _stringappend_1041_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs2, existT _ _stringappend_1041_ _) => - (match (string_drop - _stringappend_1040_ - (build_ex _stringappend_1041_)) with - | "" => - returnm ((SFENCE_VMA - (rs1, rs2)) - : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - and_boolM - (returnm ((string_startswith - _stringappend_756_ - "lr.") - : bool)) - (let _stringappend_1043_ := - string_drop - _stringappend_756_ - (build_ex (projT1 (string_length - "lr."))) in - match (maybe_aq_matches_prefix - _stringappend_1043_) with - | Some - (aq,(existT _ _stringappend_1044_ _)) => - let _stringappend_1045_ := - string_drop - _stringappend_1043_ - (build_ex _stringappend_1044_) in - match (maybe_rl_matches_prefix - _stringappend_1045_) with - | Some - (rl,(existT _ _stringappend_1046_ _)) => - let _stringappend_1047_ := - string_drop - _stringappend_1045_ - (build_ex _stringappend_1046_) in - match (size_mnemonic_matches_prefix - _stringappend_1047_) with - | Some - (size,(existT _ _stringappend_1048_ _)) => - let _stringappend_1049_ := - string_drop - _stringappend_1047_ - (build_ex _stringappend_1048_) in - match (spc_matches_prefix - _stringappend_1049_) with - | Some - (tt,(existT _ _stringappend_1050_ _)) => - let _stringappend_1051_ := - string_drop - _stringappend_1049_ - (build_ex _stringappend_1050_) in - match (reg_name_matches_prefix - _stringappend_1051_) with - | Some - (rd,(existT _ _stringappend_1052_ _)) => - let _stringappend_1053_ := - string_drop - _stringappend_1051_ - (build_ex _stringappend_1052_) in - sep_matches_prefix - _stringappend_1053_ >>= fun w__497 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__497 with - | Some - (tt,(existT _ _stringappend_1054_ _)) => - let _stringappend_1055_ := - string_drop - _stringappend_1053_ - (build_ex _stringappend_1054_) in - if - ((match (reg_name_matches_prefix - _stringappend_1055_) with - | Some - (rs1,(existT _ _stringappend_1056_ _)) => - match (string_drop - _stringappend_1055_ - (build_ex _stringappend_1056_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__498 : bool => - returnm ((if (w__498) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__499 : bool => - returnm ((if (w__499) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__500 : bool => - returnm ((if (w__500) - then - true - else false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__501 : bool => - returnm ((if (w__501) - then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__502 : bool => - returnm ((if (w__502) then - true - else false) - : bool)) >>= fun w__503 : bool => - (if (w__503) then - let _stringappend_1043_ := - string_drop - _stringappend_756_ - (build_ex (projT1 (string_length - "lr."))) in - (match (maybe_aq_matches_prefix - _stringappend_1043_) with - | Some - (aq,(existT _ _stringappend_1044_ _)) => - returnm (aq, build_ex _stringappend_1044_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(aq, existT _ _stringappend_1044_ _) => - let _stringappend_1045_ := - string_drop - _stringappend_1043_ - (build_ex _stringappend_1044_) in - (match (maybe_rl_matches_prefix - _stringappend_1045_) with - | Some - (rl,(existT _ _stringappend_1046_ _)) => - returnm (rl, build_ex _stringappend_1046_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rl, existT _ _stringappend_1046_ _) => - let _stringappend_1047_ := - string_drop - _stringappend_1045_ - (build_ex _stringappend_1046_) in - (match (size_mnemonic_matches_prefix - _stringappend_1047_) with - | Some - (size,(existT _ _stringappend_1048_ _)) => - returnm (size, build_ex _stringappend_1048_) - | _ => - exit tt - : M ((word_width * {n : Z & ArithFact (n >= - 0)})) - end : M ((word_width * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(size, existT _ _stringappend_1048_ _) => - let _stringappend_1049_ := - string_drop - _stringappend_1047_ - (build_ex _stringappend_1048_) in - (match (spc_matches_prefix - _stringappend_1049_) with - | Some - (tt,(existT _ _stringappend_1050_ _)) => - returnm (tt, build_ex _stringappend_1050_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1050_ _) => - let _stringappend_1051_ := - string_drop - _stringappend_1049_ - (build_ex _stringappend_1050_) in - (match (reg_name_matches_prefix - _stringappend_1051_) with - | Some - (rd,(existT _ _stringappend_1052_ _)) => - returnm (rd, build_ex _stringappend_1052_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_1052_ _) => - let _stringappend_1053_ := - string_drop - _stringappend_1051_ - (build_ex _stringappend_1052_) in - sep_matches_prefix - _stringappend_1053_ >>= fun w__514 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__514 with - | Some - (tt,(existT _ _stringappend_1054_ _)) => - returnm (tt, build_ex _stringappend_1054_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1054_ _) => - let _stringappend_1055_ := - string_drop - _stringappend_1053_ - (build_ex _stringappend_1054_) in - (match (reg_name_matches_prefix - _stringappend_1055_) with - | Some - (rs1,(existT _ _stringappend_1056_ _)) => - returnm (rs1, build_ex _stringappend_1056_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_1056_ _) => - (match (string_drop - _stringappend_1055_ - (build_ex _stringappend_1056_)) with - | "" => - returnm ((LOADRES - (aq, rl, - rs1, size, - rd)) - : ast ) - | _ => exit tt : M (ast) - end) - : M (ast) - else - and_boolM - (returnm ((string_startswith - _stringappend_756_ - "sc.") - : bool)) - (let _stringappend_1058_ := - string_drop - _stringappend_756_ - (build_ex (projT1 (string_length - "sc."))) in - match (maybe_aq_matches_prefix - _stringappend_1058_) with - | Some - (aq,(existT _ _stringappend_1059_ _)) => - let _stringappend_1060_ := - string_drop - _stringappend_1058_ - (build_ex _stringappend_1059_) in - match (maybe_rl_matches_prefix - _stringappend_1060_) with - | Some - (rl,(existT _ _stringappend_1061_ _)) => - let _stringappend_1062_ := - string_drop - _stringappend_1060_ - (build_ex _stringappend_1061_) in - match (size_mnemonic_matches_prefix - _stringappend_1062_) with - | Some - (size,(existT _ _stringappend_1063_ _)) => - let _stringappend_1064_ := - string_drop - _stringappend_1062_ - (build_ex _stringappend_1063_) in - match (spc_matches_prefix - _stringappend_1064_) with - | Some - (tt,(existT _ _stringappend_1065_ _)) => - let _stringappend_1066_ := - string_drop - _stringappend_1064_ - (build_ex _stringappend_1065_) in - match (reg_name_matches_prefix - _stringappend_1066_) with - | Some - (rd,(existT _ _stringappend_1067_ _)) => - let _stringappend_1068_ := - string_drop - _stringappend_1066_ - (build_ex _stringappend_1067_) in - sep_matches_prefix - _stringappend_1068_ >>= fun w__521 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__521 with - | Some - (tt,(existT _ _stringappend_1069_ _)) => - let _stringappend_1070_ := - string_drop - _stringappend_1068_ - (build_ex _stringappend_1069_) in - match (reg_name_matches_prefix - _stringappend_1070_) with - | Some - (rs1,(existT _ _stringappend_1071_ _)) => - let _stringappend_1072_ := - string_drop - _stringappend_1070_ - (build_ex _stringappend_1071_) in - sep_matches_prefix - _stringappend_1072_ >>= fun w__522 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if - ((match w__522 with - | Some - (tt,(existT _ _stringappend_1073_ _)) => - let _stringappend_1074_ := - string_drop - _stringappend_1072_ - (build_ex _stringappend_1073_) in - if - ((match (reg_name_matches_prefix - _stringappend_1074_) with - | Some - (rs2,(existT _ _stringappend_1075_ _)) => - match (string_drop - _stringappend_1074_ - (build_ex _stringappend_1075_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__523 : bool => - returnm ((if - (w__523) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__524 : bool => - returnm ((if - (w__524) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__525 : bool => - returnm ((if (w__525) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__526 : bool => - returnm ((if (w__526) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__527 : bool => - returnm ((if (w__527) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__528 : bool => - returnm ((if (w__528) - then - true - else false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__529 : bool => - returnm ((if (w__529) - then - true - else false) - : bool)) >>= fun w__530 : bool => - (if (w__530) then - let _stringappend_1058_ := - string_drop - _stringappend_756_ - (build_ex (projT1 (string_length - "sc."))) in - (match (maybe_aq_matches_prefix - _stringappend_1058_) with - | Some - (aq,(existT _ _stringappend_1059_ _)) => - returnm (aq, build_ex _stringappend_1059_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(aq, existT _ _stringappend_1059_ _) => - let _stringappend_1060_ := - string_drop - _stringappend_1058_ - (build_ex _stringappend_1059_) in - (match (maybe_rl_matches_prefix - _stringappend_1060_) with - | Some - (rl,(existT _ _stringappend_1061_ _)) => - returnm (rl, build_ex _stringappend_1061_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rl, existT _ _stringappend_1061_ _) => - let _stringappend_1062_ := - string_drop - _stringappend_1060_ - (build_ex _stringappend_1061_) in - (match (size_mnemonic_matches_prefix - _stringappend_1062_) with - | Some - (size,(existT _ _stringappend_1063_ _)) => - returnm (size, build_ex _stringappend_1063_) - | _ => - exit tt - : M ((word_width * {n : Z & ArithFact (n >= - 0)})) - end : M ((word_width * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(size, existT _ _stringappend_1063_ _) => - let _stringappend_1064_ := - string_drop - _stringappend_1062_ - (build_ex _stringappend_1063_) in - (match (spc_matches_prefix - _stringappend_1064_) with - | Some - (tt,(existT _ _stringappend_1065_ _)) => - returnm (tt, build_ex _stringappend_1065_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1065_ _) => - let _stringappend_1066_ := - string_drop - _stringappend_1064_ - (build_ex _stringappend_1065_) in - (match (reg_name_matches_prefix - _stringappend_1066_) with - | Some - (rd,(existT _ _stringappend_1067_ _)) => - returnm (rd, build_ex _stringappend_1067_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_1067_ _) => - let _stringappend_1068_ := - string_drop - _stringappend_1066_ - (build_ex _stringappend_1067_) in - sep_matches_prefix - _stringappend_1068_ >>= fun w__541 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__541 with - | Some - (tt,(existT _ _stringappend_1069_ _)) => - returnm (tt, build_ex _stringappend_1069_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1069_ _) => - let _stringappend_1070_ := - string_drop - _stringappend_1068_ - (build_ex _stringappend_1069_) in - (match (reg_name_matches_prefix - _stringappend_1070_) with - | Some - (rs1,(existT _ _stringappend_1071_ _)) => - returnm (rs1, build_ex _stringappend_1071_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_1071_ _) => - let _stringappend_1072_ := - string_drop - _stringappend_1070_ - (build_ex _stringappend_1071_) in - sep_matches_prefix - _stringappend_1072_ >>= fun w__546 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__546 with - | Some - (tt,(existT _ _stringappend_1073_ _)) => - returnm (tt, build_ex _stringappend_1073_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1073_ _) => - let _stringappend_1074_ := - string_drop - _stringappend_1072_ - (build_ex _stringappend_1073_) in - (match (reg_name_matches_prefix - _stringappend_1074_) with - | Some - (rs2,(existT _ _stringappend_1075_ _)) => - returnm (rs2, build_ex _stringappend_1075_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs2, existT _ _stringappend_1075_ _) => - (match (string_drop - _stringappend_1074_ - (build_ex _stringappend_1075_)) with - | "" => - returnm ((STORECON - (aq, rl, - rs2, rs1, - size, rd)) - : ast ) - | _ => - exit tt : M (ast) - end) - : M (ast) - else - match (amo_mnemonic_matches_prefix - _stringappend_756_) with - | Some - (op,(existT _ _stringappend_1077_ _)) => - let _stringappend_1078_ := - string_drop - _stringappend_756_ - (build_ex _stringappend_1077_) in - and_boolM - (returnm ((string_startswith - _stringappend_1078_ - ".") - : bool)) - (let _stringappend_1079_ := - string_drop - _stringappend_1078_ - (build_ex (projT1 (string_length - "."))) in - match (size_mnemonic_matches_prefix - _stringappend_1079_) with - | Some - (width,(existT _ _stringappend_1080_ _)) => - let _stringappend_1081_ := - string_drop - _stringappend_1079_ - (build_ex _stringappend_1080_) in - match (maybe_aq_matches_prefix - _stringappend_1081_) with - | Some - (aq,(existT _ _stringappend_1082_ _)) => - let _stringappend_1083_ := - string_drop - _stringappend_1081_ - (build_ex _stringappend_1082_) in - match (maybe_rl_matches_prefix - _stringappend_1083_) with - | Some - (rl,(existT _ _stringappend_1084_ _)) => - let _stringappend_1085_ := - string_drop - _stringappend_1083_ - (build_ex _stringappend_1084_) in - match (spc_matches_prefix - _stringappend_1085_) with - | Some - (tt,(existT _ _stringappend_1086_ _)) => - let _stringappend_1087_ := - string_drop - _stringappend_1085_ - (build_ex _stringappend_1086_) in - match (reg_name_matches_prefix - _stringappend_1087_) with - | Some - (rd,(existT _ _stringappend_1088_ _)) => - let _stringappend_1089_ := - string_drop - _stringappend_1087_ - (build_ex _stringappend_1088_) in - sep_matches_prefix - _stringappend_1089_ >>= fun w__553 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__553 with - | Some - (tt,(existT _ _stringappend_1090_ _)) => - let _stringappend_1091_ := - string_drop - _stringappend_1089_ - (build_ex _stringappend_1090_) in - match (reg_name_matches_prefix - _stringappend_1091_) with - | Some - (rs1,(existT _ _stringappend_1092_ _)) => - let _stringappend_1093_ := - string_drop - _stringappend_1091_ - (build_ex _stringappend_1092_) in - sep_matches_prefix - _stringappend_1093_ >>= fun w__554 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if - ((match w__554 with - | Some - (tt,(existT _ _stringappend_1094_ _)) => - let _stringappend_1095_ := - string_drop - _stringappend_1093_ - (build_ex _stringappend_1094_) in - if - ((match (reg_name_matches_prefix - _stringappend_1095_) with - | Some - (rs2,(existT _ _stringappend_1096_ _)) => - match (string_drop - _stringappend_1095_ - (build_ex _stringappend_1096_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__555 : bool => - returnm ((if - (w__555) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__556 : bool => - returnm ((if - (w__556) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__557 : bool => - returnm ((if - (w__557) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__558 : bool => - returnm ((if - (w__558) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__559 : bool => - returnm ((if (w__559) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__560 : bool => - returnm ((if (w__560) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__561 : bool => - returnm ((if (w__561) - then - true - else - false) - : bool)) >>= fun w__562 : bool => - returnm ((if (w__562) - then - true - else false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__563 : bool => - (if (w__563) then - (match (amo_mnemonic_matches_prefix - _stringappend_756_) with - | Some - (op,(existT _ _stringappend_1077_ _)) => - returnm (op, build_ex _stringappend_1077_) - | _ => - exit tt - : M ((amoop * {n : Z & ArithFact (n >= - 0)})) - end : M ((amoop * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(op, existT _ _stringappend_1077_ _) => - let _stringappend_1078_ := - string_drop - _stringappend_756_ - (build_ex _stringappend_1077_) in - let _stringappend_1079_ := - string_drop - _stringappend_1078_ - (build_ex (projT1 (string_length - "."))) in - (match (size_mnemonic_matches_prefix - _stringappend_1079_) with - | Some - (width,(existT _ _stringappend_1080_ _)) => - returnm (width, build_ex _stringappend_1080_) - | _ => - exit tt - : M ((word_width * {n : Z & ArithFact (n >= - 0)})) - end : M ((word_width * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(width, existT _ _stringappend_1080_ _) => - let _stringappend_1081_ := - string_drop - _stringappend_1079_ - (build_ex _stringappend_1080_) in - (match (maybe_aq_matches_prefix - _stringappend_1081_) with - | Some - (aq,(existT _ _stringappend_1082_ _)) => - returnm (aq, build_ex _stringappend_1082_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(aq, existT _ _stringappend_1082_ _) => - let _stringappend_1083_ := - string_drop - _stringappend_1081_ - (build_ex _stringappend_1082_) in - (match (maybe_rl_matches_prefix - _stringappend_1083_) with - | Some - (rl,(existT _ _stringappend_1084_ _)) => - returnm (rl, build_ex _stringappend_1084_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rl, existT _ _stringappend_1084_ _) => - let _stringappend_1085_ := - string_drop - _stringappend_1083_ - (build_ex _stringappend_1084_) in - (match (spc_matches_prefix - _stringappend_1085_) with - | Some - (tt,(existT _ _stringappend_1086_ _)) => - returnm (tt, build_ex _stringappend_1086_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1086_ _) => - let _stringappend_1087_ := - string_drop - _stringappend_1085_ - (build_ex _stringappend_1086_) in - (match (reg_name_matches_prefix - _stringappend_1087_) with - | Some - (rd,(existT _ _stringappend_1088_ _)) => - returnm (rd, build_ex _stringappend_1088_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_1088_ _) => - let _stringappend_1089_ := - string_drop - _stringappend_1087_ - (build_ex _stringappend_1088_) in - sep_matches_prefix - _stringappend_1089_ >>= fun w__576 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__576 with - | Some - (tt,(existT _ _stringappend_1090_ _)) => - returnm (tt, build_ex _stringappend_1090_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1090_ _) => - let _stringappend_1091_ := - string_drop - _stringappend_1089_ - (build_ex _stringappend_1090_) in - (match (reg_name_matches_prefix - _stringappend_1091_) with - | Some - (rs1,(existT _ _stringappend_1092_ _)) => - returnm (rs1, build_ex _stringappend_1092_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_1092_ _) => - let _stringappend_1093_ := - string_drop - _stringappend_1091_ - (build_ex _stringappend_1092_) in - sep_matches_prefix - _stringappend_1093_ >>= fun w__581 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__581 with - | Some - (tt,(existT _ _stringappend_1094_ _)) => - returnm (tt, build_ex _stringappend_1094_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1094_ _) => - let _stringappend_1095_ := - string_drop - _stringappend_1093_ - (build_ex _stringappend_1094_) in - (match (reg_name_matches_prefix - _stringappend_1095_) with - | Some - (rs2,(existT _ _stringappend_1096_ _)) => - returnm (rs2, build_ex _stringappend_1096_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs2, existT _ _stringappend_1096_ _) => - (match (string_drop - _stringappend_1095_ - (build_ex _stringappend_1096_)) with - | "" => - returnm ((AMO - (op, - aq, - rl, - rs2, - rs1, - width, - rd)) - : ast ) - | _ => - exit tt - : M (ast) - end) - : M (ast) - else - match (csr_mnemonic_matches_prefix - _stringappend_756_) with - | Some - (op,(existT _ _stringappend_1098_ _)) => - let _stringappend_1099_ := - string_drop - _stringappend_756_ - (build_ex _stringappend_1098_) in - and_boolM - (returnm ((string_startswith - _stringappend_1099_ - "i") - : bool)) - (let _stringappend_1100_ := - string_drop - _stringappend_1099_ - (build_ex (projT1 (string_length - "i"))) in - match (spc_matches_prefix - _stringappend_1100_) with - | Some - (tt,(existT _ _stringappend_1101_ _)) => - let _stringappend_1102_ := - string_drop - _stringappend_1100_ - (build_ex _stringappend_1101_) in - match (reg_name_matches_prefix - _stringappend_1102_) with - | Some - (rd,(existT _ _stringappend_1103_ _)) => - let _stringappend_1104_ := - string_drop - _stringappend_1102_ - (build_ex _stringappend_1103_) in - sep_matches_prefix - _stringappend_1104_ >>= fun w__588 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__588 with - | Some - (tt,(existT _ _stringappend_1105_ _)) => - let _stringappend_1106_ := - string_drop - _stringappend_1104_ - (build_ex _stringappend_1105_) in - match (hex_bits_5_matches_prefix - _stringappend_1106_) with - | Some - (rs1,(existT _ _stringappend_1107_ _)) => - let _stringappend_1108_ := - string_drop - _stringappend_1106_ - (build_ex _stringappend_1107_) in - sep_matches_prefix - _stringappend_1108_ >>= fun w__589 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if - ((match w__589 with - | Some - (tt,(existT _ _stringappend_1109_ _)) => - let _stringappend_1110_ := - string_drop - _stringappend_1108_ - (build_ex _stringappend_1109_) in - if - ((match (csr_name_map_matches_prefix - _stringappend_1110_) with - | Some - (csr,(existT _ _stringappend_1111_ _)) => - match (string_drop - _stringappend_1110_ - (build_ex _stringappend_1111_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__590 : bool => - returnm ((if - (w__590) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__591 : bool => - returnm ((if - (w__591) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__592 : bool => - returnm ((if (w__592) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__593 : bool => - returnm ((if (w__593) - then - true - else - false) - : bool)) >>= fun w__594 : bool => - returnm ((if (w__594) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__595 : bool => - (if (w__595) then - (match (csr_mnemonic_matches_prefix - _stringappend_756_) with - | Some - (op,(existT _ _stringappend_1098_ _)) => - returnm (op, build_ex _stringappend_1098_) - | _ => - exit tt - : M ((csrop * {n : Z & ArithFact (n >= - 0)})) - end : M ((csrop * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(op, existT _ _stringappend_1098_ _) => - let _stringappend_1099_ := - string_drop - _stringappend_756_ - (build_ex _stringappend_1098_) in - let _stringappend_1100_ := - string_drop - _stringappend_1099_ - (build_ex (projT1 (string_length - "i"))) in - (match (spc_matches_prefix - _stringappend_1100_) with - | Some - (tt,(existT _ _stringappend_1101_ _)) => - returnm (tt, build_ex _stringappend_1101_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1101_ _) => - let _stringappend_1102_ := - string_drop - _stringappend_1100_ - (build_ex _stringappend_1101_) in - (match (reg_name_matches_prefix - _stringappend_1102_) with - | Some - (rd,(existT _ _stringappend_1103_ _)) => - returnm (rd, build_ex _stringappend_1103_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_1103_ _) => - let _stringappend_1104_ := - string_drop - _stringappend_1102_ - (build_ex _stringappend_1103_) in - sep_matches_prefix - _stringappend_1104_ >>= fun w__602 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__602 with - | Some - (tt,(existT _ _stringappend_1105_ _)) => - returnm (tt, build_ex _stringappend_1105_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1105_ _) => - let _stringappend_1106_ := - string_drop - _stringappend_1104_ - (build_ex _stringappend_1105_) in - (match (hex_bits_5_matches_prefix - _stringappend_1106_) with - | Some - (rs1,(existT _ _stringappend_1107_ _)) => - returnm (rs1, build_ex _stringappend_1107_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_1107_ _) => - let _stringappend_1108_ := - string_drop - _stringappend_1106_ - (build_ex _stringappend_1107_) in - sep_matches_prefix - _stringappend_1108_ >>= fun w__607 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__607 with - | Some - (tt,(existT _ _stringappend_1109_ _)) => - returnm (tt, build_ex _stringappend_1109_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1109_ _) => - let _stringappend_1110_ := - string_drop - _stringappend_1108_ - (build_ex _stringappend_1109_) in - (match (csr_name_map_matches_prefix - _stringappend_1110_) with - | Some - (csr,(existT _ _stringappend_1111_ _)) => - returnm (csr, build_ex _stringappend_1111_) - | _ => - exit tt - : M ((mword 12 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(csr, existT _ _stringappend_1111_ _) => - (match (string_drop - _stringappend_1110_ - (build_ex _stringappend_1111_)) with - | "" => - returnm ((CSR - (csr, - rs1, - rd, - true, - op)) - : ast ) - | _ => - exit tt - : M (ast) - end) - : M (ast) - else - match (csr_mnemonic_matches_prefix - _stringappend_756_) with - | Some - (op,(existT _ _stringappend_1113_ _)) => - let _stringappend_1114_ := - string_drop - _stringappend_756_ - (build_ex _stringappend_1113_) in - match (spc_matches_prefix - _stringappend_1114_) with - | Some - (tt,(existT _ _stringappend_1115_ _)) => - let _stringappend_1116_ := - string_drop - _stringappend_1114_ - (build_ex _stringappend_1115_) in - match (reg_name_matches_prefix - _stringappend_1116_) with - | Some - (rd,(existT _ _stringappend_1117_ _)) => - let _stringappend_1118_ := - string_drop - _stringappend_1116_ - (build_ex _stringappend_1117_) in - sep_matches_prefix - _stringappend_1118_ >>= fun w__614 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__614 with - | Some - (tt,(existT _ _stringappend_1119_ _)) => - let _stringappend_1120_ := - string_drop - _stringappend_1118_ - (build_ex _stringappend_1119_) in - match (reg_name_matches_prefix - _stringappend_1120_) with - | Some - (rs1,(existT _ _stringappend_1121_ _)) => - let _stringappend_1122_ := - string_drop - _stringappend_1120_ - (build_ex _stringappend_1121_) in - sep_matches_prefix - _stringappend_1122_ >>= fun w__615 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if - ((match w__615 with - | Some - (tt,(existT _ _stringappend_1123_ _)) => - let _stringappend_1124_ := - string_drop - _stringappend_1122_ - (build_ex _stringappend_1123_) in - if - ((match (csr_name_map_matches_prefix - _stringappend_1124_) with - | Some - (csr,(existT _ _stringappend_1125_ _)) => - match (string_drop - _stringappend_1124_ - (build_ex _stringappend_1125_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__616 : bool => - returnm ((if - (w__616) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__617 : bool => - returnm ((if - (w__617) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__618 : bool => - returnm ((if - (w__618) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__619 : bool => - returnm ((if (w__619) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__620 : bool => - (if (w__620) then - (match (csr_mnemonic_matches_prefix - _stringappend_756_) with - | Some - (op,(existT _ _stringappend_1113_ _)) => - returnm (op, build_ex _stringappend_1113_) - | _ => - exit tt - : M ((csrop * {n : Z & ArithFact (n >= - 0)})) - end : M ((csrop * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(op, existT _ _stringappend_1113_ _) => - let _stringappend_1114_ := - string_drop - _stringappend_756_ - (build_ex _stringappend_1113_) in - (match (spc_matches_prefix - _stringappend_1114_) with - | Some - (tt,(existT _ _stringappend_1115_ _)) => - returnm (tt, build_ex _stringappend_1115_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1115_ _) => - let _stringappend_1116_ := - string_drop - _stringappend_1114_ - (build_ex _stringappend_1115_) in - (match (reg_name_matches_prefix - _stringappend_1116_) with - | Some - (rd,(existT _ _stringappend_1117_ _)) => - returnm (rd, build_ex _stringappend_1117_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_1117_ _) => - let _stringappend_1118_ := - string_drop - _stringappend_1116_ - (build_ex _stringappend_1117_) in - sep_matches_prefix - _stringappend_1118_ >>= fun w__627 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__627 with - | Some - (tt,(existT _ _stringappend_1119_ _)) => - returnm (tt, build_ex _stringappend_1119_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1119_ _) => - let _stringappend_1120_ := - string_drop - _stringappend_1118_ - (build_ex _stringappend_1119_) in - (match (reg_name_matches_prefix - _stringappend_1120_) with - | Some - (rs1,(existT _ _stringappend_1121_ _)) => - returnm (rs1, build_ex _stringappend_1121_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_1121_ _) => - let _stringappend_1122_ := - string_drop - _stringappend_1120_ - (build_ex _stringappend_1121_) in - sep_matches_prefix - _stringappend_1122_ >>= fun w__632 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__632 with - | Some - (tt,(existT _ _stringappend_1123_ _)) => - returnm (tt, build_ex _stringappend_1123_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1123_ _) => - let _stringappend_1124_ := - string_drop - _stringappend_1122_ - (build_ex _stringappend_1123_) in - (match (csr_name_map_matches_prefix - _stringappend_1124_) with - | Some - (csr,(existT _ _stringappend_1125_ _)) => - returnm (csr, build_ex _stringappend_1125_) - | _ => - exit tt - : M ((mword 12 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(csr, existT _ _stringappend_1125_ _) => - (match (string_drop - _stringappend_1124_ - (build_ex _stringappend_1125_)) with - | "" => - returnm ((CSR - (csr, - rs1, - rd, - false, - op)) - : ast ) - | _ => - exit tt - : M (ast) - end) - : M (ast) - else - let _stringappend_1127_ := - string_drop - _stringappend_756_ - (build_ex (projT1 (string_length - "illegal"))) in - (match (spc_matches_prefix - _stringappend_1127_) with - | Some - (tt,(existT _ _stringappend_1128_ _)) => - returnm (tt, build_ex _stringappend_1128_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_1128_ _) => - let _stringappend_1129_ := - string_drop - _stringappend_1127_ - (build_ex _stringappend_1128_) in - (match (hex_bits_32_matches_prefix - _stringappend_1129_) with - | Some - (s,(existT _ _stringappend_1130_ _)) => - returnm (s, build_ex _stringappend_1130_) - | _ => - exit tt - : M ((mword 32 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 32 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(s, existT _ _stringappend_1130_ _) => - (match (string_drop - _stringappend_1129_ - (build_ex _stringappend_1130_)) with - | "" => - returnm ((ILLEGAL - (s)) - : ast ) - | _ => - exit tt - : M (ast) - end) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast) - end) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast)) - : M (ast). - -Definition assembly_forwards_matches (arg_ : ast) -: bool := - match arg_ with - | UTYPE (imm,rd,op) => true - | RISCV_JAL (imm,rd) => true - | RISCV_JALR (imm,rs1,rd) => true - | BTYPE (imm,rs2,rs1,op) => true - | ITYPE (imm,rs1,rd,op) => true - | SHIFTIOP (shamt,rs1,rd,op) => true - | RTYPE (rs2,rs1,rd,op) => true - | LOAD (imm,rs1,rd,is_unsigned,size,aq,rl) => true - | STORE (imm,rs1,rd,size,aq,rl) => true - | ADDIW (imm,rs1,rd) => true - | SHIFTW (shamt,rs1,rd,op) => true - | RTYPEW (rs2,rs1,rd,op) => true - | SHIFTIWOP (shamt,rs1,rd,op) => true - | MUL (rs2,rs1,rd,high,signed1,signed2) => true - | DIV (rs2,rs1,rd,s) => true - | REM (rs2,rs1,rd,s) => true - | MULW (rs2,rs1,rd) => true - | DIVW (rs2,rs1,rd,s) => true - | REMW (rs2,rs1,rd,s) => true - | FENCE (pred,succ) => true - | FENCEI (tt) => true - | ECALL (tt) => true - | MRET (tt) => true - | SRET (tt) => true - | EBREAK (tt) => true - | WFI (tt) => true - | SFENCE_VMA (rs1,rs2) => true - | LOADRES (aq,rl,rs1,size,rd) => true - | STORECON (aq,rl,rs2,rs1,size,rd) => true - | AMO (op,aq,rl,rs2,rs1,width,rd) => true - | CSR (csr,rs1,rd,true,op) => true - | CSR (csr,rs1,rd,false,op) => true - | ILLEGAL (s) => true - | _ => false - end. - -Definition assembly_backwards_matches (arg_ : string) -: M (bool) := - let _stringappend_381_ := arg_ in - match (utype_mnemonic_matches_prefix _stringappend_381_) with - | Some (op,(existT _ _stringappend_382_ _)) => - let _stringappend_383_ := string_drop _stringappend_381_ (build_ex _stringappend_382_) in - match (spc_matches_prefix _stringappend_383_) with - | Some (tt,(existT _ _stringappend_384_ _)) => - let _stringappend_385_ := string_drop _stringappend_383_ (build_ex _stringappend_384_) in - match (reg_name_matches_prefix _stringappend_385_) with - | Some (rd,(existT _ _stringappend_386_ _)) => - let _stringappend_387_ := string_drop _stringappend_385_ (build_ex _stringappend_386_) in - sep_matches_prefix _stringappend_387_ >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__0 with - | Some (tt,(existT _ _stringappend_388_ _)) => - let _stringappend_389_ := - string_drop _stringappend_387_ (build_ex _stringappend_388_) in - if ((match (hex_bits_20_matches_prefix _stringappend_389_) with - | Some (imm,(existT _ _stringappend_390_ _)) => - match (string_drop _stringappend_389_ - (build_ex _stringappend_390_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__1 : bool => - returnm ((if (w__1) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__2 : bool => - returnm ((if (w__2) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__3 : bool => - (if (w__3) then - (match (utype_mnemonic_matches_prefix _stringappend_381_) with - | Some (op,(existT _ _stringappend_382_ _)) => returnm (op, build_ex _stringappend_382_) - | _ => exit tt : M ((uop * {n : Z & ArithFact (n >= 0)})) - end : M ((uop * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_382_ _) => - let _stringappend_383_ := string_drop _stringappend_381_ (build_ex _stringappend_382_) in - (match (spc_matches_prefix _stringappend_383_) with - | Some (tt,(existT _ _stringappend_384_ _)) => returnm (tt, build_ex _stringappend_384_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_384_ _) => - let _stringappend_385_ := string_drop _stringappend_383_ (build_ex _stringappend_384_) in - (match (reg_name_matches_prefix _stringappend_385_) with - | Some (rd,(existT _ _stringappend_386_ _)) => returnm (rd, build_ex _stringappend_386_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_386_ _) => - let _stringappend_387_ := string_drop _stringappend_385_ (build_ex _stringappend_386_) in - sep_matches_prefix _stringappend_387_ >>= fun w__10 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__10 with - | Some (tt,(existT _ _stringappend_388_ _)) => returnm (tt, build_ex _stringappend_388_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_388_ _) => - let _stringappend_389_ := string_drop _stringappend_387_ (build_ex _stringappend_388_) in - (match (hex_bits_20_matches_prefix _stringappend_389_) with - | Some (imm,(existT _ _stringappend_390_ _)) => returnm (imm, build_ex _stringappend_390_) - | _ => exit tt : M ((mword 20 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 20 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_390_ _) => - (match (string_drop _stringappend_389_ (build_ex _stringappend_390_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - and_boolM (returnm ((string_startswith _stringappend_381_ "jal") : bool)) - (let _stringappend_392_ := - string_drop _stringappend_381_ (build_ex (projT1 (string_length "jal"))) in - match (spc_matches_prefix _stringappend_392_) with - | Some (tt,(existT _ _stringappend_393_ _)) => - let _stringappend_394_ := string_drop _stringappend_392_ (build_ex _stringappend_393_) in - match (reg_name_matches_prefix _stringappend_394_) with - | Some (rd,(existT _ _stringappend_395_ _)) => - let _stringappend_396_ := string_drop _stringappend_394_ (build_ex _stringappend_395_) in - sep_matches_prefix _stringappend_396_ >>= fun w__17 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__17 with - | Some (tt,(existT _ _stringappend_397_ _)) => - let _stringappend_398_ := - string_drop _stringappend_396_ (build_ex _stringappend_397_) in - if ((match (hex_bits_21_matches_prefix _stringappend_398_) with - | Some (imm,(existT _ _stringappend_399_ _)) => - match (string_drop _stringappend_398_ - (build_ex _stringappend_399_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__18 : bool => - returnm ((if (w__18) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__19 : bool => - returnm ((if (w__19) then true - else false) - : bool)) >>= fun w__20 : bool => - (if (w__20) then - let _stringappend_392_ := - string_drop _stringappend_381_ (build_ex (projT1 (string_length "jal"))) in - (match (spc_matches_prefix _stringappend_392_) with - | Some (tt,(existT _ _stringappend_393_ _)) => returnm (tt, build_ex _stringappend_393_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_393_ _) => - let _stringappend_394_ := string_drop _stringappend_392_ (build_ex _stringappend_393_) in - (match (reg_name_matches_prefix _stringappend_394_) with - | Some (rd,(existT _ _stringappend_395_ _)) => returnm (rd, build_ex _stringappend_395_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_395_ _) => - let _stringappend_396_ := string_drop _stringappend_394_ (build_ex _stringappend_395_) in - sep_matches_prefix _stringappend_396_ >>= fun w__25 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__25 with - | Some (tt,(existT _ _stringappend_397_ _)) => returnm (tt, build_ex _stringappend_397_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_397_ _) => - let _stringappend_398_ := string_drop _stringappend_396_ (build_ex _stringappend_397_) in - (match (hex_bits_21_matches_prefix _stringappend_398_) with - | Some (imm,(existT _ _stringappend_399_ _)) => returnm (imm, build_ex _stringappend_399_) - | _ => exit tt : M ((mword 21 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 21 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_399_ _) => - (match (string_drop _stringappend_398_ (build_ex _stringappend_399_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - and_boolM (returnm ((string_startswith _stringappend_381_ "jalr") : bool)) - (let _stringappend_401_ := - string_drop _stringappend_381_ (build_ex (projT1 (string_length "jalr"))) in - match (spc_matches_prefix _stringappend_401_) with - | Some (tt,(existT _ _stringappend_402_ _)) => - let _stringappend_403_ := string_drop _stringappend_401_ (build_ex _stringappend_402_) in - match (reg_name_matches_prefix _stringappend_403_) with - | Some (rd,(existT _ _stringappend_404_ _)) => - let _stringappend_405_ := - string_drop _stringappend_403_ (build_ex _stringappend_404_) in - sep_matches_prefix _stringappend_405_ >>= fun w__32 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__32 with - | Some (tt,(existT _ _stringappend_406_ _)) => - let _stringappend_407_ := - string_drop _stringappend_405_ (build_ex _stringappend_406_) in - match (reg_name_matches_prefix _stringappend_407_) with - | Some (rs1,(existT _ _stringappend_408_ _)) => - let _stringappend_409_ := - string_drop _stringappend_407_ (build_ex _stringappend_408_) in - sep_matches_prefix _stringappend_409_ >>= fun w__33 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__33 with - | Some (tt,(existT _ _stringappend_410_ _)) => - let _stringappend_411_ := - string_drop _stringappend_409_ - (build_ex _stringappend_410_) in - if ((match (hex_bits_12_matches_prefix _stringappend_411_) with - | Some (imm,(existT _ _stringappend_412_ _)) => - match (string_drop _stringappend_411_ - (build_ex _stringappend_412_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__34 : bool => - returnm ((if (w__34) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__35 : bool => - returnm ((if (w__35) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__36 : bool => - returnm ((if (w__36) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__37 : bool => - returnm ((if (w__37) then true - else false) - : bool)) >>= fun w__38 : bool => - (if (w__38) then - let _stringappend_401_ := - string_drop _stringappend_381_ (build_ex (projT1 (string_length "jalr"))) in - (match (spc_matches_prefix _stringappend_401_) with - | Some (tt,(existT _ _stringappend_402_ _)) => - returnm (tt, build_ex _stringappend_402_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_402_ _) => - let _stringappend_403_ := string_drop _stringappend_401_ (build_ex _stringappend_402_) in - (match (reg_name_matches_prefix _stringappend_403_) with - | Some (rd,(existT _ _stringappend_404_ _)) => - returnm (rd, build_ex _stringappend_404_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_404_ _) => - let _stringappend_405_ := string_drop _stringappend_403_ (build_ex _stringappend_404_) in - sep_matches_prefix _stringappend_405_ >>= fun w__43 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__43 with - | Some (tt,(existT _ _stringappend_406_ _)) => - returnm (tt, build_ex _stringappend_406_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_406_ _) => - let _stringappend_407_ := string_drop _stringappend_405_ (build_ex _stringappend_406_) in - (match (reg_name_matches_prefix _stringappend_407_) with - | Some (rs1,(existT _ _stringappend_408_ _)) => - returnm (rs1, build_ex _stringappend_408_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_408_ _) => - let _stringappend_409_ := string_drop _stringappend_407_ (build_ex _stringappend_408_) in - sep_matches_prefix _stringappend_409_ >>= fun w__48 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__48 with - | Some (tt,(existT _ _stringappend_410_ _)) => - returnm (tt, build_ex _stringappend_410_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_410_ _) => - let _stringappend_411_ := string_drop _stringappend_409_ (build_ex _stringappend_410_) in - (match (hex_bits_12_matches_prefix _stringappend_411_) with - | Some (imm,(existT _ _stringappend_412_ _)) => - returnm (imm, build_ex _stringappend_412_) - | _ => exit tt : M ((mword 12 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_412_ _) => - (match (string_drop _stringappend_411_ (build_ex _stringappend_412_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - match (btype_mnemonic_matches_prefix _stringappend_381_) with - | Some (op,(existT _ _stringappend_414_ _)) => - let _stringappend_415_ := - string_drop _stringappend_381_ (build_ex _stringappend_414_) in - match (spc_matches_prefix _stringappend_415_) with - | Some (tt,(existT _ _stringappend_416_ _)) => - let _stringappend_417_ := - string_drop _stringappend_415_ (build_ex _stringappend_416_) in - match (reg_name_matches_prefix _stringappend_417_) with - | Some (rs1,(existT _ _stringappend_418_ _)) => - let _stringappend_419_ := - string_drop _stringappend_417_ (build_ex _stringappend_418_) in - sep_matches_prefix _stringappend_419_ >>= fun w__55 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__55 with - | Some (tt,(existT _ _stringappend_420_ _)) => - let _stringappend_421_ := - string_drop _stringappend_419_ (build_ex _stringappend_420_) in - match (reg_name_matches_prefix _stringappend_421_) with - | Some (rs2,(existT _ _stringappend_422_ _)) => - let _stringappend_423_ := - string_drop _stringappend_421_ (build_ex _stringappend_422_) in - sep_matches_prefix _stringappend_423_ >>= fun w__56 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__56 with - | Some (tt,(existT _ _stringappend_424_ _)) => - let _stringappend_425_ := - string_drop _stringappend_423_ - (build_ex _stringappend_424_) in - if ((match (hex_bits_13_matches_prefix - _stringappend_425_) with - | Some (imm,(existT _ _stringappend_426_ _)) => - match (string_drop _stringappend_425_ - (build_ex _stringappend_426_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__57 : bool => - returnm ((if (w__57) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__58 : bool => - returnm ((if (w__58) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__59 : bool => - returnm ((if (w__59) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__60 : bool => - returnm ((if (w__60) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__61 : bool => - (if (w__61) then - (match (btype_mnemonic_matches_prefix _stringappend_381_) with - | Some (op,(existT _ _stringappend_414_ _)) => - returnm (op, build_ex _stringappend_414_) - | _ => exit tt : M ((bop * {n : Z & ArithFact (n >= 0)})) - end : M ((bop * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_414_ _) => - let _stringappend_415_ := - string_drop _stringappend_381_ (build_ex _stringappend_414_) in - (match (spc_matches_prefix _stringappend_415_) with - | Some (tt,(existT _ _stringappend_416_ _)) => - returnm (tt, build_ex _stringappend_416_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_416_ _) => - let _stringappend_417_ := - string_drop _stringappend_415_ (build_ex _stringappend_416_) in - (match (reg_name_matches_prefix _stringappend_417_) with - | Some (rs1,(existT _ _stringappend_418_ _)) => - returnm (rs1, build_ex _stringappend_418_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_418_ _) => - let _stringappend_419_ := - string_drop _stringappend_417_ (build_ex _stringappend_418_) in - sep_matches_prefix _stringappend_419_ >>= fun w__68 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__68 with - | Some (tt,(existT _ _stringappend_420_ _)) => - returnm (tt, build_ex _stringappend_420_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_420_ _) => - let _stringappend_421_ := - string_drop _stringappend_419_ (build_ex _stringappend_420_) in - (match (reg_name_matches_prefix _stringappend_421_) with - | Some (rs2,(existT _ _stringappend_422_ _)) => - returnm (rs2, build_ex _stringappend_422_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs2, existT _ _stringappend_422_ _) => - let _stringappend_423_ := - string_drop _stringappend_421_ (build_ex _stringappend_422_) in - sep_matches_prefix _stringappend_423_ >>= fun w__73 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__73 with - | Some (tt,(existT _ _stringappend_424_ _)) => - returnm (tt, build_ex _stringappend_424_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_424_ _) => - let _stringappend_425_ := - string_drop _stringappend_423_ (build_ex _stringappend_424_) in - (match (hex_bits_13_matches_prefix _stringappend_425_) with - | Some (imm,(existT _ _stringappend_426_ _)) => - returnm (imm, build_ex _stringappend_426_) - | _ => exit tt : M ((mword 13 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 13 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_426_ _) => - (match (string_drop _stringappend_425_ (build_ex _stringappend_426_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - match (itype_mnemonic_matches_prefix _stringappend_381_) with - | Some (op,(existT _ _stringappend_428_ _)) => - let _stringappend_429_ := - string_drop _stringappend_381_ (build_ex _stringappend_428_) in - match (spc_matches_prefix _stringappend_429_) with - | Some (tt,(existT _ _stringappend_430_ _)) => - let _stringappend_431_ := - string_drop _stringappend_429_ (build_ex _stringappend_430_) in - match (reg_name_matches_prefix _stringappend_431_) with - | Some (rd,(existT _ _stringappend_432_ _)) => - let _stringappend_433_ := - string_drop _stringappend_431_ (build_ex _stringappend_432_) in - sep_matches_prefix _stringappend_433_ >>= fun w__80 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__80 with - | Some (tt,(existT _ _stringappend_434_ _)) => - let _stringappend_435_ := - string_drop _stringappend_433_ (build_ex _stringappend_434_) in - match (reg_name_matches_prefix _stringappend_435_) with - | Some (rs1,(existT _ _stringappend_436_ _)) => - let _stringappend_437_ := - string_drop _stringappend_435_ (build_ex _stringappend_436_) in - sep_matches_prefix _stringappend_437_ >>= fun w__81 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__81 with - | Some (tt,(existT _ _stringappend_438_ _)) => - let _stringappend_439_ := - string_drop _stringappend_437_ - (build_ex _stringappend_438_) in - if ((match (hex_bits_12_matches_prefix - _stringappend_439_) with - | Some (imm,(existT _ _stringappend_440_ _)) => - match (string_drop _stringappend_439_ - (build_ex _stringappend_440_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__82 : bool => - returnm ((if (w__82) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__83 : bool => - returnm ((if (w__83) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__84 : bool => - returnm ((if (w__84) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__85 : bool => - returnm ((if (w__85) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__86 : bool => - (if (w__86) then - (match (itype_mnemonic_matches_prefix _stringappend_381_) with - | Some (op,(existT _ _stringappend_428_ _)) => - returnm (op, build_ex _stringappend_428_) - | _ => exit tt : M ((iop * {n : Z & ArithFact (n >= 0)})) - end : M ((iop * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_428_ _) => - let _stringappend_429_ := - string_drop _stringappend_381_ (build_ex _stringappend_428_) in - (match (spc_matches_prefix _stringappend_429_) with - | Some (tt,(existT _ _stringappend_430_ _)) => - returnm (tt, build_ex _stringappend_430_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_430_ _) => - let _stringappend_431_ := - string_drop _stringappend_429_ (build_ex _stringappend_430_) in - (match (reg_name_matches_prefix _stringappend_431_) with - | Some (rd,(existT _ _stringappend_432_ _)) => - returnm (rd, build_ex _stringappend_432_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_432_ _) => - let _stringappend_433_ := - string_drop _stringappend_431_ (build_ex _stringappend_432_) in - sep_matches_prefix _stringappend_433_ >>= fun w__93 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__93 with - | Some (tt,(existT _ _stringappend_434_ _)) => - returnm (tt, build_ex _stringappend_434_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_434_ _) => - let _stringappend_435_ := - string_drop _stringappend_433_ (build_ex _stringappend_434_) in - (match (reg_name_matches_prefix _stringappend_435_) with - | Some (rs1,(existT _ _stringappend_436_ _)) => - returnm (rs1, build_ex _stringappend_436_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_436_ _) => - let _stringappend_437_ := - string_drop _stringappend_435_ (build_ex _stringappend_436_) in - sep_matches_prefix _stringappend_437_ >>= fun w__98 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__98 with - | Some (tt,(existT _ _stringappend_438_ _)) => - returnm (tt, build_ex _stringappend_438_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_438_ _) => - let _stringappend_439_ := - string_drop _stringappend_437_ (build_ex _stringappend_438_) in - (match (hex_bits_12_matches_prefix _stringappend_439_) with - | Some (imm,(existT _ _stringappend_440_ _)) => - returnm (imm, build_ex _stringappend_440_) - | _ => exit tt : M ((mword 12 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_440_ _) => - (match (string_drop _stringappend_439_ (build_ex _stringappend_440_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - match (shiftiop_mnemonic_matches_prefix _stringappend_381_) with - | Some (op,(existT _ _stringappend_442_ _)) => - let _stringappend_443_ := - string_drop _stringappend_381_ (build_ex _stringappend_442_) in - match (spc_matches_prefix _stringappend_443_) with - | Some (tt,(existT _ _stringappend_444_ _)) => - let _stringappend_445_ := - string_drop _stringappend_443_ (build_ex _stringappend_444_) in - match (reg_name_matches_prefix _stringappend_445_) with - | Some (rd,(existT _ _stringappend_446_ _)) => - let _stringappend_447_ := - string_drop _stringappend_445_ (build_ex _stringappend_446_) in - sep_matches_prefix _stringappend_447_ >>= fun w__105 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__105 with - | Some (tt,(existT _ _stringappend_448_ _)) => - let _stringappend_449_ := - string_drop _stringappend_447_ - (build_ex _stringappend_448_) in - if ((match (reg_name_matches_prefix _stringappend_449_) with - | Some (rs1,(existT _ _stringappend_450_ _)) => - let _stringappend_451_ := - string_drop _stringappend_449_ - (build_ex _stringappend_450_) in - if ((match (hex_bits_6_matches_prefix - _stringappend_451_) with - | Some - (shamt,(existT _ _stringappend_452_ _)) => - match (string_drop _stringappend_451_ - (build_ex _stringappend_452_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__106 : bool => - returnm ((if (w__106) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__107 : bool => - returnm ((if (w__107) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__108 : bool => - (if (w__108) then - (match (shiftiop_mnemonic_matches_prefix _stringappend_381_) with - | Some (op,(existT _ _stringappend_442_ _)) => - returnm (op, build_ex _stringappend_442_) - | _ => exit tt : M ((sop * {n : Z & ArithFact (n >= 0)})) - end : M ((sop * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_442_ _) => - let _stringappend_443_ := - string_drop _stringappend_381_ (build_ex _stringappend_442_) in - (match (spc_matches_prefix _stringappend_443_) with - | Some (tt,(existT _ _stringappend_444_ _)) => - returnm (tt, build_ex _stringappend_444_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_444_ _) => - let _stringappend_445_ := - string_drop _stringappend_443_ (build_ex _stringappend_444_) in - (match (reg_name_matches_prefix _stringappend_445_) with - | Some (rd,(existT _ _stringappend_446_ _)) => - returnm (rd, build_ex _stringappend_446_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_446_ _) => - let _stringappend_447_ := - string_drop _stringappend_445_ (build_ex _stringappend_446_) in - sep_matches_prefix _stringappend_447_ >>= fun w__115 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__115 with - | Some (tt,(existT _ _stringappend_448_ _)) => - returnm (tt, build_ex _stringappend_448_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_448_ _) => - let _stringappend_449_ := - string_drop _stringappend_447_ (build_ex _stringappend_448_) in - (match (reg_name_matches_prefix _stringappend_449_) with - | Some (rs1,(existT _ _stringappend_450_ _)) => - returnm (rs1, build_ex _stringappend_450_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_450_ _) => - let _stringappend_451_ := - string_drop _stringappend_449_ (build_ex _stringappend_450_) in - (match (hex_bits_6_matches_prefix _stringappend_451_) with - | Some (shamt,(existT _ _stringappend_452_ _)) => - returnm (shamt, build_ex _stringappend_452_) - | _ => exit tt : M ((mword 6 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 6 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(shamt, existT _ _stringappend_452_ _) => - (match (string_drop _stringappend_451_ (build_ex _stringappend_452_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - match (rtype_mnemonic_matches_prefix _stringappend_381_) with - | Some (op,(existT _ _stringappend_454_ _)) => - let _stringappend_455_ := - string_drop _stringappend_381_ (build_ex _stringappend_454_) in - match (spc_matches_prefix _stringappend_455_) with - | Some (tt,(existT _ _stringappend_456_ _)) => - let _stringappend_457_ := - string_drop _stringappend_455_ (build_ex _stringappend_456_) in - match (reg_name_matches_prefix _stringappend_457_) with - | Some (rd,(existT _ _stringappend_458_ _)) => - let _stringappend_459_ := - string_drop _stringappend_457_ (build_ex _stringappend_458_) in - sep_matches_prefix _stringappend_459_ >>= fun w__124 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__124 with - | Some (tt,(existT _ _stringappend_460_ _)) => - let _stringappend_461_ := - string_drop _stringappend_459_ (build_ex _stringappend_460_) in - match (reg_name_matches_prefix _stringappend_461_) with - | Some (rs1,(existT _ _stringappend_462_ _)) => - let _stringappend_463_ := - string_drop _stringappend_461_ (build_ex _stringappend_462_) in - sep_matches_prefix _stringappend_463_ >>= fun w__125 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__125 with - | Some (tt,(existT _ _stringappend_464_ _)) => - let _stringappend_465_ := - string_drop _stringappend_463_ - (build_ex _stringappend_464_) in - if ((match (reg_name_matches_prefix - _stringappend_465_) with - | Some - (rs2,(existT _ _stringappend_466_ _)) => - match (string_drop _stringappend_465_ - (build_ex _stringappend_466_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__126 : bool => - returnm ((if (w__126) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__127 : bool => - returnm ((if (w__127) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__128 : bool => - returnm ((if (w__128) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__129 : bool => - returnm ((if (w__129) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__130 : bool => - (if (w__130) then - (match (rtype_mnemonic_matches_prefix _stringappend_381_) with - | Some (op,(existT _ _stringappend_454_ _)) => - returnm (op, build_ex _stringappend_454_) - | _ => exit tt : M ((rop * {n : Z & ArithFact (n >= 0)})) - end : M ((rop * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_454_ _) => - let _stringappend_455_ := - string_drop _stringappend_381_ (build_ex _stringappend_454_) in - (match (spc_matches_prefix _stringappend_455_) with - | Some (tt,(existT _ _stringappend_456_ _)) => - returnm (tt, build_ex _stringappend_456_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_456_ _) => - let _stringappend_457_ := - string_drop _stringappend_455_ (build_ex _stringappend_456_) in - (match (reg_name_matches_prefix _stringappend_457_) with - | Some (rd,(existT _ _stringappend_458_ _)) => - returnm (rd, build_ex _stringappend_458_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_458_ _) => - let _stringappend_459_ := - string_drop _stringappend_457_ (build_ex _stringappend_458_) in - sep_matches_prefix _stringappend_459_ >>= fun w__137 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__137 with - | Some (tt,(existT _ _stringappend_460_ _)) => - returnm (tt, build_ex _stringappend_460_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_460_ _) => - let _stringappend_461_ := - string_drop _stringappend_459_ (build_ex _stringappend_460_) in - (match (reg_name_matches_prefix _stringappend_461_) with - | Some (rs1,(existT _ _stringappend_462_ _)) => - returnm (rs1, build_ex _stringappend_462_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_462_ _) => - let _stringappend_463_ := - string_drop _stringappend_461_ (build_ex _stringappend_462_) in - sep_matches_prefix _stringappend_463_ >>= fun w__142 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__142 with - | Some (tt,(existT _ _stringappend_464_ _)) => - returnm (tt, build_ex _stringappend_464_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_464_ _) => - let _stringappend_465_ := - string_drop _stringappend_463_ (build_ex _stringappend_464_) in - (match (reg_name_matches_prefix _stringappend_465_) with - | Some (rs2,(existT _ _stringappend_466_ _)) => - returnm (rs2, build_ex _stringappend_466_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs2, existT _ _stringappend_466_ _) => - (match (string_drop _stringappend_465_ (build_ex _stringappend_466_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - and_boolM (returnm ((string_startswith _stringappend_381_ "l") : bool)) - (let _stringappend_468_ := - string_drop _stringappend_381_ (build_ex (projT1 (string_length "l"))) in - match (size_mnemonic_matches_prefix _stringappend_468_) with - | Some (size,(existT _ _stringappend_469_ _)) => - let _stringappend_470_ := - string_drop _stringappend_468_ (build_ex _stringappend_469_) in - match (maybe_u_matches_prefix _stringappend_470_) with - | Some (is_unsigned,(existT _ _stringappend_471_ _)) => - let _stringappend_472_ := - string_drop _stringappend_470_ (build_ex _stringappend_471_) in - match (maybe_aq_matches_prefix _stringappend_472_) with - | Some (aq,(existT _ _stringappend_473_ _)) => - let _stringappend_474_ := - string_drop _stringappend_472_ (build_ex _stringappend_473_) in - match (maybe_rl_matches_prefix _stringappend_474_) with - | Some (rl,(existT _ _stringappend_475_ _)) => - let _stringappend_476_ := - string_drop _stringappend_474_ (build_ex _stringappend_475_) in - match (spc_matches_prefix _stringappend_476_) with - | Some (tt,(existT _ _stringappend_477_ _)) => - let _stringappend_478_ := - string_drop _stringappend_476_ - (build_ex _stringappend_477_) in - match (reg_name_matches_prefix _stringappend_478_) with - | Some (rd,(existT _ _stringappend_479_ _)) => - let _stringappend_480_ := - string_drop _stringappend_478_ - (build_ex _stringappend_479_) in - sep_matches_prefix _stringappend_480_ >>= fun w__149 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__149 with - | Some (tt,(existT _ _stringappend_481_ _)) => - let _stringappend_482_ := - string_drop _stringappend_480_ - (build_ex _stringappend_481_) in - match (reg_name_matches_prefix _stringappend_482_) with - | Some (rs1,(existT _ _stringappend_483_ _)) => - let _stringappend_484_ := - string_drop _stringappend_482_ - (build_ex _stringappend_483_) in - sep_matches_prefix _stringappend_484_ >>= fun w__150 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__150 with - | Some - (tt,(existT _ _stringappend_485_ _)) => - let _stringappend_486_ := - string_drop _stringappend_484_ - (build_ex _stringappend_485_) in - if ((match (hex_bits_12_matches_prefix - _stringappend_486_) with - | Some - (imm,(existT _ _stringappend_487_ _)) => - match (string_drop - _stringappend_486_ - (build_ex _stringappend_487_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__151 : bool => - returnm ((if (w__151) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__152 : bool => - returnm ((if (w__152) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__153 : bool => - returnm ((if (w__153) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__154 : bool => - returnm ((if (w__154) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__155 : bool => - returnm ((if (w__155) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__156 : bool => - returnm ((if (w__156) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__157 : bool => - returnm ((if (w__157) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__158 : bool => - returnm ((if (w__158) then true - else false) - : bool)) >>= fun w__159 : bool => - (if (w__159) then - let _stringappend_468_ := - string_drop _stringappend_381_ (build_ex (projT1 (string_length "l"))) in - (match (size_mnemonic_matches_prefix _stringappend_468_) with - | Some (size,(existT _ _stringappend_469_ _)) => - returnm (size, build_ex _stringappend_469_) - | _ => exit tt : M ((word_width * {n : Z & ArithFact (n >= 0)})) - end : M ((word_width * {n : Z & ArithFact (n >= 0)}))) >>= fun '(size, existT _ _stringappend_469_ _) => - let _stringappend_470_ := - string_drop _stringappend_468_ (build_ex _stringappend_469_) in - (match (maybe_u_matches_prefix _stringappend_470_) with - | Some (is_unsigned,(existT _ _stringappend_471_ _)) => - returnm (is_unsigned, build_ex _stringappend_471_) - | _ => exit tt : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(is_unsigned, existT _ _stringappend_471_ _) => - let _stringappend_472_ := - string_drop _stringappend_470_ (build_ex _stringappend_471_) in - (match (maybe_aq_matches_prefix _stringappend_472_) with - | Some (aq,(existT _ _stringappend_473_ _)) => - returnm (aq, build_ex _stringappend_473_) - | _ => exit tt : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(aq, existT _ _stringappend_473_ _) => - let _stringappend_474_ := - string_drop _stringappend_472_ (build_ex _stringappend_473_) in - (match (maybe_rl_matches_prefix _stringappend_474_) with - | Some (rl,(existT _ _stringappend_475_ _)) => - returnm (rl, build_ex _stringappend_475_) - | _ => exit tt : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rl, existT _ _stringappend_475_ _) => - let _stringappend_476_ := - string_drop _stringappend_474_ (build_ex _stringappend_475_) in - (match (spc_matches_prefix _stringappend_476_) with - | Some (tt,(existT _ _stringappend_477_ _)) => - returnm (tt, build_ex _stringappend_477_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_477_ _) => - let _stringappend_478_ := - string_drop _stringappend_476_ (build_ex _stringappend_477_) in - (match (reg_name_matches_prefix _stringappend_478_) with - | Some (rd,(existT _ _stringappend_479_ _)) => - returnm (rd, build_ex _stringappend_479_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_479_ _) => - let _stringappend_480_ := - string_drop _stringappend_478_ (build_ex _stringappend_479_) in - sep_matches_prefix _stringappend_480_ >>= fun w__172 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__172 with - | Some (tt,(existT _ _stringappend_481_ _)) => - returnm (tt, build_ex _stringappend_481_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_481_ _) => - let _stringappend_482_ := - string_drop _stringappend_480_ (build_ex _stringappend_481_) in - (match (reg_name_matches_prefix _stringappend_482_) with - | Some (rs1,(existT _ _stringappend_483_ _)) => - returnm (rs1, build_ex _stringappend_483_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_483_ _) => - let _stringappend_484_ := - string_drop _stringappend_482_ (build_ex _stringappend_483_) in - sep_matches_prefix _stringappend_484_ >>= fun w__177 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__177 with - | Some (tt,(existT _ _stringappend_485_ _)) => - returnm (tt, build_ex _stringappend_485_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_485_ _) => - let _stringappend_486_ := - string_drop _stringappend_484_ (build_ex _stringappend_485_) in - (match (hex_bits_12_matches_prefix _stringappend_486_) with - | Some (imm,(existT _ _stringappend_487_ _)) => - returnm (imm, build_ex _stringappend_487_) - | _ => exit tt : M ((mword 12 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_487_ _) => - (match (string_drop _stringappend_486_ (build_ex _stringappend_487_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - and_boolM (returnm ((string_startswith _stringappend_381_ "s") : bool)) - (let _stringappend_489_ := - string_drop _stringappend_381_ - (build_ex (projT1 (string_length "s"))) in - match (size_mnemonic_matches_prefix _stringappend_489_) with - | Some (size,(existT _ _stringappend_490_ _)) => - let _stringappend_491_ := - string_drop _stringappend_489_ (build_ex _stringappend_490_) in - match (maybe_aq_matches_prefix _stringappend_491_) with - | Some (aq,(existT _ _stringappend_492_ _)) => - let _stringappend_493_ := - string_drop _stringappend_491_ (build_ex _stringappend_492_) in - match (maybe_rl_matches_prefix _stringappend_493_) with - | Some (rl,(existT _ _stringappend_494_ _)) => - let _stringappend_495_ := - string_drop _stringappend_493_ (build_ex _stringappend_494_) in - match (spc_matches_prefix _stringappend_495_) with - | Some (tt,(existT _ _stringappend_496_ _)) => - let _stringappend_497_ := - string_drop _stringappend_495_ - (build_ex _stringappend_496_) in - match (reg_name_matches_prefix _stringappend_497_) with - | Some (rd,(existT _ _stringappend_498_ _)) => - let _stringappend_499_ := - string_drop _stringappend_497_ - (build_ex _stringappend_498_) in - sep_matches_prefix _stringappend_499_ >>= fun w__184 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__184 with - | Some (tt,(existT _ _stringappend_500_ _)) => - let _stringappend_501_ := - string_drop _stringappend_499_ - (build_ex _stringappend_500_) in - match (reg_name_matches_prefix _stringappend_501_) with - | Some (rs1,(existT _ _stringappend_502_ _)) => - let _stringappend_503_ := - string_drop _stringappend_501_ - (build_ex _stringappend_502_) in - sep_matches_prefix _stringappend_503_ >>= fun w__185 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__185 with - | Some - (tt,(existT _ _stringappend_504_ _)) => - let _stringappend_505_ := - string_drop _stringappend_503_ - (build_ex _stringappend_504_) in - if ((match (hex_bits_12_matches_prefix - _stringappend_505_) with - | Some - (imm,(existT _ _stringappend_506_ _)) => - match (string_drop - _stringappend_505_ - (build_ex _stringappend_506_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__186 : bool => - returnm ((if (w__186) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__187 : bool => - returnm ((if (w__187) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__188 : bool => - returnm ((if (w__188) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__189 : bool => - returnm ((if (w__189) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__190 : bool => - returnm ((if (w__190) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__191 : bool => - returnm ((if (w__191) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__192 : bool => - returnm ((if (w__192) then true - else false) - : bool)) >>= fun w__193 : bool => - (if (w__193) then - let _stringappend_489_ := - string_drop _stringappend_381_ - (build_ex (projT1 (string_length "s"))) in - (match (size_mnemonic_matches_prefix _stringappend_489_) with - | Some (size,(existT _ _stringappend_490_ _)) => - returnm (size, build_ex _stringappend_490_) - | _ => exit tt : M ((word_width * {n : Z & ArithFact (n >= 0)})) - end : M ((word_width * {n : Z & ArithFact (n >= 0)}))) >>= fun '(size, existT _ _stringappend_490_ _) => - let _stringappend_491_ := - string_drop _stringappend_489_ (build_ex _stringappend_490_) in - (match (maybe_aq_matches_prefix _stringappend_491_) with - | Some (aq,(existT _ _stringappend_492_ _)) => - returnm (aq, build_ex _stringappend_492_) - | _ => exit tt : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(aq, existT _ _stringappend_492_ _) => - let _stringappend_493_ := - string_drop _stringappend_491_ (build_ex _stringappend_492_) in - (match (maybe_rl_matches_prefix _stringappend_493_) with - | Some (rl,(existT _ _stringappend_494_ _)) => - returnm (rl, build_ex _stringappend_494_) - | _ => exit tt : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rl, existT _ _stringappend_494_ _) => - let _stringappend_495_ := - string_drop _stringappend_493_ (build_ex _stringappend_494_) in - (match (spc_matches_prefix _stringappend_495_) with - | Some (tt,(existT _ _stringappend_496_ _)) => - returnm (tt, build_ex _stringappend_496_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_496_ _) => - let _stringappend_497_ := - string_drop _stringappend_495_ (build_ex _stringappend_496_) in - (match (reg_name_matches_prefix _stringappend_497_) with - | Some (rd,(existT _ _stringappend_498_ _)) => - returnm (rd, build_ex _stringappend_498_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_498_ _) => - let _stringappend_499_ := - string_drop _stringappend_497_ (build_ex _stringappend_498_) in - sep_matches_prefix _stringappend_499_ >>= fun w__204 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__204 with - | Some (tt,(existT _ _stringappend_500_ _)) => - returnm (tt, build_ex _stringappend_500_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_500_ _) => - let _stringappend_501_ := - string_drop _stringappend_499_ (build_ex _stringappend_500_) in - (match (reg_name_matches_prefix _stringappend_501_) with - | Some (rs1,(existT _ _stringappend_502_ _)) => - returnm (rs1, build_ex _stringappend_502_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_502_ _) => - let _stringappend_503_ := - string_drop _stringappend_501_ (build_ex _stringappend_502_) in - sep_matches_prefix _stringappend_503_ >>= fun w__209 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__209 with - | Some (tt,(existT _ _stringappend_504_ _)) => - returnm (tt, build_ex _stringappend_504_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_504_ _) => - let _stringappend_505_ := - string_drop _stringappend_503_ (build_ex _stringappend_504_) in - (match (hex_bits_12_matches_prefix _stringappend_505_) with - | Some (imm,(existT _ _stringappend_506_ _)) => - returnm (imm, build_ex _stringappend_506_) - | _ => exit tt : M ((mword 12 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_506_ _) => - (match (string_drop _stringappend_505_ (build_ex _stringappend_506_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - and_boolM - (returnm ((string_startswith _stringappend_381_ "addiw") - : bool)) - (let _stringappend_508_ := - string_drop _stringappend_381_ - (build_ex (projT1 (string_length "addiw"))) in - match (spc_matches_prefix _stringappend_508_) with - | Some (tt,(existT _ _stringappend_509_ _)) => - let _stringappend_510_ := - string_drop _stringappend_508_ (build_ex _stringappend_509_) in - match (reg_name_matches_prefix _stringappend_510_) with - | Some (rd,(existT _ _stringappend_511_ _)) => - let _stringappend_512_ := - string_drop _stringappend_510_ (build_ex _stringappend_511_) in - sep_matches_prefix _stringappend_512_ >>= fun w__216 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__216 with - | Some (tt,(existT _ _stringappend_513_ _)) => - let _stringappend_514_ := - string_drop _stringappend_512_ - (build_ex _stringappend_513_) in - match (reg_name_matches_prefix _stringappend_514_) with - | Some (rs1,(existT _ _stringappend_515_ _)) => - let _stringappend_516_ := - string_drop _stringappend_514_ - (build_ex _stringappend_515_) in - sep_matches_prefix _stringappend_516_ >>= fun w__217 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__217 with - | Some - (tt,(existT _ _stringappend_517_ _)) => - let _stringappend_518_ := - string_drop _stringappend_516_ - (build_ex _stringappend_517_) in - if ((match (hex_bits_12_matches_prefix - _stringappend_518_) with - | Some - (imm,(existT _ _stringappend_519_ _)) => - match (string_drop - _stringappend_518_ - (build_ex _stringappend_519_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__218 : bool => - returnm ((if (w__218) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__219 : bool => - returnm ((if (w__219) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__220 : bool => - returnm ((if (w__220) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__221 : bool => - returnm ((if (w__221) then true - else false) - : bool)) >>= fun w__222 : bool => - (if (w__222) then - let _stringappend_508_ := - string_drop _stringappend_381_ - (build_ex (projT1 (string_length "addiw"))) in - (match (spc_matches_prefix _stringappend_508_) with - | Some (tt,(existT _ _stringappend_509_ _)) => - returnm (tt, build_ex _stringappend_509_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_509_ _) => - let _stringappend_510_ := - string_drop _stringappend_508_ (build_ex _stringappend_509_) in - (match (reg_name_matches_prefix _stringappend_510_) with - | Some (rd,(existT _ _stringappend_511_ _)) => - returnm (rd, build_ex _stringappend_511_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_511_ _) => - let _stringappend_512_ := - string_drop _stringappend_510_ (build_ex _stringappend_511_) in - sep_matches_prefix _stringappend_512_ >>= fun w__227 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__227 with - | Some (tt,(existT _ _stringappend_513_ _)) => - returnm (tt, build_ex _stringappend_513_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_513_ _) => - let _stringappend_514_ := - string_drop _stringappend_512_ (build_ex _stringappend_513_) in - (match (reg_name_matches_prefix _stringappend_514_) with - | Some (rs1,(existT _ _stringappend_515_ _)) => - returnm (rs1, build_ex _stringappend_515_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_515_ _) => - let _stringappend_516_ := - string_drop _stringappend_514_ (build_ex _stringappend_515_) in - sep_matches_prefix _stringappend_516_ >>= fun w__232 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__232 with - | Some (tt,(existT _ _stringappend_517_ _)) => - returnm (tt, build_ex _stringappend_517_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_517_ _) => - let _stringappend_518_ := - string_drop _stringappend_516_ (build_ex _stringappend_517_) in - (match (hex_bits_12_matches_prefix _stringappend_518_) with - | Some (imm,(existT _ _stringappend_519_ _)) => - returnm (imm, build_ex _stringappend_519_) - | _ => exit tt : M ((mword 12 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_519_ _) => - (match (string_drop _stringappend_518_ - (build_ex _stringappend_519_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - match (shiftw_mnemonic_matches_prefix _stringappend_381_) with - | Some (op,(existT _ _stringappend_521_ _)) => - let _stringappend_522_ := - string_drop _stringappend_381_ (build_ex _stringappend_521_) in - match (spc_matches_prefix _stringappend_522_) with - | Some (tt,(existT _ _stringappend_523_ _)) => - let _stringappend_524_ := - string_drop _stringappend_522_ - (build_ex _stringappend_523_) in - match (reg_name_matches_prefix _stringappend_524_) with - | Some (rd,(existT _ _stringappend_525_ _)) => - let _stringappend_526_ := - string_drop _stringappend_524_ - (build_ex _stringappend_525_) in - sep_matches_prefix _stringappend_526_ >>= fun w__239 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__239 with - | Some (tt,(existT _ _stringappend_527_ _)) => - let _stringappend_528_ := - string_drop _stringappend_526_ - (build_ex _stringappend_527_) in - match (reg_name_matches_prefix _stringappend_528_) with - | Some (rs1,(existT _ _stringappend_529_ _)) => - let _stringappend_530_ := - string_drop _stringappend_528_ - (build_ex _stringappend_529_) in - sep_matches_prefix _stringappend_530_ >>= fun w__240 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__240 with - | Some - (tt,(existT _ _stringappend_531_ _)) => - let _stringappend_532_ := - string_drop _stringappend_530_ - (build_ex _stringappend_531_) in - if ((match (hex_bits_5_matches_prefix - _stringappend_532_) with - | Some - (shamt,(existT _ _stringappend_533_ _)) => - match (string_drop - _stringappend_532_ - (build_ex _stringappend_533_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__241 : bool => - returnm ((if (w__241) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__242 : bool => - returnm ((if (w__242) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__243 : bool => - returnm ((if (w__243) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__244 : bool => - returnm ((if (w__244) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__245 : bool => - (if (w__245) then - (match (shiftw_mnemonic_matches_prefix _stringappend_381_) with - | Some (op,(existT _ _stringappend_521_ _)) => - returnm (op, build_ex _stringappend_521_) - | _ => exit tt : M ((sop * {n : Z & ArithFact (n >= 0)})) - end : M ((sop * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_521_ _) => - let _stringappend_522_ := - string_drop _stringappend_381_ (build_ex _stringappend_521_) in - (match (spc_matches_prefix _stringappend_522_) with - | Some (tt,(existT _ _stringappend_523_ _)) => - returnm (tt, build_ex _stringappend_523_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_523_ _) => - let _stringappend_524_ := - string_drop _stringappend_522_ (build_ex _stringappend_523_) in - (match (reg_name_matches_prefix _stringappend_524_) with - | Some (rd,(existT _ _stringappend_525_ _)) => - returnm (rd, build_ex _stringappend_525_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_525_ _) => - let _stringappend_526_ := - string_drop _stringappend_524_ (build_ex _stringappend_525_) in - sep_matches_prefix _stringappend_526_ >>= fun w__252 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__252 with - | Some (tt,(existT _ _stringappend_527_ _)) => - returnm (tt, build_ex _stringappend_527_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_527_ _) => - let _stringappend_528_ := - string_drop _stringappend_526_ (build_ex _stringappend_527_) in - (match (reg_name_matches_prefix _stringappend_528_) with - | Some (rs1,(existT _ _stringappend_529_ _)) => - returnm (rs1, build_ex _stringappend_529_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_529_ _) => - let _stringappend_530_ := - string_drop _stringappend_528_ (build_ex _stringappend_529_) in - sep_matches_prefix _stringappend_530_ >>= fun w__257 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__257 with - | Some (tt,(existT _ _stringappend_531_ _)) => - returnm (tt, build_ex _stringappend_531_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_531_ _) => - let _stringappend_532_ := - string_drop _stringappend_530_ (build_ex _stringappend_531_) in - (match (hex_bits_5_matches_prefix _stringappend_532_) with - | Some (shamt,(existT _ _stringappend_533_ _)) => - returnm (shamt, build_ex _stringappend_533_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(shamt, existT _ _stringappend_533_ _) => - (match (string_drop _stringappend_532_ - (build_ex _stringappend_533_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - match (rtypew_mnemonic_matches_prefix _stringappend_381_) with - | Some (op,(existT _ _stringappend_535_ _)) => - let _stringappend_536_ := - string_drop _stringappend_381_ - (build_ex _stringappend_535_) in - match (spc_matches_prefix _stringappend_536_) with - | Some (tt,(existT _ _stringappend_537_ _)) => - let _stringappend_538_ := - string_drop _stringappend_536_ - (build_ex _stringappend_537_) in - match (reg_name_matches_prefix _stringappend_538_) with - | Some (rd,(existT _ _stringappend_539_ _)) => - let _stringappend_540_ := - string_drop _stringappend_538_ - (build_ex _stringappend_539_) in - sep_matches_prefix _stringappend_540_ >>= fun w__264 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__264 with - | Some (tt,(existT _ _stringappend_541_ _)) => - let _stringappend_542_ := - string_drop _stringappend_540_ - (build_ex _stringappend_541_) in - match (reg_name_matches_prefix _stringappend_542_) with - | Some (rs1,(existT _ _stringappend_543_ _)) => - let _stringappend_544_ := - string_drop _stringappend_542_ - (build_ex _stringappend_543_) in - sep_matches_prefix _stringappend_544_ >>= fun w__265 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__265 with - | Some - (tt,(existT _ _stringappend_545_ _)) => - let _stringappend_546_ := - string_drop - _stringappend_544_ - (build_ex _stringappend_545_) in - if ((match (reg_name_matches_prefix - _stringappend_546_) with - | Some - (rs2,(existT _ _stringappend_547_ _)) => - match (string_drop - _stringappend_546_ - (build_ex _stringappend_547_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__266 : bool => - returnm ((if (w__266) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__267 : bool => - returnm ((if (w__267) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__268 : bool => - returnm ((if (w__268) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__269 : bool => - returnm ((if (w__269) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__270 : bool => - (if (w__270) then - (match (rtypew_mnemonic_matches_prefix _stringappend_381_) with - | Some (op,(existT _ _stringappend_535_ _)) => - returnm (op, build_ex _stringappend_535_) - | _ => exit tt : M ((ropw * {n : Z & ArithFact (n >= 0)})) - end : M ((ropw * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_535_ _) => - let _stringappend_536_ := - string_drop _stringappend_381_ - (build_ex _stringappend_535_) in - (match (spc_matches_prefix _stringappend_536_) with - | Some (tt,(existT _ _stringappend_537_ _)) => - returnm (tt, build_ex _stringappend_537_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_537_ _) => - let _stringappend_538_ := - string_drop _stringappend_536_ - (build_ex _stringappend_537_) in - (match (reg_name_matches_prefix _stringappend_538_) with - | Some (rd,(existT _ _stringappend_539_ _)) => - returnm (rd, build_ex _stringappend_539_) - | _ => - exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_539_ _) => - let _stringappend_540_ := - string_drop _stringappend_538_ - (build_ex _stringappend_539_) in - sep_matches_prefix _stringappend_540_ >>= fun w__277 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__277 with - | Some (tt,(existT _ _stringappend_541_ _)) => - returnm (tt, build_ex _stringappend_541_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_541_ _) => - let _stringappend_542_ := - string_drop _stringappend_540_ - (build_ex _stringappend_541_) in - (match (reg_name_matches_prefix _stringappend_542_) with - | Some (rs1,(existT _ _stringappend_543_ _)) => - returnm (rs1, build_ex _stringappend_543_) - | _ => - exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_543_ _) => - let _stringappend_544_ := - string_drop _stringappend_542_ - (build_ex _stringappend_543_) in - sep_matches_prefix _stringappend_544_ >>= fun w__282 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__282 with - | Some (tt,(existT _ _stringappend_545_ _)) => - returnm (tt, build_ex _stringappend_545_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_545_ _) => - let _stringappend_546_ := - string_drop _stringappend_544_ - (build_ex _stringappend_545_) in - (match (reg_name_matches_prefix _stringappend_546_) with - | Some (rs2,(existT _ _stringappend_547_ _)) => - returnm (rs2, build_ex _stringappend_547_) - | _ => - exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs2, existT _ _stringappend_547_ _) => - (match (string_drop _stringappend_546_ - (build_ex _stringappend_547_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - match (shiftiwop_mnemonic_matches_prefix _stringappend_381_) with - | Some (op,(existT _ _stringappend_549_ _)) => - let _stringappend_550_ := - string_drop _stringappend_381_ - (build_ex _stringappend_549_) in - match (spc_matches_prefix _stringappend_550_) with - | Some (tt,(existT _ _stringappend_551_ _)) => - let _stringappend_552_ := - string_drop _stringappend_550_ - (build_ex _stringappend_551_) in - match (reg_name_matches_prefix _stringappend_552_) with - | Some (rd,(existT _ _stringappend_553_ _)) => - let _stringappend_554_ := - string_drop _stringappend_552_ - (build_ex _stringappend_553_) in - sep_matches_prefix _stringappend_554_ >>= fun w__289 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__289 with - | Some - (tt,(existT _ _stringappend_555_ _)) => - let _stringappend_556_ := - string_drop _stringappend_554_ - (build_ex _stringappend_555_) in - if ((match (reg_name_matches_prefix - _stringappend_556_) with - | Some - (rs1,(existT _ _stringappend_557_ _)) => - let _stringappend_558_ := - string_drop - _stringappend_556_ - (build_ex _stringappend_557_) in - if ((match (hex_bits_5_matches_prefix - _stringappend_558_) with - | Some - (shamt,(existT _ _stringappend_559_ _)) => - match (string_drop - _stringappend_558_ - (build_ex _stringappend_559_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__290 : bool => - returnm ((if (w__290) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__291 : bool => - returnm ((if (w__291) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__292 : bool => - (if (w__292) then - (match (shiftiwop_mnemonic_matches_prefix - _stringappend_381_) with - | Some (op,(existT _ _stringappend_549_ _)) => - returnm (op, build_ex _stringappend_549_) - | _ => - exit tt : M ((sopw * {n : Z & ArithFact (n >= 0)})) - end : M ((sopw * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_549_ _) => - let _stringappend_550_ := - string_drop _stringappend_381_ - (build_ex _stringappend_549_) in - (match (spc_matches_prefix _stringappend_550_) with - | Some (tt,(existT _ _stringappend_551_ _)) => - returnm (tt, build_ex _stringappend_551_) - | _ => - exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_551_ _) => - let _stringappend_552_ := - string_drop _stringappend_550_ - (build_ex _stringappend_551_) in - (match (reg_name_matches_prefix _stringappend_552_) with - | Some (rd,(existT _ _stringappend_553_ _)) => - returnm (rd, build_ex _stringappend_553_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_553_ _) => - let _stringappend_554_ := - string_drop _stringappend_552_ - (build_ex _stringappend_553_) in - sep_matches_prefix _stringappend_554_ >>= fun w__299 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__299 with - | Some (tt,(existT _ _stringappend_555_ _)) => - returnm (tt, build_ex _stringappend_555_) - | _ => - exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_555_ _) => - let _stringappend_556_ := - string_drop _stringappend_554_ - (build_ex _stringappend_555_) in - (match (reg_name_matches_prefix _stringappend_556_) with - | Some (rs1,(existT _ _stringappend_557_ _)) => - returnm (rs1, build_ex _stringappend_557_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_557_ _) => - let _stringappend_558_ := - string_drop _stringappend_556_ - (build_ex _stringappend_557_) in - (match (hex_bits_5_matches_prefix _stringappend_558_) with - | Some (shamt,(existT _ _stringappend_559_ _)) => - returnm (shamt, build_ex _stringappend_559_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(shamt, existT _ _stringappend_559_ _) => - (match (string_drop _stringappend_558_ - (build_ex _stringappend_559_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - match (mul_mnemonic_matches_prefix _stringappend_381_) with - | Some - ((high, signed1, signed2),(existT _ _stringappend_561_ _)) => - let _stringappend_562_ := - string_drop _stringappend_381_ - (build_ex _stringappend_561_) in - match (spc_matches_prefix _stringappend_562_) with - | Some (tt,(existT _ _stringappend_563_ _)) => - let _stringappend_564_ := - string_drop _stringappend_562_ - (build_ex _stringappend_563_) in - match (reg_name_matches_prefix _stringappend_564_) with - | Some (rd,(existT _ _stringappend_565_ _)) => - let _stringappend_566_ := - string_drop _stringappend_564_ - (build_ex _stringappend_565_) in - sep_matches_prefix _stringappend_566_ >>= fun w__308 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__308 with - | Some (tt,(existT _ _stringappend_567_ _)) => - let _stringappend_568_ := - string_drop _stringappend_566_ - (build_ex _stringappend_567_) in - match (reg_name_matches_prefix - _stringappend_568_) with - | Some (rs1,(existT _ _stringappend_569_ _)) => - let _stringappend_570_ := - string_drop _stringappend_568_ - (build_ex _stringappend_569_) in - sep_matches_prefix _stringappend_570_ >>= fun w__309 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__309 with - | Some - (tt,(existT _ _stringappend_571_ _)) => - let _stringappend_572_ := - string_drop - _stringappend_570_ - (build_ex _stringappend_571_) in - if ((match (reg_name_matches_prefix - _stringappend_572_) with - | Some - (rs2,(existT _ _stringappend_573_ _)) => - match (string_drop - _stringappend_572_ - (build_ex _stringappend_573_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__310 : bool => - returnm ((if (w__310) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__311 : bool => - returnm ((if (w__311) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__312 : bool => - returnm ((if (w__312) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__313 : bool => - returnm ((if (w__313) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__314 : bool => - (if (w__314) then - (match (mul_mnemonic_matches_prefix _stringappend_381_) with - | Some - ((high, signed1, signed2),(existT _ _stringappend_561_ _)) => - returnm ((high, signed1, signed2), build_ex _stringappend_561_) - | _ => - exit tt - : M (((bool * bool * bool) * {n : Z & ArithFact (n >= - 0)})) - end : M (((bool * bool * bool) * {n : Z & ArithFact (n >= - 0)}))) >>= fun '((high, signed1, signed2), existT _ _stringappend_561_ _) => - let _stringappend_562_ := - string_drop _stringappend_381_ - (build_ex _stringappend_561_) in - (match (spc_matches_prefix _stringappend_562_) with - | Some (tt,(existT _ _stringappend_563_ _)) => - returnm (tt, build_ex _stringappend_563_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_563_ _) => - let _stringappend_564_ := - string_drop _stringappend_562_ - (build_ex _stringappend_563_) in - (match (reg_name_matches_prefix _stringappend_564_) with - | Some (rd,(existT _ _stringappend_565_ _)) => - returnm (rd, build_ex _stringappend_565_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_565_ _) => - let _stringappend_566_ := - string_drop _stringappend_564_ - (build_ex _stringappend_565_) in - sep_matches_prefix _stringappend_566_ >>= fun w__321 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__321 with - | Some (tt,(existT _ _stringappend_567_ _)) => - returnm (tt, build_ex _stringappend_567_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_567_ _) => - let _stringappend_568_ := - string_drop _stringappend_566_ - (build_ex _stringappend_567_) in - (match (reg_name_matches_prefix _stringappend_568_) with - | Some (rs1,(existT _ _stringappend_569_ _)) => - returnm (rs1, build_ex _stringappend_569_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_569_ _) => - let _stringappend_570_ := - string_drop _stringappend_568_ - (build_ex _stringappend_569_) in - sep_matches_prefix _stringappend_570_ >>= fun w__326 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__326 with - | Some (tt,(existT _ _stringappend_571_ _)) => - returnm (tt, build_ex _stringappend_571_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_571_ _) => - let _stringappend_572_ := - string_drop _stringappend_570_ - (build_ex _stringappend_571_) in - (match (reg_name_matches_prefix _stringappend_572_) with - | Some (rs2,(existT _ _stringappend_573_ _)) => - returnm (rs2, build_ex _stringappend_573_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs2, existT _ _stringappend_573_ _) => - (match (string_drop _stringappend_572_ - (build_ex _stringappend_573_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - and_boolM - (returnm ((string_startswith _stringappend_381_ "div") - : bool)) - (let _stringappend_575_ := - string_drop _stringappend_381_ - (build_ex (projT1 (string_length "div"))) in - match (maybe_not_u_matches_prefix _stringappend_575_) with - | Some (s,(existT _ _stringappend_576_ _)) => - let _stringappend_577_ := - string_drop _stringappend_575_ - (build_ex _stringappend_576_) in - match (spc_matches_prefix _stringappend_577_) with - | Some (tt,(existT _ _stringappend_578_ _)) => - let _stringappend_579_ := - string_drop _stringappend_577_ - (build_ex _stringappend_578_) in - match (reg_name_matches_prefix - _stringappend_579_) with - | Some (rd,(existT _ _stringappend_580_ _)) => - let _stringappend_581_ := - string_drop _stringappend_579_ - (build_ex _stringappend_580_) in - sep_matches_prefix _stringappend_581_ >>= fun w__333 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__333 with - | Some (tt,(existT _ _stringappend_582_ _)) => - let _stringappend_583_ := - string_drop _stringappend_581_ - (build_ex _stringappend_582_) in - match (reg_name_matches_prefix - _stringappend_583_) with - | Some - (rs1,(existT _ _stringappend_584_ _)) => - let _stringappend_585_ := - string_drop _stringappend_583_ - (build_ex _stringappend_584_) in - sep_matches_prefix _stringappend_585_ >>= fun w__334 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__334 with - | Some - (tt,(existT _ _stringappend_586_ _)) => - let _stringappend_587_ := - string_drop - _stringappend_585_ - (build_ex _stringappend_586_) in - if ((match (reg_name_matches_prefix - _stringappend_587_) with - | Some - (rs2,(existT _ _stringappend_588_ _)) => - match (string_drop - _stringappend_587_ - (build_ex _stringappend_588_)) with - | "" => true - | _ => false - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__335 : bool => - returnm ((if (w__335) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__336 : bool => - returnm ((if (w__336) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__337 : bool => - returnm ((if (w__337) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__338 : bool => - returnm ((if (w__338) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__339 : bool => - returnm ((if (w__339) then true - else false) - : bool)) >>= fun w__340 : bool => - (if (w__340) then - let _stringappend_575_ := - string_drop _stringappend_381_ - (build_ex (projT1 (string_length "div"))) in - (match (maybe_not_u_matches_prefix - _stringappend_575_) with - | Some (s,(existT _ _stringappend_576_ _)) => - returnm (s, build_ex _stringappend_576_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(s, existT _ _stringappend_576_ _) => - let _stringappend_577_ := - string_drop _stringappend_575_ - (build_ex _stringappend_576_) in - (match (spc_matches_prefix _stringappend_577_) with - | Some (tt,(existT _ _stringappend_578_ _)) => - returnm (tt, build_ex _stringappend_578_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_578_ _) => - let _stringappend_579_ := - string_drop _stringappend_577_ - (build_ex _stringappend_578_) in - (match (reg_name_matches_prefix _stringappend_579_) with - | Some (rd,(existT _ _stringappend_580_ _)) => - returnm (rd, build_ex _stringappend_580_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_580_ _) => - let _stringappend_581_ := - string_drop _stringappend_579_ - (build_ex _stringappend_580_) in - sep_matches_prefix _stringappend_581_ >>= fun w__347 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__347 with - | Some (tt,(existT _ _stringappend_582_ _)) => - returnm (tt, build_ex _stringappend_582_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_582_ _) => - let _stringappend_583_ := - string_drop _stringappend_581_ - (build_ex _stringappend_582_) in - (match (reg_name_matches_prefix _stringappend_583_) with - | Some (rs1,(existT _ _stringappend_584_ _)) => - returnm (rs1, build_ex _stringappend_584_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_584_ _) => - let _stringappend_585_ := - string_drop _stringappend_583_ - (build_ex _stringappend_584_) in - sep_matches_prefix _stringappend_585_ >>= fun w__352 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__352 with - | Some (tt,(existT _ _stringappend_586_ _)) => - returnm (tt, build_ex _stringappend_586_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_586_ _) => - let _stringappend_587_ := - string_drop _stringappend_585_ - (build_ex _stringappend_586_) in - (match (reg_name_matches_prefix _stringappend_587_) with - | Some (rs2,(existT _ _stringappend_588_ _)) => - returnm (rs2, build_ex _stringappend_588_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs2, existT _ _stringappend_588_ _) => - (match (string_drop _stringappend_587_ - (build_ex _stringappend_588_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - and_boolM - (returnm ((string_startswith _stringappend_381_ - "rem") - : bool)) - (let _stringappend_590_ := - string_drop _stringappend_381_ - (build_ex (projT1 (string_length "rem"))) in - match (maybe_not_u_matches_prefix - _stringappend_590_) with - | Some (s,(existT _ _stringappend_591_ _)) => - let _stringappend_592_ := - string_drop _stringappend_590_ - (build_ex _stringappend_591_) in - match (spc_matches_prefix _stringappend_592_) with - | Some (tt,(existT _ _stringappend_593_ _)) => - let _stringappend_594_ := - string_drop _stringappend_592_ - (build_ex _stringappend_593_) in - match (reg_name_matches_prefix - _stringappend_594_) with - | Some (rd,(existT _ _stringappend_595_ _)) => - let _stringappend_596_ := - string_drop _stringappend_594_ - (build_ex _stringappend_595_) in - sep_matches_prefix _stringappend_596_ >>= fun w__359 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__359 with - | Some - (tt,(existT _ _stringappend_597_ _)) => - let _stringappend_598_ := - string_drop _stringappend_596_ - (build_ex _stringappend_597_) in - match (reg_name_matches_prefix - _stringappend_598_) with - | Some - (rs1,(existT _ _stringappend_599_ _)) => - let _stringappend_600_ := - string_drop _stringappend_598_ - (build_ex _stringappend_599_) in - sep_matches_prefix - _stringappend_600_ >>= fun w__360 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__360 with - | Some - (tt,(existT _ _stringappend_601_ _)) => - let _stringappend_602_ := - string_drop - _stringappend_600_ - (build_ex _stringappend_601_) in - if ((match (reg_name_matches_prefix - _stringappend_602_) with - | Some - (rs2,(existT _ _stringappend_603_ _)) => - match (string_drop - _stringappend_602_ - (build_ex _stringappend_603_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__361 : bool => - returnm ((if (w__361) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__362 : bool => - returnm ((if (w__362) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__363 : bool => - returnm ((if (w__363) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__364 : bool => - returnm ((if (w__364) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__365 : bool => - returnm ((if (w__365) then true - else false) - : bool)) >>= fun w__366 : bool => - (if (w__366) then - let _stringappend_590_ := - string_drop _stringappend_381_ - (build_ex (projT1 (string_length "rem"))) in - (match (maybe_not_u_matches_prefix - _stringappend_590_) with - | Some (s,(existT _ _stringappend_591_ _)) => - returnm (s, build_ex _stringappend_591_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(s, existT _ _stringappend_591_ _) => - let _stringappend_592_ := - string_drop _stringappend_590_ - (build_ex _stringappend_591_) in - (match (spc_matches_prefix _stringappend_592_) with - | Some (tt,(existT _ _stringappend_593_ _)) => - returnm (tt, build_ex _stringappend_593_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_593_ _) => - let _stringappend_594_ := - string_drop _stringappend_592_ - (build_ex _stringappend_593_) in - (match (reg_name_matches_prefix - _stringappend_594_) with - | Some (rd,(existT _ _stringappend_595_ _)) => - returnm (rd, build_ex _stringappend_595_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_595_ _) => - let _stringappend_596_ := - string_drop _stringappend_594_ - (build_ex _stringappend_595_) in - sep_matches_prefix _stringappend_596_ >>= fun w__373 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__373 with - | Some (tt,(existT _ _stringappend_597_ _)) => - returnm (tt, build_ex _stringappend_597_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_597_ _) => - let _stringappend_598_ := - string_drop _stringappend_596_ - (build_ex _stringappend_597_) in - (match (reg_name_matches_prefix - _stringappend_598_) with - | Some (rs1,(existT _ _stringappend_599_ _)) => - returnm (rs1, build_ex _stringappend_599_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_599_ _) => - let _stringappend_600_ := - string_drop _stringappend_598_ - (build_ex _stringappend_599_) in - sep_matches_prefix _stringappend_600_ >>= fun w__378 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__378 with - | Some (tt,(existT _ _stringappend_601_ _)) => - returnm (tt, build_ex _stringappend_601_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_601_ _) => - let _stringappend_602_ := - string_drop _stringappend_600_ - (build_ex _stringappend_601_) in - (match (reg_name_matches_prefix - _stringappend_602_) with - | Some (rs2,(existT _ _stringappend_603_ _)) => - returnm (rs2, build_ex _stringappend_603_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs2, existT _ _stringappend_603_ _) => - (match (string_drop _stringappend_602_ - (build_ex _stringappend_603_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - and_boolM - (returnm ((string_startswith _stringappend_381_ - "mulw") - : bool)) - (let _stringappend_605_ := - string_drop _stringappend_381_ - (build_ex (projT1 (string_length "mulw"))) in - match (spc_matches_prefix _stringappend_605_) with - | Some (tt,(existT _ _stringappend_606_ _)) => - let _stringappend_607_ := - string_drop _stringappend_605_ - (build_ex _stringappend_606_) in - match (reg_name_matches_prefix - _stringappend_607_) with - | Some (rd,(existT _ _stringappend_608_ _)) => - let _stringappend_609_ := - string_drop _stringappend_607_ - (build_ex _stringappend_608_) in - sep_matches_prefix _stringappend_609_ >>= fun w__385 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__385 with - | Some - (tt,(existT _ _stringappend_610_ _)) => - let _stringappend_611_ := - string_drop _stringappend_609_ - (build_ex _stringappend_610_) in - match (reg_name_matches_prefix - _stringappend_611_) with - | Some - (rs1,(existT _ _stringappend_612_ _)) => - let _stringappend_613_ := - string_drop _stringappend_611_ - (build_ex _stringappend_612_) in - sep_matches_prefix - _stringappend_613_ >>= fun w__386 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__386 with - | Some - (tt,(existT _ _stringappend_614_ _)) => - let _stringappend_615_ := - string_drop - _stringappend_613_ - (build_ex _stringappend_614_) in - if ((match (reg_name_matches_prefix - _stringappend_615_) with - | Some - (rs2,(existT _ _stringappend_616_ _)) => - match (string_drop - _stringappend_615_ - (build_ex _stringappend_616_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__387 : bool => - returnm ((if (w__387) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__388 : bool => - returnm ((if (w__388) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__389 : bool => - returnm ((if (w__389) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__390 : bool => - returnm ((if (w__390) then true - else false) - : bool)) >>= fun w__391 : bool => - (if (w__391) then - let _stringappend_605_ := - string_drop _stringappend_381_ - (build_ex (projT1 (string_length "mulw"))) in - (match (spc_matches_prefix _stringappend_605_) with - | Some (tt,(existT _ _stringappend_606_ _)) => - returnm (tt, build_ex _stringappend_606_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_606_ _) => - let _stringappend_607_ := - string_drop _stringappend_605_ - (build_ex _stringappend_606_) in - (match (reg_name_matches_prefix - _stringappend_607_) with - | Some (rd,(existT _ _stringappend_608_ _)) => - returnm (rd, build_ex _stringappend_608_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_608_ _) => - let _stringappend_609_ := - string_drop _stringappend_607_ - (build_ex _stringappend_608_) in - sep_matches_prefix _stringappend_609_ >>= fun w__396 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__396 with - | Some (tt,(existT _ _stringappend_610_ _)) => - returnm (tt, build_ex _stringappend_610_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_610_ _) => - let _stringappend_611_ := - string_drop _stringappend_609_ - (build_ex _stringappend_610_) in - (match (reg_name_matches_prefix - _stringappend_611_) with - | Some (rs1,(existT _ _stringappend_612_ _)) => - returnm (rs1, build_ex _stringappend_612_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_612_ _) => - let _stringappend_613_ := - string_drop _stringappend_611_ - (build_ex _stringappend_612_) in - sep_matches_prefix _stringappend_613_ >>= fun w__401 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__401 with - | Some (tt,(existT _ _stringappend_614_ _)) => - returnm (tt, build_ex _stringappend_614_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_614_ _) => - let _stringappend_615_ := - string_drop _stringappend_613_ - (build_ex _stringappend_614_) in - (match (reg_name_matches_prefix - _stringappend_615_) with - | Some (rs2,(existT _ _stringappend_616_ _)) => - returnm (rs2, build_ex _stringappend_616_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs2, existT _ _stringappend_616_ _) => - (match (string_drop _stringappend_615_ - (build_ex _stringappend_616_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - and_boolM - (returnm ((string_startswith - _stringappend_381_ "div") - : bool)) - (let _stringappend_618_ := - string_drop _stringappend_381_ - (build_ex (projT1 (string_length "div"))) in - match (maybe_not_u_matches_prefix - _stringappend_618_) with - | Some (s,(existT _ _stringappend_619_ _)) => - let _stringappend_620_ := - string_drop _stringappend_618_ - (build_ex _stringappend_619_) in - and_boolM - (returnm ((string_startswith - _stringappend_620_ "w") - : bool)) - (let _stringappend_621_ := - string_drop _stringappend_620_ - (build_ex (projT1 (string_length - "w"))) in - match (spc_matches_prefix - _stringappend_621_) with - | Some - (tt,(existT _ _stringappend_622_ _)) => - let _stringappend_623_ := - string_drop _stringappend_621_ - (build_ex _stringappend_622_) in - match (reg_name_matches_prefix - _stringappend_623_) with - | Some - (rd,(existT _ _stringappend_624_ _)) => - let _stringappend_625_ := - string_drop _stringappend_623_ - (build_ex _stringappend_624_) in - sep_matches_prefix - _stringappend_625_ >>= fun w__408 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__408 with - | Some - (tt,(existT _ _stringappend_626_ _)) => - let _stringappend_627_ := - string_drop - _stringappend_625_ - (build_ex _stringappend_626_) in - match (reg_name_matches_prefix - _stringappend_627_) with - | Some - (rs1,(existT _ _stringappend_628_ _)) => - let _stringappend_629_ := - string_drop - _stringappend_627_ - (build_ex _stringappend_628_) in - sep_matches_prefix - _stringappend_629_ >>= fun w__409 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__409 with - | Some - (tt,(existT _ _stringappend_630_ _)) => - let _stringappend_631_ := - string_drop - _stringappend_629_ - (build_ex _stringappend_630_) in - if ((match (reg_name_matches_prefix - _stringappend_631_) with - | Some - (rs2,(existT _ _stringappend_632_ _)) => - match (string_drop - _stringappend_631_ - (build_ex _stringappend_632_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__410 : bool => - returnm ((if (w__410) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__411 : bool => - returnm ((if (w__411) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__412 : bool => - returnm ((if (w__412) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__413 : bool => - returnm ((if (w__413) then true - else false) - : bool)) >>= fun w__414 : bool => - returnm ((if (w__414) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__415 : bool => - returnm ((if (w__415) then true - else false) - : bool)) >>= fun w__416 : bool => - (if (w__416) then - let _stringappend_618_ := - string_drop _stringappend_381_ - (build_ex (projT1 (string_length "div"))) in - (match (maybe_not_u_matches_prefix - _stringappend_618_) with - | Some (s,(existT _ _stringappend_619_ _)) => - returnm (s, build_ex _stringappend_619_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(s, existT _ _stringappend_619_ _) => - let _stringappend_620_ := - string_drop _stringappend_618_ - (build_ex _stringappend_619_) in - let _stringappend_621_ := - string_drop _stringappend_620_ - (build_ex (projT1 (string_length "w"))) in - (match (spc_matches_prefix - _stringappend_621_) with - | Some - (tt,(existT _ _stringappend_622_ _)) => - returnm (tt, build_ex _stringappend_622_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_622_ _) => - let _stringappend_623_ := - string_drop _stringappend_621_ - (build_ex _stringappend_622_) in - (match (reg_name_matches_prefix - _stringappend_623_) with - | Some - (rd,(existT _ _stringappend_624_ _)) => - returnm (rd, build_ex _stringappend_624_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_624_ _) => - let _stringappend_625_ := - string_drop _stringappend_623_ - (build_ex _stringappend_624_) in - sep_matches_prefix _stringappend_625_ >>= fun w__423 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__423 with - | Some - (tt,(existT _ _stringappend_626_ _)) => - returnm (tt, build_ex _stringappend_626_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_626_ _) => - let _stringappend_627_ := - string_drop _stringappend_625_ - (build_ex _stringappend_626_) in - (match (reg_name_matches_prefix - _stringappend_627_) with - | Some - (rs1,(existT _ _stringappend_628_ _)) => - returnm (rs1, build_ex _stringappend_628_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_628_ _) => - let _stringappend_629_ := - string_drop _stringappend_627_ - (build_ex _stringappend_628_) in - sep_matches_prefix _stringappend_629_ >>= fun w__428 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__428 with - | Some - (tt,(existT _ _stringappend_630_ _)) => - returnm (tt, build_ex _stringappend_630_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_630_ _) => - let _stringappend_631_ := - string_drop _stringappend_629_ - (build_ex _stringappend_630_) in - (match (reg_name_matches_prefix - _stringappend_631_) with - | Some - (rs2,(existT _ _stringappend_632_ _)) => - returnm (rs2, build_ex _stringappend_632_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs2, existT _ _stringappend_632_ _) => - (match (string_drop _stringappend_631_ - (build_ex _stringappend_632_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - and_boolM - (returnm ((string_startswith - _stringappend_381_ "rem") - : bool)) - (let _stringappend_634_ := - string_drop _stringappend_381_ - (build_ex (projT1 (string_length - "rem"))) in - match (maybe_not_u_matches_prefix - _stringappend_634_) with - | Some - (s,(existT _ _stringappend_635_ _)) => - let _stringappend_636_ := - string_drop _stringappend_634_ - (build_ex _stringappend_635_) in - and_boolM - (returnm ((string_startswith - _stringappend_636_ "w") - : bool)) - (let _stringappend_637_ := - string_drop _stringappend_636_ - (build_ex (projT1 (string_length - "w"))) in - match (spc_matches_prefix - _stringappend_637_) with - | Some - (tt,(existT _ _stringappend_638_ _)) => - let _stringappend_639_ := - string_drop _stringappend_637_ - (build_ex _stringappend_638_) in - match (reg_name_matches_prefix - _stringappend_639_) with - | Some - (rd,(existT _ _stringappend_640_ _)) => - let _stringappend_641_ := - string_drop - _stringappend_639_ - (build_ex _stringappend_640_) in - sep_matches_prefix - _stringappend_641_ >>= fun w__435 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__435 with - | Some - (tt,(existT _ _stringappend_642_ _)) => - let _stringappend_643_ := - string_drop - _stringappend_641_ - (build_ex _stringappend_642_) in - match (reg_name_matches_prefix - _stringappend_643_) with - | Some - (rs1,(existT _ _stringappend_644_ _)) => - let _stringappend_645_ := - string_drop - _stringappend_643_ - (build_ex _stringappend_644_) in - sep_matches_prefix - _stringappend_645_ >>= fun w__436 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__436 with - | Some - (tt,(existT _ _stringappend_646_ _)) => - let _stringappend_647_ := - string_drop - _stringappend_645_ - (build_ex _stringappend_646_) in - if ((match (reg_name_matches_prefix - _stringappend_647_) with - | Some - (rs2,(existT _ _stringappend_648_ _)) => - match (string_drop - _stringappend_647_ - (build_ex _stringappend_648_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) - then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__437 : bool => - returnm ((if (w__437) then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__438 : bool => - returnm ((if (w__438) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__439 : bool => - returnm ((if (w__439) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__440 : bool => - returnm ((if (w__440) then true - else false) - : bool)) >>= fun w__441 : bool => - returnm ((if (w__441) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__442 : bool => - returnm ((if (w__442) then true - else false) - : bool)) >>= fun w__443 : bool => - (if (w__443) then - let _stringappend_634_ := - string_drop _stringappend_381_ - (build_ex (projT1 (string_length - "rem"))) in - (match (maybe_not_u_matches_prefix - _stringappend_634_) with - | Some - (s,(existT _ _stringappend_635_ _)) => - returnm (s, build_ex _stringappend_635_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(s, existT _ _stringappend_635_ _) => - let _stringappend_636_ := - string_drop _stringappend_634_ - (build_ex _stringappend_635_) in - let _stringappend_637_ := - string_drop _stringappend_636_ - (build_ex (projT1 (string_length "w"))) in - (match (spc_matches_prefix - _stringappend_637_) with - | Some - (tt,(existT _ _stringappend_638_ _)) => - returnm (tt, build_ex _stringappend_638_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_638_ _) => - let _stringappend_639_ := - string_drop _stringappend_637_ - (build_ex _stringappend_638_) in - (match (reg_name_matches_prefix - _stringappend_639_) with - | Some - (rd,(existT _ _stringappend_640_ _)) => - returnm (rd, build_ex _stringappend_640_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_640_ _) => - let _stringappend_641_ := - string_drop _stringappend_639_ - (build_ex _stringappend_640_) in - sep_matches_prefix _stringappend_641_ >>= fun w__450 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__450 with - | Some - (tt,(existT _ _stringappend_642_ _)) => - returnm (tt, build_ex _stringappend_642_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_642_ _) => - let _stringappend_643_ := - string_drop _stringappend_641_ - (build_ex _stringappend_642_) in - (match (reg_name_matches_prefix - _stringappend_643_) with - | Some - (rs1,(existT _ _stringappend_644_ _)) => - returnm (rs1, build_ex _stringappend_644_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_644_ _) => - let _stringappend_645_ := - string_drop _stringappend_643_ - (build_ex _stringappend_644_) in - sep_matches_prefix _stringappend_645_ >>= fun w__455 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__455 with - | Some - (tt,(existT _ _stringappend_646_ _)) => - returnm (tt, build_ex _stringappend_646_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_646_ _) => - let _stringappend_647_ := - string_drop _stringappend_645_ - (build_ex _stringappend_646_) in - (match (reg_name_matches_prefix - _stringappend_647_) with - | Some - (rs2,(existT _ _stringappend_648_ _)) => - returnm (rs2, build_ex _stringappend_648_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs2, existT _ _stringappend_648_ _) => - (match (string_drop _stringappend_647_ - (build_ex _stringappend_648_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - and_boolM - (returnm ((string_startswith - _stringappend_381_ - "fence") - : bool)) - (let _stringappend_650_ := - string_drop _stringappend_381_ - (build_ex (projT1 (string_length - "fence"))) in - match (spc_matches_prefix - _stringappend_650_) with - | Some - (tt,(existT _ _stringappend_651_ _)) => - let _stringappend_652_ := - string_drop _stringappend_650_ - (build_ex _stringappend_651_) in - fence_bits_matches_prefix - _stringappend_652_ >>= fun w__462 : option ((mword 4 * {n : Z & ArithFact (n >= - 0)})) => - match w__462 with - | Some - (pred,(existT _ _stringappend_653_ _)) => - let _stringappend_654_ := - string_drop _stringappend_652_ - (build_ex _stringappend_653_) in - sep_matches_prefix - _stringappend_654_ >>= fun w__463 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__463 with - | Some - (tt,(existT _ _stringappend_655_ _)) => - let _stringappend_656_ := - string_drop - _stringappend_654_ - (build_ex _stringappend_655_) in - fence_bits_matches_prefix - _stringappend_656_ >>= fun w__464 : option ((mword 4 * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__464 with - | Some - (succ,(existT _ _stringappend_657_ _)) => - match (string_drop - _stringappend_656_ - (build_ex _stringappend_657_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__465 : bool => - returnm ((if (w__465) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__466 : bool => - returnm ((if (w__466) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__467 : bool => - returnm ((if (w__467) then true - else false) - : bool)) >>= fun w__468 : bool => - (if (w__468) then - let _stringappend_650_ := - string_drop _stringappend_381_ - (build_ex (projT1 (string_length - "fence"))) in - (match (spc_matches_prefix - _stringappend_650_) with - | Some - (tt,(existT _ _stringappend_651_ _)) => - returnm (tt, build_ex _stringappend_651_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_651_ _) => - let _stringappend_652_ := - string_drop _stringappend_650_ - (build_ex _stringappend_651_) in - fence_bits_matches_prefix - _stringappend_652_ >>= fun w__471 : option ((mword 4 * {n : Z & ArithFact (n >= - 0)})) => - (match w__471 with - | Some - (pred,(existT _ _stringappend_653_ _)) => - returnm (pred, build_ex _stringappend_653_) - | _ => - exit tt - : M ((mword 4 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 4 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(pred, existT _ _stringappend_653_ _) => - let _stringappend_654_ := - string_drop _stringappend_652_ - (build_ex _stringappend_653_) in - sep_matches_prefix _stringappend_654_ >>= fun w__474 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__474 with - | Some - (tt,(existT _ _stringappend_655_ _)) => - returnm (tt, build_ex _stringappend_655_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_655_ _) => - let _stringappend_656_ := - string_drop _stringappend_654_ - (build_ex _stringappend_655_) in - fence_bits_matches_prefix - _stringappend_656_ >>= fun w__477 : option ((mword 4 * {n : Z & ArithFact (n >= - 0)})) => - (match w__477 with - | Some - (succ,(existT _ _stringappend_657_ _)) => - returnm (succ, build_ex _stringappend_657_) - | _ => - exit tt - : M ((mword 4 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 4 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(succ, existT _ _stringappend_657_ _) => - (match (string_drop - _stringappend_656_ - (build_ex _stringappend_657_)) with - | "" => returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - (match _stringappend_381_ with - | "fence.i" => - returnm (true : bool) - | "ecall" => returnm (true : bool) - | "mret" => returnm (true : bool) - | "sret" => returnm (true : bool) - | "ebreak" => returnm (true : bool) - | "wfi" => returnm (true : bool) - | _stringappend_381_ => - and_boolM - (returnm ((string_startswith - _stringappend_381_ - "sfence.vma") - : bool)) - (let _stringappend_659_ := - string_drop - _stringappend_381_ - (build_ex (projT1 (string_length - "sfence.vma"))) in - match (spc_matches_prefix - _stringappend_659_) with - | Some - (tt,(existT _ _stringappend_660_ _)) => - let _stringappend_661_ := - string_drop - _stringappend_659_ - (build_ex _stringappend_660_) in - match (reg_name_matches_prefix - _stringappend_661_) with - | Some - (rs1,(existT _ _stringappend_662_ _)) => - let _stringappend_663_ := - string_drop - _stringappend_661_ - (build_ex _stringappend_662_) in - sep_matches_prefix - _stringappend_663_ >>= fun w__482 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__482 with - | Some - (tt,(existT _ _stringappend_664_ _)) => - let _stringappend_665_ := - string_drop - _stringappend_663_ - (build_ex _stringappend_664_) in - if ((match (reg_name_matches_prefix - _stringappend_665_) with - | Some - (rs2,(existT _ _stringappend_666_ _)) => - match (string_drop - _stringappend_665_ - (build_ex _stringappend_666_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__483 : bool => - returnm ((if (w__483) then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__484 : bool => - returnm ((if (w__484) then true - else false) - : bool)) >>= fun w__485 : bool => - (if (w__485) then - let _stringappend_659_ := - string_drop - _stringappend_381_ - (build_ex (projT1 (string_length - "sfence.vma"))) in - (match (spc_matches_prefix - _stringappend_659_) with - | Some - (tt,(existT _ _stringappend_660_ _)) => - returnm (tt, build_ex _stringappend_660_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_660_ _) => - let _stringappend_661_ := - string_drop - _stringappend_659_ - (build_ex _stringappend_660_) in - (match (reg_name_matches_prefix - _stringappend_661_) with - | Some - (rs1,(existT _ _stringappend_662_ _)) => - returnm (rs1, build_ex _stringappend_662_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_662_ _) => - let _stringappend_663_ := - string_drop - _stringappend_661_ - (build_ex _stringappend_662_) in - sep_matches_prefix - _stringappend_663_ >>= fun w__490 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__490 with - | Some - (tt,(existT _ _stringappend_664_ _)) => - returnm (tt, build_ex _stringappend_664_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_664_ _) => - let _stringappend_665_ := - string_drop - _stringappend_663_ - (build_ex _stringappend_664_) in - (match (reg_name_matches_prefix - _stringappend_665_) with - | Some - (rs2,(existT _ _stringappend_666_ _)) => - returnm (rs2, build_ex _stringappend_666_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs2, existT _ _stringappend_666_ _) => - (match (string_drop - _stringappend_665_ - (build_ex _stringappend_666_)) with - | "" => - returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - and_boolM - (returnm ((string_startswith - _stringappend_381_ - "lr.") - : bool)) - (let _stringappend_668_ := - string_drop - _stringappend_381_ - (build_ex (projT1 (string_length - "lr."))) in - match (maybe_aq_matches_prefix - _stringappend_668_) with - | Some - (aq,(existT _ _stringappend_669_ _)) => - let _stringappend_670_ := - string_drop - _stringappend_668_ - (build_ex _stringappend_669_) in - match (maybe_rl_matches_prefix - _stringappend_670_) with - | Some - (rl,(existT _ _stringappend_671_ _)) => - let _stringappend_672_ := - string_drop - _stringappend_670_ - (build_ex _stringappend_671_) in - match (size_mnemonic_matches_prefix - _stringappend_672_) with - | Some - (size,(existT _ _stringappend_673_ _)) => - let _stringappend_674_ := - string_drop - _stringappend_672_ - (build_ex _stringappend_673_) in - match (spc_matches_prefix - _stringappend_674_) with - | Some - (tt,(existT _ _stringappend_675_ _)) => - let _stringappend_676_ := - string_drop - _stringappend_674_ - (build_ex _stringappend_675_) in - match (reg_name_matches_prefix - _stringappend_676_) with - | Some - (rd,(existT _ _stringappend_677_ _)) => - let _stringappend_678_ := - string_drop - _stringappend_676_ - (build_ex _stringappend_677_) in - sep_matches_prefix - _stringappend_678_ >>= fun w__497 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__497 with - | Some - (tt,(existT _ _stringappend_679_ _)) => - let _stringappend_680_ := - string_drop - _stringappend_678_ - (build_ex _stringappend_679_) in - if - ((match (reg_name_matches_prefix - _stringappend_680_) with - | Some - (rs1,(existT _ _stringappend_681_ _)) => - match (string_drop - _stringappend_680_ - (build_ex _stringappend_681_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__498 : bool => - returnm ((if (w__498) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__499 : bool => - returnm ((if (w__499) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__500 : bool => - returnm ((if (w__500) - then - true - else false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__501 : bool => - returnm ((if (w__501) - then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__502 : bool => - returnm ((if (w__502) then - true - else false) - : bool)) >>= fun w__503 : bool => - (if (w__503) then - let _stringappend_668_ := - string_drop - _stringappend_381_ - (build_ex (projT1 (string_length - "lr."))) in - (match (maybe_aq_matches_prefix - _stringappend_668_) with - | Some - (aq,(existT _ _stringappend_669_ _)) => - returnm (aq, build_ex _stringappend_669_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(aq, existT _ _stringappend_669_ _) => - let _stringappend_670_ := - string_drop - _stringappend_668_ - (build_ex _stringappend_669_) in - (match (maybe_rl_matches_prefix - _stringappend_670_) with - | Some - (rl,(existT _ _stringappend_671_ _)) => - returnm (rl, build_ex _stringappend_671_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rl, existT _ _stringappend_671_ _) => - let _stringappend_672_ := - string_drop - _stringappend_670_ - (build_ex _stringappend_671_) in - (match (size_mnemonic_matches_prefix - _stringappend_672_) with - | Some - (size,(existT _ _stringappend_673_ _)) => - returnm (size, build_ex _stringappend_673_) - | _ => - exit tt - : M ((word_width * {n : Z & ArithFact (n >= - 0)})) - end : M ((word_width * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(size, existT _ _stringappend_673_ _) => - let _stringappend_674_ := - string_drop - _stringappend_672_ - (build_ex _stringappend_673_) in - (match (spc_matches_prefix - _stringappend_674_) with - | Some - (tt,(existT _ _stringappend_675_ _)) => - returnm (tt, build_ex _stringappend_675_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_675_ _) => - let _stringappend_676_ := - string_drop - _stringappend_674_ - (build_ex _stringappend_675_) in - (match (reg_name_matches_prefix - _stringappend_676_) with - | Some - (rd,(existT _ _stringappend_677_ _)) => - returnm (rd, build_ex _stringappend_677_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_677_ _) => - let _stringappend_678_ := - string_drop - _stringappend_676_ - (build_ex _stringappend_677_) in - sep_matches_prefix - _stringappend_678_ >>= fun w__514 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__514 with - | Some - (tt,(existT _ _stringappend_679_ _)) => - returnm (tt, build_ex _stringappend_679_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_679_ _) => - let _stringappend_680_ := - string_drop - _stringappend_678_ - (build_ex _stringappend_679_) in - (match (reg_name_matches_prefix - _stringappend_680_) with - | Some - (rs1,(existT _ _stringappend_681_ _)) => - returnm (rs1, build_ex _stringappend_681_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_681_ _) => - (match (string_drop - _stringappend_680_ - (build_ex _stringappend_681_)) with - | "" => - returnm (true : bool) - | _ => exit tt : M (bool) - end) - : M (bool) - else - and_boolM - (returnm ((string_startswith - _stringappend_381_ - "sc.") - : bool)) - (let _stringappend_683_ := - string_drop - _stringappend_381_ - (build_ex (projT1 (string_length - "sc."))) in - match (maybe_aq_matches_prefix - _stringappend_683_) with - | Some - (aq,(existT _ _stringappend_684_ _)) => - let _stringappend_685_ := - string_drop - _stringappend_683_ - (build_ex _stringappend_684_) in - match (maybe_rl_matches_prefix - _stringappend_685_) with - | Some - (rl,(existT _ _stringappend_686_ _)) => - let _stringappend_687_ := - string_drop - _stringappend_685_ - (build_ex _stringappend_686_) in - match (size_mnemonic_matches_prefix - _stringappend_687_) with - | Some - (size,(existT _ _stringappend_688_ _)) => - let _stringappend_689_ := - string_drop - _stringappend_687_ - (build_ex _stringappend_688_) in - match (spc_matches_prefix - _stringappend_689_) with - | Some - (tt,(existT _ _stringappend_690_ _)) => - let _stringappend_691_ := - string_drop - _stringappend_689_ - (build_ex _stringappend_690_) in - match (reg_name_matches_prefix - _stringappend_691_) with - | Some - (rd,(existT _ _stringappend_692_ _)) => - let _stringappend_693_ := - string_drop - _stringappend_691_ - (build_ex _stringappend_692_) in - sep_matches_prefix - _stringappend_693_ >>= fun w__521 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__521 with - | Some - (tt,(existT _ _stringappend_694_ _)) => - let _stringappend_695_ := - string_drop - _stringappend_693_ - (build_ex _stringappend_694_) in - match (reg_name_matches_prefix - _stringappend_695_) with - | Some - (rs1,(existT _ _stringappend_696_ _)) => - let _stringappend_697_ := - string_drop - _stringappend_695_ - (build_ex _stringappend_696_) in - sep_matches_prefix - _stringappend_697_ >>= fun w__522 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if - ((match w__522 with - | Some - (tt,(existT _ _stringappend_698_ _)) => - let _stringappend_699_ := - string_drop - _stringappend_697_ - (build_ex _stringappend_698_) in - if - ((match (reg_name_matches_prefix - _stringappend_699_) with - | Some - (rs2,(existT _ _stringappend_700_ _)) => - match (string_drop - _stringappend_699_ - (build_ex _stringappend_700_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__523 : bool => - returnm ((if - (w__523) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__524 : bool => - returnm ((if - (w__524) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__525 : bool => - returnm ((if (w__525) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__526 : bool => - returnm ((if (w__526) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__527 : bool => - returnm ((if (w__527) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__528 : bool => - returnm ((if (w__528) - then - true - else false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__529 : bool => - returnm ((if (w__529) - then - true - else false) - : bool)) >>= fun w__530 : bool => - (if (w__530) then - let _stringappend_683_ := - string_drop - _stringappend_381_ - (build_ex (projT1 (string_length - "sc."))) in - (match (maybe_aq_matches_prefix - _stringappend_683_) with - | Some - (aq,(existT _ _stringappend_684_ _)) => - returnm (aq, build_ex _stringappend_684_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(aq, existT _ _stringappend_684_ _) => - let _stringappend_685_ := - string_drop - _stringappend_683_ - (build_ex _stringappend_684_) in - (match (maybe_rl_matches_prefix - _stringappend_685_) with - | Some - (rl,(existT _ _stringappend_686_ _)) => - returnm (rl, build_ex _stringappend_686_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rl, existT _ _stringappend_686_ _) => - let _stringappend_687_ := - string_drop - _stringappend_685_ - (build_ex _stringappend_686_) in - (match (size_mnemonic_matches_prefix - _stringappend_687_) with - | Some - (size,(existT _ _stringappend_688_ _)) => - returnm (size, build_ex _stringappend_688_) - | _ => - exit tt - : M ((word_width * {n : Z & ArithFact (n >= - 0)})) - end : M ((word_width * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(size, existT _ _stringappend_688_ _) => - let _stringappend_689_ := - string_drop - _stringappend_687_ - (build_ex _stringappend_688_) in - (match (spc_matches_prefix - _stringappend_689_) with - | Some - (tt,(existT _ _stringappend_690_ _)) => - returnm (tt, build_ex _stringappend_690_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_690_ _) => - let _stringappend_691_ := - string_drop - _stringappend_689_ - (build_ex _stringappend_690_) in - (match (reg_name_matches_prefix - _stringappend_691_) with - | Some - (rd,(existT _ _stringappend_692_ _)) => - returnm (rd, build_ex _stringappend_692_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_692_ _) => - let _stringappend_693_ := - string_drop - _stringappend_691_ - (build_ex _stringappend_692_) in - sep_matches_prefix - _stringappend_693_ >>= fun w__541 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__541 with - | Some - (tt,(existT _ _stringappend_694_ _)) => - returnm (tt, build_ex _stringappend_694_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_694_ _) => - let _stringappend_695_ := - string_drop - _stringappend_693_ - (build_ex _stringappend_694_) in - (match (reg_name_matches_prefix - _stringappend_695_) with - | Some - (rs1,(existT _ _stringappend_696_ _)) => - returnm (rs1, build_ex _stringappend_696_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_696_ _) => - let _stringappend_697_ := - string_drop - _stringappend_695_ - (build_ex _stringappend_696_) in - sep_matches_prefix - _stringappend_697_ >>= fun w__546 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__546 with - | Some - (tt,(existT _ _stringappend_698_ _)) => - returnm (tt, build_ex _stringappend_698_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_698_ _) => - let _stringappend_699_ := - string_drop - _stringappend_697_ - (build_ex _stringappend_698_) in - (match (reg_name_matches_prefix - _stringappend_699_) with - | Some - (rs2,(existT _ _stringappend_700_ _)) => - returnm (rs2, build_ex _stringappend_700_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs2, existT _ _stringappend_700_ _) => - (match (string_drop - _stringappend_699_ - (build_ex _stringappend_700_)) with - | "" => - returnm (true - : bool) - | _ => - exit tt : M (bool) - end) - : M (bool) - else - match (amo_mnemonic_matches_prefix - _stringappend_381_) with - | Some - (op,(existT _ _stringappend_702_ _)) => - let _stringappend_703_ := - string_drop - _stringappend_381_ - (build_ex _stringappend_702_) in - and_boolM - (returnm ((string_startswith - _stringappend_703_ - ".") - : bool)) - (let _stringappend_704_ := - string_drop - _stringappend_703_ - (build_ex (projT1 (string_length - "."))) in - match (size_mnemonic_matches_prefix - _stringappend_704_) with - | Some - (width,(existT _ _stringappend_705_ _)) => - let _stringappend_706_ := - string_drop - _stringappend_704_ - (build_ex _stringappend_705_) in - match (maybe_aq_matches_prefix - _stringappend_706_) with - | Some - (aq,(existT _ _stringappend_707_ _)) => - let _stringappend_708_ := - string_drop - _stringappend_706_ - (build_ex _stringappend_707_) in - match (maybe_rl_matches_prefix - _stringappend_708_) with - | Some - (rl,(existT _ _stringappend_709_ _)) => - let _stringappend_710_ := - string_drop - _stringappend_708_ - (build_ex _stringappend_709_) in - match (spc_matches_prefix - _stringappend_710_) with - | Some - (tt,(existT _ _stringappend_711_ _)) => - let _stringappend_712_ := - string_drop - _stringappend_710_ - (build_ex _stringappend_711_) in - match (reg_name_matches_prefix - _stringappend_712_) with - | Some - (rd,(existT _ _stringappend_713_ _)) => - let _stringappend_714_ := - string_drop - _stringappend_712_ - (build_ex _stringappend_713_) in - sep_matches_prefix - _stringappend_714_ >>= fun w__553 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__553 with - | Some - (tt,(existT _ _stringappend_715_ _)) => - let _stringappend_716_ := - string_drop - _stringappend_714_ - (build_ex _stringappend_715_) in - match (reg_name_matches_prefix - _stringappend_716_) with - | Some - (rs1,(existT _ _stringappend_717_ _)) => - let _stringappend_718_ := - string_drop - _stringappend_716_ - (build_ex _stringappend_717_) in - sep_matches_prefix - _stringappend_718_ >>= fun w__554 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if - ((match w__554 with - | Some - (tt,(existT _ _stringappend_719_ _)) => - let _stringappend_720_ := - string_drop - _stringappend_718_ - (build_ex _stringappend_719_) in - if - ((match (reg_name_matches_prefix - _stringappend_720_) with - | Some - (rs2,(existT _ _stringappend_721_ _)) => - match (string_drop - _stringappend_720_ - (build_ex _stringappend_721_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__555 : bool => - returnm ((if - (w__555) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__556 : bool => - returnm ((if - (w__556) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__557 : bool => - returnm ((if - (w__557) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__558 : bool => - returnm ((if - (w__558) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__559 : bool => - returnm ((if (w__559) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__560 : bool => - returnm ((if (w__560) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__561 : bool => - returnm ((if (w__561) - then - true - else - false) - : bool)) >>= fun w__562 : bool => - returnm ((if (w__562) - then - true - else false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__563 : bool => - (if (w__563) then - (match (amo_mnemonic_matches_prefix - _stringappend_381_) with - | Some - (op,(existT _ _stringappend_702_ _)) => - returnm (op, build_ex _stringappend_702_) - | _ => - exit tt - : M ((amoop * {n : Z & ArithFact (n >= - 0)})) - end : M ((amoop * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(op, existT _ _stringappend_702_ _) => - let _stringappend_703_ := - string_drop - _stringappend_381_ - (build_ex _stringappend_702_) in - let _stringappend_704_ := - string_drop - _stringappend_703_ - (build_ex (projT1 (string_length - "."))) in - (match (size_mnemonic_matches_prefix - _stringappend_704_) with - | Some - (width,(existT _ _stringappend_705_ _)) => - returnm (width, build_ex _stringappend_705_) - | _ => - exit tt - : M ((word_width * {n : Z & ArithFact (n >= - 0)})) - end : M ((word_width * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(width, existT _ _stringappend_705_ _) => - let _stringappend_706_ := - string_drop - _stringappend_704_ - (build_ex _stringappend_705_) in - (match (maybe_aq_matches_prefix - _stringappend_706_) with - | Some - (aq,(existT _ _stringappend_707_ _)) => - returnm (aq, build_ex _stringappend_707_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(aq, existT _ _stringappend_707_ _) => - let _stringappend_708_ := - string_drop - _stringappend_706_ - (build_ex _stringappend_707_) in - (match (maybe_rl_matches_prefix - _stringappend_708_) with - | Some - (rl,(existT _ _stringappend_709_ _)) => - returnm (rl, build_ex _stringappend_709_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rl, existT _ _stringappend_709_ _) => - let _stringappend_710_ := - string_drop - _stringappend_708_ - (build_ex _stringappend_709_) in - (match (spc_matches_prefix - _stringappend_710_) with - | Some - (tt,(existT _ _stringappend_711_ _)) => - returnm (tt, build_ex _stringappend_711_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_711_ _) => - let _stringappend_712_ := - string_drop - _stringappend_710_ - (build_ex _stringappend_711_) in - (match (reg_name_matches_prefix - _stringappend_712_) with - | Some - (rd,(existT _ _stringappend_713_ _)) => - returnm (rd, build_ex _stringappend_713_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_713_ _) => - let _stringappend_714_ := - string_drop - _stringappend_712_ - (build_ex _stringappend_713_) in - sep_matches_prefix - _stringappend_714_ >>= fun w__576 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__576 with - | Some - (tt,(existT _ _stringappend_715_ _)) => - returnm (tt, build_ex _stringappend_715_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_715_ _) => - let _stringappend_716_ := - string_drop - _stringappend_714_ - (build_ex _stringappend_715_) in - (match (reg_name_matches_prefix - _stringappend_716_) with - | Some - (rs1,(existT _ _stringappend_717_ _)) => - returnm (rs1, build_ex _stringappend_717_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_717_ _) => - let _stringappend_718_ := - string_drop - _stringappend_716_ - (build_ex _stringappend_717_) in - sep_matches_prefix - _stringappend_718_ >>= fun w__581 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__581 with - | Some - (tt,(existT _ _stringappend_719_ _)) => - returnm (tt, build_ex _stringappend_719_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_719_ _) => - let _stringappend_720_ := - string_drop - _stringappend_718_ - (build_ex _stringappend_719_) in - (match (reg_name_matches_prefix - _stringappend_720_) with - | Some - (rs2,(existT _ _stringappend_721_ _)) => - returnm (rs2, build_ex _stringappend_721_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs2, existT _ _stringappend_721_ _) => - (match (string_drop - _stringappend_720_ - (build_ex _stringappend_721_)) with - | "" => - returnm (true - : bool) - | _ => - exit tt - : M (bool) - end) - : M (bool) - else - match (csr_mnemonic_matches_prefix - _stringappend_381_) with - | Some - (op,(existT _ _stringappend_723_ _)) => - let _stringappend_724_ := - string_drop - _stringappend_381_ - (build_ex _stringappend_723_) in - and_boolM - (returnm ((string_startswith - _stringappend_724_ - "i") - : bool)) - (let _stringappend_725_ := - string_drop - _stringappend_724_ - (build_ex (projT1 (string_length - "i"))) in - match (spc_matches_prefix - _stringappend_725_) with - | Some - (tt,(existT _ _stringappend_726_ _)) => - let _stringappend_727_ := - string_drop - _stringappend_725_ - (build_ex _stringappend_726_) in - match (reg_name_matches_prefix - _stringappend_727_) with - | Some - (rd,(existT _ _stringappend_728_ _)) => - let _stringappend_729_ := - string_drop - _stringappend_727_ - (build_ex _stringappend_728_) in - sep_matches_prefix - _stringappend_729_ >>= fun w__588 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__588 with - | Some - (tt,(existT _ _stringappend_730_ _)) => - let _stringappend_731_ := - string_drop - _stringappend_729_ - (build_ex _stringappend_730_) in - match (hex_bits_5_matches_prefix - _stringappend_731_) with - | Some - (rs1,(existT _ _stringappend_732_ _)) => - let _stringappend_733_ := - string_drop - _stringappend_731_ - (build_ex _stringappend_732_) in - sep_matches_prefix - _stringappend_733_ >>= fun w__589 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if - ((match w__589 with - | Some - (tt,(existT _ _stringappend_734_ _)) => - let _stringappend_735_ := - string_drop - _stringappend_733_ - (build_ex _stringappend_734_) in - if - ((match (csr_name_map_matches_prefix - _stringappend_735_) with - | Some - (csr,(existT _ _stringappend_736_ _)) => - match (string_drop - _stringappend_735_ - (build_ex _stringappend_736_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__590 : bool => - returnm ((if - (w__590) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__591 : bool => - returnm ((if - (w__591) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__592 : bool => - returnm ((if (w__592) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__593 : bool => - returnm ((if (w__593) - then - true - else - false) - : bool)) >>= fun w__594 : bool => - returnm ((if (w__594) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__595 : bool => - (if (w__595) then - (match (csr_mnemonic_matches_prefix - _stringappend_381_) with - | Some - (op,(existT _ _stringappend_723_ _)) => - returnm (op, build_ex _stringappend_723_) - | _ => - exit tt - : M ((csrop * {n : Z & ArithFact (n >= - 0)})) - end : M ((csrop * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(op, existT _ _stringappend_723_ _) => - let _stringappend_724_ := - string_drop - _stringappend_381_ - (build_ex _stringappend_723_) in - let _stringappend_725_ := - string_drop - _stringappend_724_ - (build_ex (projT1 (string_length - "i"))) in - (match (spc_matches_prefix - _stringappend_725_) with - | Some - (tt,(existT _ _stringappend_726_ _)) => - returnm (tt, build_ex _stringappend_726_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_726_ _) => - let _stringappend_727_ := - string_drop - _stringappend_725_ - (build_ex _stringappend_726_) in - (match (reg_name_matches_prefix - _stringappend_727_) with - | Some - (rd,(existT _ _stringappend_728_ _)) => - returnm (rd, build_ex _stringappend_728_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_728_ _) => - let _stringappend_729_ := - string_drop - _stringappend_727_ - (build_ex _stringappend_728_) in - sep_matches_prefix - _stringappend_729_ >>= fun w__602 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__602 with - | Some - (tt,(existT _ _stringappend_730_ _)) => - returnm (tt, build_ex _stringappend_730_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_730_ _) => - let _stringappend_731_ := - string_drop - _stringappend_729_ - (build_ex _stringappend_730_) in - (match (hex_bits_5_matches_prefix - _stringappend_731_) with - | Some - (rs1,(existT _ _stringappend_732_ _)) => - returnm (rs1, build_ex _stringappend_732_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_732_ _) => - let _stringappend_733_ := - string_drop - _stringappend_731_ - (build_ex _stringappend_732_) in - sep_matches_prefix - _stringappend_733_ >>= fun w__607 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__607 with - | Some - (tt,(existT _ _stringappend_734_ _)) => - returnm (tt, build_ex _stringappend_734_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_734_ _) => - let _stringappend_735_ := - string_drop - _stringappend_733_ - (build_ex _stringappend_734_) in - (match (csr_name_map_matches_prefix - _stringappend_735_) with - | Some - (csr,(existT _ _stringappend_736_ _)) => - returnm (csr, build_ex _stringappend_736_) - | _ => - exit tt - : M ((mword 12 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(csr, existT _ _stringappend_736_ _) => - (match (string_drop - _stringappend_735_ - (build_ex _stringappend_736_)) with - | "" => - returnm (true - : bool) - | _ => - exit tt - : M (bool) - end) - : M (bool) - else - match (csr_mnemonic_matches_prefix - _stringappend_381_) with - | Some - (op,(existT _ _stringappend_738_ _)) => - let _stringappend_739_ := - string_drop - _stringappend_381_ - (build_ex _stringappend_738_) in - match (spc_matches_prefix - _stringappend_739_) with - | Some - (tt,(existT _ _stringappend_740_ _)) => - let _stringappend_741_ := - string_drop - _stringappend_739_ - (build_ex _stringappend_740_) in - match (reg_name_matches_prefix - _stringappend_741_) with - | Some - (rd,(existT _ _stringappend_742_ _)) => - let _stringappend_743_ := - string_drop - _stringappend_741_ - (build_ex _stringappend_742_) in - sep_matches_prefix - _stringappend_743_ >>= fun w__614 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__614 with - | Some - (tt,(existT _ _stringappend_744_ _)) => - let _stringappend_745_ := - string_drop - _stringappend_743_ - (build_ex _stringappend_744_) in - match (reg_name_matches_prefix - _stringappend_745_) with - | Some - (rs1,(existT _ _stringappend_746_ _)) => - let _stringappend_747_ := - string_drop - _stringappend_745_ - (build_ex _stringappend_746_) in - sep_matches_prefix - _stringappend_747_ >>= fun w__615 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if - ((match w__615 with - | Some - (tt,(existT _ _stringappend_748_ _)) => - let _stringappend_749_ := - string_drop - _stringappend_747_ - (build_ex _stringappend_748_) in - if - ((match (csr_name_map_matches_prefix - _stringappend_749_) with - | Some - (csr,(existT _ _stringappend_750_ _)) => - match (string_drop - _stringappend_749_ - (build_ex _stringappend_750_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__616 : bool => - returnm ((if - (w__616) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__617 : bool => - returnm ((if - (w__617) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__618 : bool => - returnm ((if - (w__618) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__619 : bool => - returnm ((if (w__619) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__620 : bool => - (if (w__620) then - (match (csr_mnemonic_matches_prefix - _stringappend_381_) with - | Some - (op,(existT _ _stringappend_738_ _)) => - returnm (op, build_ex _stringappend_738_) - | _ => - exit tt - : M ((csrop * {n : Z & ArithFact (n >= - 0)})) - end : M ((csrop * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(op, existT _ _stringappend_738_ _) => - let _stringappend_739_ := - string_drop - _stringappend_381_ - (build_ex _stringappend_738_) in - (match (spc_matches_prefix - _stringappend_739_) with - | Some - (tt,(existT _ _stringappend_740_ _)) => - returnm (tt, build_ex _stringappend_740_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_740_ _) => - let _stringappend_741_ := - string_drop - _stringappend_739_ - (build_ex _stringappend_740_) in - (match (reg_name_matches_prefix - _stringappend_741_) with - | Some - (rd,(existT _ _stringappend_742_ _)) => - returnm (rd, build_ex _stringappend_742_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_742_ _) => - let _stringappend_743_ := - string_drop - _stringappend_741_ - (build_ex _stringappend_742_) in - sep_matches_prefix - _stringappend_743_ >>= fun w__627 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__627 with - | Some - (tt,(existT _ _stringappend_744_ _)) => - returnm (tt, build_ex _stringappend_744_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_744_ _) => - let _stringappend_745_ := - string_drop - _stringappend_743_ - (build_ex _stringappend_744_) in - (match (reg_name_matches_prefix - _stringappend_745_) with - | Some - (rs1,(existT _ _stringappend_746_ _)) => - returnm (rs1, build_ex _stringappend_746_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_746_ _) => - let _stringappend_747_ := - string_drop - _stringappend_745_ - (build_ex _stringappend_746_) in - sep_matches_prefix - _stringappend_747_ >>= fun w__632 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__632 with - | Some - (tt,(existT _ _stringappend_748_ _)) => - returnm (tt, build_ex _stringappend_748_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_748_ _) => - let _stringappend_749_ := - string_drop - _stringappend_747_ - (build_ex _stringappend_748_) in - (match (csr_name_map_matches_prefix - _stringappend_749_) with - | Some - (csr,(existT _ _stringappend_750_ _)) => - returnm (csr, build_ex _stringappend_750_) - | _ => - exit tt - : M ((mword 12 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(csr, existT _ _stringappend_750_ _) => - (match (string_drop - _stringappend_749_ - (build_ex _stringappend_750_)) with - | "" => - returnm (true - : bool) - | _ => - exit tt - : M (bool) - end) - : M (bool) - else if ((andb - (string_startswith - _stringappend_381_ - "illegal") - (let _stringappend_752_ := - string_drop - _stringappend_381_ - (build_ex (projT1 (string_length - "illegal"))) in - if ((match (spc_matches_prefix - _stringappend_752_) with - | Some - (tt,(existT _ _stringappend_753_ _)) => - let _stringappend_754_ := - string_drop - _stringappend_752_ - (build_ex _stringappend_753_) in - if - ((match (hex_bits_32_matches_prefix - _stringappend_754_) with - | Some - (s,(existT _ _stringappend_755_ _)) => - match (string_drop - _stringappend_754_ - (build_ex _stringappend_755_)) with - | "" => - true - | _ => - false - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) - then - true - else - false))) - then - let _stringappend_752_ := - string_drop - _stringappend_381_ - (build_ex (projT1 (string_length - "illegal"))) in - (match (spc_matches_prefix - _stringappend_752_) with - | Some - (tt,(existT _ _stringappend_753_ _)) => - returnm (tt, build_ex _stringappend_753_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_753_ _) => - let _stringappend_754_ := - string_drop - _stringappend_752_ - (build_ex _stringappend_753_) in - (match (hex_bits_32_matches_prefix - _stringappend_754_) with - | Some - (s,(existT _ _stringappend_755_ _)) => - returnm (s, build_ex _stringappend_755_) - | _ => - exit tt - : M ((mword 32 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 32 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(s, existT _ _stringappend_755_ _) => - (match (string_drop - _stringappend_754_ - (build_ex _stringappend_755_)) with - | "" => - returnm (true - : bool) - | _ => - exit tt - : M (bool) - end) - : M (bool) - else - returnm (false - : bool)) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool) - end) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool)) - : M (bool). - -Definition assembly_matches_prefix (arg_ : string) -: M (option ((ast * {n : Z & ArithFact (n >= 0)}))) := - let _stringappend_0_ := arg_ in - match (utype_mnemonic_matches_prefix _stringappend_0_) with - | Some (op,(existT _ _stringappend_1_ _)) => - let _stringappend_2_ := string_drop _stringappend_0_ (build_ex _stringappend_1_) in - match (spc_matches_prefix _stringappend_2_) with - | Some (tt,(existT _ _stringappend_3_ _)) => - let _stringappend_4_ := string_drop _stringappend_2_ (build_ex _stringappend_3_) in - match (reg_name_matches_prefix _stringappend_4_) with - | Some (rd,(existT _ _stringappend_5_ _)) => - let _stringappend_6_ := string_drop _stringappend_4_ (build_ex _stringappend_5_) in - sep_matches_prefix _stringappend_6_ >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__0 with - | Some (tt,(existT _ _stringappend_7_ _)) => - let _stringappend_8_ := - string_drop _stringappend_6_ (build_ex _stringappend_7_) in - if ((match (hex_bits_20_matches_prefix _stringappend_8_) with - | Some (imm,(existT _ _stringappend_9_ _)) => - match (string_drop _stringappend_8_ - (build_ex _stringappend_9_)) with - | s_ => true - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__1 : bool => - returnm ((if (w__1) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__2 : bool => - returnm ((if (w__2) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__3 : bool => - (if (w__3) then - (match (utype_mnemonic_matches_prefix _stringappend_0_) with - | Some (op,(existT _ _stringappend_1_ _)) => returnm (op, build_ex _stringappend_1_) - | _ => exit tt : M ((uop * {n : Z & ArithFact (n >= 0)})) - end : M ((uop * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_1_ _) => - let _stringappend_2_ := string_drop _stringappend_0_ (build_ex _stringappend_1_) in - (match (spc_matches_prefix _stringappend_2_) with - | Some (tt,(existT _ _stringappend_3_ _)) => returnm (tt, build_ex _stringappend_3_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_3_ _) => - let _stringappend_4_ := string_drop _stringappend_2_ (build_ex _stringappend_3_) in - (match (reg_name_matches_prefix _stringappend_4_) with - | Some (rd,(existT _ _stringappend_5_ _)) => returnm (rd, build_ex _stringappend_5_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_5_ _) => - let _stringappend_6_ := string_drop _stringappend_4_ (build_ex _stringappend_5_) in - sep_matches_prefix _stringappend_6_ >>= fun w__10 : option ((unit * {n : Z & ArithFact (n >= 0)})) => - (match w__10 with - | Some (tt,(existT _ _stringappend_7_ _)) => returnm (tt, build_ex _stringappend_7_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_7_ _) => - let _stringappend_8_ := string_drop _stringappend_6_ (build_ex _stringappend_7_) in - (match (hex_bits_20_matches_prefix _stringappend_8_) with - | Some (imm,(existT _ _stringappend_9_ _)) => returnm (imm, build_ex _stringappend_9_) - | _ => exit tt : M ((mword 20 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 20 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_9_ _) => - returnm ((match (string_drop _stringappend_8_ (build_ex _stringappend_9_)) with - | s_ => - Some - ((UTYPE - (imm, rd, op), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= 0)}))) - else - and_boolM (returnm ((string_startswith _stringappend_0_ "jal") : bool)) - (let _stringappend_11_ := - string_drop _stringappend_0_ (build_ex (projT1 (string_length "jal"))) in - match (spc_matches_prefix _stringappend_11_) with - | Some (tt,(existT _ _stringappend_12_ _)) => - let _stringappend_13_ := string_drop _stringappend_11_ (build_ex _stringappend_12_) in - match (reg_name_matches_prefix _stringappend_13_) with - | Some (rd,(existT _ _stringappend_14_ _)) => - let _stringappend_15_ := string_drop _stringappend_13_ (build_ex _stringappend_14_) in - sep_matches_prefix _stringappend_15_ >>= fun w__15 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__15 with - | Some (tt,(existT _ _stringappend_16_ _)) => - let _stringappend_17_ := - string_drop _stringappend_15_ (build_ex _stringappend_16_) in - if ((match (hex_bits_21_matches_prefix _stringappend_17_) with - | Some (imm,(existT _ _stringappend_18_ _)) => - match (string_drop _stringappend_17_ - (build_ex _stringappend_18_)) with - | s_ => true - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__16 : bool => - returnm ((if (w__16) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__17 : bool => - returnm ((if (w__17) then true - else false) - : bool)) >>= fun w__18 : bool => - (if (w__18) then - let _stringappend_11_ := - string_drop _stringappend_0_ (build_ex (projT1 (string_length "jal"))) in - (match (spc_matches_prefix _stringappend_11_) with - | Some (tt,(existT _ _stringappend_12_ _)) => returnm (tt, build_ex _stringappend_12_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_12_ _) => - let _stringappend_13_ := string_drop _stringappend_11_ (build_ex _stringappend_12_) in - (match (reg_name_matches_prefix _stringappend_13_) with - | Some (rd,(existT _ _stringappend_14_ _)) => returnm (rd, build_ex _stringappend_14_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_14_ _) => - let _stringappend_15_ := string_drop _stringappend_13_ (build_ex _stringappend_14_) in - sep_matches_prefix _stringappend_15_ >>= fun w__23 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__23 with - | Some (tt,(existT _ _stringappend_16_ _)) => returnm (tt, build_ex _stringappend_16_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_16_ _) => - let _stringappend_17_ := string_drop _stringappend_15_ (build_ex _stringappend_16_) in - (match (hex_bits_21_matches_prefix _stringappend_17_) with - | Some (imm,(existT _ _stringappend_18_ _)) => returnm (imm, build_ex _stringappend_18_) - | _ => exit tt : M ((mword 21 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 21 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_18_ _) => - returnm ((match (string_drop _stringappend_17_ (build_ex _stringappend_18_)) with - | s_ => - Some - ((RISCV_JAL - (imm, rd), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length arg_))) - (build_ex (projT1 (string_length s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= 0)}))) - else - and_boolM (returnm ((string_startswith _stringappend_0_ "jalr") : bool)) - (let _stringappend_20_ := - string_drop _stringappend_0_ (build_ex (projT1 (string_length "jalr"))) in - match (spc_matches_prefix _stringappend_20_) with - | Some (tt,(existT _ _stringappend_21_ _)) => - let _stringappend_22_ := string_drop _stringappend_20_ (build_ex _stringappend_21_) in - match (reg_name_matches_prefix _stringappend_22_) with - | Some (rd,(existT _ _stringappend_23_ _)) => - let _stringappend_24_ := string_drop _stringappend_22_ (build_ex _stringappend_23_) in - sep_matches_prefix _stringappend_24_ >>= fun w__28 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__28 with - | Some (tt,(existT _ _stringappend_25_ _)) => - let _stringappend_26_ := - string_drop _stringappend_24_ (build_ex _stringappend_25_) in - match (reg_name_matches_prefix _stringappend_26_) with - | Some (rs1,(existT _ _stringappend_27_ _)) => - let _stringappend_28_ := - string_drop _stringappend_26_ (build_ex _stringappend_27_) in - sep_matches_prefix _stringappend_28_ >>= fun w__29 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__29 with - | Some (tt,(existT _ _stringappend_29_ _)) => - let _stringappend_30_ := - string_drop _stringappend_28_ - (build_ex _stringappend_29_) in - if ((match (hex_bits_12_matches_prefix _stringappend_30_) with - | Some (imm,(existT _ _stringappend_31_ _)) => - match (string_drop _stringappend_30_ - (build_ex _stringappend_31_)) with - | s_ => true - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__30 : bool => - returnm ((if (w__30) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__31 : bool => - returnm ((if (w__31) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__32 : bool => - returnm ((if (w__32) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__33 : bool => - returnm ((if (w__33) then true - else false) - : bool)) >>= fun w__34 : bool => - (if (w__34) then - let _stringappend_20_ := - string_drop _stringappend_0_ (build_ex (projT1 (string_length "jalr"))) in - (match (spc_matches_prefix _stringappend_20_) with - | Some (tt,(existT _ _stringappend_21_ _)) => returnm (tt, build_ex _stringappend_21_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_21_ _) => - let _stringappend_22_ := string_drop _stringappend_20_ (build_ex _stringappend_21_) in - (match (reg_name_matches_prefix _stringappend_22_) with - | Some (rd,(existT _ _stringappend_23_ _)) => returnm (rd, build_ex _stringappend_23_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_23_ _) => - let _stringappend_24_ := string_drop _stringappend_22_ (build_ex _stringappend_23_) in - sep_matches_prefix _stringappend_24_ >>= fun w__39 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__39 with - | Some (tt,(existT _ _stringappend_25_ _)) => returnm (tt, build_ex _stringappend_25_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_25_ _) => - let _stringappend_26_ := string_drop _stringappend_24_ (build_ex _stringappend_25_) in - (match (reg_name_matches_prefix _stringappend_26_) with - | Some (rs1,(existT _ _stringappend_27_ _)) => - returnm (rs1, build_ex _stringappend_27_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_27_ _) => - let _stringappend_28_ := string_drop _stringappend_26_ (build_ex _stringappend_27_) in - sep_matches_prefix _stringappend_28_ >>= fun w__44 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__44 with - | Some (tt,(existT _ _stringappend_29_ _)) => returnm (tt, build_ex _stringappend_29_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_29_ _) => - let _stringappend_30_ := string_drop _stringappend_28_ (build_ex _stringappend_29_) in - (match (hex_bits_12_matches_prefix _stringappend_30_) with - | Some (imm,(existT _ _stringappend_31_ _)) => - returnm (imm, build_ex _stringappend_31_) - | _ => exit tt : M ((mword 12 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_31_ _) => - returnm ((match (string_drop _stringappend_30_ (build_ex _stringappend_31_)) with - | s_ => - Some - ((RISCV_JALR - (imm, rs1, rd), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= 0)}))) - else - match (btype_mnemonic_matches_prefix _stringappend_0_) with - | Some (op,(existT _ _stringappend_33_ _)) => - let _stringappend_34_ := string_drop _stringappend_0_ (build_ex _stringappend_33_) in - match (spc_matches_prefix _stringappend_34_) with - | Some (tt,(existT _ _stringappend_35_ _)) => - let _stringappend_36_ := - string_drop _stringappend_34_ (build_ex _stringappend_35_) in - match (reg_name_matches_prefix _stringappend_36_) with - | Some (rs1,(existT _ _stringappend_37_ _)) => - let _stringappend_38_ := - string_drop _stringappend_36_ (build_ex _stringappend_37_) in - sep_matches_prefix _stringappend_38_ >>= fun w__49 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__49 with - | Some (tt,(existT _ _stringappend_39_ _)) => - let _stringappend_40_ := - string_drop _stringappend_38_ (build_ex _stringappend_39_) in - match (reg_name_matches_prefix _stringappend_40_) with - | Some (rs2,(existT _ _stringappend_41_ _)) => - let _stringappend_42_ := - string_drop _stringappend_40_ (build_ex _stringappend_41_) in - sep_matches_prefix _stringappend_42_ >>= fun w__50 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__50 with - | Some (tt,(existT _ _stringappend_43_ _)) => - let _stringappend_44_ := - string_drop _stringappend_42_ - (build_ex _stringappend_43_) in - if ((match (hex_bits_13_matches_prefix - _stringappend_44_) with - | Some (imm,(existT _ _stringappend_45_ _)) => - match (string_drop _stringappend_44_ - (build_ex _stringappend_45_)) with - | s_ => true - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__51 : bool => - returnm ((if (w__51) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__52 : bool => - returnm ((if (w__52) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__53 : bool => - returnm ((if (w__53) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__54 : bool => - returnm ((if (w__54) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__55 : bool => - (if (w__55) then - (match (btype_mnemonic_matches_prefix _stringappend_0_) with - | Some (op,(existT _ _stringappend_33_ _)) => - returnm (op, build_ex _stringappend_33_) - | _ => exit tt : M ((bop * {n : Z & ArithFact (n >= 0)})) - end : M ((bop * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_33_ _) => - let _stringappend_34_ := string_drop _stringappend_0_ (build_ex _stringappend_33_) in - (match (spc_matches_prefix _stringappend_34_) with - | Some (tt,(existT _ _stringappend_35_ _)) => - returnm (tt, build_ex _stringappend_35_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_35_ _) => - let _stringappend_36_ := string_drop _stringappend_34_ (build_ex _stringappend_35_) in - (match (reg_name_matches_prefix _stringappend_36_) with - | Some (rs1,(existT _ _stringappend_37_ _)) => - returnm (rs1, build_ex _stringappend_37_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_37_ _) => - let _stringappend_38_ := string_drop _stringappend_36_ (build_ex _stringappend_37_) in - sep_matches_prefix _stringappend_38_ >>= fun w__62 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__62 with - | Some (tt,(existT _ _stringappend_39_ _)) => - returnm (tt, build_ex _stringappend_39_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_39_ _) => - let _stringappend_40_ := string_drop _stringappend_38_ (build_ex _stringappend_39_) in - (match (reg_name_matches_prefix _stringappend_40_) with - | Some (rs2,(existT _ _stringappend_41_ _)) => - returnm (rs2, build_ex _stringappend_41_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs2, existT _ _stringappend_41_ _) => - let _stringappend_42_ := string_drop _stringappend_40_ (build_ex _stringappend_41_) in - sep_matches_prefix _stringappend_42_ >>= fun w__67 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__67 with - | Some (tt,(existT _ _stringappend_43_ _)) => - returnm (tt, build_ex _stringappend_43_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_43_ _) => - let _stringappend_44_ := string_drop _stringappend_42_ (build_ex _stringappend_43_) in - (match (hex_bits_13_matches_prefix _stringappend_44_) with - | Some (imm,(existT _ _stringappend_45_ _)) => - returnm (imm, build_ex _stringappend_45_) - | _ => exit tt : M ((mword 13 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 13 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_45_ _) => - returnm ((match (string_drop _stringappend_44_ (build_ex _stringappend_45_)) with - | s_ => - Some - ((BTYPE - (imm, rs2, rs1, op), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= 0)}))) - else - match (itype_mnemonic_matches_prefix _stringappend_0_) with - | Some (op,(existT _ _stringappend_47_ _)) => - let _stringappend_48_ := string_drop _stringappend_0_ (build_ex _stringappend_47_) in - match (spc_matches_prefix _stringappend_48_) with - | Some (tt,(existT _ _stringappend_49_ _)) => - let _stringappend_50_ := - string_drop _stringappend_48_ (build_ex _stringappend_49_) in - match (reg_name_matches_prefix _stringappend_50_) with - | Some (rd,(existT _ _stringappend_51_ _)) => - let _stringappend_52_ := - string_drop _stringappend_50_ (build_ex _stringappend_51_) in - sep_matches_prefix _stringappend_52_ >>= fun w__72 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__72 with - | Some (tt,(existT _ _stringappend_53_ _)) => - let _stringappend_54_ := - string_drop _stringappend_52_ (build_ex _stringappend_53_) in - match (reg_name_matches_prefix _stringappend_54_) with - | Some (rs1,(existT _ _stringappend_55_ _)) => - let _stringappend_56_ := - string_drop _stringappend_54_ (build_ex _stringappend_55_) in - sep_matches_prefix _stringappend_56_ >>= fun w__73 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__73 with - | Some (tt,(existT _ _stringappend_57_ _)) => - let _stringappend_58_ := - string_drop _stringappend_56_ - (build_ex _stringappend_57_) in - if ((match (hex_bits_12_matches_prefix - _stringappend_58_) with - | Some (imm,(existT _ _stringappend_59_ _)) => - match (string_drop _stringappend_58_ - (build_ex _stringappend_59_)) with - | s_ => true - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__74 : bool => - returnm ((if (w__74) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__75 : bool => - returnm ((if (w__75) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__76 : bool => - returnm ((if (w__76) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__77 : bool => - returnm ((if (w__77) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__78 : bool => - (if (w__78) then - (match (itype_mnemonic_matches_prefix _stringappend_0_) with - | Some (op,(existT _ _stringappend_47_ _)) => - returnm (op, build_ex _stringappend_47_) - | _ => exit tt : M ((iop * {n : Z & ArithFact (n >= 0)})) - end : M ((iop * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_47_ _) => - let _stringappend_48_ := string_drop _stringappend_0_ (build_ex _stringappend_47_) in - (match (spc_matches_prefix _stringappend_48_) with - | Some (tt,(existT _ _stringappend_49_ _)) => - returnm (tt, build_ex _stringappend_49_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_49_ _) => - let _stringappend_50_ := - string_drop _stringappend_48_ (build_ex _stringappend_49_) in - (match (reg_name_matches_prefix _stringappend_50_) with - | Some (rd,(existT _ _stringappend_51_ _)) => - returnm (rd, build_ex _stringappend_51_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_51_ _) => - let _stringappend_52_ := - string_drop _stringappend_50_ (build_ex _stringappend_51_) in - sep_matches_prefix _stringappend_52_ >>= fun w__85 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__85 with - | Some (tt,(existT _ _stringappend_53_ _)) => - returnm (tt, build_ex _stringappend_53_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_53_ _) => - let _stringappend_54_ := - string_drop _stringappend_52_ (build_ex _stringappend_53_) in - (match (reg_name_matches_prefix _stringappend_54_) with - | Some (rs1,(existT _ _stringappend_55_ _)) => - returnm (rs1, build_ex _stringappend_55_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_55_ _) => - let _stringappend_56_ := - string_drop _stringappend_54_ (build_ex _stringappend_55_) in - sep_matches_prefix _stringappend_56_ >>= fun w__90 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__90 with - | Some (tt,(existT _ _stringappend_57_ _)) => - returnm (tt, build_ex _stringappend_57_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_57_ _) => - let _stringappend_58_ := - string_drop _stringappend_56_ (build_ex _stringappend_57_) in - (match (hex_bits_12_matches_prefix _stringappend_58_) with - | Some (imm,(existT _ _stringappend_59_ _)) => - returnm (imm, build_ex _stringappend_59_) - | _ => exit tt : M ((mword 12 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_59_ _) => - returnm ((match (string_drop _stringappend_58_ (build_ex _stringappend_59_)) with - | s_ => - Some - ((ITYPE - (imm, rs1, rd, op), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= 0)}))) - else - match (shiftiop_mnemonic_matches_prefix _stringappend_0_) with - | Some (op,(existT _ _stringappend_61_ _)) => - let _stringappend_62_ := - string_drop _stringappend_0_ (build_ex _stringappend_61_) in - match (spc_matches_prefix _stringappend_62_) with - | Some (tt,(existT _ _stringappend_63_ _)) => - let _stringappend_64_ := - string_drop _stringappend_62_ (build_ex _stringappend_63_) in - match (reg_name_matches_prefix _stringappend_64_) with - | Some (rd,(existT _ _stringappend_65_ _)) => - let _stringappend_66_ := - string_drop _stringappend_64_ (build_ex _stringappend_65_) in - sep_matches_prefix _stringappend_66_ >>= fun w__95 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__95 with - | Some (tt,(existT _ _stringappend_67_ _)) => - let _stringappend_68_ := - string_drop _stringappend_66_ - (build_ex _stringappend_67_) in - if ((match (reg_name_matches_prefix _stringappend_68_) with - | Some (rs1,(existT _ _stringappend_69_ _)) => - let _stringappend_70_ := - string_drop _stringappend_68_ - (build_ex _stringappend_69_) in - if ((match (hex_bits_6_matches_prefix - _stringappend_70_) with - | Some - (shamt,(existT _ _stringappend_71_ _)) => - match (string_drop _stringappend_70_ - (build_ex _stringappend_71_)) with - | s_ => true - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__96 : bool => - returnm ((if (w__96) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__97 : bool => - returnm ((if (w__97) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__98 : bool => - (if (w__98) then - (match (shiftiop_mnemonic_matches_prefix _stringappend_0_) with - | Some (op,(existT _ _stringappend_61_ _)) => - returnm (op, build_ex _stringappend_61_) - | _ => exit tt : M ((sop * {n : Z & ArithFact (n >= 0)})) - end : M ((sop * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_61_ _) => - let _stringappend_62_ := - string_drop _stringappend_0_ (build_ex _stringappend_61_) in - (match (spc_matches_prefix _stringappend_62_) with - | Some (tt,(existT _ _stringappend_63_ _)) => - returnm (tt, build_ex _stringappend_63_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_63_ _) => - let _stringappend_64_ := - string_drop _stringappend_62_ (build_ex _stringappend_63_) in - (match (reg_name_matches_prefix _stringappend_64_) with - | Some (rd,(existT _ _stringappend_65_ _)) => - returnm (rd, build_ex _stringappend_65_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_65_ _) => - let _stringappend_66_ := - string_drop _stringappend_64_ (build_ex _stringappend_65_) in - sep_matches_prefix _stringappend_66_ >>= fun w__105 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__105 with - | Some (tt,(existT _ _stringappend_67_ _)) => - returnm (tt, build_ex _stringappend_67_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_67_ _) => - let _stringappend_68_ := - string_drop _stringappend_66_ (build_ex _stringappend_67_) in - (match (reg_name_matches_prefix _stringappend_68_) with - | Some (rs1,(existT _ _stringappend_69_ _)) => - returnm (rs1, build_ex _stringappend_69_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_69_ _) => - let _stringappend_70_ := - string_drop _stringappend_68_ (build_ex _stringappend_69_) in - (match (hex_bits_6_matches_prefix _stringappend_70_) with - | Some (shamt,(existT _ _stringappend_71_ _)) => - returnm (shamt, build_ex _stringappend_71_) - | _ => exit tt : M ((mword 6 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 6 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(shamt, existT _ _stringappend_71_ _) => - returnm ((match (string_drop _stringappend_70_ (build_ex _stringappend_71_)) with - | s_ => - Some - ((SHIFTIOP - (shamt, rs1, rd, op), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= 0)}))) - else - match (rtype_mnemonic_matches_prefix _stringappend_0_) with - | Some (op,(existT _ _stringappend_73_ _)) => - let _stringappend_74_ := - string_drop _stringappend_0_ (build_ex _stringappend_73_) in - match (spc_matches_prefix _stringappend_74_) with - | Some (tt,(existT _ _stringappend_75_ _)) => - let _stringappend_76_ := - string_drop _stringappend_74_ (build_ex _stringappend_75_) in - match (reg_name_matches_prefix _stringappend_76_) with - | Some (rd,(existT _ _stringappend_77_ _)) => - let _stringappend_78_ := - string_drop _stringappend_76_ (build_ex _stringappend_77_) in - sep_matches_prefix _stringappend_78_ >>= fun w__112 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__112 with - | Some (tt,(existT _ _stringappend_79_ _)) => - let _stringappend_80_ := - string_drop _stringappend_78_ (build_ex _stringappend_79_) in - match (reg_name_matches_prefix _stringappend_80_) with - | Some (rs1,(existT _ _stringappend_81_ _)) => - let _stringappend_82_ := - string_drop _stringappend_80_ (build_ex _stringappend_81_) in - sep_matches_prefix _stringappend_82_ >>= fun w__113 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__113 with - | Some (tt,(existT _ _stringappend_83_ _)) => - let _stringappend_84_ := - string_drop _stringappend_82_ - (build_ex _stringappend_83_) in - if ((match (reg_name_matches_prefix - _stringappend_84_) with - | Some - (rs2,(existT _ _stringappend_85_ _)) => - match (string_drop _stringappend_84_ - (build_ex _stringappend_85_)) with - | s_ => true - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__114 : bool => - returnm ((if (w__114) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__115 : bool => - returnm ((if (w__115) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__116 : bool => - returnm ((if (w__116) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__117 : bool => - returnm ((if (w__117) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__118 : bool => - (if (w__118) then - (match (rtype_mnemonic_matches_prefix _stringappend_0_) with - | Some (op,(existT _ _stringappend_73_ _)) => - returnm (op, build_ex _stringappend_73_) - | _ => exit tt : M ((rop * {n : Z & ArithFact (n >= 0)})) - end : M ((rop * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_73_ _) => - let _stringappend_74_ := - string_drop _stringappend_0_ (build_ex _stringappend_73_) in - (match (spc_matches_prefix _stringappend_74_) with - | Some (tt,(existT _ _stringappend_75_ _)) => - returnm (tt, build_ex _stringappend_75_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_75_ _) => - let _stringappend_76_ := - string_drop _stringappend_74_ (build_ex _stringappend_75_) in - (match (reg_name_matches_prefix _stringappend_76_) with - | Some (rd,(existT _ _stringappend_77_ _)) => - returnm (rd, build_ex _stringappend_77_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_77_ _) => - let _stringappend_78_ := - string_drop _stringappend_76_ (build_ex _stringappend_77_) in - sep_matches_prefix _stringappend_78_ >>= fun w__125 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__125 with - | Some (tt,(existT _ _stringappend_79_ _)) => - returnm (tt, build_ex _stringappend_79_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_79_ _) => - let _stringappend_80_ := - string_drop _stringappend_78_ (build_ex _stringappend_79_) in - (match (reg_name_matches_prefix _stringappend_80_) with - | Some (rs1,(existT _ _stringappend_81_ _)) => - returnm (rs1, build_ex _stringappend_81_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_81_ _) => - let _stringappend_82_ := - string_drop _stringappend_80_ (build_ex _stringappend_81_) in - sep_matches_prefix _stringappend_82_ >>= fun w__130 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__130 with - | Some (tt,(existT _ _stringappend_83_ _)) => - returnm (tt, build_ex _stringappend_83_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_83_ _) => - let _stringappend_84_ := - string_drop _stringappend_82_ (build_ex _stringappend_83_) in - (match (reg_name_matches_prefix _stringappend_84_) with - | Some (rs2,(existT _ _stringappend_85_ _)) => - returnm (rs2, build_ex _stringappend_85_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs2, existT _ _stringappend_85_ _) => - returnm ((match (string_drop _stringappend_84_ (build_ex _stringappend_85_)) with - | s_ => - Some - ((RTYPE - (rs2, rs1, rd, op), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= 0)}))) - else - and_boolM (returnm ((string_startswith _stringappend_0_ "l") : bool)) - (let _stringappend_87_ := - string_drop _stringappend_0_ (build_ex (projT1 (string_length "l"))) in - match (size_mnemonic_matches_prefix _stringappend_87_) with - | Some (size,(existT _ _stringappend_88_ _)) => - let _stringappend_89_ := - string_drop _stringappend_87_ (build_ex _stringappend_88_) in - match (maybe_u_matches_prefix _stringappend_89_) with - | Some (is_unsigned,(existT _ _stringappend_90_ _)) => - let _stringappend_91_ := - string_drop _stringappend_89_ (build_ex _stringappend_90_) in - match (maybe_aq_matches_prefix _stringappend_91_) with - | Some (aq,(existT _ _stringappend_92_ _)) => - let _stringappend_93_ := - string_drop _stringappend_91_ (build_ex _stringappend_92_) in - match (maybe_rl_matches_prefix _stringappend_93_) with - | Some (rl,(existT _ _stringappend_94_ _)) => - let _stringappend_95_ := - string_drop _stringappend_93_ (build_ex _stringappend_94_) in - match (spc_matches_prefix _stringappend_95_) with - | Some (tt,(existT _ _stringappend_96_ _)) => - let _stringappend_97_ := - string_drop _stringappend_95_ - (build_ex _stringappend_96_) in - match (reg_name_matches_prefix _stringappend_97_) with - | Some (rd,(existT _ _stringappend_98_ _)) => - let _stringappend_99_ := - string_drop _stringappend_97_ - (build_ex _stringappend_98_) in - sep_matches_prefix _stringappend_99_ >>= fun w__135 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__135 with - | Some (tt,(existT _ _stringappend_100_ _)) => - let _stringappend_101_ := - string_drop _stringappend_99_ - (build_ex _stringappend_100_) in - match (reg_name_matches_prefix _stringappend_101_) with - | Some (rs1,(existT _ _stringappend_102_ _)) => - let _stringappend_103_ := - string_drop _stringappend_101_ - (build_ex _stringappend_102_) in - sep_matches_prefix _stringappend_103_ >>= fun w__136 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__136 with - | Some - (tt,(existT _ _stringappend_104_ _)) => - let _stringappend_105_ := - string_drop _stringappend_103_ - (build_ex _stringappend_104_) in - if ((match (hex_bits_12_matches_prefix - _stringappend_105_) with - | Some - (imm,(existT _ _stringappend_106_ _)) => - match (string_drop - _stringappend_105_ - (build_ex _stringappend_106_)) with - | s_ => true - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__137 : bool => - returnm ((if (w__137) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__138 : bool => - returnm ((if (w__138) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__139 : bool => - returnm ((if (w__139) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__140 : bool => - returnm ((if (w__140) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__141 : bool => - returnm ((if (w__141) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__142 : bool => - returnm ((if (w__142) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__143 : bool => - returnm ((if (w__143) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__144 : bool => - returnm ((if (w__144) then true - else false) - : bool)) >>= fun w__145 : bool => - (if (w__145) then - let _stringappend_87_ := - string_drop _stringappend_0_ (build_ex (projT1 (string_length "l"))) in - (match (size_mnemonic_matches_prefix _stringappend_87_) with - | Some (size,(existT _ _stringappend_88_ _)) => - returnm (size, build_ex _stringappend_88_) - | _ => exit tt : M ((word_width * {n : Z & ArithFact (n >= 0)})) - end : M ((word_width * {n : Z & ArithFact (n >= 0)}))) >>= fun '(size, existT _ _stringappend_88_ _) => - let _stringappend_89_ := - string_drop _stringappend_87_ (build_ex _stringappend_88_) in - (match (maybe_u_matches_prefix _stringappend_89_) with - | Some (is_unsigned,(existT _ _stringappend_90_ _)) => - returnm (is_unsigned, build_ex _stringappend_90_) - | _ => exit tt : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(is_unsigned, existT _ _stringappend_90_ _) => - let _stringappend_91_ := - string_drop _stringappend_89_ (build_ex _stringappend_90_) in - (match (maybe_aq_matches_prefix _stringappend_91_) with - | Some (aq,(existT _ _stringappend_92_ _)) => - returnm (aq, build_ex _stringappend_92_) - | _ => exit tt : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(aq, existT _ _stringappend_92_ _) => - let _stringappend_93_ := - string_drop _stringappend_91_ (build_ex _stringappend_92_) in - (match (maybe_rl_matches_prefix _stringappend_93_) with - | Some (rl,(existT _ _stringappend_94_ _)) => - returnm (rl, build_ex _stringappend_94_) - | _ => exit tt : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rl, existT _ _stringappend_94_ _) => - let _stringappend_95_ := - string_drop _stringappend_93_ (build_ex _stringappend_94_) in - (match (spc_matches_prefix _stringappend_95_) with - | Some (tt,(existT _ _stringappend_96_ _)) => - returnm (tt, build_ex _stringappend_96_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_96_ _) => - let _stringappend_97_ := - string_drop _stringappend_95_ (build_ex _stringappend_96_) in - (match (reg_name_matches_prefix _stringappend_97_) with - | Some (rd,(existT _ _stringappend_98_ _)) => - returnm (rd, build_ex _stringappend_98_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_98_ _) => - let _stringappend_99_ := - string_drop _stringappend_97_ (build_ex _stringappend_98_) in - sep_matches_prefix _stringappend_99_ >>= fun w__158 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__158 with - | Some (tt,(existT _ _stringappend_100_ _)) => - returnm (tt, build_ex _stringappend_100_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_100_ _) => - let _stringappend_101_ := - string_drop _stringappend_99_ (build_ex _stringappend_100_) in - (match (reg_name_matches_prefix _stringappend_101_) with - | Some (rs1,(existT _ _stringappend_102_ _)) => - returnm (rs1, build_ex _stringappend_102_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_102_ _) => - let _stringappend_103_ := - string_drop _stringappend_101_ (build_ex _stringappend_102_) in - sep_matches_prefix _stringappend_103_ >>= fun w__163 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__163 with - | Some (tt,(existT _ _stringappend_104_ _)) => - returnm (tt, build_ex _stringappend_104_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_104_ _) => - let _stringappend_105_ := - string_drop _stringappend_103_ (build_ex _stringappend_104_) in - (match (hex_bits_12_matches_prefix _stringappend_105_) with - | Some (imm,(existT _ _stringappend_106_ _)) => - returnm (imm, build_ex _stringappend_106_) - | _ => exit tt : M ((mword 12 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_106_ _) => - returnm ((match (string_drop _stringappend_105_ - (build_ex _stringappend_106_)) with - | s_ => - Some - ((LOAD - (imm, rs1, rd, is_unsigned, size, aq, rl), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= 0)}))) - else - and_boolM (returnm ((string_startswith _stringappend_0_ "s") : bool)) - (let _stringappend_108_ := - string_drop _stringappend_0_ (build_ex (projT1 (string_length "s"))) in - match (size_mnemonic_matches_prefix _stringappend_108_) with - | Some (size,(existT _ _stringappend_109_ _)) => - let _stringappend_110_ := - string_drop _stringappend_108_ (build_ex _stringappend_109_) in - match (maybe_aq_matches_prefix _stringappend_110_) with - | Some (aq,(existT _ _stringappend_111_ _)) => - let _stringappend_112_ := - string_drop _stringappend_110_ (build_ex _stringappend_111_) in - match (maybe_rl_matches_prefix _stringappend_112_) with - | Some (rl,(existT _ _stringappend_113_ _)) => - let _stringappend_114_ := - string_drop _stringappend_112_ (build_ex _stringappend_113_) in - match (spc_matches_prefix _stringappend_114_) with - | Some (tt,(existT _ _stringappend_115_ _)) => - let _stringappend_116_ := - string_drop _stringappend_114_ - (build_ex _stringappend_115_) in - match (reg_name_matches_prefix _stringappend_116_) with - | Some (rd,(existT _ _stringappend_117_ _)) => - let _stringappend_118_ := - string_drop _stringappend_116_ - (build_ex _stringappend_117_) in - sep_matches_prefix _stringappend_118_ >>= fun w__168 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__168 with - | Some (tt,(existT _ _stringappend_119_ _)) => - let _stringappend_120_ := - string_drop _stringappend_118_ - (build_ex _stringappend_119_) in - match (reg_name_matches_prefix _stringappend_120_) with - | Some (rs1,(existT _ _stringappend_121_ _)) => - let _stringappend_122_ := - string_drop _stringappend_120_ - (build_ex _stringappend_121_) in - sep_matches_prefix _stringappend_122_ >>= fun w__169 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__169 with - | Some - (tt,(existT _ _stringappend_123_ _)) => - let _stringappend_124_ := - string_drop _stringappend_122_ - (build_ex _stringappend_123_) in - if ((match (hex_bits_12_matches_prefix - _stringappend_124_) with - | Some - (imm,(existT _ _stringappend_125_ _)) => - match (string_drop - _stringappend_124_ - (build_ex _stringappend_125_)) with - | s_ => true - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__170 : bool => - returnm ((if (w__170) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__171 : bool => - returnm ((if (w__171) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__172 : bool => - returnm ((if (w__172) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__173 : bool => - returnm ((if (w__173) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__174 : bool => - returnm ((if (w__174) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__175 : bool => - returnm ((if (w__175) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__176 : bool => - returnm ((if (w__176) then true - else false) - : bool)) >>= fun w__177 : bool => - (if (w__177) then - let _stringappend_108_ := - string_drop _stringappend_0_ (build_ex (projT1 (string_length "s"))) in - (match (size_mnemonic_matches_prefix _stringappend_108_) with - | Some (size,(existT _ _stringappend_109_ _)) => - returnm (size, build_ex _stringappend_109_) - | _ => exit tt : M ((word_width * {n : Z & ArithFact (n >= 0)})) - end : M ((word_width * {n : Z & ArithFact (n >= 0)}))) >>= fun '(size, existT _ _stringappend_109_ _) => - let _stringappend_110_ := - string_drop _stringappend_108_ (build_ex _stringappend_109_) in - (match (maybe_aq_matches_prefix _stringappend_110_) with - | Some (aq,(existT _ _stringappend_111_ _)) => - returnm (aq, build_ex _stringappend_111_) - | _ => exit tt : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(aq, existT _ _stringappend_111_ _) => - let _stringappend_112_ := - string_drop _stringappend_110_ (build_ex _stringappend_111_) in - (match (maybe_rl_matches_prefix _stringappend_112_) with - | Some (rl,(existT _ _stringappend_113_ _)) => - returnm (rl, build_ex _stringappend_113_) - | _ => exit tt : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rl, existT _ _stringappend_113_ _) => - let _stringappend_114_ := - string_drop _stringappend_112_ (build_ex _stringappend_113_) in - (match (spc_matches_prefix _stringappend_114_) with - | Some (tt,(existT _ _stringappend_115_ _)) => - returnm (tt, build_ex _stringappend_115_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_115_ _) => - let _stringappend_116_ := - string_drop _stringappend_114_ (build_ex _stringappend_115_) in - (match (reg_name_matches_prefix _stringappend_116_) with - | Some (rd,(existT _ _stringappend_117_ _)) => - returnm (rd, build_ex _stringappend_117_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_117_ _) => - let _stringappend_118_ := - string_drop _stringappend_116_ (build_ex _stringappend_117_) in - sep_matches_prefix _stringappend_118_ >>= fun w__188 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__188 with - | Some (tt,(existT _ _stringappend_119_ _)) => - returnm (tt, build_ex _stringappend_119_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_119_ _) => - let _stringappend_120_ := - string_drop _stringappend_118_ (build_ex _stringappend_119_) in - (match (reg_name_matches_prefix _stringappend_120_) with - | Some (rs1,(existT _ _stringappend_121_ _)) => - returnm (rs1, build_ex _stringappend_121_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_121_ _) => - let _stringappend_122_ := - string_drop _stringappend_120_ (build_ex _stringappend_121_) in - sep_matches_prefix _stringappend_122_ >>= fun w__193 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__193 with - | Some (tt,(existT _ _stringappend_123_ _)) => - returnm (tt, build_ex _stringappend_123_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_123_ _) => - let _stringappend_124_ := - string_drop _stringappend_122_ (build_ex _stringappend_123_) in - (match (hex_bits_12_matches_prefix _stringappend_124_) with - | Some (imm,(existT _ _stringappend_125_ _)) => - returnm (imm, build_ex _stringappend_125_) - | _ => exit tt : M ((mword 12 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_125_ _) => - returnm ((match (string_drop _stringappend_124_ - (build_ex _stringappend_125_)) with - | s_ => - Some - ((STORE - (imm, rs1, rd, size, aq, rl), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= 0)}))) - else - and_boolM - (returnm ((string_startswith _stringappend_0_ "addiw") - : bool)) - (let _stringappend_127_ := - string_drop _stringappend_0_ - (build_ex (projT1 (string_length "addiw"))) in - match (spc_matches_prefix _stringappend_127_) with - | Some (tt,(existT _ _stringappend_128_ _)) => - let _stringappend_129_ := - string_drop _stringappend_127_ (build_ex _stringappend_128_) in - match (reg_name_matches_prefix _stringappend_129_) with - | Some (rd,(existT _ _stringappend_130_ _)) => - let _stringappend_131_ := - string_drop _stringappend_129_ (build_ex _stringappend_130_) in - sep_matches_prefix _stringappend_131_ >>= fun w__198 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__198 with - | Some (tt,(existT _ _stringappend_132_ _)) => - let _stringappend_133_ := - string_drop _stringappend_131_ - (build_ex _stringappend_132_) in - match (reg_name_matches_prefix _stringappend_133_) with - | Some (rs1,(existT _ _stringappend_134_ _)) => - let _stringappend_135_ := - string_drop _stringappend_133_ - (build_ex _stringappend_134_) in - sep_matches_prefix _stringappend_135_ >>= fun w__199 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__199 with - | Some - (tt,(existT _ _stringappend_136_ _)) => - let _stringappend_137_ := - string_drop _stringappend_135_ - (build_ex _stringappend_136_) in - if ((match (hex_bits_12_matches_prefix - _stringappend_137_) with - | Some - (imm,(existT _ _stringappend_138_ _)) => - match (string_drop - _stringappend_137_ - (build_ex _stringappend_138_)) with - | s_ => true - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__200 : bool => - returnm ((if (w__200) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__201 : bool => - returnm ((if (w__201) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__202 : bool => - returnm ((if (w__202) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__203 : bool => - returnm ((if (w__203) then true - else false) - : bool)) >>= fun w__204 : bool => - (if (w__204) then - let _stringappend_127_ := - string_drop _stringappend_0_ - (build_ex (projT1 (string_length "addiw"))) in - (match (spc_matches_prefix _stringappend_127_) with - | Some (tt,(existT _ _stringappend_128_ _)) => - returnm (tt, build_ex _stringappend_128_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_128_ _) => - let _stringappend_129_ := - string_drop _stringappend_127_ (build_ex _stringappend_128_) in - (match (reg_name_matches_prefix _stringappend_129_) with - | Some (rd,(existT _ _stringappend_130_ _)) => - returnm (rd, build_ex _stringappend_130_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_130_ _) => - let _stringappend_131_ := - string_drop _stringappend_129_ (build_ex _stringappend_130_) in - sep_matches_prefix _stringappend_131_ >>= fun w__209 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__209 with - | Some (tt,(existT _ _stringappend_132_ _)) => - returnm (tt, build_ex _stringappend_132_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_132_ _) => - let _stringappend_133_ := - string_drop _stringappend_131_ (build_ex _stringappend_132_) in - (match (reg_name_matches_prefix _stringappend_133_) with - | Some (rs1,(existT _ _stringappend_134_ _)) => - returnm (rs1, build_ex _stringappend_134_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_134_ _) => - let _stringappend_135_ := - string_drop _stringappend_133_ (build_ex _stringappend_134_) in - sep_matches_prefix _stringappend_135_ >>= fun w__214 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__214 with - | Some (tt,(existT _ _stringappend_136_ _)) => - returnm (tt, build_ex _stringappend_136_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_136_ _) => - let _stringappend_137_ := - string_drop _stringappend_135_ (build_ex _stringappend_136_) in - (match (hex_bits_12_matches_prefix _stringappend_137_) with - | Some (imm,(existT _ _stringappend_138_ _)) => - returnm (imm, build_ex _stringappend_138_) - | _ => exit tt : M ((mword 12 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(imm, existT _ _stringappend_138_ _) => - returnm ((match (string_drop _stringappend_137_ - (build_ex _stringappend_138_)) with - | s_ => - Some - ((ADDIW - (imm, rs1, rd), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= 0)}))) - else - match (shiftw_mnemonic_matches_prefix _stringappend_0_) with - | Some (op,(existT _ _stringappend_140_ _)) => - let _stringappend_141_ := - string_drop _stringappend_0_ (build_ex _stringappend_140_) in - match (spc_matches_prefix _stringappend_141_) with - | Some (tt,(existT _ _stringappend_142_ _)) => - let _stringappend_143_ := - string_drop _stringappend_141_ - (build_ex _stringappend_142_) in - match (reg_name_matches_prefix _stringappend_143_) with - | Some (rd,(existT _ _stringappend_144_ _)) => - let _stringappend_145_ := - string_drop _stringappend_143_ - (build_ex _stringappend_144_) in - sep_matches_prefix _stringappend_145_ >>= fun w__219 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__219 with - | Some (tt,(existT _ _stringappend_146_ _)) => - let _stringappend_147_ := - string_drop _stringappend_145_ - (build_ex _stringappend_146_) in - match (reg_name_matches_prefix _stringappend_147_) with - | Some (rs1,(existT _ _stringappend_148_ _)) => - let _stringappend_149_ := - string_drop _stringappend_147_ - (build_ex _stringappend_148_) in - sep_matches_prefix _stringappend_149_ >>= fun w__220 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__220 with - | Some - (tt,(existT _ _stringappend_150_ _)) => - let _stringappend_151_ := - string_drop _stringappend_149_ - (build_ex _stringappend_150_) in - if ((match (hex_bits_5_matches_prefix - _stringappend_151_) with - | Some - (shamt,(existT _ _stringappend_152_ _)) => - match (string_drop - _stringappend_151_ - (build_ex _stringappend_152_)) with - | s_ => true - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__221 : bool => - returnm ((if (w__221) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__222 : bool => - returnm ((if (w__222) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__223 : bool => - returnm ((if (w__223) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__224 : bool => - returnm ((if (w__224) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__225 : bool => - (if (w__225) then - (match (shiftw_mnemonic_matches_prefix _stringappend_0_) with - | Some (op,(existT _ _stringappend_140_ _)) => - returnm (op, build_ex _stringappend_140_) - | _ => exit tt : M ((sop * {n : Z & ArithFact (n >= 0)})) - end : M ((sop * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_140_ _) => - let _stringappend_141_ := - string_drop _stringappend_0_ (build_ex _stringappend_140_) in - (match (spc_matches_prefix _stringappend_141_) with - | Some (tt,(existT _ _stringappend_142_ _)) => - returnm (tt, build_ex _stringappend_142_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_142_ _) => - let _stringappend_143_ := - string_drop _stringappend_141_ (build_ex _stringappend_142_) in - (match (reg_name_matches_prefix _stringappend_143_) with - | Some (rd,(existT _ _stringappend_144_ _)) => - returnm (rd, build_ex _stringappend_144_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_144_ _) => - let _stringappend_145_ := - string_drop _stringappend_143_ (build_ex _stringappend_144_) in - sep_matches_prefix _stringappend_145_ >>= fun w__232 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__232 with - | Some (tt,(existT _ _stringappend_146_ _)) => - returnm (tt, build_ex _stringappend_146_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_146_ _) => - let _stringappend_147_ := - string_drop _stringappend_145_ (build_ex _stringappend_146_) in - (match (reg_name_matches_prefix _stringappend_147_) with - | Some (rs1,(existT _ _stringappend_148_ _)) => - returnm (rs1, build_ex _stringappend_148_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_148_ _) => - let _stringappend_149_ := - string_drop _stringappend_147_ (build_ex _stringappend_148_) in - sep_matches_prefix _stringappend_149_ >>= fun w__237 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__237 with - | Some (tt,(existT _ _stringappend_150_ _)) => - returnm (tt, build_ex _stringappend_150_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_150_ _) => - let _stringappend_151_ := - string_drop _stringappend_149_ (build_ex _stringappend_150_) in - (match (hex_bits_5_matches_prefix _stringappend_151_) with - | Some (shamt,(existT _ _stringappend_152_ _)) => - returnm (shamt, build_ex _stringappend_152_) - | _ => exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(shamt, existT _ _stringappend_152_ _) => - returnm ((match (string_drop _stringappend_151_ - (build_ex _stringappend_152_)) with - | s_ => - Some - ((SHIFTW - (shamt, rs1, rd, op), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= 0)}))) - else - match (rtypew_mnemonic_matches_prefix _stringappend_0_) with - | Some (op,(existT _ _stringappend_154_ _)) => - let _stringappend_155_ := - string_drop _stringappend_0_ (build_ex _stringappend_154_) in - match (spc_matches_prefix _stringappend_155_) with - | Some (tt,(existT _ _stringappend_156_ _)) => - let _stringappend_157_ := - string_drop _stringappend_155_ - (build_ex _stringappend_156_) in - match (reg_name_matches_prefix _stringappend_157_) with - | Some (rd,(existT _ _stringappend_158_ _)) => - let _stringappend_159_ := - string_drop _stringappend_157_ - (build_ex _stringappend_158_) in - sep_matches_prefix _stringappend_159_ >>= fun w__242 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__242 with - | Some (tt,(existT _ _stringappend_160_ _)) => - let _stringappend_161_ := - string_drop _stringappend_159_ - (build_ex _stringappend_160_) in - match (reg_name_matches_prefix _stringappend_161_) with - | Some (rs1,(existT _ _stringappend_162_ _)) => - let _stringappend_163_ := - string_drop _stringappend_161_ - (build_ex _stringappend_162_) in - sep_matches_prefix _stringappend_163_ >>= fun w__243 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__243 with - | Some - (tt,(existT _ _stringappend_164_ _)) => - let _stringappend_165_ := - string_drop - _stringappend_163_ - (build_ex _stringappend_164_) in - if ((match (reg_name_matches_prefix - _stringappend_165_) with - | Some - (rs2,(existT _ _stringappend_166_ _)) => - match (string_drop - _stringappend_165_ - (build_ex _stringappend_166_)) with - | s_ => true - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__244 : bool => - returnm ((if (w__244) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__245 : bool => - returnm ((if (w__245) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__246 : bool => - returnm ((if (w__246) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__247 : bool => - returnm ((if (w__247) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__248 : bool => - (if (w__248) then - (match (rtypew_mnemonic_matches_prefix _stringappend_0_) with - | Some (op,(existT _ _stringappend_154_ _)) => - returnm (op, build_ex _stringappend_154_) - | _ => exit tt : M ((ropw * {n : Z & ArithFact (n >= 0)})) - end : M ((ropw * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_154_ _) => - let _stringappend_155_ := - string_drop _stringappend_0_ (build_ex _stringappend_154_) in - (match (spc_matches_prefix _stringappend_155_) with - | Some (tt,(existT _ _stringappend_156_ _)) => - returnm (tt, build_ex _stringappend_156_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_156_ _) => - let _stringappend_157_ := - string_drop _stringappend_155_ - (build_ex _stringappend_156_) in - (match (reg_name_matches_prefix _stringappend_157_) with - | Some (rd,(existT _ _stringappend_158_ _)) => - returnm (rd, build_ex _stringappend_158_) - | _ => - exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_158_ _) => - let _stringappend_159_ := - string_drop _stringappend_157_ - (build_ex _stringappend_158_) in - sep_matches_prefix _stringappend_159_ >>= fun w__255 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__255 with - | Some (tt,(existT _ _stringappend_160_ _)) => - returnm (tt, build_ex _stringappend_160_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_160_ _) => - let _stringappend_161_ := - string_drop _stringappend_159_ - (build_ex _stringappend_160_) in - (match (reg_name_matches_prefix _stringappend_161_) with - | Some (rs1,(existT _ _stringappend_162_ _)) => - returnm (rs1, build_ex _stringappend_162_) - | _ => - exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_162_ _) => - let _stringappend_163_ := - string_drop _stringappend_161_ - (build_ex _stringappend_162_) in - sep_matches_prefix _stringappend_163_ >>= fun w__260 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__260 with - | Some (tt,(existT _ _stringappend_164_ _)) => - returnm (tt, build_ex _stringappend_164_) - | _ => exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_164_ _) => - let _stringappend_165_ := - string_drop _stringappend_163_ - (build_ex _stringappend_164_) in - (match (reg_name_matches_prefix _stringappend_165_) with - | Some (rs2,(existT _ _stringappend_166_ _)) => - returnm (rs2, build_ex _stringappend_166_) - | _ => - exit tt : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs2, existT _ _stringappend_166_ _) => - returnm ((match (string_drop _stringappend_165_ - (build_ex _stringappend_166_)) with - | s_ => - Some - ((RTYPEW - (rs2, rs1, rd, op), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= 0)}))) - else - match (shiftiwop_mnemonic_matches_prefix _stringappend_0_) with - | Some (op,(existT _ _stringappend_168_ _)) => - let _stringappend_169_ := - string_drop _stringappend_0_ - (build_ex _stringappend_168_) in - match (spc_matches_prefix _stringappend_169_) with - | Some (tt,(existT _ _stringappend_170_ _)) => - let _stringappend_171_ := - string_drop _stringappend_169_ - (build_ex _stringappend_170_) in - match (reg_name_matches_prefix _stringappend_171_) with - | Some (rd,(existT _ _stringappend_172_ _)) => - let _stringappend_173_ := - string_drop _stringappend_171_ - (build_ex _stringappend_172_) in - sep_matches_prefix _stringappend_173_ >>= fun w__265 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__265 with - | Some - (tt,(existT _ _stringappend_174_ _)) => - let _stringappend_175_ := - string_drop _stringappend_173_ - (build_ex _stringappend_174_) in - if ((match (reg_name_matches_prefix - _stringappend_175_) with - | Some - (rs1,(existT _ _stringappend_176_ _)) => - let _stringappend_177_ := - string_drop - _stringappend_175_ - (build_ex _stringappend_176_) in - if ((match (hex_bits_5_matches_prefix - _stringappend_177_) with - | Some - (shamt,(existT _ _stringappend_178_ _)) => - match (string_drop - _stringappend_177_ - (build_ex _stringappend_178_)) with - | s_ => true - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__266 : bool => - returnm ((if (w__266) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__267 : bool => - returnm ((if (w__267) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__268 : bool => - (if (w__268) then - (match (shiftiwop_mnemonic_matches_prefix _stringappend_0_) with - | Some (op,(existT _ _stringappend_168_ _)) => - returnm (op, build_ex _stringappend_168_) - | _ => - exit tt : M ((sopw * {n : Z & ArithFact (n >= 0)})) - end : M ((sopw * {n : Z & ArithFact (n >= 0)}))) >>= fun '(op, existT _ _stringappend_168_ _) => - let _stringappend_169_ := - string_drop _stringappend_0_ - (build_ex _stringappend_168_) in - (match (spc_matches_prefix _stringappend_169_) with - | Some (tt,(existT _ _stringappend_170_ _)) => - returnm (tt, build_ex _stringappend_170_) - | _ => - exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_170_ _) => - let _stringappend_171_ := - string_drop _stringappend_169_ - (build_ex _stringappend_170_) in - (match (reg_name_matches_prefix _stringappend_171_) with - | Some (rd,(existT _ _stringappend_172_ _)) => - returnm (rd, build_ex _stringappend_172_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_172_ _) => - let _stringappend_173_ := - string_drop _stringappend_171_ - (build_ex _stringappend_172_) in - sep_matches_prefix _stringappend_173_ >>= fun w__275 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__275 with - | Some (tt,(existT _ _stringappend_174_ _)) => - returnm (tt, build_ex _stringappend_174_) - | _ => - exit tt : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_174_ _) => - let _stringappend_175_ := - string_drop _stringappend_173_ - (build_ex _stringappend_174_) in - (match (reg_name_matches_prefix _stringappend_175_) with - | Some (rs1,(existT _ _stringappend_176_ _)) => - returnm (rs1, build_ex _stringappend_176_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_176_ _) => - let _stringappend_177_ := - string_drop _stringappend_175_ - (build_ex _stringappend_176_) in - (match (hex_bits_5_matches_prefix _stringappend_177_) with - | Some (shamt,(existT _ _stringappend_178_ _)) => - returnm (shamt, build_ex _stringappend_178_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(shamt, existT _ _stringappend_178_ _) => - returnm ((match (string_drop _stringappend_177_ - (build_ex _stringappend_178_)) with - | s_ => - Some - ((SHIFTIWOP - (shamt, rs1, rd, op), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= 0)}))) - else - match (mul_mnemonic_matches_prefix _stringappend_0_) with - | Some - ((high, signed1, signed2),(existT _ _stringappend_180_ _)) => - let _stringappend_181_ := - string_drop _stringappend_0_ - (build_ex _stringappend_180_) in - match (spc_matches_prefix _stringappend_181_) with - | Some (tt,(existT _ _stringappend_182_ _)) => - let _stringappend_183_ := - string_drop _stringappend_181_ - (build_ex _stringappend_182_) in - match (reg_name_matches_prefix _stringappend_183_) with - | Some (rd,(existT _ _stringappend_184_ _)) => - let _stringappend_185_ := - string_drop _stringappend_183_ - (build_ex _stringappend_184_) in - sep_matches_prefix _stringappend_185_ >>= fun w__282 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__282 with - | Some (tt,(existT _ _stringappend_186_ _)) => - let _stringappend_187_ := - string_drop _stringappend_185_ - (build_ex _stringappend_186_) in - match (reg_name_matches_prefix - _stringappend_187_) with - | Some (rs1,(existT _ _stringappend_188_ _)) => - let _stringappend_189_ := - string_drop _stringappend_187_ - (build_ex _stringappend_188_) in - sep_matches_prefix _stringappend_189_ >>= fun w__283 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__283 with - | Some - (tt,(existT _ _stringappend_190_ _)) => - let _stringappend_191_ := - string_drop - _stringappend_189_ - (build_ex _stringappend_190_) in - if ((match (reg_name_matches_prefix - _stringappend_191_) with - | Some - (rs2,(existT _ _stringappend_192_ _)) => - match (string_drop - _stringappend_191_ - (build_ex _stringappend_192_)) with - | s_ => true - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__284 : bool => - returnm ((if (w__284) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__285 : bool => - returnm ((if (w__285) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__286 : bool => - returnm ((if (w__286) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__287 : bool => - returnm ((if (w__287) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__288 : bool => - (if (w__288) then - (match (mul_mnemonic_matches_prefix _stringappend_0_) with - | Some - ((high, signed1, signed2),(existT _ _stringappend_180_ _)) => - returnm ((high, signed1, signed2), build_ex _stringappend_180_) - | _ => - exit tt - : M (((bool * bool * bool) * {n : Z & ArithFact (n >= - 0)})) - end : M (((bool * bool * bool) * {n : Z & ArithFact (n >= - 0)}))) >>= fun '((high, signed1, signed2), existT _ _stringappend_180_ _) => - let _stringappend_181_ := - string_drop _stringappend_0_ - (build_ex _stringappend_180_) in - (match (spc_matches_prefix _stringappend_181_) with - | Some (tt,(existT _ _stringappend_182_ _)) => - returnm (tt, build_ex _stringappend_182_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_182_ _) => - let _stringappend_183_ := - string_drop _stringappend_181_ - (build_ex _stringappend_182_) in - (match (reg_name_matches_prefix _stringappend_183_) with - | Some (rd,(existT _ _stringappend_184_ _)) => - returnm (rd, build_ex _stringappend_184_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_184_ _) => - let _stringappend_185_ := - string_drop _stringappend_183_ - (build_ex _stringappend_184_) in - sep_matches_prefix _stringappend_185_ >>= fun w__295 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__295 with - | Some (tt,(existT _ _stringappend_186_ _)) => - returnm (tt, build_ex _stringappend_186_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_186_ _) => - let _stringappend_187_ := - string_drop _stringappend_185_ - (build_ex _stringappend_186_) in - (match (reg_name_matches_prefix _stringappend_187_) with - | Some (rs1,(existT _ _stringappend_188_ _)) => - returnm (rs1, build_ex _stringappend_188_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_188_ _) => - let _stringappend_189_ := - string_drop _stringappend_187_ - (build_ex _stringappend_188_) in - sep_matches_prefix _stringappend_189_ >>= fun w__300 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__300 with - | Some (tt,(existT _ _stringappend_190_ _)) => - returnm (tt, build_ex _stringappend_190_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_190_ _) => - let _stringappend_191_ := - string_drop _stringappend_189_ - (build_ex _stringappend_190_) in - (match (reg_name_matches_prefix _stringappend_191_) with - | Some (rs2,(existT _ _stringappend_192_ _)) => - returnm (rs2, build_ex _stringappend_192_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs2, existT _ _stringappend_192_ _) => - returnm ((match (string_drop _stringappend_191_ - (build_ex _stringappend_192_)) with - | s_ => - Some - ((MUL - (rs2, rs1, rd, high, signed1, - signed2), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= 0)}))) - else - and_boolM - (returnm ((string_startswith _stringappend_0_ "div") - : bool)) - (let _stringappend_194_ := - string_drop _stringappend_0_ - (build_ex (projT1 (string_length "div"))) in - match (maybe_not_u_matches_prefix _stringappend_194_) with - | Some (s,(existT _ _stringappend_195_ _)) => - let _stringappend_196_ := - string_drop _stringappend_194_ - (build_ex _stringappend_195_) in - match (spc_matches_prefix _stringappend_196_) with - | Some (tt,(existT _ _stringappend_197_ _)) => - let _stringappend_198_ := - string_drop _stringappend_196_ - (build_ex _stringappend_197_) in - match (reg_name_matches_prefix - _stringappend_198_) with - | Some (rd,(existT _ _stringappend_199_ _)) => - let _stringappend_200_ := - string_drop _stringappend_198_ - (build_ex _stringappend_199_) in - sep_matches_prefix _stringappend_200_ >>= fun w__305 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__305 with - | Some (tt,(existT _ _stringappend_201_ _)) => - let _stringappend_202_ := - string_drop _stringappend_200_ - (build_ex _stringappend_201_) in - match (reg_name_matches_prefix - _stringappend_202_) with - | Some - (rs1,(existT _ _stringappend_203_ _)) => - let _stringappend_204_ := - string_drop _stringappend_202_ - (build_ex _stringappend_203_) in - sep_matches_prefix _stringappend_204_ >>= fun w__306 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__306 with - | Some - (tt,(existT _ _stringappend_205_ _)) => - let _stringappend_206_ := - string_drop - _stringappend_204_ - (build_ex _stringappend_205_) in - if ((match (reg_name_matches_prefix - _stringappend_206_) with - | Some - (rs2,(existT _ _stringappend_207_ _)) => - match (string_drop - _stringappend_206_ - (build_ex _stringappend_207_)) with - | s_ => true - end - | None => false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__307 : bool => - returnm ((if (w__307) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__308 : bool => - returnm ((if (w__308) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__309 : bool => - returnm ((if (w__309) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__310 : bool => - returnm ((if (w__310) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__311 : bool => - returnm ((if (w__311) then true - else false) - : bool)) >>= fun w__312 : bool => - (if (w__312) then - let _stringappend_194_ := - string_drop _stringappend_0_ - (build_ex (projT1 (string_length "div"))) in - (match (maybe_not_u_matches_prefix - _stringappend_194_) with - | Some (s,(existT _ _stringappend_195_ _)) => - returnm (s, build_ex _stringappend_195_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(s, existT _ _stringappend_195_ _) => - let _stringappend_196_ := - string_drop _stringappend_194_ - (build_ex _stringappend_195_) in - (match (spc_matches_prefix _stringappend_196_) with - | Some (tt,(existT _ _stringappend_197_ _)) => - returnm (tt, build_ex _stringappend_197_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_197_ _) => - let _stringappend_198_ := - string_drop _stringappend_196_ - (build_ex _stringappend_197_) in - (match (reg_name_matches_prefix _stringappend_198_) with - | Some (rd,(existT _ _stringappend_199_ _)) => - returnm (rd, build_ex _stringappend_199_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_199_ _) => - let _stringappend_200_ := - string_drop _stringappend_198_ - (build_ex _stringappend_199_) in - sep_matches_prefix _stringappend_200_ >>= fun w__319 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__319 with - | Some (tt,(existT _ _stringappend_201_ _)) => - returnm (tt, build_ex _stringappend_201_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_201_ _) => - let _stringappend_202_ := - string_drop _stringappend_200_ - (build_ex _stringappend_201_) in - (match (reg_name_matches_prefix _stringappend_202_) with - | Some (rs1,(existT _ _stringappend_203_ _)) => - returnm (rs1, build_ex _stringappend_203_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_203_ _) => - let _stringappend_204_ := - string_drop _stringappend_202_ - (build_ex _stringappend_203_) in - sep_matches_prefix _stringappend_204_ >>= fun w__324 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__324 with - | Some (tt,(existT _ _stringappend_205_ _)) => - returnm (tt, build_ex _stringappend_205_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_205_ _) => - let _stringappend_206_ := - string_drop _stringappend_204_ - (build_ex _stringappend_205_) in - (match (reg_name_matches_prefix _stringappend_206_) with - | Some (rs2,(existT _ _stringappend_207_ _)) => - returnm (rs2, build_ex _stringappend_207_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs2, existT _ _stringappend_207_ _) => - returnm ((match (string_drop _stringappend_206_ - (build_ex _stringappend_207_)) with - | s_ => - Some - ((DIV - (rs2, rs1, rd, s), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= 0)}))) - else - and_boolM - (returnm ((string_startswith _stringappend_0_ - "rem") - : bool)) - (let _stringappend_209_ := - string_drop _stringappend_0_ - (build_ex (projT1 (string_length "rem"))) in - match (maybe_not_u_matches_prefix - _stringappend_209_) with - | Some (s,(existT _ _stringappend_210_ _)) => - let _stringappend_211_ := - string_drop _stringappend_209_ - (build_ex _stringappend_210_) in - match (spc_matches_prefix _stringappend_211_) with - | Some (tt,(existT _ _stringappend_212_ _)) => - let _stringappend_213_ := - string_drop _stringappend_211_ - (build_ex _stringappend_212_) in - match (reg_name_matches_prefix - _stringappend_213_) with - | Some (rd,(existT _ _stringappend_214_ _)) => - let _stringappend_215_ := - string_drop _stringappend_213_ - (build_ex _stringappend_214_) in - sep_matches_prefix _stringappend_215_ >>= fun w__329 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__329 with - | Some - (tt,(existT _ _stringappend_216_ _)) => - let _stringappend_217_ := - string_drop _stringappend_215_ - (build_ex _stringappend_216_) in - match (reg_name_matches_prefix - _stringappend_217_) with - | Some - (rs1,(existT _ _stringappend_218_ _)) => - let _stringappend_219_ := - string_drop _stringappend_217_ - (build_ex _stringappend_218_) in - sep_matches_prefix - _stringappend_219_ >>= fun w__330 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__330 with - | Some - (tt,(existT _ _stringappend_220_ _)) => - let _stringappend_221_ := - string_drop - _stringappend_219_ - (build_ex _stringappend_220_) in - if ((match (reg_name_matches_prefix - _stringappend_221_) with - | Some - (rs2,(existT _ _stringappend_222_ _)) => - match (string_drop - _stringappend_221_ - (build_ex _stringappend_222_)) with - | s_ => - true - end - | None => - false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__331 : bool => - returnm ((if (w__331) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__332 : bool => - returnm ((if (w__332) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__333 : bool => - returnm ((if (w__333) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__334 : bool => - returnm ((if (w__334) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__335 : bool => - returnm ((if (w__335) then true - else false) - : bool)) >>= fun w__336 : bool => - (if (w__336) then - let _stringappend_209_ := - string_drop _stringappend_0_ - (build_ex (projT1 (string_length "rem"))) in - (match (maybe_not_u_matches_prefix - _stringappend_209_) with - | Some (s,(existT _ _stringappend_210_ _)) => - returnm (s, build_ex _stringappend_210_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= 0)})) - end : M ((bool * {n : Z & ArithFact (n >= 0)}))) >>= fun '(s, existT _ _stringappend_210_ _) => - let _stringappend_211_ := - string_drop _stringappend_209_ - (build_ex _stringappend_210_) in - (match (spc_matches_prefix _stringappend_211_) with - | Some (tt,(existT _ _stringappend_212_ _)) => - returnm (tt, build_ex _stringappend_212_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_212_ _) => - let _stringappend_213_ := - string_drop _stringappend_211_ - (build_ex _stringappend_212_) in - (match (reg_name_matches_prefix - _stringappend_213_) with - | Some (rd,(existT _ _stringappend_214_ _)) => - returnm (rd, build_ex _stringappend_214_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rd, existT _ _stringappend_214_ _) => - let _stringappend_215_ := - string_drop _stringappend_213_ - (build_ex _stringappend_214_) in - sep_matches_prefix _stringappend_215_ >>= fun w__343 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__343 with - | Some (tt,(existT _ _stringappend_216_ _)) => - returnm (tt, build_ex _stringappend_216_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_216_ _) => - let _stringappend_217_ := - string_drop _stringappend_215_ - (build_ex _stringappend_216_) in - (match (reg_name_matches_prefix - _stringappend_217_) with - | Some (rs1,(existT _ _stringappend_218_ _)) => - returnm (rs1, build_ex _stringappend_218_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs1, existT _ _stringappend_218_ _) => - let _stringappend_219_ := - string_drop _stringappend_217_ - (build_ex _stringappend_218_) in - sep_matches_prefix _stringappend_219_ >>= fun w__348 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__348 with - | Some (tt,(existT _ _stringappend_220_ _)) => - returnm (tt, build_ex _stringappend_220_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_220_ _) => - let _stringappend_221_ := - string_drop _stringappend_219_ - (build_ex _stringappend_220_) in - (match (reg_name_matches_prefix - _stringappend_221_) with - | Some (rs2,(existT _ _stringappend_222_ _)) => - returnm (rs2, build_ex _stringappend_222_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= 0)}))) >>= fun '(rs2, existT _ _stringappend_222_ _) => - returnm ((match (string_drop _stringappend_221_ - (build_ex _stringappend_222_)) with - | s_ => - Some - ((REM - (rs2, rs1, rd, s), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= 0)}))) - else - and_boolM - (returnm ((string_startswith _stringappend_0_ - "mulw") - : bool)) - (let _stringappend_224_ := - string_drop _stringappend_0_ - (build_ex (projT1 (string_length "mulw"))) in - match (spc_matches_prefix _stringappend_224_) with - | Some (tt,(existT _ _stringappend_225_ _)) => - let _stringappend_226_ := - string_drop _stringappend_224_ - (build_ex _stringappend_225_) in - match (reg_name_matches_prefix - _stringappend_226_) with - | Some (rd,(existT _ _stringappend_227_ _)) => - let _stringappend_228_ := - string_drop _stringappend_226_ - (build_ex _stringappend_227_) in - sep_matches_prefix _stringappend_228_ >>= fun w__353 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__353 with - | Some - (tt,(existT _ _stringappend_229_ _)) => - let _stringappend_230_ := - string_drop _stringappend_228_ - (build_ex _stringappend_229_) in - match (reg_name_matches_prefix - _stringappend_230_) with - | Some - (rs1,(existT _ _stringappend_231_ _)) => - let _stringappend_232_ := - string_drop _stringappend_230_ - (build_ex _stringappend_231_) in - sep_matches_prefix - _stringappend_232_ >>= fun w__354 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__354 with - | Some - (tt,(existT _ _stringappend_233_ _)) => - let _stringappend_234_ := - string_drop - _stringappend_232_ - (build_ex _stringappend_233_) in - if ((match (reg_name_matches_prefix - _stringappend_234_) with - | Some - (rs2,(existT _ _stringappend_235_ _)) => - match (string_drop - _stringappend_234_ - (build_ex _stringappend_235_)) with - | s_ => - true - end - | None => - false - end)) then - true - else false - | None => false - end)) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__355 : bool => - returnm ((if (w__355) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__356 : bool => - returnm ((if (w__356) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__357 : bool => - returnm ((if (w__357) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__358 : bool => - returnm ((if (w__358) then true - else false) - : bool)) >>= fun w__359 : bool => - (if (w__359) then - let _stringappend_224_ := - string_drop _stringappend_0_ - (build_ex (projT1 (string_length "mulw"))) in - (match (spc_matches_prefix _stringappend_224_) with - | Some (tt,(existT _ _stringappend_225_ _)) => - returnm (tt, build_ex _stringappend_225_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_225_ _) => - let _stringappend_226_ := - string_drop _stringappend_224_ - (build_ex _stringappend_225_) in - (match (reg_name_matches_prefix - _stringappend_226_) with - | Some (rd,(existT _ _stringappend_227_ _)) => - returnm (rd, build_ex _stringappend_227_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_227_ _) => - let _stringappend_228_ := - string_drop _stringappend_226_ - (build_ex _stringappend_227_) in - sep_matches_prefix _stringappend_228_ >>= fun w__364 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__364 with - | Some (tt,(existT _ _stringappend_229_ _)) => - returnm (tt, build_ex _stringappend_229_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_229_ _) => - let _stringappend_230_ := - string_drop _stringappend_228_ - (build_ex _stringappend_229_) in - (match (reg_name_matches_prefix - _stringappend_230_) with - | Some (rs1,(existT _ _stringappend_231_ _)) => - returnm (rs1, build_ex _stringappend_231_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_231_ _) => - let _stringappend_232_ := - string_drop _stringappend_230_ - (build_ex _stringappend_231_) in - sep_matches_prefix _stringappend_232_ >>= fun w__369 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__369 with - | Some (tt,(existT _ _stringappend_233_ _)) => - returnm (tt, build_ex _stringappend_233_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= 0)})) - end : M ((unit * {n : Z & ArithFact (n >= 0)}))) >>= fun '(tt, existT _ _stringappend_233_ _) => - let _stringappend_234_ := - string_drop _stringappend_232_ - (build_ex _stringappend_233_) in - (match (reg_name_matches_prefix - _stringappend_234_) with - | Some (rs2,(existT _ _stringappend_235_ _)) => - returnm (rs2, build_ex _stringappend_235_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs2, existT _ _stringappend_235_ _) => - returnm ((match (string_drop - _stringappend_234_ - (build_ex _stringappend_235_)) with - | s_ => - Some - ((MULW - (rs2, rs1, rd), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= 0)}))) - else - and_boolM - (returnm ((string_startswith - _stringappend_0_ "div") - : bool)) - (let _stringappend_237_ := - string_drop _stringappend_0_ - (build_ex (projT1 (string_length "div"))) in - match (maybe_not_u_matches_prefix - _stringappend_237_) with - | Some (s,(existT _ _stringappend_238_ _)) => - let _stringappend_239_ := - string_drop _stringappend_237_ - (build_ex _stringappend_238_) in - and_boolM - (returnm ((string_startswith - _stringappend_239_ "w") - : bool)) - (let _stringappend_240_ := - string_drop _stringappend_239_ - (build_ex (projT1 (string_length - "w"))) in - match (spc_matches_prefix - _stringappend_240_) with - | Some - (tt,(existT _ _stringappend_241_ _)) => - let _stringappend_242_ := - string_drop _stringappend_240_ - (build_ex _stringappend_241_) in - match (reg_name_matches_prefix - _stringappend_242_) with - | Some - (rd,(existT _ _stringappend_243_ _)) => - let _stringappend_244_ := - string_drop _stringappend_242_ - (build_ex _stringappend_243_) in - sep_matches_prefix - _stringappend_244_ >>= fun w__374 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__374 with - | Some - (tt,(existT _ _stringappend_245_ _)) => - let _stringappend_246_ := - string_drop - _stringappend_244_ - (build_ex _stringappend_245_) in - match (reg_name_matches_prefix - _stringappend_246_) with - | Some - (rs1,(existT _ _stringappend_247_ _)) => - let _stringappend_248_ := - string_drop - _stringappend_246_ - (build_ex _stringappend_247_) in - sep_matches_prefix - _stringappend_248_ >>= fun w__375 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__375 with - | Some - (tt,(existT _ _stringappend_249_ _)) => - let _stringappend_250_ := - string_drop - _stringappend_248_ - (build_ex _stringappend_249_) in - if ((match (reg_name_matches_prefix - _stringappend_250_) with - | Some - (rs2,(existT _ _stringappend_251_ _)) => - match (string_drop - _stringappend_250_ - (build_ex _stringappend_251_)) with - | s_ => - true - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__376 : bool => - returnm ((if (w__376) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__377 : bool => - returnm ((if (w__377) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__378 : bool => - returnm ((if (w__378) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__379 : bool => - returnm ((if (w__379) then true - else false) - : bool)) >>= fun w__380 : bool => - returnm ((if (w__380) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__381 : bool => - returnm ((if (w__381) then true - else false) - : bool)) >>= fun w__382 : bool => - (if (w__382) then - let _stringappend_237_ := - string_drop _stringappend_0_ - (build_ex (projT1 (string_length "div"))) in - (match (maybe_not_u_matches_prefix - _stringappend_237_) with - | Some (s,(existT _ _stringappend_238_ _)) => - returnm (s, build_ex _stringappend_238_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(s, existT _ _stringappend_238_ _) => - let _stringappend_239_ := - string_drop _stringappend_237_ - (build_ex _stringappend_238_) in - let _stringappend_240_ := - string_drop _stringappend_239_ - (build_ex (projT1 (string_length "w"))) in - (match (spc_matches_prefix - _stringappend_240_) with - | Some - (tt,(existT _ _stringappend_241_ _)) => - returnm (tt, build_ex _stringappend_241_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_241_ _) => - let _stringappend_242_ := - string_drop _stringappend_240_ - (build_ex _stringappend_241_) in - (match (reg_name_matches_prefix - _stringappend_242_) with - | Some - (rd,(existT _ _stringappend_243_ _)) => - returnm (rd, build_ex _stringappend_243_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_243_ _) => - let _stringappend_244_ := - string_drop _stringappend_242_ - (build_ex _stringappend_243_) in - sep_matches_prefix _stringappend_244_ >>= fun w__389 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__389 with - | Some - (tt,(existT _ _stringappend_245_ _)) => - returnm (tt, build_ex _stringappend_245_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_245_ _) => - let _stringappend_246_ := - string_drop _stringappend_244_ - (build_ex _stringappend_245_) in - (match (reg_name_matches_prefix - _stringappend_246_) with - | Some - (rs1,(existT _ _stringappend_247_ _)) => - returnm (rs1, build_ex _stringappend_247_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_247_ _) => - let _stringappend_248_ := - string_drop _stringappend_246_ - (build_ex _stringappend_247_) in - sep_matches_prefix _stringappend_248_ >>= fun w__394 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__394 with - | Some - (tt,(existT _ _stringappend_249_ _)) => - returnm (tt, build_ex _stringappend_249_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_249_ _) => - let _stringappend_250_ := - string_drop _stringappend_248_ - (build_ex _stringappend_249_) in - (match (reg_name_matches_prefix - _stringappend_250_) with - | Some - (rs2,(existT _ _stringappend_251_ _)) => - returnm (rs2, build_ex _stringappend_251_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs2, existT _ _stringappend_251_ _) => - returnm ((match (string_drop - _stringappend_250_ - (build_ex _stringappend_251_)) with - | s_ => - Some - ((DIVW - (rs2, rs1, rd, s), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= - 0)}))) - else - and_boolM - (returnm ((string_startswith - _stringappend_0_ "rem") - : bool)) - (let _stringappend_253_ := - string_drop _stringappend_0_ - (build_ex (projT1 (string_length - "rem"))) in - match (maybe_not_u_matches_prefix - _stringappend_253_) with - | Some - (s,(existT _ _stringappend_254_ _)) => - let _stringappend_255_ := - string_drop _stringappend_253_ - (build_ex _stringappend_254_) in - and_boolM - (returnm ((string_startswith - _stringappend_255_ "w") - : bool)) - (let _stringappend_256_ := - string_drop _stringappend_255_ - (build_ex (projT1 (string_length - "w"))) in - match (spc_matches_prefix - _stringappend_256_) with - | Some - (tt,(existT _ _stringappend_257_ _)) => - let _stringappend_258_ := - string_drop _stringappend_256_ - (build_ex _stringappend_257_) in - match (reg_name_matches_prefix - _stringappend_258_) with - | Some - (rd,(existT _ _stringappend_259_ _)) => - let _stringappend_260_ := - string_drop - _stringappend_258_ - (build_ex _stringappend_259_) in - sep_matches_prefix - _stringappend_260_ >>= fun w__399 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__399 with - | Some - (tt,(existT _ _stringappend_261_ _)) => - let _stringappend_262_ := - string_drop - _stringappend_260_ - (build_ex _stringappend_261_) in - match (reg_name_matches_prefix - _stringappend_262_) with - | Some - (rs1,(existT _ _stringappend_263_ _)) => - let _stringappend_264_ := - string_drop - _stringappend_262_ - (build_ex _stringappend_263_) in - sep_matches_prefix - _stringappend_264_ >>= fun w__400 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__400 with - | Some - (tt,(existT _ _stringappend_265_ _)) => - let _stringappend_266_ := - string_drop - _stringappend_264_ - (build_ex _stringappend_265_) in - if ((match (reg_name_matches_prefix - _stringappend_266_) with - | Some - (rs2,(existT _ _stringappend_267_ _)) => - match (string_drop - _stringappend_266_ - (build_ex _stringappend_267_)) with - | s_ => - true - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) - then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__401 : bool => - returnm ((if (w__401) then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__402 : bool => - returnm ((if (w__402) then - true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__403 : bool => - returnm ((if (w__403) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__404 : bool => - returnm ((if (w__404) then true - else false) - : bool)) >>= fun w__405 : bool => - returnm ((if (w__405) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__406 : bool => - returnm ((if (w__406) then true - else false) - : bool)) >>= fun w__407 : bool => - (if (w__407) then - let _stringappend_253_ := - string_drop _stringappend_0_ - (build_ex (projT1 (string_length - "rem"))) in - (match (maybe_not_u_matches_prefix - _stringappend_253_) with - | Some - (s,(existT _ _stringappend_254_ _)) => - returnm (s, build_ex _stringappend_254_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(s, existT _ _stringappend_254_ _) => - let _stringappend_255_ := - string_drop _stringappend_253_ - (build_ex _stringappend_254_) in - let _stringappend_256_ := - string_drop _stringappend_255_ - (build_ex (projT1 (string_length "w"))) in - (match (spc_matches_prefix - _stringappend_256_) with - | Some - (tt,(existT _ _stringappend_257_ _)) => - returnm (tt, build_ex _stringappend_257_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_257_ _) => - let _stringappend_258_ := - string_drop _stringappend_256_ - (build_ex _stringappend_257_) in - (match (reg_name_matches_prefix - _stringappend_258_) with - | Some - (rd,(existT _ _stringappend_259_ _)) => - returnm (rd, build_ex _stringappend_259_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_259_ _) => - let _stringappend_260_ := - string_drop _stringappend_258_ - (build_ex _stringappend_259_) in - sep_matches_prefix _stringappend_260_ >>= fun w__414 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__414 with - | Some - (tt,(existT _ _stringappend_261_ _)) => - returnm (tt, build_ex _stringappend_261_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_261_ _) => - let _stringappend_262_ := - string_drop _stringappend_260_ - (build_ex _stringappend_261_) in - (match (reg_name_matches_prefix - _stringappend_262_) with - | Some - (rs1,(existT _ _stringappend_263_ _)) => - returnm (rs1, build_ex _stringappend_263_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_263_ _) => - let _stringappend_264_ := - string_drop _stringappend_262_ - (build_ex _stringappend_263_) in - sep_matches_prefix _stringappend_264_ >>= fun w__419 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__419 with - | Some - (tt,(existT _ _stringappend_265_ _)) => - returnm (tt, build_ex _stringappend_265_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_265_ _) => - let _stringappend_266_ := - string_drop _stringappend_264_ - (build_ex _stringappend_265_) in - (match (reg_name_matches_prefix - _stringappend_266_) with - | Some - (rs2,(existT _ _stringappend_267_ _)) => - returnm (rs2, build_ex _stringappend_267_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs2, existT _ _stringappend_267_ _) => - returnm ((match (string_drop - _stringappend_266_ - (build_ex _stringappend_267_)) with - | s_ => - Some - ((REMW - (rs2, rs1, rd, s), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= - 0)}))) - else - and_boolM - (returnm ((string_startswith - _stringappend_0_ "fence") - : bool)) - (let _stringappend_269_ := - string_drop _stringappend_0_ - (build_ex (projT1 (string_length - "fence"))) in - match (spc_matches_prefix - _stringappend_269_) with - | Some - (tt,(existT _ _stringappend_270_ _)) => - let _stringappend_271_ := - string_drop _stringappend_269_ - (build_ex _stringappend_270_) in - fence_bits_matches_prefix - _stringappend_271_ >>= fun w__424 : option ((mword 4 * {n : Z & ArithFact (n >= - 0)})) => - match w__424 with - | Some - (pred,(existT _ _stringappend_272_ _)) => - let _stringappend_273_ := - string_drop _stringappend_271_ - (build_ex _stringappend_272_) in - sep_matches_prefix - _stringappend_273_ >>= fun w__425 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__425 with - | Some - (tt,(existT _ _stringappend_274_ _)) => - let _stringappend_275_ := - string_drop - _stringappend_273_ - (build_ex _stringappend_274_) in - fence_bits_matches_prefix - _stringappend_275_ >>= fun w__426 : option ((mword 4 * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__426 with - | Some - (succ,(existT _ _stringappend_276_ _)) => - match (string_drop - _stringappend_275_ - (build_ex _stringappend_276_)) with - | s_ => - true - end - | None => - false - end)) then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__427 : bool => - returnm ((if (w__427) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__428 : bool => - returnm ((if (w__428) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__429 : bool => - returnm ((if (w__429) then true - else false) - : bool)) >>= fun w__430 : bool => - (if (w__430) then - let _stringappend_269_ := - string_drop _stringappend_0_ - (build_ex (projT1 (string_length - "fence"))) in - (match (spc_matches_prefix - _stringappend_269_) with - | Some - (tt,(existT _ _stringappend_270_ _)) => - returnm (tt, build_ex _stringappend_270_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_270_ _) => - let _stringappend_271_ := - string_drop _stringappend_269_ - (build_ex _stringappend_270_) in - fence_bits_matches_prefix - _stringappend_271_ >>= fun w__433 : option ((mword 4 * {n : Z & ArithFact (n >= - 0)})) => - (match w__433 with - | Some - (pred,(existT _ _stringappend_272_ _)) => - returnm (pred, build_ex _stringappend_272_) - | _ => - exit tt - : M ((mword 4 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 4 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(pred, existT _ _stringappend_272_ _) => - let _stringappend_273_ := - string_drop _stringappend_271_ - (build_ex _stringappend_272_) in - sep_matches_prefix _stringappend_273_ >>= fun w__436 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__436 with - | Some - (tt,(existT _ _stringappend_274_ _)) => - returnm (tt, build_ex _stringappend_274_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_274_ _) => - let _stringappend_275_ := - string_drop _stringappend_273_ - (build_ex _stringappend_274_) in - fence_bits_matches_prefix - _stringappend_275_ >>= fun w__439 : option ((mword 4 * {n : Z & ArithFact (n >= - 0)})) => - (match w__439 with - | Some - (succ,(existT _ _stringappend_276_ _)) => - returnm (succ, build_ex _stringappend_276_) - | _ => - exit tt - : M ((mword 4 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 4 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(succ, existT _ _stringappend_276_ _) => - returnm ((match (string_drop - _stringappend_275_ - (build_ex _stringappend_276_)) with - | s_ => - Some - ((FENCE - (pred, succ), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= - 0)}))) - else if ((andb - (string_startswith - _stringappend_0_ - "fence.i") - (match (string_drop - _stringappend_0_ - (build_ex (projT1 (string_length - "fence.i")))) with - | s_ => true - end))) then - returnm ((match (string_drop - _stringappend_0_ - (build_ex (projT1 (string_length - "fence.i")))) with - | s_ => - Some - ((FENCEI - (tt), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= - 0)}))) - else if ((andb - (string_startswith - _stringappend_0_ "ecall") - (match (string_drop - _stringappend_0_ - (build_ex (projT1 (string_length - "ecall")))) with - | s_ => true - end))) then - returnm ((match (string_drop - _stringappend_0_ - (build_ex (projT1 (string_length - "ecall")))) with - | s_ => - Some - ((ECALL - (tt), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= - 0)}))) - else if ((andb - (string_startswith - _stringappend_0_ "mret") - (match (string_drop - _stringappend_0_ - (build_ex (projT1 (string_length - "mret")))) with - | s_ => true - end))) then - returnm ((match (string_drop - _stringappend_0_ - (build_ex (projT1 (string_length - "mret")))) with - | s_ => - Some - ((MRET - (tt), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= - 0)}))) - else if ((andb - (string_startswith - _stringappend_0_ "sret") - (match (string_drop - _stringappend_0_ - (build_ex (projT1 (string_length - "sret")))) with - | s_ => true - end))) then - returnm ((match (string_drop - _stringappend_0_ - (build_ex (projT1 (string_length - "sret")))) with - | s_ => - Some - ((SRET - (tt), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= - 0)}))) - else if ((andb - (string_startswith - _stringappend_0_ - "ebreak") - (match (string_drop - _stringappend_0_ - (build_ex (projT1 (string_length - "ebreak")))) with - | s_ => true - end))) then - returnm ((match (string_drop - _stringappend_0_ - (build_ex (projT1 (string_length - "ebreak")))) with - | s_ => - Some - ((EBREAK - (tt), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= - 0)}))) - else if ((andb - (string_startswith - _stringappend_0_ "wfi") - (match (string_drop - _stringappend_0_ - (build_ex (projT1 (string_length - "wfi")))) with - | s_ => true - end))) then - returnm ((match (string_drop - _stringappend_0_ - (build_ex (projT1 (string_length - "wfi")))) with - | s_ => - Some - ((WFI - (tt), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= - 0)}))) - else - and_boolM - (returnm ((string_startswith - _stringappend_0_ - "sfence.vma") - : bool)) - (let _stringappend_284_ := - string_drop _stringappend_0_ - (build_ex (projT1 (string_length - "sfence.vma"))) in - match (spc_matches_prefix - _stringappend_284_) with - | Some - (tt,(existT _ _stringappend_285_ _)) => - let _stringappend_286_ := - string_drop _stringappend_284_ - (build_ex _stringappend_285_) in - match (reg_name_matches_prefix - _stringappend_286_) with - | Some - (rs1,(existT _ _stringappend_287_ _)) => - let _stringappend_288_ := - string_drop - _stringappend_286_ - (build_ex _stringappend_287_) in - sep_matches_prefix - _stringappend_288_ >>= fun w__442 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__442 with - | Some - (tt,(existT _ _stringappend_289_ _)) => - let _stringappend_290_ := - string_drop - _stringappend_288_ - (build_ex _stringappend_289_) in - if ((match (reg_name_matches_prefix - _stringappend_290_) with - | Some - (rs2,(existT _ _stringappend_291_ _)) => - match (string_drop - _stringappend_290_ - (build_ex _stringappend_291_)) with - | s_ => - true - end - | None => - false - end)) - then - true - else false - | None => - false - end)) then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__443 : bool => - returnm ((if (w__443) then true - else false) - : bool) - | None => returnm (false : bool) - end >>= fun w__444 : bool => - returnm ((if (w__444) then true - else false) - : bool)) >>= fun w__445 : bool => - (if (w__445) then - let _stringappend_284_ := - string_drop _stringappend_0_ - (build_ex (projT1 (string_length - "sfence.vma"))) in - (match (spc_matches_prefix - _stringappend_284_) with - | Some - (tt,(existT _ _stringappend_285_ _)) => - returnm (tt, build_ex _stringappend_285_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_285_ _) => - let _stringappend_286_ := - string_drop _stringappend_284_ - (build_ex _stringappend_285_) in - (match (reg_name_matches_prefix - _stringappend_286_) with - | Some - (rs1,(existT _ _stringappend_287_ _)) => - returnm (rs1, build_ex _stringappend_287_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_287_ _) => - let _stringappend_288_ := - string_drop _stringappend_286_ - (build_ex _stringappend_287_) in - sep_matches_prefix - _stringappend_288_ >>= fun w__450 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__450 with - | Some - (tt,(existT _ _stringappend_289_ _)) => - returnm (tt, build_ex _stringappend_289_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_289_ _) => - let _stringappend_290_ := - string_drop _stringappend_288_ - (build_ex _stringappend_289_) in - (match (reg_name_matches_prefix - _stringappend_290_) with - | Some - (rs2,(existT _ _stringappend_291_ _)) => - returnm (rs2, build_ex _stringappend_291_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs2, existT _ _stringappend_291_ _) => - returnm ((match (string_drop - _stringappend_290_ - (build_ex _stringappend_291_)) with - | s_ => - Some - ((SFENCE_VMA - (rs1, rs2), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= - 0)}))) - else - and_boolM - (returnm ((string_startswith - _stringappend_0_ - "lr.") - : bool)) - (let _stringappend_293_ := - string_drop _stringappend_0_ - (build_ex (projT1 (string_length - "lr."))) in - match (maybe_aq_matches_prefix - _stringappend_293_) with - | Some - (aq,(existT _ _stringappend_294_ _)) => - let _stringappend_295_ := - string_drop - _stringappend_293_ - (build_ex _stringappend_294_) in - match (maybe_rl_matches_prefix - _stringappend_295_) with - | Some - (rl,(existT _ _stringappend_296_ _)) => - let _stringappend_297_ := - string_drop - _stringappend_295_ - (build_ex _stringappend_296_) in - match (size_mnemonic_matches_prefix - _stringappend_297_) with - | Some - (size,(existT _ _stringappend_298_ _)) => - let _stringappend_299_ := - string_drop - _stringappend_297_ - (build_ex _stringappend_298_) in - match (spc_matches_prefix - _stringappend_299_) with - | Some - (tt,(existT _ _stringappend_300_ _)) => - let _stringappend_301_ := - string_drop - _stringappend_299_ - (build_ex _stringappend_300_) in - match (reg_name_matches_prefix - _stringappend_301_) with - | Some - (rd,(existT _ _stringappend_302_ _)) => - let _stringappend_303_ := - string_drop - _stringappend_301_ - (build_ex _stringappend_302_) in - sep_matches_prefix - _stringappend_303_ >>= fun w__455 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if ((match w__455 with - | Some - (tt,(existT _ _stringappend_304_ _)) => - let _stringappend_305_ := - string_drop - _stringappend_303_ - (build_ex _stringappend_304_) in - if - ((match (reg_name_matches_prefix - _stringappend_305_) with - | Some - (rs1,(existT _ _stringappend_306_ _)) => - match (string_drop - _stringappend_305_ - (build_ex _stringappend_306_)) with - | s_ => - true - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__456 : bool => - returnm ((if (w__456) - then - true - else false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__457 : bool => - returnm ((if (w__457) - then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__458 : bool => - returnm ((if (w__458) then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__459 : bool => - returnm ((if (w__459) then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__460 : bool => - returnm ((if (w__460) then true - else false) - : bool)) >>= fun w__461 : bool => - (if (w__461) then - let _stringappend_293_ := - string_drop _stringappend_0_ - (build_ex (projT1 (string_length - "lr."))) in - (match (maybe_aq_matches_prefix - _stringappend_293_) with - | Some - (aq,(existT _ _stringappend_294_ _)) => - returnm (aq, build_ex _stringappend_294_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(aq, existT _ _stringappend_294_ _) => - let _stringappend_295_ := - string_drop - _stringappend_293_ - (build_ex _stringappend_294_) in - (match (maybe_rl_matches_prefix - _stringappend_295_) with - | Some - (rl,(existT _ _stringappend_296_ _)) => - returnm (rl, build_ex _stringappend_296_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rl, existT _ _stringappend_296_ _) => - let _stringappend_297_ := - string_drop - _stringappend_295_ - (build_ex _stringappend_296_) in - (match (size_mnemonic_matches_prefix - _stringappend_297_) with - | Some - (size,(existT _ _stringappend_298_ _)) => - returnm (size, build_ex _stringappend_298_) - | _ => - exit tt - : M ((word_width * {n : Z & ArithFact (n >= - 0)})) - end : M ((word_width * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(size, existT _ _stringappend_298_ _) => - let _stringappend_299_ := - string_drop - _stringappend_297_ - (build_ex _stringappend_298_) in - (match (spc_matches_prefix - _stringappend_299_) with - | Some - (tt,(existT _ _stringappend_300_ _)) => - returnm (tt, build_ex _stringappend_300_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_300_ _) => - let _stringappend_301_ := - string_drop - _stringappend_299_ - (build_ex _stringappend_300_) in - (match (reg_name_matches_prefix - _stringappend_301_) with - | Some - (rd,(existT _ _stringappend_302_ _)) => - returnm (rd, build_ex _stringappend_302_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_302_ _) => - let _stringappend_303_ := - string_drop - _stringappend_301_ - (build_ex _stringappend_302_) in - sep_matches_prefix - _stringappend_303_ >>= fun w__472 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__472 with - | Some - (tt,(existT _ _stringappend_304_ _)) => - returnm (tt, build_ex _stringappend_304_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_304_ _) => - let _stringappend_305_ := - string_drop - _stringappend_303_ - (build_ex _stringappend_304_) in - (match (reg_name_matches_prefix - _stringappend_305_) with - | Some - (rs1,(existT _ _stringappend_306_ _)) => - returnm (rs1, build_ex _stringappend_306_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_306_ _) => - returnm ((match (string_drop - _stringappend_305_ - (build_ex _stringappend_306_)) with - | s_ => - Some - ((LOADRES - (aq, rl, rs1, - size, rd), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= - 0)}))) - else - and_boolM - (returnm ((string_startswith - _stringappend_0_ - "sc.") - : bool)) - (let _stringappend_308_ := - string_drop - _stringappend_0_ - (build_ex (projT1 (string_length - "sc."))) in - match (maybe_aq_matches_prefix - _stringappend_308_) with - | Some - (aq,(existT _ _stringappend_309_ _)) => - let _stringappend_310_ := - string_drop - _stringappend_308_ - (build_ex _stringappend_309_) in - match (maybe_rl_matches_prefix - _stringappend_310_) with - | Some - (rl,(existT _ _stringappend_311_ _)) => - let _stringappend_312_ := - string_drop - _stringappend_310_ - (build_ex _stringappend_311_) in - match (size_mnemonic_matches_prefix - _stringappend_312_) with - | Some - (size,(existT _ _stringappend_313_ _)) => - let _stringappend_314_ := - string_drop - _stringappend_312_ - (build_ex _stringappend_313_) in - match (spc_matches_prefix - _stringappend_314_) with - | Some - (tt,(existT _ _stringappend_315_ _)) => - let _stringappend_316_ := - string_drop - _stringappend_314_ - (build_ex _stringappend_315_) in - match (reg_name_matches_prefix - _stringappend_316_) with - | Some - (rd,(existT _ _stringappend_317_ _)) => - let _stringappend_318_ := - string_drop - _stringappend_316_ - (build_ex _stringappend_317_) in - sep_matches_prefix - _stringappend_318_ >>= fun w__477 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__477 with - | Some - (tt,(existT _ _stringappend_319_ _)) => - let _stringappend_320_ := - string_drop - _stringappend_318_ - (build_ex _stringappend_319_) in - match (reg_name_matches_prefix - _stringappend_320_) with - | Some - (rs1,(existT _ _stringappend_321_ _)) => - let _stringappend_322_ := - string_drop - _stringappend_320_ - (build_ex _stringappend_321_) in - sep_matches_prefix - _stringappend_322_ >>= fun w__478 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if - ((match w__478 with - | Some - (tt,(existT _ _stringappend_323_ _)) => - let _stringappend_324_ := - string_drop - _stringappend_322_ - (build_ex _stringappend_323_) in - if - ((match (reg_name_matches_prefix - _stringappend_324_) with - | Some - (rs2,(existT _ _stringappend_325_ _)) => - match (string_drop - _stringappend_324_ - (build_ex _stringappend_325_)) with - | s_ => - true - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__479 : bool => - returnm ((if - (w__479) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__480 : bool => - returnm ((if (w__480) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__481 : bool => - returnm ((if (w__481) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__482 : bool => - returnm ((if (w__482) - then - true - else false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__483 : bool => - returnm ((if (w__483) - then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__484 : bool => - returnm ((if (w__484) then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__485 : bool => - returnm ((if (w__485) then - true - else false) - : bool)) >>= fun w__486 : bool => - (if (w__486) then - let _stringappend_308_ := - string_drop - _stringappend_0_ - (build_ex (projT1 (string_length - "sc."))) in - (match (maybe_aq_matches_prefix - _stringappend_308_) with - | Some - (aq,(existT _ _stringappend_309_ _)) => - returnm (aq, build_ex _stringappend_309_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(aq, existT _ _stringappend_309_ _) => - let _stringappend_310_ := - string_drop - _stringappend_308_ - (build_ex _stringappend_309_) in - (match (maybe_rl_matches_prefix - _stringappend_310_) with - | Some - (rl,(existT _ _stringappend_311_ _)) => - returnm (rl, build_ex _stringappend_311_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rl, existT _ _stringappend_311_ _) => - let _stringappend_312_ := - string_drop - _stringappend_310_ - (build_ex _stringappend_311_) in - (match (size_mnemonic_matches_prefix - _stringappend_312_) with - | Some - (size,(existT _ _stringappend_313_ _)) => - returnm (size, build_ex _stringappend_313_) - | _ => - exit tt - : M ((word_width * {n : Z & ArithFact (n >= - 0)})) - end : M ((word_width * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(size, existT _ _stringappend_313_ _) => - let _stringappend_314_ := - string_drop - _stringappend_312_ - (build_ex _stringappend_313_) in - (match (spc_matches_prefix - _stringappend_314_) with - | Some - (tt,(existT _ _stringappend_315_ _)) => - returnm (tt, build_ex _stringappend_315_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_315_ _) => - let _stringappend_316_ := - string_drop - _stringappend_314_ - (build_ex _stringappend_315_) in - (match (reg_name_matches_prefix - _stringappend_316_) with - | Some - (rd,(existT _ _stringappend_317_ _)) => - returnm (rd, build_ex _stringappend_317_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_317_ _) => - let _stringappend_318_ := - string_drop - _stringappend_316_ - (build_ex _stringappend_317_) in - sep_matches_prefix - _stringappend_318_ >>= fun w__497 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__497 with - | Some - (tt,(existT _ _stringappend_319_ _)) => - returnm (tt, build_ex _stringappend_319_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_319_ _) => - let _stringappend_320_ := - string_drop - _stringappend_318_ - (build_ex _stringappend_319_) in - (match (reg_name_matches_prefix - _stringappend_320_) with - | Some - (rs1,(existT _ _stringappend_321_ _)) => - returnm (rs1, build_ex _stringappend_321_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_321_ _) => - let _stringappend_322_ := - string_drop - _stringappend_320_ - (build_ex _stringappend_321_) in - sep_matches_prefix - _stringappend_322_ >>= fun w__502 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__502 with - | Some - (tt,(existT _ _stringappend_323_ _)) => - returnm (tt, build_ex _stringappend_323_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_323_ _) => - let _stringappend_324_ := - string_drop - _stringappend_322_ - (build_ex _stringappend_323_) in - (match (reg_name_matches_prefix - _stringappend_324_) with - | Some - (rs2,(existT _ _stringappend_325_ _)) => - returnm (rs2, build_ex _stringappend_325_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs2, existT _ _stringappend_325_ _) => - returnm ((match (string_drop - _stringappend_324_ - (build_ex _stringappend_325_)) with - | s_ => - Some - ((STORECON - (aq, rl, - rs2, rs1, - size, rd), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= - 0)}))) - else - match (amo_mnemonic_matches_prefix - _stringappend_0_) with - | Some - (op,(existT _ _stringappend_327_ _)) => - let _stringappend_328_ := - string_drop - _stringappend_0_ - (build_ex _stringappend_327_) in - and_boolM - (returnm ((string_startswith - _stringappend_328_ - ".") - : bool)) - (let _stringappend_329_ := - string_drop - _stringappend_328_ - (build_ex (projT1 (string_length - "."))) in - match (size_mnemonic_matches_prefix - _stringappend_329_) with - | Some - (width,(existT _ _stringappend_330_ _)) => - let _stringappend_331_ := - string_drop - _stringappend_329_ - (build_ex _stringappend_330_) in - match (maybe_aq_matches_prefix - _stringappend_331_) with - | Some - (aq,(existT _ _stringappend_332_ _)) => - let _stringappend_333_ := - string_drop - _stringappend_331_ - (build_ex _stringappend_332_) in - match (maybe_rl_matches_prefix - _stringappend_333_) with - | Some - (rl,(existT _ _stringappend_334_ _)) => - let _stringappend_335_ := - string_drop - _stringappend_333_ - (build_ex _stringappend_334_) in - match (spc_matches_prefix - _stringappend_335_) with - | Some - (tt,(existT _ _stringappend_336_ _)) => - let _stringappend_337_ := - string_drop - _stringappend_335_ - (build_ex _stringappend_336_) in - match (reg_name_matches_prefix - _stringappend_337_) with - | Some - (rd,(existT _ _stringappend_338_ _)) => - let _stringappend_339_ := - string_drop - _stringappend_337_ - (build_ex _stringappend_338_) in - sep_matches_prefix - _stringappend_339_ >>= fun w__507 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__507 with - | Some - (tt,(existT _ _stringappend_340_ _)) => - let _stringappend_341_ := - string_drop - _stringappend_339_ - (build_ex _stringappend_340_) in - match (reg_name_matches_prefix - _stringappend_341_) with - | Some - (rs1,(existT _ _stringappend_342_ _)) => - let _stringappend_343_ := - string_drop - _stringappend_341_ - (build_ex _stringappend_342_) in - sep_matches_prefix - _stringappend_343_ >>= fun w__508 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if - ((match w__508 with - | Some - (tt,(existT _ _stringappend_344_ _)) => - let _stringappend_345_ := - string_drop - _stringappend_343_ - (build_ex _stringappend_344_) in - if - ((match (reg_name_matches_prefix - _stringappend_345_) with - | Some - (rs2,(existT _ _stringappend_346_ _)) => - match (string_drop - _stringappend_345_ - (build_ex _stringappend_346_)) with - | s_ => - true - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__509 : bool => - returnm ((if - (w__509) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__510 : bool => - returnm ((if - (w__510) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__511 : bool => - returnm ((if - (w__511) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__512 : bool => - returnm ((if (w__512) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__513 : bool => - returnm ((if (w__513) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__514 : bool => - returnm ((if (w__514) - then - true - else false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__515 : bool => - returnm ((if (w__515) - then - true - else false) - : bool)) >>= fun w__516 : bool => - returnm ((if (w__516) - then - true - else false) - : bool) - | None => - returnm (false : bool) - end >>= fun w__517 : bool => - (if (w__517) then - (match (amo_mnemonic_matches_prefix - _stringappend_0_) with - | Some - (op,(existT _ _stringappend_327_ _)) => - returnm (op, build_ex _stringappend_327_) - | _ => - exit tt - : M ((amoop * {n : Z & ArithFact (n >= - 0)})) - end : M ((amoop * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(op, existT _ _stringappend_327_ _) => - let _stringappend_328_ := - string_drop - _stringappend_0_ - (build_ex _stringappend_327_) in - let _stringappend_329_ := - string_drop - _stringappend_328_ - (build_ex (projT1 (string_length - "."))) in - (match (size_mnemonic_matches_prefix - _stringappend_329_) with - | Some - (width,(existT _ _stringappend_330_ _)) => - returnm (width, build_ex _stringappend_330_) - | _ => - exit tt - : M ((word_width * {n : Z & ArithFact (n >= - 0)})) - end : M ((word_width * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(width, existT _ _stringappend_330_ _) => - let _stringappend_331_ := - string_drop - _stringappend_329_ - (build_ex _stringappend_330_) in - (match (maybe_aq_matches_prefix - _stringappend_331_) with - | Some - (aq,(existT _ _stringappend_332_ _)) => - returnm (aq, build_ex _stringappend_332_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(aq, existT _ _stringappend_332_ _) => - let _stringappend_333_ := - string_drop - _stringappend_331_ - (build_ex _stringappend_332_) in - (match (maybe_rl_matches_prefix - _stringappend_333_) with - | Some - (rl,(existT _ _stringappend_334_ _)) => - returnm (rl, build_ex _stringappend_334_) - | _ => - exit tt - : M ((bool * {n : Z & ArithFact (n >= - 0)})) - end : M ((bool * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rl, existT _ _stringappend_334_ _) => - let _stringappend_335_ := - string_drop - _stringappend_333_ - (build_ex _stringappend_334_) in - (match (spc_matches_prefix - _stringappend_335_) with - | Some - (tt,(existT _ _stringappend_336_ _)) => - returnm (tt, build_ex _stringappend_336_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_336_ _) => - let _stringappend_337_ := - string_drop - _stringappend_335_ - (build_ex _stringappend_336_) in - (match (reg_name_matches_prefix - _stringappend_337_) with - | Some - (rd,(existT _ _stringappend_338_ _)) => - returnm (rd, build_ex _stringappend_338_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_338_ _) => - let _stringappend_339_ := - string_drop - _stringappend_337_ - (build_ex _stringappend_338_) in - sep_matches_prefix - _stringappend_339_ >>= fun w__530 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__530 with - | Some - (tt,(existT _ _stringappend_340_ _)) => - returnm (tt, build_ex _stringappend_340_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_340_ _) => - let _stringappend_341_ := - string_drop - _stringappend_339_ - (build_ex _stringappend_340_) in - (match (reg_name_matches_prefix - _stringappend_341_) with - | Some - (rs1,(existT _ _stringappend_342_ _)) => - returnm (rs1, build_ex _stringappend_342_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_342_ _) => - let _stringappend_343_ := - string_drop - _stringappend_341_ - (build_ex _stringappend_342_) in - sep_matches_prefix - _stringappend_343_ >>= fun w__535 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__535 with - | Some - (tt,(existT _ _stringappend_344_ _)) => - returnm (tt, build_ex _stringappend_344_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_344_ _) => - let _stringappend_345_ := - string_drop - _stringappend_343_ - (build_ex _stringappend_344_) in - (match (reg_name_matches_prefix - _stringappend_345_) with - | Some - (rs2,(existT _ _stringappend_346_ _)) => - returnm (rs2, build_ex _stringappend_346_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs2, existT _ _stringappend_346_ _) => - returnm ((match (string_drop - _stringappend_345_ - (build_ex _stringappend_346_)) with - | s_ => - Some - ((AMO - (op, - aq, rl, - rs2, - rs1, - width, - rd), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= - 0)}))) - else - match (csr_mnemonic_matches_prefix - _stringappend_0_) with - | Some - (op,(existT _ _stringappend_348_ _)) => - let _stringappend_349_ := - string_drop - _stringappend_0_ - (build_ex _stringappend_348_) in - and_boolM - (returnm ((string_startswith - _stringappend_349_ - "i") - : bool)) - (let _stringappend_350_ := - string_drop - _stringappend_349_ - (build_ex (projT1 (string_length - "i"))) in - match (spc_matches_prefix - _stringappend_350_) with - | Some - (tt,(existT _ _stringappend_351_ _)) => - let _stringappend_352_ := - string_drop - _stringappend_350_ - (build_ex _stringappend_351_) in - match (reg_name_matches_prefix - _stringappend_352_) with - | Some - (rd,(existT _ _stringappend_353_ _)) => - let _stringappend_354_ := - string_drop - _stringappend_352_ - (build_ex _stringappend_353_) in - sep_matches_prefix - _stringappend_354_ >>= fun w__540 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__540 with - | Some - (tt,(existT _ _stringappend_355_ _)) => - let _stringappend_356_ := - string_drop - _stringappend_354_ - (build_ex _stringappend_355_) in - match (hex_bits_5_matches_prefix - _stringappend_356_) with - | Some - (rs1,(existT _ _stringappend_357_ _)) => - let _stringappend_358_ := - string_drop - _stringappend_356_ - (build_ex _stringappend_357_) in - sep_matches_prefix - _stringappend_358_ >>= fun w__541 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if - ((match w__541 with - | Some - (tt,(existT _ _stringappend_359_ _)) => - let _stringappend_360_ := - string_drop - _stringappend_358_ - (build_ex _stringappend_359_) in - if - ((match (csr_name_map_matches_prefix - _stringappend_360_) with - | Some - (csr,(existT _ _stringappend_361_ _)) => - match (string_drop - _stringappend_360_ - (build_ex _stringappend_361_)) with - | s_ => - true - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__542 : bool => - returnm ((if - (w__542) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__543 : bool => - returnm ((if (w__543) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__544 : bool => - returnm ((if (w__544) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__545 : bool => - returnm ((if (w__545) - then - true - else false) - : bool)) >>= fun w__546 : bool => - returnm ((if (w__546) - then - true - else false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__547 : bool => - (if (w__547) then - (match (csr_mnemonic_matches_prefix - _stringappend_0_) with - | Some - (op,(existT _ _stringappend_348_ _)) => - returnm (op, build_ex _stringappend_348_) - | _ => - exit tt - : M ((csrop * {n : Z & ArithFact (n >= - 0)})) - end : M ((csrop * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(op, existT _ _stringappend_348_ _) => - let _stringappend_349_ := - string_drop - _stringappend_0_ - (build_ex _stringappend_348_) in - let _stringappend_350_ := - string_drop - _stringappend_349_ - (build_ex (projT1 (string_length - "i"))) in - (match (spc_matches_prefix - _stringappend_350_) with - | Some - (tt,(existT _ _stringappend_351_ _)) => - returnm (tt, build_ex _stringappend_351_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_351_ _) => - let _stringappend_352_ := - string_drop - _stringappend_350_ - (build_ex _stringappend_351_) in - (match (reg_name_matches_prefix - _stringappend_352_) with - | Some - (rd,(existT _ _stringappend_353_ _)) => - returnm (rd, build_ex _stringappend_353_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_353_ _) => - let _stringappend_354_ := - string_drop - _stringappend_352_ - (build_ex _stringappend_353_) in - sep_matches_prefix - _stringappend_354_ >>= fun w__554 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__554 with - | Some - (tt,(existT _ _stringappend_355_ _)) => - returnm (tt, build_ex _stringappend_355_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_355_ _) => - let _stringappend_356_ := - string_drop - _stringappend_354_ - (build_ex _stringappend_355_) in - (match (hex_bits_5_matches_prefix - _stringappend_356_) with - | Some - (rs1,(existT _ _stringappend_357_ _)) => - returnm (rs1, build_ex _stringappend_357_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_357_ _) => - let _stringappend_358_ := - string_drop - _stringappend_356_ - (build_ex _stringappend_357_) in - sep_matches_prefix - _stringappend_358_ >>= fun w__559 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__559 with - | Some - (tt,(existT _ _stringappend_359_ _)) => - returnm (tt, build_ex _stringappend_359_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_359_ _) => - let _stringappend_360_ := - string_drop - _stringappend_358_ - (build_ex _stringappend_359_) in - (match (csr_name_map_matches_prefix - _stringappend_360_) with - | Some - (csr,(existT _ _stringappend_361_ _)) => - returnm (csr, build_ex _stringappend_361_) - | _ => - exit tt - : M ((mword 12 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(csr, existT _ _stringappend_361_ _) => - returnm ((match (string_drop - _stringappend_360_ - (build_ex _stringappend_361_)) with - | s_ => - Some - ((CSR - (csr, - rs1, - rd, - true, - op), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= - 0)}))) - else - match (csr_mnemonic_matches_prefix - _stringappend_0_) with - | Some - (op,(existT _ _stringappend_363_ _)) => - let _stringappend_364_ := - string_drop - _stringappend_0_ - (build_ex _stringappend_363_) in - match (spc_matches_prefix - _stringappend_364_) with - | Some - (tt,(existT _ _stringappend_365_ _)) => - let _stringappend_366_ := - string_drop - _stringappend_364_ - (build_ex _stringappend_365_) in - match (reg_name_matches_prefix - _stringappend_366_) with - | Some - (rd,(existT _ _stringappend_367_ _)) => - let _stringappend_368_ := - string_drop - _stringappend_366_ - (build_ex _stringappend_367_) in - sep_matches_prefix - _stringappend_368_ >>= fun w__564 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - match w__564 with - | Some - (tt,(existT _ _stringappend_369_ _)) => - let _stringappend_370_ := - string_drop - _stringappend_368_ - (build_ex _stringappend_369_) in - match (reg_name_matches_prefix - _stringappend_370_) with - | Some - (rs1,(existT _ _stringappend_371_ _)) => - let _stringappend_372_ := - string_drop - _stringappend_370_ - (build_ex _stringappend_371_) in - sep_matches_prefix - _stringappend_372_ >>= fun w__565 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - returnm ((if - ((match w__565 with - | Some - (tt,(existT _ _stringappend_373_ _)) => - let _stringappend_374_ := - string_drop - _stringappend_372_ - (build_ex _stringappend_373_) in - if - ((match (csr_name_map_matches_prefix - _stringappend_374_) with - | Some - (csr,(existT _ _stringappend_375_ _)) => - match (string_drop - _stringappend_374_ - (build_ex _stringappend_375_)) with - | s_ => - true - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__566 : bool => - returnm ((if - (w__566) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__567 : bool => - returnm ((if (w__567) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__568 : bool => - returnm ((if (w__568) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__569 : bool => - returnm ((if (w__569) - then - true - else - false) - : bool) - | None => - returnm (false - : bool) - end >>= fun w__570 : bool => - (if (w__570) then - (match (csr_mnemonic_matches_prefix - _stringappend_0_) with - | Some - (op,(existT _ _stringappend_363_ _)) => - returnm (op, build_ex _stringappend_363_) - | _ => - exit tt - : M ((csrop * {n : Z & ArithFact (n >= - 0)})) - end : M ((csrop * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(op, existT _ _stringappend_363_ _) => - let _stringappend_364_ := - string_drop - _stringappend_0_ - (build_ex _stringappend_363_) in - (match (spc_matches_prefix - _stringappend_364_) with - | Some - (tt,(existT _ _stringappend_365_ _)) => - returnm (tt, build_ex _stringappend_365_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_365_ _) => - let _stringappend_366_ := - string_drop - _stringappend_364_ - (build_ex _stringappend_365_) in - (match (reg_name_matches_prefix - _stringappend_366_) with - | Some - (rd,(existT _ _stringappend_367_ _)) => - returnm (rd, build_ex _stringappend_367_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rd, existT _ _stringappend_367_ _) => - let _stringappend_368_ := - string_drop - _stringappend_366_ - (build_ex _stringappend_367_) in - sep_matches_prefix - _stringappend_368_ >>= fun w__577 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__577 with - | Some - (tt,(existT _ _stringappend_369_ _)) => - returnm (tt, build_ex _stringappend_369_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_369_ _) => - let _stringappend_370_ := - string_drop - _stringappend_368_ - (build_ex _stringappend_369_) in - (match (reg_name_matches_prefix - _stringappend_370_) with - | Some - (rs1,(existT _ _stringappend_371_ _)) => - returnm (rs1, build_ex _stringappend_371_) - | _ => - exit tt - : M ((mword 5 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 5 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(rs1, existT _ _stringappend_371_ _) => - let _stringappend_372_ := - string_drop - _stringappend_370_ - (build_ex _stringappend_371_) in - sep_matches_prefix - _stringappend_372_ >>= fun w__582 : option ((unit * {n : Z & ArithFact (n >= - 0)})) => - (match w__582 with - | Some - (tt,(existT _ _stringappend_373_ _)) => - returnm (tt, build_ex _stringappend_373_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_373_ _) => - let _stringappend_374_ := - string_drop - _stringappend_372_ - (build_ex _stringappend_373_) in - (match (csr_name_map_matches_prefix - _stringappend_374_) with - | Some - (csr,(existT _ _stringappend_375_ _)) => - returnm (csr, build_ex _stringappend_375_) - | _ => - exit tt - : M ((mword 12 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 12 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(csr, existT _ _stringappend_375_ _) => - returnm ((match (string_drop - _stringappend_374_ - (build_ex _stringappend_375_)) with - | s_ => - Some - ((CSR - (csr, - rs1, - rd, - false, - op), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= - 0)}))) - else if ((andb - (string_startswith - _stringappend_0_ - "illegal") - (let _stringappend_377_ := - string_drop - _stringappend_0_ - (build_ex (projT1 (string_length - "illegal"))) in - if ((match (spc_matches_prefix - _stringappend_377_) with - | Some - (tt,(existT _ _stringappend_378_ _)) => - let _stringappend_379_ := - string_drop - _stringappend_377_ - (build_ex _stringappend_378_) in - if - ((match (hex_bits_32_matches_prefix - _stringappend_379_) with - | Some - (s,(existT _ _stringappend_380_ _)) => - match (string_drop - _stringappend_379_ - (build_ex _stringappend_380_)) with - | s_ => - true - end - | None => - false - end)) - then - true - else - false - | None => - false - end)) - then - true - else - false))) - then - let _stringappend_377_ := - string_drop - _stringappend_0_ - (build_ex (projT1 (string_length - "illegal"))) in - (match (spc_matches_prefix - _stringappend_377_) with - | Some - (tt,(existT _ _stringappend_378_ _)) => - returnm (tt, build_ex _stringappend_378_) - | _ => - exit tt - : M ((unit * {n : Z & ArithFact (n >= - 0)})) - end : M ((unit * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(tt, existT _ _stringappend_378_ _) => - let _stringappend_379_ := - string_drop - _stringappend_377_ - (build_ex _stringappend_378_) in - (match (hex_bits_32_matches_prefix - _stringappend_379_) with - | Some - (s,(existT _ _stringappend_380_ _)) => - returnm (s, build_ex _stringappend_380_) - | _ => - exit tt - : M ((mword 32 * {n : Z & ArithFact (n >= - 0)})) - end : M ((mword 32 * {n : Z & ArithFact (n >= - 0)}))) >>= fun '(s, existT _ _stringappend_380_ _) => - returnm ((match (string_drop - _stringappend_379_ - (build_ex _stringappend_380_)) with - | s_ => - Some - ((ILLEGAL - (s), build_ex (projT1 (sub_nat - (build_ex (projT1 (string_length - arg_))) - (build_ex (projT1 (string_length - s_))))))) - end) - : option ((ast * {n : Z & ArithFact (n >= - 0)}))) - else - returnm (None - : option ((ast * {n : Z & ArithFact (n >= - 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= - 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= - 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= - 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= - 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= - 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= - 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= - 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= - 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= - 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) - : M (option ((ast * {n : Z & ArithFact (n >= 0)}))). -*) -Definition encdec_forwards (arg_ : ast) -: M (mword 32) := - (match arg_ with - | UTYPE (imm,rd,op) => - returnm ((concat_vec (imm : mword 20) (concat_vec (rd : mword 5) (encdec_uop_forwards op))) - : mword (20 + 12)) - | RISCV_JAL (v__172,rd) => - let imm_19 : bits 1 := subrange_vec_dec v__172 20 20 in - let imm_8 : bits 1 := subrange_vec_dec v__172 11 11 in - let imm_7_0 : bits 8 := subrange_vec_dec v__172 19 12 in - let imm_19 : bits 1 := subrange_vec_dec v__172 20 20 in - let imm_18_13 : bits 6 := subrange_vec_dec v__172 10 5 in - let imm_12_9 : bits 4 := subrange_vec_dec v__172 4 1 in - returnm ((concat_vec (imm_19 : bits 1) - (concat_vec (imm_18_13 : bits 6) - (concat_vec (imm_12_9 : bits 4) - (concat_vec (imm_8 : bits 1) - (concat_vec (imm_7_0 : bits 8) - (concat_vec (rd : mword 5) - (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : mword 7))))))) - : mword 32) - | RISCV_JALR (imm,rs1,rd) => - returnm ((concat_vec (imm : mword 12) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (rd : mword 5) (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : mword 7))))) - : mword (12 + 20)) - | BTYPE (v__174,rs2,rs1,op) => - let imm7_6 : bits 1 := subrange_vec_dec v__174 12 12 in - let imm7_6 : bits 1 := subrange_vec_dec v__174 12 12 in - let imm7_5_0 : bits 6 := subrange_vec_dec v__174 10 5 in - let imm5_4_1 : bits 4 := subrange_vec_dec v__174 4 1 in - let imm5_0 : bits 1 := subrange_vec_dec v__174 11 11 in - returnm ((concat_vec (imm7_6 : bits 1) - (concat_vec (imm7_5_0 : bits 6) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (encdec_bop_forwards op) - (concat_vec (imm5_4_1 : bits 4) - (concat_vec (imm5_0 : bits 1) - (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : mword 7)))))))) - : mword 32) - | ITYPE (imm,rs1,rd,op) => - returnm ((concat_vec (imm : mword 12) - (concat_vec (rs1 : mword 5) - (concat_vec (encdec_iop_forwards op) - (concat_vec (rd : mword 5) (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7))))) - : mword (12 + 20)) - | SHIFTIOP (shamt,rs1,rd,RISCV_SLLI) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6) - (concat_vec (shamt : mword 6) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7)))))) - : mword (6 + 26)) - | SHIFTIOP (shamt,rs1,rd,RISCV_SRLI) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6) - (concat_vec (shamt : mword 6) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7)))))) - : mword (6 + 26)) - | SHIFTIOP (shamt,rs1,rd,RISCV_SRAI) => - returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0] : mword 6) - (concat_vec (shamt : mword 6) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7)))))) - : mword (6 + 26)) - | RTYPE (rs2,rs1,rd,RISCV_ADD) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | RTYPE (rs2,rs1,rd,RISCV_SUB) => - returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | RTYPE (rs2,rs1,rd,RISCV_SLL) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | RTYPE (rs2,rs1,rd,RISCV_SLT) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B0;B1;B0] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | RTYPE (rs2,rs1,rd,RISCV_SLTU) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B0;B1;B1] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | RTYPE (rs2,rs1,rd,RISCV_XOR) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B1;B0;B0] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | RTYPE (rs2,rs1,rd,RISCV_SRL) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | RTYPE (rs2,rs1,rd,RISCV_SRA) => - returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | RTYPE (rs2,rs1,rd,RISCV_OR) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B1;B1;B0] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | RTYPE (rs2,rs1,rd,RISCV_AND) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B1;B1;B1] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | LOAD (imm,rs1,rd,is_unsigned,size,false,false) => - returnm ((concat_vec (imm : mword 12) - (concat_vec (rs1 : mword 5) - (concat_vec (bool_bits_forwards is_unsigned) - (concat_vec (size_bits_forwards size) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : mword 7)))))) - : mword (12 + 20)) - | STORE (v__176,rs2,rs1,size,false,false) => - let imm7 : bits 7 := subrange_vec_dec v__176 11 5 in - let imm7 : bits 7 := subrange_vec_dec v__176 11 5 in - let imm5 : bits 5 := subrange_vec_dec v__176 4 0 in - returnm ((concat_vec (imm7 : bits 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B0] : mword 1) - (concat_vec (size_bits_forwards size) - (concat_vec (imm5 : bits 5) - (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : mword 7))))))) - : mword 32) - | ADDIW (imm,rs1,rd) => - returnm ((concat_vec (imm : mword 12) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (rd : mword 5) (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))) - : mword (12 + 20)) - | SHIFTW (shamt,rs1,rd,RISCV_SLLI) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (shamt : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | SHIFTW (shamt,rs1,rd,RISCV_SRLI) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (shamt : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | SHIFTW (shamt,rs1,rd,RISCV_SRAI) => - returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (shamt : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | RTYPEW (rs2,rs1,rd,RISCV_ADDW) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | RTYPEW (rs2,rs1,rd,RISCV_SUBW) => - returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | RTYPEW (rs2,rs1,rd,RISCV_SLLW) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | RTYPEW (rs2,rs1,rd,RISCV_SRLW) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | RTYPEW (rs2,rs1,rd,RISCV_SRAW) => - returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | SHIFTIWOP (shamt,rs1,rd,RISCV_SLLIW) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (shamt : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | SHIFTIWOP (shamt,rs1,rd,RISCV_SRLIW) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (shamt : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | SHIFTIWOP (shamt,rs1,rd,RISCV_SRAIW) => - returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7) - (concat_vec (shamt : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | MUL (rs2,rs1,rd,high,signed1,signed2) => - encdec_mul_op_forwards high signed1 signed2 >>= fun w__0 : mword 3 => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (w__0 : bits 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | DIV (rs2,rs1,rd,s) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B1;B0] : mword 2) - (concat_vec (bool_not_bits_forwards s) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))) - : mword (7 + 25)) - | REM (rs2,rs1,rd,s) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B1;B1] : mword 2) - (concat_vec (bool_not_bits_forwards s) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))) - : mword (7 + 25)) - | MULW (rs2,rs1,rd) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | DIVW (rs2,rs1,rd,s) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B1;B0] : mword 2) - (concat_vec (bool_not_bits_forwards s) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))))) - : mword (7 + 25)) - | REMW (rs2,rs1,rd,s) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B1;B1] : mword 2) - (concat_vec (bool_not_bits_forwards s) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))))) - : mword (7 + 25)) - | FENCE (pred,succ) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) - (concat_vec (pred : mword 4) - (concat_vec (succ : mword 4) - (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) - (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : mword 7))))))) - : mword (4 + 28)) - | FENCEI (tt) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) - (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) - (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) - (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : mword 7))))) - : mword (12 + 20)) - | ECALL (tt) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) - (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) - (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7))))) - : mword (12 + 20)) - | MRET (tt) => - returnm ((concat_vec (vec_of_bits [B0;B0;B1;B1;B0;B0;B0] : mword 7) - (concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5) - (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) - (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | SRET (tt) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B0] : mword 7) - (concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5) - (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) - (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | EBREAK (tt) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12) - (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) - (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7))))) - : mword (12 + 20)) - | WFI (tt) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12) - (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) - (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7))))) - : mword (12 + 20)) - | SFENCE_VMA (rs1,rs2) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : mword 7) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) - (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7)))))) - : mword (7 + 25)) - | LOADRES (aq,rl,rs1,size,rd) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5) - (concat_vec (bool_bits_forwards aq) - (concat_vec (bool_bits_forwards rl) - (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B0] : mword 1) - (concat_vec (size_bits_forwards size) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7))))))))) - : mword (5 + 27)) - | STORECON (aq,rl,rs2,rs1,size,rd) => - returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B1] : mword 5) - (concat_vec (bool_bits_forwards aq) - (concat_vec (bool_bits_forwards rl) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B0] : mword 1) - (concat_vec (size_bits_forwards size) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7))))))))) - : mword (5 + 27)) - | AMO (op,aq,rl,rs2,rs1,size,rd) => - returnm ((concat_vec (encdec_amoop_forwards op) - (concat_vec (bool_bits_forwards aq) - (concat_vec (bool_bits_forwards rl) - (concat_vec (rs2 : mword 5) - (concat_vec (rs1 : mword 5) - (concat_vec (vec_of_bits [B0] : mword 1) - (concat_vec (size_bits_forwards size) - (concat_vec (rd : mword 5) - (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7))))))))) - : mword (5 + 27)) - | CSR (csr,rs1,rd,is_imm,op) => - returnm ((concat_vec (csr : mword 12) - (concat_vec (rs1 : mword 5) - (concat_vec (bool_bits_forwards is_imm) - (concat_vec (encdec_csrop_forwards op) - (concat_vec (rd : mword 5) - (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7)))))) - : mword (12 + 20)) - | STOP_FETCHING (tt) => - returnm ((concat_vec - (vec_of_bits [B1;B1;B1;B1;B1;B0;B1;B0;B1;B1;B0;B1;B1;B1;B1;B0] : mword 16) - (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8) - (concat_vec (vec_of_bits [B0] : mword 1) - (concat_vec (vec_of_bits [B0;B0] : mword 2) - (concat_vec (vec_of_bits [B0;B1;B0] : mword 3) - (vec_of_bits [B1;B1] : mword 2)))))) - : mword (16 + 16)) - | THREAD_START (tt) => - returnm ((concat_vec - (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1;B1;B1;B0] : mword 16) - (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8) - (concat_vec (vec_of_bits [B0] : mword 1) - (concat_vec (vec_of_bits [B0;B0] : mword 2) - (concat_vec (vec_of_bits [B0;B1;B0] : mword 3) - (vec_of_bits [B1;B1] : mword 2)))))) - : mword (16 + 16)) - | ILLEGAL (s) => returnm (s : mword 32) - | _ => exit tt : M (mword 32) - end) - : M (mword 32). - -Definition encdec_backwards (arg_ : mword 32) -: ast := - let v__177 := arg_ in - if ((let _mappingpatterns_23_ := subrange_vec_dec v__177 6 0 in - andb (encdec_uop_backwards_matches _mappingpatterns_23_) - (if ((encdec_uop_backwards_matches _mappingpatterns_23_)) then - let op := encdec_uop_backwards _mappingpatterns_23_ in - true - else false))) then - let imm : mword 20 := subrange_vec_dec v__177 31 12 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - let imm : mword 20 := subrange_vec_dec v__177 31 12 in - let _mappingpatterns_23_ := subrange_vec_dec v__177 6 0 in - let op := encdec_uop_backwards _mappingpatterns_23_ in - UTYPE - (imm, rd, op) - else if ((eq_vec (subrange_vec_dec v__177 6 0) (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : mword 7))) - then - let imm_19 : bits 1 := subrange_vec_dec v__177 31 31 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - let imm_8 : bits 1 := subrange_vec_dec v__177 20 20 in - let imm_7_0 : bits 8 := subrange_vec_dec v__177 19 12 in - let imm_19 : bits 1 := subrange_vec_dec v__177 31 31 in - let imm_18_13 : bits 6 := subrange_vec_dec v__177 30 25 in - let imm_12_9 : bits 4 := subrange_vec_dec v__177 24 21 in - RISCV_JAL - (concat_vec (imm_19 : bits 1) - (concat_vec (imm_7_0 : bits 8) - (concat_vec (imm_8 : bits 1) - (concat_vec (imm_18_13 : bits 6) - (concat_vec (imm_12_9 : bits 4) (vec_of_bits [B0] : mword 1))))), rd) - else if ((andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B0;B0;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : mword 7)))) - then - let imm : mword 12 := subrange_vec_dec v__177 31 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - let imm : mword 12 := subrange_vec_dec v__177 31 20 in - RISCV_JALR - (imm, rs1, rd) - else if ((andb - (let _mappingpatterns_24_ := subrange_vec_dec v__177 14 12 in - andb (encdec_bop_backwards_matches _mappingpatterns_24_) - (if ((encdec_bop_backwards_matches _mappingpatterns_24_)) then - let op := encdec_bop_backwards _mappingpatterns_24_ in - true - else false)) - (eq_vec (subrange_vec_dec v__177 6 0) (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : mword 7)))) - then - let imm7_6 : bits 1 := subrange_vec_dec v__177 31 31 in - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let imm7_6 : bits 1 := subrange_vec_dec v__177 31 31 in - let imm7_5_0 : bits 6 := subrange_vec_dec v__177 30 25 in - let imm5_4_1 : bits 4 := subrange_vec_dec v__177 11 8 in - let imm5_0 : bits 1 := subrange_vec_dec v__177 7 7 in - let _mappingpatterns_24_ := subrange_vec_dec v__177 14 12 in - let op := encdec_bop_backwards _mappingpatterns_24_ in - BTYPE - (concat_vec (imm7_6 : bits 1) - (concat_vec (imm5_0 : bits 1) - (concat_vec (imm7_5_0 : bits 6) - (concat_vec (imm5_4_1 : bits 4) (vec_of_bits [B0] : mword 1)))), rs2, rs1, op) - else if ((andb - (let _mappingpatterns_25_ := subrange_vec_dec v__177 14 12 in - andb (encdec_iop_backwards_matches _mappingpatterns_25_) - (if ((encdec_iop_backwards_matches _mappingpatterns_25_)) then - let op := encdec_iop_backwards _mappingpatterns_25_ in - true - else false)) - (eq_vec (subrange_vec_dec v__177 6 0) (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7)))) - then - let imm : mword 12 := subrange_vec_dec v__177 31 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - let imm : mword 12 := subrange_vec_dec v__177 31 20 in - let _mappingpatterns_25_ := subrange_vec_dec v__177 14 12 in - let op := encdec_iop_backwards _mappingpatterns_25_ in - ITYPE - (imm, rs1, rd, op) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B0;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7))))) then - let shamt : mword 6 := subrange_vec_dec v__177 25 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - SHIFTIOP - (shamt, rs1, rd, RISCV_SLLI) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7))))) then - let shamt : mword 6 := subrange_vec_dec v__177 25 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - SHIFTIOP - (shamt, rs1, rd, RISCV_SRLI) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 26) (vec_of_bits [B0;B1;B0;B0;B0;B0] : mword 6)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7))))) then - let shamt : mword 6 := subrange_vec_dec v__177 25 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - SHIFTIOP - (shamt, rs1, rd, RISCV_SRAI) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B0;B0;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - RTYPE - (rs2, rs1, rd, RISCV_ADD) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B0;B0;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - RTYPE - (rs2, rs1, rd, RISCV_SUB) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B0;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - RTYPE - (rs2, rs1, rd, RISCV_SLL) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B0;B1;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - RTYPE - (rs2, rs1, rd, RISCV_SLT) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B0;B1;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - RTYPE - (rs2, rs1, rd, RISCV_SLTU) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B1;B0;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - RTYPE - (rs2, rs1, rd, RISCV_XOR) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - RTYPE - (rs2, rs1, rd, RISCV_SRL) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - RTYPE - (rs2, rs1, rd, RISCV_SRA) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B1;B1;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - RTYPE - (rs2, rs1, rd, RISCV_OR) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B1;B1;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - RTYPE - (rs2, rs1, rd, RISCV_AND) - else if ((andb - (let _mappingpatterns_27_ := subrange_vec_dec v__177 13 12 in - let _mappingpatterns_26_ := subrange_vec_dec v__177 14 14 in - andb (size_bits_backwards_matches _mappingpatterns_27_) - (if ((size_bits_backwards_matches _mappingpatterns_27_)) then - let size := size_bits_backwards _mappingpatterns_27_ in - andb (bool_bits_backwards_matches _mappingpatterns_26_) - (if ((bool_bits_backwards_matches _mappingpatterns_26_)) then - let is_unsigned := bool_bits_backwards _mappingpatterns_26_ in - true - else false) - else false)) - (eq_vec (subrange_vec_dec v__177 6 0) (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : mword 7)))) - then - let imm : mword 12 := subrange_vec_dec v__177 31 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - let imm : mword 12 := subrange_vec_dec v__177 31 20 in - let _mappingpatterns_27_ := subrange_vec_dec v__177 13 12 in - let _mappingpatterns_26_ := subrange_vec_dec v__177 14 14 in - let size := size_bits_backwards _mappingpatterns_27_ in - let is_unsigned := bool_bits_backwards _mappingpatterns_26_ in - LOAD - (imm, rs1, rd, is_unsigned, size, false, false) - else if ((andb - (let _mappingpatterns_28_ := subrange_vec_dec v__177 13 12 in - andb (size_bits_backwards_matches _mappingpatterns_28_) - (if ((size_bits_backwards_matches _mappingpatterns_28_)) then - let size := size_bits_backwards _mappingpatterns_28_ in - true - else false)) - (andb (eq_vec (subrange_vec_dec v__177 14 14) (vec_of_bits [B0] : mword 1)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : mword 7))))) then - let imm7 : bits 7 := subrange_vec_dec v__177 31 25 in - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let imm7 : bits 7 := subrange_vec_dec v__177 31 25 in - let imm5 : bits 5 := subrange_vec_dec v__177 11 7 in - let _mappingpatterns_28_ := subrange_vec_dec v__177 13 12 in - let size := size_bits_backwards _mappingpatterns_28_ in - STORE - (concat_vec (imm7 : bits 7) (imm5 : bits 5), rs2, rs1, size, false, false) - else if ((andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B0;B0;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))) - then - let imm : mword 12 := subrange_vec_dec v__177 31 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - let imm : mword 12 := subrange_vec_dec v__177 31 20 in - ADDIW - (imm, rs1, rd) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B0;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))) then - let shamt : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - SHIFTW - (shamt, rs1, rd, RISCV_SLLI) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))) then - let shamt : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - SHIFTW - (shamt, rs1, rd, RISCV_SRLI) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))) then - let shamt : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - SHIFTW - (shamt, rs1, rd, RISCV_SRAI) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B0;B0;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - RTYPEW - (rs2, rs1, rd, RISCV_ADDW) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B0;B0;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - RTYPEW - (rs2, rs1, rd, RISCV_SUBW) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B0;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - RTYPEW - (rs2, rs1, rd, RISCV_SLLW) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - RTYPEW - (rs2, rs1, rd, RISCV_SRLW) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - RTYPEW - (rs2, rs1, rd, RISCV_SRAW) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B0;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))) then - let shamt : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - SHIFTIWOP - (shamt, rs1, rd, RISCV_SLLIW) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))) then - let shamt : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - SHIFTIWOP - (shamt, rs1, rd, RISCV_SRLIW) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))) then - let shamt : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - SHIFTIWOP - (shamt, rs1, rd, RISCV_SRAIW) - else if ((andb - (let _mappingpatterns_29_ : bits 3 := subrange_vec_dec v__177 14 12 in - andb (encdec_mul_op_backwards_matches _mappingpatterns_29_) - (if ((encdec_mul_op_backwards_matches _mappingpatterns_29_)) then - let '(high, signed1, signed2) := encdec_mul_op_backwards _mappingpatterns_29_ in - true - else false)) - (andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - let _mappingpatterns_29_ : bits 3 := subrange_vec_dec v__177 14 12 in - let '(high, signed1, signed2) := encdec_mul_op_backwards _mappingpatterns_29_ in - MUL - (rs2, rs1, rd, high, signed1, signed2) - else if ((andb - (let _mappingpatterns_30_ := subrange_vec_dec v__177 12 12 in - andb (bool_not_bits_backwards_matches _mappingpatterns_30_) - (if ((bool_not_bits_backwards_matches _mappingpatterns_30_)) then - let s := bool_not_bits_backwards _mappingpatterns_30_ in - true - else false)) - (andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 13) (vec_of_bits [B1;B0] : mword 2)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - let _mappingpatterns_30_ := subrange_vec_dec v__177 12 12 in - let s := bool_not_bits_backwards _mappingpatterns_30_ in - DIV - (rs2, rs1, rd, s) - else if ((andb - (let _mappingpatterns_31_ := subrange_vec_dec v__177 12 12 in - andb (bool_not_bits_backwards_matches _mappingpatterns_31_) - (if ((bool_not_bits_backwards_matches _mappingpatterns_31_)) then - let s := bool_not_bits_backwards _mappingpatterns_31_ in - true - else false)) - (andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 13) (vec_of_bits [B1;B1] : mword 2)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - let _mappingpatterns_31_ := subrange_vec_dec v__177 12 12 in - let s := bool_not_bits_backwards _mappingpatterns_31_ in - REM - (rs2, rs1, rd, s) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 12) (vec_of_bits [B0;B0;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - MULW - (rs2, rs1, rd) - else if ((andb - (let _mappingpatterns_32_ := subrange_vec_dec v__177 12 12 in - andb (bool_not_bits_backwards_matches _mappingpatterns_32_) - (if ((bool_not_bits_backwards_matches _mappingpatterns_32_)) then - let s := bool_not_bits_backwards _mappingpatterns_32_ in - true - else false)) - (andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 13) (vec_of_bits [B1;B0] : mword 2)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - let _mappingpatterns_32_ := subrange_vec_dec v__177 12 12 in - let s := bool_not_bits_backwards _mappingpatterns_32_ in - DIVW - (rs2, rs1, rd, s) - else if ((andb - (let _mappingpatterns_33_ := subrange_vec_dec v__177 12 12 in - andb (bool_not_bits_backwards_matches _mappingpatterns_33_) - (if ((bool_not_bits_backwards_matches _mappingpatterns_33_)) then - let s := bool_not_bits_backwards _mappingpatterns_33_ in - true - else false)) - (andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__177 14 13) (vec_of_bits [B1;B1] : mword 2)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - let _mappingpatterns_33_ := subrange_vec_dec v__177 12 12 in - let s := bool_not_bits_backwards _mappingpatterns_33_ in - REMW - (rs2, rs1, rd, s) - else if ((andb (eq_vec (subrange_vec_dec v__177 31 28) (vec_of_bits [B0;B0;B0;B0] : mword 4)) - (eq_vec (subrange_vec_dec v__177 19 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] - : mword 20)))) then - let succ : mword 4 := subrange_vec_dec v__177 23 20 in - let pred : mword 4 := subrange_vec_dec v__177 27 24 in - FENCE - (pred, succ) - else if ((eq_vec v__177 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0; - B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] - : mword 32))) then - FENCEI - (tt) - else if ((eq_vec v__177 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] - : mword 32))) then - ECALL - (tt) - else if ((eq_vec v__177 - (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] - : mword 32))) then - MRET - (tt) - else if ((eq_vec v__177 - (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] - : mword 32))) then - SRET - (tt) - else if ((eq_vec v__177 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] - : mword 32))) then - EBREAK - (tt) - else if ((eq_vec v__177 - (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] - : mword 32))) then - WFI - (tt) - else if ((andb - (eq_vec (subrange_vec_dec v__177 31 25) - (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : mword 7)) - (eq_vec (subrange_vec_dec v__177 14 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] : mword 15)))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - SFENCE_VMA - (rs1, rs2) - else if sumbool_of_bool ((andb - (let _mappingpatterns_36_ := subrange_vec_dec v__177 13 12 in - let _mappingpatterns_35_ := subrange_vec_dec v__177 25 25 in - let _mappingpatterns_34_ := subrange_vec_dec v__177 26 26 in - andb (size_bits_backwards_matches _mappingpatterns_36_) - (if ((size_bits_backwards_matches _mappingpatterns_36_)) then - let size := size_bits_backwards _mappingpatterns_36_ in - andb (bool_bits_backwards_matches _mappingpatterns_35_) - (if ((bool_bits_backwards_matches _mappingpatterns_35_)) then - let rl := bool_bits_backwards _mappingpatterns_35_ in - andb (bool_bits_backwards_matches _mappingpatterns_34_) - (if ((bool_bits_backwards_matches _mappingpatterns_34_)) - then - let aq := bool_bits_backwards _mappingpatterns_34_ in - true - else false) - else false) - else false)) - (andb - (Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno - (subrange_vec_dec v__177 31 27)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)}))) - (andb - (Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno - (subrange_vec_dec v__177 24 20)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)}))) - (andb - (eq_vec (subrange_vec_dec v__177 14 14) - (vec_of_bits [B0] : mword 1)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7))))))) - then - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - let _mappingpatterns_36_ := subrange_vec_dec v__177 13 12 in - let _mappingpatterns_35_ := subrange_vec_dec v__177 25 25 in - let _mappingpatterns_34_ := subrange_vec_dec v__177 26 26 in - let size := size_bits_backwards _mappingpatterns_36_ in - let rl := bool_bits_backwards _mappingpatterns_35_ in - let aq := bool_bits_backwards _mappingpatterns_34_ in - LOADRES - (aq, rl, rs1, size, rd) - else if sumbool_of_bool ((andb - (let _mappingpatterns_39_ := subrange_vec_dec v__177 13 12 in - let _mappingpatterns_38_ := subrange_vec_dec v__177 25 25 in - let _mappingpatterns_37_ := subrange_vec_dec v__177 26 26 in - andb (size_bits_backwards_matches _mappingpatterns_39_) - (if ((size_bits_backwards_matches _mappingpatterns_39_)) then - let size := size_bits_backwards _mappingpatterns_39_ in - andb (bool_bits_backwards_matches _mappingpatterns_38_) - (if ((bool_bits_backwards_matches _mappingpatterns_38_)) then - let rl := bool_bits_backwards _mappingpatterns_38_ in - andb (bool_bits_backwards_matches _mappingpatterns_37_) - (if ((bool_bits_backwards_matches _mappingpatterns_37_)) - then - let aq := bool_bits_backwards _mappingpatterns_37_ in - true - else false) - else false) - else false)) - (andb - (Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno - (subrange_vec_dec v__177 31 27)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)}))) - (andb - (eq_vec (subrange_vec_dec v__177 14 14) - (vec_of_bits [B0] : mword 1)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7)))))) then - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - let _mappingpatterns_39_ := subrange_vec_dec v__177 13 12 in - let _mappingpatterns_38_ := subrange_vec_dec v__177 25 25 in - let _mappingpatterns_37_ := subrange_vec_dec v__177 26 26 in - let size := size_bits_backwards _mappingpatterns_39_ in - let rl := bool_bits_backwards _mappingpatterns_38_ in - let aq := bool_bits_backwards _mappingpatterns_37_ in - STORECON - (aq, rl, rs2, rs1, size, rd) - else if ((andb - (let _mappingpatterns_40_ := subrange_vec_dec v__177 31 27 in - let _mappingpatterns_43_ := subrange_vec_dec v__177 13 12 in - let _mappingpatterns_42_ := subrange_vec_dec v__177 25 25 in - let _mappingpatterns_41_ := subrange_vec_dec v__177 26 26 in - let _mappingpatterns_40_ := subrange_vec_dec v__177 31 27 in - andb (size_bits_backwards_matches _mappingpatterns_43_) - (if ((size_bits_backwards_matches _mappingpatterns_43_)) then - let size := size_bits_backwards _mappingpatterns_43_ in - andb (bool_bits_backwards_matches _mappingpatterns_42_) - (if ((bool_bits_backwards_matches _mappingpatterns_42_)) then - let rl := bool_bits_backwards _mappingpatterns_42_ in - andb (bool_bits_backwards_matches _mappingpatterns_41_) - (if ((bool_bits_backwards_matches _mappingpatterns_41_)) then - let aq := bool_bits_backwards _mappingpatterns_41_ in - andb (encdec_amoop_backwards_matches _mappingpatterns_40_) - (if ((encdec_amoop_backwards_matches _mappingpatterns_40_)) then - let op := encdec_amoop_backwards _mappingpatterns_40_ in - true - else false) - else false) - else false) - else false)) - (andb (eq_vec (subrange_vec_dec v__177 14 14) (vec_of_bits [B0] : mword 1)) - (eq_vec (subrange_vec_dec v__177 6 0) - (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7))))) then - let _mappingpatterns_40_ := subrange_vec_dec v__177 31 27 in - let rs2 : mword 5 := subrange_vec_dec v__177 24 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - let _mappingpatterns_43_ := subrange_vec_dec v__177 13 12 in - let _mappingpatterns_42_ := subrange_vec_dec v__177 25 25 in - let _mappingpatterns_41_ := subrange_vec_dec v__177 26 26 in - let _mappingpatterns_40_ := subrange_vec_dec v__177 31 27 in - let size := size_bits_backwards _mappingpatterns_43_ in - let rl := bool_bits_backwards _mappingpatterns_42_ in - let aq := bool_bits_backwards _mappingpatterns_41_ in - let op := encdec_amoop_backwards _mappingpatterns_40_ in - AMO - (op, aq, rl, rs2, rs1, size, rd) - else if ((andb - (let _mappingpatterns_45_ := subrange_vec_dec v__177 13 12 in - let _mappingpatterns_44_ := subrange_vec_dec v__177 14 14 in - andb (encdec_csrop_backwards_matches _mappingpatterns_45_) - (if ((encdec_csrop_backwards_matches _mappingpatterns_45_)) then - let op := encdec_csrop_backwards _mappingpatterns_45_ in - andb (bool_bits_backwards_matches _mappingpatterns_44_) - (if ((bool_bits_backwards_matches _mappingpatterns_44_)) then - let is_imm := bool_bits_backwards _mappingpatterns_44_ in - true - else false) - else false)) - (eq_vec (subrange_vec_dec v__177 6 0) (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7)))) - then - let csr : mword 12 := subrange_vec_dec v__177 31 20 in - let rs1 : mword 5 := subrange_vec_dec v__177 19 15 in - let rd : mword 5 := subrange_vec_dec v__177 11 7 in - let csr : mword 12 := subrange_vec_dec v__177 31 20 in - let _mappingpatterns_45_ := subrange_vec_dec v__177 13 12 in - let _mappingpatterns_44_ := subrange_vec_dec v__177 14 14 in - let op := encdec_csrop_backwards _mappingpatterns_45_ in - let is_imm := bool_bits_backwards _mappingpatterns_44_ in - CSR - (csr, rs1, rd, is_imm, op) - else if ((eq_vec v__177 - (vec_of_bits [B1;B1;B1;B1;B1;B0;B1;B0;B1;B1;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] - : mword 32))) then - STOP_FETCHING - (tt) - else if ((eq_vec v__177 - (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] - : mword 32))) then - THREAD_START - (tt) - else ILLEGAL (v__177). - -Definition encdec_forwards_matches (arg_ : ast) -: bool := - match arg_ with - | UTYPE (imm,rd,op) => true - | RISCV_JAL (v__391,rd) => - if ((eq_vec (subrange_vec_dec v__391 0 0) (vec_of_bits [B0] : mword 1))) then true - else - let g__13 := RISCV_JAL (v__391, rd) in - false - | RISCV_JALR (imm,rs1,rd) => true - | BTYPE (v__393,rs2,rs1,op) => - if ((eq_vec (subrange_vec_dec v__393 0 0) (vec_of_bits [B0] : mword 1))) then true - else - let g__13 := BTYPE (v__393, rs2, rs1, op) in - false - | ITYPE (imm,rs1,rd,op) => true - | SHIFTIOP (shamt,rs1,rd,RISCV_SLLI) => true - | SHIFTIOP (shamt,rs1,rd,RISCV_SRLI) => true - | SHIFTIOP (shamt,rs1,rd,RISCV_SRAI) => true - | RTYPE (rs2,rs1,rd,RISCV_ADD) => true - | RTYPE (rs2,rs1,rd,RISCV_SUB) => true - | RTYPE (rs2,rs1,rd,RISCV_SLL) => true - | RTYPE (rs2,rs1,rd,RISCV_SLT) => true - | RTYPE (rs2,rs1,rd,RISCV_SLTU) => true - | RTYPE (rs2,rs1,rd,RISCV_XOR) => true - | RTYPE (rs2,rs1,rd,RISCV_SRL) => true - | RTYPE (rs2,rs1,rd,RISCV_SRA) => true - | RTYPE (rs2,rs1,rd,RISCV_OR) => true - | RTYPE (rs2,rs1,rd,RISCV_AND) => true - | LOAD (imm,rs1,rd,is_unsigned,size,false,false) => true - | STORE (v__395,rs2,rs1,size,false,false) => true - | ADDIW (imm,rs1,rd) => true - | SHIFTW (shamt,rs1,rd,RISCV_SLLI) => true - | SHIFTW (shamt,rs1,rd,RISCV_SRLI) => true - | SHIFTW (shamt,rs1,rd,RISCV_SRAI) => true - | RTYPEW (rs2,rs1,rd,RISCV_ADDW) => true - | RTYPEW (rs2,rs1,rd,RISCV_SUBW) => true - | RTYPEW (rs2,rs1,rd,RISCV_SLLW) => true - | RTYPEW (rs2,rs1,rd,RISCV_SRLW) => true - | RTYPEW (rs2,rs1,rd,RISCV_SRAW) => true - | SHIFTIWOP (shamt,rs1,rd,RISCV_SLLIW) => true - | SHIFTIWOP (shamt,rs1,rd,RISCV_SRLIW) => true - | SHIFTIWOP (shamt,rs1,rd,RISCV_SRAIW) => true - | MUL (rs2,rs1,rd,high,signed1,signed2) => true - | DIV (rs2,rs1,rd,s) => true - | REM (rs2,rs1,rd,s) => true - | MULW (rs2,rs1,rd) => true - | DIVW (rs2,rs1,rd,s) => true - | REMW (rs2,rs1,rd,s) => true - | FENCE (pred,succ) => true - | FENCEI (tt) => true - | ECALL (tt) => true - | MRET (tt) => true - | SRET (tt) => true - | EBREAK (tt) => true - | WFI (tt) => true - | SFENCE_VMA (rs1,rs2) => true - | LOADRES (aq,rl,rs1,size,rd) => true - | STORECON (aq,rl,rs2,rs1,size,rd) => true - | AMO (op,aq,rl,rs2,rs1,size,rd) => true - | CSR (csr,rs1,rd,is_imm,op) => true - | STOP_FETCHING (tt) => true - | THREAD_START (tt) => true - | ILLEGAL (s) => true - | g__13 => false - end. - -Definition encdec_backwards_matches (arg_ : mword 32) -: bool := - let v__396 := arg_ in - if ((let _mappingpatterns_0_ := subrange_vec_dec v__396 6 0 in - andb (encdec_uop_backwards_matches _mappingpatterns_0_) - (if ((encdec_uop_backwards_matches _mappingpatterns_0_)) then - let op := encdec_uop_backwards _mappingpatterns_0_ in - true - else false))) then - let _mappingpatterns_0_ := subrange_vec_dec v__396 6 0 in - let op := encdec_uop_backwards _mappingpatterns_0_ in - true - else if ((eq_vec (subrange_vec_dec v__396 6 0) (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : mword 7))) - then - true - else if ((andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B0;B0;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : mword 7)))) - then - true - else if ((andb - (let _mappingpatterns_1_ := subrange_vec_dec v__396 14 12 in - andb (encdec_bop_backwards_matches _mappingpatterns_1_) - (if ((encdec_bop_backwards_matches _mappingpatterns_1_)) then - let op := encdec_bop_backwards _mappingpatterns_1_ in - true - else false)) - (eq_vec (subrange_vec_dec v__396 6 0) (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : mword 7)))) - then - let _mappingpatterns_1_ := subrange_vec_dec v__396 14 12 in - let op := encdec_bop_backwards _mappingpatterns_1_ in - true - else if ((andb - (let _mappingpatterns_2_ := subrange_vec_dec v__396 14 12 in - andb (encdec_iop_backwards_matches _mappingpatterns_2_) - (if ((encdec_iop_backwards_matches _mappingpatterns_2_)) then - let op := encdec_iop_backwards _mappingpatterns_2_ in - true - else false)) - (eq_vec (subrange_vec_dec v__396 6 0) (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7)))) - then - let _mappingpatterns_2_ := subrange_vec_dec v__396 14 12 in - let op := encdec_iop_backwards _mappingpatterns_2_ in - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B0;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 26) (vec_of_bits [B0;B1;B0;B0;B0;B0] : mword 6)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B0;B0;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B0;B0;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B0;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B0;B1;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B0;B1;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B1;B0;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B1;B1;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B1;B1;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (let _mappingpatterns_4_ := subrange_vec_dec v__396 13 12 in - let _mappingpatterns_3_ := subrange_vec_dec v__396 14 14 in - andb (size_bits_backwards_matches _mappingpatterns_4_) - (if ((size_bits_backwards_matches _mappingpatterns_4_)) then - let size := size_bits_backwards _mappingpatterns_4_ in - andb (bool_bits_backwards_matches _mappingpatterns_3_) - (if ((bool_bits_backwards_matches _mappingpatterns_3_)) then - let is_unsigned := bool_bits_backwards _mappingpatterns_3_ in - true - else false) - else false)) - (eq_vec (subrange_vec_dec v__396 6 0) (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : mword 7)))) - then - let _mappingpatterns_4_ := subrange_vec_dec v__396 13 12 in - let _mappingpatterns_3_ := subrange_vec_dec v__396 14 14 in - let size := size_bits_backwards _mappingpatterns_4_ in - let is_unsigned := bool_bits_backwards _mappingpatterns_3_ in - true - else if ((andb - (let _mappingpatterns_5_ := subrange_vec_dec v__396 13 12 in - andb (size_bits_backwards_matches _mappingpatterns_5_) - (if ((size_bits_backwards_matches _mappingpatterns_5_)) then - let size := size_bits_backwards _mappingpatterns_5_ in - true - else false)) - (andb (eq_vec (subrange_vec_dec v__396 14 14) (vec_of_bits [B0] : mword 1)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : mword 7))))) then - let _mappingpatterns_5_ := subrange_vec_dec v__396 13 12 in - let size := size_bits_backwards _mappingpatterns_5_ in - true - else if ((andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B0;B0;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))) - then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B0;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B0;B0;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B0;B0;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B0;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B0;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B1;B0;B1] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (let _mappingpatterns_6_ : bits 3 := subrange_vec_dec v__396 14 12 in - andb (encdec_mul_op_backwards_matches _mappingpatterns_6_) - (if ((encdec_mul_op_backwards_matches _mappingpatterns_6_)) then - let '(high, signed1, signed2) := encdec_mul_op_backwards _mappingpatterns_6_ in - true - else false)) - (andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))) then - let _mappingpatterns_6_ : bits 3 := subrange_vec_dec v__396 14 12 in - let '(high, signed1, signed2) := encdec_mul_op_backwards _mappingpatterns_6_ in - true - else if ((andb - (let _mappingpatterns_7_ := subrange_vec_dec v__396 12 12 in - andb (bool_not_bits_backwards_matches _mappingpatterns_7_) - (if ((bool_not_bits_backwards_matches _mappingpatterns_7_)) then - let s := bool_not_bits_backwards _mappingpatterns_7_ in - true - else false)) - (andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 13) (vec_of_bits [B1;B0] : mword 2)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) then - let _mappingpatterns_7_ := subrange_vec_dec v__396 12 12 in - let s := bool_not_bits_backwards _mappingpatterns_7_ in - true - else if ((andb - (let _mappingpatterns_8_ := subrange_vec_dec v__396 12 12 in - andb (bool_not_bits_backwards_matches _mappingpatterns_8_) - (if ((bool_not_bits_backwards_matches _mappingpatterns_8_)) then - let s := bool_not_bits_backwards _mappingpatterns_8_ in - true - else false)) - (andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 13) (vec_of_bits [B1;B1] : mword 2)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) then - let _mappingpatterns_8_ := subrange_vec_dec v__396 12 12 in - let s := bool_not_bits_backwards _mappingpatterns_8_ in - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 12) (vec_of_bits [B0;B0;B0] : mword 3)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))) then - true - else if ((andb - (let _mappingpatterns_9_ := subrange_vec_dec v__396 12 12 in - andb (bool_not_bits_backwards_matches _mappingpatterns_9_) - (if ((bool_not_bits_backwards_matches _mappingpatterns_9_)) then - let s := bool_not_bits_backwards _mappingpatterns_9_ in - true - else false)) - (andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 13) (vec_of_bits [B1;B0] : mword 2)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) then - let _mappingpatterns_9_ := subrange_vec_dec v__396 12 12 in - let s := bool_not_bits_backwards _mappingpatterns_9_ in - true - else if ((andb - (let _mappingpatterns_10_ := subrange_vec_dec v__396 12 12 in - andb (bool_not_bits_backwards_matches _mappingpatterns_10_) - (if ((bool_not_bits_backwards_matches _mappingpatterns_10_)) then - let s := bool_not_bits_backwards _mappingpatterns_10_ in - true - else false)) - (andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)) - (andb (eq_vec (subrange_vec_dec v__396 14 13) (vec_of_bits [B1;B1] : mword 2)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) then - let _mappingpatterns_10_ := subrange_vec_dec v__396 12 12 in - let s := bool_not_bits_backwards _mappingpatterns_10_ in - true - else if ((andb (eq_vec (subrange_vec_dec v__396 31 28) (vec_of_bits [B0;B0;B0;B0] : mword 4)) - (eq_vec (subrange_vec_dec v__396 19 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] - : mword 20)))) then - true - else if ((eq_vec v__396 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0; - B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] - : mword 32))) then - true - else if ((eq_vec v__396 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] - : mword 32))) then - true - else if ((eq_vec v__396 - (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] - : mword 32))) then - true - else if ((eq_vec v__396 - (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] - : mword 32))) then - true - else if ((eq_vec v__396 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] - : mword 32))) then - true - else if ((eq_vec v__396 - (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] - : mword 32))) then - true - else if ((andb - (eq_vec (subrange_vec_dec v__396 31 25) - (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : mword 7)) - (eq_vec (subrange_vec_dec v__396 14 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] : mword 15)))) then - true - else if sumbool_of_bool ((andb - (let _mappingpatterns_13_ := subrange_vec_dec v__396 13 12 in - let _mappingpatterns_12_ := subrange_vec_dec v__396 25 25 in - let _mappingpatterns_11_ := subrange_vec_dec v__396 26 26 in - andb (size_bits_backwards_matches _mappingpatterns_13_) - (if ((size_bits_backwards_matches _mappingpatterns_13_)) then - let size := size_bits_backwards _mappingpatterns_13_ in - andb (bool_bits_backwards_matches _mappingpatterns_12_) - (if ((bool_bits_backwards_matches _mappingpatterns_12_)) then - let rl := bool_bits_backwards _mappingpatterns_12_ in - andb (bool_bits_backwards_matches _mappingpatterns_11_) - (if ((bool_bits_backwards_matches _mappingpatterns_11_)) - then - let aq := bool_bits_backwards _mappingpatterns_11_ in - true - else false) - else false) - else false)) - (andb - (Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno - (subrange_vec_dec v__396 31 27)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B1;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)}))) - (andb - (Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno - (subrange_vec_dec v__396 24 20)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B0;B0] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)}))) - (andb - (eq_vec (subrange_vec_dec v__396 14 14) - (vec_of_bits [B0] : mword 1)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7))))))) - then - let _mappingpatterns_13_ := subrange_vec_dec v__396 13 12 in - let _mappingpatterns_12_ := subrange_vec_dec v__396 25 25 in - let _mappingpatterns_11_ := subrange_vec_dec v__396 26 26 in - let size := size_bits_backwards _mappingpatterns_13_ in - let rl := bool_bits_backwards _mappingpatterns_12_ in - let aq := bool_bits_backwards _mappingpatterns_11_ in - true - else if sumbool_of_bool ((andb - (let _mappingpatterns_16_ := subrange_vec_dec v__396 13 12 in - let _mappingpatterns_15_ := subrange_vec_dec v__396 25 25 in - let _mappingpatterns_14_ := subrange_vec_dec v__396 26 26 in - andb (size_bits_backwards_matches _mappingpatterns_16_) - (if ((size_bits_backwards_matches _mappingpatterns_16_)) then - let size := size_bits_backwards _mappingpatterns_16_ in - andb (bool_bits_backwards_matches _mappingpatterns_15_) - (if ((bool_bits_backwards_matches _mappingpatterns_15_)) then - let rl := bool_bits_backwards _mappingpatterns_15_ in - andb (bool_bits_backwards_matches _mappingpatterns_14_) - (if ((bool_bits_backwards_matches _mappingpatterns_14_)) - then - let aq := bool_bits_backwards _mappingpatterns_14_ in - true - else false) - else false) - else false)) - (andb - (Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno - (subrange_vec_dec v__396 31 27)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) - (projT1 ((build_ex (projT1 (regbits_to_regno - (vec_of_bits [B0;B0;B0;B1;B1] - : mword 5)))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)}))) - (andb - (eq_vec (subrange_vec_dec v__396 14 14) - (vec_of_bits [B0] : mword 1)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7)))))) then - let _mappingpatterns_16_ := subrange_vec_dec v__396 13 12 in - let _mappingpatterns_15_ := subrange_vec_dec v__396 25 25 in - let _mappingpatterns_14_ := subrange_vec_dec v__396 26 26 in - let size := size_bits_backwards _mappingpatterns_16_ in - let rl := bool_bits_backwards _mappingpatterns_15_ in - let aq := bool_bits_backwards _mappingpatterns_14_ in - true - else if ((andb - (let _mappingpatterns_17_ := subrange_vec_dec v__396 31 27 in - let _mappingpatterns_20_ := subrange_vec_dec v__396 13 12 in - let _mappingpatterns_19_ := subrange_vec_dec v__396 25 25 in - let _mappingpatterns_18_ := subrange_vec_dec v__396 26 26 in - let _mappingpatterns_17_ := subrange_vec_dec v__396 31 27 in - andb (size_bits_backwards_matches _mappingpatterns_20_) - (if ((size_bits_backwards_matches _mappingpatterns_20_)) then - let size := size_bits_backwards _mappingpatterns_20_ in - andb (bool_bits_backwards_matches _mappingpatterns_19_) - (if ((bool_bits_backwards_matches _mappingpatterns_19_)) then - let rl := bool_bits_backwards _mappingpatterns_19_ in - andb (bool_bits_backwards_matches _mappingpatterns_18_) - (if ((bool_bits_backwards_matches _mappingpatterns_18_)) then - let aq := bool_bits_backwards _mappingpatterns_18_ in - andb (encdec_amoop_backwards_matches _mappingpatterns_17_) - (if ((encdec_amoop_backwards_matches _mappingpatterns_17_)) then - let op := encdec_amoop_backwards _mappingpatterns_17_ in - true - else false) - else false) - else false) - else false)) - (andb (eq_vec (subrange_vec_dec v__396 14 14) (vec_of_bits [B0] : mword 1)) - (eq_vec (subrange_vec_dec v__396 6 0) - (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7))))) then - let _mappingpatterns_17_ := subrange_vec_dec v__396 31 27 in - let _mappingpatterns_20_ := subrange_vec_dec v__396 13 12 in - let _mappingpatterns_19_ := subrange_vec_dec v__396 25 25 in - let _mappingpatterns_18_ := subrange_vec_dec v__396 26 26 in - let _mappingpatterns_17_ := subrange_vec_dec v__396 31 27 in - let size := size_bits_backwards _mappingpatterns_20_ in - let rl := bool_bits_backwards _mappingpatterns_19_ in - let aq := bool_bits_backwards _mappingpatterns_18_ in - let op := encdec_amoop_backwards _mappingpatterns_17_ in - true - else if ((andb - (let _mappingpatterns_22_ := subrange_vec_dec v__396 13 12 in - let _mappingpatterns_21_ := subrange_vec_dec v__396 14 14 in - andb (encdec_csrop_backwards_matches _mappingpatterns_22_) - (if ((encdec_csrop_backwards_matches _mappingpatterns_22_)) then - let op := encdec_csrop_backwards _mappingpatterns_22_ in - andb (bool_bits_backwards_matches _mappingpatterns_21_) - (if ((bool_bits_backwards_matches _mappingpatterns_21_)) then - let is_imm := bool_bits_backwards _mappingpatterns_21_ in - true - else false) - else false)) - (eq_vec (subrange_vec_dec v__396 6 0) (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7)))) - then - let _mappingpatterns_22_ := subrange_vec_dec v__396 13 12 in - let _mappingpatterns_21_ := subrange_vec_dec v__396 14 14 in - let op := encdec_csrop_backwards _mappingpatterns_22_ in - let is_imm := bool_bits_backwards _mappingpatterns_21_ in - true - else if ((eq_vec v__396 - (vec_of_bits [B1;B1;B1;B1;B1;B0;B1;B0;B1;B1;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] - : mword 32))) then - true - else if ((eq_vec v__396 - (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] - : mword 32))) then - true - else true. - -Definition print_insn (merge_var : ast) -: M (string) := - match merge_var with - | NOP (tt) => returnm ("nop" : string) - | C_ADDI4SPN (rdc,nzimm) => - returnm ((String.append "c.addi4spn " - (String.append ((reg_name_abi (creg2reg_bits rdc)) : string) - (String.append ", " (string_of_bits nzimm)))) - : string) - | C_LW (uimm,rsc,rdc) => - returnm ((String.append "c.lw " - (String.append ((reg_name_abi (creg2reg_bits rdc)) : string) - (String.append ", " - (String.append ((reg_name_abi (creg2reg_bits rsc)) : string) - (String.append ", " (string_of_bits uimm)))))) - : string) - | C_LD (uimm,rsc,rdc) => - returnm ((String.append "c.ld " - (String.append ((reg_name_abi (creg2reg_bits rdc)) : string) - (String.append ", " - (String.append ((reg_name_abi (creg2reg_bits rsc)) : string) - (String.append ", " (string_of_bits uimm)))))) - : string) - | C_SW (uimm,rsc1,rsc2) => - returnm ((String.append "c.sw " - (String.append ((reg_name_abi (creg2reg_bits rsc1)) : string) - (String.append ", " - (String.append ((reg_name_abi (creg2reg_bits rsc2)) : string) - (String.append ", " (string_of_bits uimm)))))) - : string) - | C_SD (uimm,rsc1,rsc2) => - returnm ((String.append "c.sd " - (String.append ((reg_name_abi (creg2reg_bits rsc1)) : string) - (String.append ", " - (String.append ((reg_name_abi (creg2reg_bits rsc2)) : string) - (String.append ", " (string_of_bits uimm)))))) - : string) - | C_ADDI (nzi,rsd) => - returnm ((String.append "c.addi " - (String.append ((reg_name_abi rsd) : string) - (String.append ", " (string_of_bits nzi)))) - : string) - | C_JAL (imm) => returnm ((String.append "c.jal " (string_of_bits imm)) : string) - | C_ADDIW (imm,rsd) => - returnm ((String.append "c.addiw " - (String.append ((reg_name_abi rsd) : string) - (String.append ", " (string_of_bits imm)))) - : string) - | C_LI (imm,rd) => - returnm ((String.append "c.li " - (String.append ((reg_name_abi rd) : string) - (String.append ", " (string_of_bits imm)))) - : string) - | C_ADDI16SP (imm) => returnm ((String.append "c.addi16sp " (string_of_bits imm)) : string) - | C_LUI (imm,rd) => - returnm ((String.append "c.lui " - (String.append ((reg_name_abi rd) : string) - (String.append ", " (string_of_bits imm)))) - : string) - | C_SRLI (shamt,rsd) => - returnm ((String.append "c.srli " - (String.append ((reg_name_abi (creg2reg_bits rsd)) : string) - (String.append ", " (string_of_bits shamt)))) - : string) - | C_SRAI (shamt,rsd) => - returnm ((String.append "c.srai " - (String.append ((reg_name_abi (creg2reg_bits rsd)) : string) - (String.append ", " (string_of_bits shamt)))) - : string) - | C_ANDI (imm,rsd) => - returnm ((String.append "c.andi " - (String.append ((reg_name_abi (creg2reg_bits rsd)) : string) - (String.append ", " (string_of_bits imm)))) - : string) - | C_SUB (rsd,rs2) => - returnm ((String.append "c.sub " - (String.append ((reg_name_abi (creg2reg_bits rsd)) : string) - (String.append ", " ((reg_name_abi (creg2reg_bits rs2)) : string)))) - : string) - | C_XOR (rsd,rs2) => - returnm ((String.append "c.xor " - (String.append ((reg_name_abi (creg2reg_bits rsd)) : string) - (String.append ", " ((reg_name_abi (creg2reg_bits rs2)) : string)))) - : string) - | C_OR (rsd,rs2) => - returnm ((String.append "c.or " - (String.append ((reg_name_abi (creg2reg_bits rsd)) : string) - (String.append ", " ((reg_name_abi (creg2reg_bits rs2)) : string)))) - : string) - | C_AND (rsd,rs2) => - returnm ((String.append "c.and " - (String.append ((reg_name_abi (creg2reg_bits rsd)) : string) - (String.append ", " ((reg_name_abi (creg2reg_bits rs2)) : string)))) - : string) - | C_SUBW (rsd,rs2) => - returnm ((String.append "c.subw " - (String.append ((reg_name_abi (creg2reg_bits rsd)) : string) - (String.append ", " ((reg_name_abi (creg2reg_bits rs2)) : string)))) - : string) - | C_ADDW (rsd,rs2) => - returnm ((String.append "c.addw " - (String.append ((reg_name_abi (creg2reg_bits rsd)) : string) - (String.append ", " ((reg_name_abi (creg2reg_bits rs2)) : string)))) - : string) - | C_J (imm) => returnm ((String.append "c.j " (string_of_bits imm)) : string) - | C_BEQZ (imm,rs) => - returnm ((String.append "c.beqz " - (String.append ((reg_name_abi (creg2reg_bits rs)) : string) - (String.append ", " (string_of_bits imm)))) - : string) - | C_BNEZ (imm,rs) => - returnm ((String.append "c.bnez " - (String.append ((reg_name_abi (creg2reg_bits rs)) : string) - (String.append ", " (string_of_bits imm)))) - : string) - | C_SLLI (shamt,rsd) => - returnm ((String.append "c.slli " - (String.append ((reg_name_abi rsd) : string) - (String.append ", " (string_of_bits shamt)))) - : string) - | C_LWSP (uimm,rd) => - returnm ((String.append "c.lwsp " - (String.append ((reg_name_abi rd) : string) - (String.append ", " (string_of_bits uimm)))) - : string) - | C_LDSP (uimm,rd) => - returnm ((String.append "c.ldsp " - (String.append ((reg_name_abi rd) : string) - (String.append ", " (string_of_bits uimm)))) - : string) - | C_SWSP (uimm,rd) => - returnm ((String.append "c.swsp " - (String.append ((reg_name_abi rd) : string) - (String.append ", " (string_of_bits uimm)))) - : string) - | C_SDSP (uimm,rd) => - returnm ((String.append "c.sdsp " - (String.append ((reg_name_abi rd) : string) - (String.append ", " (string_of_bits uimm)))) - : string) - | C_JR (rs1) => returnm ((String.append "c.jr " ((reg_name_abi rs1) : string)) : string) - | C_JALR (rs1) => returnm ((String.append "c.jalr " ((reg_name_abi rs1) : string)) : string) - | C_MV (rd,rs2) => - returnm ((String.append "c.mv " - (String.append ((reg_name_abi rd) : string) - (String.append ", " ((reg_name_abi rs2) : string)))) - : string) - | C_ADD (rsd,rs2) => - returnm ((String.append "c.add " - (String.append ((reg_name_abi rsd) : string) - (String.append ", " ((reg_name_abi rs2) : string)))) - : string) - | STOP_FETCHING (tt) => returnm ("stop_fetching" : string) - | THREAD_START (tt) => returnm ("thread_start" : string) - | ILLEGAL (s) => returnm ((String.append "illegal " (string_of_bits s)) : string) - | C_ILLEGAL (tt) => returnm ("c.illegal" : string) - | insn => (assembly_forwards insn) : M (string) - end. - -Definition decode (bv : mword 32) : option ast := Some (encdec_backwards bv). - -Definition isRVC (h : mword 16) -: bool := - negb (eq_vec (subrange_vec_dec h 1 0) (vec_of_bits [B1;B1] : mword 2)). - -Definition fetch '(tt : unit) -: M (FetchResult) := - or_boolM - ((read_reg PC_ref : M (mword 64)) >>= fun w__0 : xlenbits => - cast_unit_vec (access_vec_dec w__0 0) >>= fun w__1 : mword 1 => - returnm ((neq_vec (w__1 : mword 1) (vec_of_bits [B0] : mword 1)) - : bool)) - ((and_boolM - ((read_reg PC_ref : M (mword 64)) >>= fun w__2 : xlenbits => - cast_unit_vec (access_vec_dec w__2 1) >>= fun w__3 : mword 1 => - returnm ((neq_vec (w__3 : mword 1) (vec_of_bits [B0] : mword 1)) - : bool)) (haveRVC tt >>= fun w__4 : bool => returnm ((negb w__4) : bool))) - : M (bool)) >>= fun w__6 : bool => - (if (w__6) then - (read_reg PC_ref : M (mword 64)) >>= fun w__7 : xlenbits => - returnm ((F_Error - (E_Fetch_Addr_Align, w__7)) - : FetchResult ) - else - (read_reg PC_ref : M (mword 64)) >>= fun w__8 : xlenbits => - translateAddr w__8 Execute Instruction >>= fun w__9 : TR_Result => - (match w__9 with - | TR_Failure (e) => - (read_reg PC_ref : M (mword 64)) >>= fun w__10 : xlenbits => - returnm ((F_Error - (e, w__10)) - : FetchResult ) - | TR_Address (ppclo) => - checked_mem_read Instruction ppclo 2 >>= fun w__11 : MemoryOpResult (mword (8 * 2)) => - (match w__11 with - | MemException (e) => - (read_reg PC_ref : M (mword 64)) >>= fun w__12 : xlenbits => - returnm ((F_Error - (E_Fetch_Access_Fault, w__12)) - : FetchResult ) - | MemValue (ilo) => - (if ((isRVC ilo)) then returnm ((F_RVC (ilo)) : FetchResult ) - else - (read_reg PC_ref : M (mword 64)) >>= fun w__13 : xlenbits => - let PChi : xlenbits := add_vec_int w__13 2 in - translateAddr PChi Execute Instruction >>= fun w__14 : TR_Result => - (match w__14 with - | TR_Failure (e) => returnm ((F_Error (e, PChi)) : FetchResult ) - | TR_Address (ppchi) => - checked_mem_read Instruction ppchi 2 >>= fun w__15 : MemoryOpResult (mword (8 * 2)) => - returnm ((match w__15 with - | MemException (e) => F_Error (E_Fetch_Access_Fault, PChi) - | MemValue (ihi) => F_Base (concat_vec ihi ilo) - end) - : FetchResult) - end) - : M (FetchResult)) - : M (FetchResult) - end) - : M (FetchResult) - end) - : M (FetchResult)) - : M (FetchResult). - -Definition step (step_no : Z) -: M ((bool * bool)) := - read_reg cur_privilege_ref >>= fun w__0 : Privilege => - read_reg mip_ref >>= fun w__1 : Minterrupts => - read_reg mie_ref >>= fun w__2 : Minterrupts => - read_reg mideleg_ref >>= fun w__3 : Minterrupts => - curInterrupt w__0 w__1 w__2 w__3 >>= fun w__4 : option ((InterruptType * Privilege)) => - (match w__4 with - | Some (intr,priv) => - let '_ := - (print_bits "Handling interrupt: " ((interruptType_to_bits intr) : mword 4)) - : unit in - handle_interrupt intr priv >> returnm (false, false) - | None => - fetch tt >>= fun w__5 : FetchResult => - (match w__5 with - | F_Error (e,addr) => handle_mem_exception addr e >> returnm (false, false) - | F_RVC (h) => - (match (decodeCompressed h) with - | None => - read_reg cur_privilege_ref >>= fun w__6 : Privilege => - (read_reg PC_ref : M (mword 64)) >>= fun w__7 : xlenbits => - let '_ := - (print_endline - (String.append "[" - (String.append (string_of_int step_no) - (String.append "] [" - (String.append ((privLevel_to_str w__6) : string) - (String.append "]: " - (String.append (string_of_bits w__7) - (String.append " (" - (String.append (string_of_bits h) ") "))))))))) - : unit in - handle_decode_exception (EXTZ 64 h) >> returnm (false, true) - | Some (ast) => - read_reg cur_privilege_ref >>= fun w__8 : Privilege => - (read_reg PC_ref : M (mword 64)) >>= fun w__9 : xlenbits => - print_insn ast >>= fun w__10 : string => - let '_ := - (print_endline - (String.append "[" - (String.append (string_of_int step_no) - (String.append "] [" - (String.append ((privLevel_to_str w__8) : string) - (String.append "]: " - (String.append (string_of_bits w__9) - (String.append " (" - (String.append (string_of_bits h) - (String.append ") " (w__10 : string))))))))))) - : unit in - (read_reg PC_ref : M (mword 64)) >>= fun w__11 : xlenbits => - write_reg nextPC_ref (add_vec_int w__11 2) >> - execute ast >>= fun w__12 : bool => returnm (w__12, true) - end) - : M ((bool * bool)) - | F_Base (w) => - (match (decode w) with - | None => - read_reg cur_privilege_ref >>= fun w__14 : Privilege => - (read_reg PC_ref : M (mword 64)) >>= fun w__15 : xlenbits => - let '_ := - (print_endline - (String.append "[" - (String.append (string_of_int step_no) - (String.append "] [" - (String.append ((privLevel_to_str w__14) : string) - (String.append "]: " - (String.append (string_of_bits w__15) - (String.append " (" - (String.append (string_of_bits w) ") "))))))))) - : unit in - handle_decode_exception (EXTZ 64 w) >> returnm (false, true) - | Some (ast) => - read_reg cur_privilege_ref >>= fun w__16 : Privilege => - (read_reg PC_ref : M (mword 64)) >>= fun w__17 : xlenbits => - print_insn ast >>= fun w__18 : string => - let '_ := - (print_endline - (String.append "[" - (String.append (string_of_int step_no) - (String.append "] [" - (String.append ((privLevel_to_str w__16) : string) - (String.append "]: " - (String.append (string_of_bits w__17) - (String.append " (" - (String.append (string_of_bits w) - (String.append ") " (w__18 : string))))))))))) - : unit in - (read_reg PC_ref : M (mword 64)) >>= fun w__19 : xlenbits => - write_reg nextPC_ref (add_vec_int w__19 4) >> - execute ast >>= fun w__20 : bool => returnm (w__20, true) - end) - : M ((bool * bool)) - end) - : M ((bool * bool)) - end) - : M ((bool * bool)). -(* -Definition loop '(tt : unit) -: M (unit) := - let insns_per_tick := plat_insns_per_tick tt in - let i : Z := 0 in - let step_no : Z := 0 in - (whileM (i, step_no) - (fun varstup => let '(i, step_no) := varstup in - read_reg htif_done_ref >>= fun w__0 : bool => returnm ((negb w__0) : bool)) - (fun varstup => let '(i, step_no) := varstup in - write_reg minstret_written_ref false >> - step step_no >>= fun '(retired, stepped) => - (read_reg nextPC_ref : M (mword 64)) >>= fun w__1 : xlenbits => - write_reg PC_ref w__1 >> - (if (retired) then (retire_instruction tt) : M (unit) - else returnm (tt : unit)) >> - let step_no : Z := - if (stepped) then - projT1 (add_range - (build_ex (projT1 ((build_ex (projT1 (ex_int step_no))) - : {n : Z & ArithFact (True)}))) (build_ex 1)) - else step_no in - read_reg htif_done_ref >>= fun w__2 : bool => - (if (w__2) then - (read_reg htif_exit_code_ref : M (mword 64)) >>= fun w__3 : xlenbits => - let 'exit_val := projT1 (uint w__3) in - returnm (let '_ := - (if sumbool_of_bool ((Z.eqb exit_val 0)) then print_endline "SUCCESS" - else print_int "FAILURE: " exit_val) - : unit in - i) - else - let i := - projT1 ((build_ex (projT1 (add_range - (build_ex (projT1 ((build_ex (projT1 (ex_int i))) - : {n : Z & ArithFact (True)}))) (build_ex 1)))) - : {arg0_ex46277_n : Z & {rangevar : Z & ArithFact ((arg0_ex46277_n + 1) <= rangevar /\ - rangevar <= (arg0_ex46277_n + 1))}}) in - (if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (ex_int projT1i))) - : {n : Z & ArithFact (True)})) insns_per_tick)) then - tick_clock tt >> tick_platform tt >> returnm 0 - else returnm projT1i) - : M (Z)) >>= fun i : Z => - returnm (i, step_no))) >>= fun '(i, step_no) => - returnm (tt - : unit). -*) -Definition read_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 11)} -: read_kind := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then Read_plain - else if sumbool_of_bool ((Z.eqb p0_ 1)) then Read_reserve - else if sumbool_of_bool ((Z.eqb p0_ 2)) then Read_acquire - else if sumbool_of_bool ((Z.eqb p0_ 3)) then Read_exclusive - else if sumbool_of_bool ((Z.eqb p0_ 4)) then Read_exclusive_acquire - else if sumbool_of_bool ((Z.eqb p0_ 5)) then Read_stream - else if sumbool_of_bool ((Z.eqb p0_ 6)) then Read_RISCV_acquire - else if sumbool_of_bool ((Z.eqb p0_ 7)) then Read_RISCV_strong_acquire - else if sumbool_of_bool ((Z.eqb p0_ 8)) then Read_RISCV_reserved - else if sumbool_of_bool ((Z.eqb p0_ 9)) then Read_RISCV_reserved_acquire - else if sumbool_of_bool ((Z.eqb p0_ 10)) then Read_RISCV_reserved_strong_acquire - else Read_X86_locked. - -Definition num_of_read_kind (arg_ : read_kind) -: {e : Z & ArithFact (0 <= e /\ e <= 11)} := - build_ex(match arg_ with - | Read_plain => 0 - | Read_reserve => 1 - | Read_acquire => 2 - | Read_exclusive => 3 - | Read_exclusive_acquire => 4 - | Read_stream => 5 - | Read_RISCV_acquire => 6 - | Read_RISCV_strong_acquire => 7 - | Read_RISCV_reserved => 8 - | Read_RISCV_reserved_acquire => 9 - | Read_RISCV_reserved_strong_acquire => 10 - | Read_X86_locked => 11 - end). - -Definition write_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 10)} -: write_kind := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then Write_plain - else if sumbool_of_bool ((Z.eqb p0_ 1)) then Write_conditional - else if sumbool_of_bool ((Z.eqb p0_ 2)) then Write_release - else if sumbool_of_bool ((Z.eqb p0_ 3)) then Write_exclusive - else if sumbool_of_bool ((Z.eqb p0_ 4)) then Write_exclusive_release - else if sumbool_of_bool ((Z.eqb p0_ 5)) then Write_RISCV_release - else if sumbool_of_bool ((Z.eqb p0_ 6)) then Write_RISCV_strong_release - else if sumbool_of_bool ((Z.eqb p0_ 7)) then Write_RISCV_conditional - else if sumbool_of_bool ((Z.eqb p0_ 8)) then Write_RISCV_conditional_release - else if sumbool_of_bool ((Z.eqb p0_ 9)) then Write_RISCV_conditional_strong_release - else Write_X86_locked. - -Definition num_of_write_kind (arg_ : write_kind) -: {e : Z & ArithFact (0 <= e /\ e <= 10)} := - build_ex(match arg_ with - | Write_plain => 0 - | Write_conditional => 1 - | Write_release => 2 - | Write_exclusive => 3 - | Write_exclusive_release => 4 - | Write_RISCV_release => 5 - | Write_RISCV_strong_release => 6 - | Write_RISCV_conditional => 7 - | Write_RISCV_conditional_release => 8 - | Write_RISCV_conditional_strong_release => 9 - | Write_X86_locked => 10 - end). - -Definition barrier_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 22)} -: barrier_kind := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then Barrier_Sync - else if sumbool_of_bool ((Z.eqb p0_ 1)) then Barrier_LwSync - else if sumbool_of_bool ((Z.eqb p0_ 2)) then Barrier_Eieio - else if sumbool_of_bool ((Z.eqb p0_ 3)) then Barrier_Isync - else if sumbool_of_bool ((Z.eqb p0_ 4)) then Barrier_DMB - else if sumbool_of_bool ((Z.eqb p0_ 5)) then Barrier_DMB_ST - else if sumbool_of_bool ((Z.eqb p0_ 6)) then Barrier_DMB_LD - else if sumbool_of_bool ((Z.eqb p0_ 7)) then Barrier_DSB - else if sumbool_of_bool ((Z.eqb p0_ 8)) then Barrier_DSB_ST - else if sumbool_of_bool ((Z.eqb p0_ 9)) then Barrier_DSB_LD - else if sumbool_of_bool ((Z.eqb p0_ 10)) then Barrier_ISB - else if sumbool_of_bool ((Z.eqb p0_ 11)) then Barrier_MIPS_SYNC - else if sumbool_of_bool ((Z.eqb p0_ 12)) then Barrier_RISCV_rw_rw - else if sumbool_of_bool ((Z.eqb p0_ 13)) then Barrier_RISCV_r_rw - else if sumbool_of_bool ((Z.eqb p0_ 14)) then Barrier_RISCV_r_r - else if sumbool_of_bool ((Z.eqb p0_ 15)) then Barrier_RISCV_rw_w - else if sumbool_of_bool ((Z.eqb p0_ 16)) then Barrier_RISCV_w_w - else if sumbool_of_bool ((Z.eqb p0_ 17)) then Barrier_RISCV_w_rw - else if sumbool_of_bool ((Z.eqb p0_ 18)) then Barrier_RISCV_rw_r - else if sumbool_of_bool ((Z.eqb p0_ 19)) then Barrier_RISCV_r_w - else if sumbool_of_bool ((Z.eqb p0_ 20)) then Barrier_RISCV_w_r - else if sumbool_of_bool ((Z.eqb p0_ 21)) then Barrier_RISCV_i - else Barrier_x86_MFENCE. - -Definition num_of_barrier_kind (arg_ : barrier_kind) -: {e : Z & ArithFact (0 <= e /\ e <= 22)} := - build_ex(match arg_ with - | Barrier_Sync => 0 - | Barrier_LwSync => 1 - | Barrier_Eieio => 2 - | Barrier_Isync => 3 - | Barrier_DMB => 4 - | Barrier_DMB_ST => 5 - | Barrier_DMB_LD => 6 - | Barrier_DSB => 7 - | Barrier_DSB_ST => 8 - | Barrier_DSB_LD => 9 - | Barrier_ISB => 10 - | Barrier_MIPS_SYNC => 11 - | Barrier_RISCV_rw_rw => 12 - | Barrier_RISCV_r_rw => 13 - | Barrier_RISCV_r_r => 14 - | Barrier_RISCV_rw_w => 15 - | Barrier_RISCV_w_w => 16 - | Barrier_RISCV_w_rw => 17 - | Barrier_RISCV_rw_r => 18 - | Barrier_RISCV_r_w => 19 - | Barrier_RISCV_w_r => 20 - | Barrier_RISCV_i => 21 - | Barrier_x86_MFENCE => 22 - end). - -Definition trans_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} -: trans_kind := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then Transaction_start - else if sumbool_of_bool ((Z.eqb p0_ 1)) then Transaction_commit - else Transaction_abort. - -Definition num_of_trans_kind (arg_ : trans_kind) -: {e : Z & ArithFact (0 <= e /\ e <= 2)} := - build_ex(match arg_ with - | Transaction_start => 0 - | Transaction_commit => 1 - | Transaction_abort => 2 - end). - -Definition GPRstr : vec string 32 := -vec_of_list_len ["x31";"x30";"x29";"x28";"x27";"x26";"x25";"x24";"x23";"x22";"x21";"x20";"x19";"x18";"x17";"x16";"x15";"x14";"x13";"x12";"x11"; - "x10";"x9";"x8";"x7";"x6";"x5";"x4";"x3";"x2";"x1";"x0"]. -Hint Unfold GPRstr : sail. -Definition CIA_fp := RFull ("CIA"). -Hint Unfold CIA_fp : sail. -Definition NIA_fp := RFull ("NIA"). -Hint Unfold NIA_fp : sail. -Definition initial_analysis (instr : ast) -: M ((list regfp * list regfp * list regfp * list niafp * diafp * instruction_kind)) := - let iR := [] : regfps in - let oR := [] : regfps in - let aR := [] : regfps in - let ik := (IK_simple (tt)) : instruction_kind in - let Nias := [NIAFP_successor (tt)] : niafps in - let Dia := (DIAFP_none (tt)) : diafp in - match instr with - | EBREAK (tt) => returnm (Nias, aR, iR, ik, oR) - | UTYPE (imm,rd,op) => - let oR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - oR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - oR in - returnm (Nias, aR, iR, ik, oR) - | RISCV_JAL (imm,rd) => - let oR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - oR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - oR in - let offset : bits 64 := EXTS 64 imm in - (read_reg PC_ref : M (mword 64)) >>= fun w__0 : xlenbits => - let Nias : niafps := [NIAFP_concrete_address (add_vec w__0 offset)] in - let ik : instruction_kind := IK_branch (tt) in - returnm (Nias, aR, iR, ik, oR) - | RISCV_JALR (imm,rs,rd) => - let iR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - iR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - iR in - let oR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - oR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - oR in - let offset : bits 64 := EXTS 64 imm in - let Nias : niafps := [NIAFP_indirect_address (tt)] in - let ik : instruction_kind := IK_branch (tt) in - returnm (Nias, aR, iR, ik, oR) - | BTYPE (imm,rs2,rs1,op) => - let iR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - iR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - iR in - let iR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - iR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - iR in - let ik := (IK_branch (tt)) : instruction_kind in - let offset : bits 64 := EXTS 64 imm in - (read_reg PC_ref : M (mword 64)) >>= fun w__1 : xlenbits => - let Nias : niafps := [NIAFP_concrete_address (add_vec w__1 offset);NIAFP_successor (tt)] in - returnm (Nias, aR, iR, ik, oR) - | ITYPE (imm,rs,rd,op) => - let iR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - iR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - iR in - let oR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - oR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - oR in - returnm (Nias, aR, iR, ik, oR) - | SHIFTIOP (imm,rs,rd,op) => - let iR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - iR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - iR in - let oR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - oR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - oR in - returnm (Nias, aR, iR, ik, oR) - | RTYPE (rs2,rs1,rd,op) => - let iR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - iR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - iR in - let iR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - iR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - iR in - let oR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - oR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - oR in - returnm (Nias, aR, iR, ik, oR) - | CSR (csr,rs1,rd,is_imm,op) => - let isWrite : bool := - match op with - | CSRRW => true - | _ => - if (is_imm) then neq_range (build_ex (projT1 (uint rs1))) (build_ex 0) - else neq_range (build_ex (projT1 (uint rs1))) (build_ex 0) - end in - let iR : regfps := (RFull (csr_name csr)) :: iR in - let iR : regfps := - if ((negb is_imm)) then - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - iR - else iR in - let oR : regfps := if (isWrite) then (RFull (csr_name csr)) :: oR else oR in - let oR : regfps := - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - oR in - returnm (Nias, aR, iR, ik, oR) - | LOAD (imm,rs,rd,unsign,width,aq,rl) => - let iR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - iR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - iR in - let oR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - oR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - oR in - let aR := iR : regfps in - match (aq, rl) with - | (false, false) => returnm ((IK_mem_read (Read_plain)) : instruction_kind ) - | (true, false) => returnm ((IK_mem_read (Read_RISCV_acquire)) : instruction_kind ) - | (true, true) => returnm ((IK_mem_read (Read_RISCV_strong_acquire)) : instruction_kind ) - | _ => - (internal_error "LOAD type not implemented in initial_analysis") : M (instruction_kind) - end >>= fun w__3 : instruction_kind => - let ik : instruction_kind := w__3 in - returnm (Nias, aR, iR, ik, oR) - | STORE (imm,rs2,rs1,width,aq,rl) => - let iR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - iR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - iR in - let iR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - iR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - iR in - let aR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - aR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - aR in - match (aq, rl) with - | (false, false) => returnm ((IK_mem_write (Write_plain)) : instruction_kind ) - | (false, true) => returnm ((IK_mem_write (Write_RISCV_release)) : instruction_kind ) - | (true, true) => returnm ((IK_mem_write (Write_RISCV_strong_release)) : instruction_kind ) - | _ => - (internal_error "STORE type not implemented in initial_analysis") : M (instruction_kind) - end >>= fun w__5 : instruction_kind => - let ik : instruction_kind := w__5 in - returnm (Nias, aR, iR, ik, oR) - | ADDIW (imm,rs,rd) => - let iR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - iR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - iR in - let oR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - oR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - oR in - returnm (Nias, aR, iR, ik, oR) - | SHIFTW (imm,rs,rd,op) => - let iR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - iR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - iR in - let oR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - oR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - oR in - returnm (Nias, aR, iR, ik, oR) - | RTYPEW (rs2,rs1,rd,op) => - let iR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - iR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - iR in - let iR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - iR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - iR in - let oR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - oR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - oR in - returnm (Nias, aR, iR, ik, oR) - | FENCE (pred,succ) => - match (pred, succ) with - | (v__610, v__611) => - (if ((andb (eq_vec (subrange_vec_dec v__610 1 0) (vec_of_bits [B1;B1] : mword 2)) - (eq_vec (subrange_vec_dec v__611 1 0) (vec_of_bits [B1;B1] : mword 2)))) then - returnm ((IK_barrier - (Barrier_RISCV_rw_rw)) - : instruction_kind ) - else if ((andb (eq_vec (subrange_vec_dec v__610 1 0) (vec_of_bits [B1;B0] : mword 2)) - (eq_vec (subrange_vec_dec v__611 1 0) (vec_of_bits [B1;B1] : mword 2)))) then - returnm ((IK_barrier - (Barrier_RISCV_r_rw)) - : instruction_kind ) - else if ((andb (eq_vec (subrange_vec_dec v__610 1 0) (vec_of_bits [B1;B0] : mword 2)) - (eq_vec (subrange_vec_dec v__611 1 0) (vec_of_bits [B1;B0] : mword 2)))) then - returnm ((IK_barrier - (Barrier_RISCV_r_r)) - : instruction_kind ) - else if ((andb (eq_vec (subrange_vec_dec v__610 1 0) (vec_of_bits [B1;B1] : mword 2)) - (eq_vec (subrange_vec_dec v__611 1 0) (vec_of_bits [B0;B1] : mword 2)))) then - returnm ((IK_barrier - (Barrier_RISCV_rw_w)) - : instruction_kind ) - else if ((andb (eq_vec (subrange_vec_dec v__610 1 0) (vec_of_bits [B0;B1] : mword 2)) - (eq_vec (subrange_vec_dec v__611 1 0) (vec_of_bits [B0;B1] : mword 2)))) then - returnm ((IK_barrier - (Barrier_RISCV_w_w)) - : instruction_kind ) - else if ((andb (eq_vec (subrange_vec_dec v__610 1 0) (vec_of_bits [B0;B1] : mword 2)) - (eq_vec (subrange_vec_dec v__611 1 0) (vec_of_bits [B1;B1] : mword 2)))) then - returnm ((IK_barrier - (Barrier_RISCV_w_rw)) - : instruction_kind ) - else if ((andb (eq_vec (subrange_vec_dec v__610 1 0) (vec_of_bits [B1;B1] : mword 2)) - (eq_vec (subrange_vec_dec v__611 1 0) (vec_of_bits [B1;B0] : mword 2)))) then - returnm ((IK_barrier - (Barrier_RISCV_rw_r)) - : instruction_kind ) - else if ((andb (eq_vec (subrange_vec_dec v__610 1 0) (vec_of_bits [B1;B0] : mword 2)) - (eq_vec (subrange_vec_dec v__611 1 0) (vec_of_bits [B0;B1] : mword 2)))) then - returnm ((IK_barrier - (Barrier_RISCV_r_w)) - : instruction_kind ) - else if ((andb (eq_vec (subrange_vec_dec v__610 1 0) (vec_of_bits [B0;B1] : mword 2)) - (eq_vec (subrange_vec_dec v__611 1 0) (vec_of_bits [B1;B0] : mword 2)))) then - returnm ((IK_barrier - (Barrier_RISCV_w_r)) - : instruction_kind ) - else if ((andb (eq_vec (subrange_vec_dec v__610 1 0) (vec_of_bits [B0;B0] : mword 2)) - (eq_vec (subrange_vec_dec v__611 1 0) (vec_of_bits [B0;B0] : mword 2)))) then - returnm ((IK_simple - (tt)) - : instruction_kind ) - else - (internal_error "barrier type not implemented in initial_analysis") - : M (instruction_kind)) - : M (instruction_kind) - end >>= fun w__17 : instruction_kind => - let ik : instruction_kind := w__17 in - returnm (Nias, aR, iR, ik, oR) - | FENCEI (tt) => - let ik : instruction_kind := IK_simple (tt) in - returnm (Nias, aR, iR, ik, oR) - | LOADRES (aq,rl,rs1,width,rd) => - let iR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - iR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - iR in - let oR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - oR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - oR in - let aR := iR : regfps in - match (aq, rl) with - | (false, false) => returnm ((IK_mem_read (Read_RISCV_reserved)) : instruction_kind ) - | (true, false) => returnm ((IK_mem_read (Read_RISCV_reserved_acquire)) : instruction_kind ) - | (true, true) => - returnm ((IK_mem_read (Read_RISCV_reserved_strong_acquire)) : instruction_kind ) - | (false, true) => - (internal_error "LOADRES type not implemented in initial_analysis") : M (instruction_kind) - end >>= fun w__19 : instruction_kind => - let ik : instruction_kind := w__19 in - returnm (Nias, aR, iR, ik, oR) - | STORECON (aq,rl,rs2,rs1,width,rd) => - let iR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - iR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - iR in - let iR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - iR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - iR in - let aR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - aR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - aR in - let oR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - oR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - oR in - match (aq, rl) with - | (false, false) => returnm ((IK_mem_write (Write_RISCV_conditional)) : instruction_kind ) - | (false, true) => - returnm ((IK_mem_write (Write_RISCV_conditional_release)) : instruction_kind ) - | (true, true) => - returnm ((IK_mem_write (Write_RISCV_conditional_strong_release)) : instruction_kind ) - | (true, false) => - (internal_error "STORECON type not implemented in initial_analysis") - : M (instruction_kind) - end >>= fun w__21 : instruction_kind => - let ik : instruction_kind := w__21 in - returnm (Nias, aR, iR, ik, oR) - | AMO (op,aq,rl,rs2,rs1,width,rd) => - let iR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - iR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs2))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - iR in - let iR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - iR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - iR in - let aR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - aR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rs1))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - aR in - let oR : regfps := - if sumbool_of_bool ((Z.eqb - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})) 0)) then - oR - else - (RFull - (vec_access_dec GPRstr - (projT1 ((build_ex (projT1 (regbits_to_regno rd))) - : {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)})))) :: - oR in - let ik : instruction_kind := - match (aq, rl) with - | (false, false) => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional) - | (false, true) => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional_release) - | (true, false) => IK_mem_rmw (Read_RISCV_reserved_acquire, Write_RISCV_conditional) - | (true, true) => IK_mem_rmw (Read_RISCV_reserved_acquire, Write_RISCV_conditional_release) - end in - returnm (Nias, aR, iR, ik, oR) - | _ => returnm (Nias, aR, iR, ik, oR) - end >>= fun '(Nias, aR, iR, ik, oR) => - returnm (iR, oR, aR, Nias, Dia, ik). - -Definition initial_regstate : regstate := -{| tlb39 := None; - htif_exit_code := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - htif_done := false; - htif_tohost := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - mtimecmp := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - tselect := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - stval := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - scause := - ({| Mcause_Mcause_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - sepc := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - sscratch := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - stvec := - ({| Mtvec_Mtvec_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - satp := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - sideleg := - ({| Sinterrupts_Sinterrupts_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - sedeleg := - ({| Sedeleg_Sedeleg_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - pmpcfg0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - pmpaddr0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - mhartid := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - marchid := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - mimpid := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - mvendorid := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - minstret_written := false; - minstret := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - mtime := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - mcycle := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - scounteren := - ({| Counteren_Counteren_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 32) |}); - mcounteren := - ({| Counteren_Counteren_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 32) |}); - mscratch := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - mtval := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - mepc := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - mcause := - ({| Mcause_Mcause_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - mtvec := - ({| Mtvec_Mtvec_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - medeleg := - ({| Medeleg_Medeleg_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - mideleg := - ({| Minterrupts_Minterrupts_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - mie := - ({| Minterrupts_Minterrupts_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - mip := - ({| Minterrupts_Minterrupts_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - mstatus := - ({| Mstatus_Mstatus_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - misa := - ({| Misa_Misa_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - cur_inst := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - cur_privilege := User; - x31 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x30 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x29 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x28 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x27 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x26 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x25 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x24 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x23 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x22 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x21 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x20 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x19 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x18 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x17 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x16 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x15 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x14 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x13 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x12 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x11 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x10 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x9 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x8 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x7 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x6 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x5 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x4 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x3 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x2 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - x1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - Xs := - (vec_of_list_len [(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64)]); - nextPC := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - PC := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}. -Hint Unfold initial_regstate : sail. - -End Content. diff --git a/snapshots/coq-riscv/sail/riscv/riscv_extras.v b/snapshots/coq-riscv/sail/riscv/riscv_extras.v deleted file mode 100644 index 820e3f3a..00000000 --- a/snapshots/coq-riscv/sail/riscv/riscv_extras.v +++ /dev/null @@ -1,134 +0,0 @@ -Require Import Sail2_instr_kinds. -Require Import Sail2_values. -Require Import Sail2_operators_mwords. -Require Import Sail2_prompt_monad. -Require Import Sail2_prompt. -Require Import String. -Require Import List. -Import List.ListNotations. - -Axiom real : Type. - -Definition MEM_fence_rw_rw {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_rw_rw. -Definition MEM_fence_r_rw {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_r_rw. -Definition MEM_fence_r_r {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_r_r. -Definition MEM_fence_rw_w {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_rw_w. -Definition MEM_fence_w_w {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_w_w. -Definition MEM_fence_w_rw {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_w_rw. -Definition MEM_fence_rw_r {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_rw_r. -Definition MEM_fence_r_w {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_r_w. -Definition MEM_fence_w_r {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_w_r. -Definition MEM_fence_i {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_i. -(* -val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -val MEMea_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -val MEMea_conditional : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -val MEMea_conditional_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e -*) -Definition MEMea {rv a e} (addr : mword a) size : monad rv unit e := write_mem_ea Write_plain addr size. -Definition MEMea_release {rv a e} (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_release addr size. -Definition MEMea_strong_release {rv a e} (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_strong_release addr size. -Definition MEMea_conditional {rv a e} (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_conditional addr size. -Definition MEMea_conditional_release {rv a e} (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_conditional_release addr size. -Definition MEMea_conditional_strong_release {rv a e} (addr : mword a) size : monad rv unit e - := write_mem_ea Write_RISCV_conditional_strong_release addr size. - - -(* Some wrappers copied from aarch64_extras *) -(* TODO: Harmonise into a common library *) -(* -Definition get_slice_int_bl len n lo := - (* TODO: Is this the intended behaviour? *) - let hi := lo + len - 1 in - let bs := bools_of_int (hi + 1) n in - subrange_list false bs hi lo - -val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a -Definition get_slice_int len n lo := of_bools (get_slice_int_bl len n lo) -*) -Definition write_ram {rv e} m size (hexRAM : mword m) (addr : mword m) (data : mword (8 * size)) : monad rv bool e := - write_mem_val data. - -Definition read_ram {rv e} m size `{ArithFact (size >= 0)} (_ : mword m) (addr : mword m) : monad rv (mword (8 * size)) e := - read_mem Read_plain addr size. -(* -Definition string_of_bits bs := string_of_bv (bits_of bs). -Definition string_of_int := show - -Definition _sign_extend bits len := maybe_failwith (of_bits (exts_bv len bits)) -Definition _zero_extend bits len := maybe_failwith (of_bits (extz_bv len bits)) -*) -Definition shift_bits_left {a b} (v : mword a) (n : mword b) : mword a := - shiftl v (int_of_mword false n). - -Definition shift_bits_right {a b} (v : mword a) (n : mword b) : mword a := - shiftr v (int_of_mword false n). - -Definition shift_bits_right_arith {a b} (v : mword a) (n : mword b) : mword a := - arith_shiftr v (int_of_mword false n). - -(* Use constants for undefined values for now *) -Definition internal_pick {rv a e} (vs : list a) : monad rv a e := -match vs with -| (h::_) => returnm h -| _ => Fail "empty list in internal_pick" -end. -Definition undefined_string {rv e} (_:unit) : monad rv string e := returnm ""%string. -Definition undefined_unit {rv e} (_:unit) : monad rv unit e := returnm tt. -Definition undefined_int {rv e} (_:unit) : monad rv Z e := returnm (0:ii). -(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*) -Definition undefined_vector {rv a e} len (u : a) `{ArithFact (len >= 0)} : monad rv (vec a len) e := returnm (vec_init u len). -(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) -Definition undefined_bitvector {rv e} len `{ArithFact (len >= 0)} : monad rv (mword len) e := returnm (mword_of_int 0). -(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) -Definition undefined_bits {rv e} := @undefined_bitvector rv e. -Definition undefined_bit {rv e} (_:unit) : monad rv bitU e := returnm BU. -(*Definition undefined_real {rv e} (_:unit) : monad rv real e := returnm (realFromFrac 0 1).*) -Definition undefined_range {rv e} i j `{ArithFact (i <= j)} : monad rv {z : Z & ArithFact (i <= z /\ z <= j)} e := returnm (build_ex i). -Definition undefined_atom {rv e} i : monad rv Z e := returnm i. -Definition undefined_nat {rv e} (_:unit) : monad rv Z e := returnm (0:ii). - -Definition skip {rv e} (_:unit) : monad rv unit e := returnm tt. - -(*val elf_entry : unit -> integer*) -Definition elf_entry (_:unit) : Z := 0. -(*declare ocaml target_rep function elf_entry := `Elf_loader.elf_entry`*) - -Definition print_bits {n} msg (bs : mword n) := prerr_endline (msg ++ (string_of_bits bs)). - -(*val get_time_ns : unit -> integer*) -Definition get_time_ns (_:unit) : Z := 0. -(*declare ocaml target_rep function get_time_ns := `(fun () -> Big_int.of_int (int_of_float (1e9 *. Unix.gettimeofday ())))`*) - -Definition eq_bit (x : bitU) (y : bitU) : bool := - match x, y with - | B0, B0 => true - | B1, B1 => true - | BU, BU => true - | _,_ => false - end. - -Require Import Zeuclid. -Definition euclid_modulo (m n : Z) `{ArithFact (n > 0)} : {z : Z & ArithFact (0 <= z <= n-1)}. -apply existT with (x := ZEuclid.modulo m n). -constructor. -destruct H. -assert (Z.abs n = n). { rewrite Z.abs_eq; auto with zarith. } -rewrite <- H at 3. -lapply (ZEuclid.mod_always_pos m n); omega. -Qed. - -(* Override the more general version *) - -Definition mults_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mults_vec l r. -Definition mult_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mult_vec l r. - - -Definition print_endline (_:string) : unit := tt. -Definition prerr_endline (_:string) : unit := tt. -Definition prerr_string (_:string) : unit := tt. -Definition putchar {T} (_:T) : unit := tt. -Require DecimalString. -Definition string_of_int z := DecimalString.NilZero.string_of_int (Z.to_int z). diff --git a/snapshots/coq-riscv/sail/riscv/riscv_types.v b/snapshots/coq-riscv/sail/riscv/riscv_types.v deleted file mode 100644 index 6d3817c6..00000000 --- a/snapshots/coq-riscv/sail/riscv/riscv_types.v +++ /dev/null @@ -1,1388 +0,0 @@ -(*Generated by Sail from riscv.*) -Require Import Sail2_instr_kinds. -Require Import Sail2_values. -Require Import Sail2_string. -Require Import Sail2_operators_mwords. -Require Import Sail2_prompt_monad. -Require Import Sail2_prompt. -Require Import Sail2_state. -Definition bits (n : Z) : Type := mword n. - - - -Definition xlenbits : Type := bits 64. - -Definition half : Type := bits 16. - -Definition word : Type := bits 32. - -Definition regbits : Type := bits 5. - -Definition cregbits : Type := bits 3. - -Definition csreg : Type := bits 12. - -Definition regno (n : Z)`{ArithFact (0 <= n /\ (n + 1) <= 32)} : Type := Z. - -Definition opcode : Type := bits 7. - -Definition imm12 : Type := bits 12. - -Definition imm20 : Type := bits 20. - -Definition amo : Type := bits 1. - -Inductive Architecture := RV32 | RV64 | RV128. -Scheme Equality for Architecture. -Instance Decidable_eq_Architecture : forall (x y : Architecture), Decidable (x = y) := -Decidable_eq_from_dec Architecture_eq_dec. - - -Definition arch_xlen : Type := bits 2. - -Definition priv_level : Type := bits 2. - -Inductive Privilege := User | Supervisor | Machine. -Scheme Equality for Privilege. -Instance Decidable_eq_Privilege : forall (x y : Privilege), Decidable (x = y) := -Decidable_eq_from_dec Privilege_eq_dec. - - -Inductive AccessType := Read | Write | ReadWrite | Execute. -Scheme Equality for AccessType. -Instance Decidable_eq_AccessType : forall (x y : AccessType), Decidable (x = y) := -Decidable_eq_from_dec AccessType_eq_dec. - - -Inductive ReadType := Instruction | Data. -Scheme Equality for ReadType. -Instance Decidable_eq_ReadType : forall (x y : ReadType), Decidable (x = y) := -Decidable_eq_from_dec ReadType_eq_dec. - - -Inductive word_width := BYTE | HALF | WORD | DOUBLE. -Scheme Equality for word_width. -Instance Decidable_eq_word_width : forall (x y : word_width), Decidable (x = y) := -Decidable_eq_from_dec word_width_eq_dec. - - -Definition exc_code : Type := bits 4. - -Inductive InterruptType := - I_U_Software - | I_S_Software - | I_M_Software - | I_U_Timer - | I_S_Timer - | I_M_Timer - | I_U_External - | I_S_External - | I_M_External. -Scheme Equality for InterruptType. -Instance Decidable_eq_InterruptType : forall (x y : InterruptType), Decidable (x = y) := -Decidable_eq_from_dec InterruptType_eq_dec. - - -Inductive ExceptionType := - E_Fetch_Addr_Align - | E_Fetch_Access_Fault - | E_Illegal_Instr - | E_Breakpoint - | E_Load_Addr_Align - | E_Load_Access_Fault - | E_SAMO_Addr_Align - | E_SAMO_Access_Fault - | E_U_EnvCall - | E_S_EnvCall - | E_Reserved_10 - | E_M_EnvCall - | E_Fetch_Page_Fault - | E_Load_Page_Fault - | E_Reserved_14 - | E_SAMO_Page_Fault. -Scheme Equality for ExceptionType. -Instance Decidable_eq_ExceptionType : forall (x y : ExceptionType), Decidable (x = y) := -Decidable_eq_from_dec ExceptionType_eq_dec. - - -Inductive exception := - Error_not_implemented : string -> exception | Error_internal_error : unit -> exception. -Arguments exception : clear implicits. - - - -Definition tv_mode : Type := bits 2. - -Inductive TrapVectorMode := TV_Direct | TV_Vector | TV_Reserved. -Scheme Equality for TrapVectorMode. -Instance Decidable_eq_TrapVectorMode : forall (x y : TrapVectorMode), Decidable (x = y) := -Decidable_eq_from_dec TrapVectorMode_eq_dec. - - -Definition ext_status : Type := bits 2. - -Inductive ExtStatus := Off | Initial | Clean | Dirty. -Scheme Equality for ExtStatus. -Instance Decidable_eq_ExtStatus : forall (x y : ExtStatus), Decidable (x = y) := -Decidable_eq_from_dec ExtStatus_eq_dec. - - -Definition satp_mode : Type := bits 4. - -Inductive SATPMode := Sbare | Sv32 | Sv39. -Scheme Equality for SATPMode. -Instance Decidable_eq_SATPMode : forall (x y : SATPMode), Decidable (x = y) := -Decidable_eq_from_dec SATPMode_eq_dec. - - -Definition csrRW : Type := bits 2. - -Inductive uop := RISCV_LUI | RISCV_AUIPC. -Scheme Equality for uop. -Instance Decidable_eq_uop : forall (x y : uop), Decidable (x = y) := -Decidable_eq_from_dec uop_eq_dec. - - -Inductive bop := RISCV_BEQ | RISCV_BNE | RISCV_BLT | RISCV_BGE | RISCV_BLTU | RISCV_BGEU. -Scheme Equality for bop. -Instance Decidable_eq_bop : forall (x y : bop), Decidable (x = y) := -Decidable_eq_from_dec bop_eq_dec. - - -Inductive iop := RISCV_ADDI | RISCV_SLTI | RISCV_SLTIU | RISCV_XORI | RISCV_ORI | RISCV_ANDI. -Scheme Equality for iop. -Instance Decidable_eq_iop : forall (x y : iop), Decidable (x = y) := -Decidable_eq_from_dec iop_eq_dec. - - -Inductive sop := RISCV_SLLI | RISCV_SRLI | RISCV_SRAI. -Scheme Equality for sop. -Instance Decidable_eq_sop : forall (x y : sop), Decidable (x = y) := -Decidable_eq_from_dec sop_eq_dec. - - -Inductive rop := - RISCV_ADD - | RISCV_SUB - | RISCV_SLL - | RISCV_SLT - | RISCV_SLTU - | RISCV_XOR - | RISCV_SRL - | RISCV_SRA - | RISCV_OR - | RISCV_AND. -Scheme Equality for rop. -Instance Decidable_eq_rop : forall (x y : rop), Decidable (x = y) := -Decidable_eq_from_dec rop_eq_dec. - - -Inductive ropw := RISCV_ADDW | RISCV_SUBW | RISCV_SLLW | RISCV_SRLW | RISCV_SRAW. -Scheme Equality for ropw. -Instance Decidable_eq_ropw : forall (x y : ropw), Decidable (x = y) := -Decidable_eq_from_dec ropw_eq_dec. - - -Inductive sopw := RISCV_SLLIW | RISCV_SRLIW | RISCV_SRAIW. -Scheme Equality for sopw. -Instance Decidable_eq_sopw : forall (x y : sopw), Decidable (x = y) := -Decidable_eq_from_dec sopw_eq_dec. - - -Inductive amoop := AMOSWAP | AMOADD | AMOXOR | AMOAND | AMOOR | AMOMIN | AMOMAX | AMOMINU | AMOMAXU. -Scheme Equality for amoop. -Instance Decidable_eq_amoop : forall (x y : amoop), Decidable (x = y) := -Decidable_eq_from_dec amoop_eq_dec. - - -Inductive csrop := CSRRW | CSRRS | CSRRC. -Scheme Equality for csrop. -Instance Decidable_eq_csrop : forall (x y : csrop), Decidable (x = y) := -Decidable_eq_from_dec csrop_eq_dec. - - -Record Misa := { Misa_Misa_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'Misa_Misa_chunk_0' := e ]}" := ({| Misa_Misa_chunk_0 := e |}). - -Record SV39_PTE := { SV39_PTE_SV39_PTE_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'SV39_PTE_SV39_PTE_chunk_0' := e ]}" := ({| SV39_PTE_SV39_PTE_chunk_0 := e |}). - -Record PTE_Bits := { PTE_Bits_PTE_Bits_chunk_0 : mword 8; }. -Notation "{[ r 'with' 'PTE_Bits_PTE_Bits_chunk_0' := e ]}" := ({| PTE_Bits_PTE_Bits_chunk_0 := e |}). - -Record Mstatus := { Mstatus_Mstatus_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'Mstatus_Mstatus_chunk_0' := e ]}" := ({| Mstatus_Mstatus_chunk_0 := e |}). - -Record Sstatus := { Sstatus_Sstatus_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'Sstatus_Sstatus_chunk_0' := e ]}" := ({| Sstatus_Sstatus_chunk_0 := e |}). - -Record Minterrupts := { Minterrupts_Minterrupts_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'Minterrupts_Minterrupts_chunk_0' := e ]}" := ({| Minterrupts_Minterrupts_chunk_0 := e |}). - -Record Sinterrupts := { Sinterrupts_Sinterrupts_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'Sinterrupts_Sinterrupts_chunk_0' := e ]}" := ({| Sinterrupts_Sinterrupts_chunk_0 := e |}). - -Record Medeleg := { Medeleg_Medeleg_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'Medeleg_Medeleg_chunk_0' := e ]}" := ({| Medeleg_Medeleg_chunk_0 := e |}). - -Record Sedeleg := { Sedeleg_Sedeleg_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'Sedeleg_Sedeleg_chunk_0' := e ]}" := ({| Sedeleg_Sedeleg_chunk_0 := e |}). - -Record Mtvec := { Mtvec_Mtvec_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'Mtvec_Mtvec_chunk_0' := e ]}" := ({| Mtvec_Mtvec_chunk_0 := e |}). - -Record Satp64 := { Satp64_Satp64_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'Satp64_Satp64_chunk_0' := e ]}" := ({| Satp64_Satp64_chunk_0 := e |}). - -Record Mcause := { Mcause_Mcause_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'Mcause_Mcause_chunk_0' := e ]}" := ({| Mcause_Mcause_chunk_0 := e |}). - -Record Counteren := { Counteren_Counteren_chunk_0 : mword 32; }. -Notation "{[ r 'with' 'Counteren_Counteren_chunk_0' := e ]}" := ({| Counteren_Counteren_chunk_0 := e |}). - -Record sync_exception := - { sync_exception_trap : ExceptionType; sync_exception_excinfo : option xlenbits; }. -Notation "{[ r 'with' 'sync_exception_trap' := e ]}" := ({| sync_exception_trap := e; sync_exception_excinfo := sync_exception_excinfo r |}). -Notation "{[ r 'with' 'sync_exception_excinfo' := e ]}" := ({| sync_exception_excinfo := e; sync_exception_trap := sync_exception_trap r |}). - -Inductive ctl_result := - CTL_TRAP : sync_exception -> ctl_result - | CTL_SRET : unit -> ctl_result - | CTL_MRET : unit -> ctl_result. -Arguments ctl_result : clear implicits. - - - -Inductive MemoryOpResult {a : Type} := - MemValue : a -> MemoryOpResult | MemException : ExceptionType -> MemoryOpResult. -Arguments MemoryOpResult : clear implicits. - - - -Record htif_cmd := { htif_cmd_htif_cmd_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'htif_cmd_htif_cmd_chunk_0' := e ]}" := ({| htif_cmd_htif_cmd_chunk_0 := e |}). - -Definition pteAttribs : Type := bits 8. - -Inductive PTW_Error := - PTW_Access | PTW_Invalid_PTE | PTW_No_Permission | PTW_Misaligned | PTW_PTE_Update. -Scheme Equality for PTW_Error. -Instance Decidable_eq_PTW_Error : forall (x y : PTW_Error), Decidable (x = y) := -Decidable_eq_from_dec PTW_Error_eq_dec. - - -Definition vaddr39 : Type := bits 39. - -Definition paddr39 : Type := bits 56. - -Definition pte39 : Type := xlenbits. - -Record SV39_Vaddr := { SV39_Vaddr_SV39_Vaddr_chunk_0 : mword 39; }. -Notation "{[ r 'with' 'SV39_Vaddr_SV39_Vaddr_chunk_0' := e ]}" := ({| SV39_Vaddr_SV39_Vaddr_chunk_0 := e |}). - -Record SV39_Paddr := { SV39_Paddr_SV39_Paddr_chunk_0 : mword 56; }. -Notation "{[ r 'with' 'SV39_Paddr_SV39_Paddr_chunk_0' := e ]}" := ({| SV39_Paddr_SV39_Paddr_chunk_0 := e |}). - -Definition asid64 : Type := bits 16. - -Inductive PTW_Result := - PTW_Success : (paddr39 * SV39_PTE * paddr39 * {n : Z & ArithFact (n >= 0)} * bool) -> PTW_Result - | PTW_Failure : PTW_Error -> PTW_Result. -Arguments PTW_Result : clear implicits. - - - -Record TLB39_Entry := - { TLB39_Entry_asid : asid64; - TLB39_Entry_global : bool; - TLB39_Entry_vAddr : vaddr39; - TLB39_Entry_pAddr : paddr39; - TLB39_Entry_vMatchMask : vaddr39; - TLB39_Entry_vAddrMask : vaddr39; - TLB39_Entry_pte : SV39_PTE; - TLB39_Entry_pteAddr : paddr39; - TLB39_Entry_age : xlenbits; }. -Notation "{[ r 'with' 'TLB39_Entry_asid' := e ]}" := ({| TLB39_Entry_asid := e; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). -Notation "{[ r 'with' 'TLB39_Entry_global' := e ]}" := ({| TLB39_Entry_global := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). -Notation "{[ r 'with' 'TLB39_Entry_vAddr' := e ]}" := ({| TLB39_Entry_vAddr := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). -Notation "{[ r 'with' 'TLB39_Entry_pAddr' := e ]}" := ({| TLB39_Entry_pAddr := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). -Notation "{[ r 'with' 'TLB39_Entry_vMatchMask' := e ]}" := ({| TLB39_Entry_vMatchMask := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). -Notation "{[ r 'with' 'TLB39_Entry_vAddrMask' := e ]}" := ({| TLB39_Entry_vAddrMask := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). -Notation "{[ r 'with' 'TLB39_Entry_pte' := e ]}" := ({| TLB39_Entry_pte := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). -Notation "{[ r 'with' 'TLB39_Entry_pteAddr' := e ]}" := ({| TLB39_Entry_pteAddr := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_age := TLB39_Entry_age r |}). -Notation "{[ r 'with' 'TLB39_Entry_age' := e ]}" := ({| TLB39_Entry_age := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r |}). - -Inductive TR39_Result := - TR39_Address : paddr39 -> TR39_Result | TR39_Failure : PTW_Error -> TR39_Result. -Arguments TR39_Result : clear implicits. - - - -Inductive TR_Result := TR_Address : xlenbits -> TR_Result | TR_Failure : ExceptionType -> TR_Result. -Arguments TR_Result : clear implicits. - - - -Inductive ast := - UTYPE : (bits 20 * regbits * uop) -> ast - | RISCV_JAL : (bits 21 * regbits) -> ast - | RISCV_JALR : (bits 12 * regbits * regbits) -> ast - | BTYPE : (bits 13 * regbits * regbits * bop) -> ast - | ITYPE : (bits 12 * regbits * regbits * iop) -> ast - | SHIFTIOP : (bits 6 * regbits * regbits * sop) -> ast - | RTYPE : (regbits * regbits * regbits * rop) -> ast - | LOAD : (bits 12 * regbits * regbits * bool * word_width * bool * bool) -> ast - | STORE : (bits 12 * regbits * regbits * word_width * bool * bool) -> ast - | ADDIW : (bits 12 * regbits * regbits) -> ast - | SHIFTW : (bits 5 * regbits * regbits * sop) -> ast - | RTYPEW : (regbits * regbits * regbits * ropw) -> ast - | SHIFTIWOP : (bits 5 * regbits * regbits * sopw) -> ast - | MUL : (regbits * regbits * regbits * bool * bool * bool) -> ast - | DIV : (regbits * regbits * regbits * bool) -> ast - | REM : (regbits * regbits * regbits * bool) -> ast - | MULW : (regbits * regbits * regbits) -> ast - | DIVW : (regbits * regbits * regbits * bool) -> ast - | REMW : (regbits * regbits * regbits * bool) -> ast - | FENCE : (bits 4 * bits 4) -> ast - | FENCEI : unit -> ast - | ECALL : unit -> ast - | MRET : unit -> ast - | SRET : unit -> ast - | EBREAK : unit -> ast - | WFI : unit -> ast - | SFENCE_VMA : (regbits * regbits) -> ast - | LOADRES : (bool * bool * regbits * word_width * regbits) -> ast - | STORECON : (bool * bool * regbits * regbits * word_width * regbits) -> ast - | AMO : (amoop * bool * bool * regbits * regbits * word_width * regbits) -> ast - | CSR : (bits 12 * regbits * regbits * bool * csrop) -> ast - | NOP : unit -> ast - | C_ADDI4SPN : (cregbits * bits 8) -> ast - | C_LW : (bits 5 * cregbits * cregbits) -> ast - | C_LD : (bits 5 * cregbits * cregbits) -> ast - | C_SW : (bits 5 * cregbits * cregbits) -> ast - | C_SD : (bits 5 * cregbits * cregbits) -> ast - | C_ADDI : (bits 6 * regbits) -> ast - | C_JAL : bits 11 -> ast - | C_ADDIW : (bits 6 * regbits) -> ast - | C_LI : (bits 6 * regbits) -> ast - | C_ADDI16SP : bits 6 -> ast - | C_LUI : (bits 6 * regbits) -> ast - | C_SRLI : (bits 6 * cregbits) -> ast - | C_SRAI : (bits 6 * cregbits) -> ast - | C_ANDI : (bits 6 * cregbits) -> ast - | C_SUB : (cregbits * cregbits) -> ast - | C_XOR : (cregbits * cregbits) -> ast - | C_OR : (cregbits * cregbits) -> ast - | C_AND : (cregbits * cregbits) -> ast - | C_SUBW : (cregbits * cregbits) -> ast - | C_ADDW : (cregbits * cregbits) -> ast - | C_J : bits 11 -> ast - | C_BEQZ : (bits 8 * cregbits) -> ast - | C_BNEZ : (bits 8 * cregbits) -> ast - | C_SLLI : (bits 6 * regbits) -> ast - | C_LWSP : (bits 6 * regbits) -> ast - | C_LDSP : (bits 6 * regbits) -> ast - | C_SWSP : (bits 6 * regbits) -> ast - | C_SDSP : (bits 6 * regbits) -> ast - | C_JR : regbits -> ast - | C_JALR : regbits -> ast - | C_MV : (regbits * regbits) -> ast - | C_ADD : (regbits * regbits) -> ast - | STOP_FETCHING : unit -> ast - | THREAD_START : unit -> ast - | ILLEGAL : word -> ast - | C_ILLEGAL : unit -> ast. -Arguments ast : clear implicits. - - - -Inductive FetchResult := - F_Base : word -> FetchResult - | F_RVC : half -> FetchResult - | F_Error : (ExceptionType * xlenbits) -> FetchResult. -Arguments FetchResult : clear implicits. - - - -Inductive regfp := - RFull : string -> regfp - | RSlice : (string * {n : Z & ArithFact (n >= 0)} * {n : Z & ArithFact (n >= 0)}) -> regfp - | RSliceBit : (string * {n : Z & ArithFact (n >= 0)}) -> regfp - | RField : (string * string) -> regfp. -Arguments regfp : clear implicits. - - - -Definition regfps : Type := list regfp. - -Inductive niafp := - NIAFP_successor : unit -> niafp - | NIAFP_concrete_address : bits 64 -> niafp - | NIAFP_indirect_address : unit -> niafp. -Arguments niafp : clear implicits. - - - -Definition niafps : Type := list niafp. - -Inductive diafp := - DIAFP_none : unit -> diafp | DIAFP_concrete : bits 64 -> diafp | DIAFP_reg : regfp -> diafp. -Arguments diafp : clear implicits. - - - - - - - - - - - - - -Inductive register_value := - Regval_vector : (Z * bool * list register_value) -> register_value - | Regval_list : list register_value -> register_value - | Regval_option : option register_value -> register_value - | Regval_Counteren : Counteren -> register_value - | Regval_Mcause : Mcause -> register_value - | Regval_Medeleg : Medeleg -> register_value - | Regval_Minterrupts : Minterrupts -> register_value - | Regval_Misa : Misa -> register_value - | Regval_Mstatus : Mstatus -> register_value - | Regval_Mtvec : Mtvec -> register_value - | Regval_Privilege : Privilege -> register_value - | Regval_Sedeleg : Sedeleg -> register_value - | Regval_Sinterrupts : Sinterrupts -> register_value - | Regval_TLB39_Entry : TLB39_Entry -> register_value - | Regval_bool : bool -> register_value - | Regval_vector_64_dec_bit : mword 64 -> register_value. -Arguments register_value : clear implicits. - - - -Record regstate := - { tlb39 : option TLB39_Entry; - htif_exit_code : mword 64; - htif_done : bool; - htif_tohost : mword 64; - mtimecmp : mword 64; - tselect : mword 64; - stval : mword 64; - scause : Mcause; - sepc : mword 64; - sscratch : mword 64; - stvec : Mtvec; - satp : mword 64; - sideleg : Sinterrupts; - sedeleg : Sedeleg; - pmpcfg0 : mword 64; - pmpaddr0 : mword 64; - mhartid : mword 64; - marchid : mword 64; - mimpid : mword 64; - mvendorid : mword 64; - minstret_written : bool; - minstret : mword 64; - mtime : mword 64; - mcycle : mword 64; - scounteren : Counteren; - mcounteren : Counteren; - mscratch : mword 64; - mtval : mword 64; - mepc : mword 64; - mcause : Mcause; - mtvec : Mtvec; - medeleg : Medeleg; - mideleg : Minterrupts; - mie : Minterrupts; - mip : Minterrupts; - mstatus : Mstatus; - misa : Misa; - cur_inst : mword 64; - cur_privilege : Privilege; - x31 : mword 64; - x30 : mword 64; - x29 : mword 64; - x28 : mword 64; - x27 : mword 64; - x26 : mword 64; - x25 : mword 64; - x24 : mword 64; - x23 : mword 64; - x22 : mword 64; - x21 : mword 64; - x20 : mword 64; - x19 : mword 64; - x18 : mword 64; - x17 : mword 64; - x16 : mword 64; - x15 : mword 64; - x14 : mword 64; - x13 : mword 64; - x12 : mword 64; - x11 : mword 64; - x10 : mword 64; - x9 : mword 64; - x8 : mword 64; - x7 : mword 64; - x6 : mword 64; - x5 : mword 64; - x4 : mword 64; - x3 : mword 64; - x2 : mword 64; - x1 : mword 64; - Xs : vec (mword 64) 32; - nextPC : mword 64; - PC : mword 64; }. -Notation "{[ r 'with' 'tlb39' := e ]}" := ({| tlb39 := e; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'htif_exit_code' := e ]}" := ({| htif_exit_code := e; tlb39 := tlb39 r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'htif_done' := e ]}" := ({| htif_done := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'htif_tohost' := e ]}" := ({| htif_tohost := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'mtimecmp' := e ]}" := ({| mtimecmp := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'tselect' := e ]}" := ({| tselect := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'stval' := e ]}" := ({| stval := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'scause' := e ]}" := ({| scause := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'sepc' := e ]}" := ({| sepc := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'sscratch' := e ]}" := ({| sscratch := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'stvec' := e ]}" := ({| stvec := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'satp' := e ]}" := ({| satp := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'sideleg' := e ]}" := ({| sideleg := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'sedeleg' := e ]}" := ({| sedeleg := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'pmpcfg0' := e ]}" := ({| pmpcfg0 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'pmpaddr0' := e ]}" := ({| pmpaddr0 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'mhartid' := e ]}" := ({| mhartid := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'marchid' := e ]}" := ({| marchid := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'mimpid' := e ]}" := ({| mimpid := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'mvendorid' := e ]}" := ({| mvendorid := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'minstret_written' := e ]}" := ({| minstret_written := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'minstret' := e ]}" := ({| minstret := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'mtime' := e ]}" := ({| mtime := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'mcycle' := e ]}" := ({| mcycle := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'scounteren' := e ]}" := ({| scounteren := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'mcounteren' := e ]}" := ({| mcounteren := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'mscratch' := e ]}" := ({| mscratch := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'mtval' := e ]}" := ({| mtval := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'mepc' := e ]}" := ({| mepc := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'mcause' := e ]}" := ({| mcause := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'mtvec' := e ]}" := ({| mtvec := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'medeleg' := e ]}" := ({| medeleg := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'mideleg' := e ]}" := ({| mideleg := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'mie' := e ]}" := ({| mie := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'mip' := e ]}" := ({| mip := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'mstatus' := e ]}" := ({| mstatus := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'misa' := e ]}" := ({| misa := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'cur_inst' := e ]}" := ({| cur_inst := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'cur_privilege' := e ]}" := ({| cur_privilege := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x31' := e ]}" := ({| x31 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x30' := e ]}" := ({| x30 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x29' := e ]}" := ({| x29 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x28' := e ]}" := ({| x28 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x27' := e ]}" := ({| x27 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x26' := e ]}" := ({| x26 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x25' := e ]}" := ({| x25 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x24' := e ]}" := ({| x24 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x23' := e ]}" := ({| x23 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x22' := e ]}" := ({| x22 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x21' := e ]}" := ({| x21 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x20' := e ]}" := ({| x20 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x19' := e ]}" := ({| x19 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x18' := e ]}" := ({| x18 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x17' := e ]}" := ({| x17 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x16' := e ]}" := ({| x16 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x15' := e ]}" := ({| x15 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x14' := e ]}" := ({| x14 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x13' := e ]}" := ({| x13 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x12' := e ]}" := ({| x12 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x11' := e ]}" := ({| x11 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x10' := e ]}" := ({| x10 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x9' := e ]}" := ({| x9 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x8' := e ]}" := ({| x8 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x7' := e ]}" := ({| x7 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x6' := e ]}" := ({| x6 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x5' := e ]}" := ({| x5 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x4' := e ]}" := ({| x4 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x3' := e ]}" := ({| x3 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x2' := e ]}" := ({| x2 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'x1' := e ]}" := ({| x1 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'Xs' := e ]}" := ({| Xs := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'nextPC' := e ]}" := ({| nextPC := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; PC := PC r |}). -Notation "{[ r 'with' 'PC' := e ]}" := ({| PC := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r |}). - - - -Definition Counteren_of_regval (merge_var : register_value) -: option Counteren := - match merge_var with | Regval_Counteren (v) => Some (v) | g__12 => None end. - -Definition regval_of_Counteren (v : Counteren) : register_value := Regval_Counteren (v). - -Definition Mcause_of_regval (merge_var : register_value) -: option Mcause := - match merge_var with | Regval_Mcause (v) => Some (v) | g__11 => None end. - -Definition regval_of_Mcause (v : Mcause) : register_value := Regval_Mcause (v). - -Definition Medeleg_of_regval (merge_var : register_value) -: option Medeleg := - match merge_var with | Regval_Medeleg (v) => Some (v) | g__10 => None end. - -Definition regval_of_Medeleg (v : Medeleg) : register_value := Regval_Medeleg (v). - -Definition Minterrupts_of_regval (merge_var : register_value) -: option Minterrupts := - match merge_var with | Regval_Minterrupts (v) => Some (v) | g__9 => None end. - -Definition regval_of_Minterrupts (v : Minterrupts) : register_value := Regval_Minterrupts (v). - -Definition Misa_of_regval (merge_var : register_value) -: option Misa := - match merge_var with | Regval_Misa (v) => Some (v) | g__8 => None end. - -Definition regval_of_Misa (v : Misa) : register_value := Regval_Misa (v). - -Definition Mstatus_of_regval (merge_var : register_value) -: option Mstatus := - match merge_var with | Regval_Mstatus (v) => Some (v) | g__7 => None end. - -Definition regval_of_Mstatus (v : Mstatus) : register_value := Regval_Mstatus (v). - -Definition Mtvec_of_regval (merge_var : register_value) -: option Mtvec := - match merge_var with | Regval_Mtvec (v) => Some (v) | g__6 => None end. - -Definition regval_of_Mtvec (v : Mtvec) : register_value := Regval_Mtvec (v). - -Definition Privilege_of_regval (merge_var : register_value) -: option Privilege := - match merge_var with | Regval_Privilege (v) => Some (v) | g__5 => None end. - -Definition regval_of_Privilege (v : Privilege) : register_value := Regval_Privilege (v). - -Definition Sedeleg_of_regval (merge_var : register_value) -: option Sedeleg := - match merge_var with | Regval_Sedeleg (v) => Some (v) | g__4 => None end. - -Definition regval_of_Sedeleg (v : Sedeleg) : register_value := Regval_Sedeleg (v). - -Definition Sinterrupts_of_regval (merge_var : register_value) -: option Sinterrupts := - match merge_var with | Regval_Sinterrupts (v) => Some (v) | g__3 => None end. - -Definition regval_of_Sinterrupts (v : Sinterrupts) : register_value := Regval_Sinterrupts (v). - -Definition TLB39_Entry_of_regval (merge_var : register_value) -: option TLB39_Entry := - match merge_var with | Regval_TLB39_Entry (v) => Some (v) | g__2 => None end. - -Definition regval_of_TLB39_Entry (v : TLB39_Entry) : register_value := Regval_TLB39_Entry (v). - -Definition bool_of_regval (merge_var : register_value) -: option bool := - match merge_var with | Regval_bool (v) => Some (v) | g__1 => None end. - -Definition regval_of_bool (v : bool) : register_value := Regval_bool (v). - -Definition vector_64_dec_bit_of_regval (merge_var : register_value) -: option (mword 64) := - match merge_var with | Regval_vector_64_dec_bit (v) => Some (v) | g__0 => None end. - -Definition regval_of_vector_64_dec_bit (v : mword 64) -: register_value := - Regval_vector_64_dec_bit - (v). - - - -Definition vector_of_regval {a} n (of_regval : register_value -> option a) (rv : register_value) : option (vec a n) := match rv with - | Regval_vector (n', _, v) => if n =? n' then map_bind (vec_of_list n) (just_list (List.map of_regval v)) else None - | _ => None -end. - -Definition regval_of_vector {a} (regval_of : a -> register_value) (size : Z) (is_inc : bool) (xs : vec a size) : register_value := Regval_vector (size, is_inc, List.map regval_of (list_of_vec xs)). - -Definition list_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (list a) := match rv with - | Regval_list v => just_list (List.map of_regval v) - | _ => None -end. - -Definition regval_of_list {a} (regval_of : a -> register_value) (xs : list a) : register_value := Regval_list (List.map regval_of xs). - -Definition option_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (option a) := match rv with - | Regval_option v => option_map of_regval v - | _ => None -end. - -Definition regval_of_option {a} (regval_of : a -> register_value) (v : option a) := Regval_option (option_map regval_of v). - - -Definition tlb39_ref := {| - name := "tlb39"; - read_from := (fun s => s.(tlb39)); - write_to := (fun v s => ({[ s with tlb39 := v ]})); - of_regval := (fun v => option_of_regval (fun v => TLB39_Entry_of_regval v) v); - regval_of := (fun v => regval_of_option (fun v => regval_of_TLB39_Entry v) v) |}. - -Definition htif_exit_code_ref := {| - name := "htif_exit_code"; - read_from := (fun s => s.(htif_exit_code)); - write_to := (fun v s => ({[ s with htif_exit_code := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition htif_done_ref := {| - name := "htif_done"; - read_from := (fun s => s.(htif_done)); - write_to := (fun v s => ({[ s with htif_done := v ]})); - of_regval := (fun v => bool_of_regval v); - regval_of := (fun v => regval_of_bool v) |}. - -Definition htif_tohost_ref := {| - name := "htif_tohost"; - read_from := (fun s => s.(htif_tohost)); - write_to := (fun v s => ({[ s with htif_tohost := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition mtimecmp_ref := {| - name := "mtimecmp"; - read_from := (fun s => s.(mtimecmp)); - write_to := (fun v s => ({[ s with mtimecmp := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition tselect_ref := {| - name := "tselect"; - read_from := (fun s => s.(tselect)); - write_to := (fun v s => ({[ s with tselect := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition stval_ref := {| - name := "stval"; - read_from := (fun s => s.(stval)); - write_to := (fun v s => ({[ s with stval := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition scause_ref := {| - name := "scause"; - read_from := (fun s => s.(scause)); - write_to := (fun v s => ({[ s with scause := v ]})); - of_regval := (fun v => Mcause_of_regval v); - regval_of := (fun v => regval_of_Mcause v) |}. - -Definition sepc_ref := {| - name := "sepc"; - read_from := (fun s => s.(sepc)); - write_to := (fun v s => ({[ s with sepc := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition sscratch_ref := {| - name := "sscratch"; - read_from := (fun s => s.(sscratch)); - write_to := (fun v s => ({[ s with sscratch := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition stvec_ref := {| - name := "stvec"; - read_from := (fun s => s.(stvec)); - write_to := (fun v s => ({[ s with stvec := v ]})); - of_regval := (fun v => Mtvec_of_regval v); - regval_of := (fun v => regval_of_Mtvec v) |}. - -Definition satp_ref := {| - name := "satp"; - read_from := (fun s => s.(satp)); - write_to := (fun v s => ({[ s with satp := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition sideleg_ref := {| - name := "sideleg"; - read_from := (fun s => s.(sideleg)); - write_to := (fun v s => ({[ s with sideleg := v ]})); - of_regval := (fun v => Sinterrupts_of_regval v); - regval_of := (fun v => regval_of_Sinterrupts v) |}. - -Definition sedeleg_ref := {| - name := "sedeleg"; - read_from := (fun s => s.(sedeleg)); - write_to := (fun v s => ({[ s with sedeleg := v ]})); - of_regval := (fun v => Sedeleg_of_regval v); - regval_of := (fun v => regval_of_Sedeleg v) |}. - -Definition pmpcfg0_ref := {| - name := "pmpcfg0"; - read_from := (fun s => s.(pmpcfg0)); - write_to := (fun v s => ({[ s with pmpcfg0 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition pmpaddr0_ref := {| - name := "pmpaddr0"; - read_from := (fun s => s.(pmpaddr0)); - write_to := (fun v s => ({[ s with pmpaddr0 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition mhartid_ref := {| - name := "mhartid"; - read_from := (fun s => s.(mhartid)); - write_to := (fun v s => ({[ s with mhartid := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition marchid_ref := {| - name := "marchid"; - read_from := (fun s => s.(marchid)); - write_to := (fun v s => ({[ s with marchid := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition mimpid_ref := {| - name := "mimpid"; - read_from := (fun s => s.(mimpid)); - write_to := (fun v s => ({[ s with mimpid := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition mvendorid_ref := {| - name := "mvendorid"; - read_from := (fun s => s.(mvendorid)); - write_to := (fun v s => ({[ s with mvendorid := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition minstret_written_ref := {| - name := "minstret_written"; - read_from := (fun s => s.(minstret_written)); - write_to := (fun v s => ({[ s with minstret_written := v ]})); - of_regval := (fun v => bool_of_regval v); - regval_of := (fun v => regval_of_bool v) |}. - -Definition minstret_ref := {| - name := "minstret"; - read_from := (fun s => s.(minstret)); - write_to := (fun v s => ({[ s with minstret := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition mtime_ref := {| - name := "mtime"; - read_from := (fun s => s.(mtime)); - write_to := (fun v s => ({[ s with mtime := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition mcycle_ref := {| - name := "mcycle"; - read_from := (fun s => s.(mcycle)); - write_to := (fun v s => ({[ s with mcycle := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition scounteren_ref := {| - name := "scounteren"; - read_from := (fun s => s.(scounteren)); - write_to := (fun v s => ({[ s with scounteren := v ]})); - of_regval := (fun v => Counteren_of_regval v); - regval_of := (fun v => regval_of_Counteren v) |}. - -Definition mcounteren_ref := {| - name := "mcounteren"; - read_from := (fun s => s.(mcounteren)); - write_to := (fun v s => ({[ s with mcounteren := v ]})); - of_regval := (fun v => Counteren_of_regval v); - regval_of := (fun v => regval_of_Counteren v) |}. - -Definition mscratch_ref := {| - name := "mscratch"; - read_from := (fun s => s.(mscratch)); - write_to := (fun v s => ({[ s with mscratch := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition mtval_ref := {| - name := "mtval"; - read_from := (fun s => s.(mtval)); - write_to := (fun v s => ({[ s with mtval := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition mepc_ref := {| - name := "mepc"; - read_from := (fun s => s.(mepc)); - write_to := (fun v s => ({[ s with mepc := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition mcause_ref := {| - name := "mcause"; - read_from := (fun s => s.(mcause)); - write_to := (fun v s => ({[ s with mcause := v ]})); - of_regval := (fun v => Mcause_of_regval v); - regval_of := (fun v => regval_of_Mcause v) |}. - -Definition mtvec_ref := {| - name := "mtvec"; - read_from := (fun s => s.(mtvec)); - write_to := (fun v s => ({[ s with mtvec := v ]})); - of_regval := (fun v => Mtvec_of_regval v); - regval_of := (fun v => regval_of_Mtvec v) |}. - -Definition medeleg_ref := {| - name := "medeleg"; - read_from := (fun s => s.(medeleg)); - write_to := (fun v s => ({[ s with medeleg := v ]})); - of_regval := (fun v => Medeleg_of_regval v); - regval_of := (fun v => regval_of_Medeleg v) |}. - -Definition mideleg_ref := {| - name := "mideleg"; - read_from := (fun s => s.(mideleg)); - write_to := (fun v s => ({[ s with mideleg := v ]})); - of_regval := (fun v => Minterrupts_of_regval v); - regval_of := (fun v => regval_of_Minterrupts v) |}. - -Definition mie_ref := {| - name := "mie"; - read_from := (fun s => s.(mie)); - write_to := (fun v s => ({[ s with mie := v ]})); - of_regval := (fun v => Minterrupts_of_regval v); - regval_of := (fun v => regval_of_Minterrupts v) |}. - -Definition mip_ref := {| - name := "mip"; - read_from := (fun s => s.(mip)); - write_to := (fun v s => ({[ s with mip := v ]})); - of_regval := (fun v => Minterrupts_of_regval v); - regval_of := (fun v => regval_of_Minterrupts v) |}. - -Definition mstatus_ref := {| - name := "mstatus"; - read_from := (fun s => s.(mstatus)); - write_to := (fun v s => ({[ s with mstatus := v ]})); - of_regval := (fun v => Mstatus_of_regval v); - regval_of := (fun v => regval_of_Mstatus v) |}. - -Definition misa_ref := {| - name := "misa"; - read_from := (fun s => s.(misa)); - write_to := (fun v s => ({[ s with misa := v ]})); - of_regval := (fun v => Misa_of_regval v); - regval_of := (fun v => regval_of_Misa v) |}. - -Definition cur_inst_ref := {| - name := "cur_inst"; - read_from := (fun s => s.(cur_inst)); - write_to := (fun v s => ({[ s with cur_inst := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition cur_privilege_ref := {| - name := "cur_privilege"; - read_from := (fun s => s.(cur_privilege)); - write_to := (fun v s => ({[ s with cur_privilege := v ]})); - of_regval := (fun v => Privilege_of_regval v); - regval_of := (fun v => regval_of_Privilege v) |}. - -Definition x31_ref := {| - name := "x31"; - read_from := (fun s => s.(x31)); - write_to := (fun v s => ({[ s with x31 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x30_ref := {| - name := "x30"; - read_from := (fun s => s.(x30)); - write_to := (fun v s => ({[ s with x30 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x29_ref := {| - name := "x29"; - read_from := (fun s => s.(x29)); - write_to := (fun v s => ({[ s with x29 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x28_ref := {| - name := "x28"; - read_from := (fun s => s.(x28)); - write_to := (fun v s => ({[ s with x28 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x27_ref := {| - name := "x27"; - read_from := (fun s => s.(x27)); - write_to := (fun v s => ({[ s with x27 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x26_ref := {| - name := "x26"; - read_from := (fun s => s.(x26)); - write_to := (fun v s => ({[ s with x26 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x25_ref := {| - name := "x25"; - read_from := (fun s => s.(x25)); - write_to := (fun v s => ({[ s with x25 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x24_ref := {| - name := "x24"; - read_from := (fun s => s.(x24)); - write_to := (fun v s => ({[ s with x24 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x23_ref := {| - name := "x23"; - read_from := (fun s => s.(x23)); - write_to := (fun v s => ({[ s with x23 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x22_ref := {| - name := "x22"; - read_from := (fun s => s.(x22)); - write_to := (fun v s => ({[ s with x22 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x21_ref := {| - name := "x21"; - read_from := (fun s => s.(x21)); - write_to := (fun v s => ({[ s with x21 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x20_ref := {| - name := "x20"; - read_from := (fun s => s.(x20)); - write_to := (fun v s => ({[ s with x20 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x19_ref := {| - name := "x19"; - read_from := (fun s => s.(x19)); - write_to := (fun v s => ({[ s with x19 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x18_ref := {| - name := "x18"; - read_from := (fun s => s.(x18)); - write_to := (fun v s => ({[ s with x18 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x17_ref := {| - name := "x17"; - read_from := (fun s => s.(x17)); - write_to := (fun v s => ({[ s with x17 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x16_ref := {| - name := "x16"; - read_from := (fun s => s.(x16)); - write_to := (fun v s => ({[ s with x16 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x15_ref := {| - name := "x15"; - read_from := (fun s => s.(x15)); - write_to := (fun v s => ({[ s with x15 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x14_ref := {| - name := "x14"; - read_from := (fun s => s.(x14)); - write_to := (fun v s => ({[ s with x14 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x13_ref := {| - name := "x13"; - read_from := (fun s => s.(x13)); - write_to := (fun v s => ({[ s with x13 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x12_ref := {| - name := "x12"; - read_from := (fun s => s.(x12)); - write_to := (fun v s => ({[ s with x12 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x11_ref := {| - name := "x11"; - read_from := (fun s => s.(x11)); - write_to := (fun v s => ({[ s with x11 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x10_ref := {| - name := "x10"; - read_from := (fun s => s.(x10)); - write_to := (fun v s => ({[ s with x10 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x9_ref := {| - name := "x9"; - read_from := (fun s => s.(x9)); - write_to := (fun v s => ({[ s with x9 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x8_ref := {| - name := "x8"; - read_from := (fun s => s.(x8)); - write_to := (fun v s => ({[ s with x8 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x7_ref := {| - name := "x7"; - read_from := (fun s => s.(x7)); - write_to := (fun v s => ({[ s with x7 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x6_ref := {| - name := "x6"; - read_from := (fun s => s.(x6)); - write_to := (fun v s => ({[ s with x6 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x5_ref := {| - name := "x5"; - read_from := (fun s => s.(x5)); - write_to := (fun v s => ({[ s with x5 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x4_ref := {| - name := "x4"; - read_from := (fun s => s.(x4)); - write_to := (fun v s => ({[ s with x4 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x3_ref := {| - name := "x3"; - read_from := (fun s => s.(x3)); - write_to := (fun v s => ({[ s with x3 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x2_ref := {| - name := "x2"; - read_from := (fun s => s.(x2)); - write_to := (fun v s => ({[ s with x2 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition x1_ref := {| - name := "x1"; - read_from := (fun s => s.(x1)); - write_to := (fun v s => ({[ s with x1 := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition Xs_ref := {| - name := "Xs"; - read_from := (fun s => s.(Xs)); - write_to := (fun v s => ({[ s with Xs := v ]})); - of_regval := (fun v => vector_of_regval 32 (fun v => vector_64_dec_bit_of_regval v) v); - regval_of := (fun v => regval_of_vector (fun v => regval_of_vector_64_dec_bit v) 32 false v) |}. - -Definition nextPC_ref := {| - name := "nextPC"; - read_from := (fun s => s.(nextPC)); - write_to := (fun v s => ({[ s with nextPC := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition PC_ref := {| - name := "PC"; - read_from := (fun s => s.(PC)); - write_to := (fun v s => ({[ s with PC := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Local Open Scope string. -Definition get_regval (reg_name : string) (s : regstate) : option register_value := - if string_dec reg_name "tlb39" then Some (tlb39_ref.(regval_of) (tlb39_ref.(read_from) s)) else - if string_dec reg_name "htif_exit_code" then Some (htif_exit_code_ref.(regval_of) (htif_exit_code_ref.(read_from) s)) else - if string_dec reg_name "htif_done" then Some (htif_done_ref.(regval_of) (htif_done_ref.(read_from) s)) else - if string_dec reg_name "htif_tohost" then Some (htif_tohost_ref.(regval_of) (htif_tohost_ref.(read_from) s)) else - if string_dec reg_name "mtimecmp" then Some (mtimecmp_ref.(regval_of) (mtimecmp_ref.(read_from) s)) else - if string_dec reg_name "tselect" then Some (tselect_ref.(regval_of) (tselect_ref.(read_from) s)) else - if string_dec reg_name "stval" then Some (stval_ref.(regval_of) (stval_ref.(read_from) s)) else - if string_dec reg_name "scause" then Some (scause_ref.(regval_of) (scause_ref.(read_from) s)) else - if string_dec reg_name "sepc" then Some (sepc_ref.(regval_of) (sepc_ref.(read_from) s)) else - if string_dec reg_name "sscratch" then Some (sscratch_ref.(regval_of) (sscratch_ref.(read_from) s)) else - if string_dec reg_name "stvec" then Some (stvec_ref.(regval_of) (stvec_ref.(read_from) s)) else - if string_dec reg_name "satp" then Some (satp_ref.(regval_of) (satp_ref.(read_from) s)) else - if string_dec reg_name "sideleg" then Some (sideleg_ref.(regval_of) (sideleg_ref.(read_from) s)) else - if string_dec reg_name "sedeleg" then Some (sedeleg_ref.(regval_of) (sedeleg_ref.(read_from) s)) else - if string_dec reg_name "pmpcfg0" then Some (pmpcfg0_ref.(regval_of) (pmpcfg0_ref.(read_from) s)) else - if string_dec reg_name "pmpaddr0" then Some (pmpaddr0_ref.(regval_of) (pmpaddr0_ref.(read_from) s)) else - if string_dec reg_name "mhartid" then Some (mhartid_ref.(regval_of) (mhartid_ref.(read_from) s)) else - if string_dec reg_name "marchid" then Some (marchid_ref.(regval_of) (marchid_ref.(read_from) s)) else - if string_dec reg_name "mimpid" then Some (mimpid_ref.(regval_of) (mimpid_ref.(read_from) s)) else - if string_dec reg_name "mvendorid" then Some (mvendorid_ref.(regval_of) (mvendorid_ref.(read_from) s)) else - if string_dec reg_name "minstret_written" then Some (minstret_written_ref.(regval_of) (minstret_written_ref.(read_from) s)) else - if string_dec reg_name "minstret" then Some (minstret_ref.(regval_of) (minstret_ref.(read_from) s)) else - if string_dec reg_name "mtime" then Some (mtime_ref.(regval_of) (mtime_ref.(read_from) s)) else - if string_dec reg_name "mcycle" then Some (mcycle_ref.(regval_of) (mcycle_ref.(read_from) s)) else - if string_dec reg_name "scounteren" then Some (scounteren_ref.(regval_of) (scounteren_ref.(read_from) s)) else - if string_dec reg_name "mcounteren" then Some (mcounteren_ref.(regval_of) (mcounteren_ref.(read_from) s)) else - if string_dec reg_name "mscratch" then Some (mscratch_ref.(regval_of) (mscratch_ref.(read_from) s)) else - if string_dec reg_name "mtval" then Some (mtval_ref.(regval_of) (mtval_ref.(read_from) s)) else - if string_dec reg_name "mepc" then Some (mepc_ref.(regval_of) (mepc_ref.(read_from) s)) else - if string_dec reg_name "mcause" then Some (mcause_ref.(regval_of) (mcause_ref.(read_from) s)) else - if string_dec reg_name "mtvec" then Some (mtvec_ref.(regval_of) (mtvec_ref.(read_from) s)) else - if string_dec reg_name "medeleg" then Some (medeleg_ref.(regval_of) (medeleg_ref.(read_from) s)) else - if string_dec reg_name "mideleg" then Some (mideleg_ref.(regval_of) (mideleg_ref.(read_from) s)) else - if string_dec reg_name "mie" then Some (mie_ref.(regval_of) (mie_ref.(read_from) s)) else - if string_dec reg_name "mip" then Some (mip_ref.(regval_of) (mip_ref.(read_from) s)) else - if string_dec reg_name "mstatus" then Some (mstatus_ref.(regval_of) (mstatus_ref.(read_from) s)) else - if string_dec reg_name "misa" then Some (misa_ref.(regval_of) (misa_ref.(read_from) s)) else - if string_dec reg_name "cur_inst" then Some (cur_inst_ref.(regval_of) (cur_inst_ref.(read_from) s)) else - if string_dec reg_name "cur_privilege" then Some (cur_privilege_ref.(regval_of) (cur_privilege_ref.(read_from) s)) else - if string_dec reg_name "x31" then Some (x31_ref.(regval_of) (x31_ref.(read_from) s)) else - if string_dec reg_name "x30" then Some (x30_ref.(regval_of) (x30_ref.(read_from) s)) else - if string_dec reg_name "x29" then Some (x29_ref.(regval_of) (x29_ref.(read_from) s)) else - if string_dec reg_name "x28" then Some (x28_ref.(regval_of) (x28_ref.(read_from) s)) else - if string_dec reg_name "x27" then Some (x27_ref.(regval_of) (x27_ref.(read_from) s)) else - if string_dec reg_name "x26" then Some (x26_ref.(regval_of) (x26_ref.(read_from) s)) else - if string_dec reg_name "x25" then Some (x25_ref.(regval_of) (x25_ref.(read_from) s)) else - if string_dec reg_name "x24" then Some (x24_ref.(regval_of) (x24_ref.(read_from) s)) else - if string_dec reg_name "x23" then Some (x23_ref.(regval_of) (x23_ref.(read_from) s)) else - if string_dec reg_name "x22" then Some (x22_ref.(regval_of) (x22_ref.(read_from) s)) else - if string_dec reg_name "x21" then Some (x21_ref.(regval_of) (x21_ref.(read_from) s)) else - if string_dec reg_name "x20" then Some (x20_ref.(regval_of) (x20_ref.(read_from) s)) else - if string_dec reg_name "x19" then Some (x19_ref.(regval_of) (x19_ref.(read_from) s)) else - if string_dec reg_name "x18" then Some (x18_ref.(regval_of) (x18_ref.(read_from) s)) else - if string_dec reg_name "x17" then Some (x17_ref.(regval_of) (x17_ref.(read_from) s)) else - if string_dec reg_name "x16" then Some (x16_ref.(regval_of) (x16_ref.(read_from) s)) else - if string_dec reg_name "x15" then Some (x15_ref.(regval_of) (x15_ref.(read_from) s)) else - if string_dec reg_name "x14" then Some (x14_ref.(regval_of) (x14_ref.(read_from) s)) else - if string_dec reg_name "x13" then Some (x13_ref.(regval_of) (x13_ref.(read_from) s)) else - if string_dec reg_name "x12" then Some (x12_ref.(regval_of) (x12_ref.(read_from) s)) else - if string_dec reg_name "x11" then Some (x11_ref.(regval_of) (x11_ref.(read_from) s)) else - if string_dec reg_name "x10" then Some (x10_ref.(regval_of) (x10_ref.(read_from) s)) else - if string_dec reg_name "x9" then Some (x9_ref.(regval_of) (x9_ref.(read_from) s)) else - if string_dec reg_name "x8" then Some (x8_ref.(regval_of) (x8_ref.(read_from) s)) else - if string_dec reg_name "x7" then Some (x7_ref.(regval_of) (x7_ref.(read_from) s)) else - if string_dec reg_name "x6" then Some (x6_ref.(regval_of) (x6_ref.(read_from) s)) else - if string_dec reg_name "x5" then Some (x5_ref.(regval_of) (x5_ref.(read_from) s)) else - if string_dec reg_name "x4" then Some (x4_ref.(regval_of) (x4_ref.(read_from) s)) else - if string_dec reg_name "x3" then Some (x3_ref.(regval_of) (x3_ref.(read_from) s)) else - if string_dec reg_name "x2" then Some (x2_ref.(regval_of) (x2_ref.(read_from) s)) else - if string_dec reg_name "x1" then Some (x1_ref.(regval_of) (x1_ref.(read_from) s)) else - if string_dec reg_name "Xs" then Some (Xs_ref.(regval_of) (Xs_ref.(read_from) s)) else - if string_dec reg_name "nextPC" then Some (nextPC_ref.(regval_of) (nextPC_ref.(read_from) s)) else - if string_dec reg_name "PC" then Some (PC_ref.(regval_of) (PC_ref.(read_from) s)) else - None. - -Definition set_regval (reg_name : string) (v : register_value) (s : regstate) : option regstate := - if string_dec reg_name "tlb39" then option_map (fun v => tlb39_ref.(write_to) v s) (tlb39_ref.(of_regval) v) else - if string_dec reg_name "htif_exit_code" then option_map (fun v => htif_exit_code_ref.(write_to) v s) (htif_exit_code_ref.(of_regval) v) else - if string_dec reg_name "htif_done" then option_map (fun v => htif_done_ref.(write_to) v s) (htif_done_ref.(of_regval) v) else - if string_dec reg_name "htif_tohost" then option_map (fun v => htif_tohost_ref.(write_to) v s) (htif_tohost_ref.(of_regval) v) else - if string_dec reg_name "mtimecmp" then option_map (fun v => mtimecmp_ref.(write_to) v s) (mtimecmp_ref.(of_regval) v) else - if string_dec reg_name "tselect" then option_map (fun v => tselect_ref.(write_to) v s) (tselect_ref.(of_regval) v) else - if string_dec reg_name "stval" then option_map (fun v => stval_ref.(write_to) v s) (stval_ref.(of_regval) v) else - if string_dec reg_name "scause" then option_map (fun v => scause_ref.(write_to) v s) (scause_ref.(of_regval) v) else - if string_dec reg_name "sepc" then option_map (fun v => sepc_ref.(write_to) v s) (sepc_ref.(of_regval) v) else - if string_dec reg_name "sscratch" then option_map (fun v => sscratch_ref.(write_to) v s) (sscratch_ref.(of_regval) v) else - if string_dec reg_name "stvec" then option_map (fun v => stvec_ref.(write_to) v s) (stvec_ref.(of_regval) v) else - if string_dec reg_name "satp" then option_map (fun v => satp_ref.(write_to) v s) (satp_ref.(of_regval) v) else - if string_dec reg_name "sideleg" then option_map (fun v => sideleg_ref.(write_to) v s) (sideleg_ref.(of_regval) v) else - if string_dec reg_name "sedeleg" then option_map (fun v => sedeleg_ref.(write_to) v s) (sedeleg_ref.(of_regval) v) else - if string_dec reg_name "pmpcfg0" then option_map (fun v => pmpcfg0_ref.(write_to) v s) (pmpcfg0_ref.(of_regval) v) else - if string_dec reg_name "pmpaddr0" then option_map (fun v => pmpaddr0_ref.(write_to) v s) (pmpaddr0_ref.(of_regval) v) else - if string_dec reg_name "mhartid" then option_map (fun v => mhartid_ref.(write_to) v s) (mhartid_ref.(of_regval) v) else - if string_dec reg_name "marchid" then option_map (fun v => marchid_ref.(write_to) v s) (marchid_ref.(of_regval) v) else - if string_dec reg_name "mimpid" then option_map (fun v => mimpid_ref.(write_to) v s) (mimpid_ref.(of_regval) v) else - if string_dec reg_name "mvendorid" then option_map (fun v => mvendorid_ref.(write_to) v s) (mvendorid_ref.(of_regval) v) else - if string_dec reg_name "minstret_written" then option_map (fun v => minstret_written_ref.(write_to) v s) (minstret_written_ref.(of_regval) v) else - if string_dec reg_name "minstret" then option_map (fun v => minstret_ref.(write_to) v s) (minstret_ref.(of_regval) v) else - if string_dec reg_name "mtime" then option_map (fun v => mtime_ref.(write_to) v s) (mtime_ref.(of_regval) v) else - if string_dec reg_name "mcycle" then option_map (fun v => mcycle_ref.(write_to) v s) (mcycle_ref.(of_regval) v) else - if string_dec reg_name "scounteren" then option_map (fun v => scounteren_ref.(write_to) v s) (scounteren_ref.(of_regval) v) else - if string_dec reg_name "mcounteren" then option_map (fun v => mcounteren_ref.(write_to) v s) (mcounteren_ref.(of_regval) v) else - if string_dec reg_name "mscratch" then option_map (fun v => mscratch_ref.(write_to) v s) (mscratch_ref.(of_regval) v) else - if string_dec reg_name "mtval" then option_map (fun v => mtval_ref.(write_to) v s) (mtval_ref.(of_regval) v) else - if string_dec reg_name "mepc" then option_map (fun v => mepc_ref.(write_to) v s) (mepc_ref.(of_regval) v) else - if string_dec reg_name "mcause" then option_map (fun v => mcause_ref.(write_to) v s) (mcause_ref.(of_regval) v) else - if string_dec reg_name "mtvec" then option_map (fun v => mtvec_ref.(write_to) v s) (mtvec_ref.(of_regval) v) else - if string_dec reg_name "medeleg" then option_map (fun v => medeleg_ref.(write_to) v s) (medeleg_ref.(of_regval) v) else - if string_dec reg_name "mideleg" then option_map (fun v => mideleg_ref.(write_to) v s) (mideleg_ref.(of_regval) v) else - if string_dec reg_name "mie" then option_map (fun v => mie_ref.(write_to) v s) (mie_ref.(of_regval) v) else - if string_dec reg_name "mip" then option_map (fun v => mip_ref.(write_to) v s) (mip_ref.(of_regval) v) else - if string_dec reg_name "mstatus" then option_map (fun v => mstatus_ref.(write_to) v s) (mstatus_ref.(of_regval) v) else - if string_dec reg_name "misa" then option_map (fun v => misa_ref.(write_to) v s) (misa_ref.(of_regval) v) else - if string_dec reg_name "cur_inst" then option_map (fun v => cur_inst_ref.(write_to) v s) (cur_inst_ref.(of_regval) v) else - if string_dec reg_name "cur_privilege" then option_map (fun v => cur_privilege_ref.(write_to) v s) (cur_privilege_ref.(of_regval) v) else - if string_dec reg_name "x31" then option_map (fun v => x31_ref.(write_to) v s) (x31_ref.(of_regval) v) else - if string_dec reg_name "x30" then option_map (fun v => x30_ref.(write_to) v s) (x30_ref.(of_regval) v) else - if string_dec reg_name "x29" then option_map (fun v => x29_ref.(write_to) v s) (x29_ref.(of_regval) v) else - if string_dec reg_name "x28" then option_map (fun v => x28_ref.(write_to) v s) (x28_ref.(of_regval) v) else - if string_dec reg_name "x27" then option_map (fun v => x27_ref.(write_to) v s) (x27_ref.(of_regval) v) else - if string_dec reg_name "x26" then option_map (fun v => x26_ref.(write_to) v s) (x26_ref.(of_regval) v) else - if string_dec reg_name "x25" then option_map (fun v => x25_ref.(write_to) v s) (x25_ref.(of_regval) v) else - if string_dec reg_name "x24" then option_map (fun v => x24_ref.(write_to) v s) (x24_ref.(of_regval) v) else - if string_dec reg_name "x23" then option_map (fun v => x23_ref.(write_to) v s) (x23_ref.(of_regval) v) else - if string_dec reg_name "x22" then option_map (fun v => x22_ref.(write_to) v s) (x22_ref.(of_regval) v) else - if string_dec reg_name "x21" then option_map (fun v => x21_ref.(write_to) v s) (x21_ref.(of_regval) v) else - if string_dec reg_name "x20" then option_map (fun v => x20_ref.(write_to) v s) (x20_ref.(of_regval) v) else - if string_dec reg_name "x19" then option_map (fun v => x19_ref.(write_to) v s) (x19_ref.(of_regval) v) else - if string_dec reg_name "x18" then option_map (fun v => x18_ref.(write_to) v s) (x18_ref.(of_regval) v) else - if string_dec reg_name "x17" then option_map (fun v => x17_ref.(write_to) v s) (x17_ref.(of_regval) v) else - if string_dec reg_name "x16" then option_map (fun v => x16_ref.(write_to) v s) (x16_ref.(of_regval) v) else - if string_dec reg_name "x15" then option_map (fun v => x15_ref.(write_to) v s) (x15_ref.(of_regval) v) else - if string_dec reg_name "x14" then option_map (fun v => x14_ref.(write_to) v s) (x14_ref.(of_regval) v) else - if string_dec reg_name "x13" then option_map (fun v => x13_ref.(write_to) v s) (x13_ref.(of_regval) v) else - if string_dec reg_name "x12" then option_map (fun v => x12_ref.(write_to) v s) (x12_ref.(of_regval) v) else - if string_dec reg_name "x11" then option_map (fun v => x11_ref.(write_to) v s) (x11_ref.(of_regval) v) else - if string_dec reg_name "x10" then option_map (fun v => x10_ref.(write_to) v s) (x10_ref.(of_regval) v) else - if string_dec reg_name "x9" then option_map (fun v => x9_ref.(write_to) v s) (x9_ref.(of_regval) v) else - if string_dec reg_name "x8" then option_map (fun v => x8_ref.(write_to) v s) (x8_ref.(of_regval) v) else - if string_dec reg_name "x7" then option_map (fun v => x7_ref.(write_to) v s) (x7_ref.(of_regval) v) else - if string_dec reg_name "x6" then option_map (fun v => x6_ref.(write_to) v s) (x6_ref.(of_regval) v) else - if string_dec reg_name "x5" then option_map (fun v => x5_ref.(write_to) v s) (x5_ref.(of_regval) v) else - if string_dec reg_name "x4" then option_map (fun v => x4_ref.(write_to) v s) (x4_ref.(of_regval) v) else - if string_dec reg_name "x3" then option_map (fun v => x3_ref.(write_to) v s) (x3_ref.(of_regval) v) else - if string_dec reg_name "x2" then option_map (fun v => x2_ref.(write_to) v s) (x2_ref.(of_regval) v) else - if string_dec reg_name "x1" then option_map (fun v => x1_ref.(write_to) v s) (x1_ref.(of_regval) v) else - if string_dec reg_name "Xs" then option_map (fun v => Xs_ref.(write_to) v s) (Xs_ref.(of_regval) v) else - if string_dec reg_name "nextPC" then option_map (fun v => nextPC_ref.(write_to) v s) (nextPC_ref.(of_regval) v) else - if string_dec reg_name "PC" then option_map (fun v => PC_ref.(write_to) v s) (PC_ref.(of_regval) v) else - None. - -Definition register_accessors := (get_regval, set_regval). - - -Definition MR a r := monadR register_value a r exception. -Definition M a := monad register_value a exception. diff --git a/snapshots/coq/README b/snapshots/coq/README deleted file mode 100644 index bd7f12d0..00000000 --- a/snapshots/coq/README +++ /dev/null @@ -1,2 +0,0 @@ -Check out a copy of https://github.com/mit-plv/bbv in the parent directory and -build it. Then run ./build. diff --git a/snapshots/coq/README.md b/snapshots/coq/README.md new file mode 100644 index 00000000..8cc69d7f --- /dev/null +++ b/snapshots/coq/README.md @@ -0,0 +1,7 @@ +Check out a copy of in the parent directory and +build it. Then run `./build`. + +The model was built with +* `sail` commit `1c80d84c` +* `sail-cheri-mips` commit `17deb9f2` +and checked against bbv commit `8f5aece` and coq 8.8.2. diff --git a/snapshots/coq/build b/snapshots/coq/build index e672912e..a4afcd95 100755 --- a/snapshots/coq/build +++ b/snapshots/coq/build @@ -1,7 +1,7 @@ #!/bin/bash -if [ ! -d mips ]; then - echo Run clean from the coq directory +if [ ! -d cheri-mips ]; then + echo Run build from the coq directory exit 1 fi @@ -13,7 +13,13 @@ fi set -ex cd lib/coq make -cd ../../mips +cd ../../cheri-mips coqc -R ../../bbv/theories bbv -R ../lib/coq Sail mips_extras.v coqc -R ../../bbv/theories bbv -R ../lib/coq Sail mips_types.v coqc -R ../../bbv/theories bbv -R ../lib/coq Sail mips.v +coqc -R ../../bbv/theories bbv -R ../lib/coq Sail cheri_types.v +coqc -R ../../bbv/theories bbv -R ../lib/coq Sail cheri.v +cd ../riscv +coqc -R ../../bbv/theories bbv -R ../lib/coq Sail riscv_extras.v +coqc -R ../../bbv/theories bbv -R ../lib/coq Sail riscv_types.v +coqc -R ../../bbv/theories bbv -R ../lib/coq Sail riscv.v diff --git a/snapshots/coq/cheri-mips/_CoqProject b/snapshots/coq/cheri-mips/_CoqProject new file mode 100644 index 00000000..ad38d28d --- /dev/null +++ b/snapshots/coq/cheri-mips/_CoqProject @@ -0,0 +1,2 @@ +-R ../../bbv/theories bbv +-R ../lib/coq Sail \ No newline at end of file diff --git a/snapshots/coq/cheri-mips/cheri.v b/snapshots/coq/cheri-mips/cheri.v new file mode 100644 index 00000000..3a5b0ce6 --- /dev/null +++ b/snapshots/coq/cheri-mips/cheri.v @@ -0,0 +1,12167 @@ +(*Generated by Sail from cheri.*) +Require Import Sail2_instr_kinds. +Require Import Sail2_values. +Require Import Sail2_string. +Require Import Sail2_real. +Require Import Sail2_operators_mwords. +Require Import Sail2_prompt_monad. +Require Import Sail2_prompt. +Require Import Sail2_state. +Require Import cheri_types. +Require Import mips_extras. +Import ListNotations. +Open Scope string. +Open Scope bool. +Section Content. + +Definition cap_size := 32. +Hint Unfold cap_size : sail. +Definition trace : bool := false. +Hint Unfold trace : sail. +Definition eq_unit (g__19 : unit) (g__20 : unit) : bool := true. + +Definition neq_int (x : Z) (y : Z) : bool := negb (Z.eqb x y). + +Definition neq_bool (x : bool) (y : bool) : bool := negb (Bool.eqb x y). + +Definition undefined_option {a : Type} (typ_a : a) +: M (option a) := + + (undefined_unit tt) >>= fun u_0 : unit => + let u_1 : a := typ_a in + (internal_pick [Some (u_1);None]) + : M (option a). + +Definition is_none {a : Type} (opt : option a) +: bool := + + match opt with | Some (_) => false | None => true end. + +Definition is_some {a : Type} (opt : option a) +: bool := + + match opt with | Some (_) => true | None => false end. + +Definition sail_mask {v0 : Z} (len : Z) (v : mword v0) `{ArithFact (len >= 0 /\ v0 >= 0)} +: mword len := + + if sumbool_of_bool ((Z.leb len (length_mword v))) then vector_truncate v len + else zero_extend v len. + +Definition neq_vec {n : Z} (x : mword n) (y : mword n) : bool := negb (eq_vec x y). + + + +Definition cast_unit_vec (b : bitU) +: mword 1 := + + match b with | B0 => (vec_of_bits [B0] : mword 1) | _ => (vec_of_bits [B1] : mword 1) end. + +Definition __MIPS_write (addr : mword 64) (width : Z) (data : mword (8 * width)) +: M (unit) := + + (write_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr data) >> + returnm (tt + : unit). + +Definition __MIPS_read (addr : mword 64) (width : Z) `{ArithFact (width >= 0)} +: M (mword (8 * width)) := + + (read_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr) + : M (mword (8 * width)). + +Definition zopz0zQzQ {n0 : Z} (bs : mword n0) (n : Z) `{ArithFact (n >= 0)} +: mword (n0 * n) := + + replicate_bits bs n. + +Definition undefined_exception '(tt : unit) +: M (exception) := + + (undefined_string tt) >>= fun u_0 : string => + (undefined_unit tt) >>= fun u_1 : unit => + (internal_pick + [ISAException + (u_1);Error_not_implemented + (u_0);Error_misaligned_access + (u_1);Error_EBREAK + (u_1);Error_internal_error + (u_1)]) + : M (exception). + +Definition mips_sign_extend {n : Z} (m__tv : Z) (v : mword n) `{ArithFact (m__tv >= n)} +: mword m__tv := + + sign_extend v m__tv. + +Definition mips_zero_extend {n : Z} (m__tv : Z) (v : mword n) `{ArithFact (m__tv >= n)} +: mword m__tv := + + zero_extend v m__tv. + +Axiom sign_extend : forall {n : Z} {m : Z} (_ : mword n) `{ArithFact (m >= n)}, mword m. + +Axiom zero_extend : forall {n : Z} {m : Z} (_ : mword n) `{ArithFact (m >= n)}, mword m. + +Definition zeros_implicit (n__tv : Z) '(tt : unit) `{ArithFact (n__tv >= 0)} +: mword n__tv := + + zeros n__tv. +Arguments zeros_implicit _ _ {_}. + +Definition ones_n (n : Z) `{ArithFact (n >= 0)} +: mword n := + + autocast (replicate_bits (vec_of_bits [B1] : mword 1) n). + +Definition ones_implicit (n__tv : Z) '(tt : unit) `{ArithFact (n__tv >= 0)} +: mword n__tv := + + ones_n n__tv. +Arguments ones_implicit _ _ {_}. + +Definition zopz0zI_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= (0 + 1))} +: bool := + + Z.ltb (projT1 (sint x)) (projT1 (sint y)). + +Definition zopz0zKzJ_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= (0 + 1))} +: bool := + + Z.geb (projT1 (sint x)) (projT1 (sint y)). + +Definition zopz0zI_u {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 0)} +: bool := + + Z.ltb (projT1 (uint x)) (projT1 (uint y)). + +Definition zopz0zKzJ_u {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 0)} +: bool := + + Z.geb (projT1 (uint x)) (projT1 (uint y)). + +Definition bool_to_bits (x : bool) +: mword 1 := + + if (x) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1). + +Definition bool_to_bit (x : bool) : bitU := if (x) then B1 else B0. + +Definition bit_to_bool (b : bitU) : bool := match b with | B1 => true | _ => false end. + +Definition bits_to_bool (x : mword 1) : bool := bit_to_bool (access_vec_dec x 0). + +Definition to_bits (l : Z) (n : Z) `{ArithFact (l >= 0)} : mword l := get_slice_int l n 0. + +Definition mask {m : Z} (n__tv : Z) (bs : mword m) `{ArithFact (m >= n__tv /\ n__tv >= (0 + 1))} +: mword n__tv := + + autocast (subrange_vec_dec bs (Z.sub n__tv 1) 0). + +Definition undefined_CauseReg '(tt : unit) +: M (CauseReg) := + + (undefined_bitvector 32) >>= fun w__0 : mword 32 => + returnm (({| CauseReg_CauseReg_chunk_0 := w__0 |}) + : CauseReg). + +Definition Mk_CauseReg (v : mword 32) +: CauseReg := + + {| CauseReg_CauseReg_chunk_0 := (subrange_vec_dec v 31 0) |}. + +Definition _get_CauseReg_bits (v : CauseReg) +: mword 32 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 0. + +Definition _set_CauseReg_bits (r_ref : register_ref regstate register_value CauseReg) (v : mword 32) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_bits (v : CauseReg) (x : mword 32) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}. + +Definition _get_CauseReg_BD (v : CauseReg) +: mword 1 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 31. + +Definition _set_CauseReg_BD (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 31 31 (subrange_vec_dec v 0 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_BD (v : CauseReg) (x : mword 1) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 31 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_CauseReg_CE (v : CauseReg) +: mword 2 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 29 28. + +Definition _set_CauseReg_CE (r_ref : register_ref regstate register_value CauseReg) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 29 28 (subrange_vec_dec v 1 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_CE (v : CauseReg) (x : mword 2) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 29 28 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_CauseReg_IV (v : CauseReg) +: mword 1 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 23 23. + +Definition _set_CauseReg_IV (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 23 23 (subrange_vec_dec v 0 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_IV (v : CauseReg) (x : mword 1) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 23 23 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_CauseReg_WP (v : CauseReg) +: mword 1 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 22 22. + +Definition _set_CauseReg_WP (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_WP (v : CauseReg) (x : mword 1) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_CauseReg_IP (v : CauseReg) +: mword 8 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 15 8. + +Definition _set_CauseReg_IP (r_ref : register_ref regstate register_value CauseReg) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 15 8 (subrange_vec_dec v 7 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_IP (v : CauseReg) (x : mword 8) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 15 8 (subrange_vec_dec x 7 0)) ]}. + +Definition _get_CauseReg_ExcCode (v : CauseReg) +: mword 5 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 6 2. + +Definition _set_CauseReg_ExcCode +(r_ref : register_ref regstate register_value CauseReg) (v : mword 5) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 6 2 (subrange_vec_dec v 4 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_ExcCode (v : CauseReg) (x : mword 5) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 6 2 (subrange_vec_dec x 4 0)) ]}. + +Definition undefined_TLBEntryLoReg '(tt : unit) +: M (TLBEntryLoReg) := + + (undefined_bitvector 64) >>= fun w__0 : mword 64 => + returnm (({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := w__0 |}) + : TLBEntryLoReg). + +Definition Mk_TLBEntryLoReg (v : mword 64) +: TLBEntryLoReg := + + {| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_TLBEntryLoReg_bits (v : TLBEntryLoReg) +: mword 64 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 0. + +Definition _set_TLBEntryLoReg_bits +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 0 + (subrange_vec_dec v 63 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_bits (v : TLBEntryLoReg) (x : mword 64) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 0 + (subrange_vec_dec x 63 0)) ]}. + +Definition _get_TLBEntryLoReg_CapS (v : TLBEntryLoReg) +: mword 1 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 63. + +Definition _set_TLBEntryLoReg_CapS +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 63 + (subrange_vec_dec v 0 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_CapS (v : TLBEntryLoReg) (x : mword 1) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 63 + (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntryLoReg_CapL (v : TLBEntryLoReg) +: mword 1 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 62 62. + +Definition _set_TLBEntryLoReg_CapL +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 62 62 + (subrange_vec_dec v 0 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_CapL (v : TLBEntryLoReg) (x : mword 1) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 62 62 + (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntryLoReg_PFN (v : TLBEntryLoReg) +: mword 24 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 29 6. + +Definition _set_TLBEntryLoReg_PFN +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 24) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 29 6 + (subrange_vec_dec v 23 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_PFN (v : TLBEntryLoReg) (x : mword 24) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 29 6 + (subrange_vec_dec x 23 0)) ]}. + +Definition _get_TLBEntryLoReg_C (v : TLBEntryLoReg) +: mword 3 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 5 3. + +Definition _set_TLBEntryLoReg_C +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 3) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 5 3 + (subrange_vec_dec v 2 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_C (v : TLBEntryLoReg) (x : mword 3) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 5 3 (subrange_vec_dec x 2 0)) ]}. + +Definition _get_TLBEntryLoReg_D (v : TLBEntryLoReg) +: mword 1 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 2 2. + +Definition _set_TLBEntryLoReg_D +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 2 2 + (subrange_vec_dec v 0 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_D (v : TLBEntryLoReg) (x : mword 1) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntryLoReg_V (v : TLBEntryLoReg) +: mword 1 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 1 1. + +Definition _set_TLBEntryLoReg_V +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 1 1 + (subrange_vec_dec v 0 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_V (v : TLBEntryLoReg) (x : mword 1) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntryLoReg_G (v : TLBEntryLoReg) +: mword 1 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 0 0. + +Definition _set_TLBEntryLoReg_G +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 0 0 + (subrange_vec_dec v 0 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_G (v : TLBEntryLoReg) (x : mword 1) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition undefined_TLBEntryHiReg '(tt : unit) +: M (TLBEntryHiReg) := + + (undefined_bitvector 64) >>= fun w__0 : mword 64 => + returnm (({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := w__0 |}) + : TLBEntryHiReg). + +Definition Mk_TLBEntryHiReg (v : mword 64) +: TLBEntryHiReg := + + {| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_TLBEntryHiReg_bits (v : TLBEntryHiReg) +: mword 64 := + + subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 0. + +Definition _set_TLBEntryHiReg_bits +(r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 0 + (subrange_vec_dec v 63 0)) ]} + : TLBEntryHiReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryHiReg_bits (v : TLBEntryHiReg) (x : mword 64) +: TLBEntryHiReg := + + {[ v with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 0 + (subrange_vec_dec x 63 0)) ]}. + +Definition _get_TLBEntryHiReg_R (v : TLBEntryHiReg) +: mword 2 := + + subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 62. + +Definition _set_TLBEntryHiReg_R +(r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 62 + (subrange_vec_dec v 1 0)) ]} + : TLBEntryHiReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryHiReg_R (v : TLBEntryHiReg) (x : mword 2) +: TLBEntryHiReg := + + {[ v with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 62 + (subrange_vec_dec x 1 0)) ]}. + +Definition _get_TLBEntryHiReg_VPN2 (v : TLBEntryHiReg) +: mword 27 := + + subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 39 13. + +Definition _set_TLBEntryHiReg_VPN2 +(r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 27) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 39 13 + (subrange_vec_dec v 26 0)) ]} + : TLBEntryHiReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryHiReg_VPN2 (v : TLBEntryHiReg) (x : mword 27) +: TLBEntryHiReg := + + {[ v with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 39 13 + (subrange_vec_dec x 26 0)) ]}. + +Definition _get_TLBEntryHiReg_ASID (v : TLBEntryHiReg) +: mword 8 := + + subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 7 0. + +Definition _set_TLBEntryHiReg_ASID +(r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 7 0 + (subrange_vec_dec v 7 0)) ]} + : TLBEntryHiReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryHiReg_ASID (v : TLBEntryHiReg) (x : mword 8) +: TLBEntryHiReg := + + {[ v with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}. + +Definition undefined_ContextReg '(tt : unit) +: M (ContextReg) := + + (undefined_bitvector 64) >>= fun w__0 : mword 64 => + returnm (({| ContextReg_ContextReg_chunk_0 := w__0 |}) + : ContextReg). + +Definition Mk_ContextReg (v : mword 64) +: ContextReg := + + {| ContextReg_ContextReg_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_ContextReg_bits (v : ContextReg) +: mword 64 := + + subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 0. + +Definition _set_ContextReg_bits +(r_ref : register_ref regstate register_value ContextReg) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + ContextReg_ContextReg_chunk_0 := + (update_subrange_vec_dec r.(ContextReg_ContextReg_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : ContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_ContextReg_bits (v : ContextReg) (x : mword 64) +: ContextReg := + + {[ v with + ContextReg_ContextReg_chunk_0 := + (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_ContextReg_PTEBase (v : ContextReg) +: mword 41 := + + subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 23. + +Definition _set_ContextReg_PTEBase +(r_ref : register_ref regstate register_value ContextReg) (v : mword 41) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + ContextReg_ContextReg_chunk_0 := + (update_subrange_vec_dec r.(ContextReg_ContextReg_chunk_0) 63 23 (subrange_vec_dec v 40 0)) ]} + : ContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_ContextReg_PTEBase (v : ContextReg) (x : mword 41) +: ContextReg := + + {[ v with + ContextReg_ContextReg_chunk_0 := + (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 23 (subrange_vec_dec x 40 0)) ]}. + +Definition _get_ContextReg_BadVPN2 (v : ContextReg) +: mword 19 := + + subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 22 4. + +Definition _set_ContextReg_BadVPN2 +(r_ref : register_ref regstate register_value ContextReg) (v : mword 19) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + ContextReg_ContextReg_chunk_0 := + (update_subrange_vec_dec r.(ContextReg_ContextReg_chunk_0) 22 4 (subrange_vec_dec v 18 0)) ]} + : ContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_ContextReg_BadVPN2 (v : ContextReg) (x : mword 19) +: ContextReg := + + {[ v with + ContextReg_ContextReg_chunk_0 := + (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 22 4 (subrange_vec_dec x 18 0)) ]}. + +Definition undefined_XContextReg '(tt : unit) +: M (XContextReg) := + + (undefined_bitvector 64) >>= fun w__0 : mword 64 => + returnm (({| XContextReg_XContextReg_chunk_0 := w__0 |}) + : XContextReg). + +Definition Mk_XContextReg (v : mword 64) +: XContextReg := + + {| XContextReg_XContextReg_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_XContextReg_bits (v : XContextReg) +: mword 64 := + + subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 0. + +Definition _set_XContextReg_bits +(r_ref : register_ref regstate register_value XContextReg) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : XContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_XContextReg_bits (v : XContextReg) (x : mword 64) +: XContextReg := + + {[ v with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_XContextReg_XPTEBase (v : XContextReg) +: mword 31 := + + subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 33. + +Definition _set_XContextReg_XPTEBase +(r_ref : register_ref regstate register_value XContextReg) (v : mword 31) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 63 33 + (subrange_vec_dec v 30 0)) ]} + : XContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_XContextReg_XPTEBase (v : XContextReg) (x : mword 31) +: XContextReg := + + {[ v with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 33 (subrange_vec_dec x 30 0)) ]}. + +Definition _get_XContextReg_XR (v : XContextReg) +: mword 2 := + + subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 32 31. + +Definition _set_XContextReg_XR +(r_ref : register_ref regstate register_value XContextReg) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 32 31 (subrange_vec_dec v 1 0)) ]} + : XContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_XContextReg_XR (v : XContextReg) (x : mword 2) +: XContextReg := + + {[ v with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 32 31 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_XContextReg_XBadVPN2 (v : XContextReg) +: mword 27 := + + subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 30 4. + +Definition _set_XContextReg_XBadVPN2 +(r_ref : register_ref regstate register_value XContextReg) (v : mword 27) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 30 4 (subrange_vec_dec v 26 0)) ]} + : XContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_XContextReg_XBadVPN2 (v : XContextReg) (x : mword 27) +: XContextReg := + + {[ v with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 30 4 (subrange_vec_dec x 26 0)) ]}. + +Definition TLBNumEntries := 64. +Hint Unfold TLBNumEntries : sail. +Definition TLBIndexMax : TLBIndexT := (vec_of_bits [B1;B1;B1;B1;B1;B1] : mword 6). +Hint Unfold TLBIndexMax : sail. +Definition MAX (n : Z) `{ArithFact (n >= 0)} +: {_retval : Z & ArithFact (_retval = (2 ^ n - 1))} := + + build_ex(Z.sub (projT1 (pow2 n)) 1). + +Definition MAX_U64 := projT1 (MAX 64). +Hint Unfold MAX_U64 : sail. +Definition MAX_VA := projT1 (MAX 40). +Hint Unfold MAX_VA : sail. +Definition MAX_PA := projT1 (MAX 36). +Hint Unfold MAX_PA : sail. +Definition undefined_TLBEntry '(tt : unit) +: M (TLBEntry) := + + (undefined_bitvector 53) >>= fun w__0 : mword 53 => + (undefined_bitvector 64) >>= fun w__1 : mword 64 => + returnm (({| TLBEntry_TLBEntry_chunk_1 := w__0; + TLBEntry_TLBEntry_chunk_0 := w__1 |}) + : TLBEntry). + +Definition Mk_TLBEntry (v : mword 117) +: TLBEntry := + + {| TLBEntry_TLBEntry_chunk_1 := (subrange_vec_dec v 116 64); + TLBEntry_TLBEntry_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_TLBEntry_bits (v : TLBEntry) +: mword 117 := + + concat_vec (subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 0) + (subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 0). + +Definition _set_TLBEntry_bits +(r_ref : register_ref regstate register_value TLBEntry) (v : mword 117) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 52 0 (subrange_vec_dec v 116 64)) ]} + : TLBEntry in + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_bits (v : TLBEntry) (x : mword 117) +: TLBEntry := + + let v := + {[ v with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 0 (subrange_vec_dec x 116 64)) ]} in + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_TLBEntry_pagemask (v : TLBEntry) +: mword 16 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 37. + +Definition _set_TLBEntry_pagemask +(r_ref : register_ref regstate register_value TLBEntry) (v : mword 16) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 52 37 (subrange_vec_dec v 15 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_pagemask (v : TLBEntry) (x : mword 16) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 37 (subrange_vec_dec x 15 0)) ]}. + +Definition _get_TLBEntry_r (v : TLBEntry) +: mword 2 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 36 35. + +Definition _set_TLBEntry_r (r_ref : register_ref regstate register_value TLBEntry) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 36 35 (subrange_vec_dec v 1 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_r (v : TLBEntry) (x : mword 2) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 36 35 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_TLBEntry_vpn2 (v : TLBEntry) +: mword 27 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 34 8. + +Definition _set_TLBEntry_vpn2 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 27) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 34 8 (subrange_vec_dec v 26 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_vpn2 (v : TLBEntry) (x : mword 27) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 34 8 (subrange_vec_dec x 26 0)) ]}. + +Definition _get_TLBEntry_asid (v : TLBEntry) +: mword 8 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 7 0. + +Definition _set_TLBEntry_asid (r_ref : register_ref regstate register_value TLBEntry) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 7 0 (subrange_vec_dec v 7 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_asid (v : TLBEntry) (x : mword 8) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 7 0 (subrange_vec_dec x 7 0)) ]}. + +Definition _get_TLBEntry_g (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 63. + +Definition _set_TLBEntry_g (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 63 63 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_g (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 63 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_valid (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 62 62. + +Definition _set_TLBEntry_valid (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 62 62 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_valid (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 62 62 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_caps1 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 61 61. + +Definition _set_TLBEntry_caps1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 61 61 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_caps1 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 61 61 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_capl1 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 60 60. + +Definition _set_TLBEntry_capl1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 60 60 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_capl1 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 60 60 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_pfn1 (v : TLBEntry) +: mword 24 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 59 36. + +Definition _set_TLBEntry_pfn1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 24) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 59 36 (subrange_vec_dec v 23 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_pfn1 (v : TLBEntry) (x : mword 24) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 59 36 (subrange_vec_dec x 23 0)) ]}. + +Definition _get_TLBEntry_c1 (v : TLBEntry) +: mword 3 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 35 33. + +Definition _set_TLBEntry_c1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 3) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 35 33 (subrange_vec_dec v 2 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_c1 (v : TLBEntry) (x : mword 3) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 35 33 (subrange_vec_dec x 2 0)) ]}. + +Definition _get_TLBEntry_d1 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 32 32. + +Definition _set_TLBEntry_d1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 32 32 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_d1 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 32 32 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_v1 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 31 31. + +Definition _set_TLBEntry_v1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 31 31 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_v1 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 31 31 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_caps0 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 30 30. + +Definition _set_TLBEntry_caps0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 30 30 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_caps0 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 30 30 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_capl0 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 29 29. + +Definition _set_TLBEntry_capl0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 29 29 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_capl0 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 29 29 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_pfn0 (v : TLBEntry) +: mword 24 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 28 5. + +Definition _set_TLBEntry_pfn0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 24) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 28 5 (subrange_vec_dec v 23 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_pfn0 (v : TLBEntry) (x : mword 24) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 28 5 (subrange_vec_dec x 23 0)) ]}. + +Definition _get_TLBEntry_c0 (v : TLBEntry) +: mword 3 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 4 2. + +Definition _set_TLBEntry_c0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 3) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 4 2 (subrange_vec_dec v 2 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_c0 (v : TLBEntry) (x : mword 3) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 4 2 (subrange_vec_dec x 2 0)) ]}. + +Definition _get_TLBEntry_d0 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 1 1. + +Definition _set_TLBEntry_d0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_d0 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_v0 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 0 0. + +Definition _set_TLBEntry_v0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_v0 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition TLBEntries : vec (register_ref regstate register_value TLBEntry) 64 := +vec_of_list_len [TLBEntry63_ref;TLBEntry62_ref;TLBEntry61_ref;TLBEntry60_ref;TLBEntry59_ref;TLBEntry58_ref;TLBEntry57_ref;TLBEntry56_ref;TLBEntry55_ref;TLBEntry54_ref;TLBEntry53_ref;TLBEntry52_ref;TLBEntry51_ref;TLBEntry50_ref;TLBEntry49_ref;TLBEntry48_ref;TLBEntry47_ref;TLBEntry46_ref;TLBEntry45_ref;TLBEntry44_ref;TLBEntry43_ref; + TLBEntry42_ref;TLBEntry41_ref;TLBEntry40_ref;TLBEntry39_ref;TLBEntry38_ref;TLBEntry37_ref;TLBEntry36_ref;TLBEntry35_ref;TLBEntry34_ref;TLBEntry33_ref;TLBEntry32_ref;TLBEntry31_ref;TLBEntry30_ref;TLBEntry29_ref;TLBEntry28_ref;TLBEntry27_ref;TLBEntry26_ref;TLBEntry25_ref;TLBEntry24_ref;TLBEntry23_ref;TLBEntry22_ref; + TLBEntry21_ref;TLBEntry20_ref;TLBEntry19_ref;TLBEntry18_ref;TLBEntry17_ref;TLBEntry16_ref;TLBEntry15_ref;TLBEntry14_ref;TLBEntry13_ref;TLBEntry12_ref;TLBEntry11_ref;TLBEntry10_ref;TLBEntry09_ref;TLBEntry08_ref;TLBEntry07_ref;TLBEntry06_ref;TLBEntry05_ref;TLBEntry04_ref;TLBEntry03_ref;TLBEntry02_ref;TLBEntry01_ref; + TLBEntry00_ref]. +Hint Unfold TLBEntries : sail. +Definition undefined_StatusReg '(tt : unit) +: M (StatusReg) := + + (undefined_bitvector 32) >>= fun w__0 : mword 32 => + returnm (({| StatusReg_StatusReg_chunk_0 := w__0 |}) + : StatusReg). + +Definition Mk_StatusReg (v : mword 32) +: StatusReg := + + {| StatusReg_StatusReg_chunk_0 := (subrange_vec_dec v 31 0) |}. + +Definition _get_StatusReg_bits (v : StatusReg) +: mword 32 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 0. + +Definition _set_StatusReg_bits +(r_ref : register_ref regstate register_value StatusReg) (v : mword 32) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_bits (v : StatusReg) (x : mword 32) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}. + +Definition _get_StatusReg_CU (v : StatusReg) +: mword 4 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 28. + +Definition _set_StatusReg_CU (r_ref : register_ref regstate register_value StatusReg) (v : mword 4) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 31 28 (subrange_vec_dec v 3 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_CU (v : StatusReg) (x : mword 4) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 28 (subrange_vec_dec x 3 0)) ]}. + +Definition _get_StatusReg_BEV (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 22 22. + +Definition _set_StatusReg_BEV (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_BEV (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_StatusReg_IM (v : StatusReg) +: mword 8 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 15 8. + +Definition _set_StatusReg_IM (r_ref : register_ref regstate register_value StatusReg) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 15 8 (subrange_vec_dec v 7 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_IM (v : StatusReg) (x : mword 8) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 15 8 (subrange_vec_dec x 7 0)) ]}. + +Definition _get_StatusReg_KX (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 7 7. + +Definition _set_StatusReg_KX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_KX (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_StatusReg_SX (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 6 6. + +Definition _set_StatusReg_SX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_SX (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_StatusReg_UX (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 5 5. + +Definition _set_StatusReg_UX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_UX (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_StatusReg_KSU (v : StatusReg) +: mword 2 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 4 3. + +Definition _set_StatusReg_KSU (r_ref : register_ref regstate register_value StatusReg) (v : mword 2) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 4 3 (subrange_vec_dec v 1 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_KSU (v : StatusReg) (x : mword 2) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 4 3 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_StatusReg_ERL (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 2 2. + +Definition _set_StatusReg_ERL (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_ERL (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_StatusReg_EXL (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 1 1. + +Definition _set_StatusReg_EXL (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_EXL (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_StatusReg_IE (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 0 0. + +Definition _set_StatusReg_IE (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_IE (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition execute_branch_mips (pc : mword 64) +: M (unit) := + + write_reg DelayedPC_ref pc >> + write_reg BranchPending_ref (vec_of_bits [B1] : mword 1) >> + write_reg NextInBranchDelay_ref (vec_of_bits [B1] : mword 1) + : M (unit). + +Definition NotWordVal (word : mword 64) +: bool := + + neq_vec (zopz0zQzQ (cast_unit_vec (access_vec_dec word 31)) 32) (subrange_vec_dec word 63 32). + +Definition rGPR (idx : mword 5) +: M (mword 64) := + + let 'i := projT1 (uint idx) in + (if sumbool_of_bool ((Z.eqb i 0)) then + returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + : mword 64) + else + read_reg GPR_ref >>= fun w__0 : vec (bits 64) 32 => + returnm ((vec_access_dec w__0 i) + : mword 64)) + : M (mword 64). + +Definition wGPR (idx : mword 5) (v : mword 64) +: M (unit) := + + let 'i := projT1 (uint idx) in + (if ((neq_int i 0)) then + let '_ := + (if (trace) then + let '_ := (prerr (string_of_int i)) : unit in + prerr_bits " <- " v + else tt) + : unit in + read_reg GPR_ref >>= fun w__0 : vec (bits 64) 32 => + write_reg GPR_ref (vec_update_dec w__0 i v) + : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition MEMr (addr : mword 64) (size : Z) `{ArithFact (size >= 0)} +: M (mword (8 * size)) := + + (__MIPS_read addr size) + : M (mword (8 * size)). + +Definition MEMr_reserve (addr : mword 64) (size : Z) `{ArithFact (size >= 0)} +: M (mword (8 * size)) := + + (__MIPS_read addr size) + : M (mword (8 * size)). + +Definition MEM_sync '(tt : unit) : M (unit) := (skip tt) : M (unit). + +Definition MEMea (addr : mword 64) (size : Z) : M (unit) := (skip tt) : M (unit). + +Definition MEMea_conditional (addr : mword 64) (size : Z) : M (unit) := (skip tt) : M (unit). + +Definition MEMval (addr : mword 64) (size : Z) (data : mword (8 * size)) +: M (unit) := + + (__MIPS_write addr size data) + : M (unit). + +Definition MEMval_conditional (addr : mword 64) (size : Z) (data : mword (8 * size)) +: M (bool) := + + (__MIPS_write addr size data) >> returnm (true : bool). + +Definition Exception_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 18)} +: Exception := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Interrupt + else if sumbool_of_bool ((Z.eqb p0_ 1)) then TLBMod + else if sumbool_of_bool ((Z.eqb p0_ 2)) then TLBL + else if sumbool_of_bool ((Z.eqb p0_ 3)) then TLBS + else if sumbool_of_bool ((Z.eqb p0_ 4)) then AdEL + else if sumbool_of_bool ((Z.eqb p0_ 5)) then AdES + else if sumbool_of_bool ((Z.eqb p0_ 6)) then Sys + else if sumbool_of_bool ((Z.eqb p0_ 7)) then Bp + else if sumbool_of_bool ((Z.eqb p0_ 8)) then ResI + else if sumbool_of_bool ((Z.eqb p0_ 9)) then CpU + else if sumbool_of_bool ((Z.eqb p0_ 10)) then Ov + else if sumbool_of_bool ((Z.eqb p0_ 11)) then Tr + else if sumbool_of_bool ((Z.eqb p0_ 12)) then C2E + else if sumbool_of_bool ((Z.eqb p0_ 13)) then C2Trap + else if sumbool_of_bool ((Z.eqb p0_ 14)) then XTLBRefillL + else if sumbool_of_bool ((Z.eqb p0_ 15)) then XTLBRefillS + else if sumbool_of_bool ((Z.eqb p0_ 16)) then XTLBInvL + else if sumbool_of_bool ((Z.eqb p0_ 17)) then XTLBInvS + else MCheck. + +Definition num_of_Exception (arg_ : Exception) +: {e : Z & ArithFact (0 <= e /\ e <= 18)} := + + build_ex(match arg_ with + | Interrupt => 0 + | TLBMod => 1 + | TLBL => 2 + | TLBS => 3 + | AdEL => 4 + | AdES => 5 + | Sys => 6 + | Bp => 7 + | ResI => 8 + | CpU => 9 + | Ov => 10 + | Tr => 11 + | C2E => 12 + | C2Trap => 13 + | XTLBRefillL => 14 + | XTLBRefillS => 15 + | XTLBInvL => 16 + | XTLBInvS => 17 + | MCheck => 18 + end). + +Definition undefined_Exception '(tt : unit) +: M (Exception) := + + (internal_pick + [Interrupt;TLBMod;TLBL;TLBS;AdEL;AdES;Sys;Bp;ResI;CpU;Ov;Tr;C2E;C2Trap;XTLBRefillL;XTLBRefillS;XTLBInvL;XTLBInvS;MCheck]) + : M (Exception). + +Definition ExceptionCode (ex : Exception) +: mword 5 := + + let x : bits 8 := + match ex with + | Interrupt => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8) + | TLBMod => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : mword 8) + | TLBL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : mword 8) + | TLBS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : mword 8) + | AdEL => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : mword 8) + | AdES => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : mword 8) + | Sys => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : mword 8) + | Bp => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : mword 8) + | ResI => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0] : mword 8) + | CpU => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1] : mword 8) + | Ov => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B0] : mword 8) + | Tr => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B1] : mword 8) + | C2E => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : mword 8) + | C2Trap => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : mword 8) + | XTLBRefillL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : mword 8) + | XTLBRefillS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : mword 8) + | XTLBInvL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : mword 8) + | XTLBInvS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : mword 8) + | MCheck => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0] : mword 8) + end in + subrange_vec_dec x 4 0. + +Definition string_of_exception (ex : Exception) +: string := + + match ex with + | Interrupt => "Interrupt" + | TLBMod => "TLBMod" + | TLBL => "TLBL" + | TLBS => "TLBS" + | AdEL => "AdEL" + | AdES => "AdES" + | Sys => "Sys" + | Bp => "Bp " + | ResI => "ResI" + | CpU => "CpU" + | Ov => "Ov" + | Tr => "Tr" + | C2E => "C2E" + | C2Trap => "C2Trap" + | XTLBRefillL => "XTLBRefillL" + | XTLBRefillS => "XTLBRefillS" + | XTLBInvL => "XTLBInvL" + | XTLBInvS => "XTLBInvS" + | MCheck => "MCheck" + end. + +Definition SignalExceptionMIPS {o : Type} (ex : Exception) (kccBase : mword 64) +: M (o) := + + let '_ := + (if (trace) then + let '_ := (prerr " EXCEPTION ") : unit in + prerr_endline (string_of_exception ex) + else tt) + : unit in + read_reg CP0Status_ref >>= fun w__0 : StatusReg => + (if ((negb ((bits_to_bool (_get_StatusReg_EXL w__0)) : bool))) then + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__1 : bits 1 => + (if (((bit_to_bool (access_vec_dec w__1 0)) : bool)) then + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + write_reg CP0EPC_ref (sub_vec_int w__2 4) >> + (_set_CauseReg_BD CP0Cause_ref (vec_of_bits [B1] : mword 1)) + : M (unit) + else + ((read_reg PC_ref) : M (mword 64)) >>= fun w__3 : bits 64 => + write_reg CP0EPC_ref w__3 >> + (_set_CauseReg_BD CP0Cause_ref (vec_of_bits [B0] : mword 1)) + : M (unit)) + : M (unit) + else returnm (tt : unit)) >> + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__4 : bits 1 => + (if (((bit_to_bool (access_vec_dec w__4 0)) : bool)) then + ((read_reg LastInstrBits_ref) : M (mword 32)) >>= fun w__5 : bits 32 => + write_reg CP0BadInstrP_ref w__5 + : M (unit) + else returnm (tt : unit)) >> + ((read_reg CurrentInstrBits_ref) : M (mword 32)) >>= fun w__6 : bits 32 => + write_reg CP0BadInstr_ref w__6 >> + read_reg CP0Status_ref >>= fun w__7 : StatusReg => + let vectorOffset := + if (((bits_to_bool (_get_StatusReg_EXL w__7)) : bool)) then + (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((orb (generic_eq ex XTLBRefillL) (generic_eq ex XTLBRefillS))) then + (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq ex C2Trap)) then + (vec_of_bits [B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) in + read_reg CP0Status_ref >>= fun w__8 : StatusReg => + let vectorBase : bits 64 := + if (((bits_to_bool (_get_StatusReg_BEV w__8)) : bool)) then + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + else + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) in + write_reg NextPC_ref (sub_vec (add_vec vectorBase (mips_sign_extend 64 vectorOffset)) kccBase) >> + (_set_CauseReg_ExcCode CP0Cause_ref (ExceptionCode ex)) >> + (_set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1] : mword 1)) >> + (throw (ISAException + (tt))) + : M (o). + +Definition undefined_Capability '(tt : unit) +: M (Capability) := + + (undefined_bool tt) >>= fun w__0 : bool => + (undefined_bitvector 8) >>= fun w__1 : mword 8 => + (undefined_bitvector 24) >>= fun w__2 : mword 24 => + (undefined_bitvector 16) >>= fun w__3 : mword 16 => + (undefined_bitvector 3) >>= fun w__4 : mword 3 => + (undefined_bool tt) >>= fun w__5 : bool => + (undefined_bool tt) >>= fun w__6 : bool => + (undefined_bool tt) >>= fun w__7 : bool => + (undefined_bool tt) >>= fun w__8 : bool => + (undefined_bool tt) >>= fun w__9 : bool => + (undefined_bool tt) >>= fun w__10 : bool => + (undefined_bool tt) >>= fun w__11 : bool => + (undefined_bool tt) >>= fun w__12 : bool => + (undefined_bool tt) >>= fun w__13 : bool => + (undefined_bool tt) >>= fun w__14 : bool => + (undefined_bool tt) >>= fun w__15 : bool => + (undefined_bool tt) >>= fun w__16 : bool => + (undefined_bool tt) >>= fun w__17 : bool => + (undefined_bitvector 64) >>= fun w__18 : mword 64 => + (undefined_bitvector 64) >>= fun w__19 : mword 64 => + (undefined_bitvector 64) >>= fun w__20 : mword 64 => + returnm (({| Capability_tag := w__0; + Capability_padding := w__1; + Capability_otype := w__2; + Capability_uperms := w__3; + Capability_perm_reserved12_14 := w__4; + Capability_permit_set_CID := w__5; + Capability_access_system_regs := w__6; + Capability_permit_unseal := w__7; + Capability_permit_ccall := w__8; + Capability_permit_seal := w__9; + Capability_permit_store_local_cap := w__10; + Capability_permit_store_cap := w__11; + Capability_permit_load_cap := w__12; + Capability_permit_store := w__13; + Capability_permit_load := w__14; + Capability_permit_execute := w__15; + Capability_global := w__16; + Capability_sealed := w__17; + Capability_address := w__18; + Capability_base := w__19; + Capability_length := w__20 |}) + : Capability). + +Definition getCapBase (c : Capability) +: {rangevar : Z & ArithFact (0 <= rangevar /\ rangevar <= (2 ^ 64 - 1))} := + + build_ex(projT1 (uint c.(Capability_base))). + +Definition set_next_pcc (newPCC : Capability) +: M (unit) := + + write_reg NextPCC_ref newPCC >> write_reg DelayedPCC_ref newPCC : M (unit). + +Definition SignalException {o : Type} (ex : Exception) +: M (o) := + + read_reg CP0Status_ref >>= fun w__0 : StatusReg => + (if ((negb ((bits_to_bool (_get_StatusReg_EXL w__0)) : bool))) then + read_reg PCC_ref >>= fun w__1 : Capability => write_reg EPCC_ref w__1 : M (unit) + else returnm (tt : unit)) >> + read_reg KCC_ref >>= fun w__2 : Capability => + (set_next_pcc w__2) >> + read_reg KCC_ref >>= fun w__3 : Capability => + let 'base := projT1 (getCapBase w__3) in + (SignalExceptionMIPS ex (to_bits 64 base)) + : M (o). + +Definition SignalExceptionBadAddr {o : Type} (ex : Exception) (badAddr : mword 64) +: M (o) := + + write_reg CP0BadVAddr_ref badAddr >> (SignalException ex) : M (o). + +Definition SignalExceptionTLB {o : Type} (ex : Exception) (badAddr : mword 64) +: M (o) := + + write_reg CP0BadVAddr_ref badAddr >> + (_set_ContextReg_BadVPN2 TLBContext_ref (subrange_vec_dec badAddr 31 13)) >> + (_set_XContextReg_XBadVPN2 TLBXContext_ref (subrange_vec_dec badAddr 39 13)) >> + (_set_XContextReg_XR TLBXContext_ref (subrange_vec_dec badAddr 63 62)) >> + (_set_TLBEntryHiReg_R TLBEntryHi_ref (subrange_vec_dec badAddr 63 62)) >> + (_set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (subrange_vec_dec badAddr 39 13)) >> + (SignalException ex) + : M (o). + +Definition MemAccessType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: MemAccessType := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Instruction + else if sumbool_of_bool ((Z.eqb p0_ 1)) then LoadData + else StoreData. + +Definition num_of_MemAccessType (arg_ : MemAccessType) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with | Instruction => 0 | LoadData => 1 | StoreData => 2 end). + +Definition undefined_MemAccessType '(tt : unit) +: M (MemAccessType) := + + (internal_pick [Instruction;LoadData;StoreData]) + : M (MemAccessType). + +Definition AccessLevel_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: AccessLevel := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then User + else if sumbool_of_bool ((Z.eqb p0_ 1)) then Supervisor + else Kernel. + +Definition num_of_AccessLevel (arg_ : AccessLevel) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with | User => 0 | Supervisor => 1 | Kernel => 2 end). + +Definition undefined_AccessLevel '(tt : unit) +: M (AccessLevel) := + + (internal_pick [User;Supervisor;Kernel]) + : M (AccessLevel). + +Definition int_of_AccessLevel (level : AccessLevel) +: {n : Z & ArithFact (In n [0; 1; 2])} := + + build_ex(match level with | User => 0 | Supervisor => 1 | Kernel => 2 end). + +Definition grantsAccess (currentLevel : AccessLevel) (requiredLevel : AccessLevel) +: bool := + + Z.geb (projT1 (int_of_AccessLevel currentLevel)) (projT1 (int_of_AccessLevel requiredLevel)). + +Definition getAccessLevel '(tt : unit) +: M (AccessLevel) := + + (or_boolM + (read_reg CP0Status_ref >>= fun w__0 : StatusReg => + returnm ((bits_to_bool (_get_StatusReg_EXL w__0)) + : bool)) + (read_reg CP0Status_ref >>= fun w__1 : StatusReg => + returnm ((bits_to_bool (_get_StatusReg_ERL w__1)) + : bool))) >>= fun w__2 : bool => + (if (w__2) then returnm (Kernel : AccessLevel) + else + read_reg CP0Status_ref >>= fun w__3 : StatusReg => + let p__18 := _get_StatusReg_KSU w__3 in + let b__0 := p__18 in + returnm ((if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then Kernel + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then Supervisor + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then User + else User) + : AccessLevel)) + : M (AccessLevel). + +Definition checkCP0Access '(tt : unit) +: M (unit) := + + (getAccessLevel tt) >>= fun accessLevel => + (and_boolM (returnm ((generic_neq accessLevel Kernel) : bool)) + (read_reg CP0Status_ref >>= fun w__0 : StatusReg => + returnm ((negb ((bit_to_bool (access_vec_dec (_get_StatusReg_CU w__0) 0)) : bool)) + : bool))) >>= fun w__1 : bool => + (if (w__1) then + (_set_CauseReg_CE CP0Cause_ref (vec_of_bits [B0;B0] : mword 2)) >> + (SignalException CpU) + : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition incrementCP0Count '(tt : unit) +: M (unit) := + + ((read_reg TLBRandom_ref) : M (mword 6)) >>= fun w__0 : TLBIndexT => + ((read_reg TLBWired_ref) : M (mword 6)) >>= fun w__1 : TLBIndexT => + (if ((eq_vec w__0 w__1)) then returnm (TLBIndexMax : TLBIndexT) + else + ((read_reg TLBRandom_ref) : M (mword 6)) >>= fun w__2 : TLBIndexT => + returnm ((sub_vec_int w__2 1) + : mword 6)) >>= fun w__3 : mword 6 => + write_reg TLBRandom_ref w__3 >> + ((read_reg CP0Count_ref) : M (mword 32)) >>= fun w__4 : bits 32 => + write_reg CP0Count_ref (add_vec_int w__4 1) >> + ((read_reg CP0Count_ref) : M (mword 32)) >>= fun w__5 : bits 32 => + ((read_reg CP0Compare_ref) : M (mword 32)) >>= fun w__6 : bits 32 => + (if ((eq_vec w__5 w__6)) then + read_reg CP0Cause_ref >>= fun w__7 : CauseReg => + (_set_CauseReg_IP CP0Cause_ref + (or_vec (_get_CauseReg_IP w__7) (vec_of_bits [B1;B0;B0;B0;B0;B0;B0;B0] : mword 8))) + : M (unit) + else returnm (tt : unit)) >> + read_reg CP0Status_ref >>= fun w__8 : StatusReg => + let ims := _get_StatusReg_IM w__8 in + read_reg CP0Cause_ref >>= fun w__9 : CauseReg => + let ips := _get_CauseReg_IP w__9 in + read_reg CP0Status_ref >>= fun w__10 : StatusReg => + let ie := _get_StatusReg_IE w__10 in + read_reg CP0Status_ref >>= fun w__11 : StatusReg => + let exl := _get_StatusReg_EXL w__11 in + read_reg CP0Status_ref >>= fun w__12 : StatusReg => + let erl := _get_StatusReg_ERL w__12 in + (if ((andb (negb ((bits_to_bool exl) : bool)) + (andb (negb ((bits_to_bool erl) : bool)) + (andb ((bits_to_bool ie) : bool) + (neq_vec (and_vec ips ims) (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8)))))) + then + (SignalException Interrupt) + : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition decode_failure_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} +: decode_failure := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then no_matching_pattern + else if sumbool_of_bool ((Z.eqb p0_ 1)) then unsupported_instruction + else if sumbool_of_bool ((Z.eqb p0_ 2)) then illegal_instruction + else internal_error. + +Definition num_of_decode_failure (arg_ : decode_failure) +: {e : Z & ArithFact (0 <= e /\ e <= 3)} := + + build_ex(match arg_ with + | no_matching_pattern => 0 + | unsupported_instruction => 1 + | illegal_instruction => 2 + | internal_error => 3 + end). + +Definition undefined_decode_failure '(tt : unit) +: M (decode_failure) := + + (internal_pick [no_matching_pattern;unsupported_instruction;illegal_instruction;internal_error]) + : M (decode_failure). + +Definition Comparison_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 7)} +: Comparison := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then EQ' + else if sumbool_of_bool ((Z.eqb p0_ 1)) then NE + else if sumbool_of_bool ((Z.eqb p0_ 2)) then GE + else if sumbool_of_bool ((Z.eqb p0_ 3)) then GEU + else if sumbool_of_bool ((Z.eqb p0_ 4)) then GT' + else if sumbool_of_bool ((Z.eqb p0_ 5)) then LE + else if sumbool_of_bool ((Z.eqb p0_ 6)) then LT' + else LTU. + +Definition num_of_Comparison (arg_ : Comparison) +: {e : Z & ArithFact (0 <= e /\ e <= 7)} := + + build_ex(match arg_ with + | EQ' => 0 + | NE => 1 + | GE => 2 + | GEU => 3 + | GT' => 4 + | LE => 5 + | LT' => 6 + | LTU => 7 + end). + +Definition undefined_Comparison '(tt : unit) +: M (Comparison) := + + (internal_pick [EQ';NE;GE;GEU;GT';LE;LT';LTU]) + : M (Comparison). + +Definition compare (cmp : Comparison) (valA : mword 64) (valB : mword 64) +: bool := + + match cmp with + | EQ' => eq_vec valA valB + | NE => neq_vec valA valB + | GE => zopz0zKzJ_s valA valB + | GEU => zopz0zKzJ_u valA valB + | GT' => zopz0zI_s valB valA + | LE => zopz0zKzJ_s valB valA + | LT' => zopz0zI_s valA valB + | LTU => zopz0zI_u valA valB + end. + +Definition WordType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} +: WordType := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then B + else if sumbool_of_bool ((Z.eqb p0_ 1)) then H + else if sumbool_of_bool ((Z.eqb p0_ 2)) then W + else D. + +Definition num_of_WordType (arg_ : WordType) +: {e : Z & ArithFact (0 <= e /\ e <= 3)} := + + build_ex(match arg_ with | B => 0 | H => 1 | W => 2 | D => 3 end). + +Definition undefined_WordType '(tt : unit) +: M (WordType) := + + (internal_pick [B;H;W;D]) + : M (WordType). + +Definition WordTypeUnaligned_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} +: WordTypeUnaligned := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then WL + else if sumbool_of_bool ((Z.eqb p0_ 1)) then WR + else if sumbool_of_bool ((Z.eqb p0_ 2)) then DL + else DR. + +Definition num_of_WordTypeUnaligned (arg_ : WordTypeUnaligned) +: {e : Z & ArithFact (0 <= e /\ e <= 3)} := + + build_ex(match arg_ with | WL => 0 | WR => 1 | DL => 2 | DR => 3 end). + +Definition undefined_WordTypeUnaligned '(tt : unit) +: M (WordTypeUnaligned) := + + (internal_pick [WL;WR;DL;DR]) + : M (WordTypeUnaligned). + +Definition wordWidthBytes (w : WordType) +: {rangevar : Z & ArithFact (1 <= rangevar /\ rangevar <= 8)} := + + build_ex(match w with | B => 1 | H => 2 | W => 4 | D => 8 end). + +Definition alignment_width := 16. +Hint Unfold alignment_width : sail. +Definition isAddressAligned (addr : mword 64) (wordType : WordType) +: bool := + + let 'a := projT1 (uint addr) in + Z.eqb (projT1 (ediv_with_eq a alignment_width)) + (projT1 (ediv_with_eq (Z.sub (Z.add a (projT1 (wordWidthBytes wordType))) 1) alignment_width)). + +Definition extendLoad {sz : Z} (memResult : mword sz) (sign : bool) `{ArithFact (sz <= 64)} +: mword 64 := + + if (sign) then mips_sign_extend 64 memResult + else mips_zero_extend 64 memResult. + +Definition MEMr_wrapper (addr : mword 64) (size : Z) `{ArithFact (1 <= size /\ size <= 8)} +: M (mword (8 * size)) := + + (if ((eq_vec addr + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))) then + ((read_reg UART_RVALID_ref) : M (mword 1)) >>= fun rvalid => + write_reg UART_RVALID_ref (vec_of_bits [B0] : mword 1) >> + ((read_reg UART_RDATA_ref) : M (mword 8)) >>= fun w__0 : bits 8 => + returnm ((mask (Z.mul 8 size) + (concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) + (concat_vec w__0 + (concat_vec rvalid + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 16)))))) + : mword (8 * size)) + else if ((eq_vec addr + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0; + B0] + : mword 64))) then + returnm ((mask (Z.mul 8 size) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B1;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1] + : mword 64)) + : mword (8 * size)) + else + (MEMr addr size) >>= fun w__1 : mword (8 * size) => + returnm ((reverse_endianness w__1) + : mword (8 * size))) + : M (mword (8 * size)). + +Definition MEMr_reserve_wrapper (addr : mword 64) (size : Z) `{ArithFact (1 <= size /\ size <= 8)} +: M (mword (8 * size)) := + + (MEMr_reserve addr size) >>= fun w__0 : mword (8 * size) => + returnm ((reverse_endianness w__0) + : mword (8 * size)). + +Definition init_cp0_state '(tt : unit) +: M (unit) := + + (_set_StatusReg_BEV CP0Status_ref ((cast_unit_vec B1) : mword 1)) + : M (unit). + +Definition tlbEntryMatch (r : mword 2) (vpn2 : mword 27) (asid : mword 8) (entry : TLBEntry) +: bool := + + let entryValid := _get_TLBEntry_valid entry in + let entryR := _get_TLBEntry_r entry in + let entryMask := _get_TLBEntry_pagemask entry in + let entryVPN := _get_TLBEntry_vpn2 entry in + let entryASID := _get_TLBEntry_asid entry in + let entryG := _get_TLBEntry_g entry in + let vpnMask : bits 27 := not_vec (mips_zero_extend 27 entryMask) in + andb ((bits_to_bool entryValid) : bool) + (andb (eq_vec r entryR) + (andb (eq_vec (and_vec vpn2 vpnMask) (and_vec entryVPN vpnMask)) + (orb (eq_vec asid entryASID) ((bits_to_bool entryG) : bool)))). + +Definition tlbSearch (VAddr : mword 64) +: M (option (mword 6)) := + + catch_early_return + (let r := subrange_vec_dec VAddr 63 62 in + let vpn2 := subrange_vec_dec VAddr 39 13 in + liftR (read_reg TLBEntryHi_ref) >>= fun w__0 : TLBEntryHiReg => + let asid := _get_TLBEntryHiReg_ASID w__0 in + (foreach_ZM_up 0 63 1 tt + (fun idx _ unit_var => + liftR ((reg_deref (vec_access_dec TLBEntries idx))) >>= fun w__1 : TLBEntry => + (if ((tlbEntryMatch r vpn2 asid w__1)) then + (early_return ((Some + (to_bits 6 idx)) + : option (mword 6))) + : MR (unit) _ + else returnm (tt : unit)) + : MR (unit) _)) >> + returnm (None + : option (mword 6))). + +Definition TLBTranslate2 (vAddr : mword 64) (accessType : MemAccessType) +: M ((mword 64 * bool)) := + + (tlbSearch vAddr) >>= fun idx => + (match idx with + | Some (idx) => + let 'i := projT1 (uint idx) in + (reg_deref (vec_access_dec TLBEntries i)) >>= fun entry => + let entryMask := _get_TLBEntry_pagemask entry in + let b__0 := entryMask in + (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16))) + then + returnm (build_ex (12 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 16))) + then + returnm (build_ex (14 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (16 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (18 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (20 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (22 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (24 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (26 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (28 + : Z)) + else + (undefined_range 12 28) + : M ({rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})) >>= fun '(existT _ evenOddBit _ : {rangevar : Z & ArithFact (12 <= + rangevar /\ + rangevar <= 28)}) => + let isOdd := access_vec_dec vAddr evenOddBit in + let '(caps, capl, pfn, d, v) := + if (((bit_to_bool isOdd) : bool)) then + (_get_TLBEntry_caps1 entry, _get_TLBEntry_capl1 entry, _get_TLBEntry_pfn1 entry, _get_TLBEntry_d1 + entry, _get_TLBEntry_v1 + entry) + else + (_get_TLBEntry_caps0 entry, _get_TLBEntry_capl0 entry, _get_TLBEntry_pfn0 entry, _get_TLBEntry_d0 + entry, _get_TLBEntry_v0 + entry) in + (if ((negb ((bits_to_bool v) : bool))) then + (SignalExceptionTLB (if ((generic_eq accessType StoreData)) then XTLBInvS else XTLBInvL) + vAddr) + : M ((mword 64 * bool)) + else if ((andb (generic_eq accessType StoreData) (negb ((bits_to_bool d) : bool)))) then + (SignalExceptionTLB TLBMod vAddr) + : M ((mword 64 * bool)) + else + let res : bits 64 := + mips_zero_extend 64 + (concat_vec (subrange_vec_dec pfn 23 (Z.sub evenOddBit 12)) + (subrange_vec_dec vAddr (Z.sub evenOddBit 1) 0)) in + returnm (res, bits_to_bool (if ((generic_eq accessType StoreData)) then caps else capl))) + : M ((mword 64 * bool)) + | None => + (SignalExceptionTLB + (if ((generic_eq accessType StoreData)) then XTLBRefillS + else XTLBRefillL) vAddr) + : M ((mword 64 * bool)) + end) + : M ((mword 64 * bool)). + +Definition TLBTranslateC (vAddr : mword 64) (accessType : MemAccessType) +: M ((mword 64 * bool)) := + + (getAccessLevel tt) >>= fun currentAccessLevel => + let compat32 := + eq_vec (subrange_vec_dec vAddr 61 31) + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : mword (61 - 31 + 1)) in + let b__0 := subrange_vec_dec vAddr 63 62 in + let '(requiredLevel, addr) := + (if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword (63 - 62 + 1)))) then + match (compat32, subrange_vec_dec vAddr 30 29) with + | (true, b__1) => + if ((eq_vec b__1 (vec_of_bits [B1;B1] : mword (30 - 29 + 1)))) then + (Kernel, None + : option (bits 64)) + else if ((eq_vec b__1 (vec_of_bits [B1;B0] : mword (30 - 29 + 1)))) then + (Supervisor, None + : option (bits 64)) + else if ((eq_vec b__1 (vec_of_bits [B0;B1] : mword (30 - 29 + 1)))) then + (Kernel, Some + (concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (subrange_vec_dec vAddr 28 0)))) + else if ((eq_vec b__1 (vec_of_bits [B0;B0] : mword (30 - 29 + 1)))) then + (Kernel, Some + (concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (subrange_vec_dec vAddr 28 0)))) + else match (true, b__1) with | (g__16, g__17) => (Kernel, None : option (bits 64)) end + | (g__16, g__17) => (Kernel, None : option (bits 64)) + end + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword (63 - 62 + 1)))) then + (Kernel, Some + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (subrange_vec_dec vAddr 58 0))) + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword (63 - 62 + 1)))) then + (Supervisor, None + : option (bits 64)) + else (User, None : option (bits 64))) + : (AccessLevel * option (bits 64)) in + (if ((negb (grantsAccess currentAccessLevel requiredLevel))) then + (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL) vAddr) + : M ((mword 64 * bool)) + else + (match addr with + | Some (a) => returnm (a, false) + | None => + (if sumbool_of_bool ((andb (negb compat32) + (Z.gtb (projT1 (uint (subrange_vec_dec vAddr 61 0))) MAX_VA))) + then + (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL) + vAddr) + : M ((mword 64 * bool)) + else (TLBTranslate2 vAddr accessType) : M ((mword 64 * bool))) + : M ((mword 64 * bool)) + end) >>= fun '(pa, c) => + (if sumbool_of_bool ((Z.gtb (projT1 (uint pa)) MAX_PA)) then + (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL) vAddr) + : M ((mword 64 * bool)) + else returnm (pa, c)) + : M ((mword 64 * bool))) + : M ((mword 64 * bool)). + +Definition TLBTranslate (vAddr : mword 64) (accessType : MemAccessType) +: M (mword 64) := + + (TLBTranslateC vAddr accessType) >>= fun '(addr, c) => returnm (addr : mword 64). + +Definition CPtrCmpOp_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 7)} +: CPtrCmpOp := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then CEQ + else if sumbool_of_bool ((Z.eqb p0_ 1)) then CNE + else if sumbool_of_bool ((Z.eqb p0_ 2)) then CLT + else if sumbool_of_bool ((Z.eqb p0_ 3)) then CLE + else if sumbool_of_bool ((Z.eqb p0_ 4)) then CLTU + else if sumbool_of_bool ((Z.eqb p0_ 5)) then CLEU + else if sumbool_of_bool ((Z.eqb p0_ 6)) then CEXEQ + else CNEXEQ. + +Definition num_of_CPtrCmpOp (arg_ : CPtrCmpOp) +: {e : Z & ArithFact (0 <= e /\ e <= 7)} := + + build_ex(match arg_ with + | CEQ => 0 + | CNE => 1 + | CLT => 2 + | CLE => 3 + | CLTU => 4 + | CLEU => 5 + | CEXEQ => 6 + | CNEXEQ => 7 + end). + +Definition undefined_CPtrCmpOp '(tt : unit) +: M (CPtrCmpOp) := + + (internal_pick [CEQ;CNE;CLT;CLE;CLTU;CLEU;CEXEQ;CNEXEQ]) + : M (CPtrCmpOp). + +Definition ClearRegSet_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} +: ClearRegSet := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then GPLo + else if sumbool_of_bool ((Z.eqb p0_ 1)) then GPHi + else if sumbool_of_bool ((Z.eqb p0_ 2)) then CLo + else CHi. + +Definition num_of_ClearRegSet (arg_ : ClearRegSet) +: {e : Z & ArithFact (0 <= e /\ e <= 3)} := + + build_ex(match arg_ with | GPLo => 0 | GPHi => 1 | CLo => 2 | CHi => 3 end). + +Definition undefined_ClearRegSet '(tt : unit) +: M (ClearRegSet) := + + (internal_pick [GPLo;GPHi;CLo;CHi]) + : M (ClearRegSet). + +Definition max_otype := projT1 (MAX 24). +Hint Unfold max_otype : sail. +Definition null_cap : Capability := +{| Capability_tag := false; + Capability_padding := (zeros_implicit 8 tt); + Capability_otype := (zeros_implicit 24 tt); + Capability_uperms := (zeros_implicit 16 tt); + Capability_perm_reserved12_14 := (zeros_implicit 3 tt); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := (zeros_implicit 64 tt); + Capability_base := (zeros_implicit 64 tt); + Capability_length := + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1] + : mword 64) |}. +Hint Unfold null_cap : sail. +Definition default_cap : Capability := +{| Capability_tag := true; + Capability_padding := (zeros_implicit 8 tt); + Capability_otype := (zeros_implicit 24 tt); + Capability_uperms := (ones_implicit 16 tt); + Capability_perm_reserved12_14 := (zeros_implicit 3 tt); + Capability_permit_set_CID := true; + Capability_access_system_regs := true; + Capability_permit_unseal := true; + Capability_permit_ccall := true; + Capability_permit_seal := true; + Capability_permit_store_local_cap := true; + Capability_permit_store_cap := true; + Capability_permit_load_cap := true; + Capability_permit_store := true; + Capability_permit_load := true; + Capability_permit_execute := true; + Capability_global := true; + Capability_sealed := false; + Capability_address := (zeros_implicit 64 tt); + Capability_base := (zeros_implicit 64 tt); + Capability_length := + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1] + : mword 64) |}. +Hint Unfold default_cap : sail. +Definition capBitsToCapability (tag : bool) (capBits : mword 256) +: Capability := + + {| Capability_tag := tag; + Capability_padding := (subrange_vec_dec capBits 255 248); + Capability_otype := (subrange_vec_dec capBits 247 224); + Capability_uperms := (subrange_vec_dec capBits 223 208); + Capability_perm_reserved12_14 := (subrange_vec_dec capBits 207 205); + Capability_permit_set_CID := ((bit_to_bool (access_vec_dec capBits 204)) : bool); + Capability_access_system_regs := ((bit_to_bool (access_vec_dec capBits 203)) : bool); + Capability_permit_unseal := ((bit_to_bool (access_vec_dec capBits 202)) : bool); + Capability_permit_ccall := ((bit_to_bool (access_vec_dec capBits 201)) : bool); + Capability_permit_seal := ((bit_to_bool (access_vec_dec capBits 200)) : bool); + Capability_permit_store_local_cap := ((bit_to_bool (access_vec_dec capBits 199)) : bool); + Capability_permit_store_cap := ((bit_to_bool (access_vec_dec capBits 198)) : bool); + Capability_permit_load_cap := ((bit_to_bool (access_vec_dec capBits 197)) : bool); + Capability_permit_store := ((bit_to_bool (access_vec_dec capBits 196)) : bool); + Capability_permit_load := ((bit_to_bool (access_vec_dec capBits 195)) : bool); + Capability_permit_execute := ((bit_to_bool (access_vec_dec capBits 194)) : bool); + Capability_global := ((bit_to_bool (access_vec_dec capBits 193)) : bool); + Capability_sealed := ((bit_to_bool (access_vec_dec capBits 192)) : bool); + Capability_address := (subrange_vec_dec capBits 191 128); + Capability_base := (subrange_vec_dec capBits 127 64); + Capability_length := (subrange_vec_dec capBits 63 0) |}. + +Definition getCapPerms (cap : Capability) +: mword 31 := + + concat_vec cap.(Capability_uperms) + (concat_vec cap.(Capability_perm_reserved12_14) + (concat_vec (bool_to_bits cap.(Capability_permit_set_CID)) + (concat_vec (bool_to_bits cap.(Capability_access_system_regs)) + (concat_vec (bool_to_bits cap.(Capability_permit_unseal)) + (concat_vec (bool_to_bits cap.(Capability_permit_ccall)) + (concat_vec (bool_to_bits cap.(Capability_permit_seal)) + (concat_vec (bool_to_bits cap.(Capability_permit_store_local_cap)) + (concat_vec (bool_to_bits cap.(Capability_permit_store_cap)) + (concat_vec (bool_to_bits cap.(Capability_permit_load_cap)) + (concat_vec (bool_to_bits cap.(Capability_permit_store)) + (concat_vec (bool_to_bits cap.(Capability_permit_load)) + (concat_vec (bool_to_bits cap.(Capability_permit_execute)) + (bool_to_bits cap.(Capability_global)))))))))))))). + +Definition capToBits (cap : Capability) +: mword 256 := + + concat_vec cap.(Capability_padding) + (concat_vec cap.(Capability_otype) + (concat_vec (getCapPerms cap) + (concat_vec (bool_to_bits cap.(Capability_sealed)) + (concat_vec cap.(Capability_address) + (concat_vec cap.(Capability_base) cap.(Capability_length)))))). + +Definition null_cap_bits : CapBits := capToBits null_cap. +Hint Unfold null_cap_bits : sail. +Definition capToMemBits (cap : Capability) : mword 256 := xor_vec (capToBits cap) null_cap_bits. + +Definition memBitsToCapability (tag : bool) (b : mword 256) +: Capability := + + capBitsToCapability tag (xor_vec b null_cap_bits). + +Definition setCapPerms (cap : Capability) (perms : mword 31) +: Capability := + + {| Capability_tag := cap.(Capability_tag); + Capability_padding := cap.(Capability_padding); + Capability_otype := cap.(Capability_otype); + Capability_uperms := (subrange_vec_dec perms 30 15); + Capability_perm_reserved12_14 := cap.(Capability_perm_reserved12_14); + Capability_permit_set_CID := ((bit_to_bool (access_vec_dec perms 11)) : bool); + Capability_access_system_regs := ((bit_to_bool (access_vec_dec perms 10)) : bool); + Capability_permit_unseal := ((bit_to_bool (access_vec_dec perms 9)) : bool); + Capability_permit_ccall := ((bit_to_bool (access_vec_dec perms 8)) : bool); + Capability_permit_seal := ((bit_to_bool (access_vec_dec perms 7)) : bool); + Capability_permit_store_local_cap := ((bit_to_bool (access_vec_dec perms 6)) : bool); + Capability_permit_store_cap := ((bit_to_bool (access_vec_dec perms 5)) : bool); + Capability_permit_load_cap := ((bit_to_bool (access_vec_dec perms 4)) : bool); + Capability_permit_store := ((bit_to_bool (access_vec_dec perms 3)) : bool); + Capability_permit_load := ((bit_to_bool (access_vec_dec perms 2)) : bool); + Capability_permit_execute := ((bit_to_bool (access_vec_dec perms 1)) : bool); + Capability_global := ((bit_to_bool (access_vec_dec perms 0)) : bool); + Capability_sealed := cap.(Capability_sealed); + Capability_address := cap.(Capability_address); + Capability_base := cap.(Capability_base); + Capability_length := cap.(Capability_length) |}. + +Definition sealCap (cap : Capability) (otype : mword 24) +: (bool * Capability) := + + (true, {| Capability_tag := cap.(Capability_tag); + Capability_padding := cap.(Capability_padding); + Capability_otype := otype; + Capability_uperms := cap.(Capability_uperms); + Capability_perm_reserved12_14 := cap.(Capability_perm_reserved12_14); + Capability_permit_set_CID := cap.(Capability_permit_set_CID); + Capability_access_system_regs := cap.(Capability_access_system_regs); + Capability_permit_unseal := cap.(Capability_permit_unseal); + Capability_permit_ccall := cap.(Capability_permit_ccall); + Capability_permit_seal := cap.(Capability_permit_seal); + Capability_permit_store_local_cap := cap.(Capability_permit_store_local_cap); + Capability_permit_store_cap := cap.(Capability_permit_store_cap); + Capability_permit_load_cap := cap.(Capability_permit_load_cap); + Capability_permit_store := cap.(Capability_permit_store); + Capability_permit_load := cap.(Capability_permit_load); + Capability_permit_execute := cap.(Capability_permit_execute); + Capability_global := cap.(Capability_global); + Capability_sealed := true; + Capability_address := cap.(Capability_address); + Capability_base := cap.(Capability_base); + Capability_length := cap.(Capability_length) |}). + +Definition getCapTop (c : Capability) +: {rangevar : Z & ArithFact (0 <= rangevar /\ rangevar <= (2 ^ 65))} := + + build_ex(Z.add (projT1 (uint c.(Capability_base))) (projT1 (uint c.(Capability_length)))). + +Definition getCapBounds (c : Capability) +: +({rangevar : Z & ArithFact (0 <= rangevar /\ rangevar <= (2 ^ 64 - 1))} * {rangevar : Z & ArithFact (0 <= + rangevar /\ + rangevar <= (2 ^ 65))}) := + + (build_ex (projT1 (getCapBase c)), build_ex (projT1 (getCapTop c))). + +Definition getCapOffset (c : Capability) +: {rangevar : Z & ArithFact (0 <= rangevar /\ rangevar <= (2 ^ 64 - 1))} := + + build_ex(projT1 (emod_with_eq + (Z.sub (projT1 (uint c.(Capability_address))) + (projT1 (uint c.(Capability_base)))) (projT1 (pow2 64)))). + +Definition getCapLength (c : Capability) +: {rangevar : Z & ArithFact (0 <= rangevar /\ rangevar <= (2 ^ 65))} := + + build_ex(projT1 (uint c.(Capability_length))). + +Definition getCapCursor (c : Capability) +: {rangevar : Z & ArithFact (0 <= rangevar /\ rangevar <= (2 ^ 64 - 1))} := + + build_ex(projT1 (uint c.(Capability_address))). + +Definition setCapOffset (c : Capability) (offset : mword 64) +: (bool * Capability) := + + (true, {[ c with Capability_address := (add_vec c.(Capability_base) offset) ]}). + +Definition incCapOffset (c : Capability) (delta : mword 64) +: (bool * Capability) := + + let newAddr : bits 64 := add_vec c.(Capability_address) delta in + (true, {[ c with Capability_address := newAddr ]}). + +Definition setCapBounds (cap : Capability) (base : mword 64) (top : mword 65) +: (bool * Capability) := + + let length : bits 65 := sub_vec top (concat_vec (vec_of_bits [B0] : mword 1) base) in + (true, {| Capability_tag := cap.(Capability_tag); + Capability_padding := cap.(Capability_padding); + Capability_otype := cap.(Capability_otype); + Capability_uperms := cap.(Capability_uperms); + Capability_perm_reserved12_14 := cap.(Capability_perm_reserved12_14); + Capability_permit_set_CID := cap.(Capability_permit_set_CID); + Capability_access_system_regs := cap.(Capability_access_system_regs); + Capability_permit_unseal := cap.(Capability_permit_unseal); + Capability_permit_ccall := cap.(Capability_permit_ccall); + Capability_permit_seal := cap.(Capability_permit_seal); + Capability_permit_store_local_cap := cap.(Capability_permit_store_local_cap); + Capability_permit_store_cap := cap.(Capability_permit_store_cap); + Capability_permit_load_cap := cap.(Capability_permit_load_cap); + Capability_permit_store := cap.(Capability_permit_store); + Capability_permit_load := cap.(Capability_permit_load); + Capability_permit_execute := cap.(Capability_permit_execute); + Capability_global := cap.(Capability_global); + Capability_sealed := cap.(Capability_sealed); + Capability_address := base; + Capability_base := base; + Capability_length := (subrange_vec_dec length 63 0) |}). + +Definition int_to_cap (address : mword 64) +: Capability := + + {[ null_cap with Capability_address := address ]}. + +Definition CapRegs : vec (register_ref regstate register_value Capability) 32 := +vec_of_list_len [C31_ref;C30_ref;C29_ref;C28_ref;C27_ref;C26_ref;C25_ref;C24_ref;C23_ref;C22_ref;C21_ref;C20_ref;C19_ref;C18_ref;C17_ref;C16_ref;C15_ref;C14_ref;C13_ref;C12_ref;C11_ref; + C10_ref;C09_ref;C08_ref;C07_ref;C06_ref;C05_ref;C04_ref;C03_ref;C02_ref;C01_ref;DDC_ref]. +Hint Unfold CapRegs : sail. +Definition have_cp2 := true. +Hint Unfold have_cp2 : sail. +Definition readCapReg (n : mword 5) +: M (Capability) := + + (if ((eq_vec n (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))) then returnm (null_cap : Capability) + else + let 'i := projT1 (uint n) in + (reg_deref (vec_access_dec CapRegs i)) + : M (Capability)) + : M (Capability). + +Definition readCapRegDDC (n : mword 5) +: M (Capability) := + + let 'i := projT1 (uint n) in + (reg_deref (vec_access_dec CapRegs i)) + : M (Capability). + +Definition capToString (cap : Capability) (fixlen : bool) +: M (string) := + + (skip tt) >> + let 'len := projT1 (getCapLength cap) in + let len_str := + if (fixlen) then string_of_bits (to_bits 64 (projT1 (min_atom len (projT1 (MAX 64))))) + else string_of_bits (to_bits 68 len) in + let otype24 : bits 24 := + if sumbool_of_bool ((Z.eqb (projT1 (sint cap.(Capability_otype))) (-1))) then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24) + else mips_zero_extend 24 cap.(Capability_otype) in + returnm ((String.append " t:" + (String.append (if (cap.(Capability_tag)) then "1" else "0") + (String.append " s:" + (String.append (if (cap.(Capability_sealed)) then "1" else "0") + (String.append " perms:" + (String.append + (string_of_bits + (concat_vec (vec_of_bits [B0] : mword 1) (getCapPerms cap))) + (String.append " type:" + (String.append (string_of_bits otype24) + (String.append " offset:" + (String.append + (string_of_bits (to_bits 64 (projT1 (getCapOffset cap)))) + (String.append " base:" + (String.append + (string_of_bits + (to_bits 64 (projT1 (getCapBase cap)))) + (String.append " length:" len_str))))))))))))) + : string). + +Definition writeCapReg (n : mword 5) (cap : Capability) +: M (unit) := + + (if ((eq_vec n (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))) then returnm (tt : unit) + else + let 'i := projT1 (uint n) in + (if (trace) then + let '_ := (prerr (string_of_int i)) : unit in + let '_ := (prerr " <- ") : unit in + (capToString cap false) >>= fun w__0 : string => + let '_ := (prerr_endline w__0) : unit in + let cap2 := capBitsToCapability cap.(Capability_tag) (capToBits cap) in + (if ((generic_neq cap cap2)) then + let '_ := (prerr_endline "Wrote non-normal cap:") : unit in + (capToString cap false) >>= fun w__1 : string => + let '_ := (prerr_endline w__1) : unit in + (capToString cap2 false) >>= fun w__2 : string => + let '_ := (prerr_endline w__2) : unit in + (assert_exp false "wrote non-normal capability") + : M (unit) + else returnm (tt : unit)) + : M (unit) + else (skip tt) : M (unit)) >> + write_reg (vec_access_dec CapRegs i) cap + : M (unit)) + : M (unit). + +Definition CapEx_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 23)} +: CapEx := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then CapEx_None + else if sumbool_of_bool ((Z.eqb p0_ 1)) then CapEx_LengthViolation + else if sumbool_of_bool ((Z.eqb p0_ 2)) then CapEx_TagViolation + else if sumbool_of_bool ((Z.eqb p0_ 3)) then CapEx_SealViolation + else if sumbool_of_bool ((Z.eqb p0_ 4)) then CapEx_TypeViolation + else if sumbool_of_bool ((Z.eqb p0_ 5)) then CapEx_CallTrap + else if sumbool_of_bool ((Z.eqb p0_ 6)) then CapEx_ReturnTrap + else if sumbool_of_bool ((Z.eqb p0_ 7)) then CapEx_TSSUnderFlow + else if sumbool_of_bool ((Z.eqb p0_ 8)) then CapEx_UserDefViolation + else if sumbool_of_bool ((Z.eqb p0_ 9)) then CapEx_TLBNoStoreCap + else if sumbool_of_bool ((Z.eqb p0_ 10)) then CapEx_InexactBounds + else if sumbool_of_bool ((Z.eqb p0_ 11)) then CapEx_GlobalViolation + else if sumbool_of_bool ((Z.eqb p0_ 12)) then CapEx_PermitExecuteViolation + else if sumbool_of_bool ((Z.eqb p0_ 13)) then CapEx_PermitLoadViolation + else if sumbool_of_bool ((Z.eqb p0_ 14)) then CapEx_PermitStoreViolation + else if sumbool_of_bool ((Z.eqb p0_ 15)) then CapEx_PermitLoadCapViolation + else if sumbool_of_bool ((Z.eqb p0_ 16)) then CapEx_PermitStoreCapViolation + else if sumbool_of_bool ((Z.eqb p0_ 17)) then CapEx_PermitStoreLocalCapViolation + else if sumbool_of_bool ((Z.eqb p0_ 18)) then CapEx_PermitSealViolation + else if sumbool_of_bool ((Z.eqb p0_ 19)) then CapEx_AccessSystemRegsViolation + else if sumbool_of_bool ((Z.eqb p0_ 20)) then CapEx_PermitCCallViolation + else if sumbool_of_bool ((Z.eqb p0_ 21)) then CapEx_AccessCCallIDCViolation + else if sumbool_of_bool ((Z.eqb p0_ 22)) then CapEx_PermitUnsealViolation + else CapEx_PermitSetCIDViolation. + +Definition num_of_CapEx (arg_ : CapEx) +: {e : Z & ArithFact (0 <= e /\ e <= 23)} := + + build_ex(match arg_ with + | CapEx_None => 0 + | CapEx_LengthViolation => 1 + | CapEx_TagViolation => 2 + | CapEx_SealViolation => 3 + | CapEx_TypeViolation => 4 + | CapEx_CallTrap => 5 + | CapEx_ReturnTrap => 6 + | CapEx_TSSUnderFlow => 7 + | CapEx_UserDefViolation => 8 + | CapEx_TLBNoStoreCap => 9 + | CapEx_InexactBounds => 10 + | CapEx_GlobalViolation => 11 + | CapEx_PermitExecuteViolation => 12 + | CapEx_PermitLoadViolation => 13 + | CapEx_PermitStoreViolation => 14 + | CapEx_PermitLoadCapViolation => 15 + | CapEx_PermitStoreCapViolation => 16 + | CapEx_PermitStoreLocalCapViolation => 17 + | CapEx_PermitSealViolation => 18 + | CapEx_AccessSystemRegsViolation => 19 + | CapEx_PermitCCallViolation => 20 + | CapEx_AccessCCallIDCViolation => 21 + | CapEx_PermitUnsealViolation => 22 + | CapEx_PermitSetCIDViolation => 23 + end). + +Definition undefined_CapEx '(tt : unit) +: M (CapEx) := + + (internal_pick + [CapEx_None;CapEx_LengthViolation;CapEx_TagViolation;CapEx_SealViolation;CapEx_TypeViolation;CapEx_CallTrap;CapEx_ReturnTrap;CapEx_TSSUnderFlow;CapEx_UserDefViolation;CapEx_TLBNoStoreCap;CapEx_InexactBounds;CapEx_GlobalViolation;CapEx_PermitExecuteViolation;CapEx_PermitLoadViolation;CapEx_PermitStoreViolation;CapEx_PermitLoadCapViolation;CapEx_PermitStoreCapViolation;CapEx_PermitStoreLocalCapViolation;CapEx_PermitSealViolation;CapEx_AccessSystemRegsViolation;CapEx_PermitCCallViolation;CapEx_AccessCCallIDCViolation;CapEx_PermitUnsealViolation;CapEx_PermitSetCIDViolation]) + : M (CapEx). + +Definition CapExCode (ex : CapEx) +: mword 8 := + + match ex with + | CapEx_None => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8) + | CapEx_LengthViolation => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : mword 8) + | CapEx_TagViolation => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : mword 8) + | CapEx_SealViolation => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : mword 8) + | CapEx_TypeViolation => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : mword 8) + | CapEx_CallTrap => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : mword 8) + | CapEx_ReturnTrap => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B0] : mword 8) + | CapEx_TSSUnderFlow => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1] : mword 8) + | CapEx_UserDefViolation => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : mword 8) + | CapEx_TLBNoStoreCap => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : mword 8) + | CapEx_InexactBounds => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0] : mword 8) + | CapEx_GlobalViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0] : mword 8) + | CapEx_PermitExecuteViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B1] : mword 8) + | CapEx_PermitLoadViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : mword 8) + | CapEx_PermitStoreViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B1] : mword 8) + | CapEx_PermitLoadCapViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0] : mword 8) + | CapEx_PermitStoreCapViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B1] : mword 8) + | CapEx_PermitStoreLocalCapViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B0] : mword 8) + | CapEx_PermitSealViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B1] : mword 8) + | CapEx_AccessSystemRegsViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0] : mword 8) + | CapEx_PermitCCallViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B1] : mword 8) + | CapEx_AccessCCallIDCViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B1;B0] : mword 8) + | CapEx_PermitUnsealViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B1;B1] : mword 8) + | CapEx_PermitSetCIDViolation => (vec_of_bits [B0;B0;B0;B1;B1;B1;B0;B0] : mword 8) + end. + +Definition string_of_capex (ex : CapEx) +: string := + + match ex with + | CapEx_None => "None" + | CapEx_LengthViolation => "LengthViolation" + | CapEx_TagViolation => "TagViolation" + | CapEx_SealViolation => "SealViolation" + | CapEx_TypeViolation => "TypeViolation" + | CapEx_CallTrap => "CallTrap" + | CapEx_ReturnTrap => "ReturnTrap" + | CapEx_TSSUnderFlow => "TSSUnderFlow" + | CapEx_UserDefViolation => "UserDefViolation" + | CapEx_TLBNoStoreCap => "TLBNoStoreCap" + | CapEx_InexactBounds => "InexactBounds" + | CapEx_GlobalViolation => "GlobalViolation" + | CapEx_PermitExecuteViolation => "PermitExecuteViolation" + | CapEx_PermitLoadViolation => "PermitLoadViolation" + | CapEx_PermitStoreViolation => "PermitStoreViolation" + | CapEx_PermitLoadCapViolation => "PermitLoadCapViolation" + | CapEx_PermitStoreCapViolation => "PermitStoreCapViolation" + | CapEx_PermitStoreLocalCapViolation => "PermitStoreLocalCapViolation" + | CapEx_PermitSealViolation => "PermitSealViolation" + | CapEx_AccessSystemRegsViolation => "AccessSystemRegsViolation" + | CapEx_PermitCCallViolation => "PermitCCallViolation" + | CapEx_AccessCCallIDCViolation => "AccessCCallIDCViolation" + | CapEx_PermitUnsealViolation => "PermitUnsealViolation" + | CapEx_PermitSetCIDViolation => "PermitSetCIDViolation" + end. + +Definition undefined_CapCauseReg '(tt : unit) +: M (CapCauseReg) := + + (undefined_bitvector 16) >>= fun w__0 : mword 16 => + returnm (({| CapCauseReg_CapCauseReg_chunk_0 := w__0 |}) + : CapCauseReg). + +Definition Mk_CapCauseReg (v : mword 16) +: CapCauseReg := + + {| CapCauseReg_CapCauseReg_chunk_0 := (subrange_vec_dec v 15 0) |}. + +Definition _get_CapCauseReg_bits (v : CapCauseReg) +: mword 16 := + + subrange_vec_dec v.(CapCauseReg_CapCauseReg_chunk_0) 15 0. + +Definition _set_CapCauseReg_bits +(r_ref : register_ref regstate register_value CapCauseReg) (v : mword 16) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CapCauseReg_CapCauseReg_chunk_0 := + (update_subrange_vec_dec r.(CapCauseReg_CapCauseReg_chunk_0) 15 0 (subrange_vec_dec v 15 0)) ]} + : CapCauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CapCauseReg_bits (v : CapCauseReg) (x : mword 16) +: CapCauseReg := + + {[ v with + CapCauseReg_CapCauseReg_chunk_0 := + (update_subrange_vec_dec v.(CapCauseReg_CapCauseReg_chunk_0) 15 0 (subrange_vec_dec x 15 0)) ]}. + +Definition _get_CapCauseReg_ExcCode (v : CapCauseReg) +: mword 8 := + + subrange_vec_dec v.(CapCauseReg_CapCauseReg_chunk_0) 15 8. + +Definition _set_CapCauseReg_ExcCode +(r_ref : register_ref regstate register_value CapCauseReg) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CapCauseReg_CapCauseReg_chunk_0 := + (update_subrange_vec_dec r.(CapCauseReg_CapCauseReg_chunk_0) 15 8 (subrange_vec_dec v 7 0)) ]} + : CapCauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CapCauseReg_ExcCode (v : CapCauseReg) (x : mword 8) +: CapCauseReg := + + {[ v with + CapCauseReg_CapCauseReg_chunk_0 := + (update_subrange_vec_dec v.(CapCauseReg_CapCauseReg_chunk_0) 15 8 (subrange_vec_dec x 7 0)) ]}. + +Definition _get_CapCauseReg_RegNum (v : CapCauseReg) +: mword 8 := + + subrange_vec_dec v.(CapCauseReg_CapCauseReg_chunk_0) 7 0. + +Definition _set_CapCauseReg_RegNum +(r_ref : register_ref regstate register_value CapCauseReg) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CapCauseReg_CapCauseReg_chunk_0 := + (update_subrange_vec_dec r.(CapCauseReg_CapCauseReg_chunk_0) 7 0 (subrange_vec_dec v 7 0)) ]} + : CapCauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CapCauseReg_RegNum (v : CapCauseReg) (x : mword 8) +: CapCauseReg := + + {[ v with + CapCauseReg_CapCauseReg_chunk_0 := + (update_subrange_vec_dec v.(CapCauseReg_CapCauseReg_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}. + +Definition execute_branch_pcc (newPCC : Capability) +: M (unit) := + + write_reg DelayedPC_ref (to_bits 64 (projT1 (getCapOffset newPCC))) >> + write_reg DelayedPCC_ref newPCC >> + write_reg BranchPending_ref (vec_of_bits [B1] : mword 1) >> + write_reg NextInBranchDelay_ref (vec_of_bits [B1] : mword 1) + : M (unit). + +Definition ERETHook '(tt : unit) +: M (unit) := + + read_reg EPCC_ref >>= fun w__0 : Capability => (set_next_pcc w__0) : M (unit). + +Definition raise_c2_exception8 {o : Type} (capEx : CapEx) (regnum : mword 8) +: M (o) := + + let '_ := + (if (trace) then + let '_ := (prerr " C2Ex ") : unit in + let '_ := (prerr (string_of_capex capEx)) : unit in + let '_ := (prerr " reg: ") : unit in + prerr_endline (string_of_bits regnum) + else tt) + : unit in + (_set_CapCauseReg_ExcCode CapCause_ref (CapExCode capEx)) >> + (_set_CapCauseReg_RegNum CapCause_ref regnum) >> + let mipsEx := + if ((orb (generic_eq capEx CapEx_CallTrap) (generic_eq capEx CapEx_ReturnTrap))) then C2Trap + else C2E in + (SignalException mipsEx) + : M (o). + +Definition raise_c2_exception {o : Type} (capEx : CapEx) (regnum : mword 5) +: M (o) := + + let reg8 := concat_vec (vec_of_bits [B0;B0;B0] : mword 3) regnum in + (raise_c2_exception8 capEx reg8) + : M (o). + +Definition raise_c2_exception_noreg {o : Type} (capEx : CapEx) +: M (o) := + + (raise_c2_exception8 capEx (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1] : mword 8)) + : M (o). + +Definition pcc_access_system_regs '(tt : unit) +: M (bool) := + + read_reg PCC_ref >>= fun w__0 : Capability => + returnm (w__0.(Capability_access_system_regs) + : bool). + +Definition MEMr_tagged (addr : mword 64) +: M ((bool * mword (32 * 8))) := + + assert_exp' (Z.eqb (projT1 (emod_with_eq (projT1 (uint addr)) cap_size)) 0) "file ""cheri_prelude_common.sail"", line 357, character 40 to line 357, character 40: ((unsigned(addr) % cap_size) == 0)" >>= fun _ => + (read_tag_bool addr) >>= fun tag => + (MEMr addr cap_size) >>= fun data => returnm (tag, reverse_endianness data). + +Definition MEMr_tagged_reserve (addr : mword 64) +: M ((bool * mword (32 * 8))) := + + assert_exp' (Z.eqb (projT1 (emod_with_eq (projT1 (uint addr)) cap_size)) 0) "file ""cheri_prelude_common.sail"", line 370, character 40 to line 370, character 40: ((unsigned(addr) % cap_size) == 0)" >>= fun _ => + (read_tag_bool addr) >>= fun tag => + (MEMr_reserve addr cap_size) >>= fun data => returnm (tag, reverse_endianness data). + +Definition MEMw_tagged (addr : mword 64) (tag : bool) (data : mword (32 * 8)) +: M (unit) := + + assert_exp' (Z.eqb (projT1 (emod_with_eq (projT1 (uint addr)) cap_size)) 0) "file ""cheri_prelude_common.sail"", line 383, character 40 to line 383, character 40: ((unsigned(addr) % cap_size) == 0)" >>= fun _ => + (MEMea addr cap_size) >> + (MEMval addr cap_size (reverse_endianness data)) >> (write_tag_bool addr tag) : M (unit). + +Definition MEMw_tagged_conditional (addr : mword 64) (tag : bool) (data : mword (32 * 8)) +: M (bool) := + + assert_exp' (Z.eqb (projT1 (emod_with_eq (projT1 (uint addr)) cap_size)) 0) "file ""cheri_prelude_common.sail"", line 396, character 40 to line 396, character 40: ((unsigned(addr) % cap_size) == 0)" >>= fun _ => + (MEMea_conditional addr cap_size) >> + (MEMval_conditional addr cap_size (reverse_endianness data)) >>= fun success => + (if (success) then (write_tag_bool addr tag) : M (unit) + else returnm (tt : unit)) >> + returnm (success + : bool). + +Definition cap_addr_mask := to_bits 64 (Z.sub (projT1 (pow2 64)) cap_size). +Hint Unfold cap_addr_mask : sail. +Definition MEMw_wrapper (addr : mword 64) (size : Z) (data : mword (8 * size)) +`{ArithFact (size >= 1)} +: M (unit) := + + let ledata := reverse_endianness data in + (if ((eq_vec addr + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))) then + write_reg UART_WDATA_ref (subrange_vec_dec ledata 7 0) >> + write_reg UART_WRITTEN_ref (vec_of_bits [B1] : mword 1) + : M (unit) + else + assert_exp' (eq_vec (and_vec addr cap_addr_mask) + (and_vec (add_vec addr (to_bits 64 (Z.sub size 1))) cap_addr_mask)) "file ""cheri_prelude_common.sail"", line 420, character 86 to line 420, character 86: ((addr & cap_addr_mask) == ((addr + to_bits(64, (size - 1))) & cap_addr_mask))" >>= fun _ => + (MEMea addr size) >> + (MEMval addr size ledata) >> (write_tag_bool (and_vec addr cap_addr_mask) false) : M (unit)) + : M (unit). + +Definition MEMw_conditional_wrapper (addr : mword 64) (size : Z) (data : mword (8 * size)) +`{ArithFact (size >= 1)} +: M (bool) := + + assert_exp' (eq_vec (and_vec addr cap_addr_mask) + (and_vec (add_vec addr (to_bits 64 (Z.sub size 1))) cap_addr_mask)) "file ""cheri_prelude_common.sail"", line 434, character 86 to line 434, character 86: ((addr & cap_addr_mask) == ((addr + to_bits(64, (size - 1))) & cap_addr_mask))" >>= fun _ => + (MEMea_conditional addr size) >> + (MEMval_conditional addr size (reverse_endianness data)) >>= fun success => + (if (success) then (write_tag_bool (and_vec addr cap_addr_mask) false) : M (unit) + else returnm (tt : unit)) >> + returnm (success + : bool). + +Definition checkDDCPerms (ddc : Capability) (accessType : MemAccessType) +: M (unit) := + + (if ((negb ddc.(Capability_tag))) then + (raise_c2_exception CapEx_TagViolation (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + : M (unit) + else if (ddc.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + : M (unit) + else returnm (tt : unit)) >> + (match accessType with + | Instruction => + (assert_exp false "file ""cheri_prelude_common.sail"", line 451, character 35 to line 451, character 35: false") + : M (unit) + | LoadData => + (if ((negb ddc.(Capability_permit_load))) then + (raise_c2_exception CapEx_PermitLoadViolation (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + : M (unit) + else returnm (tt : unit)) + : M (unit) + | StoreData => + (if ((negb ddc.(Capability_permit_store))) then + (raise_c2_exception CapEx_PermitStoreViolation (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + : M (unit) + else returnm (tt : unit)) + : M (unit) + end) + : M (unit). + +Definition addrWrapper (addr : mword 64) (accessType : MemAccessType) (width : WordType) +: M (mword 64) := + + read_reg DDC_ref >>= fun ddc => + (checkDDCPerms ddc accessType) >> + let 'cursor := projT1 (getCapCursor ddc) in + let 'vAddr := projT1 (emod_with_eq (Z.add cursor (projT1 (uint addr))) (projT1 (pow2 64))) in + let 'size := projT1 (wordWidthBytes width) in + let '(existT _ base _, existT _ top _) := getCapBounds ddc in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr size) top)) then + (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + : M (mword 64) + else if sumbool_of_bool ((Z.ltb vAddr base)) then + (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + : M (mword 64) + else returnm ((to_bits 64 vAddr) : mword 64)) + : M (mword 64). + +Definition addrWrapperUnaligned +(addr : mword 64) (accessType : MemAccessType) (width : WordTypeUnaligned) +: M (mword 64) := + + read_reg DDC_ref >>= fun ddc => + (checkDDCPerms ddc accessType) >> + let 'cursor := projT1 (getCapCursor ddc) in + let 'vAddr := projT1 (emod_with_eq (Z.add cursor (projT1 (uint addr))) (projT1 (pow2 64))) in + let 'woffset := projT1 (emod_with_eq vAddr 4) in + let 'doffset := projT1 (emod_with_eq vAddr 8) in + let '(waddr, size) := + (match width with + | WL => (vAddr, Z.sub 4 woffset) + | WR => (Z.sub vAddr woffset, Z.add woffset 1) + | DL => (vAddr, Z.sub 8 doffset) + | DR => (Z.sub vAddr doffset, Z.add doffset 1) + end) + : (Z * Z) in + let '(existT _ base _, existT _ top _) := getCapBounds ddc in + (if sumbool_of_bool ((Z.gtb (Z.add waddr size) top)) then + (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + : M (mword 64) + else if sumbool_of_bool ((Z.ltb waddr base)) then + (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + : M (mword 64) + else returnm ((to_bits 64 vAddr) : mword 64)) + : M (mword 64). + +Definition execute_branch (pc : mword 64) +: M (unit) := + + read_reg PCC_ref >>= fun w__0 : Capability => + let 'len := projT1 (getCapLength w__0) in + (if sumbool_of_bool ((Z.gtb (Z.add (projT1 (uint pc)) 4) len)) then + (raise_c2_exception_noreg CapEx_LengthViolation) + : M (unit) + else returnm (tt : unit)) >> + (execute_branch_mips pc) + : M (unit). + +Definition TranslatePC (vAddr : mword 64) +: M (mword 64) := + + (incrementCP0Count tt) >> + read_reg PCC_ref >>= fun pcc => + let '(existT _ base _, existT _ top _) := getCapBounds pcc in + let 'absPC := Z.add base (projT1 (uint vAddr)) in + (if ((neq_int (projT1 (emod_with_eq absPC 4)) 0)) then + (SignalExceptionBadAddr AdEL (to_bits 64 absPC)) + : M (mword 64) + else if ((negb pcc.(Capability_tag))) then + (raise_c2_exception_noreg CapEx_TagViolation) + : M (mword 64) + else if (pcc.(Capability_sealed)) then + (raise_c2_exception_noreg CapEx_SealViolation) + : M (mword 64) + else if ((negb pcc.(Capability_permit_execute))) then + (raise_c2_exception_noreg CapEx_PermitExecuteViolation) + : M (mword 64) + else if sumbool_of_bool ((Z.gtb (Z.add absPC 4) top)) then + (raise_c2_exception_noreg CapEx_LengthViolation) + : M (mword 64) + else (TLBTranslate (to_bits 64 absPC) Instruction) : M (mword 64)) + : M (mword 64). + +Definition checkCP2usable '(tt : unit) +: M (unit) := + + read_reg CP0Status_ref >>= fun w__0 : StatusReg => + (if ((negb ((bit_to_bool (access_vec_dec (_get_StatusReg_CU w__0) 2)) : bool))) then + (_set_CauseReg_CE CP0Cause_ref (vec_of_bits [B1;B0] : mword 2)) >> + (SignalException CpU) + : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition init_cp2_state '(tt : unit) +: M (unit) := + + write_reg PCC_ref default_cap >> + write_reg NextPCC_ref default_cap >> + write_reg DelayedPCC_ref default_cap >> + write_reg DDC_ref default_cap >> + write_reg KCC_ref default_cap >> + write_reg EPCC_ref default_cap >> + write_reg KDC_ref null_cap >> + write_reg KR1C_ref null_cap >> + write_reg KR2C_ref null_cap >> + write_reg CTLSP_ref null_cap >> + write_reg CTLSU_ref null_cap >> + (foreach_ZM_up 1 31 1 tt + (fun i _ unit_var => + let idx := to_bits 5 i in + (writeCapReg idx null_cap) + : M (unit))) + : M (unit). + +Definition cp2_next_pc '(tt : unit) +: M (unit) := + + read_reg NextPCC_ref >>= fun w__0 : Capability => + write_reg PCC_ref w__0 >> + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__1 : bits 1 => + (if (((bits_to_bool w__1) : bool)) then + read_reg DelayedPCC_ref >>= fun w__2 : Capability => write_reg NextPCC_ref w__2 : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition readEPCC '(tt : unit) +: M (Capability) := + + read_reg CP0Status_ref >>= fun w__0 : StatusReg => + (if ((Bool.eqb ((bits_to_bool (_get_StatusReg_ERL w__0)) : bool) ((bit_to_bool B1) : bool))) + then + ((read_reg CP0ErrorEPC_ref) : M (mword 64)) + : M (bits 64) + else ((read_reg CP0EPC_ref) : M (mword 64)) : M (bits 64)) >>= fun epccOffset => + read_reg EPCC_ref >>= fun epcc => + let '(success, epcc2) := setCapOffset epcc epccOffset in + returnm ((if (success) then epcc2 + else + int_to_cap + (add_vec_int (to_bits 64 (projT1 (getCapBase epcc))) (projT1 (uint epccOffset)))) + : Capability). + +Definition dump_cp2_state '(tt : unit) +: M (unit) := + + read_reg PCC_ref >>= fun w__0 : Capability => + (capToString w__0 true) >>= fun w__1 : string => + let '_ := (print_endline (String.append "DEBUG CAP PCC" w__1)) : unit in + (foreach_ZM_up 0 31 1 tt + (fun i _ unit_var => + (readCapReg (to_bits 5 i)) >>= fun w__2 : Capability => + (capToString w__2 true) >>= fun w__3 : string => + returnm (let '_ := + (print_endline (String.append "DEBUG CAP REG " (String.append (string_of_int i) w__3))) + : unit in + tt))) >> + read_reg DDC_ref >>= fun w__4 : Capability => + (capToString w__4 true) >>= fun w__5 : string => + let '_ := (print_endline (String.append "DEBUG CAP HWREG 00" w__5)) : unit in + read_reg CTLSU_ref >>= fun w__6 : Capability => + (capToString w__6 true) >>= fun w__7 : string => + let '_ := (print_endline (String.append "DEBUG CAP HWREG 01" w__7)) : unit in + read_reg CTLSP_ref >>= fun w__8 : Capability => + (capToString w__8 true) >>= fun w__9 : string => + let '_ := (print_endline (String.append "DEBUG CAP HWREG 08" w__9)) : unit in + read_reg KR1C_ref >>= fun w__10 : Capability => + (capToString w__10 true) >>= fun w__11 : string => + let '_ := (print_endline (String.append "DEBUG CAP HWREG 22" w__11)) : unit in + read_reg KR2C_ref >>= fun w__12 : Capability => + (capToString w__12 true) >>= fun w__13 : string => + let '_ := (print_endline (String.append "DEBUG CAP HWREG 23" w__13)) : unit in + read_reg KCC_ref >>= fun w__14 : Capability => + (capToString w__14 true) >>= fun w__15 : string => + let '_ := (print_endline (String.append "DEBUG CAP HWREG 29" w__15)) : unit in + read_reg KDC_ref >>= fun w__16 : Capability => + (capToString w__16 true) >>= fun w__17 : string => + let '_ := (print_endline (String.append "DEBUG CAP HWREG 30" w__17)) : unit in + (readEPCC tt) >>= fun w__18 : Capability => + (capToString w__18 true) >>= fun w__19 : string => + returnm ((print_endline (String.append "DEBUG CAP HWREG 31" w__19)) + : unit). + +Definition TLBWriteEntry (idx : mword 6) +: M (unit) := + + ((read_reg TLBPageMask_ref) : M (mword 16)) >>= fun pagemask => + let b__0 := pagemask in + (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16))) + then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else (SignalException MCheck) : M (unit)) >> + let 'i := projT1 (uint idx) in + let entry := vec_access_dec TLBEntries i in + (_set_TLBEntry_pagemask entry pagemask) >> + read_reg TLBEntryHi_ref >>= fun w__0 : TLBEntryHiReg => + (_set_TLBEntry_r entry (_get_TLBEntryHiReg_R w__0)) >> + read_reg TLBEntryHi_ref >>= fun w__1 : TLBEntryHiReg => + (_set_TLBEntry_vpn2 entry (_get_TLBEntryHiReg_VPN2 w__1)) >> + read_reg TLBEntryHi_ref >>= fun w__2 : TLBEntryHiReg => + (_set_TLBEntry_asid entry (_get_TLBEntryHiReg_ASID w__2)) >> + (and_boolM + (read_reg TLBEntryLo0_ref >>= fun w__3 : TLBEntryLoReg => + returnm ((bits_to_bool (_get_TLBEntryLoReg_G w__3)) + : bool)) + (read_reg TLBEntryLo1_ref >>= fun w__4 : TLBEntryLoReg => + returnm ((bits_to_bool (_get_TLBEntryLoReg_G w__4)) + : bool))) >>= fun w__5 : bool => + (_set_TLBEntry_g entry ((bool_to_bits w__5) : mword 1)) >> + (_set_TLBEntry_valid entry ((cast_unit_vec B1) : mword 1)) >> + read_reg TLBEntryLo0_ref >>= fun w__6 : TLBEntryLoReg => + (_set_TLBEntry_caps0 entry (_get_TLBEntryLoReg_CapS w__6)) >> + read_reg TLBEntryLo0_ref >>= fun w__7 : TLBEntryLoReg => + (_set_TLBEntry_capl0 entry (_get_TLBEntryLoReg_CapL w__7)) >> + read_reg TLBEntryLo0_ref >>= fun w__8 : TLBEntryLoReg => + (_set_TLBEntry_pfn0 entry (_get_TLBEntryLoReg_PFN w__8)) >> + read_reg TLBEntryLo0_ref >>= fun w__9 : TLBEntryLoReg => + (_set_TLBEntry_c0 entry (_get_TLBEntryLoReg_C w__9)) >> + read_reg TLBEntryLo0_ref >>= fun w__10 : TLBEntryLoReg => + (_set_TLBEntry_d0 entry (_get_TLBEntryLoReg_D w__10)) >> + read_reg TLBEntryLo0_ref >>= fun w__11 : TLBEntryLoReg => + (_set_TLBEntry_v0 entry (_get_TLBEntryLoReg_V w__11)) >> + read_reg TLBEntryLo1_ref >>= fun w__12 : TLBEntryLoReg => + (_set_TLBEntry_caps1 entry (_get_TLBEntryLoReg_CapS w__12)) >> + read_reg TLBEntryLo1_ref >>= fun w__13 : TLBEntryLoReg => + (_set_TLBEntry_capl1 entry (_get_TLBEntryLoReg_CapL w__13)) >> + read_reg TLBEntryLo1_ref >>= fun w__14 : TLBEntryLoReg => + (_set_TLBEntry_pfn1 entry (_get_TLBEntryLoReg_PFN w__14)) >> + read_reg TLBEntryLo1_ref >>= fun w__15 : TLBEntryLoReg => + (_set_TLBEntry_c1 entry (_get_TLBEntryLoReg_C w__15)) >> + read_reg TLBEntryLo1_ref >>= fun w__16 : TLBEntryLoReg => + (_set_TLBEntry_d1 entry (_get_TLBEntryLoReg_D w__16)) >> + read_reg TLBEntryLo1_ref >>= fun w__17 : TLBEntryLoReg => + (_set_TLBEntry_v1 entry (_get_TLBEntryLoReg_V w__17)) + : M (unit). + +Definition decode (v__0 : mword 32) +: option ast := + + if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B0;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (DADDIU + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DADDU + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B0;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (DADDI + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DADD + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (ADD + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B0;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (ADDI + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (ADDU + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B0;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (ADDIU + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSUBU + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSUB + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SUB + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SUBU + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (AND + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (ANDI + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (OR + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B1;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (ORI + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (NOR + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (XOR + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B1;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (XORI + ((rs, rt, imm))) + else if ((eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0] : mword (31 - 21 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (LUI + ((rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B0;B0;B0] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSLL + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B1;B0;B0] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSLL32 + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSLLV + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B0;B1;B1] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSRA + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B1;B1;B1] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSRA32 + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSRAV + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B0;B1;B0] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSRL + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B1;B1;B0] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSRL32 + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSRLV + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let sa : regno := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SLL + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SLLV + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B1;B1] : mword (5 - 0 + 1))))) then + let sa : regno := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SRA + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SRAV + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B1;B0] : mword (5 - 0 + 1))))) then + let sa : regno := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SRL + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SRLV + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SLT + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B0;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (SLTI + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SLTU + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B0;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (SLTIU + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MOVN + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MOVZ + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 16) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (31 - 16 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MFHI + (rd)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 16) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (31 - 16 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MFLO + (rd)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B1] + : mword (20 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MTHI + (rs)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B1] + : mword (20 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MTLO + (rs)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MUL + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MULT + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MULTU + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DMULT + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B1] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DMULTU + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MADD + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MADDU + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MSUB + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MSUBU + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B0] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DIV + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DIVU + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B0] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DDIV + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DDIVU + ((rs, rt))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B1;B0] : mword (31 - 26 + 1)))) then + let offset : bits 26 := subrange_vec_dec v__0 25 0 in + Some + (J + (offset)) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B1;B1] : mword (31 - 26 + 1)))) then + let offset : bits 26 := subrange_vec_dec v__0 25 0 in + Some + (JAL + (offset)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (andb + (eq_vec (subrange_vec_dec v__0 20 11) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (20 - 11 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B0;B0;B0] : mword (5 - 0 + 1)))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (JR + (rs)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (andb + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1] : mword (5 - 0 + 1)))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (JALR + ((rs, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BEQ + ((rs, rt, imm, false, false))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B0;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BEQ + ((rs, rt, imm, false, true))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B1;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BEQ + ((rs, rt, imm, true, false))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B0;B1;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BEQ + ((rs, rt, imm, true, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, LT', false, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B1;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, LT', true, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B1;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, LT', false, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B1;B0;B0;B1;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, LT', true, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B1] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, GE, false, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B1;B0;B0;B0;B1] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, GE, true, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B1;B1] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, GE, false, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B1;B0;B0;B1;B1] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, GE, true, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B1;B1;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, GT', false, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B0;B1;B1;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, GT', false, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B1;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, LE, false, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B0;B1;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, LE, false, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B1;B0;B0] : mword (5 - 0 + 1))))) then + Some + (SYSCALL + (tt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1] : mword (5 - 0 + 1))))) then + Some + (BREAK + (tt)) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0] + : mword 32))) then + Some + (WAIT + (tt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, GE))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B0;B0;B1] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, GEU))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B0;B1;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, LT'))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B0;B1;B1] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, LTU))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B1;B0;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, EQ'))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B1;B1;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, NE))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B1;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (TRAPIMM + ((rs, imm, EQ'))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B1;B1;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (TRAPIMM + ((rs, imm, NE))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (TRAPIMM + ((rs, imm, GE))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B0;B0;B1] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (TRAPIMM + ((rs, imm, GEU))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B0;B1;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (TRAPIMM + ((rs, imm, LT'))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B0;B1;B1] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (TRAPIMM + ((rs, imm, LTU))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B0;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((B, true, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((B, false, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B0;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((H, true, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B1;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((H, false, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((W, true, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((W, false, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B1;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((D, false, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B0;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((W, true, true, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((D, false, true, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B0;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((B, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B0;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((H, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B0;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((W, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B1;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((D, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B0;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((W, true, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((D, true, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B0;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (LWL + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B1;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (LWR + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B0;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (SWL + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B1;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (SWR + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B0;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (LDL + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B0;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (LDR + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (SDL + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B1;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (SDR + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B1;B1;B1] : mword (31 - 26 + 1)))) then + let op : regno := subrange_vec_dec v__0 20 16 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (CACHE + ((base, op, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 11) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (31 - 11 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B1;B1;B1] : mword (5 - 0 + 1))))) then + Some + (SYNC + (tt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 3) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 3 + 1))))) then + let sel : bits 3 := subrange_vec_dec v__0 2 0 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MFC0 + ((rt, rd, sel, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 3) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 3 + 1))))) then + let sel : bits 3 := subrange_vec_dec v__0 2 0 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MFC0 + ((rt, rd, sel, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (15 - 0 + 1))))) then + Some + (HCF + (tt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B1;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (15 - 0 + 1))))) then + Some + (HCF + (tt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 3) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 3 + 1))))) then + let sel : bits 3 := subrange_vec_dec v__0 2 0 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MTC0 + ((rt, rd, sel, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 3) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 3 + 1))))) then + let sel : bits 3 := subrange_vec_dec v__0 2 0 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MTC0 + ((rt, rd, sel, true))) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] + : mword 32))) then + Some + ((TLBWI + (tt)) + : ast) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] + : mword 32))) then + Some + ((TLBWR + (tt)) + : ast) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] + : mword 32))) then + Some + ((TLBR + (tt)) + : ast) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0] + : mword 32))) then + Some + ((TLBP + (tt)) + : ast) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B0;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (RDHWR + ((rt, rd))) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0] + : mword 32))) then + Some + (ERET + (tt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetPerm + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetType + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetBase + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetLen + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetTag + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetSealed + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] + : mword (15 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + Some + (CGetCause + (rd)) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32))) then + Some + (CReturn + (tt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B1] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetOffset + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 11) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (31 - 11 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B1;B0;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + Some + (CSetCause + (rt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CAndPerm + ((cd, cb, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CToPtr + ((rd, cb, ct))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, ct, CEQ))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, ct, CNE))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B1;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, ct, CLT))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B1;B1] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, ct, CLE))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B1;B0;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, ct, CLTU))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B1;B0;B1] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, ct, CLEU))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B1;B1;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, ct, CEXEQ))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B1;B1;B1] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, ct, CNEXEQ))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B1] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CIncOffset + ((cd, cb, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B1] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CSetOffset + ((cd, cb, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CSetBounds + ((cd, cb, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword (10 - 0 + 1))))) then + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CClearTag + ((cd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B1;B1;B1] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CFromPtr + ((cd, cb, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B1;B1] : mword (31 - 21 + 1))) + (andb + (eq_vec (subrange_vec_dec v__0 15 11) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (15 - 11 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1)))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 20 16 in + Some + (CCheckPerm + ((cs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B1;B1] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword (10 - 0 + 1))))) then + let cs : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CCheckType + ((cs, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let ct : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CSeal + ((cd, cs, ct))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let ct : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CUnseal + ((cd, cs, ct))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B1;B1] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 0 + 1))))) then + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CJALR + ((cd, cb, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 16) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (31 - 16 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 0 + 1))))) then + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CJALR + (((vec_of_bits [B0;B0;B0;B0;B0] : mword 5), cb, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : mword (15 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + Some + (CGetCause + (rd)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : mword (15 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 20 16 in + Some + (CSetCause + (rs)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : mword (15 - 0 + 1))))) then + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CGetPCC + (cd)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : mword (15 - 0 + 1))))) then + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CJALR + (((vec_of_bits [B0;B0;B0;B0;B0] : mword 5), cb, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : mword (15 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + Some + (CGetCID + (rd)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : mword (15 - 0 + 1))))) then + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CSetCID + (cb)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B1;B0;B0;B0;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 15 11 in + let cs : regno := subrange_vec_dec v__0 20 16 in + Some + (CCheckPerm + ((cs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B1;B0;B0;B1;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let cs : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CCheckType + ((cs, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CClearTag + ((cd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B1;B0;B1;B0;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CMOVX + ((cd, cs, (vec_of_bits [B0;B0;B0;B0;B0] : mword 5), false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CJALR + ((cd, cb, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B1;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CLoadTags + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetPerm + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetType + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetBase + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetLen + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetTag + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetSealed + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetOffset + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CGetPCCSetOffset + ((cd, rs))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B1;B1;B0;B1;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let sel : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CReadHwr + ((cd, sel))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let sel : regno := subrange_vec_dec v__0 15 11 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CWriteHwr + ((cb, sel))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let sel : regno := subrange_vec_dec v__0 15 11 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CGetAddr + ((cb, sel))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B0;B1;B1] : mword (5 - 0 + 1))))) then + let ct : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CSeal + ((cd, cs, ct))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B1;B0;B0] : mword (5 - 0 + 1))))) then + let ct : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CUnseal + ((cd, cs, ct))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CAndPerm + ((cd, cs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B1;B1;B1] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CSetOffset + ((cd, cs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CSetBounds + ((cd, cs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CSetBoundsExact + ((cd, cs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B0;B0;B0;B1] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CIncOffset + ((cd, cb, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1] : mword (5 - 0 + 1))))) then + let ct : regno := subrange_vec_dec v__0 10 6 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CBuildCap + ((cd, cb, ct))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B1;B1;B1;B0] : mword (5 - 0 + 1))))) then + let ct : regno := subrange_vec_dec v__0 10 6 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CCopyType + ((cd, cb, ct))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B1;B1;B1;B1] : mword (5 - 0 + 1))))) then + let ct : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CCSeal + ((cd, cs, ct))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B0;B0;B1;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CToPtr + ((rd, cb, ct))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B0;B0;B1;B1] : mword (5 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 10 6 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CFromPtr + ((cd, cb, rs))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B0;B1;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let cs : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CSub + ((rt, cb, cs))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B1;B0;B1;B1] : mword (5 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CMOVX + ((cd, cs, rs, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (5 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CMOVX + ((cd, cs, rs, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B0;B1;B0;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cs : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, cs, CEQ))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B0;B1;B0;B1] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cs : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, cs, CNE))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B0;B1;B1;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cs : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, cs, CLT))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B0;B1;B1;B1] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cs : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, cs, CLE))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B1;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cs : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, cs, CLTU))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cs : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, cs, CLEU))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B1;B0;B1;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cs : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, cs, CEXEQ))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B0;B0;B0;B0;B1] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cs : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, cs, CNEXEQ))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CTestSubset + ((rd, cb, ct))) + else if ((eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B0;B1] : mword (31 - 21 + 1)))) then + let imm : bits 16 := subrange_vec_dec v__0 15 0 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CBX + ((cd, imm, true))) + else if ((eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B1;B0] : mword (31 - 21 + 1)))) then + let imm : bits 16 := subrange_vec_dec v__0 15 0 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CBX + ((cd, imm, false))) + else if ((eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B1] : mword (31 - 21 + 1)))) then + let imm : bits 16 := subrange_vec_dec v__0 15 0 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CBZ + ((cd, imm, false))) + else if ((eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B1;B0] : mword (31 - 21 + 1)))) then + let imm : bits 16 := subrange_vec_dec v__0 15 0 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CBZ + ((cd, imm, true))) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : mword 32))) then + Some + (CReturn + (tt)) + else if ((eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B1] : mword (31 - 21 + 1)))) then + let selector : bits 11 := subrange_vec_dec v__0 10 0 in + let cs : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CCall + ((cs, cb, selector))) + else if ((eq_vec (subrange_vec_dec v__0 31 16) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0] : mword (31 - 16 + 1)))) + then + let imm : bits 16 := subrange_vec_dec v__0 15 0 in + Some + (ClearRegs + ((GPLo, imm))) + else if ((eq_vec (subrange_vec_dec v__0 31 16) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B1] : mword (31 - 16 + 1)))) + then + let imm : bits 16 := subrange_vec_dec v__0 15 0 in + Some + (ClearRegs + ((GPHi, imm))) + else if ((eq_vec (subrange_vec_dec v__0 31 16) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B1;B0] : mword (31 - 16 + 1)))) + then + let imm : bits 16 := subrange_vec_dec v__0 15 0 in + Some + (ClearRegs + ((CLo, imm))) + else if ((eq_vec (subrange_vec_dec v__0 31 16) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B1;B1] : mword (31 - 16 + 1)))) + then + let imm : bits 16 := subrange_vec_dec v__0 15 0 in + Some + (ClearRegs + ((CHi, imm))) + else if ((eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B1;B1] : mword (31 - 21 + 1)))) then + let imm : bits 11 := subrange_vec_dec v__0 10 0 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CIncOffsetImmediate + ((cd, cb, imm))) + else if ((eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B1;B0;B0] : mword (31 - 21 + 1)))) then + let imm : bits 11 := subrange_vec_dec v__0 10 0 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CSetBoundsImmediate + ((cd, cb, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rd : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CLoad + ((rd, cb, rt, offset, false, B))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B1;B0;B0] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rd : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CLoad + ((rd, cb, rt, offset, true, B))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B0;B0;B1] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rd : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CLoad + ((rd, cb, rt, offset, false, H))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B1;B0;B1] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rd : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CLoad + ((rd, cb, rt, offset, true, H))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B0;B1;B0] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rd : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CLoad + ((rd, cb, rt, offset, false, W))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B1;B1;B0] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rd : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CLoad + ((rd, cb, rt, offset, true, W))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B0;B1;B1] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rd : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CLoad + ((rd, cb, rt, offset, false, D))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CLoadLinked + ((rd, cb, false, B))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CLoadLinked + ((rd, cb, true, B))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CLoadLinked + ((rd, cb, false, H))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CLoadLinked + ((rd, cb, true, H))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CLoadLinked + ((rd, cb, false, W))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CLoadLinked + ((rd, cb, true, W))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CLoadLinked + ((rd, cb, false, D))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CStore + ((rs, cb, rt, offset, B))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B0;B0;B1] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CStore + ((rs, cb, rt, offset, H))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B0;B1;B0] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CStore + ((rs, cb, rt, offset, W))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B0;B1;B1] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CStore + ((rs, cb, rt, offset, D))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CStoreConditional + ((rs, cb, rd, B))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (5 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CStoreConditional + ((rs, cb, rd, H))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B1;B0] : mword (5 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CStoreConditional + ((rs, cb, rd, W))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B1;B1] : mword (5 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CStoreConditional + ((rs, cb, rd, D))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B1;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 15 11 in + let offset : bits 11 := subrange_vec_dec v__0 10 0 in + let cs : regno := subrange_vec_dec v__0 25 21 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CSC + ((cs, cb, rt, offset))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B1;B1;B1] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CSCC + ((cs, cb, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B1;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 15 11 in + let offset : bits 11 := subrange_vec_dec v__0 10 0 in + let cd : regno := subrange_vec_dec v__0 25 21 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CLC + ((cd, cb, rt, offset))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CLLC + ((cd, cb))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B1] : mword (31 - 26 + 1)))) then + let offset : bits 16 := subrange_vec_dec v__0 15 0 in + let cd : regno := subrange_vec_dec v__0 25 21 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CLCBI + ((cd, cb, offset))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + Some + (C2Dump + (rt)) + else Some (RI (tt)). + +Definition execute_XORI (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (wGPR rt (xor_vec w__0 (mips_zero_extend 64 imm))) + : M (unit). + +Definition execute_XOR (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (xor_vec w__0 w__1)) : M (unit). + +Definition execute_WAIT '(tt : unit) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + write_reg NextPC_ref w__1 + : M (unit). + +Definition execute_TRAPREG (rs : mword 5) (rt : mword 5) (cmp : Comparison) +: M (unit) := + + (rGPR rs) >>= fun rs_val => + (rGPR rt) >>= fun rt_val => + let condition := compare cmp rs_val rt_val in + (if (condition) then (SignalException Tr) : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_TRAPIMM (rs : mword 5) (imm : mword 16) (cmp : Comparison) +: M (unit) := + + (rGPR rs) >>= fun rs_val => + let imm_val : bits 64 := mips_sign_extend 64 imm in + let condition := compare cmp rs_val imm_val in + (if (condition) then (SignalException Tr) : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_TLBWR '(tt : unit) +: M (unit) := + + (checkCP0Access tt) >> + ((read_reg TLBRandom_ref) : M (mword 6)) >>= fun w__0 : TLBIndexT => + (TLBWriteEntry w__0) + : M (unit). + +Definition execute_TLBWI '(tt : unit) +: M (unit) := + + (checkCP0Access tt) >> + ((read_reg TLBIndex_ref) : M (mword 6)) >>= fun w__0 : TLBIndexT => + (TLBWriteEntry w__0) + : M (unit). + +Definition execute_TLBR '(tt : unit) +: M (unit) := + + (checkCP0Access tt) >> + ((read_reg TLBIndex_ref) : M (mword 6)) >>= fun w__0 : TLBIndexT => + let 'i := projT1 (uint w__0) in + (reg_deref (vec_access_dec TLBEntries i)) >>= fun entry => + write_reg TLBPageMask_ref (_get_TLBEntry_pagemask entry) >> + (_set_TLBEntryHiReg_R TLBEntryHi_ref (_get_TLBEntry_r entry)) >> + (_set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (_get_TLBEntry_vpn2 entry)) >> + (_set_TLBEntryHiReg_ASID TLBEntryHi_ref (_get_TLBEntry_asid entry)) >> + (_set_TLBEntryLoReg_CapS TLBEntryLo0_ref (_get_TLBEntry_caps0 entry)) >> + (_set_TLBEntryLoReg_CapL TLBEntryLo0_ref (_get_TLBEntry_capl0 entry)) >> + (_set_TLBEntryLoReg_PFN TLBEntryLo0_ref (_get_TLBEntry_pfn0 entry)) >> + (_set_TLBEntryLoReg_C TLBEntryLo0_ref (_get_TLBEntry_c0 entry)) >> + (_set_TLBEntryLoReg_D TLBEntryLo0_ref (_get_TLBEntry_d0 entry)) >> + (_set_TLBEntryLoReg_V TLBEntryLo0_ref (_get_TLBEntry_v0 entry)) >> + (_set_TLBEntryLoReg_G TLBEntryLo0_ref (_get_TLBEntry_g entry)) >> + (_set_TLBEntryLoReg_CapS TLBEntryLo1_ref (_get_TLBEntry_caps1 entry)) >> + (_set_TLBEntryLoReg_CapL TLBEntryLo1_ref (_get_TLBEntry_capl1 entry)) >> + (_set_TLBEntryLoReg_PFN TLBEntryLo1_ref (_get_TLBEntry_pfn1 entry)) >> + (_set_TLBEntryLoReg_C TLBEntryLo1_ref (_get_TLBEntry_c1 entry)) >> + (_set_TLBEntryLoReg_D TLBEntryLo1_ref (_get_TLBEntry_d1 entry)) >> + (_set_TLBEntryLoReg_V TLBEntryLo1_ref (_get_TLBEntry_v1 entry)) >> + (_set_TLBEntryLoReg_G TLBEntryLo1_ref (_get_TLBEntry_g entry)) + : M (unit). + +Definition execute_TLBP '(tt : unit) +: M (unit) := + + (checkCP0Access tt) >> + read_reg TLBEntryHi_ref >>= fun w__0 : TLBEntryHiReg => + (tlbSearch (_get_TLBEntryHiReg_bits w__0)) >>= fun result => + (match result with + | Some (idx) => + write_reg TLBProbe_ref (vec_of_bits [B0] : mword 1) >> + write_reg TLBIndex_ref idx + : M (unit) + | None => + write_reg TLBProbe_ref (vec_of_bits [B1] : mword 1) >> + write_reg TLBIndex_ref (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6) + : M (unit) + end) + : M (unit). + +Definition execute_Store +(width : WordType) (conditional : bool) (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + (addrWrapper (add_vec (mips_sign_extend 64 offset) w__0) StoreData width) >>= fun vAddr : bits 64 => + (rGPR rt) >>= fun rt_val => + (if ((negb (isAddressAligned vAddr width))) then (SignalExceptionBadAddr AdES vAddr) : M (unit) + else + (TLBTranslate vAddr StoreData) >>= fun pAddr => + (if (conditional) then + ((read_reg CP0LLBit_ref) : M (mword 1)) >>= fun w__1 : bits 1 => + (if (((bit_to_bool (access_vec_dec w__1 0)) : bool)) then + (match width with + | W => (MEMw_conditional_wrapper pAddr 4 (subrange_vec_dec rt_val 31 0)) : M (bool) + | D => (MEMw_conditional_wrapper pAddr 8 rt_val) : M (bool) + | _ => (throw (Error_internal_error (tt))) : M (bool) + end) + : M (bool) + else returnm (false : bool)) >>= fun success : bool => + (wGPR rt (mips_zero_extend 64 (bool_to_bits success))) + : M (unit) + else + (match width with + | B => (MEMw_wrapper pAddr 1 (subrange_vec_dec rt_val 7 0)) : M (unit) + | H => (MEMw_wrapper pAddr 2 (subrange_vec_dec rt_val 15 0)) : M (unit) + | W => (MEMw_wrapper pAddr 4 (subrange_vec_dec rt_val 31 0)) : M (unit) + | D => (MEMw_wrapper pAddr 8 rt_val) : M (unit) + end) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_SYSCALL '(tt : unit) : M (unit) := (SignalException Sys) : M (unit). + +Definition execute_SYNC '(tt : unit) : M (unit) := (MEM_sync tt) : M (unit). + +Definition execute_SWR (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + (addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData WR) >>= fun vAddr => + (TLBTranslate vAddr StoreData) >>= fun pAddr => + let wordAddr := concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0] : mword 2) in + (rGPR rt) >>= fun reg_val => + let b__12 := subrange_vec_dec vAddr 1 0 in + (if ((eq_vec b__12 (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) then + (MEMw_wrapper wordAddr 1 (subrange_vec_dec reg_val 7 0)) + : M (unit) + else if ((eq_vec b__12 (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))) then + (MEMw_wrapper wordAddr 2 (subrange_vec_dec reg_val 15 0)) + : M (unit) + else if ((eq_vec b__12 (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))) then + (MEMw_wrapper wordAddr 3 (subrange_vec_dec reg_val 23 0)) + : M (unit) + else (MEMw_wrapper wordAddr 4 (subrange_vec_dec reg_val 31 0)) : M (unit)) + : M (unit). + +Definition execute_SWL (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + (addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData WL) >>= fun vAddr => + (TLBTranslate vAddr StoreData) >>= fun pAddr => + (rGPR rt) >>= fun reg_val => + let b__8 := subrange_vec_dec vAddr 1 0 in + (if ((eq_vec b__8 (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) then + (MEMw_wrapper pAddr 4 (subrange_vec_dec reg_val 31 0)) + : M (unit) + else if ((eq_vec b__8 (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))) then + (MEMw_wrapper pAddr 3 (subrange_vec_dec reg_val 31 8)) + : M (unit) + else if ((eq_vec b__8 (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))) then + (MEMw_wrapper pAddr 2 (subrange_vec_dec reg_val 31 16)) + : M (unit) + else (MEMw_wrapper pAddr 1 (subrange_vec_dec reg_val 31 24)) : M (unit)) + : M (unit). + +Definition execute_SUBU (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun opA => + (rGPR rt) >>= fun opB => + (if ((orb (NotWordVal opA) (NotWordVal opB))) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) + else + (wGPR rd + (mips_sign_extend 64 (sub_vec (subrange_vec_dec opA 31 0) (subrange_vec_dec opB 31 0)))) + : M (unit)) + : M (unit). + +Definition execute_SUB (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun opA => + (rGPR rt) >>= fun opB => + (if ((orb (NotWordVal opA) (NotWordVal opB))) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) + else + let temp33 : bits 33 := + sub_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0)) + (mips_sign_extend 33 (subrange_vec_dec opB 31 0)) in + (if ((neq_bool ((bit_to_bool (access_vec_dec temp33 32)) : bool) + ((bit_to_bool (access_vec_dec temp33 31)) + : bool))) then + (SignalException Ov) + : M (unit) + else (wGPR rd (mips_sign_extend 64 (subrange_vec_dec temp33 31 0))) : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_SRLV (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (rGPR rs) >>= fun w__0 : mword 64 => + let sa := subrange_vec_dec w__0 4 0 in + (if ((NotWordVal temp)) then + (undefined_bitvector 64) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit) + else + let rt32 := subrange_vec_dec temp 31 0 in + (shift_bits_right rt32 sa) >>= fun w__2 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__2)) + : M (unit)) + : M (unit). + +Definition execute_SRL (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (if ((NotWordVal temp)) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) + else + let rt32 := subrange_vec_dec temp 31 0 in + (shift_bits_right rt32 sa) >>= fun w__1 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__1)) + : M (unit)) + : M (unit). + +Definition execute_SRAV (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (rGPR rs) >>= fun w__0 : mword 64 => + let sa := subrange_vec_dec w__0 4 0 in + (if ((NotWordVal temp)) then + (undefined_bitvector 64) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit) + else + let rt32 := subrange_vec_dec temp 31 0 in + (shift_bits_right_arith rt32 sa) >>= fun w__2 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__2)) + : M (unit)) + : M (unit). + +Definition execute_SRA (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (if ((NotWordVal temp)) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) + else + let rt32 := subrange_vec_dec temp 31 0 in + (shift_bits_right_arith rt32 sa) >>= fun w__1 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__1)) + : M (unit)) + : M (unit). + +Definition execute_SLTU (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rs_val => + (rGPR rt) >>= fun rt_val => + (wGPR rd + (mips_zero_extend 64 + (if ((zopz0zI_u rs_val rt_val)) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1)))) + : M (unit). + +Definition execute_SLTIU (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun rs_val => + let immext : bits 64 := mips_sign_extend 64 imm in + (wGPR rt + (mips_zero_extend 64 + (if ((zopz0zI_u rs_val immext)) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1)))) + : M (unit). + +Definition execute_SLTI (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + let 'imm_val := projT1 (sint imm) in + (rGPR rs) >>= fun w__0 : mword 64 => + let 'rs_val := projT1 (sint w__0) in + (wGPR rt + (mips_zero_extend 64 + (if sumbool_of_bool ((Z.ltb rs_val imm_val)) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1)))) + : M (unit). + +Definition execute_SLT (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => + (wGPR rd + (mips_zero_extend 64 + (if ((zopz0zI_s w__0 w__1)) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1)))) + : M (unit). + +Definition execute_SLLV (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + let sa := subrange_vec_dec w__0 4 0 in + (rGPR rt) >>= fun w__1 : mword 64 => + let rt32 := subrange_vec_dec w__1 31 0 in + (shift_bits_left rt32 sa) >>= fun w__2 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__2)) + : M (unit). + +Definition execute_SLL (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun w__0 : mword 64 => + let rt32 := subrange_vec_dec w__0 31 0 in + (shift_bits_left rt32 sa) >>= fun w__1 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__1)) + : M (unit). + +Definition execute_SDR (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + (addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData DR) >>= fun vAddr => + (TLBTranslate vAddr StoreData) >>= fun pAddr => + (rGPR rt) >>= fun reg_val => + let wordAddr := concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0] : mword 3) in + let b__40 := subrange_vec_dec vAddr 2 0 in + (if ((eq_vec b__40 (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 1 (subrange_vec_dec reg_val 7 0)) + : M (unit) + else if ((eq_vec b__40 (vec_of_bits [B0;B0;B1] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 2 (subrange_vec_dec reg_val 15 0)) + : M (unit) + else if ((eq_vec b__40 (vec_of_bits [B0;B1;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 3 (subrange_vec_dec reg_val 23 0)) + : M (unit) + else if ((eq_vec b__40 (vec_of_bits [B0;B1;B1] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 4 (subrange_vec_dec reg_val 31 0)) + : M (unit) + else if ((eq_vec b__40 (vec_of_bits [B1;B0;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 5 (subrange_vec_dec reg_val 39 0)) + : M (unit) + else if ((eq_vec b__40 (vec_of_bits [B1;B0;B1] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 6 (subrange_vec_dec reg_val 47 0)) + : M (unit) + else if ((eq_vec b__40 (vec_of_bits [B1;B1;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 7 (subrange_vec_dec reg_val 55 0)) + : M (unit) + else (MEMw_wrapper wordAddr 8 (subrange_vec_dec reg_val 63 0)) : M (unit)) + : M (unit). + +Definition execute_SDL (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + (addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData DL) >>= fun vAddr => + (TLBTranslate vAddr StoreData) >>= fun pAddr => + (rGPR rt) >>= fun reg_val => + let b__32 := subrange_vec_dec vAddr 2 0 in + (if ((eq_vec b__32 (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 8 (subrange_vec_dec reg_val 63 0)) + : M (unit) + else if ((eq_vec b__32 (vec_of_bits [B0;B0;B1] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 7 (subrange_vec_dec reg_val 63 8)) + : M (unit) + else if ((eq_vec b__32 (vec_of_bits [B0;B1;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 6 (subrange_vec_dec reg_val 63 16)) + : M (unit) + else if ((eq_vec b__32 (vec_of_bits [B0;B1;B1] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 5 (subrange_vec_dec reg_val 63 24)) + : M (unit) + else if ((eq_vec b__32 (vec_of_bits [B1;B0;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 4 (subrange_vec_dec reg_val 63 32)) + : M (unit) + else if ((eq_vec b__32 (vec_of_bits [B1;B0;B1] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 3 (subrange_vec_dec reg_val 63 40)) + : M (unit) + else if ((eq_vec b__32 (vec_of_bits [B1;B1;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 2 (subrange_vec_dec reg_val 63 48)) + : M (unit) + else (MEMw_wrapper pAddr 1 (subrange_vec_dec reg_val 63 56)) : M (unit)) + : M (unit). + +Definition execute_RI '(tt : unit) : M (unit) := (skip tt) >> (SignalException ResI) : M (unit). + +Definition execute_RDHWR (rt : mword 5) (rd : mword 5) +: M (unit) := + + (getAccessLevel tt) >>= fun accessLevel => + let haveAccessLevel : bool := generic_eq accessLevel Kernel in + read_reg CP0Status_ref >>= fun w__0 : StatusReg => + let haveCU0 : bool := eq_bit B1 (access_vec_dec (_get_StatusReg_CU w__0) 0) in + let 'rdi := projT1 (uint rd) in + ((read_reg CP0HWREna_ref) : M (mword 32)) >>= fun w__1 : bits 32 => + let haveHWREna : bool := eq_bit B1 (access_vec_dec w__1 rdi) in + (if ((negb (orb haveAccessLevel (orb haveCU0 haveHWREna)))) then + (SignalException ResI) + : M (unit) + else returnm (tt : unit)) >> + let b__150 := rd in + (if ((eq_vec b__150 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((eq_vec b__150 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((eq_vec b__150 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5))) then + ((read_reg CP0Count_ref) : M (mword 32)) >>= fun w__2 : bits 32 => + returnm ((mips_zero_extend 64 w__2) + : mword 64) + else if ((eq_vec b__150 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B1] : mword 1)) + : mword 64) + else if ((eq_vec b__150 (vec_of_bits [B1;B1;B1;B0;B1] : mword 5))) then + ((read_reg CP0UserLocal_ref) : M (mword 64)) + : M (bits 64) + else (SignalException ResI) : M (mword 64)) >>= fun temp : bits 64 => + (wGPR rt temp) + : M (unit). + +Definition execute_ORI (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (wGPR rt (or_vec w__0 (mips_zero_extend 64 imm))) + : M (unit). + +Definition execute_OR (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (or_vec w__0 w__1)) : M (unit). + +Definition execute_NOR (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (not_vec (or_vec w__0 w__1))) : M (unit). + +Definition execute_MULTU (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun result : bits 64 => + write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> + write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) + : M (unit). + +Definition execute_MULT (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun result : bits 64 => + write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> + write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) + : M (unit). + +Definition execute_MUL (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + let result : bits 64 := + mips_sign_extend 64 (mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) in + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else returnm ((mips_sign_extend 64 (subrange_vec_dec result 31 0)) : mword 64)) >>= fun w__1 : mword 64 => + (wGPR rd w__1) + : M (unit). + +Definition execute_MTLO (rs : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => write_reg LO_ref w__0 : M (unit). + +Definition execute_MTHI (rs : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => write_reg HI_ref w__0 : M (unit). + +Definition execute_MTC0 (rt : mword 5) (rd : mword 5) (sel : mword 3) (double : bool) +: M (unit) := + + (checkCP0Access tt) >> + (rGPR rt) >>= fun reg_val => + (match (rd, sel) with + | (b__112, b__113) => + (if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg TLBIndex_ref (mask 6 reg_val) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + returnm (tt + : unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_TLBEntryLoReg_bits TLBEntryLo0_ref reg_val) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_TLBEntryLoReg_bits TLBEntryLo1_ref reg_val) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_ContextReg_PTEBase TLBContext_ref (subrange_vec_dec reg_val 63 23)) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B1;B0] : mword 3)))) then + write_reg CP0UserLocal_ref reg_val + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B1;B0;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg TLBPageMask_ref (subrange_vec_dec reg_val 28 13) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B1;B1;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg TLBWired_ref (mask 6 reg_val) >> write_reg TLBRandom_ref TLBIndexMax : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B1;B1;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg + CP0HWREna_ref + (concat_vec (subrange_vec_dec reg_val 31 29) + (concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0] + : mword 25) (subrange_vec_dec reg_val 3 0))) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + returnm (tt + : unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B0;B0;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg CP0Count_ref (subrange_vec_dec reg_val 31 0) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B0;B1;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_TLBEntryHiReg_R TLBEntryHi_ref (subrange_vec_dec reg_val 63 62)) >> + (_set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (subrange_vec_dec reg_val 39 13)) >> + (_set_TLBEntryHiReg_ASID TLBEntryHi_ref (subrange_vec_dec reg_val 7 0)) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B0;B1;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg CP0Compare_ref (subrange_vec_dec reg_val 31 0) >> + read_reg CP0Cause_ref >>= fun w__0 : CauseReg => + (_set_CauseReg_IP CP0Cause_ref + (and_vec (_get_CauseReg_IP w__0) (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1] : mword 8))) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_StatusReg_CU CP0Status_ref + (and_vec (subrange_vec_dec reg_val 31 28) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (bool_to_bits have_cp2) (vec_of_bits [B0;B1] : mword 2))))) >> + (_set_StatusReg_BEV CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 22)) : mword 1)) >> + (_set_StatusReg_IM CP0Status_ref (subrange_vec_dec reg_val 15 8)) >> + (_set_StatusReg_KX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 7)) : mword 1)) >> + (_set_StatusReg_SX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 6)) : mword 1)) >> + (_set_StatusReg_UX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 5)) : mword 1)) >> + (_set_StatusReg_KSU CP0Status_ref (subrange_vec_dec reg_val 4 3)) >> + (_set_StatusReg_ERL CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 2)) : mword 1)) >> + (_set_StatusReg_EXL CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 1)) : mword 1)) >> + (_set_StatusReg_IE CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 0)) : mword 1)) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B1;B0;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_CauseReg_IV CP0Cause_ref ((cast_unit_vec (access_vec_dec reg_val 23)) : mword 1)) >> + read_reg CP0Cause_ref >>= fun w__1 : CauseReg => + let ip := _get_CauseReg_IP w__1 in + (_set_CauseReg_IP CP0Cause_ref + (concat_vec (subrange_vec_dec ip 7 2) (subrange_vec_dec reg_val 9 8))) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B1;B1;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg CP0EPC_ref reg_val + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg CP0ConfigK0_ref (subrange_vec_dec reg_val 2 0) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_XContextReg_XPTEBase TLBXContext_ref (subrange_vec_dec reg_val 63 33)) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B1;B1;B1;B1;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg CP0ErrorEPC_ref reg_val + : M (unit) + else (SignalException ResI) : M (unit)) + : M (unit) + end) + : M (unit). + +Definition execute_MSUBU (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun mul_result : bits 64 => + ((read_reg HI_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + ((read_reg LO_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + let result := + sub_vec (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) mul_result in + write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> + write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) + : M (unit). + +Definition execute_MSUB (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun mul_result : bits 64 => + ((read_reg HI_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + ((read_reg LO_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + let result := + sub_vec (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) mul_result in + write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> + write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) + : M (unit). + +Definition execute_MOVZ (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun w__0 : mword 64 => + (if ((eq_vec w__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))) then + (rGPR rs) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_MOVN (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun w__0 : mword 64 => + (if ((neq_vec w__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))) then + (rGPR rs) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_MFLO (rd : mword 5) +: M (unit) := + + ((read_reg LO_ref) : M (mword 64)) >>= fun w__0 : bits 64 => (wGPR rd w__0) : M (unit). + +Definition execute_MFHI (rd : mword 5) +: M (unit) := + + ((read_reg HI_ref) : M (mword 64)) >>= fun w__0 : bits 64 => (wGPR rd w__0) : M (unit). + +Definition execute_MFC0 (rt : mword 5) (rd : mword 5) (sel : mword 3) (double : bool) +: M (unit) := + + (checkCP0Access tt) >> + (match (rd, sel) with + | (b__48, b__49) => + (if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg TLBIndex_ref) : M (mword 6)) >>= fun w__0 : TLBIndexT => + let idx : bits 31 := mips_zero_extend 31 w__0 in + ((read_reg TLBProbe_ref) : M (mword 1)) >>= fun w__1 : bits 1 => + returnm ((concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) (concat_vec w__1 idx)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg TLBRandom_ref) : M (mword 6)) >>= fun w__2 : TLBIndexT => + returnm ((mips_zero_extend 64 w__2) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg TLBEntryLo0_ref >>= fun w__3 : TLBEntryLoReg => + returnm ((_get_TLBEntryLoReg_bits w__3) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg TLBEntryLo1_ref >>= fun w__4 : TLBEntryLoReg => + returnm ((_get_TLBEntryLoReg_bits w__4) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg TLBContext_ref >>= fun w__5 : ContextReg => + returnm ((_get_ContextReg_bits w__5) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B1;B0] : mword 3)))) then + ((read_reg CP0UserLocal_ref) : M (mword 64)) + : M (bits 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg TLBPageMask_ref) : M (mword 16)) >>= fun w__7 : bits 16 => + returnm ((mips_zero_extend 64 + (concat_vec w__7 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg TLBWired_ref) : M (mword 6)) >>= fun w__8 : TLBIndexT => + returnm ((mips_zero_extend 64 w__8) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0HWREna_ref) : M (mword 32)) >>= fun w__9 : bits 32 => + returnm ((mips_zero_extend 64 w__9) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0BadVAddr_ref) : M (mword 64)) + : M (bits 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B1] : mword 3)))) then + ((read_reg CP0BadInstr_ref) : M (mword 32)) >>= fun w__11 : bits 32 => + returnm ((mips_zero_extend 64 w__11) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B1;B0] : mword 3)))) then + ((read_reg CP0BadInstrP_ref) : M (mword 32)) >>= fun w__12 : bits 32 => + returnm ((mips_zero_extend 64 w__12) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0Count_ref) : M (mword 32)) >>= fun w__13 : bits 32 => + returnm ((mips_zero_extend 64 w__13) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg TLBEntryHi_ref >>= fun w__14 : TLBEntryHiReg => + returnm ((_get_TLBEntryHiReg_bits w__14) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0Compare_ref) : M (mword 32)) >>= fun w__15 : bits 32 => + returnm ((mips_zero_extend 64 w__15) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg CP0Status_ref >>= fun w__16 : StatusReg => + returnm ((mips_zero_extend 64 (_get_StatusReg_bits w__16)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B0;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg CP0Cause_ref >>= fun w__17 : CauseReg => + returnm ((mips_zero_extend 64 (_get_CauseReg_bits w__17)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0EPC_ref) : M (mword 64)) + : M (bits 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + returnm ((mips_zero_extend 64 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B1;B1;B0] : mword 3)))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B1;B1;B1] : mword 3)))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0ConfigK0_ref) : M (mword 3)) >>= fun w__19 : bits 3 => + returnm ((mips_zero_extend 64 + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 15) + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec (vec_of_bits [B1;B0] : mword 2) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) w__19)))))))) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B1] : mword 3)))) then + returnm ((mips_zero_extend 64 + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec TLBIndexMax + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (bool_to_bits have_cp2) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec + (vec_of_bits [B0] : mword 1) + (vec_of_bits [B0] : mword 1)))))))))))))))) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B1;B0] : mword 3)))) then + returnm ((mips_zero_extend 64 + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (vec_of_bits [B0;B0;B0;B0] : mword 4)))))))))) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B1;B1] : mword 3)))) then + returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B1;B0;B1] : mword 3)))) then + returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B1;B1;B0] : mword 3)))) then + returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0LLAddr_ref) : M (mword 64)) + : M (bits 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg TLBXContext_ref >>= fun w__21 : XContextReg => + returnm ((_get_XContextReg_bits w__21) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B1;B1;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0ErrorEPC_ref) : M (mword 64)) + : M (bits 64) + else (SignalException ResI) : M (mword 64)) + : M (mword 64) + end) >>= fun result : bits 64 => + (wGPR rt (if (double) then result else mips_sign_extend 64 (subrange_vec_dec result 31 0))) + : M (unit). + +Definition execute_MADDU (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun mul_result : bits 64 => + ((read_reg HI_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + ((read_reg LO_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + let result := + add_vec mul_result (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) in + write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> + write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) + : M (unit). + +Definition execute_MADD (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun mul_result : bits 64 => + ((read_reg HI_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + ((read_reg LO_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + let result := + add_vec mul_result (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) in + write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> + write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) + : M (unit). + +Definition execute_Load +(width : WordType) (sign : bool) (linked : bool) (base : mword 5) (rt : mword 5) (offset : mword 16) + +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + (addrWrapper (add_vec (mips_sign_extend 64 offset) w__0) LoadData width) >>= fun vAddr : bits 64 => + (if ((negb (isAddressAligned vAddr width))) then (SignalExceptionBadAddr AdEL vAddr) : M (unit) + else + (TLBTranslate vAddr LoadData) >>= fun pAddr => + (if (linked) then + write_reg CP0LLBit_ref (vec_of_bits [B1] : mword 1) >> + write_reg CP0LLAddr_ref pAddr >> + (match width with + | W => + (MEMr_reserve_wrapper pAddr 4) >>= fun w__1 : mword (8 * 4) => + returnm ((extendLoad w__1 sign) + : mword 64) + | D => + (MEMr_reserve_wrapper pAddr 8) >>= fun w__2 : mword (8 * 8) => + returnm ((extendLoad w__2 sign) + : mword 64) + | _ => (throw (Error_internal_error (tt))) : M (mword 64) + end) + : M (mword 64) + else + (match width with + | B => + (MEMr_wrapper pAddr 1) >>= fun w__5 : mword (8 * 1) => + returnm ((extendLoad w__5 sign) + : mword 64) + | H => + (MEMr_wrapper pAddr 2) >>= fun w__6 : mword (8 * 2) => + returnm ((extendLoad w__6 sign) + : mword 64) + | W => + (MEMr_wrapper pAddr 4) >>= fun w__7 : mword (8 * 4) => + returnm ((extendLoad w__7 sign) + : mword 64) + | D => + (MEMr_wrapper pAddr 8) >>= fun w__8 : mword (8 * 8) => + returnm ((extendLoad w__8 sign) + : mword 64) + end) + : M (mword 64)) >>= fun memResult : bits 64 => + (wGPR rt memResult) + : M (unit)) + : M (unit). + +Definition execute_LWR (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + (addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData WR) >>= fun vAddr => + (TLBTranslate vAddr LoadData) >>= fun pAddr => + (MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0] : mword 2)) 4) >>= fun mem_val => + (rGPR rt) >>= fun reg_val => + let b__4 := subrange_vec_dec vAddr 1 0 in + let result : bits 32 := + if ((eq_vec b__4 (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 31 8) (subrange_vec_dec mem_val 31 24) + else if ((eq_vec b__4 (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 31 16) (subrange_vec_dec mem_val 31 16) + else if ((eq_vec b__4 (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 31 24) (subrange_vec_dec mem_val 31 8) + else mem_val in + (wGPR rt (mips_sign_extend 64 result)) + : M (unit). + +Definition execute_LWL (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + (addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData WL) >>= fun vAddr => + (TLBTranslate vAddr LoadData) >>= fun pAddr => + (MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0] : mword 2)) 4) >>= fun mem_val => + (rGPR rt) >>= fun reg_val => + let b__0 := subrange_vec_dec vAddr 1 0 in + let result : bits 32 := + if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) then mem_val + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 23 0) (subrange_vec_dec reg_val 7 0) + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 15 0) (subrange_vec_dec reg_val 15 0) + else concat_vec (subrange_vec_dec mem_val 7 0) (subrange_vec_dec reg_val 23 0) in + (wGPR rt (mips_sign_extend 64 result)) + : M (unit). + +Definition execute_LUI (rt : mword 5) (imm : mword 16) +: M (unit) := + + (wGPR rt + (mips_sign_extend 64 + (concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16)))) + : M (unit). + +Definition execute_LDR (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + (addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData DR) >>= fun vAddr => + (TLBTranslate vAddr LoadData) >>= fun pAddr => + (MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0] : mword 3)) 8) >>= fun mem_val => + (rGPR rt) >>= fun reg_val => + let b__24 := subrange_vec_dec vAddr 2 0 in + (wGPR rt + (if ((eq_vec b__24 (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 8) (subrange_vec_dec mem_val 63 56) + else if ((eq_vec b__24 (vec_of_bits [B0;B0;B1] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 16) (subrange_vec_dec mem_val 63 48) + else if ((eq_vec b__24 (vec_of_bits [B0;B1;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 24) (subrange_vec_dec mem_val 63 40) + else if ((eq_vec b__24 (vec_of_bits [B0;B1;B1] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 32) (subrange_vec_dec mem_val 63 32) + else if ((eq_vec b__24 (vec_of_bits [B1;B0;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 40) (subrange_vec_dec mem_val 63 24) + else if ((eq_vec b__24 (vec_of_bits [B1;B0;B1] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 48) (subrange_vec_dec mem_val 63 16) + else if ((eq_vec b__24 (vec_of_bits [B1;B1;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 56) (subrange_vec_dec mem_val 63 8) + else mem_val)) + : M (unit). + +Definition execute_LDL (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + (addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData DL) >>= fun vAddr => + (TLBTranslate vAddr LoadData) >>= fun pAddr => + (MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0] : mword 3)) 8) >>= fun mem_val => + (rGPR rt) >>= fun reg_val => + let b__16 := subrange_vec_dec vAddr 2 0 in + (wGPR rt + (if ((eq_vec b__16 (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1)))) then mem_val + else if ((eq_vec b__16 (vec_of_bits [B0;B0;B1] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 55 0) (subrange_vec_dec reg_val 7 0) + else if ((eq_vec b__16 (vec_of_bits [B0;B1;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 47 0) (subrange_vec_dec reg_val 15 0) + else if ((eq_vec b__16 (vec_of_bits [B0;B1;B1] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 39 0) (subrange_vec_dec reg_val 23 0) + else if ((eq_vec b__16 (vec_of_bits [B1;B0;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 31 0) (subrange_vec_dec reg_val 31 0) + else if ((eq_vec b__16 (vec_of_bits [B1;B0;B1] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 23 0) (subrange_vec_dec reg_val 39 0) + else if ((eq_vec b__16 (vec_of_bits [B1;B1;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 15 0) (subrange_vec_dec reg_val 47 0) + else concat_vec (subrange_vec_dec mem_val 7 0) (subrange_vec_dec reg_val 55 0))) + : M (unit). + +Definition execute_JR (rs : mword 5) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (rGPR rs) >>= fun w__1 : mword 64 => (execute_branch w__1) : M (unit). + +Definition execute_JALR (rs : mword 5) (rd : mword 5) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (rGPR rs) >>= fun w__1 : mword 64 => + (execute_branch w__1) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + (wGPR rd (add_vec_int w__2 8)) + : M (unit). + +Definition execute_JAL (offset : mword 26) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + (execute_branch + (concat_vec (subrange_vec_dec (add_vec_int w__1 4) 63 28) + (concat_vec offset (vec_of_bits [B0;B0] : mword 2)))) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + (wGPR (vec_of_bits [B1;B1;B1;B1;B1] : mword 5) (add_vec_int w__2 8)) + : M (unit). + +Definition execute_J (offset : mword 26) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + (execute_branch + (concat_vec (subrange_vec_dec (add_vec_int w__1 4) 63 28) + (concat_vec offset (vec_of_bits [B0;B0] : mword 2)))) + : M (unit). + +Definition execute_HCF '(tt : unit) : unit := tt. + +Definition execute_ERET '(tt : unit) +: M (unit) := + + (checkCP0Access tt) >> + (ERETHook tt) >> + write_reg CP0LLBit_ref (vec_of_bits [B0] : mword 1) >> + read_reg CP0Status_ref >>= fun w__0 : StatusReg => + (if ((Bool.eqb ((bits_to_bool (_get_StatusReg_ERL w__0)) : bool) ((bit_to_bool B1) : bool))) + then + ((read_reg CP0ErrorEPC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + write_reg NextPC_ref w__1 >> + (_set_StatusReg_ERL CP0Status_ref (vec_of_bits [B0] : mword 1)) + : M (unit) + else + ((read_reg CP0EPC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + write_reg NextPC_ref w__2 >> + (_set_StatusReg_EXL CP0Status_ref (vec_of_bits [B0] : mword 1)) + : M (unit)) + : M (unit). + +Definition execute_DSUBU (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (sub_vec w__0 w__1)) : M (unit). + +Definition execute_DSUB (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => + let temp65 : bits 65 := sub_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 w__1) in + (if ((neq_bool ((bit_to_bool (access_vec_dec temp65 64)) : bool) + ((bit_to_bool (access_vec_dec temp65 63)) + : bool))) then + (SignalException Ov) + : M (unit) + else (wGPR rd (subrange_vec_dec temp65 63 0)) : M (unit)) + : M (unit). + +Definition execute_DSRLV (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (rGPR rs) >>= fun w__0 : mword 64 => + let sa := subrange_vec_dec w__0 5 0 in + (shift_bits_right temp sa) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit). + +Definition execute_DSRL32 (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + let sa32 := concat_vec (vec_of_bits [B1] : mword 1) sa in + (shift_bits_right temp sa32) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit). + +Definition execute_DSRL (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (shift_bits_right temp sa) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit). + +Definition execute_DSRAV (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (rGPR rs) >>= fun w__0 : mword 64 => + let sa := subrange_vec_dec w__0 5 0 in + (shift_bits_right_arith temp sa) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit). + +Definition execute_DSRA32 (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + let sa32 := concat_vec (vec_of_bits [B1] : mword 1) sa in + (shift_bits_right_arith temp sa32) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit). + +Definition execute_DSRA (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (shift_bits_right_arith temp sa) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit). + +Definition execute_DSLLV (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun w__0 : mword 64 => + (rGPR rs) >>= fun w__1 : mword 64 => + (shift_bits_left w__0 (subrange_vec_dec w__1 5 0)) >>= fun w__2 : mword 64 => + (wGPR rd w__2) + : M (unit). + +Definition execute_DSLL32 (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun w__0 : mword 64 => + (shift_bits_left w__0 (concat_vec (vec_of_bits [B1] : mword 1) sa)) >>= fun w__1 : mword 64 => + (wGPR rd w__1) + : M (unit). + +Definition execute_DSLL (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun w__0 : mword 64 => + (shift_bits_left w__0 sa) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit). + +Definition execute_DMULTU (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => + let result := mult_vec w__0 w__1 in + write_reg HI_ref (subrange_vec_dec result 127 64) >> + write_reg LO_ref (subrange_vec_dec result 63 0) + : M (unit). + +Definition execute_DMULT (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => + let result := mults_vec w__0 w__1 in + write_reg HI_ref (subrange_vec_dec result 127 64) >> + write_reg LO_ref (subrange_vec_dec result 63 0) + : M (unit). + +Definition execute_DIVU (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) + (orb (NotWordVal rtVal) + (eq_vec rtVal + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))))) then + (undefined_bitvector 32) >>= fun w__0 : mword 32 => + (undefined_bitvector 32) >>= fun w__1 : mword 32 => returnm (w__0 : bits 32, w__1 : bits 32) + else + let 'si := projT1 (uint (subrange_vec_dec rsVal 31 0)) in + let 'ti := projT1 (uint (subrange_vec_dec rtVal 31 0)) in + let qi := Z.quot si ti in + let ri := Z.rem si ti in + returnm (to_bits 32 qi, to_bits 32 ri)) >>= fun '(q, r) => + write_reg HI_ref (mips_sign_extend 64 r) >> write_reg LO_ref (mips_sign_extend 64 q) : M (unit). + +Definition execute_DIV (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) + (orb (NotWordVal rtVal) + (eq_vec rtVal + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))))) then + (undefined_bitvector 32) >>= fun w__0 : mword 32 => + (undefined_bitvector 32) >>= fun w__1 : mword 32 => returnm (w__0 : bits 32, w__1 : bits 32) + else + let 'si := projT1 (sint (subrange_vec_dec rsVal 31 0)) in + let 'ti := projT1 (sint (subrange_vec_dec rtVal 31 0)) in + let qi := Z.quot si ti in + let ri := Z.sub si (Z.mul ti qi) in + returnm (to_bits 32 qi, to_bits 32 ri)) >>= fun '(q, r) => + write_reg HI_ref (mips_sign_extend 64 r) >> write_reg LO_ref (mips_sign_extend 64 q) : M (unit). + +Definition execute_DDIVU (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + let 'rsVal := projT1 (uint w__0) in + (rGPR rt) >>= fun w__1 : mword 64 => + let 'rtVal := projT1 (uint w__1) in + (if sumbool_of_bool ((Z.eqb rtVal 0)) then + (undefined_bitvector 64) >>= fun w__2 : mword 64 => + (undefined_bitvector 64) >>= fun w__3 : mword 64 => returnm (w__2 : bits 64, w__3 : bits 64) + else + let qi := Z.quot rsVal rtVal in + let ri := Z.rem rsVal rtVal in + returnm (to_bits 64 qi, to_bits 64 ri)) >>= fun '(q, r) => + write_reg LO_ref q >> write_reg HI_ref r : M (unit). + +Definition execute_DDIV (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + let 'rsVal := projT1 (sint w__0) in + (rGPR rt) >>= fun w__1 : mword 64 => + let 'rtVal := projT1 (sint w__1) in + (if sumbool_of_bool ((Z.eqb rtVal 0)) then + (undefined_bitvector 64) >>= fun w__2 : mword 64 => + (undefined_bitvector 64) >>= fun w__3 : mword 64 => returnm (w__2 : bits 64, w__3 : bits 64) + else + let qi := Z.quot rsVal rtVal in + let ri := Z.sub rsVal (Z.mul qi rtVal) in + returnm (to_bits 64 qi, to_bits 64 ri)) >>= fun '(q, r) => + write_reg LO_ref q >> write_reg HI_ref r : M (unit). + +Definition execute_DADDU (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (add_vec w__0 w__1)) : M (unit). + +Definition execute_DADDIU (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (wGPR rt (add_vec w__0 (mips_sign_extend 64 imm))) + : M (unit). + +Definition execute_DADDI (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + let sum65 : bits 65 := add_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 imm) in + (if ((neq_bool ((bit_to_bool (access_vec_dec sum65 64)) : bool) + ((bit_to_bool (access_vec_dec sum65 63)) + : bool))) then + (SignalException Ov) + : M (unit) + else (wGPR rt (subrange_vec_dec sum65 63 0)) : M (unit)) + : M (unit). + +Definition execute_DADD (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => + let sum65 : bits 65 := add_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 w__1) in + (if ((neq_bool ((bit_to_bool (access_vec_dec sum65 64)) : bool) + ((bit_to_bool (access_vec_dec sum65 63)) + : bool))) then + (SignalException Ov) + : M (unit) + else (wGPR rd (subrange_vec_dec sum65 63 0)) : M (unit)) + : M (unit). + +Definition execute_ClearRegs (regset : ClearRegSet) (m : mword 16) +: M (unit) := + + (if ((orb (generic_eq regset CLo) (generic_eq regset CHi))) then (checkCP2usable tt) : M (unit) + else returnm (tt : unit)) >> + (foreach_ZM_up 0 15 1 tt + (fun i _ unit_var => + (if (((bit_to_bool (access_vec_dec m i)) : bool)) then + (match regset with + | GPLo => (wGPR (to_bits 5 i) (zeros_implicit 64 tt)) : M (unit) + | GPHi => (wGPR (to_bits 5 (Z.add i 16)) (zeros_implicit 64 tt)) : M (unit) + | CLo => + (if sumbool_of_bool ((Z.eqb i 0)) then write_reg DDC_ref null_cap : M (unit) + else (writeCapReg (to_bits 5 i) null_cap) : M (unit)) + : M (unit) + | CHi => (writeCapReg (to_bits 5 (Z.add i 16)) null_cap) : M (unit) + end) + : M (unit) + else returnm (tt : unit)) + : M (unit))) + : M (unit). + +Definition execute_CWriteHwr (cb : mword 5) (sel : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + let 'p0_ := projT1 (uint sel) in + (if sumbool_of_bool ((Z.eqb p0_ 0)) then returnm (false, false) + else if sumbool_of_bool ((Z.eqb p0_ 1)) then returnm (false, false) + else if sumbool_of_bool ((Z.eqb p0_ 8)) then returnm (false, true) + else if sumbool_of_bool ((Z.eqb p0_ 22)) then returnm (true, false) + else if sumbool_of_bool ((Z.eqb p0_ 23)) then returnm (true, false) + else if sumbool_of_bool ((Z.eqb p0_ 29)) then returnm (true, true) + else if sumbool_of_bool ((Z.eqb p0_ 30)) then returnm (true, true) + else if sumbool_of_bool ((Z.eqb p0_ 31)) then returnm (true, true) + else (SignalException ResI) : M ((bool * bool))) >>= fun '(needSup, needAccessSys) => + (and_boolM (returnm (needAccessSys : bool)) + ((pcc_access_system_regs tt) >>= fun w__8 : bool => returnm ((negb w__8) : bool))) >>= fun w__9 : bool => + (if (w__9) then (raise_c2_exception CapEx_AccessSystemRegsViolation sel) : M (unit) + else + (and_boolM (returnm (needSup : bool)) + ((getAccessLevel tt) >>= fun w__10 : AccessLevel => + returnm ((negb (grantsAccess w__10 Supervisor)) + : bool))) >>= fun w__11 : bool => + (if (w__11) then (raise_c2_exception CapEx_AccessSystemRegsViolation sel) : M (unit) + else + (readCapReg cb) >>= fun capVal => + let 'p0_ := projT1 (uint sel) in + (if sumbool_of_bool ((Z.eqb p0_ 0)) then write_reg DDC_ref capVal : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 1)) then write_reg CTLSU_ref capVal : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 8)) then write_reg CTLSP_ref capVal : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 22)) then write_reg KR1C_ref capVal : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 23)) then write_reg KR2C_ref capVal : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 29)) then write_reg KCC_ref capVal : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 30)) then write_reg KDC_ref capVal : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 31)) then + write_reg EPCC_ref capVal >> + read_reg CP0Status_ref >>= fun w__12 : StatusReg => + (if (((bits_to_bool (_get_StatusReg_ERL w__12)) : bool)) then + write_reg CP0ErrorEPC_ref (to_bits 64 (projT1 (getCapOffset capVal))) + : M (unit) + else write_reg CP0EPC_ref (to_bits 64 (projT1 (getCapOffset capVal))) : M (unit)) + : M (unit) + else (assert_exp false "CWriteHwr: should be unreachable code") : M (unit)) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CUnseal (cd : mword 5) (cs : mword 5) (ct : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cs) >>= fun cs_val => + (readCapReg ct) >>= fun ct_val => + let 'ct_cursor := projT1 (getCapCursor ct_val) in + (if ((negb cs_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cs) : M (unit) + else if ((negb ct_val.(Capability_tag))) then + (raise_c2_exception CapEx_TagViolation ct) + : M (unit) + else if ((negb cs_val.(Capability_sealed))) then + (raise_c2_exception CapEx_SealViolation cs) + : M (unit) + else if (ct_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation ct) + : M (unit) + else if ((neq_int ct_cursor (projT1 (uint cs_val.(Capability_otype))))) then + (raise_c2_exception CapEx_TypeViolation ct) + : M (unit) + else if ((negb ct_val.(Capability_permit_unseal))) then + (raise_c2_exception CapEx_PermitUnsealViolation ct) + : M (unit) + else if sumbool_of_bool ((Z.ltb ct_cursor (projT1 (getCapBase ct_val)))) then + (raise_c2_exception CapEx_LengthViolation ct) + : M (unit) + else if sumbool_of_bool ((Z.geb ct_cursor (projT1 (getCapTop ct_val)))) then + (raise_c2_exception CapEx_LengthViolation ct) + : M (unit) + else + (writeCapReg cd + {| Capability_tag := cs_val.(Capability_tag); + Capability_padding := cs_val.(Capability_padding); + Capability_otype := (zeros_implicit 24 tt); + Capability_uperms := cs_val.(Capability_uperms); + Capability_perm_reserved12_14 := cs_val.(Capability_perm_reserved12_14); + Capability_permit_set_CID := cs_val.(Capability_permit_set_CID); + Capability_access_system_regs := cs_val.(Capability_access_system_regs); + Capability_permit_unseal := cs_val.(Capability_permit_unseal); + Capability_permit_ccall := cs_val.(Capability_permit_ccall); + Capability_permit_seal := cs_val.(Capability_permit_seal); + Capability_permit_store_local_cap := cs_val.(Capability_permit_store_local_cap); + Capability_permit_store_cap := cs_val.(Capability_permit_store_cap); + Capability_permit_load_cap := cs_val.(Capability_permit_load_cap); + Capability_permit_store := cs_val.(Capability_permit_store); + Capability_permit_load := cs_val.(Capability_permit_load); + Capability_permit_execute := cs_val.(Capability_permit_execute); + Capability_global := (andb cs_val.(Capability_global) ct_val.(Capability_global)); + Capability_sealed := false; + Capability_address := cs_val.(Capability_address); + Capability_base := cs_val.(Capability_base); + Capability_length := cs_val.(Capability_length) |}) + : M (unit)) + : M (unit). + +Definition execute_CToPtr (rd : mword 5) (cb : mword 5) (ct : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC ct) >>= fun ct_val => + (readCapReg cb) >>= fun cb_val => + (if ((negb ct_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation ct) : M (unit) + else if ((andb cb_val.(Capability_tag) cb_val.(Capability_sealed))) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else + let 'ctBase := projT1 (getCapBase ct_val) in + (wGPR rd + (if ((negb cb_val.(Capability_tag))) then zeros_implicit 64 tt + else to_bits 64 (Z.sub (projT1 (getCapCursor cb_val)) ctBase))) + : M (unit)) + : M (unit). + +Definition execute_CTestSubset (rd : mword 5) (cb : mword 5) (ct : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (readCapReg ct) >>= fun ct_val => + let 'ct_top := projT1 (getCapTop ct_val) in + let 'ct_base := projT1 (getCapBase ct_val) in + let ct_perms := getCapPerms ct_val in + let 'cb_top := projT1 (getCapTop cb_val) in + let 'cb_base := projT1 (getCapBase cb_val) in + let cb_perms := getCapPerms cb_val in + let result := + if ((neq_bool cb_val.(Capability_tag) ct_val.(Capability_tag))) then + (vec_of_bits [B0] : mword 1) + else if sumbool_of_bool ((Z.ltb ct_base cb_base)) then (vec_of_bits [B0] : mword 1) + else if sumbool_of_bool ((Z.gtb ct_top cb_top)) then (vec_of_bits [B0] : mword 1) + else if ((neq_vec (and_vec ct_perms cb_perms) ct_perms)) then (vec_of_bits [B0] : mword 1) + else (vec_of_bits [B1] : mword 1) in + (wGPR rd (mips_zero_extend 64 result)) + : M (unit). + +Definition execute_CSub (rd : mword 5) (cb : mword 5) (ct : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg ct) >>= fun ct_val => + (readCapReg cb) >>= fun cb_val => + (wGPR rd (to_bits 64 (Z.sub (projT1 (getCapCursor cb_val)) (projT1 (getCapCursor ct_val))))) + : M (unit). + +Definition execute_CStoreConditional (rs : mword 5) (cb : mword 5) (rd : mword 5) (width : WordType) + +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_store))) then + (raise_c2_exception CapEx_PermitStoreViolation cb) + : M (unit) + else + let 'size := projT1 (wordWidthBytes width) in + let 'vAddr := projT1 (getCapCursor cb_val) in + let vAddr64 := to_bits 64 vAddr in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr size) (projT1 (getCapTop cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb vAddr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((negb (isAddressAligned vAddr64 width))) then + (SignalExceptionBadAddr AdES vAddr64) + : M (unit) + else + (TLBTranslate vAddr64 StoreData) >>= fun pAddr => + (rGPR rs) >>= fun rs_val => + ((read_reg CP0LLBit_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bit_to_bool (access_vec_dec w__0 0)) : bool)) then + (match width with + | B => (MEMw_conditional_wrapper pAddr 1 (subrange_vec_dec rs_val 7 0)) : M (bool) + | H => (MEMw_conditional_wrapper pAddr 2 (subrange_vec_dec rs_val 15 0)) : M (bool) + | W => (MEMw_conditional_wrapper pAddr 4 (subrange_vec_dec rs_val 31 0)) : M (bool) + | D => (MEMw_conditional_wrapper pAddr 8 rs_val) : M (bool) + end) + : M (bool) + else returnm (false : bool)) >>= fun success : bool => + (wGPR rd (mips_zero_extend 64 (bool_to_bits success))) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CStore +(rs : mword 5) (cb : mword 5) (rt : mword 5) (offset : mword 8) (width : WordType) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_store))) then + (raise_c2_exception CapEx_PermitStoreViolation cb) + : M (unit) + else + let 'size := projT1 (wordWidthBytes width) in + let 'cursor := projT1 (getCapCursor cb_val) in + (rGPR rt) >>= fun w__0 : mword 64 => + let 'vAddr := + projT1 (emod_with_eq + (Z.add (Z.add cursor (projT1 (uint w__0))) (Z.mul size (projT1 (sint offset)))) + (projT1 (pow2 64))) in + let vAddr64 := to_bits 64 vAddr in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr size) (projT1 (getCapTop cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb vAddr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((negb (isAddressAligned vAddr64 width))) then + (SignalExceptionBadAddr AdES vAddr64) + : M (unit) + else + (TLBTranslate vAddr64 StoreData) >>= fun pAddr => + (rGPR rs) >>= fun rs_val => + (match width with + | B => (MEMw_wrapper pAddr 1 (subrange_vec_dec rs_val 7 0)) : M (unit) + | H => (MEMw_wrapper pAddr 2 (subrange_vec_dec rs_val 15 0)) : M (unit) + | W => (MEMw_wrapper pAddr 4 (subrange_vec_dec rs_val 31 0)) : M (unit) + | D => (MEMw_wrapper pAddr 8 rs_val) : M (unit) + end) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CSetOffset (cd : mword 5) (cb : mword 5) (rt : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + (rGPR rt) >>= fun rt_val => + (if ((andb cb_val.(Capability_tag) cb_val.(Capability_sealed))) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else + let '(success, newCap) := setCapOffset cb_val rt_val in + (if (success) then (writeCapReg cd newCap) : M (unit) + else + (writeCapReg cd (int_to_cap (add_vec (to_bits 64 (projT1 (getCapBase cb_val))) rt_val))) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CSetCause (rt : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (pcc_access_system_regs tt) >>= fun w__0 : bool => + (if ((negb w__0)) then (raise_c2_exception_noreg CapEx_AccessSystemRegsViolation) : M (unit) + else + (rGPR rt) >>= fun rt_val => + (_set_CapCauseReg_ExcCode CapCause_ref (subrange_vec_dec rt_val 15 8)) >> + (_set_CapCauseReg_RegNum CapCause_ref (subrange_vec_dec rt_val 7 0)) + : M (unit)) + : M (unit). + +Definition execute_CSetCID (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_set_CID))) then + (raise_c2_exception CapEx_PermitSetCIDViolation cb) + : M (unit) + else + let 'addr := projT1 (getCapCursor cb_val) in + (if sumbool_of_bool ((Z.ltb addr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.geb addr (projT1 (getCapTop cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else write_reg CID_ref (to_bits 64 addr) : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CSetBoundsImmediate (cd : mword 5) (cb : mword 5) (imm : mword 11) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + let 'immU := projT1 (uint imm) in + let 'cursor := projT1 (getCapCursor cb_val) in + let 'base := projT1 (getCapBase cb_val) in + let 'top := projT1 (getCapTop cb_val) in + let newTop := Z.add cursor immU in + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb cursor base)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.gtb newTop top)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else + let '(_, newCap) := setCapBounds cb_val (to_bits 64 cursor) (to_bits 65 newTop) in + (writeCapReg cd newCap) + : M (unit)) + : M (unit). + +Definition execute_CSetBoundsExact (cd : mword 5) (cb : mword 5) (rt : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + (rGPR rt) >>= fun w__0 : mword 64 => + let 'rt_val := projT1 (uint w__0) in + let 'cursor := projT1 (getCapCursor cb_val) in + let 'base := projT1 (getCapBase cb_val) in + let 'top := projT1 (getCapTop cb_val) in + let newTop := Z.add cursor rt_val in + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb cursor base)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.gtb newTop top)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else + let '(exact, newCap) := setCapBounds cb_val (to_bits 64 cursor) (to_bits 65 newTop) in + (if ((negb exact)) then (raise_c2_exception CapEx_InexactBounds cb) : M (unit) + else (writeCapReg cd newCap) : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CSetBounds (cd : mword 5) (cb : mword 5) (rt : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + (rGPR rt) >>= fun w__0 : mword 64 => + let 'rt_val := projT1 (uint w__0) in + let 'cursor := projT1 (getCapCursor cb_val) in + let 'base := projT1 (getCapBase cb_val) in + let 'top := projT1 (getCapTop cb_val) in + let newTop := Z.add cursor rt_val in + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb cursor base)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.gtb newTop top)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else + let '(_, newCap) := setCapBounds cb_val (to_bits 64 cursor) (to_bits 65 newTop) in + (writeCapReg cd newCap) + : M (unit)) + : M (unit). + +Definition execute_CSeal (cd : mword 5) (cs : mword 5) (ct : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cs) >>= fun cs_val => + (readCapReg ct) >>= fun ct_val => + let 'ct_cursor := projT1 (getCapCursor ct_val) in + let 'ct_top := projT1 (getCapTop ct_val) in + let 'ct_base := projT1 (getCapBase ct_val) in + (if ((negb cs_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cs) : M (unit) + else if ((negb ct_val.(Capability_tag))) then + (raise_c2_exception CapEx_TagViolation ct) + : M (unit) + else if (cs_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cs) + : M (unit) + else if (ct_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation ct) + : M (unit) + else if ((negb ct_val.(Capability_permit_seal))) then + (raise_c2_exception CapEx_PermitSealViolation ct) + : M (unit) + else if sumbool_of_bool ((Z.ltb ct_cursor ct_base)) then + (raise_c2_exception CapEx_LengthViolation ct) + : M (unit) + else if sumbool_of_bool ((Z.geb ct_cursor ct_top)) then + (raise_c2_exception CapEx_LengthViolation ct) + : M (unit) + else if sumbool_of_bool ((Z.gtb ct_cursor max_otype)) then + (raise_c2_exception CapEx_LengthViolation ct) + : M (unit) + else + let '(success, newCap) := sealCap cs_val (to_bits 24 ct_cursor) in + (if ((negb success)) then (raise_c2_exception CapEx_InexactBounds cs) : M (unit) + else (writeCapReg cd newCap) : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CSCC (cs : mword 5) (cb : mword 5) (rd : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cs) >>= fun cs_val => + (readCapRegDDC cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_store))) then + (raise_c2_exception CapEx_PermitStoreViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_store_cap))) then + (raise_c2_exception CapEx_PermitStoreCapViolation cb) + : M (unit) + else if ((andb (negb cb_val.(Capability_permit_store_local_cap)) + (andb cs_val.(Capability_tag) (negb cs_val.(Capability_global))))) then + (raise_c2_exception CapEx_PermitStoreLocalCapViolation cb) + : M (unit) + else + let 'vAddr := projT1 (getCapCursor cb_val) in + let vAddr64 := to_bits 64 vAddr in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr cap_size) (projT1 (getCapTop cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb vAddr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((neq_int (projT1 (emod_with_eq vAddr cap_size)) 0)) then + (SignalExceptionBadAddr AdES vAddr64) + : M (unit) + else + (TLBTranslateC vAddr64 StoreData) >>= fun '(pAddr, noStoreCap) => + (if ((andb cs_val.(Capability_tag) noStoreCap)) then + (raise_c2_exception CapEx_TLBNoStoreCap cs) + : M (unit) + else + ((read_reg CP0LLBit_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bit_to_bool (access_vec_dec w__0 0)) : bool)) then + (MEMw_tagged_conditional pAddr cs_val.(Capability_tag) (capToMemBits cs_val)) + : M (bool) + else returnm (false : bool)) >>= fun success => + (wGPR rd (mips_zero_extend 64 (bool_to_bits success))) + : M (unit)) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CSC (cs : mword 5) (cb : mword 5) (rt : mword 5) (offset : mword 11) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cs) >>= fun cs_val => + (readCapRegDDC cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_store))) then + (raise_c2_exception CapEx_PermitStoreViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_store_cap))) then + (raise_c2_exception CapEx_PermitStoreCapViolation cb) + : M (unit) + else if ((andb (negb cb_val.(Capability_permit_store_local_cap)) + (andb cs_val.(Capability_tag) (negb cs_val.(Capability_global))))) then + (raise_c2_exception CapEx_PermitStoreLocalCapViolation cb) + : M (unit) + else + let 'cursor := projT1 (getCapCursor cb_val) in + (rGPR rt) >>= fun w__0 : mword 64 => + let 'vAddr := + projT1 (emod_with_eq + (Z.add (Z.add cursor (projT1 (uint w__0))) (Z.mul 16 (projT1 (sint offset)))) + (projT1 (pow2 64))) in + let vAddr64 := to_bits 64 vAddr in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr cap_size) (projT1 (getCapTop cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb vAddr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((neq_int (projT1 (emod_with_eq vAddr cap_size)) 0)) then + (SignalExceptionBadAddr AdES vAddr64) + : M (unit) + else + (TLBTranslateC vAddr64 StoreData) >>= fun '(pAddr, noStoreCap) => + (if ((andb cs_val.(Capability_tag) noStoreCap)) then + (raise_c2_exception CapEx_TLBNoStoreCap cs) + : M (unit) + else (MEMw_tagged pAddr cs_val.(Capability_tag) (capToMemBits cs_val)) : M (unit)) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CReturn '(tt : unit) +: M (unit) := + + (checkCP2usable tt) >> (raise_c2_exception_noreg CapEx_ReturnTrap) : M (unit). + +Definition execute_CReadHwr (cd : mword 5) (sel : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + let 'p0_ := projT1 (uint sel) in + (if sumbool_of_bool ((Z.eqb p0_ 0)) then returnm (false, false) + else if sumbool_of_bool ((Z.eqb p0_ 1)) then returnm (false, false) + else if sumbool_of_bool ((Z.eqb p0_ 8)) then returnm (false, true) + else if sumbool_of_bool ((Z.eqb p0_ 22)) then returnm (true, false) + else if sumbool_of_bool ((Z.eqb p0_ 23)) then returnm (true, false) + else if sumbool_of_bool ((Z.eqb p0_ 29)) then returnm (true, true) + else if sumbool_of_bool ((Z.eqb p0_ 30)) then returnm (true, true) + else if sumbool_of_bool ((Z.eqb p0_ 31)) then returnm (true, true) + else (SignalException ResI) : M ((bool * bool))) >>= fun '(needSup, needAccessSys) => + (and_boolM (returnm (needAccessSys : bool)) + ((pcc_access_system_regs tt) >>= fun w__8 : bool => returnm ((negb w__8) : bool))) >>= fun w__9 : bool => + (if (w__9) then (raise_c2_exception CapEx_AccessSystemRegsViolation sel) : M (unit) + else + (and_boolM (returnm (needSup : bool)) + ((getAccessLevel tt) >>= fun w__10 : AccessLevel => + returnm ((negb (grantsAccess w__10 Supervisor)) + : bool))) >>= fun w__11 : bool => + (if (w__11) then (raise_c2_exception CapEx_AccessSystemRegsViolation sel) : M (unit) + else + let 'p0_ := projT1 (uint sel) in + (if sumbool_of_bool ((Z.eqb p0_ 0)) then read_reg DDC_ref : M (Capability) + else if sumbool_of_bool ((Z.eqb p0_ 1)) then read_reg CTLSU_ref : M (Capability) + else if sumbool_of_bool ((Z.eqb p0_ 8)) then read_reg CTLSP_ref : M (Capability) + else if sumbool_of_bool ((Z.eqb p0_ 22)) then read_reg KR1C_ref : M (Capability) + else if sumbool_of_bool ((Z.eqb p0_ 23)) then read_reg KR2C_ref : M (Capability) + else if sumbool_of_bool ((Z.eqb p0_ 29)) then read_reg KCC_ref : M (Capability) + else if sumbool_of_bool ((Z.eqb p0_ 30)) then read_reg KDC_ref : M (Capability) + else if sumbool_of_bool ((Z.eqb p0_ 31)) then (readEPCC tt) : M (Capability) + else + assert_exp' false "CReadHwr: should be unreachable code" >>= fun _ => + (undefined_Capability tt) + : M (Capability)) >>= fun capVal : Capability => + (writeCapReg cd capVal) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CPtrCmp (rd : mword 5) (cb : mword 5) (ct : mword 5) (op : CPtrCmpOp) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + (readCapReg ct) >>= fun ct_val => + let equal := false in + let ltu := false in + let lts := false in + let '(equal, lts, ltu) := + (if ((neq_bool cb_val.(Capability_tag) ct_val.(Capability_tag))) then + let '(lts, ltu) := + (if ((negb cb_val.(Capability_tag))) then + let ltu : bool := true in + let lts : bool := true in + (lts, ltu) + else (lts, ltu)) + : (bool * bool) in + (equal, lts, ltu) + else + let 'cursor1 := projT1 (getCapCursor cb_val) in + let 'cursor2 := projT1 (getCapCursor ct_val) in + let equal : bool := Z.eqb cursor1 cursor2 in + let ltu : bool := Z.ltb cursor1 cursor2 in + let lts : bool := zopz0zI_s (to_bits 64 cursor1) (to_bits 64 cursor2) in + (equal, lts, ltu)) + : (bool * bool * bool) in + let cmp : bool := + match op with + | CEQ => equal + | CNE => negb equal + | CLT => lts + | CLE => orb lts equal + | CLTU => ltu + | CLEU => orb ltu equal + | CEXEQ => generic_eq cb_val ct_val + | CNEXEQ => generic_neq cb_val ct_val + end in + (wGPR rd (mips_zero_extend 64 (bool_to_bits cmp))) + : M (unit). + +Definition execute_CMOVX (cd : mword 5) (cb : mword 5) (rt : mword 5) (ismovn : bool) +: M (unit) := + + (checkCP2usable tt) >> + (rGPR rt) >>= fun w__0 : mword 64 => + (if (((bits_to_bool + (xor_vec (bool_to_bits (eq_vec w__0 (zeros_implicit 64 tt))) + ((bool_to_bits ismovn) + : mword 1))) + : bool)) then + (readCapReg cb) >>= fun w__1 : Capability => (writeCapReg cd w__1) : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_CLoadTags (rd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_load))) then + (raise_c2_exception CapEx_PermitLoadViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_load_cap))) then + (raise_c2_exception CapEx_PermitLoadViolation cb) + : M (unit) + else + let 'vAddr := projT1 (getCapCursor cb_val) in + let vAddr64 := to_bits 64 (projT1 (getCapCursor cb_val)) in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr (Z.mul 8 cap_size)) (projT1 (getCapTop cb_val)))) + then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb vAddr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((negb + (eq_vec (subrange_vec_dec vAddr64 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + (SignalExceptionBadAddr AdEL vAddr64) + : M (unit) + else + (TLBTranslate vAddr64 LoadData) >>= fun pAddr => + (read_tag_bool (add_vec_int pAddr (Z.mul 0 cap_size))) >>= fun tag0 => + (read_tag_bool (add_vec_int pAddr (Z.mul 1 cap_size))) >>= fun tag1 => + (read_tag_bool (add_vec_int pAddr (Z.mul 2 cap_size))) >>= fun tag2 => + (read_tag_bool (add_vec_int pAddr (Z.mul 3 cap_size))) >>= fun tag3 => + (read_tag_bool (add_vec_int pAddr (Z.mul 4 cap_size))) >>= fun tag4 => + (read_tag_bool (add_vec_int pAddr (Z.mul 5 cap_size))) >>= fun tag5 => + (read_tag_bool (add_vec_int pAddr (Z.mul 6 cap_size))) >>= fun tag6 => + (read_tag_bool (add_vec_int pAddr (Z.mul 7 cap_size))) >>= fun tag7 => + (wGPR rd + (mips_zero_extend 64 + (concat_vec (bool_to_bits tag7) + (concat_vec (bool_to_bits tag6) + (concat_vec (bool_to_bits tag5) + (concat_vec (bool_to_bits tag4) + (concat_vec (bool_to_bits tag3) + (concat_vec (bool_to_bits tag2) + (concat_vec (bool_to_bits tag1) (bool_to_bits tag0)))))))))) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CLoadLinked (rd : mword 5) (cb : mword 5) (signext : bool) (width : WordType) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_load))) then + (raise_c2_exception CapEx_PermitLoadViolation cb) + : M (unit) + else + let 'size := projT1 (wordWidthBytes width) in + let 'vAddr := projT1 (getCapCursor cb_val) in + let vAddr64 := to_bits 64 vAddr in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr size) (projT1 (getCapTop cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb vAddr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((negb (isAddressAligned vAddr64 width))) then + (SignalExceptionBadAddr AdEL vAddr64) + : M (unit) + else + (TLBTranslate vAddr64 LoadData) >>= fun pAddr => + (MEMr_reserve_wrapper pAddr size) >>= fun w__0 : mword (8 * size) => + let memResult : bits 64 := extendLoad w__0 signext in + write_reg CP0LLBit_ref (vec_of_bits [B1] : mword 1) >> + write_reg CP0LLAddr_ref pAddr >> (wGPR rd memResult) : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CLoad +(rd : mword 5) (cb : mword 5) (rt : mword 5) (offset : mword 8) (signext : bool) (width : WordType) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_load))) then + (raise_c2_exception CapEx_PermitLoadViolation cb) + : M (unit) + else + let 'size := projT1 (wordWidthBytes width) in + let 'cursor := projT1 (getCapCursor cb_val) in + (rGPR rt) >>= fun w__0 : mword 64 => + let 'vAddr := + projT1 (emod_with_eq + (Z.add (Z.add cursor (projT1 (uint w__0))) (Z.mul size (projT1 (sint offset)))) + (projT1 (pow2 64))) in + let vAddr64 := to_bits 64 vAddr in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr size) (projT1 (getCapTop cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb vAddr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((negb (isAddressAligned vAddr64 width))) then + (SignalExceptionBadAddr AdEL vAddr64) + : M (unit) + else + (TLBTranslate vAddr64 LoadData) >>= fun pAddr => + (MEMr_wrapper pAddr size) >>= fun w__1 : mword (8 * size) => + let memResult : bits 64 := extendLoad w__1 signext in + (wGPR rd memResult) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CLLC (cd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_load))) then + (raise_c2_exception CapEx_PermitLoadViolation cb) + : M (unit) + else + let 'vAddr := projT1 (getCapCursor cb_val) in + let vAddr64 := to_bits 64 vAddr in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr cap_size) (projT1 (getCapTop cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb vAddr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((neq_int (projT1 (emod_with_eq vAddr cap_size)) 0)) then + (SignalExceptionBadAddr AdEL vAddr64) + : M (unit) + else + (TLBTranslateC vAddr64 LoadData) >>= fun '(pAddr, suppressTag) => + (MEMr_tagged_reserve pAddr) >>= fun '(tag, mem) => + let cap := + memBitsToCapability + (andb tag (andb cb_val.(Capability_permit_load_cap) (negb suppressTag))) mem in + (writeCapReg cd cap) >> + write_reg CP0LLBit_ref (vec_of_bits [B1] : mword 1) >> + write_reg CP0LLAddr_ref pAddr + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CLCBI (cd : mword 5) (cb : mword 5) (offset : mword 16) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_load))) then + (raise_c2_exception CapEx_PermitLoadViolation cb) + : M (unit) + else + let 'cursor := projT1 (getCapCursor cb_val) in + let 'vAddr := + projT1 (emod_with_eq (Z.add cursor (Z.mul 16 (projT1 (sint offset)))) (projT1 (pow2 64))) in + let vAddr64 := to_bits 64 vAddr in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr cap_size) (projT1 (getCapTop cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb vAddr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((neq_int (projT1 (emod_with_eq vAddr cap_size)) 0)) then + (SignalExceptionBadAddr AdEL vAddr64) + : M (unit) + else + (TLBTranslateC vAddr64 LoadData) >>= fun '(pAddr, suppressTag) => + (MEMr_tagged pAddr) >>= fun '(tag, mem) => + let cap := + memBitsToCapability + (andb tag (andb cb_val.(Capability_permit_load_cap) (negb suppressTag))) mem in + (writeCapReg cd cap) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CLC (cd : mword 5) (cb : mword 5) (rt : mword 5) (offset : mword 11) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_load))) then + (raise_c2_exception CapEx_PermitLoadViolation cb) + : M (unit) + else + let 'cursor := projT1 (getCapCursor cb_val) in + (rGPR rt) >>= fun w__0 : mword 64 => + let 'vAddr := + projT1 (emod_with_eq + (Z.add (Z.add cursor (projT1 (uint w__0))) (Z.mul 16 (projT1 (sint offset)))) + (projT1 (pow2 64))) in + let vAddr64 := to_bits 64 vAddr in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr cap_size) (projT1 (getCapTop cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb vAddr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((neq_int (projT1 (emod_with_eq vAddr cap_size)) 0)) then + (SignalExceptionBadAddr AdEL vAddr64) + : M (unit) + else + (TLBTranslateC vAddr64 LoadData) >>= fun '(pAddr, suppressTag) => + (MEMr_tagged pAddr) >>= fun '(tag, mem) => + let cap := + memBitsToCapability + (andb tag (andb cb_val.(Capability_permit_load_cap) (negb suppressTag))) mem in + (writeCapReg cd cap) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CJALR (cd : mword 5) (cb : mword 5) (link : bool) +: M (unit) := + + (checkCP2usable tt) >> + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (readCapReg cb) >>= fun cb_val => + let 'cb_ptr := projT1 (getCapCursor cb_val) in + let 'cb_top := projT1 (getCapTop cb_val) in + let 'cb_base := projT1 (getCapBase cb_val) in + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_execute))) then + (raise_c2_exception CapEx_PermitExecuteViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb cb_ptr cb_base)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.gtb (Z.add cb_ptr 4) cb_top)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((neq_int (projT1 (emod_with_eq cb_ptr 4)) 0)) then (SignalException AdEL) : M (unit) + else + (if (link) then + read_reg PCC_ref >>= fun w__1 : Capability => + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + let '(success, linkCap) := setCapOffset w__1 (add_vec_int w__2 8) in + assert_exp' success "Link cap should always be representable." >>= fun _ => + (writeCapReg cd linkCap) + : M (unit) + else returnm (tt : unit)) >> + (execute_branch_pcc cb_val) + : M (unit)) >> + write_reg NextInBranchDelay_ref (vec_of_bits [B1] : mword 1) + : M (unit). + +Definition execute_CIncOffsetImmediate (cd : mword 5) (cb : mword 5) (imm : mword 11) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + let imm64 : bits 64 := mips_sign_extend 64 imm in + (if ((andb cb_val.(Capability_tag) cb_val.(Capability_sealed))) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else + let '(success, newCap) := incCapOffset cb_val imm64 in + (if (success) then (writeCapReg cd newCap) : M (unit) + else + (writeCapReg cd (int_to_cap (add_vec (to_bits 64 (projT1 (getCapBase cb_val))) imm64))) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CIncOffset (cd : mword 5) (cb : mword 5) (rt : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + (rGPR rt) >>= fun rt_val => + (if ((andb cb_val.(Capability_tag) + (andb cb_val.(Capability_sealed) + (neq_vec rt_val + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))))) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else + let '(success, newCap) := incCapOffset cb_val rt_val in + (if (success) then (writeCapReg cd newCap) : M (unit) + else + (writeCapReg cd (int_to_cap (add_vec (to_bits 64 (projT1 (getCapBase cb_val))) rt_val))) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CGetType (rd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun capVal => + (wGPR rd + (if (capVal.(Capability_sealed)) then mips_zero_extend 64 capVal.(Capability_otype) + else + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1] + : mword 64))) + : M (unit). + +Definition execute_CGetTag (rd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun capVal => + (wGPR rd (mips_zero_extend 64 (bool_to_bits capVal.(Capability_tag)))) + : M (unit). + +Definition execute_CGetSealed (rd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun capVal => + (wGPR rd (mips_zero_extend 64 (bool_to_bits capVal.(Capability_sealed)))) + : M (unit). + +Definition execute_CGetPerm (rd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun capVal => + (wGPR rd (mips_zero_extend 64 (getCapPerms capVal))) + : M (unit). + +Definition execute_CGetPCCSetOffset (cd : mword 5) (rs : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (rGPR rs) >>= fun rs_val => + read_reg PCC_ref >>= fun w__0 : Capability => + let '(success, newPCC) := setCapOffset w__0 rs_val in + (if (success) then (writeCapReg cd newPCC) : M (unit) + else (writeCapReg cd (int_to_cap rs_val)) : M (unit)) + : M (unit). + +Definition execute_CGetPCC (cd : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + read_reg PCC_ref >>= fun w__0 : Capability => + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + let '(success, pcc) := setCapOffset w__0 w__1 in + assert_exp' success "PCC with offset PC should always be representable" >>= fun _ => + (writeCapReg cd pcc) + : M (unit). + +Definition execute_CGetOffset (rd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun capVal => + (wGPR rd (to_bits 64 (projT1 (getCapOffset capVal)))) + : M (unit). + +Definition execute_CGetLen (rd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun capVal => + let 'len65 := projT1 (getCapLength capVal) in + (wGPR rd (to_bits 64 (if sumbool_of_bool ((Z.gtb len65 MAX_U64)) then MAX_U64 else len65))) + : M (unit). + +Definition execute_CGetCause (rd : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (pcc_access_system_regs tt) >>= fun w__0 : bool => + (if ((negb w__0)) then (raise_c2_exception_noreg CapEx_AccessSystemRegsViolation) : M (unit) + else + read_reg CapCause_ref >>= fun w__1 : CapCauseReg => + (wGPR rd (mips_zero_extend 64 (_get_CapCauseReg_bits w__1))) + : M (unit)) + : M (unit). + +Definition execute_CGetCID (rd : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + ((read_reg CID_ref) : M (mword 64)) >>= fun w__0 : bits 64 => (wGPR rd w__0) : M (unit). + +Definition execute_CGetBase (rd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun capVal => (wGPR rd (to_bits 64 (projT1 (getCapBase capVal)))) : M (unit). + +Definition execute_CGetAddr (rd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun capVal => + (wGPR rd (to_bits 64 (projT1 (getCapCursor capVal)))) + : M (unit). + +Definition execute_CFromPtr (cd : mword 5) (cb : mword 5) (rt : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (rGPR rt) >>= fun rt_val => + (if ((eq_vec rt_val + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))) then + (writeCapReg cd null_cap) + : M (unit) + else if ((negb cb_val.(Capability_tag))) then + (raise_c2_exception CapEx_TagViolation cb) + : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else + let '(success, newCap) := setCapOffset cb_val rt_val in + (if (success) then (writeCapReg cd newCap) : M (unit) + else + (writeCapReg cd (int_to_cap (add_vec (to_bits 64 (projT1 (getCapBase cb_val))) rt_val))) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CCopyType (cd : mword 5) (cb : mword 5) (ct : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + (readCapReg ct) >>= fun ct_val => + let 'cb_base := projT1 (getCapBase cb_val) in + let 'cb_top := projT1 (getCapTop cb_val) in + let 'ct_otype := projT1 (uint ct_val.(Capability_otype)) in + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if (ct_val.(Capability_sealed)) then + (if sumbool_of_bool ((Z.ltb ct_otype cb_base)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.geb ct_otype cb_top)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else + let '(success, cap) := setCapOffset cb_val (to_bits 64 (Z.sub ct_otype cb_base)) in + assert_exp' success "CopyType: offset is in bounds so should be representable" >>= fun _ => + (writeCapReg cd cap) + : M (unit)) + : M (unit) + else + (writeCapReg cd + (int_to_cap + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1] + : mword 64))) + : M (unit)) + : M (unit). + +Definition execute_CClearTag (cd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + (writeCapReg cd {[ cb_val with Capability_tag := false ]}) + : M (unit). + +Definition execute_CCheckType (cs : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cs) >>= fun cs_val => + (readCapReg cb) >>= fun cb_val => + (if ((negb cs_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cs) : M (unit) + else if ((negb cb_val.(Capability_tag))) then + (raise_c2_exception CapEx_TagViolation cb) + : M (unit) + else if ((negb cs_val.(Capability_sealed))) then + (raise_c2_exception CapEx_SealViolation cs) + : M (unit) + else if ((negb cb_val.(Capability_sealed))) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((neq_vec cs_val.(Capability_otype) cb_val.(Capability_otype))) then + (raise_c2_exception CapEx_TypeViolation cs) + : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_CCheckTag (cs : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cs) >>= fun cs_val => + (if ((negb cs_val.(Capability_tag))) then (raise_c2_exception CapEx_TypeViolation cs) : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_CCheckPerm (cs : mword 5) (rt : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cs) >>= fun cs_val => + let cs_perms : bits 64 := mips_zero_extend 64 (getCapPerms cs_val) in + (rGPR rt) >>= fun rt_perms => + (if ((negb cs_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cs) : M (unit) + else if ((neq_vec (and_vec cs_perms rt_perms) rt_perms)) then + (raise_c2_exception CapEx_UserDefViolation cs) + : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_CCall (cs : mword 5) (cb : mword 5) (b__155 : mword 11) +: M (unit) := + + (if ((eq_vec b__155 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11))) then + (checkCP2usable tt) >> + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (readCapReg cs) >>= fun cs_val => + (readCapReg cb) >>= fun cb_val => + let 'cs_cursor := projT1 (getCapCursor cs_val) in + (if ((negb cs_val.(Capability_tag))) then + (raise_c2_exception CapEx_TagViolation cs) + : M (unit) + else if ((negb cb_val.(Capability_tag))) then + (raise_c2_exception CapEx_TagViolation cb) + : M (unit) + else if ((negb cs_val.(Capability_sealed))) then + (raise_c2_exception CapEx_SealViolation cs) + : M (unit) + else if ((negb cb_val.(Capability_sealed))) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((neq_vec cs_val.(Capability_otype) cb_val.(Capability_otype))) then + (raise_c2_exception CapEx_TypeViolation cs) + : M (unit) + else if ((negb cs_val.(Capability_permit_execute))) then + (raise_c2_exception CapEx_PermitExecuteViolation cs) + : M (unit) + else if (cb_val.(Capability_permit_execute)) then + (raise_c2_exception CapEx_PermitExecuteViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb cs_cursor (projT1 (getCapBase cs_val)))) then + (raise_c2_exception CapEx_LengthViolation cs) + : M (unit) + else if sumbool_of_bool ((Z.geb cs_cursor (projT1 (getCapTop cs_val)))) then + (raise_c2_exception CapEx_LengthViolation cs) + : M (unit) + else (raise_c2_exception CapEx_CallTrap cs) : M (unit)) + : M (unit) + else + (checkCP2usable tt) >> + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__1 : bits 1 => + (if (((bits_to_bool w__1) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (readCapReg cs) >>= fun cs_val => + (readCapReg cb) >>= fun cb_val => + let 'cs_cursor := projT1 (getCapCursor cs_val) in + (if ((negb cs_val.(Capability_tag))) then + (raise_c2_exception CapEx_TagViolation cs) + : M (unit) + else if ((negb cb_val.(Capability_tag))) then + (raise_c2_exception CapEx_TagViolation cb) + : M (unit) + else if ((negb cs_val.(Capability_sealed))) then + (raise_c2_exception CapEx_SealViolation cs) + : M (unit) + else if ((negb cb_val.(Capability_sealed))) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((neq_vec cs_val.(Capability_otype) cb_val.(Capability_otype))) then + (raise_c2_exception CapEx_TypeViolation cs) + : M (unit) + else if ((negb cs_val.(Capability_permit_ccall))) then + (raise_c2_exception CapEx_PermitCCallViolation cs) + : M (unit) + else if ((negb cb_val.(Capability_permit_ccall))) then + (raise_c2_exception CapEx_PermitCCallViolation cb) + : M (unit) + else if ((negb cs_val.(Capability_permit_execute))) then + (raise_c2_exception CapEx_PermitExecuteViolation cs) + : M (unit) + else if (cb_val.(Capability_permit_execute)) then + (raise_c2_exception CapEx_PermitExecuteViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb cs_cursor (projT1 (getCapBase cs_val)))) then + (raise_c2_exception CapEx_LengthViolation cs) + : M (unit) + else if sumbool_of_bool ((Z.geb cs_cursor (projT1 (getCapTop cs_val)))) then + (raise_c2_exception CapEx_LengthViolation cs) + : M (unit) + else + (set_next_pcc + {| Capability_tag := cs_val.(Capability_tag); + Capability_padding := cs_val.(Capability_padding); + Capability_otype := (zeros_implicit 24 tt); + Capability_uperms := cs_val.(Capability_uperms); + Capability_perm_reserved12_14 := cs_val.(Capability_perm_reserved12_14); + Capability_permit_set_CID := cs_val.(Capability_permit_set_CID); + Capability_access_system_regs := cs_val.(Capability_access_system_regs); + Capability_permit_unseal := cs_val.(Capability_permit_unseal); + Capability_permit_ccall := cs_val.(Capability_permit_ccall); + Capability_permit_seal := cs_val.(Capability_permit_seal); + Capability_permit_store_local_cap := cs_val.(Capability_permit_store_local_cap); + Capability_permit_store_cap := cs_val.(Capability_permit_store_cap); + Capability_permit_load_cap := cs_val.(Capability_permit_load_cap); + Capability_permit_store := cs_val.(Capability_permit_store); + Capability_permit_load := cs_val.(Capability_permit_load); + Capability_permit_execute := cs_val.(Capability_permit_execute); + Capability_global := cs_val.(Capability_global); + Capability_sealed := false; + Capability_address := cs_val.(Capability_address); + Capability_base := cs_val.(Capability_base); + Capability_length := cs_val.(Capability_length) |}) >> + write_reg + C26_ref + {| Capability_tag := cb_val.(Capability_tag); + Capability_padding := cb_val.(Capability_padding); + Capability_otype := (zeros_implicit 24 tt); + Capability_uperms := cb_val.(Capability_uperms); + Capability_perm_reserved12_14 := cb_val.(Capability_perm_reserved12_14); + Capability_permit_set_CID := cb_val.(Capability_permit_set_CID); + Capability_access_system_regs := cb_val.(Capability_access_system_regs); + Capability_permit_unseal := cb_val.(Capability_permit_unseal); + Capability_permit_ccall := cb_val.(Capability_permit_ccall); + Capability_permit_seal := cb_val.(Capability_permit_seal); + Capability_permit_store_local_cap := cb_val.(Capability_permit_store_local_cap); + Capability_permit_store_cap := cb_val.(Capability_permit_store_cap); + Capability_permit_load_cap := cb_val.(Capability_permit_load_cap); + Capability_permit_store := cb_val.(Capability_permit_store); + Capability_permit_load := cb_val.(Capability_permit_load); + Capability_permit_execute := cb_val.(Capability_permit_execute); + Capability_global := cb_val.(Capability_global); + Capability_sealed := false; + Capability_address := cb_val.(Capability_address); + Capability_base := cb_val.(Capability_base); + Capability_length := cb_val.(Capability_length) |} >> + write_reg NextPC_ref (to_bits 64 (projT1 (getCapOffset cs_val))) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CCSeal (cd : mword 5) (cs : mword 5) (ct : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cs) >>= fun cs_val => + (readCapReg ct) >>= fun ct_val => + let 'ct_cursor := projT1 (getCapCursor ct_val) in + let 'ct_top := projT1 (getCapTop ct_val) in + let 'ct_base := projT1 (getCapBase ct_val) in + (if ((negb cs_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cs) : M (unit) + else if sumbool_of_bool ((orb (negb ct_val.(Capability_tag)) + (Z.eqb (projT1 (getCapCursor ct_val)) MAX_U64))) then + (writeCapReg cd cs_val) + : M (unit) + else if (cs_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cs) + : M (unit) + else if (ct_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation ct) + : M (unit) + else if ((negb ct_val.(Capability_permit_seal))) then + (raise_c2_exception CapEx_PermitSealViolation ct) + : M (unit) + else if sumbool_of_bool ((Z.ltb ct_cursor ct_base)) then + (raise_c2_exception CapEx_LengthViolation ct) + : M (unit) + else if sumbool_of_bool ((Z.geb ct_cursor ct_top)) then + (raise_c2_exception CapEx_LengthViolation ct) + : M (unit) + else if sumbool_of_bool ((Z.gtb ct_cursor max_otype)) then + (raise_c2_exception CapEx_LengthViolation ct) + : M (unit) + else + let '(success, newCap) := sealCap cs_val (to_bits 24 ct_cursor) in + (if ((negb success)) then (raise_c2_exception CapEx_InexactBounds cs) : M (unit) + else (writeCapReg cd newCap) : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CBuildCap (cd : mword 5) (cb : mword 5) (ct : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (readCapReg ct) >>= fun ct_val => + let 'cb_base := projT1 (getCapBase cb_val) in + let 'ct_base := projT1 (getCapBase ct_val) in + let 'cb_top := projT1 (getCapTop cb_val) in + let 'ct_top := projT1 (getCapTop ct_val) in + let cb_perms := getCapPerms cb_val in + let ct_perms := getCapPerms ct_val in + let 'ct_offset := projT1 (getCapOffset ct_val) in + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb ct_base cb_base)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.gtb ct_top cb_top)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.gtb ct_base ct_top)) then + (raise_c2_exception CapEx_LengthViolation ct) + : M (unit) + else if ((neq_vec (and_vec ct_perms cb_perms) ct_perms)) then + (raise_c2_exception CapEx_UserDefViolation cb) + : M (unit) + else + let '(exact, cd1) := setCapBounds cb_val (to_bits 64 ct_base) (to_bits 65 ct_top) in + let '(representable, cd2) := setCapOffset cd1 (to_bits 64 ct_offset) in + let cd3 := setCapPerms cd2 ct_perms in + assert_exp' exact "CBuildCap: setCapBounds was not exact" >>= fun _ => + assert_exp' representable "CBuildCap: offset was not representable" >>= fun _ => + (writeCapReg cd cd3) + : M (unit)) + : M (unit). + +Definition execute_CBZ (cb : mword 5) (imm : mword 16) (notzero : bool) +: M (unit) := + + (checkCP2usable tt) >> + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (readCapReg cb) >>= fun cb_val => + (if (((bits_to_bool + (xor_vec (bool_to_bits (generic_eq cb_val null_cap)) ((bool_to_bits notzero) : mword 1))) + : bool)) then + let offset : bits 64 := + add_vec_int (mips_sign_extend 64 (concat_vec imm (vec_of_bits [B0;B0] : mword 2))) 4 in + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + (execute_branch (add_vec w__1 offset)) + : M (unit) + else returnm (tt : unit)) >> + write_reg NextInBranchDelay_ref (vec_of_bits [B1] : mword 1) + : M (unit). + +Definition execute_CBX (cb : mword 5) (imm : mword 16) (notset : bool) +: M (unit) := + + (checkCP2usable tt) >> + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (readCapReg cb) >>= fun cb_val => + (if (((bits_to_bool + (xor_vec (bool_to_bits cb_val.(Capability_tag)) ((bool_to_bits notset) : mword 1))) + : bool)) then + let offset : bits 64 := + add_vec_int (mips_sign_extend 64 (concat_vec imm (vec_of_bits [B0;B0] : mword 2))) 4 in + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + (execute_branch (add_vec w__1 offset)) + : M (unit) + else returnm (tt : unit)) >> + write_reg NextInBranchDelay_ref (vec_of_bits [B1] : mword 1) + : M (unit). + +Definition execute_CAndPerm (cd : mword 5) (cb : mword 5) (rt : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + (rGPR rt) >>= fun rt_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else + let perms := getCapPerms cb_val in + let newCap := setCapPerms cb_val (and_vec perms (subrange_vec_dec rt_val 30 0)) in + (writeCapReg cd newCap) + : M (unit)) + : M (unit). + +Definition execute_CACHE (base : mword 5) (op : mword 5) (imm : mword 16) +: M (unit) := + + (checkCP0Access tt) + : M (unit). + +Definition execute_C2Dump (rt : mword 5) : unit := tt. + +Definition execute_BREAK '(tt : unit) : M (unit) := (SignalException Bp) : M (unit). + +Definition execute_BEQ (rs : mword 5) (rd : mword 5) (imm : mword 16) (ne : bool) (likely : bool) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (rGPR rs) >>= fun w__1 : mword 64 => + (rGPR rd) >>= fun w__2 : mword 64 => + (if (((bits_to_bool (xor_vec (bool_to_bits (eq_vec w__1 w__2)) ((bool_to_bits ne) : mword 1))) + : bool)) then + let offset : bits 64 := + add_vec_int (mips_sign_extend 64 (concat_vec imm (vec_of_bits [B0;B0] : mword 2))) 4 in + ((read_reg PC_ref) : M (mword 64)) >>= fun w__3 : bits 64 => + (execute_branch (add_vec w__3 offset)) + : M (unit) + else if (likely) then + ((read_reg PC_ref) : M (mword 64)) >>= fun w__4 : bits 64 => + write_reg NextPC_ref (add_vec_int w__4 8) + : M (unit) + else write_reg NextInBranchDelay_ref (vec_of_bits [B1] : mword 1) : M (unit)) + : M (unit). + +Definition execute_BCMPZ +(rs : mword 5) (imm : mword 16) (cmp : Comparison) (link : bool) (likely : bool) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + let linkVal := add_vec_int w__1 8 in + (rGPR rs) >>= fun regVal => + let condition := compare cmp regVal (mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) in + (if (condition) then + let offset : bits 64 := + add_vec_int (mips_sign_extend 64 (concat_vec imm (vec_of_bits [B0;B0] : mword 2))) 4 in + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + (execute_branch (add_vec w__2 offset)) + : M (unit) + else if (likely) then + ((read_reg PC_ref) : M (mword 64)) >>= fun w__3 : bits 64 => + write_reg NextPC_ref (add_vec_int w__3 8) + : M (unit) + else write_reg NextInBranchDelay_ref (vec_of_bits [B1] : mword 1) : M (unit)) >> + (if (link) then (wGPR (vec_of_bits [B1;B1;B1;B1;B1] : mword 5) linkVal) : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_ANDI (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (wGPR rt (and_vec w__0 (mips_zero_extend 64 imm))) + : M (unit). + +Definition execute_AND (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (and_vec w__0 w__1)) : M (unit). + +Definition execute_ADDU (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun opA => + (rGPR rt) >>= fun opB => + (if ((orb (NotWordVal opA) (NotWordVal opB))) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) + else + (wGPR rd + (mips_sign_extend 64 (add_vec (subrange_vec_dec opA 31 0) (subrange_vec_dec opB 31 0)))) + : M (unit)) + : M (unit). + +Definition execute_ADDIU (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun opA => + (if ((NotWordVal opA)) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rt w__0) : M (unit) + else + (wGPR rt (mips_sign_extend 64 (add_vec (subrange_vec_dec opA 31 0) (mips_sign_extend 32 imm)))) + : M (unit)) + : M (unit). + +Definition execute_ADDI (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun opA => + (if ((NotWordVal opA)) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rt w__0) : M (unit) + else + let sum33 : bits 33 := + add_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0)) (mips_sign_extend 33 imm) in + (if ((neq_bool ((bit_to_bool (access_vec_dec sum33 32)) : bool) + ((bit_to_bool (access_vec_dec sum33 31)) + : bool))) then + (SignalException Ov) + : M (unit) + else (wGPR rt (mips_sign_extend 64 (subrange_vec_dec sum33 31 0))) : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_ADD (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun opA : bits 64 => + (rGPR rt) >>= fun opB : bits 64 => + (if ((orb (NotWordVal opA) (NotWordVal opB))) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) + else + let sum33 : bits 33 := + add_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0)) + (mips_sign_extend 33 (subrange_vec_dec opB 31 0)) in + (if ((neq_bool ((bit_to_bool (access_vec_dec sum33 32)) : bool) + ((bit_to_bool (access_vec_dec sum33 31)) + : bool))) then + (SignalException Ov) + : M (unit) + else (wGPR rd (mips_sign_extend 64 (subrange_vec_dec sum33 31 0))) : M (unit)) + : M (unit)) + : M (unit). + +Definition execute (merge_var : ast) +: M (unit) := + + (match merge_var with + | DADDIU (rs,rt,imm) => (execute_DADDIU rs rt imm) : M (unit) + | DADDU (rs,rt,rd) => (execute_DADDU rs rt rd) : M (unit) + | DADDI (rs,rt,imm) => (execute_DADDI rs rt imm) : M (unit) + | DADD (rs,rt,rd) => (execute_DADD rs rt rd) : M (unit) + | ADD (rs,rt,rd) => (execute_ADD rs rt rd) : M (unit) + | ADDI (rs,rt,imm) => (execute_ADDI rs rt imm) : M (unit) + | ADDU (rs,rt,rd) => (execute_ADDU rs rt rd) : M (unit) + | ADDIU (rs,rt,imm) => (execute_ADDIU rs rt imm) : M (unit) + | DSUBU (rs,rt,rd) => (execute_DSUBU rs rt rd) : M (unit) + | DSUB (rs,rt,rd) => (execute_DSUB rs rt rd) : M (unit) + | SUB (rs,rt,rd) => (execute_SUB rs rt rd) : M (unit) + | SUBU (rs,rt,rd) => (execute_SUBU rs rt rd) : M (unit) + | AND (rs,rt,rd) => (execute_AND rs rt rd) : M (unit) + | ANDI (rs,rt,imm) => (execute_ANDI rs rt imm) : M (unit) + | OR (rs,rt,rd) => (execute_OR rs rt rd) : M (unit) + | ORI (rs,rt,imm) => (execute_ORI rs rt imm) : M (unit) + | NOR (rs,rt,rd) => (execute_NOR rs rt rd) : M (unit) + | XOR (rs,rt,rd) => (execute_XOR rs rt rd) : M (unit) + | XORI (rs,rt,imm) => (execute_XORI rs rt imm) : M (unit) + | LUI (rt,imm) => (execute_LUI rt imm) : M (unit) + | DSLL (rt,rd,sa) => (execute_DSLL rt rd sa) : M (unit) + | DSLL32 (rt,rd,sa) => (execute_DSLL32 rt rd sa) : M (unit) + | DSLLV (rs,rt,rd) => (execute_DSLLV rs rt rd) : M (unit) + | DSRA (rt,rd,sa) => (execute_DSRA rt rd sa) : M (unit) + | DSRA32 (rt,rd,sa) => (execute_DSRA32 rt rd sa) : M (unit) + | DSRAV (rs,rt,rd) => (execute_DSRAV rs rt rd) : M (unit) + | DSRL (rt,rd,sa) => (execute_DSRL rt rd sa) : M (unit) + | DSRL32 (rt,rd,sa) => (execute_DSRL32 rt rd sa) : M (unit) + | DSRLV (rs,rt,rd) => (execute_DSRLV rs rt rd) : M (unit) + | SLL (rt,rd,sa) => (execute_SLL rt rd sa) : M (unit) + | SLLV (rs,rt,rd) => (execute_SLLV rs rt rd) : M (unit) + | SRA (rt,rd,sa) => (execute_SRA rt rd sa) : M (unit) + | SRAV (rs,rt,rd) => (execute_SRAV rs rt rd) : M (unit) + | SRL (rt,rd,sa) => (execute_SRL rt rd sa) : M (unit) + | SRLV (rs,rt,rd) => (execute_SRLV rs rt rd) : M (unit) + | SLT (rs,rt,rd) => (execute_SLT rs rt rd) : M (unit) + | SLTI (rs,rt,imm) => (execute_SLTI rs rt imm) : M (unit) + | SLTU (rs,rt,rd) => (execute_SLTU rs rt rd) : M (unit) + | SLTIU (rs,rt,imm) => (execute_SLTIU rs rt imm) : M (unit) + | MOVN (rs,rt,rd) => (execute_MOVN rs rt rd) : M (unit) + | MOVZ (rs,rt,rd) => (execute_MOVZ rs rt rd) : M (unit) + | MFHI (rd) => (execute_MFHI rd) : M (unit) + | MFLO (rd) => (execute_MFLO rd) : M (unit) + | MTHI (rs) => (execute_MTHI rs) : M (unit) + | MTLO (rs) => (execute_MTLO rs) : M (unit) + | MUL (rs,rt,rd) => (execute_MUL rs rt rd) : M (unit) + | MULT (rs,rt) => (execute_MULT rs rt) : M (unit) + | MULTU (rs,rt) => (execute_MULTU rs rt) : M (unit) + | DMULT (rs,rt) => (execute_DMULT rs rt) : M (unit) + | DMULTU (rs,rt) => (execute_DMULTU rs rt) : M (unit) + | MADD (rs,rt) => (execute_MADD rs rt) : M (unit) + | MADDU (rs,rt) => (execute_MADDU rs rt) : M (unit) + | MSUB (rs,rt) => (execute_MSUB rs rt) : M (unit) + | MSUBU (rs,rt) => (execute_MSUBU rs rt) : M (unit) + | DIV (rs,rt) => (execute_DIV rs rt) : M (unit) + | DIVU (rs,rt) => (execute_DIVU rs rt) : M (unit) + | DDIV (rs,rt) => (execute_DDIV rs rt) : M (unit) + | DDIVU (rs,rt) => (execute_DDIVU rs rt) : M (unit) + | J (offset) => (execute_J offset) : M (unit) + | JAL (offset) => (execute_JAL offset) : M (unit) + | JR (rs) => (execute_JR rs) : M (unit) + | JALR (rs,rd) => (execute_JALR rs rd) : M (unit) + | BEQ (rs,rd,imm,ne,likely) => (execute_BEQ rs rd imm ne likely) : M (unit) + | BCMPZ (rs,imm,cmp,link,likely) => (execute_BCMPZ rs imm cmp link likely) : M (unit) + | SYSCALL (arg0) => (execute_SYSCALL arg0) : M (unit) + | BREAK (arg0) => (execute_BREAK arg0) : M (unit) + | WAIT (arg0) => (execute_WAIT arg0) : M (unit) + | TRAPREG (rs,rt,cmp) => (execute_TRAPREG rs rt cmp) : M (unit) + | TRAPIMM (rs,imm,cmp) => (execute_TRAPIMM rs imm cmp) : M (unit) + | Load (width,sign,linked,base,rt,offset) => + (execute_Load width sign linked base rt offset) : M (unit) + | Store (width,conditional,base,rt,offset) => + (execute_Store width conditional base rt offset) : M (unit) + | LWL (base,rt,offset) => (execute_LWL base rt offset) : M (unit) + | LWR (base,rt,offset) => (execute_LWR base rt offset) : M (unit) + | SWL (base,rt,offset) => (execute_SWL base rt offset) : M (unit) + | SWR (base,rt,offset) => (execute_SWR base rt offset) : M (unit) + | LDL (base,rt,offset) => (execute_LDL base rt offset) : M (unit) + | LDR (base,rt,offset) => (execute_LDR base rt offset) : M (unit) + | SDL (base,rt,offset) => (execute_SDL base rt offset) : M (unit) + | SDR (base,rt,offset) => (execute_SDR base rt offset) : M (unit) + | CACHE (base,op,imm) => (execute_CACHE base op imm) : M (unit) + | SYNC (arg0) => (execute_SYNC arg0) : M (unit) + | MFC0 (rt,rd,sel,double) => (execute_MFC0 rt rd sel double) : M (unit) + | HCF (arg0) => returnm ((execute_HCF arg0) : unit) + | MTC0 (rt,rd,sel,double) => (execute_MTC0 rt rd sel double) : M (unit) + | TLBWI (arg0) => (execute_TLBWI arg0) : M (unit) + | TLBWR (arg0) => (execute_TLBWR arg0) : M (unit) + | TLBR (arg0) => (execute_TLBR arg0) : M (unit) + | TLBP (arg0) => (execute_TLBP arg0) : M (unit) + | RDHWR (rt,rd) => (execute_RDHWR rt rd) : M (unit) + | ERET (arg0) => (execute_ERET arg0) : M (unit) + | CGetPerm (rd,cb) => (execute_CGetPerm rd cb) : M (unit) + | CGetType (rd,cb) => (execute_CGetType rd cb) : M (unit) + | CGetBase (rd,cb) => (execute_CGetBase rd cb) : M (unit) + | CGetOffset (rd,cb) => (execute_CGetOffset rd cb) : M (unit) + | CGetLen (rd,cb) => (execute_CGetLen rd cb) : M (unit) + | CGetTag (rd,cb) => (execute_CGetTag rd cb) : M (unit) + | CGetSealed (rd,cb) => (execute_CGetSealed rd cb) : M (unit) + | CGetAddr (rd,cb) => (execute_CGetAddr rd cb) : M (unit) + | CGetPCC (cd) => (execute_CGetPCC cd) : M (unit) + | CGetPCCSetOffset (cd,rs) => (execute_CGetPCCSetOffset cd rs) : M (unit) + | CGetCause (rd) => (execute_CGetCause rd) : M (unit) + | CSetCause (rt) => (execute_CSetCause rt) : M (unit) + | CGetCID (rd) => (execute_CGetCID rd) : M (unit) + | CSetCID (cb) => (execute_CSetCID cb) : M (unit) + | CReadHwr (cd,sel) => (execute_CReadHwr cd sel) : M (unit) + | CWriteHwr (cb,sel) => (execute_CWriteHwr cb sel) : M (unit) + | CAndPerm (cd,cb,rt) => (execute_CAndPerm cd cb rt) : M (unit) + | CToPtr (rd,cb,ct) => (execute_CToPtr rd cb ct) : M (unit) + | CSub (rd,cb,ct) => (execute_CSub rd cb ct) : M (unit) + | CPtrCmp (rd,cb,ct,op) => (execute_CPtrCmp rd cb ct op) : M (unit) + | CIncOffset (cd,cb,rt) => (execute_CIncOffset cd cb rt) : M (unit) + | CIncOffsetImmediate (cd,cb,imm) => (execute_CIncOffsetImmediate cd cb imm) : M (unit) + | CSetOffset (cd,cb,rt) => (execute_CSetOffset cd cb rt) : M (unit) + | CSetBounds (cd,cb,rt) => (execute_CSetBounds cd cb rt) : M (unit) + | CSetBoundsImmediate (cd,cb,imm) => (execute_CSetBoundsImmediate cd cb imm) : M (unit) + | CSetBoundsExact (cd,cb,rt) => (execute_CSetBoundsExact cd cb rt) : M (unit) + | CClearTag (cd,cb) => (execute_CClearTag cd cb) : M (unit) + | CMOVX (cd,cb,rt,ismovn) => (execute_CMOVX cd cb rt ismovn) : M (unit) + | ClearRegs (regset,m) => (execute_ClearRegs regset m) : M (unit) + | CFromPtr (cd,cb,rt) => (execute_CFromPtr cd cb rt) : M (unit) + | CBuildCap (cd,cb,ct) => (execute_CBuildCap cd cb ct) : M (unit) + | CCopyType (cd,cb,ct) => (execute_CCopyType cd cb ct) : M (unit) + | CCheckPerm (cs,rt) => (execute_CCheckPerm cs rt) : M (unit) + | CCheckType (cs,cb) => (execute_CCheckType cs cb) : M (unit) + | CCheckTag (cs) => (execute_CCheckTag cs) : M (unit) + | CTestSubset (rd,cb,ct) => (execute_CTestSubset rd cb ct) : M (unit) + | CSeal (cd,cs,ct) => (execute_CSeal cd cs ct) : M (unit) + | CCSeal (cd,cs,ct) => (execute_CCSeal cd cs ct) : M (unit) + | CUnseal (cd,cs,ct) => (execute_CUnseal cd cs ct) : M (unit) + | CCall (cs,cb,b__155) => (execute_CCall cs cb b__155) : M (unit) + | CReturn (arg0) => (execute_CReturn arg0) : M (unit) + | CBX (cb,imm,notset) => (execute_CBX cb imm notset) : M (unit) + | CBZ (cb,imm,notzero) => (execute_CBZ cb imm notzero) : M (unit) + | CJALR (cd,cb,link) => (execute_CJALR cd cb link) : M (unit) + | CLoad (rd,cb,rt,offset,signext,width) => + (execute_CLoad rd cb rt offset signext width) : M (unit) + | CLoadLinked (rd,cb,signext,width) => (execute_CLoadLinked rd cb signext width) : M (unit) + | CLoadTags (rd,cb) => (execute_CLoadTags rd cb) : M (unit) + | CStore (rs,cb,rt,offset,width) => (execute_CStore rs cb rt offset width) : M (unit) + | CStoreConditional (rs,cb,rd,width) => (execute_CStoreConditional rs cb rd width) : M (unit) + | CSC (cs,cb,rt,offset) => (execute_CSC cs cb rt offset) : M (unit) + | CSCC (cs,cb,rd) => (execute_CSCC cs cb rd) : M (unit) + | CLC (cd,cb,rt,offset) => (execute_CLC cd cb rt offset) : M (unit) + | CLCBI (cd,cb,offset) => (execute_CLCBI cd cb offset) : M (unit) + | CLLC (cd,cb) => (execute_CLLC cd cb) : M (unit) + | C2Dump (rt) => returnm ((execute_C2Dump rt) : unit) + | RI (arg0) => (execute_RI arg0) : M (unit) + end) + : M (unit). + +Definition supported_instructions (instr : ast) : option ast := Some (instr). + +Definition initialize_registers '(tt : unit) +: M (unit) := + + (undefined_bitvector 64) >>= fun w__0 : mword 64 => + write_reg PC_ref w__0 >> + (undefined_bitvector 64) >>= fun w__1 : mword 64 => + write_reg NextPC_ref w__1 >> + (undefined_bitvector 1) >>= fun w__2 : mword 1 => + write_reg TLBProbe_ref w__2 >> + (undefined_bitvector 6) >>= fun w__3 : mword 6 => + write_reg TLBIndex_ref w__3 >> + (undefined_bitvector 6) >>= fun w__4 : mword 6 => + write_reg TLBRandom_ref w__4 >> + (undefined_TLBEntryLoReg tt) >>= fun w__5 : TLBEntryLoReg => + write_reg TLBEntryLo0_ref w__5 >> + (undefined_TLBEntryLoReg tt) >>= fun w__6 : TLBEntryLoReg => + write_reg TLBEntryLo1_ref w__6 >> + (undefined_ContextReg tt) >>= fun w__7 : ContextReg => + write_reg TLBContext_ref w__7 >> + (undefined_bitvector 16) >>= fun w__8 : mword 16 => + write_reg TLBPageMask_ref w__8 >> + (undefined_bitvector 6) >>= fun w__9 : mword 6 => + write_reg TLBWired_ref w__9 >> + (undefined_TLBEntryHiReg tt) >>= fun w__10 : TLBEntryHiReg => + write_reg TLBEntryHi_ref w__10 >> + (undefined_XContextReg tt) >>= fun w__11 : XContextReg => + write_reg TLBXContext_ref w__11 >> + (undefined_TLBEntry tt) >>= fun w__12 : TLBEntry => + write_reg TLBEntry00_ref w__12 >> + (undefined_TLBEntry tt) >>= fun w__13 : TLBEntry => + write_reg TLBEntry01_ref w__13 >> + (undefined_TLBEntry tt) >>= fun w__14 : TLBEntry => + write_reg TLBEntry02_ref w__14 >> + (undefined_TLBEntry tt) >>= fun w__15 : TLBEntry => + write_reg TLBEntry03_ref w__15 >> + (undefined_TLBEntry tt) >>= fun w__16 : TLBEntry => + write_reg TLBEntry04_ref w__16 >> + (undefined_TLBEntry tt) >>= fun w__17 : TLBEntry => + write_reg TLBEntry05_ref w__17 >> + (undefined_TLBEntry tt) >>= fun w__18 : TLBEntry => + write_reg TLBEntry06_ref w__18 >> + (undefined_TLBEntry tt) >>= fun w__19 : TLBEntry => + write_reg TLBEntry07_ref w__19 >> + (undefined_TLBEntry tt) >>= fun w__20 : TLBEntry => + write_reg TLBEntry08_ref w__20 >> + (undefined_TLBEntry tt) >>= fun w__21 : TLBEntry => + write_reg TLBEntry09_ref w__21 >> + (undefined_TLBEntry tt) >>= fun w__22 : TLBEntry => + write_reg TLBEntry10_ref w__22 >> + (undefined_TLBEntry tt) >>= fun w__23 : TLBEntry => + write_reg TLBEntry11_ref w__23 >> + (undefined_TLBEntry tt) >>= fun w__24 : TLBEntry => + write_reg TLBEntry12_ref w__24 >> + (undefined_TLBEntry tt) >>= fun w__25 : TLBEntry => + write_reg TLBEntry13_ref w__25 >> + (undefined_TLBEntry tt) >>= fun w__26 : TLBEntry => + write_reg TLBEntry14_ref w__26 >> + (undefined_TLBEntry tt) >>= fun w__27 : TLBEntry => + write_reg TLBEntry15_ref w__27 >> + (undefined_TLBEntry tt) >>= fun w__28 : TLBEntry => + write_reg TLBEntry16_ref w__28 >> + (undefined_TLBEntry tt) >>= fun w__29 : TLBEntry => + write_reg TLBEntry17_ref w__29 >> + (undefined_TLBEntry tt) >>= fun w__30 : TLBEntry => + write_reg TLBEntry18_ref w__30 >> + (undefined_TLBEntry tt) >>= fun w__31 : TLBEntry => + write_reg TLBEntry19_ref w__31 >> + (undefined_TLBEntry tt) >>= fun w__32 : TLBEntry => + write_reg TLBEntry20_ref w__32 >> + (undefined_TLBEntry tt) >>= fun w__33 : TLBEntry => + write_reg TLBEntry21_ref w__33 >> + (undefined_TLBEntry tt) >>= fun w__34 : TLBEntry => + write_reg TLBEntry22_ref w__34 >> + (undefined_TLBEntry tt) >>= fun w__35 : TLBEntry => + write_reg TLBEntry23_ref w__35 >> + (undefined_TLBEntry tt) >>= fun w__36 : TLBEntry => + write_reg TLBEntry24_ref w__36 >> + (undefined_TLBEntry tt) >>= fun w__37 : TLBEntry => + write_reg TLBEntry25_ref w__37 >> + (undefined_TLBEntry tt) >>= fun w__38 : TLBEntry => + write_reg TLBEntry26_ref w__38 >> + (undefined_TLBEntry tt) >>= fun w__39 : TLBEntry => + write_reg TLBEntry27_ref w__39 >> + (undefined_TLBEntry tt) >>= fun w__40 : TLBEntry => + write_reg TLBEntry28_ref w__40 >> + (undefined_TLBEntry tt) >>= fun w__41 : TLBEntry => + write_reg TLBEntry29_ref w__41 >> + (undefined_TLBEntry tt) >>= fun w__42 : TLBEntry => + write_reg TLBEntry30_ref w__42 >> + (undefined_TLBEntry tt) >>= fun w__43 : TLBEntry => + write_reg TLBEntry31_ref w__43 >> + (undefined_TLBEntry tt) >>= fun w__44 : TLBEntry => + write_reg TLBEntry32_ref w__44 >> + (undefined_TLBEntry tt) >>= fun w__45 : TLBEntry => + write_reg TLBEntry33_ref w__45 >> + (undefined_TLBEntry tt) >>= fun w__46 : TLBEntry => + write_reg TLBEntry34_ref w__46 >> + (undefined_TLBEntry tt) >>= fun w__47 : TLBEntry => + write_reg TLBEntry35_ref w__47 >> + (undefined_TLBEntry tt) >>= fun w__48 : TLBEntry => + write_reg TLBEntry36_ref w__48 >> + (undefined_TLBEntry tt) >>= fun w__49 : TLBEntry => + write_reg TLBEntry37_ref w__49 >> + (undefined_TLBEntry tt) >>= fun w__50 : TLBEntry => + write_reg TLBEntry38_ref w__50 >> + (undefined_TLBEntry tt) >>= fun w__51 : TLBEntry => + write_reg TLBEntry39_ref w__51 >> + (undefined_TLBEntry tt) >>= fun w__52 : TLBEntry => + write_reg TLBEntry40_ref w__52 >> + (undefined_TLBEntry tt) >>= fun w__53 : TLBEntry => + write_reg TLBEntry41_ref w__53 >> + (undefined_TLBEntry tt) >>= fun w__54 : TLBEntry => + write_reg TLBEntry42_ref w__54 >> + (undefined_TLBEntry tt) >>= fun w__55 : TLBEntry => + write_reg TLBEntry43_ref w__55 >> + (undefined_TLBEntry tt) >>= fun w__56 : TLBEntry => + write_reg TLBEntry44_ref w__56 >> + (undefined_TLBEntry tt) >>= fun w__57 : TLBEntry => + write_reg TLBEntry45_ref w__57 >> + (undefined_TLBEntry tt) >>= fun w__58 : TLBEntry => + write_reg TLBEntry46_ref w__58 >> + (undefined_TLBEntry tt) >>= fun w__59 : TLBEntry => + write_reg TLBEntry47_ref w__59 >> + (undefined_TLBEntry tt) >>= fun w__60 : TLBEntry => + write_reg TLBEntry48_ref w__60 >> + (undefined_TLBEntry tt) >>= fun w__61 : TLBEntry => + write_reg TLBEntry49_ref w__61 >> + (undefined_TLBEntry tt) >>= fun w__62 : TLBEntry => + write_reg TLBEntry50_ref w__62 >> + (undefined_TLBEntry tt) >>= fun w__63 : TLBEntry => + write_reg TLBEntry51_ref w__63 >> + (undefined_TLBEntry tt) >>= fun w__64 : TLBEntry => + write_reg TLBEntry52_ref w__64 >> + (undefined_TLBEntry tt) >>= fun w__65 : TLBEntry => + write_reg TLBEntry53_ref w__65 >> + (undefined_TLBEntry tt) >>= fun w__66 : TLBEntry => + write_reg TLBEntry54_ref w__66 >> + (undefined_TLBEntry tt) >>= fun w__67 : TLBEntry => + write_reg TLBEntry55_ref w__67 >> + (undefined_TLBEntry tt) >>= fun w__68 : TLBEntry => + write_reg TLBEntry56_ref w__68 >> + (undefined_TLBEntry tt) >>= fun w__69 : TLBEntry => + write_reg TLBEntry57_ref w__69 >> + (undefined_TLBEntry tt) >>= fun w__70 : TLBEntry => + write_reg TLBEntry58_ref w__70 >> + (undefined_TLBEntry tt) >>= fun w__71 : TLBEntry => + write_reg TLBEntry59_ref w__71 >> + (undefined_TLBEntry tt) >>= fun w__72 : TLBEntry => + write_reg TLBEntry60_ref w__72 >> + (undefined_TLBEntry tt) >>= fun w__73 : TLBEntry => + write_reg TLBEntry61_ref w__73 >> + (undefined_TLBEntry tt) >>= fun w__74 : TLBEntry => + write_reg TLBEntry62_ref w__74 >> + (undefined_TLBEntry tt) >>= fun w__75 : TLBEntry => + write_reg TLBEntry63_ref w__75 >> + (undefined_bitvector 32) >>= fun w__76 : mword 32 => + write_reg CP0Compare_ref w__76 >> + (undefined_CauseReg tt) >>= fun w__77 : CauseReg => + write_reg CP0Cause_ref w__77 >> + (undefined_bitvector 64) >>= fun w__78 : mword 64 => + write_reg CP0EPC_ref w__78 >> + (undefined_bitvector 64) >>= fun w__79 : mword 64 => + write_reg CP0ErrorEPC_ref w__79 >> + (undefined_bitvector 1) >>= fun w__80 : mword 1 => + write_reg CP0LLBit_ref w__80 >> + (undefined_bitvector 64) >>= fun w__81 : mword 64 => + write_reg CP0LLAddr_ref w__81 >> + (undefined_bitvector 64) >>= fun w__82 : mword 64 => + write_reg CP0BadVAddr_ref w__82 >> + (undefined_bitvector 32) >>= fun w__83 : mword 32 => + write_reg CurrentInstrBits_ref w__83 >> + (undefined_bitvector 32) >>= fun w__84 : mword 32 => + write_reg LastInstrBits_ref w__84 >> + (undefined_bitvector 32) >>= fun w__85 : mword 32 => + write_reg CP0BadInstr_ref w__85 >> + (undefined_bitvector 32) >>= fun w__86 : mword 32 => + write_reg CP0BadInstrP_ref w__86 >> + (undefined_bitvector 32) >>= fun w__87 : mword 32 => + write_reg CP0Count_ref w__87 >> + (undefined_bitvector 32) >>= fun w__88 : mword 32 => + write_reg CP0HWREna_ref w__88 >> + (undefined_bitvector 64) >>= fun w__89 : mword 64 => + write_reg CP0UserLocal_ref w__89 >> + (undefined_bitvector 3) >>= fun w__90 : mword 3 => + write_reg CP0ConfigK0_ref w__90 >> + (undefined_StatusReg tt) >>= fun w__91 : StatusReg => + write_reg CP0Status_ref w__91 >> + (undefined_bitvector 1) >>= fun w__92 : mword 1 => + write_reg NextInBranchDelay_ref w__92 >> + (undefined_bitvector 1) >>= fun w__93 : mword 1 => + write_reg InBranchDelay_ref w__93 >> + (undefined_bitvector 1) >>= fun w__94 : mword 1 => + write_reg BranchPending_ref w__94 >> + (undefined_bitvector 64) >>= fun w__95 : mword 64 => + write_reg DelayedPC_ref w__95 >> + (undefined_bitvector 64) >>= fun w__96 : mword 64 => + write_reg HI_ref w__96 >> + (undefined_bitvector 64) >>= fun w__97 : mword 64 => + write_reg LO_ref w__97 >> + (undefined_bitvector 64) >>= fun w__98 : mword 64 => + (undefined_vector 32 w__98) >>= fun w__99 : vec (mword 64) 32 => + write_reg GPR_ref w__99 >> + (undefined_bitvector 8) >>= fun w__100 : mword 8 => + write_reg UART_WDATA_ref w__100 >> + (undefined_bitvector 1) >>= fun w__101 : mword 1 => + write_reg UART_WRITTEN_ref w__101 >> + (undefined_bitvector 8) >>= fun w__102 : mword 8 => + write_reg UART_RDATA_ref w__102 >> + (undefined_bitvector 1) >>= fun w__103 : mword 1 => + write_reg UART_RVALID_ref w__103 >> + (undefined_Capability tt) >>= fun w__104 : Capability => + write_reg PCC_ref w__104 >> + (undefined_Capability tt) >>= fun w__105 : Capability => + write_reg NextPCC_ref w__105 >> + (undefined_Capability tt) >>= fun w__106 : Capability => + write_reg DelayedPCC_ref w__106 >> + (undefined_Capability tt) >>= fun w__107 : Capability => + write_reg DDC_ref w__107 >> + (undefined_Capability tt) >>= fun w__108 : Capability => + write_reg C01_ref w__108 >> + (undefined_Capability tt) >>= fun w__109 : Capability => + write_reg C02_ref w__109 >> + (undefined_Capability tt) >>= fun w__110 : Capability => + write_reg C03_ref w__110 >> + (undefined_Capability tt) >>= fun w__111 : Capability => + write_reg C04_ref w__111 >> + (undefined_Capability tt) >>= fun w__112 : Capability => + write_reg C05_ref w__112 >> + (undefined_Capability tt) >>= fun w__113 : Capability => + write_reg C06_ref w__113 >> + (undefined_Capability tt) >>= fun w__114 : Capability => + write_reg C07_ref w__114 >> + (undefined_Capability tt) >>= fun w__115 : Capability => + write_reg C08_ref w__115 >> + (undefined_Capability tt) >>= fun w__116 : Capability => + write_reg C09_ref w__116 >> + (undefined_Capability tt) >>= fun w__117 : Capability => + write_reg C10_ref w__117 >> + (undefined_Capability tt) >>= fun w__118 : Capability => + write_reg C11_ref w__118 >> + (undefined_Capability tt) >>= fun w__119 : Capability => + write_reg C12_ref w__119 >> + (undefined_Capability tt) >>= fun w__120 : Capability => + write_reg C13_ref w__120 >> + (undefined_Capability tt) >>= fun w__121 : Capability => + write_reg C14_ref w__121 >> + (undefined_Capability tt) >>= fun w__122 : Capability => + write_reg C15_ref w__122 >> + (undefined_Capability tt) >>= fun w__123 : Capability => + write_reg C16_ref w__123 >> + (undefined_Capability tt) >>= fun w__124 : Capability => + write_reg C17_ref w__124 >> + (undefined_Capability tt) >>= fun w__125 : Capability => + write_reg C18_ref w__125 >> + (undefined_Capability tt) >>= fun w__126 : Capability => + write_reg C19_ref w__126 >> + (undefined_Capability tt) >>= fun w__127 : Capability => + write_reg C20_ref w__127 >> + (undefined_Capability tt) >>= fun w__128 : Capability => + write_reg C21_ref w__128 >> + (undefined_Capability tt) >>= fun w__129 : Capability => + write_reg C22_ref w__129 >> + (undefined_Capability tt) >>= fun w__130 : Capability => + write_reg C23_ref w__130 >> + (undefined_Capability tt) >>= fun w__131 : Capability => + write_reg C24_ref w__131 >> + (undefined_Capability tt) >>= fun w__132 : Capability => + write_reg C25_ref w__132 >> + (undefined_Capability tt) >>= fun w__133 : Capability => + write_reg C26_ref w__133 >> + (undefined_Capability tt) >>= fun w__134 : Capability => + write_reg C27_ref w__134 >> + (undefined_Capability tt) >>= fun w__135 : Capability => + write_reg C28_ref w__135 >> + (undefined_Capability tt) >>= fun w__136 : Capability => + write_reg C29_ref w__136 >> + (undefined_Capability tt) >>= fun w__137 : Capability => + write_reg C30_ref w__137 >> + (undefined_Capability tt) >>= fun w__138 : Capability => + write_reg C31_ref w__138 >> + (undefined_Capability tt) >>= fun w__139 : Capability => + write_reg CTLSU_ref w__139 >> + (undefined_Capability tt) >>= fun w__140 : Capability => + write_reg CTLSP_ref w__140 >> + (undefined_Capability tt) >>= fun w__141 : Capability => + write_reg KR1C_ref w__141 >> + (undefined_Capability tt) >>= fun w__142 : Capability => + write_reg KR2C_ref w__142 >> + (undefined_Capability tt) >>= fun w__143 : Capability => + write_reg KCC_ref w__143 >> + (undefined_Capability tt) >>= fun w__144 : Capability => + write_reg KDC_ref w__144 >> + (undefined_Capability tt) >>= fun w__145 : Capability => + write_reg EPCC_ref w__145 >> + (undefined_CapCauseReg tt) >>= fun w__146 : CapCauseReg => + write_reg CapCause_ref w__146 >> + (undefined_bitvector 64) >>= fun w__147 : mword 64 => write_reg CID_ref w__147 : M (unit). + +Definition initial_regstate : regstate := +{| CID := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + CapCause := + ({| CapCauseReg_CapCauseReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16) |}); + EPCC := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + KDC := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + KCC := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + KR2C := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + KR1C := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + CTLSP := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + CTLSU := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C31 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C30 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C29 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C28 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C27 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C26 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C25 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C24 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C23 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C22 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C21 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C20 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C19 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C18 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C17 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C16 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C15 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C14 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C13 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C12 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C11 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C10 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C09 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C08 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C07 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C06 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C05 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C04 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C03 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C02 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C01 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + DDC := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + DelayedPCC := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + NextPCC := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + PCC := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + UART_RVALID := (vec_of_bits [B0] : mword 1); + UART_RDATA := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + UART_WRITTEN := (vec_of_bits [B0] : mword 1); + UART_WDATA := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + GPR := + (vec_of_list_len [(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64)]); + LO := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + HI := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + DelayedPC := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + BranchPending := (vec_of_bits [B0] : mword 1); + InBranchDelay := (vec_of_bits [B0] : mword 1); + NextInBranchDelay := (vec_of_bits [B0] : mword 1); + CP0Status := + ({| StatusReg_StatusReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) |}); + CP0ConfigK0 := (vec_of_bits [B0;B0;B0] : mword 3); + CP0UserLocal := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + CP0HWREna := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + CP0Count := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + CP0BadInstrP := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + CP0BadInstr := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + LastInstrBits := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + CurrentInstrBits := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + CP0BadVAddr := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + CP0LLAddr := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + CP0LLBit := (vec_of_bits [B0] : mword 1); + CP0ErrorEPC := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + CP0EPC := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + CP0Cause := + ({| CauseReg_CauseReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) |}); + CP0Compare := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + TLBEntry63 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry62 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry61 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry60 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry59 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry58 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry57 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry56 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry55 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry54 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry53 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry52 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry51 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry50 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry49 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry48 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry47 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry46 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry45 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry44 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry43 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry42 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry41 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry40 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry39 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry38 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry37 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry36 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry35 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry34 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry33 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry32 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry31 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry30 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry29 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry28 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry27 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry26 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry25 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry24 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry23 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry22 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry21 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry20 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry19 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry18 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry17 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry16 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry15 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry14 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry13 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry12 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry11 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry10 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry09 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry08 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry07 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry06 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry05 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry04 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry03 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry02 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry01 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry00 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBXContext := + ({| XContextReg_XContextReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntryHi := + ({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBWired := (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6); + TLBPageMask := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + TLBContext := + ({| ContextReg_ContextReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntryLo1 := + ({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntryLo0 := + ({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBRandom := (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6); + TLBIndex := (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6); + TLBProbe := (vec_of_bits [B0] : mword 1); + NextPC := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + PC := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}. +Hint Unfold initial_regstate : sail. + +End Content. diff --git a/snapshots/coq/cheri-mips/cheri_types.v b/snapshots/coq/cheri-mips/cheri_types.v new file mode 100644 index 00000000..07e4bc80 --- /dev/null +++ b/snapshots/coq/cheri-mips/cheri_types.v @@ -0,0 +1,2229 @@ +(*Generated by Sail from cheri.*) +Require Import Sail2_instr_kinds. +Require Import Sail2_values. +Require Import Sail2_string. +Require Import Sail2_real. +Require Import Sail2_operators_mwords. +Require Import Sail2_prompt_monad. +Require Import Sail2_prompt. +Require Import Sail2_state. + + +Definition bits (n : Z) : Type := mword n. + +Inductive exception := + ISAException : unit -> exception + | Error_not_implemented : string -> exception + | Error_misaligned_access : unit -> exception + | Error_EBREAK : unit -> exception + | Error_internal_error : unit -> exception. +Arguments exception : clear implicits. + + + +Record CauseReg := { CauseReg_CauseReg_chunk_0 : mword 32; }. +Notation "{[ r 'with' 'CauseReg_CauseReg_chunk_0' := e ]}" := ({| CauseReg_CauseReg_chunk_0 := e |}). + +Record CapCauseReg := { CapCauseReg_CapCauseReg_chunk_0 : mword 16; }. +Notation "{[ r 'with' 'CapCauseReg_CapCauseReg_chunk_0' := e ]}" := ({| CapCauseReg_CapCauseReg_chunk_0 := e |}). + +Record TLBEntryLoReg := { TLBEntryLoReg_TLBEntryLoReg_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'TLBEntryLoReg_TLBEntryLoReg_chunk_0' := e ]}" := ({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := e |}). + +Record TLBEntryHiReg := { TLBEntryHiReg_TLBEntryHiReg_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'TLBEntryHiReg_TLBEntryHiReg_chunk_0' := e ]}" := ({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := e |}). + +Record ContextReg := { ContextReg_ContextReg_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'ContextReg_ContextReg_chunk_0' := e ]}" := ({| ContextReg_ContextReg_chunk_0 := e |}). + +Record XContextReg := { XContextReg_XContextReg_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'XContextReg_XContextReg_chunk_0' := e ]}" := ({| XContextReg_XContextReg_chunk_0 := e |}). + +Definition TLBIndexT : Type := bits 6. + +Record TLBEntry := { TLBEntry_TLBEntry_chunk_1 : mword 53; TLBEntry_TLBEntry_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'TLBEntry_TLBEntry_chunk_1' := e ]}" := ({| TLBEntry_TLBEntry_chunk_1 := e; TLBEntry_TLBEntry_chunk_0 := TLBEntry_TLBEntry_chunk_0 r |}). +Notation "{[ r 'with' 'TLBEntry_TLBEntry_chunk_0' := e ]}" := ({| TLBEntry_TLBEntry_chunk_0 := e; TLBEntry_TLBEntry_chunk_1 := TLBEntry_TLBEntry_chunk_1 r |}). + +Record StatusReg := { StatusReg_StatusReg_chunk_0 : mword 32; }. +Notation "{[ r 'with' 'StatusReg_StatusReg_chunk_0' := e ]}" := ({| StatusReg_StatusReg_chunk_0 := e |}). + +Inductive Exception := + Interrupt + | TLBMod + | TLBL + | TLBS + | AdEL + | AdES + | Sys + | Bp + | ResI + | CpU + | Ov + | Tr + | C2E + | C2Trap + | XTLBRefillL + | XTLBRefillS + | XTLBInvL + | XTLBInvS + | MCheck. +Scheme Equality for Exception. +Instance Decidable_eq_Exception : +forall (x y : Exception), Decidable (x = y) := +Decidable_eq_from_dec Exception_eq_dec. + + +Record Capability := + { Capability_tag : bool; + Capability_padding : bits 8; + Capability_otype : bits 24; + Capability_uperms : bits 16; + Capability_perm_reserved12_14 : bits 3; + Capability_permit_set_CID : bool; + Capability_access_system_regs : bool; + Capability_permit_unseal : bool; + Capability_permit_ccall : bool; + Capability_permit_seal : bool; + Capability_permit_store_local_cap : bool; + Capability_permit_store_cap : bool; + Capability_permit_load_cap : bool; + Capability_permit_store : bool; + Capability_permit_load : bool; + Capability_permit_execute : bool; + Capability_global : bool; + Capability_sealed : bool; + Capability_address : bits 64; + Capability_base : bits 64; + Capability_length : bits 64; }. +Instance Decidable_eq_Capability : +forall (x y : Capability), Decidable (x = y). + intros [x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 x17 x18 x19 x20]. + intros [y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19 y20]. +cmp_record_field x0 y0. +cmp_record_field x1 y1. +cmp_record_field x2 y2. +cmp_record_field x3 y3. +cmp_record_field x4 y4. +cmp_record_field x5 y5. +cmp_record_field x6 y6. +cmp_record_field x7 y7. +cmp_record_field x8 y8. +cmp_record_field x9 y9. +cmp_record_field x10 y10. +cmp_record_field x11 y11. +cmp_record_field x12 y12. +cmp_record_field x13 y13. +cmp_record_field x14 y14. +cmp_record_field x15 y15. +cmp_record_field x16 y16. +cmp_record_field x17 y17. +cmp_record_field x18 y18. +cmp_record_field x19 y19. +cmp_record_field x20 y20. +refine (Build_Decidable _ true _). subst. split; reflexivity. +Defined. +Notation "{[ r 'with' 'Capability_tag' := e ]}" := ({| Capability_tag := e; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_padding' := e ]}" := ({| Capability_padding := e; Capability_tag := Capability_tag r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_otype' := e ]}" := ({| Capability_otype := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_uperms' := e ]}" := ({| Capability_uperms := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_perm_reserved12_14' := e ]}" := ({| Capability_perm_reserved12_14 := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_permit_set_CID' := e ]}" := ({| Capability_permit_set_CID := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_access_system_regs' := e ]}" := ({| Capability_access_system_regs := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_permit_unseal' := e ]}" := ({| Capability_permit_unseal := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_permit_ccall' := e ]}" := ({| Capability_permit_ccall := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_permit_seal' := e ]}" := ({| Capability_permit_seal := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_permit_store_local_cap' := e ]}" := ({| Capability_permit_store_local_cap := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_permit_store_cap' := e ]}" := ({| Capability_permit_store_cap := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_permit_load_cap' := e ]}" := ({| Capability_permit_load_cap := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_permit_store' := e ]}" := ({| Capability_permit_store := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_permit_load' := e ]}" := ({| Capability_permit_load := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_permit_execute' := e ]}" := ({| Capability_permit_execute := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_global' := e ]}" := ({| Capability_global := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_sealed' := e ]}" := ({| Capability_sealed := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_address' := e ]}" := ({| Capability_address := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_base' := e ]}" := ({| Capability_base := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_length' := e ]}" := ({| Capability_length := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r |}). + +Inductive MemAccessType := Instruction | LoadData | StoreData. +Scheme Equality for MemAccessType. +Instance Decidable_eq_MemAccessType : +forall (x y : MemAccessType), Decidable (x = y) := +Decidable_eq_from_dec MemAccessType_eq_dec. + + +Inductive AccessLevel := User | Supervisor | Kernel. +Scheme Equality for AccessLevel. +Instance Decidable_eq_AccessLevel : +forall (x y : AccessLevel), Decidable (x = y) := +Decidable_eq_from_dec AccessLevel_eq_dec. + + +Definition regno : Type := bits 5. + +Definition imm16 : Type := bits 16. + +Definition regregreg : Type := (regno * regno * regno). + +Definition regregimm16 : Type := (regno * regno * imm16). + +Inductive decode_failure := + no_matching_pattern | unsupported_instruction | illegal_instruction | internal_error. +Scheme Equality for decode_failure. +Instance Decidable_eq_decode_failure : +forall (x y : decode_failure), Decidable (x = y) := +Decidable_eq_from_dec decode_failure_eq_dec. + + +Inductive Comparison := EQ' | NE | GE | GEU | GT' | LE | LT' | LTU. +Scheme Equality for Comparison. +Instance Decidable_eq_Comparison : +forall (x y : Comparison), Decidable (x = y) := +Decidable_eq_from_dec Comparison_eq_dec. + + +Inductive WordType := B | H | W | D. +Scheme Equality for WordType. +Instance Decidable_eq_WordType : +forall (x y : WordType), Decidable (x = y) := +Decidable_eq_from_dec WordType_eq_dec. + + +Inductive WordTypeUnaligned := WL | WR | DL | DR. +Scheme Equality for WordTypeUnaligned. +Instance Decidable_eq_WordTypeUnaligned : +forall (x y : WordTypeUnaligned), Decidable (x = y) := +Decidable_eq_from_dec WordTypeUnaligned_eq_dec. + + +Definition CapLen : Type := {rangevar : Z & ArithFact (0 <= rangevar /\ rangevar <= (2 ^ 65))}. + +Definition uint64 : Type := {rangevar : Z & ArithFact (0 <= rangevar /\ rangevar <= (2 ^ 64 - 1))}. + +Inductive CPtrCmpOp := CEQ | CNE | CLT | CLE | CLTU | CLEU | CEXEQ | CNEXEQ. +Scheme Equality for CPtrCmpOp. +Instance Decidable_eq_CPtrCmpOp : +forall (x y : CPtrCmpOp), Decidable (x = y) := +Decidable_eq_from_dec CPtrCmpOp_eq_dec. + + +Inductive ClearRegSet := GPLo | GPHi | CLo | CHi. +Scheme Equality for ClearRegSet. +Instance Decidable_eq_ClearRegSet : +forall (x y : ClearRegSet), Decidable (x = y) := +Decidable_eq_from_dec ClearRegSet_eq_dec. + + +Definition CapBits : Type := bits 256. + +Inductive ast := + DADDIU : (regno * regno * imm16) -> ast + | DADDU : (regno * regno * regno) -> ast + | DADDI : (regno * regno * bits 16) -> ast + | DADD : (regno * regno * regno) -> ast + | ADD : (regno * regno * regno) -> ast + | ADDI : (regno * regno * bits 16) -> ast + | ADDU : (regno * regno * regno) -> ast + | ADDIU : (regno * regno * bits 16) -> ast + | DSUBU : (regno * regno * regno) -> ast + | DSUB : (regno * regno * regno) -> ast + | SUB : (regno * regno * regno) -> ast + | SUBU : (regno * regno * regno) -> ast + | AND : (regno * regno * regno) -> ast + | ANDI : (regno * regno * bits 16) -> ast + | OR : (regno * regno * regno) -> ast + | ORI : (regno * regno * bits 16) -> ast + | NOR : (regno * regno * regno) -> ast + | XOR : (regno * regno * regno) -> ast + | XORI : (regno * regno * bits 16) -> ast + | LUI : (regno * imm16) -> ast + | DSLL : (regno * regno * regno) -> ast + | DSLL32 : (regno * regno * regno) -> ast + | DSLLV : (regno * regno * regno) -> ast + | DSRA : (regno * regno * regno) -> ast + | DSRA32 : (regno * regno * regno) -> ast + | DSRAV : (regno * regno * regno) -> ast + | DSRL : (regno * regno * regno) -> ast + | DSRL32 : (regno * regno * regno) -> ast + | DSRLV : (regno * regno * regno) -> ast + | SLL : (regno * regno * regno) -> ast + | SLLV : (regno * regno * regno) -> ast + | SRA : (regno * regno * regno) -> ast + | SRAV : (regno * regno * regno) -> ast + | SRL : (regno * regno * regno) -> ast + | SRLV : (regno * regno * regno) -> ast + | SLT : (regno * regno * regno) -> ast + | SLTI : (regno * regno * bits 16) -> ast + | SLTU : (regno * regno * regno) -> ast + | SLTIU : (regno * regno * bits 16) -> ast + | MOVN : (regno * regno * regno) -> ast + | MOVZ : (regno * regno * regno) -> ast + | MFHI : regno -> ast + | MFLO : regno -> ast + | MTHI : regno -> ast + | MTLO : regno -> ast + | MUL : (regno * regno * regno) -> ast + | MULT : (regno * regno) -> ast + | MULTU : (regno * regno) -> ast + | DMULT : (regno * regno) -> ast + | DMULTU : (regno * regno) -> ast + | MADD : (regno * regno) -> ast + | MADDU : (regno * regno) -> ast + | MSUB : (regno * regno) -> ast + | MSUBU : (regno * regno) -> ast + | DIV : (regno * regno) -> ast + | DIVU : (regno * regno) -> ast + | DDIV : (regno * regno) -> ast + | DDIVU : (regno * regno) -> ast + | J : bits 26 -> ast + | JAL : bits 26 -> ast + | JR : regno -> ast + | JALR : (regno * regno) -> ast + | BEQ : (regno * regno * imm16 * bool * bool) -> ast + | BCMPZ : (regno * imm16 * Comparison * bool * bool) -> ast + | SYSCALL : unit -> ast + | BREAK : unit -> ast + | WAIT : unit -> ast + | TRAPREG : (regno * regno * Comparison) -> ast + | TRAPIMM : (regno * imm16 * Comparison) -> ast + | Load : (WordType * bool * bool * regno * regno * imm16) -> ast + | Store : (WordType * bool * regno * regno * imm16) -> ast + | LWL : (regno * regno * bits 16) -> ast + | LWR : (regno * regno * bits 16) -> ast + | SWL : (regno * regno * bits 16) -> ast + | SWR : (regno * regno * bits 16) -> ast + | LDL : (regno * regno * bits 16) -> ast + | LDR : (regno * regno * bits 16) -> ast + | SDL : (regno * regno * bits 16) -> ast + | SDR : (regno * regno * bits 16) -> ast + | CACHE : (regno * regno * bits 16) -> ast + | SYNC : unit -> ast + | MFC0 : (regno * regno * bits 3 * bool) -> ast + | HCF : unit -> ast + | MTC0 : (regno * regno * bits 3 * bool) -> ast + | TLBWI : unit -> ast + | TLBWR : unit -> ast + | TLBR : unit -> ast + | TLBP : unit -> ast + | RDHWR : (regno * regno) -> ast + | ERET : unit -> ast + | CGetPerm : (regno * regno) -> ast + | CGetType : (regno * regno) -> ast + | CGetBase : (regno * regno) -> ast + | CGetLen : (regno * regno) -> ast + | CGetTag : (regno * regno) -> ast + | CGetSealed : (regno * regno) -> ast + | CGetOffset : (regno * regno) -> ast + | CGetAddr : (regno * regno) -> ast + | CGetPCC : regno -> ast + | CGetPCCSetOffset : (regno * regno) -> ast + | CGetCause : regno -> ast + | CSetCause : regno -> ast + | CGetCID : regno -> ast + | CSetCID : regno -> ast + | CReadHwr : (regno * regno) -> ast + | CWriteHwr : (regno * regno) -> ast + | CAndPerm : (regno * regno * regno) -> ast + | CToPtr : (regno * regno * regno) -> ast + | CSub : (regno * regno * regno) -> ast + | CPtrCmp : (regno * regno * regno * CPtrCmpOp) -> ast + | CIncOffset : (regno * regno * regno) -> ast + | CIncOffsetImmediate : (regno * regno * bits 11) -> ast + | CSetOffset : (regno * regno * regno) -> ast + | CSetBounds : (regno * regno * regno) -> ast + | CSetBoundsImmediate : (regno * regno * bits 11) -> ast + | CSetBoundsExact : (regno * regno * regno) -> ast + | CClearTag : (regno * regno) -> ast + | CMOVX : (regno * regno * regno * bool) -> ast + | ClearRegs : (ClearRegSet * bits 16) -> ast + | CFromPtr : (regno * regno * regno) -> ast + | CBuildCap : (regno * regno * regno) -> ast + | CCopyType : (regno * regno * regno) -> ast + | CCheckPerm : (regno * regno) -> ast + | CCheckType : (regno * regno) -> ast + | CCheckTag : regno -> ast + | CTestSubset : (regno * regno * regno) -> ast + | CSeal : (regno * regno * regno) -> ast + | CCSeal : (regno * regno * regno) -> ast + | CUnseal : (regno * regno * regno) -> ast + | CCall : (regno * regno * bits 11) -> ast + | CReturn : unit -> ast + | CBX : (regno * bits 16 * bool) -> ast + | CBZ : (regno * bits 16 * bool) -> ast + | CJALR : (regno * regno * bool) -> ast + | CLoad : (regno * regno * regno * bits 8 * bool * WordType) -> ast + | CLoadLinked : (regno * regno * bool * WordType) -> ast + | CLoadTags : (regno * regno) -> ast + | CStore : (regno * regno * regno * bits 8 * WordType) -> ast + | CStoreConditional : (regno * regno * regno * WordType) -> ast + | CSC : (regno * regno * regno * bits 11) -> ast + | CSCC : (regno * regno * regno) -> ast + | CLC : (regno * regno * regno * bits 11) -> ast + | CLCBI : (regno * regno * bits 16) -> ast + | CLLC : (regno * regno) -> ast + | C2Dump : regno -> ast + | RI : unit -> ast. +Arguments ast : clear implicits. + + + +Inductive CapEx := + CapEx_None + | CapEx_LengthViolation + | CapEx_TagViolation + | CapEx_SealViolation + | CapEx_TypeViolation + | CapEx_CallTrap + | CapEx_ReturnTrap + | CapEx_TSSUnderFlow + | CapEx_UserDefViolation + | CapEx_TLBNoStoreCap + | CapEx_InexactBounds + | CapEx_GlobalViolation + | CapEx_PermitExecuteViolation + | CapEx_PermitLoadViolation + | CapEx_PermitStoreViolation + | CapEx_PermitLoadCapViolation + | CapEx_PermitStoreCapViolation + | CapEx_PermitStoreLocalCapViolation + | CapEx_PermitSealViolation + | CapEx_AccessSystemRegsViolation + | CapEx_PermitCCallViolation + | CapEx_AccessCCallIDCViolation + | CapEx_PermitUnsealViolation + | CapEx_PermitSetCIDViolation. +Scheme Equality for CapEx. +Instance Decidable_eq_CapEx : +forall (x y : CapEx), Decidable (x = y) := +Decidable_eq_from_dec CapEx_eq_dec. + + +Inductive register_value := + Regval_vector : (Z * bool * list register_value) -> register_value + | Regval_list : list register_value -> register_value + | Regval_option : option register_value -> register_value + | Regval_CapCauseReg : CapCauseReg -> register_value + | Regval_Capability : Capability -> register_value + | Regval_CauseReg : CauseReg -> register_value + | Regval_ContextReg : ContextReg -> register_value + | Regval_StatusReg : StatusReg -> register_value + | Regval_TLBEntry : TLBEntry -> register_value + | Regval_TLBEntryHiReg : TLBEntryHiReg -> register_value + | Regval_TLBEntryLoReg : TLBEntryLoReg -> register_value + | Regval_XContextReg : XContextReg -> register_value + | Regval_vector_16_dec_bit : mword 16 -> register_value + | Regval_vector_1_dec_bit : mword 1 -> register_value + | Regval_vector_32_dec_bit : mword 32 -> register_value + | Regval_vector_3_dec_bit : mword 3 -> register_value + | Regval_vector_64_dec_bit : mword 64 -> register_value + | Regval_vector_6_dec_bit : mword 6 -> register_value + | Regval_vector_8_dec_bit : mword 8 -> register_value. +Arguments register_value : clear implicits. + + + +Record regstate := + { CID : mword 64; + CapCause : CapCauseReg; + EPCC : Capability; + KDC : Capability; + KCC : Capability; + KR2C : Capability; + KR1C : Capability; + CTLSP : Capability; + CTLSU : Capability; + C31 : Capability; + C30 : Capability; + C29 : Capability; + C28 : Capability; + C27 : Capability; + C26 : Capability; + C25 : Capability; + C24 : Capability; + C23 : Capability; + C22 : Capability; + C21 : Capability; + C20 : Capability; + C19 : Capability; + C18 : Capability; + C17 : Capability; + C16 : Capability; + C15 : Capability; + C14 : Capability; + C13 : Capability; + C12 : Capability; + C11 : Capability; + C10 : Capability; + C09 : Capability; + C08 : Capability; + C07 : Capability; + C06 : Capability; + C05 : Capability; + C04 : Capability; + C03 : Capability; + C02 : Capability; + C01 : Capability; + DDC : Capability; + DelayedPCC : Capability; + NextPCC : Capability; + PCC : Capability; + UART_RVALID : mword 1; + UART_RDATA : mword 8; + UART_WRITTEN : mword 1; + UART_WDATA : mword 8; + GPR : vec (mword 64) 32; + LO : mword 64; + HI : mword 64; + DelayedPC : mword 64; + BranchPending : mword 1; + InBranchDelay : mword 1; + NextInBranchDelay : mword 1; + CP0Status : StatusReg; + CP0ConfigK0 : mword 3; + CP0UserLocal : mword 64; + CP0HWREna : mword 32; + CP0Count : mword 32; + CP0BadInstrP : mword 32; + CP0BadInstr : mword 32; + LastInstrBits : mword 32; + CurrentInstrBits : mword 32; + CP0BadVAddr : mword 64; + CP0LLAddr : mword 64; + CP0LLBit : mword 1; + CP0ErrorEPC : mword 64; + CP0EPC : mword 64; + CP0Cause : CauseReg; + CP0Compare : mword 32; + TLBEntry63 : TLBEntry; + TLBEntry62 : TLBEntry; + TLBEntry61 : TLBEntry; + TLBEntry60 : TLBEntry; + TLBEntry59 : TLBEntry; + TLBEntry58 : TLBEntry; + TLBEntry57 : TLBEntry; + TLBEntry56 : TLBEntry; + TLBEntry55 : TLBEntry; + TLBEntry54 : TLBEntry; + TLBEntry53 : TLBEntry; + TLBEntry52 : TLBEntry; + TLBEntry51 : TLBEntry; + TLBEntry50 : TLBEntry; + TLBEntry49 : TLBEntry; + TLBEntry48 : TLBEntry; + TLBEntry47 : TLBEntry; + TLBEntry46 : TLBEntry; + TLBEntry45 : TLBEntry; + TLBEntry44 : TLBEntry; + TLBEntry43 : TLBEntry; + TLBEntry42 : TLBEntry; + TLBEntry41 : TLBEntry; + TLBEntry40 : TLBEntry; + TLBEntry39 : TLBEntry; + TLBEntry38 : TLBEntry; + TLBEntry37 : TLBEntry; + TLBEntry36 : TLBEntry; + TLBEntry35 : TLBEntry; + TLBEntry34 : TLBEntry; + TLBEntry33 : TLBEntry; + TLBEntry32 : TLBEntry; + TLBEntry31 : TLBEntry; + TLBEntry30 : TLBEntry; + TLBEntry29 : TLBEntry; + TLBEntry28 : TLBEntry; + TLBEntry27 : TLBEntry; + TLBEntry26 : TLBEntry; + TLBEntry25 : TLBEntry; + TLBEntry24 : TLBEntry; + TLBEntry23 : TLBEntry; + TLBEntry22 : TLBEntry; + TLBEntry21 : TLBEntry; + TLBEntry20 : TLBEntry; + TLBEntry19 : TLBEntry; + TLBEntry18 : TLBEntry; + TLBEntry17 : TLBEntry; + TLBEntry16 : TLBEntry; + TLBEntry15 : TLBEntry; + TLBEntry14 : TLBEntry; + TLBEntry13 : TLBEntry; + TLBEntry12 : TLBEntry; + TLBEntry11 : TLBEntry; + TLBEntry10 : TLBEntry; + TLBEntry09 : TLBEntry; + TLBEntry08 : TLBEntry; + TLBEntry07 : TLBEntry; + TLBEntry06 : TLBEntry; + TLBEntry05 : TLBEntry; + TLBEntry04 : TLBEntry; + TLBEntry03 : TLBEntry; + TLBEntry02 : TLBEntry; + TLBEntry01 : TLBEntry; + TLBEntry00 : TLBEntry; + TLBXContext : XContextReg; + TLBEntryHi : TLBEntryHiReg; + TLBWired : mword 6; + TLBPageMask : mword 16; + TLBContext : ContextReg; + TLBEntryLo1 : TLBEntryLoReg; + TLBEntryLo0 : TLBEntryLoReg; + TLBRandom : mword 6; + TLBIndex : mword 6; + TLBProbe : mword 1; + NextPC : mword 64; + PC : mword 64; }. +Notation "{[ r 'with' 'CID' := e ]}" := ({| CID := e; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CapCause' := e ]}" := ({| CapCause := e; CID := CID r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'EPCC' := e ]}" := ({| EPCC := e; CID := CID r; CapCause := CapCause r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'KDC' := e ]}" := ({| KDC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'KCC' := e ]}" := ({| KCC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'KR2C' := e ]}" := ({| KR2C := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'KR1C' := e ]}" := ({| KR1C := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CTLSP' := e ]}" := ({| CTLSP := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CTLSU' := e ]}" := ({| CTLSU := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C31' := e ]}" := ({| C31 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C30' := e ]}" := ({| C30 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C29' := e ]}" := ({| C29 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C28' := e ]}" := ({| C28 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C27' := e ]}" := ({| C27 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C26' := e ]}" := ({| C26 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C25' := e ]}" := ({| C25 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C24' := e ]}" := ({| C24 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C23' := e ]}" := ({| C23 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C22' := e ]}" := ({| C22 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C21' := e ]}" := ({| C21 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C20' := e ]}" := ({| C20 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C19' := e ]}" := ({| C19 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C18' := e ]}" := ({| C18 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C17' := e ]}" := ({| C17 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C16' := e ]}" := ({| C16 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C15' := e ]}" := ({| C15 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C14' := e ]}" := ({| C14 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C13' := e ]}" := ({| C13 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C12' := e ]}" := ({| C12 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C11' := e ]}" := ({| C11 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C10' := e ]}" := ({| C10 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C09' := e ]}" := ({| C09 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C08' := e ]}" := ({| C08 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C07' := e ]}" := ({| C07 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C06' := e ]}" := ({| C06 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C05' := e ]}" := ({| C05 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C04' := e ]}" := ({| C04 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C03' := e ]}" := ({| C03 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C02' := e ]}" := ({| C02 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C01' := e ]}" := ({| C01 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'DDC' := e ]}" := ({| DDC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'DelayedPCC' := e ]}" := ({| DelayedPCC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'NextPCC' := e ]}" := ({| NextPCC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'PCC' := e ]}" := ({| PCC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'UART_RVALID' := e ]}" := ({| UART_RVALID := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'UART_RDATA' := e ]}" := ({| UART_RDATA := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'UART_WRITTEN' := e ]}" := ({| UART_WRITTEN := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'UART_WDATA' := e ]}" := ({| UART_WDATA := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'GPR' := e ]}" := ({| GPR := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'LO' := e ]}" := ({| LO := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'HI' := e ]}" := ({| HI := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'DelayedPC' := e ]}" := ({| DelayedPC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'BranchPending' := e ]}" := ({| BranchPending := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'InBranchDelay' := e ]}" := ({| InBranchDelay := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'NextInBranchDelay' := e ]}" := ({| NextInBranchDelay := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0Status' := e ]}" := ({| CP0Status := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0ConfigK0' := e ]}" := ({| CP0ConfigK0 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0UserLocal' := e ]}" := ({| CP0UserLocal := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0HWREna' := e ]}" := ({| CP0HWREna := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0Count' := e ]}" := ({| CP0Count := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0BadInstrP' := e ]}" := ({| CP0BadInstrP := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0BadInstr' := e ]}" := ({| CP0BadInstr := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'LastInstrBits' := e ]}" := ({| LastInstrBits := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CurrentInstrBits' := e ]}" := ({| CurrentInstrBits := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0BadVAddr' := e ]}" := ({| CP0BadVAddr := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0LLAddr' := e ]}" := ({| CP0LLAddr := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0LLBit' := e ]}" := ({| CP0LLBit := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0ErrorEPC' := e ]}" := ({| CP0ErrorEPC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0EPC' := e ]}" := ({| CP0EPC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0Cause' := e ]}" := ({| CP0Cause := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0Compare' := e ]}" := ({| CP0Compare := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry63' := e ]}" := ({| TLBEntry63 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry62' := e ]}" := ({| TLBEntry62 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry61' := e ]}" := ({| TLBEntry61 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry60' := e ]}" := ({| TLBEntry60 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry59' := e ]}" := ({| TLBEntry59 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry58' := e ]}" := ({| TLBEntry58 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry57' := e ]}" := ({| TLBEntry57 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry56' := e ]}" := ({| TLBEntry56 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry55' := e ]}" := ({| TLBEntry55 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry54' := e ]}" := ({| TLBEntry54 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry53' := e ]}" := ({| TLBEntry53 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry52' := e ]}" := ({| TLBEntry52 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry51' := e ]}" := ({| TLBEntry51 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry50' := e ]}" := ({| TLBEntry50 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry49' := e ]}" := ({| TLBEntry49 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry48' := e ]}" := ({| TLBEntry48 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry47' := e ]}" := ({| TLBEntry47 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry46' := e ]}" := ({| TLBEntry46 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry45' := e ]}" := ({| TLBEntry45 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry44' := e ]}" := ({| TLBEntry44 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry43' := e ]}" := ({| TLBEntry43 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry42' := e ]}" := ({| TLBEntry42 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry41' := e ]}" := ({| TLBEntry41 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry40' := e ]}" := ({| TLBEntry40 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry39' := e ]}" := ({| TLBEntry39 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry38' := e ]}" := ({| TLBEntry38 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry37' := e ]}" := ({| TLBEntry37 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry36' := e ]}" := ({| TLBEntry36 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry35' := e ]}" := ({| TLBEntry35 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry34' := e ]}" := ({| TLBEntry34 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry33' := e ]}" := ({| TLBEntry33 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry32' := e ]}" := ({| TLBEntry32 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry31' := e ]}" := ({| TLBEntry31 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry30' := e ]}" := ({| TLBEntry30 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry29' := e ]}" := ({| TLBEntry29 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry28' := e ]}" := ({| TLBEntry28 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry27' := e ]}" := ({| TLBEntry27 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry26' := e ]}" := ({| TLBEntry26 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry25' := e ]}" := ({| TLBEntry25 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry24' := e ]}" := ({| TLBEntry24 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry23' := e ]}" := ({| TLBEntry23 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry22' := e ]}" := ({| TLBEntry22 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry21' := e ]}" := ({| TLBEntry21 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry20' := e ]}" := ({| TLBEntry20 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry19' := e ]}" := ({| TLBEntry19 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry18' := e ]}" := ({| TLBEntry18 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry17' := e ]}" := ({| TLBEntry17 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry16' := e ]}" := ({| TLBEntry16 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry15' := e ]}" := ({| TLBEntry15 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry14' := e ]}" := ({| TLBEntry14 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry13' := e ]}" := ({| TLBEntry13 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry12' := e ]}" := ({| TLBEntry12 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry11' := e ]}" := ({| TLBEntry11 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry10' := e ]}" := ({| TLBEntry10 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry09' := e ]}" := ({| TLBEntry09 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry08' := e ]}" := ({| TLBEntry08 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry07' := e ]}" := ({| TLBEntry07 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry06' := e ]}" := ({| TLBEntry06 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry05' := e ]}" := ({| TLBEntry05 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry04' := e ]}" := ({| TLBEntry04 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry03' := e ]}" := ({| TLBEntry03 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry02' := e ]}" := ({| TLBEntry02 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry01' := e ]}" := ({| TLBEntry01 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry00' := e ]}" := ({| TLBEntry00 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBXContext' := e ]}" := ({| TLBXContext := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntryHi' := e ]}" := ({| TLBEntryHi := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBWired' := e ]}" := ({| TLBWired := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBPageMask' := e ]}" := ({| TLBPageMask := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBContext' := e ]}" := ({| TLBContext := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntryLo1' := e ]}" := ({| TLBEntryLo1 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntryLo0' := e ]}" := ({| TLBEntryLo0 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBRandom' := e ]}" := ({| TLBRandom := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBIndex' := e ]}" := ({| TLBIndex := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBProbe' := e ]}" := ({| TLBProbe := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'NextPC' := e ]}" := ({| NextPC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; PC := PC r |}). +Notation "{[ r 'with' 'PC' := e ]}" := ({| PC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r |}). + + + +Definition CapCauseReg_of_regval (merge_var : register_value) +: option CapCauseReg := + + match merge_var with | Regval_CapCauseReg (v) => Some (v) | g__15 => None end. + +Definition regval_of_CapCauseReg (v : CapCauseReg) : register_value := Regval_CapCauseReg (v). + +Definition Capability_of_regval (merge_var : register_value) +: option Capability := + + match merge_var with | Regval_Capability (v) => Some (v) | g__14 => None end. + +Definition regval_of_Capability (v : Capability) : register_value := Regval_Capability (v). + +Definition CauseReg_of_regval (merge_var : register_value) +: option CauseReg := + + match merge_var with | Regval_CauseReg (v) => Some (v) | g__13 => None end. + +Definition regval_of_CauseReg (v : CauseReg) : register_value := Regval_CauseReg (v). + +Definition ContextReg_of_regval (merge_var : register_value) +: option ContextReg := + + match merge_var with | Regval_ContextReg (v) => Some (v) | g__12 => None end. + +Definition regval_of_ContextReg (v : ContextReg) : register_value := Regval_ContextReg (v). + +Definition StatusReg_of_regval (merge_var : register_value) +: option StatusReg := + + match merge_var with | Regval_StatusReg (v) => Some (v) | g__11 => None end. + +Definition regval_of_StatusReg (v : StatusReg) : register_value := Regval_StatusReg (v). + +Definition TLBEntry_of_regval (merge_var : register_value) +: option TLBEntry := + + match merge_var with | Regval_TLBEntry (v) => Some (v) | g__10 => None end. + +Definition regval_of_TLBEntry (v : TLBEntry) : register_value := Regval_TLBEntry (v). + +Definition TLBEntryHiReg_of_regval (merge_var : register_value) +: option TLBEntryHiReg := + + match merge_var with | Regval_TLBEntryHiReg (v) => Some (v) | g__9 => None end. + +Definition regval_of_TLBEntryHiReg (v : TLBEntryHiReg) +: register_value := + + Regval_TLBEntryHiReg + (v). + +Definition TLBEntryLoReg_of_regval (merge_var : register_value) +: option TLBEntryLoReg := + + match merge_var with | Regval_TLBEntryLoReg (v) => Some (v) | g__8 => None end. + +Definition regval_of_TLBEntryLoReg (v : TLBEntryLoReg) +: register_value := + + Regval_TLBEntryLoReg + (v). + +Definition XContextReg_of_regval (merge_var : register_value) +: option XContextReg := + + match merge_var with | Regval_XContextReg (v) => Some (v) | g__7 => None end. + +Definition regval_of_XContextReg (v : XContextReg) : register_value := Regval_XContextReg (v). + +Definition vector_16_dec_bit_of_regval (merge_var : register_value) +: option (mword 16) := + + match merge_var with | Regval_vector_16_dec_bit (v) => Some (v) | g__6 => None end. + +Definition regval_of_vector_16_dec_bit (v : mword 16) +: register_value := + + Regval_vector_16_dec_bit + (v). + +Definition vector_1_dec_bit_of_regval (merge_var : register_value) +: option (mword 1) := + + match merge_var with | Regval_vector_1_dec_bit (v) => Some (v) | g__5 => None end. + +Definition regval_of_vector_1_dec_bit (v : mword 1) +: register_value := + + Regval_vector_1_dec_bit + (v). + +Definition vector_32_dec_bit_of_regval (merge_var : register_value) +: option (mword 32) := + + match merge_var with | Regval_vector_32_dec_bit (v) => Some (v) | g__4 => None end. + +Definition regval_of_vector_32_dec_bit (v : mword 32) +: register_value := + + Regval_vector_32_dec_bit + (v). + +Definition vector_3_dec_bit_of_regval (merge_var : register_value) +: option (mword 3) := + + match merge_var with | Regval_vector_3_dec_bit (v) => Some (v) | g__3 => None end. + +Definition regval_of_vector_3_dec_bit (v : mword 3) +: register_value := + + Regval_vector_3_dec_bit + (v). + +Definition vector_64_dec_bit_of_regval (merge_var : register_value) +: option (mword 64) := + + match merge_var with | Regval_vector_64_dec_bit (v) => Some (v) | g__2 => None end. + +Definition regval_of_vector_64_dec_bit (v : mword 64) +: register_value := + + Regval_vector_64_dec_bit + (v). + +Definition vector_6_dec_bit_of_regval (merge_var : register_value) +: option (mword 6) := + + match merge_var with | Regval_vector_6_dec_bit (v) => Some (v) | g__1 => None end. + +Definition regval_of_vector_6_dec_bit (v : mword 6) +: register_value := + + Regval_vector_6_dec_bit + (v). + +Definition vector_8_dec_bit_of_regval (merge_var : register_value) +: option (mword 8) := + + match merge_var with | Regval_vector_8_dec_bit (v) => Some (v) | g__0 => None end. + +Definition regval_of_vector_8_dec_bit (v : mword 8) +: register_value := + + Regval_vector_8_dec_bit + (v). + + + +Definition vector_of_regval {a} n (of_regval : register_value -> option a) (rv : register_value) : option (vec a n) := match rv with + | Regval_vector (n', _, v) => if n =? n' then map_bind (vec_of_list n) (just_list (List.map of_regval v)) else None + | _ => None +end. + +Definition regval_of_vector {a} (regval_of : a -> register_value) (size : Z) (is_inc : bool) (xs : vec a size) : register_value := Regval_vector (size, is_inc, List.map regval_of (list_of_vec xs)). + +Definition list_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (list a) := match rv with + | Regval_list v => just_list (List.map of_regval v) + | _ => None +end. + +Definition regval_of_list {a} (regval_of : a -> register_value) (xs : list a) : register_value := Regval_list (List.map regval_of xs). + +Definition option_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (option a) := match rv with + | Regval_option v => option_map of_regval v + | _ => None +end. + +Definition regval_of_option {a} (regval_of : a -> register_value) (v : option a) := Regval_option (option_map regval_of v). + + +Definition CID_ref := {| + name := "CID"; + read_from := (fun s => s.(CID)); + write_to := (fun v s => ({[ s with CID := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CapCause_ref := {| + name := "CapCause"; + read_from := (fun s => s.(CapCause)); + write_to := (fun v s => ({[ s with CapCause := v ]})); + of_regval := (fun v => CapCauseReg_of_regval v); + regval_of := (fun v => regval_of_CapCauseReg v) |}. + +Definition KDC_ref := {| + name := "KDC"; + read_from := (fun s => s.(KDC)); + write_to := (fun v s => ({[ s with KDC := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition KR2C_ref := {| + name := "KR2C"; + read_from := (fun s => s.(KR2C)); + write_to := (fun v s => ({[ s with KR2C := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition KR1C_ref := {| + name := "KR1C"; + read_from := (fun s => s.(KR1C)); + write_to := (fun v s => ({[ s with KR1C := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition CTLSP_ref := {| + name := "CTLSP"; + read_from := (fun s => s.(CTLSP)); + write_to := (fun v s => ({[ s with CTLSP := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition CTLSU_ref := {| + name := "CTLSU"; + read_from := (fun s => s.(CTLSU)); + write_to := (fun v s => ({[ s with CTLSU := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C31_ref := {| + name := "C31"; + read_from := (fun s => s.(C31)); + write_to := (fun v s => ({[ s with C31 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C30_ref := {| + name := "C30"; + read_from := (fun s => s.(C30)); + write_to := (fun v s => ({[ s with C30 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C29_ref := {| + name := "C29"; + read_from := (fun s => s.(C29)); + write_to := (fun v s => ({[ s with C29 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C28_ref := {| + name := "C28"; + read_from := (fun s => s.(C28)); + write_to := (fun v s => ({[ s with C28 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C27_ref := {| + name := "C27"; + read_from := (fun s => s.(C27)); + write_to := (fun v s => ({[ s with C27 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C26_ref := {| + name := "C26"; + read_from := (fun s => s.(C26)); + write_to := (fun v s => ({[ s with C26 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C25_ref := {| + name := "C25"; + read_from := (fun s => s.(C25)); + write_to := (fun v s => ({[ s with C25 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C24_ref := {| + name := "C24"; + read_from := (fun s => s.(C24)); + write_to := (fun v s => ({[ s with C24 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C23_ref := {| + name := "C23"; + read_from := (fun s => s.(C23)); + write_to := (fun v s => ({[ s with C23 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C22_ref := {| + name := "C22"; + read_from := (fun s => s.(C22)); + write_to := (fun v s => ({[ s with C22 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C21_ref := {| + name := "C21"; + read_from := (fun s => s.(C21)); + write_to := (fun v s => ({[ s with C21 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C20_ref := {| + name := "C20"; + read_from := (fun s => s.(C20)); + write_to := (fun v s => ({[ s with C20 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C19_ref := {| + name := "C19"; + read_from := (fun s => s.(C19)); + write_to := (fun v s => ({[ s with C19 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C18_ref := {| + name := "C18"; + read_from := (fun s => s.(C18)); + write_to := (fun v s => ({[ s with C18 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C17_ref := {| + name := "C17"; + read_from := (fun s => s.(C17)); + write_to := (fun v s => ({[ s with C17 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C16_ref := {| + name := "C16"; + read_from := (fun s => s.(C16)); + write_to := (fun v s => ({[ s with C16 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C15_ref := {| + name := "C15"; + read_from := (fun s => s.(C15)); + write_to := (fun v s => ({[ s with C15 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C14_ref := {| + name := "C14"; + read_from := (fun s => s.(C14)); + write_to := (fun v s => ({[ s with C14 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C13_ref := {| + name := "C13"; + read_from := (fun s => s.(C13)); + write_to := (fun v s => ({[ s with C13 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C12_ref := {| + name := "C12"; + read_from := (fun s => s.(C12)); + write_to := (fun v s => ({[ s with C12 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C11_ref := {| + name := "C11"; + read_from := (fun s => s.(C11)); + write_to := (fun v s => ({[ s with C11 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C10_ref := {| + name := "C10"; + read_from := (fun s => s.(C10)); + write_to := (fun v s => ({[ s with C10 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C09_ref := {| + name := "C09"; + read_from := (fun s => s.(C09)); + write_to := (fun v s => ({[ s with C09 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C08_ref := {| + name := "C08"; + read_from := (fun s => s.(C08)); + write_to := (fun v s => ({[ s with C08 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C07_ref := {| + name := "C07"; + read_from := (fun s => s.(C07)); + write_to := (fun v s => ({[ s with C07 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C06_ref := {| + name := "C06"; + read_from := (fun s => s.(C06)); + write_to := (fun v s => ({[ s with C06 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C05_ref := {| + name := "C05"; + read_from := (fun s => s.(C05)); + write_to := (fun v s => ({[ s with C05 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C04_ref := {| + name := "C04"; + read_from := (fun s => s.(C04)); + write_to := (fun v s => ({[ s with C04 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C03_ref := {| + name := "C03"; + read_from := (fun s => s.(C03)); + write_to := (fun v s => ({[ s with C03 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C02_ref := {| + name := "C02"; + read_from := (fun s => s.(C02)); + write_to := (fun v s => ({[ s with C02 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C01_ref := {| + name := "C01"; + read_from := (fun s => s.(C01)); + write_to := (fun v s => ({[ s with C01 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition DDC_ref := {| + name := "DDC"; + read_from := (fun s => s.(DDC)); + write_to := (fun v s => ({[ s with DDC := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition NextPCC_ref := {| + name := "NextPCC"; + read_from := (fun s => s.(NextPCC)); + write_to := (fun v s => ({[ s with NextPCC := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition DelayedPCC_ref := {| + name := "DelayedPCC"; + read_from := (fun s => s.(DelayedPCC)); + write_to := (fun v s => ({[ s with DelayedPCC := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition PCC_ref := {| + name := "PCC"; + read_from := (fun s => s.(PCC)); + write_to := (fun v s => ({[ s with PCC := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition KCC_ref := {| + name := "KCC"; + read_from := (fun s => s.(KCC)); + write_to := (fun v s => ({[ s with KCC := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition EPCC_ref := {| + name := "EPCC"; + read_from := (fun s => s.(EPCC)); + write_to := (fun v s => ({[ s with EPCC := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition UART_RVALID_ref := {| + name := "UART_RVALID"; + read_from := (fun s => s.(UART_RVALID)); + write_to := (fun v s => ({[ s with UART_RVALID := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition UART_RDATA_ref := {| + name := "UART_RDATA"; + read_from := (fun s => s.(UART_RDATA)); + write_to := (fun v s => ({[ s with UART_RDATA := v ]})); + of_regval := (fun v => vector_8_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_8_dec_bit v) |}. + +Definition UART_WRITTEN_ref := {| + name := "UART_WRITTEN"; + read_from := (fun s => s.(UART_WRITTEN)); + write_to := (fun v s => ({[ s with UART_WRITTEN := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition UART_WDATA_ref := {| + name := "UART_WDATA"; + read_from := (fun s => s.(UART_WDATA)); + write_to := (fun v s => ({[ s with UART_WDATA := v ]})); + of_regval := (fun v => vector_8_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_8_dec_bit v) |}. + +Definition GPR_ref := {| + name := "GPR"; + read_from := (fun s => s.(GPR)); + write_to := (fun v s => ({[ s with GPR := v ]})); + of_regval := (fun v => vector_of_regval 32 (fun v => vector_64_dec_bit_of_regval v) v); + regval_of := (fun v => regval_of_vector (fun v => regval_of_vector_64_dec_bit v) 32 false v) |}. + +Definition LO_ref := {| + name := "LO"; + read_from := (fun s => s.(LO)); + write_to := (fun v s => ({[ s with LO := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition HI_ref := {| + name := "HI"; + read_from := (fun s => s.(HI)); + write_to := (fun v s => ({[ s with HI := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition DelayedPC_ref := {| + name := "DelayedPC"; + read_from := (fun s => s.(DelayedPC)); + write_to := (fun v s => ({[ s with DelayedPC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition BranchPending_ref := {| + name := "BranchPending"; + read_from := (fun s => s.(BranchPending)); + write_to := (fun v s => ({[ s with BranchPending := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition InBranchDelay_ref := {| + name := "InBranchDelay"; + read_from := (fun s => s.(InBranchDelay)); + write_to := (fun v s => ({[ s with InBranchDelay := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition NextInBranchDelay_ref := {| + name := "NextInBranchDelay"; + read_from := (fun s => s.(NextInBranchDelay)); + write_to := (fun v s => ({[ s with NextInBranchDelay := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition CP0Status_ref := {| + name := "CP0Status"; + read_from := (fun s => s.(CP0Status)); + write_to := (fun v s => ({[ s with CP0Status := v ]})); + of_regval := (fun v => StatusReg_of_regval v); + regval_of := (fun v => regval_of_StatusReg v) |}. + +Definition CP0ConfigK0_ref := {| + name := "CP0ConfigK0"; + read_from := (fun s => s.(CP0ConfigK0)); + write_to := (fun v s => ({[ s with CP0ConfigK0 := v ]})); + of_regval := (fun v => vector_3_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_3_dec_bit v) |}. + +Definition CP0UserLocal_ref := {| + name := "CP0UserLocal"; + read_from := (fun s => s.(CP0UserLocal)); + write_to := (fun v s => ({[ s with CP0UserLocal := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CP0HWREna_ref := {| + name := "CP0HWREna"; + read_from := (fun s => s.(CP0HWREna)); + write_to := (fun v s => ({[ s with CP0HWREna := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition CP0Count_ref := {| + name := "CP0Count"; + read_from := (fun s => s.(CP0Count)); + write_to := (fun v s => ({[ s with CP0Count := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition CP0BadInstrP_ref := {| + name := "CP0BadInstrP"; + read_from := (fun s => s.(CP0BadInstrP)); + write_to := (fun v s => ({[ s with CP0BadInstrP := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition CP0BadInstr_ref := {| + name := "CP0BadInstr"; + read_from := (fun s => s.(CP0BadInstr)); + write_to := (fun v s => ({[ s with CP0BadInstr := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition LastInstrBits_ref := {| + name := "LastInstrBits"; + read_from := (fun s => s.(LastInstrBits)); + write_to := (fun v s => ({[ s with LastInstrBits := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition CurrentInstrBits_ref := {| + name := "CurrentInstrBits"; + read_from := (fun s => s.(CurrentInstrBits)); + write_to := (fun v s => ({[ s with CurrentInstrBits := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition CP0BadVAddr_ref := {| + name := "CP0BadVAddr"; + read_from := (fun s => s.(CP0BadVAddr)); + write_to := (fun v s => ({[ s with CP0BadVAddr := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CP0LLAddr_ref := {| + name := "CP0LLAddr"; + read_from := (fun s => s.(CP0LLAddr)); + write_to := (fun v s => ({[ s with CP0LLAddr := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CP0LLBit_ref := {| + name := "CP0LLBit"; + read_from := (fun s => s.(CP0LLBit)); + write_to := (fun v s => ({[ s with CP0LLBit := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition CP0ErrorEPC_ref := {| + name := "CP0ErrorEPC"; + read_from := (fun s => s.(CP0ErrorEPC)); + write_to := (fun v s => ({[ s with CP0ErrorEPC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CP0EPC_ref := {| + name := "CP0EPC"; + read_from := (fun s => s.(CP0EPC)); + write_to := (fun v s => ({[ s with CP0EPC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CP0Cause_ref := {| + name := "CP0Cause"; + read_from := (fun s => s.(CP0Cause)); + write_to := (fun v s => ({[ s with CP0Cause := v ]})); + of_regval := (fun v => CauseReg_of_regval v); + regval_of := (fun v => regval_of_CauseReg v) |}. + +Definition CP0Compare_ref := {| + name := "CP0Compare"; + read_from := (fun s => s.(CP0Compare)); + write_to := (fun v s => ({[ s with CP0Compare := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition TLBEntry63_ref := {| + name := "TLBEntry63"; + read_from := (fun s => s.(TLBEntry63)); + write_to := (fun v s => ({[ s with TLBEntry63 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry62_ref := {| + name := "TLBEntry62"; + read_from := (fun s => s.(TLBEntry62)); + write_to := (fun v s => ({[ s with TLBEntry62 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry61_ref := {| + name := "TLBEntry61"; + read_from := (fun s => s.(TLBEntry61)); + write_to := (fun v s => ({[ s with TLBEntry61 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry60_ref := {| + name := "TLBEntry60"; + read_from := (fun s => s.(TLBEntry60)); + write_to := (fun v s => ({[ s with TLBEntry60 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry59_ref := {| + name := "TLBEntry59"; + read_from := (fun s => s.(TLBEntry59)); + write_to := (fun v s => ({[ s with TLBEntry59 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry58_ref := {| + name := "TLBEntry58"; + read_from := (fun s => s.(TLBEntry58)); + write_to := (fun v s => ({[ s with TLBEntry58 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry57_ref := {| + name := "TLBEntry57"; + read_from := (fun s => s.(TLBEntry57)); + write_to := (fun v s => ({[ s with TLBEntry57 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry56_ref := {| + name := "TLBEntry56"; + read_from := (fun s => s.(TLBEntry56)); + write_to := (fun v s => ({[ s with TLBEntry56 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry55_ref := {| + name := "TLBEntry55"; + read_from := (fun s => s.(TLBEntry55)); + write_to := (fun v s => ({[ s with TLBEntry55 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry54_ref := {| + name := "TLBEntry54"; + read_from := (fun s => s.(TLBEntry54)); + write_to := (fun v s => ({[ s with TLBEntry54 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry53_ref := {| + name := "TLBEntry53"; + read_from := (fun s => s.(TLBEntry53)); + write_to := (fun v s => ({[ s with TLBEntry53 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry52_ref := {| + name := "TLBEntry52"; + read_from := (fun s => s.(TLBEntry52)); + write_to := (fun v s => ({[ s with TLBEntry52 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry51_ref := {| + name := "TLBEntry51"; + read_from := (fun s => s.(TLBEntry51)); + write_to := (fun v s => ({[ s with TLBEntry51 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry50_ref := {| + name := "TLBEntry50"; + read_from := (fun s => s.(TLBEntry50)); + write_to := (fun v s => ({[ s with TLBEntry50 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry49_ref := {| + name := "TLBEntry49"; + read_from := (fun s => s.(TLBEntry49)); + write_to := (fun v s => ({[ s with TLBEntry49 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry48_ref := {| + name := "TLBEntry48"; + read_from := (fun s => s.(TLBEntry48)); + write_to := (fun v s => ({[ s with TLBEntry48 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry47_ref := {| + name := "TLBEntry47"; + read_from := (fun s => s.(TLBEntry47)); + write_to := (fun v s => ({[ s with TLBEntry47 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry46_ref := {| + name := "TLBEntry46"; + read_from := (fun s => s.(TLBEntry46)); + write_to := (fun v s => ({[ s with TLBEntry46 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry45_ref := {| + name := "TLBEntry45"; + read_from := (fun s => s.(TLBEntry45)); + write_to := (fun v s => ({[ s with TLBEntry45 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry44_ref := {| + name := "TLBEntry44"; + read_from := (fun s => s.(TLBEntry44)); + write_to := (fun v s => ({[ s with TLBEntry44 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry43_ref := {| + name := "TLBEntry43"; + read_from := (fun s => s.(TLBEntry43)); + write_to := (fun v s => ({[ s with TLBEntry43 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry42_ref := {| + name := "TLBEntry42"; + read_from := (fun s => s.(TLBEntry42)); + write_to := (fun v s => ({[ s with TLBEntry42 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry41_ref := {| + name := "TLBEntry41"; + read_from := (fun s => s.(TLBEntry41)); + write_to := (fun v s => ({[ s with TLBEntry41 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry40_ref := {| + name := "TLBEntry40"; + read_from := (fun s => s.(TLBEntry40)); + write_to := (fun v s => ({[ s with TLBEntry40 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry39_ref := {| + name := "TLBEntry39"; + read_from := (fun s => s.(TLBEntry39)); + write_to := (fun v s => ({[ s with TLBEntry39 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry38_ref := {| + name := "TLBEntry38"; + read_from := (fun s => s.(TLBEntry38)); + write_to := (fun v s => ({[ s with TLBEntry38 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry37_ref := {| + name := "TLBEntry37"; + read_from := (fun s => s.(TLBEntry37)); + write_to := (fun v s => ({[ s with TLBEntry37 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry36_ref := {| + name := "TLBEntry36"; + read_from := (fun s => s.(TLBEntry36)); + write_to := (fun v s => ({[ s with TLBEntry36 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry35_ref := {| + name := "TLBEntry35"; + read_from := (fun s => s.(TLBEntry35)); + write_to := (fun v s => ({[ s with TLBEntry35 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry34_ref := {| + name := "TLBEntry34"; + read_from := (fun s => s.(TLBEntry34)); + write_to := (fun v s => ({[ s with TLBEntry34 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry33_ref := {| + name := "TLBEntry33"; + read_from := (fun s => s.(TLBEntry33)); + write_to := (fun v s => ({[ s with TLBEntry33 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry32_ref := {| + name := "TLBEntry32"; + read_from := (fun s => s.(TLBEntry32)); + write_to := (fun v s => ({[ s with TLBEntry32 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry31_ref := {| + name := "TLBEntry31"; + read_from := (fun s => s.(TLBEntry31)); + write_to := (fun v s => ({[ s with TLBEntry31 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry30_ref := {| + name := "TLBEntry30"; + read_from := (fun s => s.(TLBEntry30)); + write_to := (fun v s => ({[ s with TLBEntry30 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry29_ref := {| + name := "TLBEntry29"; + read_from := (fun s => s.(TLBEntry29)); + write_to := (fun v s => ({[ s with TLBEntry29 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry28_ref := {| + name := "TLBEntry28"; + read_from := (fun s => s.(TLBEntry28)); + write_to := (fun v s => ({[ s with TLBEntry28 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry27_ref := {| + name := "TLBEntry27"; + read_from := (fun s => s.(TLBEntry27)); + write_to := (fun v s => ({[ s with TLBEntry27 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry26_ref := {| + name := "TLBEntry26"; + read_from := (fun s => s.(TLBEntry26)); + write_to := (fun v s => ({[ s with TLBEntry26 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry25_ref := {| + name := "TLBEntry25"; + read_from := (fun s => s.(TLBEntry25)); + write_to := (fun v s => ({[ s with TLBEntry25 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry24_ref := {| + name := "TLBEntry24"; + read_from := (fun s => s.(TLBEntry24)); + write_to := (fun v s => ({[ s with TLBEntry24 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry23_ref := {| + name := "TLBEntry23"; + read_from := (fun s => s.(TLBEntry23)); + write_to := (fun v s => ({[ s with TLBEntry23 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry22_ref := {| + name := "TLBEntry22"; + read_from := (fun s => s.(TLBEntry22)); + write_to := (fun v s => ({[ s with TLBEntry22 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry21_ref := {| + name := "TLBEntry21"; + read_from := (fun s => s.(TLBEntry21)); + write_to := (fun v s => ({[ s with TLBEntry21 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry20_ref := {| + name := "TLBEntry20"; + read_from := (fun s => s.(TLBEntry20)); + write_to := (fun v s => ({[ s with TLBEntry20 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry19_ref := {| + name := "TLBEntry19"; + read_from := (fun s => s.(TLBEntry19)); + write_to := (fun v s => ({[ s with TLBEntry19 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry18_ref := {| + name := "TLBEntry18"; + read_from := (fun s => s.(TLBEntry18)); + write_to := (fun v s => ({[ s with TLBEntry18 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry17_ref := {| + name := "TLBEntry17"; + read_from := (fun s => s.(TLBEntry17)); + write_to := (fun v s => ({[ s with TLBEntry17 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry16_ref := {| + name := "TLBEntry16"; + read_from := (fun s => s.(TLBEntry16)); + write_to := (fun v s => ({[ s with TLBEntry16 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry15_ref := {| + name := "TLBEntry15"; + read_from := (fun s => s.(TLBEntry15)); + write_to := (fun v s => ({[ s with TLBEntry15 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry14_ref := {| + name := "TLBEntry14"; + read_from := (fun s => s.(TLBEntry14)); + write_to := (fun v s => ({[ s with TLBEntry14 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry13_ref := {| + name := "TLBEntry13"; + read_from := (fun s => s.(TLBEntry13)); + write_to := (fun v s => ({[ s with TLBEntry13 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry12_ref := {| + name := "TLBEntry12"; + read_from := (fun s => s.(TLBEntry12)); + write_to := (fun v s => ({[ s with TLBEntry12 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry11_ref := {| + name := "TLBEntry11"; + read_from := (fun s => s.(TLBEntry11)); + write_to := (fun v s => ({[ s with TLBEntry11 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry10_ref := {| + name := "TLBEntry10"; + read_from := (fun s => s.(TLBEntry10)); + write_to := (fun v s => ({[ s with TLBEntry10 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry09_ref := {| + name := "TLBEntry09"; + read_from := (fun s => s.(TLBEntry09)); + write_to := (fun v s => ({[ s with TLBEntry09 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry08_ref := {| + name := "TLBEntry08"; + read_from := (fun s => s.(TLBEntry08)); + write_to := (fun v s => ({[ s with TLBEntry08 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry07_ref := {| + name := "TLBEntry07"; + read_from := (fun s => s.(TLBEntry07)); + write_to := (fun v s => ({[ s with TLBEntry07 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry06_ref := {| + name := "TLBEntry06"; + read_from := (fun s => s.(TLBEntry06)); + write_to := (fun v s => ({[ s with TLBEntry06 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry05_ref := {| + name := "TLBEntry05"; + read_from := (fun s => s.(TLBEntry05)); + write_to := (fun v s => ({[ s with TLBEntry05 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry04_ref := {| + name := "TLBEntry04"; + read_from := (fun s => s.(TLBEntry04)); + write_to := (fun v s => ({[ s with TLBEntry04 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry03_ref := {| + name := "TLBEntry03"; + read_from := (fun s => s.(TLBEntry03)); + write_to := (fun v s => ({[ s with TLBEntry03 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry02_ref := {| + name := "TLBEntry02"; + read_from := (fun s => s.(TLBEntry02)); + write_to := (fun v s => ({[ s with TLBEntry02 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry01_ref := {| + name := "TLBEntry01"; + read_from := (fun s => s.(TLBEntry01)); + write_to := (fun v s => ({[ s with TLBEntry01 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry00_ref := {| + name := "TLBEntry00"; + read_from := (fun s => s.(TLBEntry00)); + write_to := (fun v s => ({[ s with TLBEntry00 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBXContext_ref := {| + name := "TLBXContext"; + read_from := (fun s => s.(TLBXContext)); + write_to := (fun v s => ({[ s with TLBXContext := v ]})); + of_regval := (fun v => XContextReg_of_regval v); + regval_of := (fun v => regval_of_XContextReg v) |}. + +Definition TLBEntryHi_ref := {| + name := "TLBEntryHi"; + read_from := (fun s => s.(TLBEntryHi)); + write_to := (fun v s => ({[ s with TLBEntryHi := v ]})); + of_regval := (fun v => TLBEntryHiReg_of_regval v); + regval_of := (fun v => regval_of_TLBEntryHiReg v) |}. + +Definition TLBWired_ref := {| + name := "TLBWired"; + read_from := (fun s => s.(TLBWired)); + write_to := (fun v s => ({[ s with TLBWired := v ]})); + of_regval := (fun v => vector_6_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_6_dec_bit v) |}. + +Definition TLBPageMask_ref := {| + name := "TLBPageMask"; + read_from := (fun s => s.(TLBPageMask)); + write_to := (fun v s => ({[ s with TLBPageMask := v ]})); + of_regval := (fun v => vector_16_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_16_dec_bit v) |}. + +Definition TLBContext_ref := {| + name := "TLBContext"; + read_from := (fun s => s.(TLBContext)); + write_to := (fun v s => ({[ s with TLBContext := v ]})); + of_regval := (fun v => ContextReg_of_regval v); + regval_of := (fun v => regval_of_ContextReg v) |}. + +Definition TLBEntryLo1_ref := {| + name := "TLBEntryLo1"; + read_from := (fun s => s.(TLBEntryLo1)); + write_to := (fun v s => ({[ s with TLBEntryLo1 := v ]})); + of_regval := (fun v => TLBEntryLoReg_of_regval v); + regval_of := (fun v => regval_of_TLBEntryLoReg v) |}. + +Definition TLBEntryLo0_ref := {| + name := "TLBEntryLo0"; + read_from := (fun s => s.(TLBEntryLo0)); + write_to := (fun v s => ({[ s with TLBEntryLo0 := v ]})); + of_regval := (fun v => TLBEntryLoReg_of_regval v); + regval_of := (fun v => regval_of_TLBEntryLoReg v) |}. + +Definition TLBRandom_ref := {| + name := "TLBRandom"; + read_from := (fun s => s.(TLBRandom)); + write_to := (fun v s => ({[ s with TLBRandom := v ]})); + of_regval := (fun v => vector_6_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_6_dec_bit v) |}. + +Definition TLBIndex_ref := {| + name := "TLBIndex"; + read_from := (fun s => s.(TLBIndex)); + write_to := (fun v s => ({[ s with TLBIndex := v ]})); + of_regval := (fun v => vector_6_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_6_dec_bit v) |}. + +Definition TLBProbe_ref := {| + name := "TLBProbe"; + read_from := (fun s => s.(TLBProbe)); + write_to := (fun v s => ({[ s with TLBProbe := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition NextPC_ref := {| + name := "NextPC"; + read_from := (fun s => s.(NextPC)); + write_to := (fun v s => ({[ s with NextPC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition PC_ref := {| + name := "PC"; + read_from := (fun s => s.(PC)); + write_to := (fun v s => ({[ s with PC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Local Open Scope string. +Definition get_regval (reg_name : string) (s : regstate) : option register_value := + if string_dec reg_name "CID" then Some (CID_ref.(regval_of) (CID_ref.(read_from) s)) else + if string_dec reg_name "CapCause" then Some (CapCause_ref.(regval_of) (CapCause_ref.(read_from) s)) else + if string_dec reg_name "KDC" then Some (KDC_ref.(regval_of) (KDC_ref.(read_from) s)) else + if string_dec reg_name "KR2C" then Some (KR2C_ref.(regval_of) (KR2C_ref.(read_from) s)) else + if string_dec reg_name "KR1C" then Some (KR1C_ref.(regval_of) (KR1C_ref.(read_from) s)) else + if string_dec reg_name "CTLSP" then Some (CTLSP_ref.(regval_of) (CTLSP_ref.(read_from) s)) else + if string_dec reg_name "CTLSU" then Some (CTLSU_ref.(regval_of) (CTLSU_ref.(read_from) s)) else + if string_dec reg_name "C31" then Some (C31_ref.(regval_of) (C31_ref.(read_from) s)) else + if string_dec reg_name "C30" then Some (C30_ref.(regval_of) (C30_ref.(read_from) s)) else + if string_dec reg_name "C29" then Some (C29_ref.(regval_of) (C29_ref.(read_from) s)) else + if string_dec reg_name "C28" then Some (C28_ref.(regval_of) (C28_ref.(read_from) s)) else + if string_dec reg_name "C27" then Some (C27_ref.(regval_of) (C27_ref.(read_from) s)) else + if string_dec reg_name "C26" then Some (C26_ref.(regval_of) (C26_ref.(read_from) s)) else + if string_dec reg_name "C25" then Some (C25_ref.(regval_of) (C25_ref.(read_from) s)) else + if string_dec reg_name "C24" then Some (C24_ref.(regval_of) (C24_ref.(read_from) s)) else + if string_dec reg_name "C23" then Some (C23_ref.(regval_of) (C23_ref.(read_from) s)) else + if string_dec reg_name "C22" then Some (C22_ref.(regval_of) (C22_ref.(read_from) s)) else + if string_dec reg_name "C21" then Some (C21_ref.(regval_of) (C21_ref.(read_from) s)) else + if string_dec reg_name "C20" then Some (C20_ref.(regval_of) (C20_ref.(read_from) s)) else + if string_dec reg_name "C19" then Some (C19_ref.(regval_of) (C19_ref.(read_from) s)) else + if string_dec reg_name "C18" then Some (C18_ref.(regval_of) (C18_ref.(read_from) s)) else + if string_dec reg_name "C17" then Some (C17_ref.(regval_of) (C17_ref.(read_from) s)) else + if string_dec reg_name "C16" then Some (C16_ref.(regval_of) (C16_ref.(read_from) s)) else + if string_dec reg_name "C15" then Some (C15_ref.(regval_of) (C15_ref.(read_from) s)) else + if string_dec reg_name "C14" then Some (C14_ref.(regval_of) (C14_ref.(read_from) s)) else + if string_dec reg_name "C13" then Some (C13_ref.(regval_of) (C13_ref.(read_from) s)) else + if string_dec reg_name "C12" then Some (C12_ref.(regval_of) (C12_ref.(read_from) s)) else + if string_dec reg_name "C11" then Some (C11_ref.(regval_of) (C11_ref.(read_from) s)) else + if string_dec reg_name "C10" then Some (C10_ref.(regval_of) (C10_ref.(read_from) s)) else + if string_dec reg_name "C09" then Some (C09_ref.(regval_of) (C09_ref.(read_from) s)) else + if string_dec reg_name "C08" then Some (C08_ref.(regval_of) (C08_ref.(read_from) s)) else + if string_dec reg_name "C07" then Some (C07_ref.(regval_of) (C07_ref.(read_from) s)) else + if string_dec reg_name "C06" then Some (C06_ref.(regval_of) (C06_ref.(read_from) s)) else + if string_dec reg_name "C05" then Some (C05_ref.(regval_of) (C05_ref.(read_from) s)) else + if string_dec reg_name "C04" then Some (C04_ref.(regval_of) (C04_ref.(read_from) s)) else + if string_dec reg_name "C03" then Some (C03_ref.(regval_of) (C03_ref.(read_from) s)) else + if string_dec reg_name "C02" then Some (C02_ref.(regval_of) (C02_ref.(read_from) s)) else + if string_dec reg_name "C01" then Some (C01_ref.(regval_of) (C01_ref.(read_from) s)) else + if string_dec reg_name "DDC" then Some (DDC_ref.(regval_of) (DDC_ref.(read_from) s)) else + if string_dec reg_name "NextPCC" then Some (NextPCC_ref.(regval_of) (NextPCC_ref.(read_from) s)) else + if string_dec reg_name "DelayedPCC" then Some (DelayedPCC_ref.(regval_of) (DelayedPCC_ref.(read_from) s)) else + if string_dec reg_name "PCC" then Some (PCC_ref.(regval_of) (PCC_ref.(read_from) s)) else + if string_dec reg_name "KCC" then Some (KCC_ref.(regval_of) (KCC_ref.(read_from) s)) else + if string_dec reg_name "EPCC" then Some (EPCC_ref.(regval_of) (EPCC_ref.(read_from) s)) else + if string_dec reg_name "UART_RVALID" then Some (UART_RVALID_ref.(regval_of) (UART_RVALID_ref.(read_from) s)) else + if string_dec reg_name "UART_RDATA" then Some (UART_RDATA_ref.(regval_of) (UART_RDATA_ref.(read_from) s)) else + if string_dec reg_name "UART_WRITTEN" then Some (UART_WRITTEN_ref.(regval_of) (UART_WRITTEN_ref.(read_from) s)) else + if string_dec reg_name "UART_WDATA" then Some (UART_WDATA_ref.(regval_of) (UART_WDATA_ref.(read_from) s)) else + if string_dec reg_name "GPR" then Some (GPR_ref.(regval_of) (GPR_ref.(read_from) s)) else + if string_dec reg_name "LO" then Some (LO_ref.(regval_of) (LO_ref.(read_from) s)) else + if string_dec reg_name "HI" then Some (HI_ref.(regval_of) (HI_ref.(read_from) s)) else + if string_dec reg_name "DelayedPC" then Some (DelayedPC_ref.(regval_of) (DelayedPC_ref.(read_from) s)) else + if string_dec reg_name "BranchPending" then Some (BranchPending_ref.(regval_of) (BranchPending_ref.(read_from) s)) else + if string_dec reg_name "InBranchDelay" then Some (InBranchDelay_ref.(regval_of) (InBranchDelay_ref.(read_from) s)) else + if string_dec reg_name "NextInBranchDelay" then Some (NextInBranchDelay_ref.(regval_of) (NextInBranchDelay_ref.(read_from) s)) else + if string_dec reg_name "CP0Status" then Some (CP0Status_ref.(regval_of) (CP0Status_ref.(read_from) s)) else + if string_dec reg_name "CP0ConfigK0" then Some (CP0ConfigK0_ref.(regval_of) (CP0ConfigK0_ref.(read_from) s)) else + if string_dec reg_name "CP0UserLocal" then Some (CP0UserLocal_ref.(regval_of) (CP0UserLocal_ref.(read_from) s)) else + if string_dec reg_name "CP0HWREna" then Some (CP0HWREna_ref.(regval_of) (CP0HWREna_ref.(read_from) s)) else + if string_dec reg_name "CP0Count" then Some (CP0Count_ref.(regval_of) (CP0Count_ref.(read_from) s)) else + if string_dec reg_name "CP0BadInstrP" then Some (CP0BadInstrP_ref.(regval_of) (CP0BadInstrP_ref.(read_from) s)) else + if string_dec reg_name "CP0BadInstr" then Some (CP0BadInstr_ref.(regval_of) (CP0BadInstr_ref.(read_from) s)) else + if string_dec reg_name "LastInstrBits" then Some (LastInstrBits_ref.(regval_of) (LastInstrBits_ref.(read_from) s)) else + if string_dec reg_name "CurrentInstrBits" then Some (CurrentInstrBits_ref.(regval_of) (CurrentInstrBits_ref.(read_from) s)) else + if string_dec reg_name "CP0BadVAddr" then Some (CP0BadVAddr_ref.(regval_of) (CP0BadVAddr_ref.(read_from) s)) else + if string_dec reg_name "CP0LLAddr" then Some (CP0LLAddr_ref.(regval_of) (CP0LLAddr_ref.(read_from) s)) else + if string_dec reg_name "CP0LLBit" then Some (CP0LLBit_ref.(regval_of) (CP0LLBit_ref.(read_from) s)) else + if string_dec reg_name "CP0ErrorEPC" then Some (CP0ErrorEPC_ref.(regval_of) (CP0ErrorEPC_ref.(read_from) s)) else + if string_dec reg_name "CP0EPC" then Some (CP0EPC_ref.(regval_of) (CP0EPC_ref.(read_from) s)) else + if string_dec reg_name "CP0Cause" then Some (CP0Cause_ref.(regval_of) (CP0Cause_ref.(read_from) s)) else + if string_dec reg_name "CP0Compare" then Some (CP0Compare_ref.(regval_of) (CP0Compare_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry63" then Some (TLBEntry63_ref.(regval_of) (TLBEntry63_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry62" then Some (TLBEntry62_ref.(regval_of) (TLBEntry62_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry61" then Some (TLBEntry61_ref.(regval_of) (TLBEntry61_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry60" then Some (TLBEntry60_ref.(regval_of) (TLBEntry60_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry59" then Some (TLBEntry59_ref.(regval_of) (TLBEntry59_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry58" then Some (TLBEntry58_ref.(regval_of) (TLBEntry58_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry57" then Some (TLBEntry57_ref.(regval_of) (TLBEntry57_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry56" then Some (TLBEntry56_ref.(regval_of) (TLBEntry56_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry55" then Some (TLBEntry55_ref.(regval_of) (TLBEntry55_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry54" then Some (TLBEntry54_ref.(regval_of) (TLBEntry54_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry53" then Some (TLBEntry53_ref.(regval_of) (TLBEntry53_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry52" then Some (TLBEntry52_ref.(regval_of) (TLBEntry52_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry51" then Some (TLBEntry51_ref.(regval_of) (TLBEntry51_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry50" then Some (TLBEntry50_ref.(regval_of) (TLBEntry50_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry49" then Some (TLBEntry49_ref.(regval_of) (TLBEntry49_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry48" then Some (TLBEntry48_ref.(regval_of) (TLBEntry48_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry47" then Some (TLBEntry47_ref.(regval_of) (TLBEntry47_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry46" then Some (TLBEntry46_ref.(regval_of) (TLBEntry46_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry45" then Some (TLBEntry45_ref.(regval_of) (TLBEntry45_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry44" then Some (TLBEntry44_ref.(regval_of) (TLBEntry44_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry43" then Some (TLBEntry43_ref.(regval_of) (TLBEntry43_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry42" then Some (TLBEntry42_ref.(regval_of) (TLBEntry42_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry41" then Some (TLBEntry41_ref.(regval_of) (TLBEntry41_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry40" then Some (TLBEntry40_ref.(regval_of) (TLBEntry40_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry39" then Some (TLBEntry39_ref.(regval_of) (TLBEntry39_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry38" then Some (TLBEntry38_ref.(regval_of) (TLBEntry38_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry37" then Some (TLBEntry37_ref.(regval_of) (TLBEntry37_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry36" then Some (TLBEntry36_ref.(regval_of) (TLBEntry36_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry35" then Some (TLBEntry35_ref.(regval_of) (TLBEntry35_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry34" then Some (TLBEntry34_ref.(regval_of) (TLBEntry34_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry33" then Some (TLBEntry33_ref.(regval_of) (TLBEntry33_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry32" then Some (TLBEntry32_ref.(regval_of) (TLBEntry32_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry31" then Some (TLBEntry31_ref.(regval_of) (TLBEntry31_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry30" then Some (TLBEntry30_ref.(regval_of) (TLBEntry30_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry29" then Some (TLBEntry29_ref.(regval_of) (TLBEntry29_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry28" then Some (TLBEntry28_ref.(regval_of) (TLBEntry28_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry27" then Some (TLBEntry27_ref.(regval_of) (TLBEntry27_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry26" then Some (TLBEntry26_ref.(regval_of) (TLBEntry26_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry25" then Some (TLBEntry25_ref.(regval_of) (TLBEntry25_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry24" then Some (TLBEntry24_ref.(regval_of) (TLBEntry24_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry23" then Some (TLBEntry23_ref.(regval_of) (TLBEntry23_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry22" then Some (TLBEntry22_ref.(regval_of) (TLBEntry22_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry21" then Some (TLBEntry21_ref.(regval_of) (TLBEntry21_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry20" then Some (TLBEntry20_ref.(regval_of) (TLBEntry20_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry19" then Some (TLBEntry19_ref.(regval_of) (TLBEntry19_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry18" then Some (TLBEntry18_ref.(regval_of) (TLBEntry18_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry17" then Some (TLBEntry17_ref.(regval_of) (TLBEntry17_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry16" then Some (TLBEntry16_ref.(regval_of) (TLBEntry16_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry15" then Some (TLBEntry15_ref.(regval_of) (TLBEntry15_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry14" then Some (TLBEntry14_ref.(regval_of) (TLBEntry14_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry13" then Some (TLBEntry13_ref.(regval_of) (TLBEntry13_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry12" then Some (TLBEntry12_ref.(regval_of) (TLBEntry12_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry11" then Some (TLBEntry11_ref.(regval_of) (TLBEntry11_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry10" then Some (TLBEntry10_ref.(regval_of) (TLBEntry10_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry09" then Some (TLBEntry09_ref.(regval_of) (TLBEntry09_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry08" then Some (TLBEntry08_ref.(regval_of) (TLBEntry08_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry07" then Some (TLBEntry07_ref.(regval_of) (TLBEntry07_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry06" then Some (TLBEntry06_ref.(regval_of) (TLBEntry06_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry05" then Some (TLBEntry05_ref.(regval_of) (TLBEntry05_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry04" then Some (TLBEntry04_ref.(regval_of) (TLBEntry04_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry03" then Some (TLBEntry03_ref.(regval_of) (TLBEntry03_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry02" then Some (TLBEntry02_ref.(regval_of) (TLBEntry02_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry01" then Some (TLBEntry01_ref.(regval_of) (TLBEntry01_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry00" then Some (TLBEntry00_ref.(regval_of) (TLBEntry00_ref.(read_from) s)) else + if string_dec reg_name "TLBXContext" then Some (TLBXContext_ref.(regval_of) (TLBXContext_ref.(read_from) s)) else + if string_dec reg_name "TLBEntryHi" then Some (TLBEntryHi_ref.(regval_of) (TLBEntryHi_ref.(read_from) s)) else + if string_dec reg_name "TLBWired" then Some (TLBWired_ref.(regval_of) (TLBWired_ref.(read_from) s)) else + if string_dec reg_name "TLBPageMask" then Some (TLBPageMask_ref.(regval_of) (TLBPageMask_ref.(read_from) s)) else + if string_dec reg_name "TLBContext" then Some (TLBContext_ref.(regval_of) (TLBContext_ref.(read_from) s)) else + if string_dec reg_name "TLBEntryLo1" then Some (TLBEntryLo1_ref.(regval_of) (TLBEntryLo1_ref.(read_from) s)) else + if string_dec reg_name "TLBEntryLo0" then Some (TLBEntryLo0_ref.(regval_of) (TLBEntryLo0_ref.(read_from) s)) else + if string_dec reg_name "TLBRandom" then Some (TLBRandom_ref.(regval_of) (TLBRandom_ref.(read_from) s)) else + if string_dec reg_name "TLBIndex" then Some (TLBIndex_ref.(regval_of) (TLBIndex_ref.(read_from) s)) else + if string_dec reg_name "TLBProbe" then Some (TLBProbe_ref.(regval_of) (TLBProbe_ref.(read_from) s)) else + if string_dec reg_name "NextPC" then Some (NextPC_ref.(regval_of) (NextPC_ref.(read_from) s)) else + if string_dec reg_name "PC" then Some (PC_ref.(regval_of) (PC_ref.(read_from) s)) else + None. + +Definition set_regval (reg_name : string) (v : register_value) (s : regstate) : option regstate := + if string_dec reg_name "CID" then option_map (fun v => CID_ref.(write_to) v s) (CID_ref.(of_regval) v) else + if string_dec reg_name "CapCause" then option_map (fun v => CapCause_ref.(write_to) v s) (CapCause_ref.(of_regval) v) else + if string_dec reg_name "KDC" then option_map (fun v => KDC_ref.(write_to) v s) (KDC_ref.(of_regval) v) else + if string_dec reg_name "KR2C" then option_map (fun v => KR2C_ref.(write_to) v s) (KR2C_ref.(of_regval) v) else + if string_dec reg_name "KR1C" then option_map (fun v => KR1C_ref.(write_to) v s) (KR1C_ref.(of_regval) v) else + if string_dec reg_name "CTLSP" then option_map (fun v => CTLSP_ref.(write_to) v s) (CTLSP_ref.(of_regval) v) else + if string_dec reg_name "CTLSU" then option_map (fun v => CTLSU_ref.(write_to) v s) (CTLSU_ref.(of_regval) v) else + if string_dec reg_name "C31" then option_map (fun v => C31_ref.(write_to) v s) (C31_ref.(of_regval) v) else + if string_dec reg_name "C30" then option_map (fun v => C30_ref.(write_to) v s) (C30_ref.(of_regval) v) else + if string_dec reg_name "C29" then option_map (fun v => C29_ref.(write_to) v s) (C29_ref.(of_regval) v) else + if string_dec reg_name "C28" then option_map (fun v => C28_ref.(write_to) v s) (C28_ref.(of_regval) v) else + if string_dec reg_name "C27" then option_map (fun v => C27_ref.(write_to) v s) (C27_ref.(of_regval) v) else + if string_dec reg_name "C26" then option_map (fun v => C26_ref.(write_to) v s) (C26_ref.(of_regval) v) else + if string_dec reg_name "C25" then option_map (fun v => C25_ref.(write_to) v s) (C25_ref.(of_regval) v) else + if string_dec reg_name "C24" then option_map (fun v => C24_ref.(write_to) v s) (C24_ref.(of_regval) v) else + if string_dec reg_name "C23" then option_map (fun v => C23_ref.(write_to) v s) (C23_ref.(of_regval) v) else + if string_dec reg_name "C22" then option_map (fun v => C22_ref.(write_to) v s) (C22_ref.(of_regval) v) else + if string_dec reg_name "C21" then option_map (fun v => C21_ref.(write_to) v s) (C21_ref.(of_regval) v) else + if string_dec reg_name "C20" then option_map (fun v => C20_ref.(write_to) v s) (C20_ref.(of_regval) v) else + if string_dec reg_name "C19" then option_map (fun v => C19_ref.(write_to) v s) (C19_ref.(of_regval) v) else + if string_dec reg_name "C18" then option_map (fun v => C18_ref.(write_to) v s) (C18_ref.(of_regval) v) else + if string_dec reg_name "C17" then option_map (fun v => C17_ref.(write_to) v s) (C17_ref.(of_regval) v) else + if string_dec reg_name "C16" then option_map (fun v => C16_ref.(write_to) v s) (C16_ref.(of_regval) v) else + if string_dec reg_name "C15" then option_map (fun v => C15_ref.(write_to) v s) (C15_ref.(of_regval) v) else + if string_dec reg_name "C14" then option_map (fun v => C14_ref.(write_to) v s) (C14_ref.(of_regval) v) else + if string_dec reg_name "C13" then option_map (fun v => C13_ref.(write_to) v s) (C13_ref.(of_regval) v) else + if string_dec reg_name "C12" then option_map (fun v => C12_ref.(write_to) v s) (C12_ref.(of_regval) v) else + if string_dec reg_name "C11" then option_map (fun v => C11_ref.(write_to) v s) (C11_ref.(of_regval) v) else + if string_dec reg_name "C10" then option_map (fun v => C10_ref.(write_to) v s) (C10_ref.(of_regval) v) else + if string_dec reg_name "C09" then option_map (fun v => C09_ref.(write_to) v s) (C09_ref.(of_regval) v) else + if string_dec reg_name "C08" then option_map (fun v => C08_ref.(write_to) v s) (C08_ref.(of_regval) v) else + if string_dec reg_name "C07" then option_map (fun v => C07_ref.(write_to) v s) (C07_ref.(of_regval) v) else + if string_dec reg_name "C06" then option_map (fun v => C06_ref.(write_to) v s) (C06_ref.(of_regval) v) else + if string_dec reg_name "C05" then option_map (fun v => C05_ref.(write_to) v s) (C05_ref.(of_regval) v) else + if string_dec reg_name "C04" then option_map (fun v => C04_ref.(write_to) v s) (C04_ref.(of_regval) v) else + if string_dec reg_name "C03" then option_map (fun v => C03_ref.(write_to) v s) (C03_ref.(of_regval) v) else + if string_dec reg_name "C02" then option_map (fun v => C02_ref.(write_to) v s) (C02_ref.(of_regval) v) else + if string_dec reg_name "C01" then option_map (fun v => C01_ref.(write_to) v s) (C01_ref.(of_regval) v) else + if string_dec reg_name "DDC" then option_map (fun v => DDC_ref.(write_to) v s) (DDC_ref.(of_regval) v) else + if string_dec reg_name "NextPCC" then option_map (fun v => NextPCC_ref.(write_to) v s) (NextPCC_ref.(of_regval) v) else + if string_dec reg_name "DelayedPCC" then option_map (fun v => DelayedPCC_ref.(write_to) v s) (DelayedPCC_ref.(of_regval) v) else + if string_dec reg_name "PCC" then option_map (fun v => PCC_ref.(write_to) v s) (PCC_ref.(of_regval) v) else + if string_dec reg_name "KCC" then option_map (fun v => KCC_ref.(write_to) v s) (KCC_ref.(of_regval) v) else + if string_dec reg_name "EPCC" then option_map (fun v => EPCC_ref.(write_to) v s) (EPCC_ref.(of_regval) v) else + if string_dec reg_name "UART_RVALID" then option_map (fun v => UART_RVALID_ref.(write_to) v s) (UART_RVALID_ref.(of_regval) v) else + if string_dec reg_name "UART_RDATA" then option_map (fun v => UART_RDATA_ref.(write_to) v s) (UART_RDATA_ref.(of_regval) v) else + if string_dec reg_name "UART_WRITTEN" then option_map (fun v => UART_WRITTEN_ref.(write_to) v s) (UART_WRITTEN_ref.(of_regval) v) else + if string_dec reg_name "UART_WDATA" then option_map (fun v => UART_WDATA_ref.(write_to) v s) (UART_WDATA_ref.(of_regval) v) else + if string_dec reg_name "GPR" then option_map (fun v => GPR_ref.(write_to) v s) (GPR_ref.(of_regval) v) else + if string_dec reg_name "LO" then option_map (fun v => LO_ref.(write_to) v s) (LO_ref.(of_regval) v) else + if string_dec reg_name "HI" then option_map (fun v => HI_ref.(write_to) v s) (HI_ref.(of_regval) v) else + if string_dec reg_name "DelayedPC" then option_map (fun v => DelayedPC_ref.(write_to) v s) (DelayedPC_ref.(of_regval) v) else + if string_dec reg_name "BranchPending" then option_map (fun v => BranchPending_ref.(write_to) v s) (BranchPending_ref.(of_regval) v) else + if string_dec reg_name "InBranchDelay" then option_map (fun v => InBranchDelay_ref.(write_to) v s) (InBranchDelay_ref.(of_regval) v) else + if string_dec reg_name "NextInBranchDelay" then option_map (fun v => NextInBranchDelay_ref.(write_to) v s) (NextInBranchDelay_ref.(of_regval) v) else + if string_dec reg_name "CP0Status" then option_map (fun v => CP0Status_ref.(write_to) v s) (CP0Status_ref.(of_regval) v) else + if string_dec reg_name "CP0ConfigK0" then option_map (fun v => CP0ConfigK0_ref.(write_to) v s) (CP0ConfigK0_ref.(of_regval) v) else + if string_dec reg_name "CP0UserLocal" then option_map (fun v => CP0UserLocal_ref.(write_to) v s) (CP0UserLocal_ref.(of_regval) v) else + if string_dec reg_name "CP0HWREna" then option_map (fun v => CP0HWREna_ref.(write_to) v s) (CP0HWREna_ref.(of_regval) v) else + if string_dec reg_name "CP0Count" then option_map (fun v => CP0Count_ref.(write_to) v s) (CP0Count_ref.(of_regval) v) else + if string_dec reg_name "CP0BadInstrP" then option_map (fun v => CP0BadInstrP_ref.(write_to) v s) (CP0BadInstrP_ref.(of_regval) v) else + if string_dec reg_name "CP0BadInstr" then option_map (fun v => CP0BadInstr_ref.(write_to) v s) (CP0BadInstr_ref.(of_regval) v) else + if string_dec reg_name "LastInstrBits" then option_map (fun v => LastInstrBits_ref.(write_to) v s) (LastInstrBits_ref.(of_regval) v) else + if string_dec reg_name "CurrentInstrBits" then option_map (fun v => CurrentInstrBits_ref.(write_to) v s) (CurrentInstrBits_ref.(of_regval) v) else + if string_dec reg_name "CP0BadVAddr" then option_map (fun v => CP0BadVAddr_ref.(write_to) v s) (CP0BadVAddr_ref.(of_regval) v) else + if string_dec reg_name "CP0LLAddr" then option_map (fun v => CP0LLAddr_ref.(write_to) v s) (CP0LLAddr_ref.(of_regval) v) else + if string_dec reg_name "CP0LLBit" then option_map (fun v => CP0LLBit_ref.(write_to) v s) (CP0LLBit_ref.(of_regval) v) else + if string_dec reg_name "CP0ErrorEPC" then option_map (fun v => CP0ErrorEPC_ref.(write_to) v s) (CP0ErrorEPC_ref.(of_regval) v) else + if string_dec reg_name "CP0EPC" then option_map (fun v => CP0EPC_ref.(write_to) v s) (CP0EPC_ref.(of_regval) v) else + if string_dec reg_name "CP0Cause" then option_map (fun v => CP0Cause_ref.(write_to) v s) (CP0Cause_ref.(of_regval) v) else + if string_dec reg_name "CP0Compare" then option_map (fun v => CP0Compare_ref.(write_to) v s) (CP0Compare_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry63" then option_map (fun v => TLBEntry63_ref.(write_to) v s) (TLBEntry63_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry62" then option_map (fun v => TLBEntry62_ref.(write_to) v s) (TLBEntry62_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry61" then option_map (fun v => TLBEntry61_ref.(write_to) v s) (TLBEntry61_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry60" then option_map (fun v => TLBEntry60_ref.(write_to) v s) (TLBEntry60_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry59" then option_map (fun v => TLBEntry59_ref.(write_to) v s) (TLBEntry59_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry58" then option_map (fun v => TLBEntry58_ref.(write_to) v s) (TLBEntry58_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry57" then option_map (fun v => TLBEntry57_ref.(write_to) v s) (TLBEntry57_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry56" then option_map (fun v => TLBEntry56_ref.(write_to) v s) (TLBEntry56_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry55" then option_map (fun v => TLBEntry55_ref.(write_to) v s) (TLBEntry55_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry54" then option_map (fun v => TLBEntry54_ref.(write_to) v s) (TLBEntry54_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry53" then option_map (fun v => TLBEntry53_ref.(write_to) v s) (TLBEntry53_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry52" then option_map (fun v => TLBEntry52_ref.(write_to) v s) (TLBEntry52_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry51" then option_map (fun v => TLBEntry51_ref.(write_to) v s) (TLBEntry51_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry50" then option_map (fun v => TLBEntry50_ref.(write_to) v s) (TLBEntry50_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry49" then option_map (fun v => TLBEntry49_ref.(write_to) v s) (TLBEntry49_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry48" then option_map (fun v => TLBEntry48_ref.(write_to) v s) (TLBEntry48_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry47" then option_map (fun v => TLBEntry47_ref.(write_to) v s) (TLBEntry47_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry46" then option_map (fun v => TLBEntry46_ref.(write_to) v s) (TLBEntry46_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry45" then option_map (fun v => TLBEntry45_ref.(write_to) v s) (TLBEntry45_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry44" then option_map (fun v => TLBEntry44_ref.(write_to) v s) (TLBEntry44_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry43" then option_map (fun v => TLBEntry43_ref.(write_to) v s) (TLBEntry43_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry42" then option_map (fun v => TLBEntry42_ref.(write_to) v s) (TLBEntry42_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry41" then option_map (fun v => TLBEntry41_ref.(write_to) v s) (TLBEntry41_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry40" then option_map (fun v => TLBEntry40_ref.(write_to) v s) (TLBEntry40_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry39" then option_map (fun v => TLBEntry39_ref.(write_to) v s) (TLBEntry39_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry38" then option_map (fun v => TLBEntry38_ref.(write_to) v s) (TLBEntry38_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry37" then option_map (fun v => TLBEntry37_ref.(write_to) v s) (TLBEntry37_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry36" then option_map (fun v => TLBEntry36_ref.(write_to) v s) (TLBEntry36_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry35" then option_map (fun v => TLBEntry35_ref.(write_to) v s) (TLBEntry35_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry34" then option_map (fun v => TLBEntry34_ref.(write_to) v s) (TLBEntry34_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry33" then option_map (fun v => TLBEntry33_ref.(write_to) v s) (TLBEntry33_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry32" then option_map (fun v => TLBEntry32_ref.(write_to) v s) (TLBEntry32_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry31" then option_map (fun v => TLBEntry31_ref.(write_to) v s) (TLBEntry31_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry30" then option_map (fun v => TLBEntry30_ref.(write_to) v s) (TLBEntry30_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry29" then option_map (fun v => TLBEntry29_ref.(write_to) v s) (TLBEntry29_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry28" then option_map (fun v => TLBEntry28_ref.(write_to) v s) (TLBEntry28_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry27" then option_map (fun v => TLBEntry27_ref.(write_to) v s) (TLBEntry27_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry26" then option_map (fun v => TLBEntry26_ref.(write_to) v s) (TLBEntry26_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry25" then option_map (fun v => TLBEntry25_ref.(write_to) v s) (TLBEntry25_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry24" then option_map (fun v => TLBEntry24_ref.(write_to) v s) (TLBEntry24_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry23" then option_map (fun v => TLBEntry23_ref.(write_to) v s) (TLBEntry23_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry22" then option_map (fun v => TLBEntry22_ref.(write_to) v s) (TLBEntry22_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry21" then option_map (fun v => TLBEntry21_ref.(write_to) v s) (TLBEntry21_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry20" then option_map (fun v => TLBEntry20_ref.(write_to) v s) (TLBEntry20_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry19" then option_map (fun v => TLBEntry19_ref.(write_to) v s) (TLBEntry19_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry18" then option_map (fun v => TLBEntry18_ref.(write_to) v s) (TLBEntry18_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry17" then option_map (fun v => TLBEntry17_ref.(write_to) v s) (TLBEntry17_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry16" then option_map (fun v => TLBEntry16_ref.(write_to) v s) (TLBEntry16_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry15" then option_map (fun v => TLBEntry15_ref.(write_to) v s) (TLBEntry15_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry14" then option_map (fun v => TLBEntry14_ref.(write_to) v s) (TLBEntry14_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry13" then option_map (fun v => TLBEntry13_ref.(write_to) v s) (TLBEntry13_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry12" then option_map (fun v => TLBEntry12_ref.(write_to) v s) (TLBEntry12_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry11" then option_map (fun v => TLBEntry11_ref.(write_to) v s) (TLBEntry11_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry10" then option_map (fun v => TLBEntry10_ref.(write_to) v s) (TLBEntry10_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry09" then option_map (fun v => TLBEntry09_ref.(write_to) v s) (TLBEntry09_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry08" then option_map (fun v => TLBEntry08_ref.(write_to) v s) (TLBEntry08_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry07" then option_map (fun v => TLBEntry07_ref.(write_to) v s) (TLBEntry07_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry06" then option_map (fun v => TLBEntry06_ref.(write_to) v s) (TLBEntry06_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry05" then option_map (fun v => TLBEntry05_ref.(write_to) v s) (TLBEntry05_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry04" then option_map (fun v => TLBEntry04_ref.(write_to) v s) (TLBEntry04_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry03" then option_map (fun v => TLBEntry03_ref.(write_to) v s) (TLBEntry03_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry02" then option_map (fun v => TLBEntry02_ref.(write_to) v s) (TLBEntry02_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry01" then option_map (fun v => TLBEntry01_ref.(write_to) v s) (TLBEntry01_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry00" then option_map (fun v => TLBEntry00_ref.(write_to) v s) (TLBEntry00_ref.(of_regval) v) else + if string_dec reg_name "TLBXContext" then option_map (fun v => TLBXContext_ref.(write_to) v s) (TLBXContext_ref.(of_regval) v) else + if string_dec reg_name "TLBEntryHi" then option_map (fun v => TLBEntryHi_ref.(write_to) v s) (TLBEntryHi_ref.(of_regval) v) else + if string_dec reg_name "TLBWired" then option_map (fun v => TLBWired_ref.(write_to) v s) (TLBWired_ref.(of_regval) v) else + if string_dec reg_name "TLBPageMask" then option_map (fun v => TLBPageMask_ref.(write_to) v s) (TLBPageMask_ref.(of_regval) v) else + if string_dec reg_name "TLBContext" then option_map (fun v => TLBContext_ref.(write_to) v s) (TLBContext_ref.(of_regval) v) else + if string_dec reg_name "TLBEntryLo1" then option_map (fun v => TLBEntryLo1_ref.(write_to) v s) (TLBEntryLo1_ref.(of_regval) v) else + if string_dec reg_name "TLBEntryLo0" then option_map (fun v => TLBEntryLo0_ref.(write_to) v s) (TLBEntryLo0_ref.(of_regval) v) else + if string_dec reg_name "TLBRandom" then option_map (fun v => TLBRandom_ref.(write_to) v s) (TLBRandom_ref.(of_regval) v) else + if string_dec reg_name "TLBIndex" then option_map (fun v => TLBIndex_ref.(write_to) v s) (TLBIndex_ref.(of_regval) v) else + if string_dec reg_name "TLBProbe" then option_map (fun v => TLBProbe_ref.(write_to) v s) (TLBProbe_ref.(of_regval) v) else + if string_dec reg_name "NextPC" then option_map (fun v => NextPC_ref.(write_to) v s) (NextPC_ref.(of_regval) v) else + if string_dec reg_name "PC" then option_map (fun v => PC_ref.(write_to) v s) (PC_ref.(of_regval) v) else + None. + +Definition register_accessors := (get_regval, set_regval). + + +Definition MR a r := monadR register_value a r exception. +Definition M a := monad register_value a exception. diff --git a/snapshots/coq/cheri-mips/mips.v b/snapshots/coq/cheri-mips/mips.v new file mode 100644 index 00000000..dd3c206d --- /dev/null +++ b/snapshots/coq/cheri-mips/mips.v @@ -0,0 +1,6746 @@ +(*Generated by Sail from mips.*) +Require Import Sail2_instr_kinds. +Require Import Sail2_values. +Require Import Sail2_string. +Require Import Sail2_real. +Require Import Sail2_operators_mwords. +Require Import Sail2_prompt_monad. +Require Import Sail2_prompt. +Require Import Sail2_state. +Require Import mips_types. +Require Import mips_extras. +Import ListNotations. +Open Scope string. +Open Scope bool. +Section Content. + +Definition trace : bool := false. +Hint Unfold trace : sail. +Definition eq_unit (g__17 : unit) (g__18 : unit) : bool := true. + +Definition neq_int (x : Z) (y : Z) : bool := negb (Z.eqb x y). + +Definition neq_bool (x : bool) (y : bool) : bool := negb (Bool.eqb x y). + +Definition undefined_option {a : Type} (typ_a : a) +: M (option a) := + + (undefined_unit tt) >>= fun u_0 : unit => + let u_1 : a := typ_a in + (internal_pick [Some (u_1);None]) + : M (option a). + +Definition is_none {a : Type} (opt : option a) +: bool := + + match opt with | Some (_) => false | None => true end. + +Definition is_some {a : Type} (opt : option a) +: bool := + + match opt with | Some (_) => true | None => false end. + +Definition sail_mask {v0 : Z} (len : Z) (v : mword v0) `{ArithFact (len >= 0 /\ v0 >= 0)} +: mword len := + + if sumbool_of_bool ((Z.leb len (length_mword v))) then vector_truncate v len + else zero_extend v len. + +Definition neq_vec {n : Z} (x : mword n) (y : mword n) : bool := negb (eq_vec x y). + + + +Definition cast_unit_vec (b : bitU) +: mword 1 := + + match b with | B0 => (vec_of_bits [B0] : mword 1) | _ => (vec_of_bits [B1] : mword 1) end. + +Definition __MIPS_write (addr : mword 64) (width : Z) (data : mword (8 * width)) +: M (unit) := + + (write_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr data) >> + returnm (tt + : unit). + +Definition __MIPS_read (addr : mword 64) (width : Z) `{ArithFact (width >= 0)} +: M (mword (8 * width)) := + + (read_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr) + : M (mword (8 * width)). + +Definition zopz0zQzQ {n0 : Z} (bs : mword n0) (n : Z) `{ArithFact (n >= 0)} +: mword (n0 * n) := + + replicate_bits bs n. + +Definition undefined_exception '(tt : unit) +: M (exception) := + + (undefined_string tt) >>= fun u_0 : string => + (undefined_unit tt) >>= fun u_1 : unit => + (internal_pick + [ISAException + (u_1);Error_not_implemented + (u_0);Error_misaligned_access + (u_1);Error_EBREAK + (u_1);Error_internal_error + (u_1)]) + : M (exception). + +Definition mips_sign_extend {n : Z} (m__tv : Z) (v : mword n) `{ArithFact (m__tv >= n)} +: mword m__tv := + + sign_extend v m__tv. + +Definition mips_zero_extend {n : Z} (m__tv : Z) (v : mword n) `{ArithFact (m__tv >= n)} +: mword m__tv := + + zero_extend v m__tv. + +Axiom sign_extend : forall {n : Z} {m : Z} (_ : mword n) `{ArithFact (m >= n)}, mword m. + +Axiom zero_extend : forall {n : Z} {m : Z} (_ : mword n) `{ArithFact (m >= n)}, mword m. + +Definition zeros_implicit (n__tv : Z) '(tt : unit) `{ArithFact (n__tv >= 0)} +: mword n__tv := + + zeros n__tv. +Arguments zeros_implicit _ _ {_}. + +Definition ones_n (n : Z) `{ArithFact (n >= 0)} +: mword n := + + autocast (replicate_bits (vec_of_bits [B1] : mword 1) n). + +Definition ones_implicit (n__tv : Z) '(tt : unit) `{ArithFact (n__tv >= 0)} +: mword n__tv := + + ones_n n__tv. +Arguments ones_implicit _ _ {_}. + +Definition zopz0zI_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= (0 + 1))} +: bool := + + Z.ltb (projT1 (sint x)) (projT1 (sint y)). + +Definition zopz0zKzJ_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= (0 + 1))} +: bool := + + Z.geb (projT1 (sint x)) (projT1 (sint y)). + +Definition zopz0zI_u {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 0)} +: bool := + + Z.ltb (projT1 (uint x)) (projT1 (uint y)). + +Definition zopz0zKzJ_u {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 0)} +: bool := + + Z.geb (projT1 (uint x)) (projT1 (uint y)). + +Definition bool_to_bits (x : bool) +: mword 1 := + + if (x) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1). + +Definition bool_to_bit (x : bool) : bitU := if (x) then B1 else B0. + +Definition bit_to_bool (b : bitU) : bool := match b with | B1 => true | _ => false end. + +Definition bits_to_bool (x : mword 1) : bool := bit_to_bool (access_vec_dec x 0). + +Definition to_bits (l : Z) (n : Z) `{ArithFact (l >= 0)} : mword l := get_slice_int l n 0. + +Definition mask {m : Z} (n__tv : Z) (bs : mword m) `{ArithFact (m >= n__tv /\ n__tv >= (0 + 1))} +: mword n__tv := + + autocast (subrange_vec_dec bs (Z.sub n__tv 1) 0). + +Definition undefined_CauseReg '(tt : unit) +: M (CauseReg) := + + (undefined_bitvector 32) >>= fun w__0 : mword 32 => + returnm (({| CauseReg_CauseReg_chunk_0 := w__0 |}) + : CauseReg). + +Definition Mk_CauseReg (v : mword 32) +: CauseReg := + + {| CauseReg_CauseReg_chunk_0 := (subrange_vec_dec v 31 0) |}. + +Definition _get_CauseReg_bits (v : CauseReg) +: mword 32 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 0. + +Definition _set_CauseReg_bits (r_ref : register_ref regstate register_value CauseReg) (v : mword 32) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_bits (v : CauseReg) (x : mword 32) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}. + +Definition _get_CauseReg_BD (v : CauseReg) +: mword 1 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 31. + +Definition _set_CauseReg_BD (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 31 31 (subrange_vec_dec v 0 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_BD (v : CauseReg) (x : mword 1) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 31 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_CauseReg_CE (v : CauseReg) +: mword 2 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 29 28. + +Definition _set_CauseReg_CE (r_ref : register_ref regstate register_value CauseReg) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 29 28 (subrange_vec_dec v 1 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_CE (v : CauseReg) (x : mword 2) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 29 28 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_CauseReg_IV (v : CauseReg) +: mword 1 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 23 23. + +Definition _set_CauseReg_IV (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 23 23 (subrange_vec_dec v 0 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_IV (v : CauseReg) (x : mword 1) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 23 23 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_CauseReg_WP (v : CauseReg) +: mword 1 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 22 22. + +Definition _set_CauseReg_WP (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_WP (v : CauseReg) (x : mword 1) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_CauseReg_IP (v : CauseReg) +: mword 8 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 15 8. + +Definition _set_CauseReg_IP (r_ref : register_ref regstate register_value CauseReg) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 15 8 (subrange_vec_dec v 7 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_IP (v : CauseReg) (x : mword 8) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 15 8 (subrange_vec_dec x 7 0)) ]}. + +Definition _get_CauseReg_ExcCode (v : CauseReg) +: mword 5 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 6 2. + +Definition _set_CauseReg_ExcCode +(r_ref : register_ref regstate register_value CauseReg) (v : mword 5) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 6 2 (subrange_vec_dec v 4 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_ExcCode (v : CauseReg) (x : mword 5) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 6 2 (subrange_vec_dec x 4 0)) ]}. + +Definition undefined_TLBEntryLoReg '(tt : unit) +: M (TLBEntryLoReg) := + + (undefined_bitvector 64) >>= fun w__0 : mword 64 => + returnm (({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := w__0 |}) + : TLBEntryLoReg). + +Definition Mk_TLBEntryLoReg (v : mword 64) +: TLBEntryLoReg := + + {| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_TLBEntryLoReg_bits (v : TLBEntryLoReg) +: mword 64 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 0. + +Definition _set_TLBEntryLoReg_bits +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 0 + (subrange_vec_dec v 63 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_bits (v : TLBEntryLoReg) (x : mword 64) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 0 + (subrange_vec_dec x 63 0)) ]}. + +Definition _get_TLBEntryLoReg_CapS (v : TLBEntryLoReg) +: mword 1 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 63. + +Definition _set_TLBEntryLoReg_CapS +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 63 + (subrange_vec_dec v 0 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_CapS (v : TLBEntryLoReg) (x : mword 1) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 63 + (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntryLoReg_CapL (v : TLBEntryLoReg) +: mword 1 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 62 62. + +Definition _set_TLBEntryLoReg_CapL +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 62 62 + (subrange_vec_dec v 0 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_CapL (v : TLBEntryLoReg) (x : mword 1) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 62 62 + (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntryLoReg_PFN (v : TLBEntryLoReg) +: mword 24 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 29 6. + +Definition _set_TLBEntryLoReg_PFN +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 24) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 29 6 + (subrange_vec_dec v 23 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_PFN (v : TLBEntryLoReg) (x : mword 24) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 29 6 + (subrange_vec_dec x 23 0)) ]}. + +Definition _get_TLBEntryLoReg_C (v : TLBEntryLoReg) +: mword 3 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 5 3. + +Definition _set_TLBEntryLoReg_C +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 3) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 5 3 + (subrange_vec_dec v 2 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_C (v : TLBEntryLoReg) (x : mword 3) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 5 3 (subrange_vec_dec x 2 0)) ]}. + +Definition _get_TLBEntryLoReg_D (v : TLBEntryLoReg) +: mword 1 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 2 2. + +Definition _set_TLBEntryLoReg_D +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 2 2 + (subrange_vec_dec v 0 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_D (v : TLBEntryLoReg) (x : mword 1) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntryLoReg_V (v : TLBEntryLoReg) +: mword 1 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 1 1. + +Definition _set_TLBEntryLoReg_V +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 1 1 + (subrange_vec_dec v 0 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_V (v : TLBEntryLoReg) (x : mword 1) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntryLoReg_G (v : TLBEntryLoReg) +: mword 1 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 0 0. + +Definition _set_TLBEntryLoReg_G +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 0 0 + (subrange_vec_dec v 0 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_G (v : TLBEntryLoReg) (x : mword 1) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition undefined_TLBEntryHiReg '(tt : unit) +: M (TLBEntryHiReg) := + + (undefined_bitvector 64) >>= fun w__0 : mword 64 => + returnm (({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := w__0 |}) + : TLBEntryHiReg). + +Definition Mk_TLBEntryHiReg (v : mword 64) +: TLBEntryHiReg := + + {| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_TLBEntryHiReg_bits (v : TLBEntryHiReg) +: mword 64 := + + subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 0. + +Definition _set_TLBEntryHiReg_bits +(r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 0 + (subrange_vec_dec v 63 0)) ]} + : TLBEntryHiReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryHiReg_bits (v : TLBEntryHiReg) (x : mword 64) +: TLBEntryHiReg := + + {[ v with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 0 + (subrange_vec_dec x 63 0)) ]}. + +Definition _get_TLBEntryHiReg_R (v : TLBEntryHiReg) +: mword 2 := + + subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 62. + +Definition _set_TLBEntryHiReg_R +(r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 62 + (subrange_vec_dec v 1 0)) ]} + : TLBEntryHiReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryHiReg_R (v : TLBEntryHiReg) (x : mword 2) +: TLBEntryHiReg := + + {[ v with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 62 + (subrange_vec_dec x 1 0)) ]}. + +Definition _get_TLBEntryHiReg_VPN2 (v : TLBEntryHiReg) +: mword 27 := + + subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 39 13. + +Definition _set_TLBEntryHiReg_VPN2 +(r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 27) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 39 13 + (subrange_vec_dec v 26 0)) ]} + : TLBEntryHiReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryHiReg_VPN2 (v : TLBEntryHiReg) (x : mword 27) +: TLBEntryHiReg := + + {[ v with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 39 13 + (subrange_vec_dec x 26 0)) ]}. + +Definition _get_TLBEntryHiReg_ASID (v : TLBEntryHiReg) +: mword 8 := + + subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 7 0. + +Definition _set_TLBEntryHiReg_ASID +(r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 7 0 + (subrange_vec_dec v 7 0)) ]} + : TLBEntryHiReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryHiReg_ASID (v : TLBEntryHiReg) (x : mword 8) +: TLBEntryHiReg := + + {[ v with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}. + +Definition undefined_ContextReg '(tt : unit) +: M (ContextReg) := + + (undefined_bitvector 64) >>= fun w__0 : mword 64 => + returnm (({| ContextReg_ContextReg_chunk_0 := w__0 |}) + : ContextReg). + +Definition Mk_ContextReg (v : mword 64) +: ContextReg := + + {| ContextReg_ContextReg_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_ContextReg_bits (v : ContextReg) +: mword 64 := + + subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 0. + +Definition _set_ContextReg_bits +(r_ref : register_ref regstate register_value ContextReg) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + ContextReg_ContextReg_chunk_0 := + (update_subrange_vec_dec r.(ContextReg_ContextReg_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : ContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_ContextReg_bits (v : ContextReg) (x : mword 64) +: ContextReg := + + {[ v with + ContextReg_ContextReg_chunk_0 := + (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_ContextReg_PTEBase (v : ContextReg) +: mword 41 := + + subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 23. + +Definition _set_ContextReg_PTEBase +(r_ref : register_ref regstate register_value ContextReg) (v : mword 41) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + ContextReg_ContextReg_chunk_0 := + (update_subrange_vec_dec r.(ContextReg_ContextReg_chunk_0) 63 23 (subrange_vec_dec v 40 0)) ]} + : ContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_ContextReg_PTEBase (v : ContextReg) (x : mword 41) +: ContextReg := + + {[ v with + ContextReg_ContextReg_chunk_0 := + (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 23 (subrange_vec_dec x 40 0)) ]}. + +Definition _get_ContextReg_BadVPN2 (v : ContextReg) +: mword 19 := + + subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 22 4. + +Definition _set_ContextReg_BadVPN2 +(r_ref : register_ref regstate register_value ContextReg) (v : mword 19) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + ContextReg_ContextReg_chunk_0 := + (update_subrange_vec_dec r.(ContextReg_ContextReg_chunk_0) 22 4 (subrange_vec_dec v 18 0)) ]} + : ContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_ContextReg_BadVPN2 (v : ContextReg) (x : mword 19) +: ContextReg := + + {[ v with + ContextReg_ContextReg_chunk_0 := + (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 22 4 (subrange_vec_dec x 18 0)) ]}. + +Definition undefined_XContextReg '(tt : unit) +: M (XContextReg) := + + (undefined_bitvector 64) >>= fun w__0 : mword 64 => + returnm (({| XContextReg_XContextReg_chunk_0 := w__0 |}) + : XContextReg). + +Definition Mk_XContextReg (v : mword 64) +: XContextReg := + + {| XContextReg_XContextReg_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_XContextReg_bits (v : XContextReg) +: mword 64 := + + subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 0. + +Definition _set_XContextReg_bits +(r_ref : register_ref regstate register_value XContextReg) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : XContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_XContextReg_bits (v : XContextReg) (x : mword 64) +: XContextReg := + + {[ v with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_XContextReg_XPTEBase (v : XContextReg) +: mword 31 := + + subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 33. + +Definition _set_XContextReg_XPTEBase +(r_ref : register_ref regstate register_value XContextReg) (v : mword 31) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 63 33 + (subrange_vec_dec v 30 0)) ]} + : XContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_XContextReg_XPTEBase (v : XContextReg) (x : mword 31) +: XContextReg := + + {[ v with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 33 (subrange_vec_dec x 30 0)) ]}. + +Definition _get_XContextReg_XR (v : XContextReg) +: mword 2 := + + subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 32 31. + +Definition _set_XContextReg_XR +(r_ref : register_ref regstate register_value XContextReg) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 32 31 (subrange_vec_dec v 1 0)) ]} + : XContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_XContextReg_XR (v : XContextReg) (x : mword 2) +: XContextReg := + + {[ v with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 32 31 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_XContextReg_XBadVPN2 (v : XContextReg) +: mword 27 := + + subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 30 4. + +Definition _set_XContextReg_XBadVPN2 +(r_ref : register_ref regstate register_value XContextReg) (v : mword 27) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 30 4 (subrange_vec_dec v 26 0)) ]} + : XContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_XContextReg_XBadVPN2 (v : XContextReg) (x : mword 27) +: XContextReg := + + {[ v with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 30 4 (subrange_vec_dec x 26 0)) ]}. + +Definition TLBNumEntries := 64. +Hint Unfold TLBNumEntries : sail. +Definition TLBIndexMax : TLBIndexT := (vec_of_bits [B1;B1;B1;B1;B1;B1] : mword 6). +Hint Unfold TLBIndexMax : sail. +Definition MAX (n : Z) `{ArithFact (n >= 0)} +: {_retval : Z & ArithFact (_retval = (2 ^ n - 1))} := + + build_ex(Z.sub (projT1 (pow2 n)) 1). + +Definition MAX_U64 := projT1 (MAX 64). +Hint Unfold MAX_U64 : sail. +Definition MAX_VA := projT1 (MAX 40). +Hint Unfold MAX_VA : sail. +Definition MAX_PA := projT1 (MAX 36). +Hint Unfold MAX_PA : sail. +Definition undefined_TLBEntry '(tt : unit) +: M (TLBEntry) := + + (undefined_bitvector 53) >>= fun w__0 : mword 53 => + (undefined_bitvector 64) >>= fun w__1 : mword 64 => + returnm (({| TLBEntry_TLBEntry_chunk_1 := w__0; + TLBEntry_TLBEntry_chunk_0 := w__1 |}) + : TLBEntry). + +Definition Mk_TLBEntry (v : mword 117) +: TLBEntry := + + {| TLBEntry_TLBEntry_chunk_1 := (subrange_vec_dec v 116 64); + TLBEntry_TLBEntry_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_TLBEntry_bits (v : TLBEntry) +: mword 117 := + + concat_vec (subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 0) + (subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 0). + +Definition _set_TLBEntry_bits +(r_ref : register_ref regstate register_value TLBEntry) (v : mword 117) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 52 0 (subrange_vec_dec v 116 64)) ]} + : TLBEntry in + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_bits (v : TLBEntry) (x : mword 117) +: TLBEntry := + + let v := + {[ v with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 0 (subrange_vec_dec x 116 64)) ]} in + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_TLBEntry_pagemask (v : TLBEntry) +: mword 16 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 37. + +Definition _set_TLBEntry_pagemask +(r_ref : register_ref regstate register_value TLBEntry) (v : mword 16) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 52 37 (subrange_vec_dec v 15 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_pagemask (v : TLBEntry) (x : mword 16) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 37 (subrange_vec_dec x 15 0)) ]}. + +Definition _get_TLBEntry_r (v : TLBEntry) +: mword 2 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 36 35. + +Definition _set_TLBEntry_r (r_ref : register_ref regstate register_value TLBEntry) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 36 35 (subrange_vec_dec v 1 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_r (v : TLBEntry) (x : mword 2) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 36 35 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_TLBEntry_vpn2 (v : TLBEntry) +: mword 27 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 34 8. + +Definition _set_TLBEntry_vpn2 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 27) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 34 8 (subrange_vec_dec v 26 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_vpn2 (v : TLBEntry) (x : mword 27) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 34 8 (subrange_vec_dec x 26 0)) ]}. + +Definition _get_TLBEntry_asid (v : TLBEntry) +: mword 8 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 7 0. + +Definition _set_TLBEntry_asid (r_ref : register_ref regstate register_value TLBEntry) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 7 0 (subrange_vec_dec v 7 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_asid (v : TLBEntry) (x : mword 8) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 7 0 (subrange_vec_dec x 7 0)) ]}. + +Definition _get_TLBEntry_g (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 63. + +Definition _set_TLBEntry_g (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 63 63 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_g (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 63 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_valid (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 62 62. + +Definition _set_TLBEntry_valid (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 62 62 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_valid (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 62 62 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_caps1 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 61 61. + +Definition _set_TLBEntry_caps1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 61 61 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_caps1 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 61 61 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_capl1 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 60 60. + +Definition _set_TLBEntry_capl1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 60 60 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_capl1 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 60 60 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_pfn1 (v : TLBEntry) +: mword 24 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 59 36. + +Definition _set_TLBEntry_pfn1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 24) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 59 36 (subrange_vec_dec v 23 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_pfn1 (v : TLBEntry) (x : mword 24) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 59 36 (subrange_vec_dec x 23 0)) ]}. + +Definition _get_TLBEntry_c1 (v : TLBEntry) +: mword 3 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 35 33. + +Definition _set_TLBEntry_c1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 3) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 35 33 (subrange_vec_dec v 2 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_c1 (v : TLBEntry) (x : mword 3) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 35 33 (subrange_vec_dec x 2 0)) ]}. + +Definition _get_TLBEntry_d1 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 32 32. + +Definition _set_TLBEntry_d1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 32 32 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_d1 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 32 32 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_v1 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 31 31. + +Definition _set_TLBEntry_v1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 31 31 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_v1 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 31 31 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_caps0 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 30 30. + +Definition _set_TLBEntry_caps0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 30 30 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_caps0 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 30 30 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_capl0 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 29 29. + +Definition _set_TLBEntry_capl0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 29 29 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_capl0 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 29 29 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_pfn0 (v : TLBEntry) +: mword 24 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 28 5. + +Definition _set_TLBEntry_pfn0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 24) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 28 5 (subrange_vec_dec v 23 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_pfn0 (v : TLBEntry) (x : mword 24) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 28 5 (subrange_vec_dec x 23 0)) ]}. + +Definition _get_TLBEntry_c0 (v : TLBEntry) +: mword 3 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 4 2. + +Definition _set_TLBEntry_c0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 3) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 4 2 (subrange_vec_dec v 2 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_c0 (v : TLBEntry) (x : mword 3) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 4 2 (subrange_vec_dec x 2 0)) ]}. + +Definition _get_TLBEntry_d0 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 1 1. + +Definition _set_TLBEntry_d0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_d0 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_v0 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 0 0. + +Definition _set_TLBEntry_v0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_v0 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition TLBEntries : vec (register_ref regstate register_value TLBEntry) 64 := +vec_of_list_len [TLBEntry63_ref;TLBEntry62_ref;TLBEntry61_ref;TLBEntry60_ref;TLBEntry59_ref;TLBEntry58_ref;TLBEntry57_ref;TLBEntry56_ref;TLBEntry55_ref;TLBEntry54_ref;TLBEntry53_ref;TLBEntry52_ref;TLBEntry51_ref;TLBEntry50_ref;TLBEntry49_ref;TLBEntry48_ref;TLBEntry47_ref;TLBEntry46_ref;TLBEntry45_ref;TLBEntry44_ref;TLBEntry43_ref; + TLBEntry42_ref;TLBEntry41_ref;TLBEntry40_ref;TLBEntry39_ref;TLBEntry38_ref;TLBEntry37_ref;TLBEntry36_ref;TLBEntry35_ref;TLBEntry34_ref;TLBEntry33_ref;TLBEntry32_ref;TLBEntry31_ref;TLBEntry30_ref;TLBEntry29_ref;TLBEntry28_ref;TLBEntry27_ref;TLBEntry26_ref;TLBEntry25_ref;TLBEntry24_ref;TLBEntry23_ref;TLBEntry22_ref; + TLBEntry21_ref;TLBEntry20_ref;TLBEntry19_ref;TLBEntry18_ref;TLBEntry17_ref;TLBEntry16_ref;TLBEntry15_ref;TLBEntry14_ref;TLBEntry13_ref;TLBEntry12_ref;TLBEntry11_ref;TLBEntry10_ref;TLBEntry09_ref;TLBEntry08_ref;TLBEntry07_ref;TLBEntry06_ref;TLBEntry05_ref;TLBEntry04_ref;TLBEntry03_ref;TLBEntry02_ref;TLBEntry01_ref; + TLBEntry00_ref]. +Hint Unfold TLBEntries : sail. +Definition undefined_StatusReg '(tt : unit) +: M (StatusReg) := + + (undefined_bitvector 32) >>= fun w__0 : mword 32 => + returnm (({| StatusReg_StatusReg_chunk_0 := w__0 |}) + : StatusReg). + +Definition Mk_StatusReg (v : mword 32) +: StatusReg := + + {| StatusReg_StatusReg_chunk_0 := (subrange_vec_dec v 31 0) |}. + +Definition _get_StatusReg_bits (v : StatusReg) +: mword 32 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 0. + +Definition _set_StatusReg_bits +(r_ref : register_ref regstate register_value StatusReg) (v : mword 32) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_bits (v : StatusReg) (x : mword 32) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}. + +Definition _get_StatusReg_CU (v : StatusReg) +: mword 4 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 28. + +Definition _set_StatusReg_CU (r_ref : register_ref regstate register_value StatusReg) (v : mword 4) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 31 28 (subrange_vec_dec v 3 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_CU (v : StatusReg) (x : mword 4) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 28 (subrange_vec_dec x 3 0)) ]}. + +Definition _get_StatusReg_BEV (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 22 22. + +Definition _set_StatusReg_BEV (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_BEV (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_StatusReg_IM (v : StatusReg) +: mword 8 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 15 8. + +Definition _set_StatusReg_IM (r_ref : register_ref regstate register_value StatusReg) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 15 8 (subrange_vec_dec v 7 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_IM (v : StatusReg) (x : mword 8) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 15 8 (subrange_vec_dec x 7 0)) ]}. + +Definition _get_StatusReg_KX (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 7 7. + +Definition _set_StatusReg_KX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_KX (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_StatusReg_SX (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 6 6. + +Definition _set_StatusReg_SX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_SX (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_StatusReg_UX (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 5 5. + +Definition _set_StatusReg_UX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_UX (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_StatusReg_KSU (v : StatusReg) +: mword 2 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 4 3. + +Definition _set_StatusReg_KSU (r_ref : register_ref regstate register_value StatusReg) (v : mword 2) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 4 3 (subrange_vec_dec v 1 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_KSU (v : StatusReg) (x : mword 2) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 4 3 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_StatusReg_ERL (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 2 2. + +Definition _set_StatusReg_ERL (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_ERL (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_StatusReg_EXL (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 1 1. + +Definition _set_StatusReg_EXL (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_EXL (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_StatusReg_IE (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 0 0. + +Definition _set_StatusReg_IE (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_IE (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition execute_branch_mips (pc : mword 64) +: M (unit) := + + write_reg DelayedPC_ref pc >> + write_reg BranchPending_ref (vec_of_bits [B1] : mword 1) >> + write_reg NextInBranchDelay_ref (vec_of_bits [B1] : mword 1) + : M (unit). + +Definition NotWordVal (word : mword 64) +: bool := + + neq_vec (zopz0zQzQ (cast_unit_vec (access_vec_dec word 31)) 32) (subrange_vec_dec word 63 32). + +Definition rGPR (idx : mword 5) +: M (mword 64) := + + let 'i := projT1 (uint idx) in + (if sumbool_of_bool ((Z.eqb i 0)) then + returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + : mword 64) + else + read_reg GPR_ref >>= fun w__0 : vec (bits 64) 32 => + returnm ((vec_access_dec w__0 i) + : mword 64)) + : M (mword 64). + +Definition wGPR (idx : mword 5) (v : mword 64) +: M (unit) := + + let 'i := projT1 (uint idx) in + (if ((neq_int i 0)) then + let '_ := + (if (trace) then + let '_ := (prerr (string_of_int i)) : unit in + prerr_bits " <- " v + else tt) + : unit in + read_reg GPR_ref >>= fun w__0 : vec (bits 64) 32 => + write_reg GPR_ref (vec_update_dec w__0 i v) + : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition MEMr (addr : mword 64) (size : Z) `{ArithFact (size >= 0)} +: M (mword (8 * size)) := + + (__MIPS_read addr size) + : M (mword (8 * size)). + +Definition MEMr_reserve (addr : mword 64) (size : Z) `{ArithFact (size >= 0)} +: M (mword (8 * size)) := + + (__MIPS_read addr size) + : M (mword (8 * size)). + +Definition MEM_sync '(tt : unit) : M (unit) := (skip tt) : M (unit). + +Definition MEMea (addr : mword 64) (size : Z) : M (unit) := (skip tt) : M (unit). + +Definition MEMea_conditional (addr : mword 64) (size : Z) : M (unit) := (skip tt) : M (unit). + +Definition MEMval (addr : mword 64) (size : Z) (data : mword (8 * size)) +: M (unit) := + + (__MIPS_write addr size data) + : M (unit). + +Definition MEMval_conditional (addr : mword 64) (size : Z) (data : mword (8 * size)) +: M (bool) := + + (__MIPS_write addr size data) >> returnm (true : bool). + +Definition Exception_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 18)} +: Exception := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Interrupt + else if sumbool_of_bool ((Z.eqb p0_ 1)) then TLBMod + else if sumbool_of_bool ((Z.eqb p0_ 2)) then TLBL + else if sumbool_of_bool ((Z.eqb p0_ 3)) then TLBS + else if sumbool_of_bool ((Z.eqb p0_ 4)) then AdEL + else if sumbool_of_bool ((Z.eqb p0_ 5)) then AdES + else if sumbool_of_bool ((Z.eqb p0_ 6)) then Sys + else if sumbool_of_bool ((Z.eqb p0_ 7)) then Bp + else if sumbool_of_bool ((Z.eqb p0_ 8)) then ResI + else if sumbool_of_bool ((Z.eqb p0_ 9)) then CpU + else if sumbool_of_bool ((Z.eqb p0_ 10)) then Ov + else if sumbool_of_bool ((Z.eqb p0_ 11)) then Tr + else if sumbool_of_bool ((Z.eqb p0_ 12)) then C2E + else if sumbool_of_bool ((Z.eqb p0_ 13)) then C2Trap + else if sumbool_of_bool ((Z.eqb p0_ 14)) then XTLBRefillL + else if sumbool_of_bool ((Z.eqb p0_ 15)) then XTLBRefillS + else if sumbool_of_bool ((Z.eqb p0_ 16)) then XTLBInvL + else if sumbool_of_bool ((Z.eqb p0_ 17)) then XTLBInvS + else MCheck. + +Definition num_of_Exception (arg_ : Exception) +: {e : Z & ArithFact (0 <= e /\ e <= 18)} := + + build_ex(match arg_ with + | Interrupt => 0 + | TLBMod => 1 + | TLBL => 2 + | TLBS => 3 + | AdEL => 4 + | AdES => 5 + | Sys => 6 + | Bp => 7 + | ResI => 8 + | CpU => 9 + | Ov => 10 + | Tr => 11 + | C2E => 12 + | C2Trap => 13 + | XTLBRefillL => 14 + | XTLBRefillS => 15 + | XTLBInvL => 16 + | XTLBInvS => 17 + | MCheck => 18 + end). + +Definition undefined_Exception '(tt : unit) +: M (Exception) := + + (internal_pick + [Interrupt;TLBMod;TLBL;TLBS;AdEL;AdES;Sys;Bp;ResI;CpU;Ov;Tr;C2E;C2Trap;XTLBRefillL;XTLBRefillS;XTLBInvL;XTLBInvS;MCheck]) + : M (Exception). + +Definition ExceptionCode (ex : Exception) +: mword 5 := + + let x : bits 8 := + match ex with + | Interrupt => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8) + | TLBMod => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : mword 8) + | TLBL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : mword 8) + | TLBS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : mword 8) + | AdEL => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : mword 8) + | AdES => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : mword 8) + | Sys => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : mword 8) + | Bp => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : mword 8) + | ResI => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0] : mword 8) + | CpU => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1] : mword 8) + | Ov => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B0] : mword 8) + | Tr => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B1] : mword 8) + | C2E => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : mword 8) + | C2Trap => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : mword 8) + | XTLBRefillL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : mword 8) + | XTLBRefillS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : mword 8) + | XTLBInvL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : mword 8) + | XTLBInvS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : mword 8) + | MCheck => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0] : mword 8) + end in + subrange_vec_dec x 4 0. + +Definition string_of_exception (ex : Exception) +: string := + + match ex with + | Interrupt => "Interrupt" + | TLBMod => "TLBMod" + | TLBL => "TLBL" + | TLBS => "TLBS" + | AdEL => "AdEL" + | AdES => "AdES" + | Sys => "Sys" + | Bp => "Bp " + | ResI => "ResI" + | CpU => "CpU" + | Ov => "Ov" + | Tr => "Tr" + | C2E => "C2E" + | C2Trap => "C2Trap" + | XTLBRefillL => "XTLBRefillL" + | XTLBRefillS => "XTLBRefillS" + | XTLBInvL => "XTLBInvL" + | XTLBInvS => "XTLBInvS" + | MCheck => "MCheck" + end. + +Definition SignalExceptionMIPS {o : Type} (ex : Exception) (kccBase : mword 64) +: M (o) := + + let '_ := + (if (trace) then + let '_ := (prerr " EXCEPTION ") : unit in + prerr_endline (string_of_exception ex) + else tt) + : unit in + read_reg CP0Status_ref >>= fun w__0 : StatusReg => + (if ((negb ((bits_to_bool (_get_StatusReg_EXL w__0)) : bool))) then + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__1 : bits 1 => + (if (((bit_to_bool (access_vec_dec w__1 0)) : bool)) then + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + write_reg CP0EPC_ref (sub_vec_int w__2 4) >> + (_set_CauseReg_BD CP0Cause_ref (vec_of_bits [B1] : mword 1)) + : M (unit) + else + ((read_reg PC_ref) : M (mword 64)) >>= fun w__3 : bits 64 => + write_reg CP0EPC_ref w__3 >> + (_set_CauseReg_BD CP0Cause_ref (vec_of_bits [B0] : mword 1)) + : M (unit)) + : M (unit) + else returnm (tt : unit)) >> + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__4 : bits 1 => + (if (((bit_to_bool (access_vec_dec w__4 0)) : bool)) then + ((read_reg LastInstrBits_ref) : M (mword 32)) >>= fun w__5 : bits 32 => + write_reg CP0BadInstrP_ref w__5 + : M (unit) + else returnm (tt : unit)) >> + ((read_reg CurrentInstrBits_ref) : M (mword 32)) >>= fun w__6 : bits 32 => + write_reg CP0BadInstr_ref w__6 >> + read_reg CP0Status_ref >>= fun w__7 : StatusReg => + let vectorOffset := + if (((bits_to_bool (_get_StatusReg_EXL w__7)) : bool)) then + (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((orb (generic_eq ex XTLBRefillL) (generic_eq ex XTLBRefillS))) then + (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq ex C2Trap)) then + (vec_of_bits [B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) in + read_reg CP0Status_ref >>= fun w__8 : StatusReg => + let vectorBase : bits 64 := + if (((bits_to_bool (_get_StatusReg_BEV w__8)) : bool)) then + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + else + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) in + write_reg NextPC_ref (sub_vec (add_vec vectorBase (mips_sign_extend 64 vectorOffset)) kccBase) >> + (_set_CauseReg_ExcCode CP0Cause_ref (ExceptionCode ex)) >> + (_set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1] : mword 1)) >> + (throw (ISAException + (tt))) + : M (o). + +Definition SignalException {o : Type} (ex : Exception) +: M (o) := + + (SignalExceptionMIPS ex + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64)) + : M (o). + +Definition SignalExceptionBadAddr {o : Type} (ex : Exception) (badAddr : mword 64) +: M (o) := + + write_reg CP0BadVAddr_ref badAddr >> (SignalException ex) : M (o). + +Definition SignalExceptionTLB {o : Type} (ex : Exception) (badAddr : mword 64) +: M (o) := + + write_reg CP0BadVAddr_ref badAddr >> + (_set_ContextReg_BadVPN2 TLBContext_ref (subrange_vec_dec badAddr 31 13)) >> + (_set_XContextReg_XBadVPN2 TLBXContext_ref (subrange_vec_dec badAddr 39 13)) >> + (_set_XContextReg_XR TLBXContext_ref (subrange_vec_dec badAddr 63 62)) >> + (_set_TLBEntryHiReg_R TLBEntryHi_ref (subrange_vec_dec badAddr 63 62)) >> + (_set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (subrange_vec_dec badAddr 39 13)) >> + (SignalException ex) + : M (o). + +Definition MemAccessType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: MemAccessType := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Instruction + else if sumbool_of_bool ((Z.eqb p0_ 1)) then LoadData + else StoreData. + +Definition num_of_MemAccessType (arg_ : MemAccessType) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with | Instruction => 0 | LoadData => 1 | StoreData => 2 end). + +Definition undefined_MemAccessType '(tt : unit) +: M (MemAccessType) := + + (internal_pick [Instruction;LoadData;StoreData]) + : M (MemAccessType). + +Definition AccessLevel_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: AccessLevel := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then User + else if sumbool_of_bool ((Z.eqb p0_ 1)) then Supervisor + else Kernel. + +Definition num_of_AccessLevel (arg_ : AccessLevel) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with | User => 0 | Supervisor => 1 | Kernel => 2 end). + +Definition undefined_AccessLevel '(tt : unit) +: M (AccessLevel) := + + (internal_pick [User;Supervisor;Kernel]) + : M (AccessLevel). + +Definition int_of_AccessLevel (level : AccessLevel) +: {n : Z & ArithFact (In n [0; 1; 2])} := + + build_ex(match level with | User => 0 | Supervisor => 1 | Kernel => 2 end). + +Definition grantsAccess (currentLevel : AccessLevel) (requiredLevel : AccessLevel) +: bool := + + Z.geb (projT1 (int_of_AccessLevel currentLevel)) (projT1 (int_of_AccessLevel requiredLevel)). + +Definition getAccessLevel '(tt : unit) +: M (AccessLevel) := + + (or_boolM + (read_reg CP0Status_ref >>= fun w__0 : StatusReg => + returnm ((bits_to_bool (_get_StatusReg_EXL w__0)) + : bool)) + (read_reg CP0Status_ref >>= fun w__1 : StatusReg => + returnm ((bits_to_bool (_get_StatusReg_ERL w__1)) + : bool))) >>= fun w__2 : bool => + (if (w__2) then returnm (Kernel : AccessLevel) + else + read_reg CP0Status_ref >>= fun w__3 : StatusReg => + let p__16 := _get_StatusReg_KSU w__3 in + let b__0 := p__16 in + returnm ((if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then Kernel + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then Supervisor + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then User + else User) + : AccessLevel)) + : M (AccessLevel). + +Definition checkCP0Access '(tt : unit) +: M (unit) := + + (getAccessLevel tt) >>= fun accessLevel => + (and_boolM (returnm ((generic_neq accessLevel Kernel) : bool)) + (read_reg CP0Status_ref >>= fun w__0 : StatusReg => + returnm ((negb ((bit_to_bool (access_vec_dec (_get_StatusReg_CU w__0) 0)) : bool)) + : bool))) >>= fun w__1 : bool => + (if (w__1) then + (_set_CauseReg_CE CP0Cause_ref (vec_of_bits [B0;B0] : mword 2)) >> + (SignalException CpU) + : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition incrementCP0Count '(tt : unit) +: M (unit) := + + ((read_reg TLBRandom_ref) : M (mword 6)) >>= fun w__0 : TLBIndexT => + ((read_reg TLBWired_ref) : M (mword 6)) >>= fun w__1 : TLBIndexT => + (if ((eq_vec w__0 w__1)) then returnm (TLBIndexMax : TLBIndexT) + else + ((read_reg TLBRandom_ref) : M (mword 6)) >>= fun w__2 : TLBIndexT => + returnm ((sub_vec_int w__2 1) + : mword 6)) >>= fun w__3 : mword 6 => + write_reg TLBRandom_ref w__3 >> + ((read_reg CP0Count_ref) : M (mword 32)) >>= fun w__4 : bits 32 => + write_reg CP0Count_ref (add_vec_int w__4 1) >> + ((read_reg CP0Count_ref) : M (mword 32)) >>= fun w__5 : bits 32 => + ((read_reg CP0Compare_ref) : M (mword 32)) >>= fun w__6 : bits 32 => + (if ((eq_vec w__5 w__6)) then + read_reg CP0Cause_ref >>= fun w__7 : CauseReg => + (_set_CauseReg_IP CP0Cause_ref + (or_vec (_get_CauseReg_IP w__7) (vec_of_bits [B1;B0;B0;B0;B0;B0;B0;B0] : mword 8))) + : M (unit) + else returnm (tt : unit)) >> + read_reg CP0Status_ref >>= fun w__8 : StatusReg => + let ims := _get_StatusReg_IM w__8 in + read_reg CP0Cause_ref >>= fun w__9 : CauseReg => + let ips := _get_CauseReg_IP w__9 in + read_reg CP0Status_ref >>= fun w__10 : StatusReg => + let ie := _get_StatusReg_IE w__10 in + read_reg CP0Status_ref >>= fun w__11 : StatusReg => + let exl := _get_StatusReg_EXL w__11 in + read_reg CP0Status_ref >>= fun w__12 : StatusReg => + let erl := _get_StatusReg_ERL w__12 in + (if ((andb (negb ((bits_to_bool exl) : bool)) + (andb (negb ((bits_to_bool erl) : bool)) + (andb ((bits_to_bool ie) : bool) + (neq_vec (and_vec ips ims) (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8)))))) + then + (SignalException Interrupt) + : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition decode_failure_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} +: decode_failure := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then no_matching_pattern + else if sumbool_of_bool ((Z.eqb p0_ 1)) then unsupported_instruction + else if sumbool_of_bool ((Z.eqb p0_ 2)) then illegal_instruction + else internal_error. + +Definition num_of_decode_failure (arg_ : decode_failure) +: {e : Z & ArithFact (0 <= e /\ e <= 3)} := + + build_ex(match arg_ with + | no_matching_pattern => 0 + | unsupported_instruction => 1 + | illegal_instruction => 2 + | internal_error => 3 + end). + +Definition undefined_decode_failure '(tt : unit) +: M (decode_failure) := + + (internal_pick [no_matching_pattern;unsupported_instruction;illegal_instruction;internal_error]) + : M (decode_failure). + +Definition Comparison_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 7)} +: Comparison := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then EQ' + else if sumbool_of_bool ((Z.eqb p0_ 1)) then NE + else if sumbool_of_bool ((Z.eqb p0_ 2)) then GE + else if sumbool_of_bool ((Z.eqb p0_ 3)) then GEU + else if sumbool_of_bool ((Z.eqb p0_ 4)) then GT' + else if sumbool_of_bool ((Z.eqb p0_ 5)) then LE + else if sumbool_of_bool ((Z.eqb p0_ 6)) then LT' + else LTU. + +Definition num_of_Comparison (arg_ : Comparison) +: {e : Z & ArithFact (0 <= e /\ e <= 7)} := + + build_ex(match arg_ with + | EQ' => 0 + | NE => 1 + | GE => 2 + | GEU => 3 + | GT' => 4 + | LE => 5 + | LT' => 6 + | LTU => 7 + end). + +Definition undefined_Comparison '(tt : unit) +: M (Comparison) := + + (internal_pick [EQ';NE;GE;GEU;GT';LE;LT';LTU]) + : M (Comparison). + +Definition compare (cmp : Comparison) (valA : mword 64) (valB : mword 64) +: bool := + + match cmp with + | EQ' => eq_vec valA valB + | NE => neq_vec valA valB + | GE => zopz0zKzJ_s valA valB + | GEU => zopz0zKzJ_u valA valB + | GT' => zopz0zI_s valB valA + | LE => zopz0zKzJ_s valB valA + | LT' => zopz0zI_s valA valB + | LTU => zopz0zI_u valA valB + end. + +Definition WordType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} +: WordType := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then B + else if sumbool_of_bool ((Z.eqb p0_ 1)) then H + else if sumbool_of_bool ((Z.eqb p0_ 2)) then W + else D. + +Definition num_of_WordType (arg_ : WordType) +: {e : Z & ArithFact (0 <= e /\ e <= 3)} := + + build_ex(match arg_ with | B => 0 | H => 1 | W => 2 | D => 3 end). + +Definition undefined_WordType '(tt : unit) +: M (WordType) := + + (internal_pick [B;H;W;D]) + : M (WordType). + +Definition WordTypeUnaligned_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} +: WordTypeUnaligned := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then WL + else if sumbool_of_bool ((Z.eqb p0_ 1)) then WR + else if sumbool_of_bool ((Z.eqb p0_ 2)) then DL + else DR. + +Definition num_of_WordTypeUnaligned (arg_ : WordTypeUnaligned) +: {e : Z & ArithFact (0 <= e /\ e <= 3)} := + + build_ex(match arg_ with | WL => 0 | WR => 1 | DL => 2 | DR => 3 end). + +Definition undefined_WordTypeUnaligned '(tt : unit) +: M (WordTypeUnaligned) := + + (internal_pick [WL;WR;DL;DR]) + : M (WordTypeUnaligned). + +Definition wordWidthBytes (w : WordType) +: {rangevar : Z & ArithFact (1 <= rangevar /\ rangevar <= 8)} := + + build_ex(match w with | B => 1 | H => 2 | W => 4 | D => 8 end). + +Definition alignment_width := 16. +Hint Unfold alignment_width : sail. +Definition isAddressAligned (addr : mword 64) (wordType : WordType) +: bool := + + let 'a := projT1 (uint addr) in + Z.eqb (projT1 (ediv_with_eq a alignment_width)) + (projT1 (ediv_with_eq (Z.sub (Z.add a (projT1 (wordWidthBytes wordType))) 1) alignment_width)). + +Definition extendLoad {sz : Z} (memResult : mword sz) (sign : bool) `{ArithFact (sz <= 64)} +: mword 64 := + + if (sign) then mips_sign_extend 64 memResult + else mips_zero_extend 64 memResult. + +Definition MEMr_wrapper (addr : mword 64) (size : Z) `{ArithFact (1 <= size /\ size <= 8)} +: M (mword (8 * size)) := + + (if ((eq_vec addr + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))) then + ((read_reg UART_RVALID_ref) : M (mword 1)) >>= fun rvalid => + write_reg UART_RVALID_ref (vec_of_bits [B0] : mword 1) >> + ((read_reg UART_RDATA_ref) : M (mword 8)) >>= fun w__0 : bits 8 => + returnm ((mask (Z.mul 8 size) + (concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) + (concat_vec w__0 + (concat_vec rvalid + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 16)))))) + : mword (8 * size)) + else if ((eq_vec addr + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0; + B0] + : mword 64))) then + returnm ((mask (Z.mul 8 size) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B1;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1] + : mword 64)) + : mword (8 * size)) + else + (MEMr addr size) >>= fun w__1 : mword (8 * size) => + returnm ((reverse_endianness w__1) + : mword (8 * size))) + : M (mword (8 * size)). + +Definition MEMr_reserve_wrapper (addr : mword 64) (size : Z) `{ArithFact (1 <= size /\ size <= 8)} +: M (mword (8 * size)) := + + (MEMr_reserve addr size) >>= fun w__0 : mword (8 * size) => + returnm ((reverse_endianness w__0) + : mword (8 * size)). + +Definition init_cp0_state '(tt : unit) +: M (unit) := + + (_set_StatusReg_BEV CP0Status_ref ((cast_unit_vec B1) : mword 1)) + : M (unit). + +Definition tlbEntryMatch (r : mword 2) (vpn2 : mword 27) (asid : mword 8) (entry : TLBEntry) +: bool := + + let entryValid := _get_TLBEntry_valid entry in + let entryR := _get_TLBEntry_r entry in + let entryMask := _get_TLBEntry_pagemask entry in + let entryVPN := _get_TLBEntry_vpn2 entry in + let entryASID := _get_TLBEntry_asid entry in + let entryG := _get_TLBEntry_g entry in + let vpnMask : bits 27 := not_vec (mips_zero_extend 27 entryMask) in + andb ((bits_to_bool entryValid) : bool) + (andb (eq_vec r entryR) + (andb (eq_vec (and_vec vpn2 vpnMask) (and_vec entryVPN vpnMask)) + (orb (eq_vec asid entryASID) ((bits_to_bool entryG) : bool)))). + +Definition tlbSearch (VAddr : mword 64) +: M (option (mword 6)) := + + catch_early_return + (let r := subrange_vec_dec VAddr 63 62 in + let vpn2 := subrange_vec_dec VAddr 39 13 in + liftR (read_reg TLBEntryHi_ref) >>= fun w__0 : TLBEntryHiReg => + let asid := _get_TLBEntryHiReg_ASID w__0 in + (foreach_ZM_up 0 63 1 tt + (fun idx _ unit_var => + liftR ((reg_deref (vec_access_dec TLBEntries idx))) >>= fun w__1 : TLBEntry => + (if ((tlbEntryMatch r vpn2 asid w__1)) then + (early_return ((Some + (to_bits 6 idx)) + : option (mword 6))) + : MR (unit) _ + else returnm (tt : unit)) + : MR (unit) _)) >> + returnm (None + : option (mword 6))). + +Definition TLBTranslate2 (vAddr : mword 64) (accessType : MemAccessType) +: M ((mword 64 * bool)) := + + (tlbSearch vAddr) >>= fun idx => + (match idx with + | Some (idx) => + let 'i := projT1 (uint idx) in + (reg_deref (vec_access_dec TLBEntries i)) >>= fun entry => + let entryMask := _get_TLBEntry_pagemask entry in + let b__0 := entryMask in + (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16))) + then + returnm (build_ex (12 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 16))) + then + returnm (build_ex (14 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (16 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (18 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (20 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (22 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (24 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (26 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (28 + : Z)) + else + (undefined_range 12 28) + : M ({rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})) >>= fun '(existT _ evenOddBit _ : {rangevar : Z & ArithFact (12 <= + rangevar /\ + rangevar <= 28)}) => + let isOdd := access_vec_dec vAddr evenOddBit in + let '(caps, capl, pfn, d, v) := + if (((bit_to_bool isOdd) : bool)) then + (_get_TLBEntry_caps1 entry, _get_TLBEntry_capl1 entry, _get_TLBEntry_pfn1 entry, _get_TLBEntry_d1 + entry, _get_TLBEntry_v1 + entry) + else + (_get_TLBEntry_caps0 entry, _get_TLBEntry_capl0 entry, _get_TLBEntry_pfn0 entry, _get_TLBEntry_d0 + entry, _get_TLBEntry_v0 + entry) in + (if ((negb ((bits_to_bool v) : bool))) then + (SignalExceptionTLB (if ((generic_eq accessType StoreData)) then XTLBInvS else XTLBInvL) + vAddr) + : M ((mword 64 * bool)) + else if ((andb (generic_eq accessType StoreData) (negb ((bits_to_bool d) : bool)))) then + (SignalExceptionTLB TLBMod vAddr) + : M ((mword 64 * bool)) + else + let res : bits 64 := + mips_zero_extend 64 + (concat_vec (subrange_vec_dec pfn 23 (Z.sub evenOddBit 12)) + (subrange_vec_dec vAddr (Z.sub evenOddBit 1) 0)) in + returnm (res, bits_to_bool (if ((generic_eq accessType StoreData)) then caps else capl))) + : M ((mword 64 * bool)) + | None => + (SignalExceptionTLB + (if ((generic_eq accessType StoreData)) then XTLBRefillS + else XTLBRefillL) vAddr) + : M ((mword 64 * bool)) + end) + : M ((mword 64 * bool)). + +Definition TLBTranslateC (vAddr : mword 64) (accessType : MemAccessType) +: M ((mword 64 * bool)) := + + (getAccessLevel tt) >>= fun currentAccessLevel => + let compat32 := + eq_vec (subrange_vec_dec vAddr 61 31) + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : mword (61 - 31 + 1)) in + let b__0 := subrange_vec_dec vAddr 63 62 in + let '(requiredLevel, addr) := + (if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword (63 - 62 + 1)))) then + match (compat32, subrange_vec_dec vAddr 30 29) with + | (true, b__1) => + if ((eq_vec b__1 (vec_of_bits [B1;B1] : mword (30 - 29 + 1)))) then + (Kernel, None + : option (bits 64)) + else if ((eq_vec b__1 (vec_of_bits [B1;B0] : mword (30 - 29 + 1)))) then + (Supervisor, None + : option (bits 64)) + else if ((eq_vec b__1 (vec_of_bits [B0;B1] : mword (30 - 29 + 1)))) then + (Kernel, Some + (concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (subrange_vec_dec vAddr 28 0)))) + else if ((eq_vec b__1 (vec_of_bits [B0;B0] : mword (30 - 29 + 1)))) then + (Kernel, Some + (concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (subrange_vec_dec vAddr 28 0)))) + else match (true, b__1) with | (g__14, g__15) => (Kernel, None : option (bits 64)) end + | (g__14, g__15) => (Kernel, None : option (bits 64)) + end + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword (63 - 62 + 1)))) then + (Kernel, Some + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (subrange_vec_dec vAddr 58 0))) + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword (63 - 62 + 1)))) then + (Supervisor, None + : option (bits 64)) + else (User, None : option (bits 64))) + : (AccessLevel * option (bits 64)) in + (if ((negb (grantsAccess currentAccessLevel requiredLevel))) then + (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL) vAddr) + : M ((mword 64 * bool)) + else + (match addr with + | Some (a) => returnm (a, false) + | None => + (if sumbool_of_bool ((andb (negb compat32) + (Z.gtb (projT1 (uint (subrange_vec_dec vAddr 61 0))) MAX_VA))) + then + (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL) + vAddr) + : M ((mword 64 * bool)) + else (TLBTranslate2 vAddr accessType) : M ((mword 64 * bool))) + : M ((mword 64 * bool)) + end) >>= fun '(pa, c) => + (if sumbool_of_bool ((Z.gtb (projT1 (uint pa)) MAX_PA)) then + (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL) vAddr) + : M ((mword 64 * bool)) + else returnm (pa, c)) + : M ((mword 64 * bool))) + : M ((mword 64 * bool)). + +Definition TLBTranslate (vAddr : mword 64) (accessType : MemAccessType) +: M (mword 64) := + + (TLBTranslateC vAddr accessType) >>= fun '(addr, c) => returnm (addr : mword 64). + +Definition MEMw_wrapper (addr : mword 64) (size : Z) (data : mword (8 * size)) +`{ArithFact (1 <= size /\ size <= 8)} +: M (unit) := + + let ledata := reverse_endianness data in + (if ((eq_vec addr + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))) then + write_reg UART_WDATA_ref (subrange_vec_dec ledata 7 0) >> + write_reg UART_WRITTEN_ref ((cast_unit_vec B1) : bits 1) + : M (unit) + else (MEMea addr size) >> (MEMval addr size ledata) : M (unit)) + : M (unit). + +Definition MEMw_conditional_wrapper (addr : mword 64) (size : Z) (data : mword (8 * size)) +`{ArithFact (1 <= size /\ size <= 8)} +: M (bool) := + + (MEMea_conditional addr size) >> + (MEMval_conditional addr size (reverse_endianness data)) + : M (bool). + +Definition addrWrapper (addr : mword 64) (accessType : MemAccessType) (width : WordType) +: mword 64 := + + addr. + +Definition addrWrapperUnaligned +(addr : mword 64) (accessType : MemAccessType) (width : WordTypeUnaligned) +: mword 64 := + + addr. + +Definition TranslatePC (vAddr : mword 64) +: M (mword 64) := + + (incrementCP0Count tt) >> + (if ((neq_vec (subrange_vec_dec vAddr 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) then + (SignalExceptionBadAddr AdEL vAddr) + : M (mword 64) + else (TLBTranslate vAddr Instruction) : M (mword 64)) + : M (mword 64). + +Definition have_cp2 := false. +Hint Unfold have_cp2 : sail. +Definition ERETHook '(tt : unit) : unit := tt. + +Definition init_cp2_state '(tt : unit) : M (unit) := (skip tt) >> (skip tt) : M (unit). + +Definition cp2_next_pc '(tt : unit) : M (unit) := (skip tt) >> (skip tt) : M (unit). + +Definition dump_cp2_state '(tt : unit) : M (unit) := (skip tt) >> (skip tt) : M (unit). + +Definition execute_branch (pc : mword 64) +: M (unit) := + + (skip tt) >> (skip tt) >> (execute_branch_mips pc) : M (unit). + +Definition TLBWriteEntry (idx : mword 6) +: M (unit) := + + ((read_reg TLBPageMask_ref) : M (mword 16)) >>= fun pagemask => + let b__0 := pagemask in + (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16))) + then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else (SignalException MCheck) : M (unit)) >> + let 'i := projT1 (uint idx) in + let entry := vec_access_dec TLBEntries i in + (_set_TLBEntry_pagemask entry pagemask) >> + read_reg TLBEntryHi_ref >>= fun w__0 : TLBEntryHiReg => + (_set_TLBEntry_r entry (_get_TLBEntryHiReg_R w__0)) >> + read_reg TLBEntryHi_ref >>= fun w__1 : TLBEntryHiReg => + (_set_TLBEntry_vpn2 entry (_get_TLBEntryHiReg_VPN2 w__1)) >> + read_reg TLBEntryHi_ref >>= fun w__2 : TLBEntryHiReg => + (_set_TLBEntry_asid entry (_get_TLBEntryHiReg_ASID w__2)) >> + (and_boolM + (read_reg TLBEntryLo0_ref >>= fun w__3 : TLBEntryLoReg => + returnm ((bits_to_bool (_get_TLBEntryLoReg_G w__3)) + : bool)) + (read_reg TLBEntryLo1_ref >>= fun w__4 : TLBEntryLoReg => + returnm ((bits_to_bool (_get_TLBEntryLoReg_G w__4)) + : bool))) >>= fun w__5 : bool => + (_set_TLBEntry_g entry ((bool_to_bits w__5) : mword 1)) >> + (_set_TLBEntry_valid entry ((cast_unit_vec B1) : mword 1)) >> + read_reg TLBEntryLo0_ref >>= fun w__6 : TLBEntryLoReg => + (_set_TLBEntry_caps0 entry (_get_TLBEntryLoReg_CapS w__6)) >> + read_reg TLBEntryLo0_ref >>= fun w__7 : TLBEntryLoReg => + (_set_TLBEntry_capl0 entry (_get_TLBEntryLoReg_CapL w__7)) >> + read_reg TLBEntryLo0_ref >>= fun w__8 : TLBEntryLoReg => + (_set_TLBEntry_pfn0 entry (_get_TLBEntryLoReg_PFN w__8)) >> + read_reg TLBEntryLo0_ref >>= fun w__9 : TLBEntryLoReg => + (_set_TLBEntry_c0 entry (_get_TLBEntryLoReg_C w__9)) >> + read_reg TLBEntryLo0_ref >>= fun w__10 : TLBEntryLoReg => + (_set_TLBEntry_d0 entry (_get_TLBEntryLoReg_D w__10)) >> + read_reg TLBEntryLo0_ref >>= fun w__11 : TLBEntryLoReg => + (_set_TLBEntry_v0 entry (_get_TLBEntryLoReg_V w__11)) >> + read_reg TLBEntryLo1_ref >>= fun w__12 : TLBEntryLoReg => + (_set_TLBEntry_caps1 entry (_get_TLBEntryLoReg_CapS w__12)) >> + read_reg TLBEntryLo1_ref >>= fun w__13 : TLBEntryLoReg => + (_set_TLBEntry_capl1 entry (_get_TLBEntryLoReg_CapL w__13)) >> + read_reg TLBEntryLo1_ref >>= fun w__14 : TLBEntryLoReg => + (_set_TLBEntry_pfn1 entry (_get_TLBEntryLoReg_PFN w__14)) >> + read_reg TLBEntryLo1_ref >>= fun w__15 : TLBEntryLoReg => + (_set_TLBEntry_c1 entry (_get_TLBEntryLoReg_C w__15)) >> + read_reg TLBEntryLo1_ref >>= fun w__16 : TLBEntryLoReg => + (_set_TLBEntry_d1 entry (_get_TLBEntryLoReg_D w__16)) >> + read_reg TLBEntryLo1_ref >>= fun w__17 : TLBEntryLoReg => + (_set_TLBEntry_v1 entry (_get_TLBEntryLoReg_V w__17)) + : M (unit). + +Definition decode (v__0 : mword 32) +: option ast := + + if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B0;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (DADDIU + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DADDU + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B0;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (DADDI + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DADD + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (ADD + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B0;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (ADDI + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (ADDU + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B0;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (ADDIU + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSUBU + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSUB + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SUB + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SUBU + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (AND + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (ANDI + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (OR + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B1;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (ORI + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (NOR + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (XOR + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B1;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (XORI + ((rs, rt, imm))) + else if ((eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0] : mword (31 - 21 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (LUI + ((rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B0;B0;B0] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSLL + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B1;B0;B0] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSLL32 + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSLLV + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B0;B1;B1] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSRA + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B1;B1;B1] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSRA32 + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSRAV + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B0;B1;B0] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSRL + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B1;B1;B0] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSRL32 + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSRLV + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let sa : regno := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SLL + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SLLV + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B1;B1] : mword (5 - 0 + 1))))) then + let sa : regno := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SRA + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SRAV + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B1;B0] : mword (5 - 0 + 1))))) then + let sa : regno := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SRL + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SRLV + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SLT + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B0;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (SLTI + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SLTU + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B0;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (SLTIU + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MOVN + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MOVZ + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 16) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (31 - 16 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MFHI + (rd)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 16) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (31 - 16 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MFLO + (rd)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B1] + : mword (20 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MTHI + (rs)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B1] + : mword (20 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MTLO + (rs)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MUL + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MULT + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MULTU + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DMULT + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B1] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DMULTU + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MADD + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MADDU + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MSUB + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MSUBU + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B0] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DIV + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DIVU + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B0] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DDIV + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DDIVU + ((rs, rt))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B1;B0] : mword (31 - 26 + 1)))) then + let offset : bits 26 := subrange_vec_dec v__0 25 0 in + Some + (J + (offset)) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B1;B1] : mword (31 - 26 + 1)))) then + let offset : bits 26 := subrange_vec_dec v__0 25 0 in + Some + (JAL + (offset)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (andb + (eq_vec (subrange_vec_dec v__0 20 11) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (20 - 11 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B0;B0;B0] : mword (5 - 0 + 1)))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (JR + (rs)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (andb + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1] : mword (5 - 0 + 1)))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (JALR + ((rs, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BEQ + ((rs, rt, imm, false, false))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B0;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BEQ + ((rs, rt, imm, false, true))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B1;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BEQ + ((rs, rt, imm, true, false))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B0;B1;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BEQ + ((rs, rt, imm, true, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, LT', false, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B1;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, LT', true, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B1;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, LT', false, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B1;B0;B0;B1;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, LT', true, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B1] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, GE, false, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B1;B0;B0;B0;B1] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, GE, true, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B1;B1] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, GE, false, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B1;B0;B0;B1;B1] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, GE, true, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B1;B1;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, GT', false, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B0;B1;B1;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, GT', false, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B1;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, LE, false, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B0;B1;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, LE, false, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B1;B0;B0] : mword (5 - 0 + 1))))) then + Some + (SYSCALL + (tt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1] : mword (5 - 0 + 1))))) then + Some + (BREAK + (tt)) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0] + : mword 32))) then + Some + (WAIT + (tt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, GE))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B0;B0;B1] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, GEU))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B0;B1;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, LT'))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B0;B1;B1] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, LTU))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B1;B0;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, EQ'))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B1;B1;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, NE))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B1;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (TRAPIMM + ((rs, imm, EQ'))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B1;B1;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (TRAPIMM + ((rs, imm, NE))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (TRAPIMM + ((rs, imm, GE))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B0;B0;B1] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (TRAPIMM + ((rs, imm, GEU))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B0;B1;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (TRAPIMM + ((rs, imm, LT'))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B0;B1;B1] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (TRAPIMM + ((rs, imm, LTU))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B0;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((B, true, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((B, false, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B0;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((H, true, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B1;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((H, false, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((W, true, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((W, false, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B1;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((D, false, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B0;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((W, true, true, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((D, false, true, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B0;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((B, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B0;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((H, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B0;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((W, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B1;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((D, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B0;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((W, true, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((D, true, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B0;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (LWL + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B1;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (LWR + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B0;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (SWL + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B1;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (SWR + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B0;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (LDL + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B0;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (LDR + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (SDL + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B1;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (SDR + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B1;B1;B1] : mword (31 - 26 + 1)))) then + let op : regno := subrange_vec_dec v__0 20 16 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (CACHE + ((base, op, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 11) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (31 - 11 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B1;B1;B1] : mword (5 - 0 + 1))))) then + Some + (SYNC + (tt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 3) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 3 + 1))))) then + let sel : bits 3 := subrange_vec_dec v__0 2 0 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MFC0 + ((rt, rd, sel, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 3) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 3 + 1))))) then + let sel : bits 3 := subrange_vec_dec v__0 2 0 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MFC0 + ((rt, rd, sel, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (15 - 0 + 1))))) then + Some + (HCF + (tt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B1;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (15 - 0 + 1))))) then + Some + (HCF + (tt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 3) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 3 + 1))))) then + let sel : bits 3 := subrange_vec_dec v__0 2 0 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MTC0 + ((rt, rd, sel, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 3) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 3 + 1))))) then + let sel : bits 3 := subrange_vec_dec v__0 2 0 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MTC0 + ((rt, rd, sel, true))) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] + : mword 32))) then + Some + ((TLBWI + (tt)) + : ast) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] + : mword 32))) then + Some + ((TLBWR + (tt)) + : ast) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] + : mword 32))) then + Some + ((TLBR + (tt)) + : ast) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0] + : mword 32))) then + Some + ((TLBP + (tt)) + : ast) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B0;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (RDHWR + ((rt, rd))) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0] + : mword 32))) then + Some + (ERET + (tt)) + else Some (RI (tt)). + +Definition execute_XORI (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (wGPR rt (xor_vec w__0 (mips_zero_extend 64 imm))) + : M (unit). + +Definition execute_XOR (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (xor_vec w__0 w__1)) : M (unit). + +Definition execute_WAIT '(tt : unit) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + write_reg NextPC_ref w__1 + : M (unit). + +Definition execute_TRAPREG (rs : mword 5) (rt : mword 5) (cmp : Comparison) +: M (unit) := + + (rGPR rs) >>= fun rs_val => + (rGPR rt) >>= fun rt_val => + let condition := compare cmp rs_val rt_val in + (if (condition) then (SignalException Tr) : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_TRAPIMM (rs : mword 5) (imm : mword 16) (cmp : Comparison) +: M (unit) := + + (rGPR rs) >>= fun rs_val => + let imm_val : bits 64 := mips_sign_extend 64 imm in + let condition := compare cmp rs_val imm_val in + (if (condition) then (SignalException Tr) : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_TLBWR '(tt : unit) +: M (unit) := + + (checkCP0Access tt) >> + ((read_reg TLBRandom_ref) : M (mword 6)) >>= fun w__0 : TLBIndexT => + (TLBWriteEntry w__0) + : M (unit). + +Definition execute_TLBWI '(tt : unit) +: M (unit) := + + (checkCP0Access tt) >> + ((read_reg TLBIndex_ref) : M (mword 6)) >>= fun w__0 : TLBIndexT => + (TLBWriteEntry w__0) + : M (unit). + +Definition execute_TLBR '(tt : unit) +: M (unit) := + + (checkCP0Access tt) >> + ((read_reg TLBIndex_ref) : M (mword 6)) >>= fun w__0 : TLBIndexT => + let 'i := projT1 (uint w__0) in + (reg_deref (vec_access_dec TLBEntries i)) >>= fun entry => + write_reg TLBPageMask_ref (_get_TLBEntry_pagemask entry) >> + (_set_TLBEntryHiReg_R TLBEntryHi_ref (_get_TLBEntry_r entry)) >> + (_set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (_get_TLBEntry_vpn2 entry)) >> + (_set_TLBEntryHiReg_ASID TLBEntryHi_ref (_get_TLBEntry_asid entry)) >> + (_set_TLBEntryLoReg_CapS TLBEntryLo0_ref (_get_TLBEntry_caps0 entry)) >> + (_set_TLBEntryLoReg_CapL TLBEntryLo0_ref (_get_TLBEntry_capl0 entry)) >> + (_set_TLBEntryLoReg_PFN TLBEntryLo0_ref (_get_TLBEntry_pfn0 entry)) >> + (_set_TLBEntryLoReg_C TLBEntryLo0_ref (_get_TLBEntry_c0 entry)) >> + (_set_TLBEntryLoReg_D TLBEntryLo0_ref (_get_TLBEntry_d0 entry)) >> + (_set_TLBEntryLoReg_V TLBEntryLo0_ref (_get_TLBEntry_v0 entry)) >> + (_set_TLBEntryLoReg_G TLBEntryLo0_ref (_get_TLBEntry_g entry)) >> + (_set_TLBEntryLoReg_CapS TLBEntryLo1_ref (_get_TLBEntry_caps1 entry)) >> + (_set_TLBEntryLoReg_CapL TLBEntryLo1_ref (_get_TLBEntry_capl1 entry)) >> + (_set_TLBEntryLoReg_PFN TLBEntryLo1_ref (_get_TLBEntry_pfn1 entry)) >> + (_set_TLBEntryLoReg_C TLBEntryLo1_ref (_get_TLBEntry_c1 entry)) >> + (_set_TLBEntryLoReg_D TLBEntryLo1_ref (_get_TLBEntry_d1 entry)) >> + (_set_TLBEntryLoReg_V TLBEntryLo1_ref (_get_TLBEntry_v1 entry)) >> + (_set_TLBEntryLoReg_G TLBEntryLo1_ref (_get_TLBEntry_g entry)) + : M (unit). + +Definition execute_TLBP '(tt : unit) +: M (unit) := + + (checkCP0Access tt) >> + read_reg TLBEntryHi_ref >>= fun w__0 : TLBEntryHiReg => + (tlbSearch (_get_TLBEntryHiReg_bits w__0)) >>= fun result => + (match result with + | Some (idx) => + write_reg TLBProbe_ref (vec_of_bits [B0] : mword 1) >> + write_reg TLBIndex_ref idx + : M (unit) + | None => + write_reg TLBProbe_ref (vec_of_bits [B1] : mword 1) >> + write_reg TLBIndex_ref (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6) + : M (unit) + end) + : M (unit). + +Definition execute_Store +(width : WordType) (conditional : bool) (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + let vAddr : bits 64 := addrWrapper (add_vec (mips_sign_extend 64 offset) w__0) StoreData width in + (rGPR rt) >>= fun rt_val => + (if ((negb (isAddressAligned vAddr width))) then (SignalExceptionBadAddr AdES vAddr) : M (unit) + else + (TLBTranslate vAddr StoreData) >>= fun pAddr => + (if (conditional) then + ((read_reg CP0LLBit_ref) : M (mword 1)) >>= fun w__1 : bits 1 => + (if (((bit_to_bool (access_vec_dec w__1 0)) : bool)) then + (match width with + | W => (MEMw_conditional_wrapper pAddr 4 (subrange_vec_dec rt_val 31 0)) : M (bool) + | D => (MEMw_conditional_wrapper pAddr 8 rt_val) : M (bool) + | _ => (throw (Error_internal_error (tt))) : M (bool) + end) + : M (bool) + else returnm (false : bool)) >>= fun success : bool => + (wGPR rt (mips_zero_extend 64 (bool_to_bits success))) + : M (unit) + else + (match width with + | B => (MEMw_wrapper pAddr 1 (subrange_vec_dec rt_val 7 0)) : M (unit) + | H => (MEMw_wrapper pAddr 2 (subrange_vec_dec rt_val 15 0)) : M (unit) + | W => (MEMw_wrapper pAddr 4 (subrange_vec_dec rt_val 31 0)) : M (unit) + | D => (MEMw_wrapper pAddr 8 rt_val) : M (unit) + end) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_SYSCALL '(tt : unit) : M (unit) := (SignalException Sys) : M (unit). + +Definition execute_SYNC '(tt : unit) : M (unit) := (MEM_sync tt) : M (unit). + +Definition execute_SWR (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData WR in + (TLBTranslate vAddr StoreData) >>= fun pAddr => + let wordAddr := concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0] : mword 2) in + (rGPR rt) >>= fun reg_val => + let b__12 := subrange_vec_dec vAddr 1 0 in + (if ((eq_vec b__12 (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) then + (MEMw_wrapper wordAddr 1 (subrange_vec_dec reg_val 7 0)) + : M (unit) + else if ((eq_vec b__12 (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))) then + (MEMw_wrapper wordAddr 2 (subrange_vec_dec reg_val 15 0)) + : M (unit) + else if ((eq_vec b__12 (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))) then + (MEMw_wrapper wordAddr 3 (subrange_vec_dec reg_val 23 0)) + : M (unit) + else (MEMw_wrapper wordAddr 4 (subrange_vec_dec reg_val 31 0)) : M (unit)) + : M (unit). + +Definition execute_SWL (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData WL in + (TLBTranslate vAddr StoreData) >>= fun pAddr => + (rGPR rt) >>= fun reg_val => + let b__8 := subrange_vec_dec vAddr 1 0 in + (if ((eq_vec b__8 (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) then + (MEMw_wrapper pAddr 4 (subrange_vec_dec reg_val 31 0)) + : M (unit) + else if ((eq_vec b__8 (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))) then + (MEMw_wrapper pAddr 3 (subrange_vec_dec reg_val 31 8)) + : M (unit) + else if ((eq_vec b__8 (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))) then + (MEMw_wrapper pAddr 2 (subrange_vec_dec reg_val 31 16)) + : M (unit) + else (MEMw_wrapper pAddr 1 (subrange_vec_dec reg_val 31 24)) : M (unit)) + : M (unit). + +Definition execute_SUBU (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun opA => + (rGPR rt) >>= fun opB => + (if ((orb (NotWordVal opA) (NotWordVal opB))) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) + else + (wGPR rd + (mips_sign_extend 64 (sub_vec (subrange_vec_dec opA 31 0) (subrange_vec_dec opB 31 0)))) + : M (unit)) + : M (unit). + +Definition execute_SUB (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun opA => + (rGPR rt) >>= fun opB => + (if ((orb (NotWordVal opA) (NotWordVal opB))) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) + else + let temp33 : bits 33 := + sub_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0)) + (mips_sign_extend 33 (subrange_vec_dec opB 31 0)) in + (if ((neq_bool ((bit_to_bool (access_vec_dec temp33 32)) : bool) + ((bit_to_bool (access_vec_dec temp33 31)) + : bool))) then + (SignalException Ov) + : M (unit) + else (wGPR rd (mips_sign_extend 64 (subrange_vec_dec temp33 31 0))) : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_SRLV (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (rGPR rs) >>= fun w__0 : mword 64 => + let sa := subrange_vec_dec w__0 4 0 in + (if ((NotWordVal temp)) then + (undefined_bitvector 64) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit) + else + let rt32 := subrange_vec_dec temp 31 0 in + (shift_bits_right rt32 sa) >>= fun w__2 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__2)) + : M (unit)) + : M (unit). + +Definition execute_SRL (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (if ((NotWordVal temp)) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) + else + let rt32 := subrange_vec_dec temp 31 0 in + (shift_bits_right rt32 sa) >>= fun w__1 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__1)) + : M (unit)) + : M (unit). + +Definition execute_SRAV (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (rGPR rs) >>= fun w__0 : mword 64 => + let sa := subrange_vec_dec w__0 4 0 in + (if ((NotWordVal temp)) then + (undefined_bitvector 64) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit) + else + let rt32 := subrange_vec_dec temp 31 0 in + (shift_bits_right_arith rt32 sa) >>= fun w__2 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__2)) + : M (unit)) + : M (unit). + +Definition execute_SRA (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (if ((NotWordVal temp)) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) + else + let rt32 := subrange_vec_dec temp 31 0 in + (shift_bits_right_arith rt32 sa) >>= fun w__1 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__1)) + : M (unit)) + : M (unit). + +Definition execute_SLTU (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rs_val => + (rGPR rt) >>= fun rt_val => + (wGPR rd + (mips_zero_extend 64 + (if ((zopz0zI_u rs_val rt_val)) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1)))) + : M (unit). + +Definition execute_SLTIU (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun rs_val => + let immext : bits 64 := mips_sign_extend 64 imm in + (wGPR rt + (mips_zero_extend 64 + (if ((zopz0zI_u rs_val immext)) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1)))) + : M (unit). + +Definition execute_SLTI (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + let 'imm_val := projT1 (sint imm) in + (rGPR rs) >>= fun w__0 : mword 64 => + let 'rs_val := projT1 (sint w__0) in + (wGPR rt + (mips_zero_extend 64 + (if sumbool_of_bool ((Z.ltb rs_val imm_val)) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1)))) + : M (unit). + +Definition execute_SLT (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => + (wGPR rd + (mips_zero_extend 64 + (if ((zopz0zI_s w__0 w__1)) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1)))) + : M (unit). + +Definition execute_SLLV (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + let sa := subrange_vec_dec w__0 4 0 in + (rGPR rt) >>= fun w__1 : mword 64 => + let rt32 := subrange_vec_dec w__1 31 0 in + (shift_bits_left rt32 sa) >>= fun w__2 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__2)) + : M (unit). + +Definition execute_SLL (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun w__0 : mword 64 => + let rt32 := subrange_vec_dec w__0 31 0 in + (shift_bits_left rt32 sa) >>= fun w__1 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__1)) + : M (unit). + +Definition execute_SDR (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData DR in + (TLBTranslate vAddr StoreData) >>= fun pAddr => + (rGPR rt) >>= fun reg_val => + let wordAddr := concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0] : mword 3) in + let b__40 := subrange_vec_dec vAddr 2 0 in + (if ((eq_vec b__40 (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 1 (subrange_vec_dec reg_val 7 0)) + : M (unit) + else if ((eq_vec b__40 (vec_of_bits [B0;B0;B1] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 2 (subrange_vec_dec reg_val 15 0)) + : M (unit) + else if ((eq_vec b__40 (vec_of_bits [B0;B1;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 3 (subrange_vec_dec reg_val 23 0)) + : M (unit) + else if ((eq_vec b__40 (vec_of_bits [B0;B1;B1] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 4 (subrange_vec_dec reg_val 31 0)) + : M (unit) + else if ((eq_vec b__40 (vec_of_bits [B1;B0;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 5 (subrange_vec_dec reg_val 39 0)) + : M (unit) + else if ((eq_vec b__40 (vec_of_bits [B1;B0;B1] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 6 (subrange_vec_dec reg_val 47 0)) + : M (unit) + else if ((eq_vec b__40 (vec_of_bits [B1;B1;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 7 (subrange_vec_dec reg_val 55 0)) + : M (unit) + else (MEMw_wrapper wordAddr 8 (subrange_vec_dec reg_val 63 0)) : M (unit)) + : M (unit). + +Definition execute_SDL (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData DL in + (TLBTranslate vAddr StoreData) >>= fun pAddr => + (rGPR rt) >>= fun reg_val => + let b__32 := subrange_vec_dec vAddr 2 0 in + (if ((eq_vec b__32 (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 8 (subrange_vec_dec reg_val 63 0)) + : M (unit) + else if ((eq_vec b__32 (vec_of_bits [B0;B0;B1] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 7 (subrange_vec_dec reg_val 63 8)) + : M (unit) + else if ((eq_vec b__32 (vec_of_bits [B0;B1;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 6 (subrange_vec_dec reg_val 63 16)) + : M (unit) + else if ((eq_vec b__32 (vec_of_bits [B0;B1;B1] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 5 (subrange_vec_dec reg_val 63 24)) + : M (unit) + else if ((eq_vec b__32 (vec_of_bits [B1;B0;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 4 (subrange_vec_dec reg_val 63 32)) + : M (unit) + else if ((eq_vec b__32 (vec_of_bits [B1;B0;B1] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 3 (subrange_vec_dec reg_val 63 40)) + : M (unit) + else if ((eq_vec b__32 (vec_of_bits [B1;B1;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 2 (subrange_vec_dec reg_val 63 48)) + : M (unit) + else (MEMw_wrapper pAddr 1 (subrange_vec_dec reg_val 63 56)) : M (unit)) + : M (unit). + +Definition execute_RI '(tt : unit) : M (unit) := (skip tt) >> (SignalException ResI) : M (unit). + +Definition execute_RDHWR (rt : mword 5) (rd : mword 5) +: M (unit) := + + (getAccessLevel tt) >>= fun accessLevel => + let haveAccessLevel : bool := generic_eq accessLevel Kernel in + read_reg CP0Status_ref >>= fun w__0 : StatusReg => + let haveCU0 : bool := eq_bit B1 (access_vec_dec (_get_StatusReg_CU w__0) 0) in + let 'rdi := projT1 (uint rd) in + ((read_reg CP0HWREna_ref) : M (mword 32)) >>= fun w__1 : bits 32 => + let haveHWREna : bool := eq_bit B1 (access_vec_dec w__1 rdi) in + (if ((negb (orb haveAccessLevel (orb haveCU0 haveHWREna)))) then + (SignalException ResI) + : M (unit) + else returnm (tt : unit)) >> + let b__150 := rd in + (if ((eq_vec b__150 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((eq_vec b__150 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((eq_vec b__150 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5))) then + ((read_reg CP0Count_ref) : M (mword 32)) >>= fun w__2 : bits 32 => + returnm ((mips_zero_extend 64 w__2) + : mword 64) + else if ((eq_vec b__150 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B1] : mword 1)) + : mword 64) + else if ((eq_vec b__150 (vec_of_bits [B1;B1;B1;B0;B1] : mword 5))) then + ((read_reg CP0UserLocal_ref) : M (mword 64)) + : M (bits 64) + else (SignalException ResI) : M (mword 64)) >>= fun temp : bits 64 => + (wGPR rt temp) + : M (unit). + +Definition execute_ORI (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (wGPR rt (or_vec w__0 (mips_zero_extend 64 imm))) + : M (unit). + +Definition execute_OR (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (or_vec w__0 w__1)) : M (unit). + +Definition execute_NOR (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (not_vec (or_vec w__0 w__1))) : M (unit). + +Definition execute_MULTU (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun result : bits 64 => + write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> + write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) + : M (unit). + +Definition execute_MULT (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun result : bits 64 => + write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> + write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) + : M (unit). + +Definition execute_MUL (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + let result : bits 64 := + mips_sign_extend 64 (mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) in + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else returnm ((mips_sign_extend 64 (subrange_vec_dec result 31 0)) : mword 64)) >>= fun w__1 : mword 64 => + (wGPR rd w__1) + : M (unit). + +Definition execute_MTLO (rs : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => write_reg LO_ref w__0 : M (unit). + +Definition execute_MTHI (rs : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => write_reg HI_ref w__0 : M (unit). + +Definition execute_MTC0 (rt : mword 5) (rd : mword 5) (sel : mword 3) (double : bool) +: M (unit) := + + (checkCP0Access tt) >> + (rGPR rt) >>= fun reg_val => + (match (rd, sel) with + | (b__112, b__113) => + (if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg TLBIndex_ref (mask 6 reg_val) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + returnm (tt + : unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_TLBEntryLoReg_bits TLBEntryLo0_ref reg_val) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_TLBEntryLoReg_bits TLBEntryLo1_ref reg_val) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_ContextReg_PTEBase TLBContext_ref (subrange_vec_dec reg_val 63 23)) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B1;B0] : mword 3)))) then + write_reg CP0UserLocal_ref reg_val + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B1;B0;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg TLBPageMask_ref (subrange_vec_dec reg_val 28 13) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B1;B1;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg TLBWired_ref (mask 6 reg_val) >> write_reg TLBRandom_ref TLBIndexMax : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B1;B1;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg + CP0HWREna_ref + (concat_vec (subrange_vec_dec reg_val 31 29) + (concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0] + : mword 25) (subrange_vec_dec reg_val 3 0))) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + returnm (tt + : unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B0;B0;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg CP0Count_ref (subrange_vec_dec reg_val 31 0) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B0;B1;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_TLBEntryHiReg_R TLBEntryHi_ref (subrange_vec_dec reg_val 63 62)) >> + (_set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (subrange_vec_dec reg_val 39 13)) >> + (_set_TLBEntryHiReg_ASID TLBEntryHi_ref (subrange_vec_dec reg_val 7 0)) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B0;B1;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg CP0Compare_ref (subrange_vec_dec reg_val 31 0) >> + read_reg CP0Cause_ref >>= fun w__0 : CauseReg => + (_set_CauseReg_IP CP0Cause_ref + (and_vec (_get_CauseReg_IP w__0) (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1] : mword 8))) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_StatusReg_CU CP0Status_ref + (and_vec (subrange_vec_dec reg_val 31 28) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (bool_to_bits have_cp2) (vec_of_bits [B0;B1] : mword 2))))) >> + (_set_StatusReg_BEV CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 22)) : mword 1)) >> + (_set_StatusReg_IM CP0Status_ref (subrange_vec_dec reg_val 15 8)) >> + (_set_StatusReg_KX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 7)) : mword 1)) >> + (_set_StatusReg_SX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 6)) : mword 1)) >> + (_set_StatusReg_UX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 5)) : mword 1)) >> + (_set_StatusReg_KSU CP0Status_ref (subrange_vec_dec reg_val 4 3)) >> + (_set_StatusReg_ERL CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 2)) : mword 1)) >> + (_set_StatusReg_EXL CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 1)) : mword 1)) >> + (_set_StatusReg_IE CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 0)) : mword 1)) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B1;B0;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_CauseReg_IV CP0Cause_ref ((cast_unit_vec (access_vec_dec reg_val 23)) : mword 1)) >> + read_reg CP0Cause_ref >>= fun w__1 : CauseReg => + let ip := _get_CauseReg_IP w__1 in + (_set_CauseReg_IP CP0Cause_ref + (concat_vec (subrange_vec_dec ip 7 2) (subrange_vec_dec reg_val 9 8))) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B1;B1;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg CP0EPC_ref reg_val + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg CP0ConfigK0_ref (subrange_vec_dec reg_val 2 0) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_XContextReg_XPTEBase TLBXContext_ref (subrange_vec_dec reg_val 63 33)) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B1;B1;B1;B1;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg CP0ErrorEPC_ref reg_val + : M (unit) + else (SignalException ResI) : M (unit)) + : M (unit) + end) + : M (unit). + +Definition execute_MSUBU (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun mul_result : bits 64 => + ((read_reg HI_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + ((read_reg LO_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + let result := + sub_vec (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) mul_result in + write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> + write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) + : M (unit). + +Definition execute_MSUB (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun mul_result : bits 64 => + ((read_reg HI_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + ((read_reg LO_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + let result := + sub_vec (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) mul_result in + write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> + write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) + : M (unit). + +Definition execute_MOVZ (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun w__0 : mword 64 => + (if ((eq_vec w__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))) then + (rGPR rs) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_MOVN (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun w__0 : mword 64 => + (if ((neq_vec w__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))) then + (rGPR rs) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_MFLO (rd : mword 5) +: M (unit) := + + ((read_reg LO_ref) : M (mword 64)) >>= fun w__0 : bits 64 => (wGPR rd w__0) : M (unit). + +Definition execute_MFHI (rd : mword 5) +: M (unit) := + + ((read_reg HI_ref) : M (mword 64)) >>= fun w__0 : bits 64 => (wGPR rd w__0) : M (unit). + +Definition execute_MFC0 (rt : mword 5) (rd : mword 5) (sel : mword 3) (double : bool) +: M (unit) := + + (checkCP0Access tt) >> + (match (rd, sel) with + | (b__48, b__49) => + (if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg TLBIndex_ref) : M (mword 6)) >>= fun w__0 : TLBIndexT => + let idx : bits 31 := mips_zero_extend 31 w__0 in + ((read_reg TLBProbe_ref) : M (mword 1)) >>= fun w__1 : bits 1 => + returnm ((concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) (concat_vec w__1 idx)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg TLBRandom_ref) : M (mword 6)) >>= fun w__2 : TLBIndexT => + returnm ((mips_zero_extend 64 w__2) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg TLBEntryLo0_ref >>= fun w__3 : TLBEntryLoReg => + returnm ((_get_TLBEntryLoReg_bits w__3) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg TLBEntryLo1_ref >>= fun w__4 : TLBEntryLoReg => + returnm ((_get_TLBEntryLoReg_bits w__4) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg TLBContext_ref >>= fun w__5 : ContextReg => + returnm ((_get_ContextReg_bits w__5) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B1;B0] : mword 3)))) then + ((read_reg CP0UserLocal_ref) : M (mword 64)) + : M (bits 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg TLBPageMask_ref) : M (mword 16)) >>= fun w__7 : bits 16 => + returnm ((mips_zero_extend 64 + (concat_vec w__7 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg TLBWired_ref) : M (mword 6)) >>= fun w__8 : TLBIndexT => + returnm ((mips_zero_extend 64 w__8) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0HWREna_ref) : M (mword 32)) >>= fun w__9 : bits 32 => + returnm ((mips_zero_extend 64 w__9) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0BadVAddr_ref) : M (mword 64)) + : M (bits 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B1] : mword 3)))) then + ((read_reg CP0BadInstr_ref) : M (mword 32)) >>= fun w__11 : bits 32 => + returnm ((mips_zero_extend 64 w__11) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B1;B0] : mword 3)))) then + ((read_reg CP0BadInstrP_ref) : M (mword 32)) >>= fun w__12 : bits 32 => + returnm ((mips_zero_extend 64 w__12) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0Count_ref) : M (mword 32)) >>= fun w__13 : bits 32 => + returnm ((mips_zero_extend 64 w__13) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg TLBEntryHi_ref >>= fun w__14 : TLBEntryHiReg => + returnm ((_get_TLBEntryHiReg_bits w__14) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0Compare_ref) : M (mword 32)) >>= fun w__15 : bits 32 => + returnm ((mips_zero_extend 64 w__15) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg CP0Status_ref >>= fun w__16 : StatusReg => + returnm ((mips_zero_extend 64 (_get_StatusReg_bits w__16)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B0;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg CP0Cause_ref >>= fun w__17 : CauseReg => + returnm ((mips_zero_extend 64 (_get_CauseReg_bits w__17)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0EPC_ref) : M (mword 64)) + : M (bits 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + returnm ((mips_zero_extend 64 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B1;B1;B0] : mword 3)))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B1;B1;B1] : mword 3)))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0ConfigK0_ref) : M (mword 3)) >>= fun w__19 : bits 3 => + returnm ((mips_zero_extend 64 + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 15) + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec (vec_of_bits [B1;B0] : mword 2) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) w__19)))))))) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B1] : mword 3)))) then + returnm ((mips_zero_extend 64 + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec TLBIndexMax + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (bool_to_bits have_cp2) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec + (vec_of_bits [B0] : mword 1) + (vec_of_bits [B0] : mword 1)))))))))))))))) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B1;B0] : mword 3)))) then + returnm ((mips_zero_extend 64 + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (vec_of_bits [B0;B0;B0;B0] : mword 4)))))))))) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B1;B1] : mword 3)))) then + returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B1;B0;B1] : mword 3)))) then + returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B1;B1;B0] : mword 3)))) then + returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0LLAddr_ref) : M (mword 64)) + : M (bits 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg TLBXContext_ref >>= fun w__21 : XContextReg => + returnm ((_get_XContextReg_bits w__21) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B1;B1;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0ErrorEPC_ref) : M (mword 64)) + : M (bits 64) + else (SignalException ResI) : M (mword 64)) + : M (mword 64) + end) >>= fun result : bits 64 => + (wGPR rt (if (double) then result else mips_sign_extend 64 (subrange_vec_dec result 31 0))) + : M (unit). + +Definition execute_MADDU (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun mul_result : bits 64 => + ((read_reg HI_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + ((read_reg LO_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + let result := + add_vec mul_result (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) in + write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> + write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) + : M (unit). + +Definition execute_MADD (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun mul_result : bits 64 => + ((read_reg HI_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + ((read_reg LO_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + let result := + add_vec mul_result (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) in + write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> + write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) + : M (unit). + +Definition execute_Load +(width : WordType) (sign : bool) (linked : bool) (base : mword 5) (rt : mword 5) (offset : mword 16) + +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + let vAddr : bits 64 := addrWrapper (add_vec (mips_sign_extend 64 offset) w__0) LoadData width in + (if ((negb (isAddressAligned vAddr width))) then (SignalExceptionBadAddr AdEL vAddr) : M (unit) + else + (TLBTranslate vAddr LoadData) >>= fun pAddr => + (if (linked) then + write_reg CP0LLBit_ref (vec_of_bits [B1] : mword 1) >> + write_reg CP0LLAddr_ref pAddr >> + (match width with + | W => + (MEMr_reserve_wrapper pAddr 4) >>= fun w__1 : mword (8 * 4) => + returnm ((extendLoad w__1 sign) + : mword 64) + | D => + (MEMr_reserve_wrapper pAddr 8) >>= fun w__2 : mword (8 * 8) => + returnm ((extendLoad w__2 sign) + : mword 64) + | _ => (throw (Error_internal_error (tt))) : M (mword 64) + end) + : M (mword 64) + else + (match width with + | B => + (MEMr_wrapper pAddr 1) >>= fun w__5 : mword (8 * 1) => + returnm ((extendLoad w__5 sign) + : mword 64) + | H => + (MEMr_wrapper pAddr 2) >>= fun w__6 : mword (8 * 2) => + returnm ((extendLoad w__6 sign) + : mword 64) + | W => + (MEMr_wrapper pAddr 4) >>= fun w__7 : mword (8 * 4) => + returnm ((extendLoad w__7 sign) + : mword 64) + | D => + (MEMr_wrapper pAddr 8) >>= fun w__8 : mword (8 * 8) => + returnm ((extendLoad w__8 sign) + : mword 64) + end) + : M (mword 64)) >>= fun memResult : bits 64 => + (wGPR rt memResult) + : M (unit)) + : M (unit). + +Definition execute_LWR (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData WR in + (TLBTranslate vAddr LoadData) >>= fun pAddr => + (MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0] : mword 2)) 4) >>= fun mem_val => + (rGPR rt) >>= fun reg_val => + let b__4 := subrange_vec_dec vAddr 1 0 in + let result : bits 32 := + if ((eq_vec b__4 (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 31 8) (subrange_vec_dec mem_val 31 24) + else if ((eq_vec b__4 (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 31 16) (subrange_vec_dec mem_val 31 16) + else if ((eq_vec b__4 (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 31 24) (subrange_vec_dec mem_val 31 8) + else mem_val in + (wGPR rt (mips_sign_extend 64 result)) + : M (unit). + +Definition execute_LWL (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData WL in + (TLBTranslate vAddr LoadData) >>= fun pAddr => + (MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0] : mword 2)) 4) >>= fun mem_val => + (rGPR rt) >>= fun reg_val => + let b__0 := subrange_vec_dec vAddr 1 0 in + let result : bits 32 := + if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) then mem_val + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 23 0) (subrange_vec_dec reg_val 7 0) + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 15 0) (subrange_vec_dec reg_val 15 0) + else concat_vec (subrange_vec_dec mem_val 7 0) (subrange_vec_dec reg_val 23 0) in + (wGPR rt (mips_sign_extend 64 result)) + : M (unit). + +Definition execute_LUI (rt : mword 5) (imm : mword 16) +: M (unit) := + + (wGPR rt + (mips_sign_extend 64 + (concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16)))) + : M (unit). + +Definition execute_LDR (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData DR in + (TLBTranslate vAddr LoadData) >>= fun pAddr => + (MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0] : mword 3)) 8) >>= fun mem_val => + (rGPR rt) >>= fun reg_val => + let b__24 := subrange_vec_dec vAddr 2 0 in + (wGPR rt + (if ((eq_vec b__24 (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 8) (subrange_vec_dec mem_val 63 56) + else if ((eq_vec b__24 (vec_of_bits [B0;B0;B1] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 16) (subrange_vec_dec mem_val 63 48) + else if ((eq_vec b__24 (vec_of_bits [B0;B1;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 24) (subrange_vec_dec mem_val 63 40) + else if ((eq_vec b__24 (vec_of_bits [B0;B1;B1] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 32) (subrange_vec_dec mem_val 63 32) + else if ((eq_vec b__24 (vec_of_bits [B1;B0;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 40) (subrange_vec_dec mem_val 63 24) + else if ((eq_vec b__24 (vec_of_bits [B1;B0;B1] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 48) (subrange_vec_dec mem_val 63 16) + else if ((eq_vec b__24 (vec_of_bits [B1;B1;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 56) (subrange_vec_dec mem_val 63 8) + else mem_val)) + : M (unit). + +Definition execute_LDL (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData DL in + (TLBTranslate vAddr LoadData) >>= fun pAddr => + (MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0] : mword 3)) 8) >>= fun mem_val => + (rGPR rt) >>= fun reg_val => + let b__16 := subrange_vec_dec vAddr 2 0 in + (wGPR rt + (if ((eq_vec b__16 (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1)))) then mem_val + else if ((eq_vec b__16 (vec_of_bits [B0;B0;B1] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 55 0) (subrange_vec_dec reg_val 7 0) + else if ((eq_vec b__16 (vec_of_bits [B0;B1;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 47 0) (subrange_vec_dec reg_val 15 0) + else if ((eq_vec b__16 (vec_of_bits [B0;B1;B1] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 39 0) (subrange_vec_dec reg_val 23 0) + else if ((eq_vec b__16 (vec_of_bits [B1;B0;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 31 0) (subrange_vec_dec reg_val 31 0) + else if ((eq_vec b__16 (vec_of_bits [B1;B0;B1] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 23 0) (subrange_vec_dec reg_val 39 0) + else if ((eq_vec b__16 (vec_of_bits [B1;B1;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 15 0) (subrange_vec_dec reg_val 47 0) + else concat_vec (subrange_vec_dec mem_val 7 0) (subrange_vec_dec reg_val 55 0))) + : M (unit). + +Definition execute_JR (rs : mword 5) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (rGPR rs) >>= fun w__1 : mword 64 => (execute_branch w__1) : M (unit). + +Definition execute_JALR (rs : mword 5) (rd : mword 5) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (rGPR rs) >>= fun w__1 : mword 64 => + (execute_branch w__1) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + (wGPR rd (add_vec_int w__2 8)) + : M (unit). + +Definition execute_JAL (offset : mword 26) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + (execute_branch + (concat_vec (subrange_vec_dec (add_vec_int w__1 4) 63 28) + (concat_vec offset (vec_of_bits [B0;B0] : mword 2)))) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + (wGPR (vec_of_bits [B1;B1;B1;B1;B1] : mword 5) (add_vec_int w__2 8)) + : M (unit). + +Definition execute_J (offset : mword 26) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + (execute_branch + (concat_vec (subrange_vec_dec (add_vec_int w__1 4) 63 28) + (concat_vec offset (vec_of_bits [B0;B0] : mword 2)))) + : M (unit). + +Definition execute_HCF '(tt : unit) : unit := tt. + +Definition execute_ERET '(tt : unit) +: M (unit) := + + (checkCP0Access tt) >> + let '_ := (ERETHook tt) : unit in + write_reg CP0LLBit_ref (vec_of_bits [B0] : mword 1) >> + read_reg CP0Status_ref >>= fun w__0 : StatusReg => + (if ((Bool.eqb ((bits_to_bool (_get_StatusReg_ERL w__0)) : bool) ((bit_to_bool B1) : bool))) + then + ((read_reg CP0ErrorEPC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + write_reg NextPC_ref w__1 >> + (_set_StatusReg_ERL CP0Status_ref (vec_of_bits [B0] : mword 1)) + : M (unit) + else + ((read_reg CP0EPC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + write_reg NextPC_ref w__2 >> + (_set_StatusReg_EXL CP0Status_ref (vec_of_bits [B0] : mword 1)) + : M (unit)) + : M (unit). + +Definition execute_DSUBU (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (sub_vec w__0 w__1)) : M (unit). + +Definition execute_DSUB (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => + let temp65 : bits 65 := sub_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 w__1) in + (if ((neq_bool ((bit_to_bool (access_vec_dec temp65 64)) : bool) + ((bit_to_bool (access_vec_dec temp65 63)) + : bool))) then + (SignalException Ov) + : M (unit) + else (wGPR rd (subrange_vec_dec temp65 63 0)) : M (unit)) + : M (unit). + +Definition execute_DSRLV (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (rGPR rs) >>= fun w__0 : mword 64 => + let sa := subrange_vec_dec w__0 5 0 in + (shift_bits_right temp sa) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit). + +Definition execute_DSRL32 (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + let sa32 := concat_vec (vec_of_bits [B1] : mword 1) sa in + (shift_bits_right temp sa32) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit). + +Definition execute_DSRL (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (shift_bits_right temp sa) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit). + +Definition execute_DSRAV (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (rGPR rs) >>= fun w__0 : mword 64 => + let sa := subrange_vec_dec w__0 5 0 in + (shift_bits_right_arith temp sa) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit). + +Definition execute_DSRA32 (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + let sa32 := concat_vec (vec_of_bits [B1] : mword 1) sa in + (shift_bits_right_arith temp sa32) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit). + +Definition execute_DSRA (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (shift_bits_right_arith temp sa) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit). + +Definition execute_DSLLV (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun w__0 : mword 64 => + (rGPR rs) >>= fun w__1 : mword 64 => + (shift_bits_left w__0 (subrange_vec_dec w__1 5 0)) >>= fun w__2 : mword 64 => + (wGPR rd w__2) + : M (unit). + +Definition execute_DSLL32 (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun w__0 : mword 64 => + (shift_bits_left w__0 (concat_vec (vec_of_bits [B1] : mword 1) sa)) >>= fun w__1 : mword 64 => + (wGPR rd w__1) + : M (unit). + +Definition execute_DSLL (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun w__0 : mword 64 => + (shift_bits_left w__0 sa) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit). + +Definition execute_DMULTU (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => + let result := mult_vec w__0 w__1 in + write_reg HI_ref (subrange_vec_dec result 127 64) >> + write_reg LO_ref (subrange_vec_dec result 63 0) + : M (unit). + +Definition execute_DMULT (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => + let result := mults_vec w__0 w__1 in + write_reg HI_ref (subrange_vec_dec result 127 64) >> + write_reg LO_ref (subrange_vec_dec result 63 0) + : M (unit). + +Definition execute_DIVU (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) + (orb (NotWordVal rtVal) + (eq_vec rtVal + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))))) then + (undefined_bitvector 32) >>= fun w__0 : mword 32 => + (undefined_bitvector 32) >>= fun w__1 : mword 32 => returnm (w__0 : bits 32, w__1 : bits 32) + else + let 'si := projT1 (uint (subrange_vec_dec rsVal 31 0)) in + let 'ti := projT1 (uint (subrange_vec_dec rtVal 31 0)) in + let qi := Z.quot si ti in + let ri := Z.rem si ti in + returnm (to_bits 32 qi, to_bits 32 ri)) >>= fun '(q, r) => + write_reg HI_ref (mips_sign_extend 64 r) >> write_reg LO_ref (mips_sign_extend 64 q) : M (unit). + +Definition execute_DIV (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) + (orb (NotWordVal rtVal) + (eq_vec rtVal + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))))) then + (undefined_bitvector 32) >>= fun w__0 : mword 32 => + (undefined_bitvector 32) >>= fun w__1 : mword 32 => returnm (w__0 : bits 32, w__1 : bits 32) + else + let 'si := projT1 (sint (subrange_vec_dec rsVal 31 0)) in + let 'ti := projT1 (sint (subrange_vec_dec rtVal 31 0)) in + let qi := Z.quot si ti in + let ri := Z.sub si (Z.mul ti qi) in + returnm (to_bits 32 qi, to_bits 32 ri)) >>= fun '(q, r) => + write_reg HI_ref (mips_sign_extend 64 r) >> write_reg LO_ref (mips_sign_extend 64 q) : M (unit). + +Definition execute_DDIVU (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + let 'rsVal := projT1 (uint w__0) in + (rGPR rt) >>= fun w__1 : mword 64 => + let 'rtVal := projT1 (uint w__1) in + (if sumbool_of_bool ((Z.eqb rtVal 0)) then + (undefined_bitvector 64) >>= fun w__2 : mword 64 => + (undefined_bitvector 64) >>= fun w__3 : mword 64 => returnm (w__2 : bits 64, w__3 : bits 64) + else + let qi := Z.quot rsVal rtVal in + let ri := Z.rem rsVal rtVal in + returnm (to_bits 64 qi, to_bits 64 ri)) >>= fun '(q, r) => + write_reg LO_ref q >> write_reg HI_ref r : M (unit). + +Definition execute_DDIV (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + let 'rsVal := projT1 (sint w__0) in + (rGPR rt) >>= fun w__1 : mword 64 => + let 'rtVal := projT1 (sint w__1) in + (if sumbool_of_bool ((Z.eqb rtVal 0)) then + (undefined_bitvector 64) >>= fun w__2 : mword 64 => + (undefined_bitvector 64) >>= fun w__3 : mword 64 => returnm (w__2 : bits 64, w__3 : bits 64) + else + let qi := Z.quot rsVal rtVal in + let ri := Z.sub rsVal (Z.mul qi rtVal) in + returnm (to_bits 64 qi, to_bits 64 ri)) >>= fun '(q, r) => + write_reg LO_ref q >> write_reg HI_ref r : M (unit). + +Definition execute_DADDU (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (add_vec w__0 w__1)) : M (unit). + +Definition execute_DADDIU (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (wGPR rt (add_vec w__0 (mips_sign_extend 64 imm))) + : M (unit). + +Definition execute_DADDI (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + let sum65 : bits 65 := add_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 imm) in + (if ((neq_bool ((bit_to_bool (access_vec_dec sum65 64)) : bool) + ((bit_to_bool (access_vec_dec sum65 63)) + : bool))) then + (SignalException Ov) + : M (unit) + else (wGPR rt (subrange_vec_dec sum65 63 0)) : M (unit)) + : M (unit). + +Definition execute_DADD (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => + let sum65 : bits 65 := add_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 w__1) in + (if ((neq_bool ((bit_to_bool (access_vec_dec sum65 64)) : bool) + ((bit_to_bool (access_vec_dec sum65 63)) + : bool))) then + (SignalException Ov) + : M (unit) + else (wGPR rd (subrange_vec_dec sum65 63 0)) : M (unit)) + : M (unit). + +Definition execute_CACHE (base : mword 5) (op : mword 5) (imm : mword 16) +: M (unit) := + + (checkCP0Access tt) + : M (unit). + +Definition execute_BREAK '(tt : unit) : M (unit) := (SignalException Bp) : M (unit). + +Definition execute_BEQ (rs : mword 5) (rd : mword 5) (imm : mword 16) (ne : bool) (likely : bool) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (rGPR rs) >>= fun w__1 : mword 64 => + (rGPR rd) >>= fun w__2 : mword 64 => + (if (((bits_to_bool (xor_vec (bool_to_bits (eq_vec w__1 w__2)) ((bool_to_bits ne) : mword 1))) + : bool)) then + let offset : bits 64 := + add_vec_int (mips_sign_extend 64 (concat_vec imm (vec_of_bits [B0;B0] : mword 2))) 4 in + ((read_reg PC_ref) : M (mword 64)) >>= fun w__3 : bits 64 => + (execute_branch (add_vec w__3 offset)) + : M (unit) + else if (likely) then + ((read_reg PC_ref) : M (mword 64)) >>= fun w__4 : bits 64 => + write_reg NextPC_ref (add_vec_int w__4 8) + : M (unit) + else write_reg NextInBranchDelay_ref (vec_of_bits [B1] : mword 1) : M (unit)) + : M (unit). + +Definition execute_BCMPZ +(rs : mword 5) (imm : mword 16) (cmp : Comparison) (link : bool) (likely : bool) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + let linkVal := add_vec_int w__1 8 in + (rGPR rs) >>= fun regVal => + let condition := compare cmp regVal (mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) in + (if (condition) then + let offset : bits 64 := + add_vec_int (mips_sign_extend 64 (concat_vec imm (vec_of_bits [B0;B0] : mword 2))) 4 in + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + (execute_branch (add_vec w__2 offset)) + : M (unit) + else if (likely) then + ((read_reg PC_ref) : M (mword 64)) >>= fun w__3 : bits 64 => + write_reg NextPC_ref (add_vec_int w__3 8) + : M (unit) + else write_reg NextInBranchDelay_ref (vec_of_bits [B1] : mword 1) : M (unit)) >> + (if (link) then (wGPR (vec_of_bits [B1;B1;B1;B1;B1] : mword 5) linkVal) : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_ANDI (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (wGPR rt (and_vec w__0 (mips_zero_extend 64 imm))) + : M (unit). + +Definition execute_AND (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (and_vec w__0 w__1)) : M (unit). + +Definition execute_ADDU (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun opA => + (rGPR rt) >>= fun opB => + (if ((orb (NotWordVal opA) (NotWordVal opB))) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) + else + (wGPR rd + (mips_sign_extend 64 (add_vec (subrange_vec_dec opA 31 0) (subrange_vec_dec opB 31 0)))) + : M (unit)) + : M (unit). + +Definition execute_ADDIU (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun opA => + (if ((NotWordVal opA)) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rt w__0) : M (unit) + else + (wGPR rt (mips_sign_extend 64 (add_vec (subrange_vec_dec opA 31 0) (mips_sign_extend 32 imm)))) + : M (unit)) + : M (unit). + +Definition execute_ADDI (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun opA => + (if ((NotWordVal opA)) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rt w__0) : M (unit) + else + let sum33 : bits 33 := + add_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0)) (mips_sign_extend 33 imm) in + (if ((neq_bool ((bit_to_bool (access_vec_dec sum33 32)) : bool) + ((bit_to_bool (access_vec_dec sum33 31)) + : bool))) then + (SignalException Ov) + : M (unit) + else (wGPR rt (mips_sign_extend 64 (subrange_vec_dec sum33 31 0))) : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_ADD (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun opA : bits 64 => + (rGPR rt) >>= fun opB : bits 64 => + (if ((orb (NotWordVal opA) (NotWordVal opB))) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) + else + let sum33 : bits 33 := + add_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0)) + (mips_sign_extend 33 (subrange_vec_dec opB 31 0)) in + (if ((neq_bool ((bit_to_bool (access_vec_dec sum33 32)) : bool) + ((bit_to_bool (access_vec_dec sum33 31)) + : bool))) then + (SignalException Ov) + : M (unit) + else (wGPR rd (mips_sign_extend 64 (subrange_vec_dec sum33 31 0))) : M (unit)) + : M (unit)) + : M (unit). + +Definition execute (merge_var : ast) +: M (unit) := + + (match merge_var with + | DADDIU (rs,rt,imm) => (execute_DADDIU rs rt imm) : M (unit) + | DADDU (rs,rt,rd) => (execute_DADDU rs rt rd) : M (unit) + | DADDI (rs,rt,imm) => (execute_DADDI rs rt imm) : M (unit) + | DADD (rs,rt,rd) => (execute_DADD rs rt rd) : M (unit) + | ADD (rs,rt,rd) => (execute_ADD rs rt rd) : M (unit) + | ADDI (rs,rt,imm) => (execute_ADDI rs rt imm) : M (unit) + | ADDU (rs,rt,rd) => (execute_ADDU rs rt rd) : M (unit) + | ADDIU (rs,rt,imm) => (execute_ADDIU rs rt imm) : M (unit) + | DSUBU (rs,rt,rd) => (execute_DSUBU rs rt rd) : M (unit) + | DSUB (rs,rt,rd) => (execute_DSUB rs rt rd) : M (unit) + | SUB (rs,rt,rd) => (execute_SUB rs rt rd) : M (unit) + | SUBU (rs,rt,rd) => (execute_SUBU rs rt rd) : M (unit) + | AND (rs,rt,rd) => (execute_AND rs rt rd) : M (unit) + | ANDI (rs,rt,imm) => (execute_ANDI rs rt imm) : M (unit) + | OR (rs,rt,rd) => (execute_OR rs rt rd) : M (unit) + | ORI (rs,rt,imm) => (execute_ORI rs rt imm) : M (unit) + | NOR (rs,rt,rd) => (execute_NOR rs rt rd) : M (unit) + | XOR (rs,rt,rd) => (execute_XOR rs rt rd) : M (unit) + | XORI (rs,rt,imm) => (execute_XORI rs rt imm) : M (unit) + | LUI (rt,imm) => (execute_LUI rt imm) : M (unit) + | DSLL (rt,rd,sa) => (execute_DSLL rt rd sa) : M (unit) + | DSLL32 (rt,rd,sa) => (execute_DSLL32 rt rd sa) : M (unit) + | DSLLV (rs,rt,rd) => (execute_DSLLV rs rt rd) : M (unit) + | DSRA (rt,rd,sa) => (execute_DSRA rt rd sa) : M (unit) + | DSRA32 (rt,rd,sa) => (execute_DSRA32 rt rd sa) : M (unit) + | DSRAV (rs,rt,rd) => (execute_DSRAV rs rt rd) : M (unit) + | DSRL (rt,rd,sa) => (execute_DSRL rt rd sa) : M (unit) + | DSRL32 (rt,rd,sa) => (execute_DSRL32 rt rd sa) : M (unit) + | DSRLV (rs,rt,rd) => (execute_DSRLV rs rt rd) : M (unit) + | SLL (rt,rd,sa) => (execute_SLL rt rd sa) : M (unit) + | SLLV (rs,rt,rd) => (execute_SLLV rs rt rd) : M (unit) + | SRA (rt,rd,sa) => (execute_SRA rt rd sa) : M (unit) + | SRAV (rs,rt,rd) => (execute_SRAV rs rt rd) : M (unit) + | SRL (rt,rd,sa) => (execute_SRL rt rd sa) : M (unit) + | SRLV (rs,rt,rd) => (execute_SRLV rs rt rd) : M (unit) + | SLT (rs,rt,rd) => (execute_SLT rs rt rd) : M (unit) + | SLTI (rs,rt,imm) => (execute_SLTI rs rt imm) : M (unit) + | SLTU (rs,rt,rd) => (execute_SLTU rs rt rd) : M (unit) + | SLTIU (rs,rt,imm) => (execute_SLTIU rs rt imm) : M (unit) + | MOVN (rs,rt,rd) => (execute_MOVN rs rt rd) : M (unit) + | MOVZ (rs,rt,rd) => (execute_MOVZ rs rt rd) : M (unit) + | MFHI (rd) => (execute_MFHI rd) : M (unit) + | MFLO (rd) => (execute_MFLO rd) : M (unit) + | MTHI (rs) => (execute_MTHI rs) : M (unit) + | MTLO (rs) => (execute_MTLO rs) : M (unit) + | MUL (rs,rt,rd) => (execute_MUL rs rt rd) : M (unit) + | MULT (rs,rt) => (execute_MULT rs rt) : M (unit) + | MULTU (rs,rt) => (execute_MULTU rs rt) : M (unit) + | DMULT (rs,rt) => (execute_DMULT rs rt) : M (unit) + | DMULTU (rs,rt) => (execute_DMULTU rs rt) : M (unit) + | MADD (rs,rt) => (execute_MADD rs rt) : M (unit) + | MADDU (rs,rt) => (execute_MADDU rs rt) : M (unit) + | MSUB (rs,rt) => (execute_MSUB rs rt) : M (unit) + | MSUBU (rs,rt) => (execute_MSUBU rs rt) : M (unit) + | DIV (rs,rt) => (execute_DIV rs rt) : M (unit) + | DIVU (rs,rt) => (execute_DIVU rs rt) : M (unit) + | DDIV (rs,rt) => (execute_DDIV rs rt) : M (unit) + | DDIVU (rs,rt) => (execute_DDIVU rs rt) : M (unit) + | J (offset) => (execute_J offset) : M (unit) + | JAL (offset) => (execute_JAL offset) : M (unit) + | JR (rs) => (execute_JR rs) : M (unit) + | JALR (rs,rd) => (execute_JALR rs rd) : M (unit) + | BEQ (rs,rd,imm,ne,likely) => (execute_BEQ rs rd imm ne likely) : M (unit) + | BCMPZ (rs,imm,cmp,link,likely) => (execute_BCMPZ rs imm cmp link likely) : M (unit) + | SYSCALL (arg0) => (execute_SYSCALL arg0) : M (unit) + | BREAK (arg0) => (execute_BREAK arg0) : M (unit) + | WAIT (arg0) => (execute_WAIT arg0) : M (unit) + | TRAPREG (rs,rt,cmp) => (execute_TRAPREG rs rt cmp) : M (unit) + | TRAPIMM (rs,imm,cmp) => (execute_TRAPIMM rs imm cmp) : M (unit) + | Load (width,sign,linked,base,rt,offset) => + (execute_Load width sign linked base rt offset) : M (unit) + | Store (width,conditional,base,rt,offset) => + (execute_Store width conditional base rt offset) : M (unit) + | LWL (base,rt,offset) => (execute_LWL base rt offset) : M (unit) + | LWR (base,rt,offset) => (execute_LWR base rt offset) : M (unit) + | SWL (base,rt,offset) => (execute_SWL base rt offset) : M (unit) + | SWR (base,rt,offset) => (execute_SWR base rt offset) : M (unit) + | LDL (base,rt,offset) => (execute_LDL base rt offset) : M (unit) + | LDR (base,rt,offset) => (execute_LDR base rt offset) : M (unit) + | SDL (base,rt,offset) => (execute_SDL base rt offset) : M (unit) + | SDR (base,rt,offset) => (execute_SDR base rt offset) : M (unit) + | CACHE (base,op,imm) => (execute_CACHE base op imm) : M (unit) + | SYNC (arg0) => (execute_SYNC arg0) : M (unit) + | MFC0 (rt,rd,sel,double) => (execute_MFC0 rt rd sel double) : M (unit) + | HCF (arg0) => returnm ((execute_HCF arg0) : unit) + | MTC0 (rt,rd,sel,double) => (execute_MTC0 rt rd sel double) : M (unit) + | TLBWI (arg0) => (execute_TLBWI arg0) : M (unit) + | TLBWR (arg0) => (execute_TLBWR arg0) : M (unit) + | TLBR (arg0) => (execute_TLBR arg0) : M (unit) + | TLBP (arg0) => (execute_TLBP arg0) : M (unit) + | RDHWR (rt,rd) => (execute_RDHWR rt rd) : M (unit) + | ERET (arg0) => (execute_ERET arg0) : M (unit) + | RI (arg0) => (execute_RI arg0) : M (unit) + end) + : M (unit). + +Definition supported_instructions (instr : ast) : option ast := Some (instr). + +Definition initialize_registers '(tt : unit) +: M (unit) := + + (undefined_bitvector 64) >>= fun w__0 : mword 64 => + write_reg PC_ref w__0 >> + (undefined_bitvector 64) >>= fun w__1 : mword 64 => + write_reg NextPC_ref w__1 >> + (undefined_bitvector 1) >>= fun w__2 : mword 1 => + write_reg TLBProbe_ref w__2 >> + (undefined_bitvector 6) >>= fun w__3 : mword 6 => + write_reg TLBIndex_ref w__3 >> + (undefined_bitvector 6) >>= fun w__4 : mword 6 => + write_reg TLBRandom_ref w__4 >> + (undefined_TLBEntryLoReg tt) >>= fun w__5 : TLBEntryLoReg => + write_reg TLBEntryLo0_ref w__5 >> + (undefined_TLBEntryLoReg tt) >>= fun w__6 : TLBEntryLoReg => + write_reg TLBEntryLo1_ref w__6 >> + (undefined_ContextReg tt) >>= fun w__7 : ContextReg => + write_reg TLBContext_ref w__7 >> + (undefined_bitvector 16) >>= fun w__8 : mword 16 => + write_reg TLBPageMask_ref w__8 >> + (undefined_bitvector 6) >>= fun w__9 : mword 6 => + write_reg TLBWired_ref w__9 >> + (undefined_TLBEntryHiReg tt) >>= fun w__10 : TLBEntryHiReg => + write_reg TLBEntryHi_ref w__10 >> + (undefined_XContextReg tt) >>= fun w__11 : XContextReg => + write_reg TLBXContext_ref w__11 >> + (undefined_TLBEntry tt) >>= fun w__12 : TLBEntry => + write_reg TLBEntry00_ref w__12 >> + (undefined_TLBEntry tt) >>= fun w__13 : TLBEntry => + write_reg TLBEntry01_ref w__13 >> + (undefined_TLBEntry tt) >>= fun w__14 : TLBEntry => + write_reg TLBEntry02_ref w__14 >> + (undefined_TLBEntry tt) >>= fun w__15 : TLBEntry => + write_reg TLBEntry03_ref w__15 >> + (undefined_TLBEntry tt) >>= fun w__16 : TLBEntry => + write_reg TLBEntry04_ref w__16 >> + (undefined_TLBEntry tt) >>= fun w__17 : TLBEntry => + write_reg TLBEntry05_ref w__17 >> + (undefined_TLBEntry tt) >>= fun w__18 : TLBEntry => + write_reg TLBEntry06_ref w__18 >> + (undefined_TLBEntry tt) >>= fun w__19 : TLBEntry => + write_reg TLBEntry07_ref w__19 >> + (undefined_TLBEntry tt) >>= fun w__20 : TLBEntry => + write_reg TLBEntry08_ref w__20 >> + (undefined_TLBEntry tt) >>= fun w__21 : TLBEntry => + write_reg TLBEntry09_ref w__21 >> + (undefined_TLBEntry tt) >>= fun w__22 : TLBEntry => + write_reg TLBEntry10_ref w__22 >> + (undefined_TLBEntry tt) >>= fun w__23 : TLBEntry => + write_reg TLBEntry11_ref w__23 >> + (undefined_TLBEntry tt) >>= fun w__24 : TLBEntry => + write_reg TLBEntry12_ref w__24 >> + (undefined_TLBEntry tt) >>= fun w__25 : TLBEntry => + write_reg TLBEntry13_ref w__25 >> + (undefined_TLBEntry tt) >>= fun w__26 : TLBEntry => + write_reg TLBEntry14_ref w__26 >> + (undefined_TLBEntry tt) >>= fun w__27 : TLBEntry => + write_reg TLBEntry15_ref w__27 >> + (undefined_TLBEntry tt) >>= fun w__28 : TLBEntry => + write_reg TLBEntry16_ref w__28 >> + (undefined_TLBEntry tt) >>= fun w__29 : TLBEntry => + write_reg TLBEntry17_ref w__29 >> + (undefined_TLBEntry tt) >>= fun w__30 : TLBEntry => + write_reg TLBEntry18_ref w__30 >> + (undefined_TLBEntry tt) >>= fun w__31 : TLBEntry => + write_reg TLBEntry19_ref w__31 >> + (undefined_TLBEntry tt) >>= fun w__32 : TLBEntry => + write_reg TLBEntry20_ref w__32 >> + (undefined_TLBEntry tt) >>= fun w__33 : TLBEntry => + write_reg TLBEntry21_ref w__33 >> + (undefined_TLBEntry tt) >>= fun w__34 : TLBEntry => + write_reg TLBEntry22_ref w__34 >> + (undefined_TLBEntry tt) >>= fun w__35 : TLBEntry => + write_reg TLBEntry23_ref w__35 >> + (undefined_TLBEntry tt) >>= fun w__36 : TLBEntry => + write_reg TLBEntry24_ref w__36 >> + (undefined_TLBEntry tt) >>= fun w__37 : TLBEntry => + write_reg TLBEntry25_ref w__37 >> + (undefined_TLBEntry tt) >>= fun w__38 : TLBEntry => + write_reg TLBEntry26_ref w__38 >> + (undefined_TLBEntry tt) >>= fun w__39 : TLBEntry => + write_reg TLBEntry27_ref w__39 >> + (undefined_TLBEntry tt) >>= fun w__40 : TLBEntry => + write_reg TLBEntry28_ref w__40 >> + (undefined_TLBEntry tt) >>= fun w__41 : TLBEntry => + write_reg TLBEntry29_ref w__41 >> + (undefined_TLBEntry tt) >>= fun w__42 : TLBEntry => + write_reg TLBEntry30_ref w__42 >> + (undefined_TLBEntry tt) >>= fun w__43 : TLBEntry => + write_reg TLBEntry31_ref w__43 >> + (undefined_TLBEntry tt) >>= fun w__44 : TLBEntry => + write_reg TLBEntry32_ref w__44 >> + (undefined_TLBEntry tt) >>= fun w__45 : TLBEntry => + write_reg TLBEntry33_ref w__45 >> + (undefined_TLBEntry tt) >>= fun w__46 : TLBEntry => + write_reg TLBEntry34_ref w__46 >> + (undefined_TLBEntry tt) >>= fun w__47 : TLBEntry => + write_reg TLBEntry35_ref w__47 >> + (undefined_TLBEntry tt) >>= fun w__48 : TLBEntry => + write_reg TLBEntry36_ref w__48 >> + (undefined_TLBEntry tt) >>= fun w__49 : TLBEntry => + write_reg TLBEntry37_ref w__49 >> + (undefined_TLBEntry tt) >>= fun w__50 : TLBEntry => + write_reg TLBEntry38_ref w__50 >> + (undefined_TLBEntry tt) >>= fun w__51 : TLBEntry => + write_reg TLBEntry39_ref w__51 >> + (undefined_TLBEntry tt) >>= fun w__52 : TLBEntry => + write_reg TLBEntry40_ref w__52 >> + (undefined_TLBEntry tt) >>= fun w__53 : TLBEntry => + write_reg TLBEntry41_ref w__53 >> + (undefined_TLBEntry tt) >>= fun w__54 : TLBEntry => + write_reg TLBEntry42_ref w__54 >> + (undefined_TLBEntry tt) >>= fun w__55 : TLBEntry => + write_reg TLBEntry43_ref w__55 >> + (undefined_TLBEntry tt) >>= fun w__56 : TLBEntry => + write_reg TLBEntry44_ref w__56 >> + (undefined_TLBEntry tt) >>= fun w__57 : TLBEntry => + write_reg TLBEntry45_ref w__57 >> + (undefined_TLBEntry tt) >>= fun w__58 : TLBEntry => + write_reg TLBEntry46_ref w__58 >> + (undefined_TLBEntry tt) >>= fun w__59 : TLBEntry => + write_reg TLBEntry47_ref w__59 >> + (undefined_TLBEntry tt) >>= fun w__60 : TLBEntry => + write_reg TLBEntry48_ref w__60 >> + (undefined_TLBEntry tt) >>= fun w__61 : TLBEntry => + write_reg TLBEntry49_ref w__61 >> + (undefined_TLBEntry tt) >>= fun w__62 : TLBEntry => + write_reg TLBEntry50_ref w__62 >> + (undefined_TLBEntry tt) >>= fun w__63 : TLBEntry => + write_reg TLBEntry51_ref w__63 >> + (undefined_TLBEntry tt) >>= fun w__64 : TLBEntry => + write_reg TLBEntry52_ref w__64 >> + (undefined_TLBEntry tt) >>= fun w__65 : TLBEntry => + write_reg TLBEntry53_ref w__65 >> + (undefined_TLBEntry tt) >>= fun w__66 : TLBEntry => + write_reg TLBEntry54_ref w__66 >> + (undefined_TLBEntry tt) >>= fun w__67 : TLBEntry => + write_reg TLBEntry55_ref w__67 >> + (undefined_TLBEntry tt) >>= fun w__68 : TLBEntry => + write_reg TLBEntry56_ref w__68 >> + (undefined_TLBEntry tt) >>= fun w__69 : TLBEntry => + write_reg TLBEntry57_ref w__69 >> + (undefined_TLBEntry tt) >>= fun w__70 : TLBEntry => + write_reg TLBEntry58_ref w__70 >> + (undefined_TLBEntry tt) >>= fun w__71 : TLBEntry => + write_reg TLBEntry59_ref w__71 >> + (undefined_TLBEntry tt) >>= fun w__72 : TLBEntry => + write_reg TLBEntry60_ref w__72 >> + (undefined_TLBEntry tt) >>= fun w__73 : TLBEntry => + write_reg TLBEntry61_ref w__73 >> + (undefined_TLBEntry tt) >>= fun w__74 : TLBEntry => + write_reg TLBEntry62_ref w__74 >> + (undefined_TLBEntry tt) >>= fun w__75 : TLBEntry => + write_reg TLBEntry63_ref w__75 >> + (undefined_bitvector 32) >>= fun w__76 : mword 32 => + write_reg CP0Compare_ref w__76 >> + (undefined_CauseReg tt) >>= fun w__77 : CauseReg => + write_reg CP0Cause_ref w__77 >> + (undefined_bitvector 64) >>= fun w__78 : mword 64 => + write_reg CP0EPC_ref w__78 >> + (undefined_bitvector 64) >>= fun w__79 : mword 64 => + write_reg CP0ErrorEPC_ref w__79 >> + (undefined_bitvector 1) >>= fun w__80 : mword 1 => + write_reg CP0LLBit_ref w__80 >> + (undefined_bitvector 64) >>= fun w__81 : mword 64 => + write_reg CP0LLAddr_ref w__81 >> + (undefined_bitvector 64) >>= fun w__82 : mword 64 => + write_reg CP0BadVAddr_ref w__82 >> + (undefined_bitvector 32) >>= fun w__83 : mword 32 => + write_reg CurrentInstrBits_ref w__83 >> + (undefined_bitvector 32) >>= fun w__84 : mword 32 => + write_reg LastInstrBits_ref w__84 >> + (undefined_bitvector 32) >>= fun w__85 : mword 32 => + write_reg CP0BadInstr_ref w__85 >> + (undefined_bitvector 32) >>= fun w__86 : mword 32 => + write_reg CP0BadInstrP_ref w__86 >> + (undefined_bitvector 32) >>= fun w__87 : mword 32 => + write_reg CP0Count_ref w__87 >> + (undefined_bitvector 32) >>= fun w__88 : mword 32 => + write_reg CP0HWREna_ref w__88 >> + (undefined_bitvector 64) >>= fun w__89 : mword 64 => + write_reg CP0UserLocal_ref w__89 >> + (undefined_bitvector 3) >>= fun w__90 : mword 3 => + write_reg CP0ConfigK0_ref w__90 >> + (undefined_StatusReg tt) >>= fun w__91 : StatusReg => + write_reg CP0Status_ref w__91 >> + (undefined_bitvector 1) >>= fun w__92 : mword 1 => + write_reg NextInBranchDelay_ref w__92 >> + (undefined_bitvector 1) >>= fun w__93 : mword 1 => + write_reg InBranchDelay_ref w__93 >> + (undefined_bitvector 1) >>= fun w__94 : mword 1 => + write_reg BranchPending_ref w__94 >> + (undefined_bitvector 64) >>= fun w__95 : mword 64 => + write_reg DelayedPC_ref w__95 >> + (undefined_bitvector 64) >>= fun w__96 : mword 64 => + write_reg HI_ref w__96 >> + (undefined_bitvector 64) >>= fun w__97 : mword 64 => + write_reg LO_ref w__97 >> + (undefined_bitvector 64) >>= fun w__98 : mword 64 => + (undefined_vector 32 w__98) >>= fun w__99 : vec (mword 64) 32 => + write_reg GPR_ref w__99 >> + (undefined_bitvector 8) >>= fun w__100 : mword 8 => + write_reg UART_WDATA_ref w__100 >> + (undefined_bitvector 1) >>= fun w__101 : mword 1 => + write_reg UART_WRITTEN_ref w__101 >> + (undefined_bitvector 8) >>= fun w__102 : mword 8 => + write_reg UART_RDATA_ref w__102 >> + (undefined_bitvector 1) >>= fun w__103 : mword 1 => write_reg UART_RVALID_ref w__103 : M (unit). + +Definition initial_regstate : regstate := +{| UART_RVALID := (vec_of_bits [B0] : mword 1); + UART_RDATA := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + UART_WRITTEN := (vec_of_bits [B0] : mword 1); + UART_WDATA := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + GPR := + (vec_of_list_len [(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64)]); + LO := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + HI := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + DelayedPC := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + BranchPending := (vec_of_bits [B0] : mword 1); + InBranchDelay := (vec_of_bits [B0] : mword 1); + NextInBranchDelay := (vec_of_bits [B0] : mword 1); + CP0Status := + ({| StatusReg_StatusReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) |}); + CP0ConfigK0 := (vec_of_bits [B0;B0;B0] : mword 3); + CP0UserLocal := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + CP0HWREna := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + CP0Count := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + CP0BadInstrP := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + CP0BadInstr := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + LastInstrBits := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + CurrentInstrBits := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + CP0BadVAddr := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + CP0LLAddr := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + CP0LLBit := (vec_of_bits [B0] : mword 1); + CP0ErrorEPC := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + CP0EPC := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + CP0Cause := + ({| CauseReg_CauseReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) |}); + CP0Compare := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + TLBEntry63 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry62 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry61 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry60 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry59 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry58 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry57 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry56 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry55 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry54 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry53 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry52 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry51 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry50 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry49 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry48 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry47 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry46 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry45 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry44 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry43 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry42 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry41 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry40 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry39 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry38 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry37 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry36 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry35 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry34 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry33 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry32 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry31 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry30 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry29 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry28 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry27 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry26 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry25 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry24 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry23 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry22 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry21 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry20 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry19 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry18 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry17 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry16 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry15 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry14 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry13 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry12 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry11 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry10 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry09 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry08 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry07 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry06 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry05 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry04 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry03 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry02 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry01 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry00 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBXContext := + ({| XContextReg_XContextReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntryHi := + ({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBWired := (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6); + TLBPageMask := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + TLBContext := + ({| ContextReg_ContextReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntryLo1 := + ({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntryLo0 := + ({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBRandom := (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6); + TLBIndex := (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6); + TLBProbe := (vec_of_bits [B0] : mword 1); + NextPC := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + PC := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}. +Hint Unfold initial_regstate : sail. + +End Content. diff --git a/snapshots/coq/cheri-mips/mips_extras.v b/snapshots/coq/cheri-mips/mips_extras.v new file mode 100644 index 00000000..cdb9956d --- /dev/null +++ b/snapshots/coq/cheri-mips/mips_extras.v @@ -0,0 +1,191 @@ +Require Import Sail2_instr_kinds. +Require Import Sail2_values. +Require Import Sail2_operators_mwords. +Require Import Sail2_prompt_monad. +Require Import Sail2_prompt. +Require Import String. +Require Import List. +Import List.ListNotations. +(* +val MEMr : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e +val MEMr_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e +val MEMr_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e +val MEMr_tag_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e +*) +Definition MEMr {regval a b e} `{ArithFact (b >= 0)} (addr : mword a) size : monad regval (mword b) e := read_mem Read_plain addr size. +Definition MEMr_reserve {regval a b e} `{ArithFact (b >= 0)} (addr : mword a) size : monad regval (mword b) e := read_mem Read_reserve addr size. + +(*val read_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> monad 'regval bool 'e*) +Definition read_tag_bool {regval a e} (addr : mword a) : monad regval bool e := + read_tag addr >>= fun t => + maybe_fail "read_tag_bool" (bool_of_bitU t). + +(*val write_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> bool -> monad 'regval unit 'e*) +Definition write_tag_bool {regval a e} (addr : mword a) t : monad regval unit e := + write_tag addr (bitU_of_bool t) >>= fun _ => returnm tt. + +Definition MEMr_tag {regval a b e} `{ArithFact (b >= 0)} (addr : mword a) size : monad regval (bool * mword b) e := + read_mem Read_plain addr size >>= fun v => + read_tag_bool addr >>= fun t => + returnm (t, v). + +Definition MEMr_tag_reserve {regval a b e} `{ArithFact (b >= 0)} (addr : mword a) size : monad regval (bool * mword b) e := + read_mem Read_plain addr size >>= fun v => + read_tag_bool addr >>= fun t => + returnm (t, v). + +(* +val MEMea : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e +val MEMea_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e +val MEMea_tag : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e +val MEMea_tag_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e +*) +Definition MEMea {regval a e} (addr : mword a) size : monad regval unit e := write_mem_ea Write_plain addr size. +Definition MEMea_conditional {regval a e} (addr : mword a) size : monad regval unit e := write_mem_ea Write_conditional addr size. + +Definition MEMea_tag {regval a e} (addr : mword a) size : monad regval unit e := write_mem_ea Write_plain addr size. +Definition MEMea_tag_conditional {regval a e} (addr : mword a) size : monad regval unit e := write_mem_ea Write_conditional addr size. + +(* +val MEMval : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval unit 'e +val MEMval_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval bool 'e +val MEMval_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval unit 'e +val MEMval_tag_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval bool 'e +*) +Definition MEMval {regval a b e} (_ : mword a) (size : Z) (v : mword b) : monad regval unit e := write_mem_val v >>= fun _ => returnm tt. +Definition MEMval_conditional {regval a b e} (_ : mword a) (size : Z) (v : mword b) : monad regval bool e := write_mem_val v >>= fun b => returnm (if b then true else false). +Definition MEMval_tag {regval a b e} (addr : mword a) (size : Z) t (v : mword b) : monad regval unit e := write_mem_val v >>= fun _ => write_tag_bool addr t >>= fun _ => returnm tt. +Definition MEMval_tag_conditional {regval a b e} (addr : mword a) (size : Z) t (v : mword b) : monad regval bool e := write_mem_val v >>= fun b => write_tag_bool addr t >>= fun _ => returnm (if b then true else false). + +(*val MEM_sync : forall 'regval 'e. unit -> monad 'regval unit 'e*) + +Definition MEM_sync {regval e} (_:unit) : monad regval unit e := barrier Barrier_MIPS_SYNC. + +(* Some wrappers copied from aarch64_extras *) +(* TODO: Harmonise into a common library *) +(* +Definition get_slice_int_bl len n lo := + (* TODO: Is this the intended behaviour? *) + let hi := lo + len - 1 in + let bs := bools_of_int (hi + 1) n in + subrange_list false bs hi lo + +val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a +Definition get_slice_int len n lo := of_bools (get_slice_int_bl len n lo) +*) +Definition write_ram {rv e} m size (_ : mword m) (addr : mword m) (data : mword (8 * size)) : monad rv unit e := + MEMea addr size >> + MEMval addr size data. + +Definition read_ram {rv e} m size `{ArithFact (size >= 0)} (_ : mword m) (addr : mword m) : monad rv (mword (8 * size)) e := MEMr addr size. +(* +Definition string_of_bits bs := string_of_bv (bits_of bs). +Definition string_of_int := show + +Definition _sign_extend bits len := maybe_failwith (of_bits (exts_bv len bits)) +Definition _zero_extend bits len := maybe_failwith (of_bits (extz_bv len bits)) +*) +Definition shift_bits_left {rv e a b} (v : mword a) (n : mword b) : monad rv (mword a) e := + maybe_fail "shift_bits_left" (unsigned n) >>= fun n => + returnm (shiftl v n). + +Definition shift_bits_right {rv e a b} (v : mword a) (n : mword b) : monad rv (mword a) e := + maybe_fail "shift_bits_right" (unsigned n) >>= fun n => + returnm (shiftr v n). + +Definition shift_bits_right_arith {rv e a b} (v : mword a) (n : mword b) : monad rv (mword a) e := + maybe_fail "shift_bits_right" (unsigned n) >>= fun n => + returnm (arith_shiftr v n). + +(* Use constants for undefined values for now *) +Definition internal_pick {rv a e} (vs : list a) : monad rv a e := +match vs with +| (h::_) => returnm h +| _ => Fail "empty list in internal_pick" +end. +Definition undefined_string {rv e} (_:unit) : monad rv string e := returnm ""%string. +Definition undefined_unit {rv e} (_:unit) : monad rv unit e := returnm tt. +Definition undefined_int {rv e} (_:unit) : monad rv Z e := returnm (0:ii). +(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*) +Definition undefined_vector {rv a e} len (u : a) `{ArithFact (len >= 0)} : monad rv (vec a len) e := returnm (vec_init u len). +(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) +Definition undefined_bitvector {rv e} len `{ArithFact (len >= 0)} : monad rv (mword len) e := returnm (mword_of_int 0). +(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) +Definition undefined_bits {rv e} := @undefined_bitvector rv e. +Definition undefined_bit {rv e} (_:unit) : monad rv bitU e := returnm BU. +(*Definition undefined_real {rv e} (_:unit) : monad rv real e := returnm (realFromFrac 0 1).*) +Definition undefined_range {rv e} i j `{ArithFact (i <= j)} : monad rv {z : Z & ArithFact (i <= z /\ z <= j)} e := returnm (build_ex i). +Definition undefined_atom {rv e} i : monad rv Z e := returnm i. +Definition undefined_nat {rv e} (_:unit) : monad rv Z e := returnm (0:ii). + +Definition skip {rv e} (_:unit) : monad rv unit e := returnm tt. + +(*val elf_entry : unit -> integer*) +Definition elf_entry (_:unit) : Z := 0. +(*declare ocaml target_rep function elf_entry := `Elf_loader.elf_entry`*) + +(*Definition print_bits msg bs := prerr_endline (msg ^ (string_of_bits bs)) + +val get_time_ns : unit -> integer*) +Definition get_time_ns (_:unit) : Z := 0. +(*declare ocaml target_rep function get_time_ns := `(fun () -> Big_int.of_int (int_of_float (1e9 *. Unix.gettimeofday ())))`*) + +Definition eq_bit (x : bitU) (y : bitU) : bool := + match x, y with + | B0, B0 => true + | B1, B1 => true + | BU, BU => true + | _,_ => false + end. + +Require Import Zeuclid. +Definition euclid_modulo (m n : Z) `{ArithFact (n > 0)} : {z : Z & ArithFact (0 <= z <= n-1)}. +refine (existT _ (ZEuclid.modulo m n) _). +constructor. +destruct H. +assert (Z.abs n = n). { rewrite Z.abs_eq; auto with zarith. } +rewrite <- H at 3. +lapply (ZEuclid.mod_always_pos m n); omega. +Qed. + +(* Override the more general version *) + +Definition mults_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mults_vec l r. +Definition mult_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mult_vec l r. + + +Definition print_endline (_:string) : unit := tt. +Definition prerr_endline (_:string) : unit := tt. +Definition prerr_string (_:string) : unit := tt. +Definition putchar {T} (_:T) : unit := tt. +Require DecimalString. +Definition string_of_int z := DecimalString.NilZero.string_of_int (Z.to_int z). + +Lemma __MIPS_read_lemma : forall width, 8 * width = 8 * (8 * width ÷ 8). +intros. +rewrite Z.mul_comm. +rewrite Z.quot_mul; auto with zarith. +Qed. +Hint Resolve __MIPS_read_lemma : sail. + +Lemma MEMr_wrapper_lemma : forall size : Z, 8 * size = 8 * (8 * (8 * size ÷ 8) ÷ 8). +intros. +rewrite Z.mul_comm. +rewrite Z.quot_mul; auto with zarith. +rewrite Z.mul_comm with (m := size). +rewrite Z.quot_mul; auto with zarith. +Qed. +Hint Resolve MEMr_wrapper_lemma : sail. + +Lemma getCapOffset_lemma {x0 x1 x2 x : Z} : + 0 <= x0 <= 18446744073709551616 - 1 -> + 0 <= x1 <= 18446744073709551616 - 1 -> + 18446744073709551616 <= x2 <= 18446744073709551616 -> + x = ZEuclid.modulo (x0 - x1) x2 -> + 0 <= x <= 18446744073709551616 - 1. +intros. +match goal with H:context [ZEuclid.modulo ?X ?Y] |- _ => pose proof (ZEuclid.mod_always_pos X Y) end. +omega with Z. +Qed. +Hint Resolve getCapOffset_lemma : sail. + diff --git a/snapshots/coq/cheri-mips/mips_types.v b/snapshots/coq/cheri-mips/mips_types.v new file mode 100644 index 00000000..36c5e40b --- /dev/null +++ b/snapshots/coq/cheri-mips/mips_types.v @@ -0,0 +1,1549 @@ +(*Generated by Sail from mips.*) +Require Import Sail2_instr_kinds. +Require Import Sail2_values. +Require Import Sail2_string. +Require Import Sail2_real. +Require Import Sail2_operators_mwords. +Require Import Sail2_prompt_monad. +Require Import Sail2_prompt. +Require Import Sail2_state. + + +Definition bits (n : Z) : Type := mword n. + +Inductive exception := + ISAException : unit -> exception + | Error_not_implemented : string -> exception + | Error_misaligned_access : unit -> exception + | Error_EBREAK : unit -> exception + | Error_internal_error : unit -> exception. +Arguments exception : clear implicits. + + + +Record CauseReg := { CauseReg_CauseReg_chunk_0 : mword 32; }. +Notation "{[ r 'with' 'CauseReg_CauseReg_chunk_0' := e ]}" := ({| CauseReg_CauseReg_chunk_0 := e |}). + +Record StatusReg := { StatusReg_StatusReg_chunk_0 : mword 32; }. +Notation "{[ r 'with' 'StatusReg_StatusReg_chunk_0' := e ]}" := ({| StatusReg_StatusReg_chunk_0 := e |}). + +Record TLBEntryLoReg := { TLBEntryLoReg_TLBEntryLoReg_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'TLBEntryLoReg_TLBEntryLoReg_chunk_0' := e ]}" := ({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := e |}). + +Record TLBEntryHiReg := { TLBEntryHiReg_TLBEntryHiReg_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'TLBEntryHiReg_TLBEntryHiReg_chunk_0' := e ]}" := ({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := e |}). + +Record ContextReg := { ContextReg_ContextReg_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'ContextReg_ContextReg_chunk_0' := e ]}" := ({| ContextReg_ContextReg_chunk_0 := e |}). + +Record XContextReg := { XContextReg_XContextReg_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'XContextReg_XContextReg_chunk_0' := e ]}" := ({| XContextReg_XContextReg_chunk_0 := e |}). + +Definition TLBIndexT : Type := bits 6. + +Record TLBEntry := { TLBEntry_TLBEntry_chunk_1 : mword 53; TLBEntry_TLBEntry_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'TLBEntry_TLBEntry_chunk_1' := e ]}" := ({| TLBEntry_TLBEntry_chunk_1 := e; TLBEntry_TLBEntry_chunk_0 := TLBEntry_TLBEntry_chunk_0 r |}). +Notation "{[ r 'with' 'TLBEntry_TLBEntry_chunk_0' := e ]}" := ({| TLBEntry_TLBEntry_chunk_0 := e; TLBEntry_TLBEntry_chunk_1 := TLBEntry_TLBEntry_chunk_1 r |}). + +Inductive Exception := + Interrupt + | TLBMod + | TLBL + | TLBS + | AdEL + | AdES + | Sys + | Bp + | ResI + | CpU + | Ov + | Tr + | C2E + | C2Trap + | XTLBRefillL + | XTLBRefillS + | XTLBInvL + | XTLBInvS + | MCheck. +Scheme Equality for Exception. +Instance Decidable_eq_Exception : +forall (x y : Exception), Decidable (x = y) := +Decidable_eq_from_dec Exception_eq_dec. + + +Inductive MemAccessType := Instruction | LoadData | StoreData. +Scheme Equality for MemAccessType. +Instance Decidable_eq_MemAccessType : +forall (x y : MemAccessType), Decidable (x = y) := +Decidable_eq_from_dec MemAccessType_eq_dec. + + +Inductive AccessLevel := User | Supervisor | Kernel. +Scheme Equality for AccessLevel. +Instance Decidable_eq_AccessLevel : +forall (x y : AccessLevel), Decidable (x = y) := +Decidable_eq_from_dec AccessLevel_eq_dec. + + +Definition regno : Type := bits 5. + +Definition imm16 : Type := bits 16. + +Definition regregreg : Type := (regno * regno * regno). + +Definition regregimm16 : Type := (regno * regno * imm16). + +Inductive decode_failure := + no_matching_pattern | unsupported_instruction | illegal_instruction | internal_error. +Scheme Equality for decode_failure. +Instance Decidable_eq_decode_failure : +forall (x y : decode_failure), Decidable (x = y) := +Decidable_eq_from_dec decode_failure_eq_dec. + + +Inductive Comparison := EQ' | NE | GE | GEU | GT' | LE | LT' | LTU. +Scheme Equality for Comparison. +Instance Decidable_eq_Comparison : +forall (x y : Comparison), Decidable (x = y) := +Decidable_eq_from_dec Comparison_eq_dec. + + +Inductive WordType := B | H | W | D. +Scheme Equality for WordType. +Instance Decidable_eq_WordType : +forall (x y : WordType), Decidable (x = y) := +Decidable_eq_from_dec WordType_eq_dec. + + +Inductive WordTypeUnaligned := WL | WR | DL | DR. +Scheme Equality for WordTypeUnaligned. +Instance Decidable_eq_WordTypeUnaligned : +forall (x y : WordTypeUnaligned), Decidable (x = y) := +Decidable_eq_from_dec WordTypeUnaligned_eq_dec. + + +Inductive ast := + DADDIU : (regno * regno * imm16) -> ast + | DADDU : (regno * regno * regno) -> ast + | DADDI : (regno * regno * bits 16) -> ast + | DADD : (regno * regno * regno) -> ast + | ADD : (regno * regno * regno) -> ast + | ADDI : (regno * regno * bits 16) -> ast + | ADDU : (regno * regno * regno) -> ast + | ADDIU : (regno * regno * bits 16) -> ast + | DSUBU : (regno * regno * regno) -> ast + | DSUB : (regno * regno * regno) -> ast + | SUB : (regno * regno * regno) -> ast + | SUBU : (regno * regno * regno) -> ast + | AND : (regno * regno * regno) -> ast + | ANDI : (regno * regno * bits 16) -> ast + | OR : (regno * regno * regno) -> ast + | ORI : (regno * regno * bits 16) -> ast + | NOR : (regno * regno * regno) -> ast + | XOR : (regno * regno * regno) -> ast + | XORI : (regno * regno * bits 16) -> ast + | LUI : (regno * imm16) -> ast + | DSLL : (regno * regno * regno) -> ast + | DSLL32 : (regno * regno * regno) -> ast + | DSLLV : (regno * regno * regno) -> ast + | DSRA : (regno * regno * regno) -> ast + | DSRA32 : (regno * regno * regno) -> ast + | DSRAV : (regno * regno * regno) -> ast + | DSRL : (regno * regno * regno) -> ast + | DSRL32 : (regno * regno * regno) -> ast + | DSRLV : (regno * regno * regno) -> ast + | SLL : (regno * regno * regno) -> ast + | SLLV : (regno * regno * regno) -> ast + | SRA : (regno * regno * regno) -> ast + | SRAV : (regno * regno * regno) -> ast + | SRL : (regno * regno * regno) -> ast + | SRLV : (regno * regno * regno) -> ast + | SLT : (regno * regno * regno) -> ast + | SLTI : (regno * regno * bits 16) -> ast + | SLTU : (regno * regno * regno) -> ast + | SLTIU : (regno * regno * bits 16) -> ast + | MOVN : (regno * regno * regno) -> ast + | MOVZ : (regno * regno * regno) -> ast + | MFHI : regno -> ast + | MFLO : regno -> ast + | MTHI : regno -> ast + | MTLO : regno -> ast + | MUL : (regno * regno * regno) -> ast + | MULT : (regno * regno) -> ast + | MULTU : (regno * regno) -> ast + | DMULT : (regno * regno) -> ast + | DMULTU : (regno * regno) -> ast + | MADD : (regno * regno) -> ast + | MADDU : (regno * regno) -> ast + | MSUB : (regno * regno) -> ast + | MSUBU : (regno * regno) -> ast + | DIV : (regno * regno) -> ast + | DIVU : (regno * regno) -> ast + | DDIV : (regno * regno) -> ast + | DDIVU : (regno * regno) -> ast + | J : bits 26 -> ast + | JAL : bits 26 -> ast + | JR : regno -> ast + | JALR : (regno * regno) -> ast + | BEQ : (regno * regno * imm16 * bool * bool) -> ast + | BCMPZ : (regno * imm16 * Comparison * bool * bool) -> ast + | SYSCALL : unit -> ast + | BREAK : unit -> ast + | WAIT : unit -> ast + | TRAPREG : (regno * regno * Comparison) -> ast + | TRAPIMM : (regno * imm16 * Comparison) -> ast + | Load : (WordType * bool * bool * regno * regno * imm16) -> ast + | Store : (WordType * bool * regno * regno * imm16) -> ast + | LWL : (regno * regno * bits 16) -> ast + | LWR : (regno * regno * bits 16) -> ast + | SWL : (regno * regno * bits 16) -> ast + | SWR : (regno * regno * bits 16) -> ast + | LDL : (regno * regno * bits 16) -> ast + | LDR : (regno * regno * bits 16) -> ast + | SDL : (regno * regno * bits 16) -> ast + | SDR : (regno * regno * bits 16) -> ast + | CACHE : (regno * regno * bits 16) -> ast + | SYNC : unit -> ast + | MFC0 : (regno * regno * bits 3 * bool) -> ast + | HCF : unit -> ast + | MTC0 : (regno * regno * bits 3 * bool) -> ast + | TLBWI : unit -> ast + | TLBWR : unit -> ast + | TLBR : unit -> ast + | TLBP : unit -> ast + | RDHWR : (regno * regno) -> ast + | ERET : unit -> ast + | RI : unit -> ast. +Arguments ast : clear implicits. + + + +Inductive register_value := + Regval_vector : (Z * bool * list register_value) -> register_value + | Regval_list : list register_value -> register_value + | Regval_option : option register_value -> register_value + | Regval_CauseReg : CauseReg -> register_value + | Regval_ContextReg : ContextReg -> register_value + | Regval_StatusReg : StatusReg -> register_value + | Regval_TLBEntry : TLBEntry -> register_value + | Regval_TLBEntryHiReg : TLBEntryHiReg -> register_value + | Regval_TLBEntryLoReg : TLBEntryLoReg -> register_value + | Regval_XContextReg : XContextReg -> register_value + | Regval_vector_16_dec_bit : mword 16 -> register_value + | Regval_vector_1_dec_bit : mword 1 -> register_value + | Regval_vector_32_dec_bit : mword 32 -> register_value + | Regval_vector_3_dec_bit : mword 3 -> register_value + | Regval_vector_64_dec_bit : mword 64 -> register_value + | Regval_vector_6_dec_bit : mword 6 -> register_value + | Regval_vector_8_dec_bit : mword 8 -> register_value. +Arguments register_value : clear implicits. + + + +Record regstate := + { UART_RVALID : mword 1; + UART_RDATA : mword 8; + UART_WRITTEN : mword 1; + UART_WDATA : mword 8; + GPR : vec (mword 64) 32; + LO : mword 64; + HI : mword 64; + DelayedPC : mword 64; + BranchPending : mword 1; + InBranchDelay : mword 1; + NextInBranchDelay : mword 1; + CP0Status : StatusReg; + CP0ConfigK0 : mword 3; + CP0UserLocal : mword 64; + CP0HWREna : mword 32; + CP0Count : mword 32; + CP0BadInstrP : mword 32; + CP0BadInstr : mword 32; + LastInstrBits : mword 32; + CurrentInstrBits : mword 32; + CP0BadVAddr : mword 64; + CP0LLAddr : mword 64; + CP0LLBit : mword 1; + CP0ErrorEPC : mword 64; + CP0EPC : mword 64; + CP0Cause : CauseReg; + CP0Compare : mword 32; + TLBEntry63 : TLBEntry; + TLBEntry62 : TLBEntry; + TLBEntry61 : TLBEntry; + TLBEntry60 : TLBEntry; + TLBEntry59 : TLBEntry; + TLBEntry58 : TLBEntry; + TLBEntry57 : TLBEntry; + TLBEntry56 : TLBEntry; + TLBEntry55 : TLBEntry; + TLBEntry54 : TLBEntry; + TLBEntry53 : TLBEntry; + TLBEntry52 : TLBEntry; + TLBEntry51 : TLBEntry; + TLBEntry50 : TLBEntry; + TLBEntry49 : TLBEntry; + TLBEntry48 : TLBEntry; + TLBEntry47 : TLBEntry; + TLBEntry46 : TLBEntry; + TLBEntry45 : TLBEntry; + TLBEntry44 : TLBEntry; + TLBEntry43 : TLBEntry; + TLBEntry42 : TLBEntry; + TLBEntry41 : TLBEntry; + TLBEntry40 : TLBEntry; + TLBEntry39 : TLBEntry; + TLBEntry38 : TLBEntry; + TLBEntry37 : TLBEntry; + TLBEntry36 : TLBEntry; + TLBEntry35 : TLBEntry; + TLBEntry34 : TLBEntry; + TLBEntry33 : TLBEntry; + TLBEntry32 : TLBEntry; + TLBEntry31 : TLBEntry; + TLBEntry30 : TLBEntry; + TLBEntry29 : TLBEntry; + TLBEntry28 : TLBEntry; + TLBEntry27 : TLBEntry; + TLBEntry26 : TLBEntry; + TLBEntry25 : TLBEntry; + TLBEntry24 : TLBEntry; + TLBEntry23 : TLBEntry; + TLBEntry22 : TLBEntry; + TLBEntry21 : TLBEntry; + TLBEntry20 : TLBEntry; + TLBEntry19 : TLBEntry; + TLBEntry18 : TLBEntry; + TLBEntry17 : TLBEntry; + TLBEntry16 : TLBEntry; + TLBEntry15 : TLBEntry; + TLBEntry14 : TLBEntry; + TLBEntry13 : TLBEntry; + TLBEntry12 : TLBEntry; + TLBEntry11 : TLBEntry; + TLBEntry10 : TLBEntry; + TLBEntry09 : TLBEntry; + TLBEntry08 : TLBEntry; + TLBEntry07 : TLBEntry; + TLBEntry06 : TLBEntry; + TLBEntry05 : TLBEntry; + TLBEntry04 : TLBEntry; + TLBEntry03 : TLBEntry; + TLBEntry02 : TLBEntry; + TLBEntry01 : TLBEntry; + TLBEntry00 : TLBEntry; + TLBXContext : XContextReg; + TLBEntryHi : TLBEntryHiReg; + TLBWired : mword 6; + TLBPageMask : mword 16; + TLBContext : ContextReg; + TLBEntryLo1 : TLBEntryLoReg; + TLBEntryLo0 : TLBEntryLoReg; + TLBRandom : mword 6; + TLBIndex : mword 6; + TLBProbe : mword 1; + NextPC : mword 64; + PC : mword 64; }. +Notation "{[ r 'with' 'UART_RVALID' := e ]}" := ({| UART_RVALID := e; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'UART_RDATA' := e ]}" := ({| UART_RDATA := e; UART_RVALID := UART_RVALID r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'UART_WRITTEN' := e ]}" := ({| UART_WRITTEN := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'UART_WDATA' := e ]}" := ({| UART_WDATA := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'GPR' := e ]}" := ({| GPR := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'LO' := e ]}" := ({| LO := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'HI' := e ]}" := ({| HI := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'DelayedPC' := e ]}" := ({| DelayedPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'BranchPending' := e ]}" := ({| BranchPending := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'InBranchDelay' := e ]}" := ({| InBranchDelay := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'NextInBranchDelay' := e ]}" := ({| NextInBranchDelay := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0Status' := e ]}" := ({| CP0Status := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0ConfigK0' := e ]}" := ({| CP0ConfigK0 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0UserLocal' := e ]}" := ({| CP0UserLocal := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0HWREna' := e ]}" := ({| CP0HWREna := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0Count' := e ]}" := ({| CP0Count := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0BadInstrP' := e ]}" := ({| CP0BadInstrP := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0BadInstr' := e ]}" := ({| CP0BadInstr := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'LastInstrBits' := e ]}" := ({| LastInstrBits := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CurrentInstrBits' := e ]}" := ({| CurrentInstrBits := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0BadVAddr' := e ]}" := ({| CP0BadVAddr := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0LLAddr' := e ]}" := ({| CP0LLAddr := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0LLBit' := e ]}" := ({| CP0LLBit := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0ErrorEPC' := e ]}" := ({| CP0ErrorEPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0EPC' := e ]}" := ({| CP0EPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0Cause' := e ]}" := ({| CP0Cause := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0Compare' := e ]}" := ({| CP0Compare := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry63' := e ]}" := ({| TLBEntry63 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry62' := e ]}" := ({| TLBEntry62 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry61' := e ]}" := ({| TLBEntry61 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry60' := e ]}" := ({| TLBEntry60 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry59' := e ]}" := ({| TLBEntry59 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry58' := e ]}" := ({| TLBEntry58 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry57' := e ]}" := ({| TLBEntry57 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry56' := e ]}" := ({| TLBEntry56 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry55' := e ]}" := ({| TLBEntry55 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry54' := e ]}" := ({| TLBEntry54 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry53' := e ]}" := ({| TLBEntry53 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry52' := e ]}" := ({| TLBEntry52 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry51' := e ]}" := ({| TLBEntry51 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry50' := e ]}" := ({| TLBEntry50 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry49' := e ]}" := ({| TLBEntry49 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry48' := e ]}" := ({| TLBEntry48 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry47' := e ]}" := ({| TLBEntry47 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry46' := e ]}" := ({| TLBEntry46 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry45' := e ]}" := ({| TLBEntry45 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry44' := e ]}" := ({| TLBEntry44 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry43' := e ]}" := ({| TLBEntry43 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry42' := e ]}" := ({| TLBEntry42 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry41' := e ]}" := ({| TLBEntry41 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry40' := e ]}" := ({| TLBEntry40 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry39' := e ]}" := ({| TLBEntry39 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry38' := e ]}" := ({| TLBEntry38 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry37' := e ]}" := ({| TLBEntry37 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry36' := e ]}" := ({| TLBEntry36 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry35' := e ]}" := ({| TLBEntry35 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry34' := e ]}" := ({| TLBEntry34 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry33' := e ]}" := ({| TLBEntry33 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry32' := e ]}" := ({| TLBEntry32 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry31' := e ]}" := ({| TLBEntry31 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry30' := e ]}" := ({| TLBEntry30 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry29' := e ]}" := ({| TLBEntry29 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry28' := e ]}" := ({| TLBEntry28 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry27' := e ]}" := ({| TLBEntry27 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry26' := e ]}" := ({| TLBEntry26 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry25' := e ]}" := ({| TLBEntry25 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry24' := e ]}" := ({| TLBEntry24 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry23' := e ]}" := ({| TLBEntry23 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry22' := e ]}" := ({| TLBEntry22 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry21' := e ]}" := ({| TLBEntry21 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry20' := e ]}" := ({| TLBEntry20 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry19' := e ]}" := ({| TLBEntry19 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry18' := e ]}" := ({| TLBEntry18 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry17' := e ]}" := ({| TLBEntry17 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry16' := e ]}" := ({| TLBEntry16 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry15' := e ]}" := ({| TLBEntry15 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry14' := e ]}" := ({| TLBEntry14 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry13' := e ]}" := ({| TLBEntry13 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry12' := e ]}" := ({| TLBEntry12 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry11' := e ]}" := ({| TLBEntry11 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry10' := e ]}" := ({| TLBEntry10 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry09' := e ]}" := ({| TLBEntry09 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry08' := e ]}" := ({| TLBEntry08 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry07' := e ]}" := ({| TLBEntry07 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry06' := e ]}" := ({| TLBEntry06 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry05' := e ]}" := ({| TLBEntry05 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry04' := e ]}" := ({| TLBEntry04 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry03' := e ]}" := ({| TLBEntry03 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry02' := e ]}" := ({| TLBEntry02 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry01' := e ]}" := ({| TLBEntry01 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry00' := e ]}" := ({| TLBEntry00 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBXContext' := e ]}" := ({| TLBXContext := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntryHi' := e ]}" := ({| TLBEntryHi := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBWired' := e ]}" := ({| TLBWired := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBPageMask' := e ]}" := ({| TLBPageMask := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBContext' := e ]}" := ({| TLBContext := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntryLo1' := e ]}" := ({| TLBEntryLo1 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntryLo0' := e ]}" := ({| TLBEntryLo0 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBRandom' := e ]}" := ({| TLBRandom := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBIndex' := e ]}" := ({| TLBIndex := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBProbe' := e ]}" := ({| TLBProbe := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'NextPC' := e ]}" := ({| NextPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; PC := PC r |}). +Notation "{[ r 'with' 'PC' := e ]}" := ({| PC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r |}). + + + +Definition CauseReg_of_regval (merge_var : register_value) +: option CauseReg := + + match merge_var with | Regval_CauseReg (v) => Some (v) | g__13 => None end. + +Definition regval_of_CauseReg (v : CauseReg) : register_value := Regval_CauseReg (v). + +Definition ContextReg_of_regval (merge_var : register_value) +: option ContextReg := + + match merge_var with | Regval_ContextReg (v) => Some (v) | g__12 => None end. + +Definition regval_of_ContextReg (v : ContextReg) : register_value := Regval_ContextReg (v). + +Definition StatusReg_of_regval (merge_var : register_value) +: option StatusReg := + + match merge_var with | Regval_StatusReg (v) => Some (v) | g__11 => None end. + +Definition regval_of_StatusReg (v : StatusReg) : register_value := Regval_StatusReg (v). + +Definition TLBEntry_of_regval (merge_var : register_value) +: option TLBEntry := + + match merge_var with | Regval_TLBEntry (v) => Some (v) | g__10 => None end. + +Definition regval_of_TLBEntry (v : TLBEntry) : register_value := Regval_TLBEntry (v). + +Definition TLBEntryHiReg_of_regval (merge_var : register_value) +: option TLBEntryHiReg := + + match merge_var with | Regval_TLBEntryHiReg (v) => Some (v) | g__9 => None end. + +Definition regval_of_TLBEntryHiReg (v : TLBEntryHiReg) +: register_value := + + Regval_TLBEntryHiReg + (v). + +Definition TLBEntryLoReg_of_regval (merge_var : register_value) +: option TLBEntryLoReg := + + match merge_var with | Regval_TLBEntryLoReg (v) => Some (v) | g__8 => None end. + +Definition regval_of_TLBEntryLoReg (v : TLBEntryLoReg) +: register_value := + + Regval_TLBEntryLoReg + (v). + +Definition XContextReg_of_regval (merge_var : register_value) +: option XContextReg := + + match merge_var with | Regval_XContextReg (v) => Some (v) | g__7 => None end. + +Definition regval_of_XContextReg (v : XContextReg) : register_value := Regval_XContextReg (v). + +Definition vector_16_dec_bit_of_regval (merge_var : register_value) +: option (mword 16) := + + match merge_var with | Regval_vector_16_dec_bit (v) => Some (v) | g__6 => None end. + +Definition regval_of_vector_16_dec_bit (v : mword 16) +: register_value := + + Regval_vector_16_dec_bit + (v). + +Definition vector_1_dec_bit_of_regval (merge_var : register_value) +: option (mword 1) := + + match merge_var with | Regval_vector_1_dec_bit (v) => Some (v) | g__5 => None end. + +Definition regval_of_vector_1_dec_bit (v : mword 1) +: register_value := + + Regval_vector_1_dec_bit + (v). + +Definition vector_32_dec_bit_of_regval (merge_var : register_value) +: option (mword 32) := + + match merge_var with | Regval_vector_32_dec_bit (v) => Some (v) | g__4 => None end. + +Definition regval_of_vector_32_dec_bit (v : mword 32) +: register_value := + + Regval_vector_32_dec_bit + (v). + +Definition vector_3_dec_bit_of_regval (merge_var : register_value) +: option (mword 3) := + + match merge_var with | Regval_vector_3_dec_bit (v) => Some (v) | g__3 => None end. + +Definition regval_of_vector_3_dec_bit (v : mword 3) +: register_value := + + Regval_vector_3_dec_bit + (v). + +Definition vector_64_dec_bit_of_regval (merge_var : register_value) +: option (mword 64) := + + match merge_var with | Regval_vector_64_dec_bit (v) => Some (v) | g__2 => None end. + +Definition regval_of_vector_64_dec_bit (v : mword 64) +: register_value := + + Regval_vector_64_dec_bit + (v). + +Definition vector_6_dec_bit_of_regval (merge_var : register_value) +: option (mword 6) := + + match merge_var with | Regval_vector_6_dec_bit (v) => Some (v) | g__1 => None end. + +Definition regval_of_vector_6_dec_bit (v : mword 6) +: register_value := + + Regval_vector_6_dec_bit + (v). + +Definition vector_8_dec_bit_of_regval (merge_var : register_value) +: option (mword 8) := + + match merge_var with | Regval_vector_8_dec_bit (v) => Some (v) | g__0 => None end. + +Definition regval_of_vector_8_dec_bit (v : mword 8) +: register_value := + + Regval_vector_8_dec_bit + (v). + + + +Definition vector_of_regval {a} n (of_regval : register_value -> option a) (rv : register_value) : option (vec a n) := match rv with + | Regval_vector (n', _, v) => if n =? n' then map_bind (vec_of_list n) (just_list (List.map of_regval v)) else None + | _ => None +end. + +Definition regval_of_vector {a} (regval_of : a -> register_value) (size : Z) (is_inc : bool) (xs : vec a size) : register_value := Regval_vector (size, is_inc, List.map regval_of (list_of_vec xs)). + +Definition list_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (list a) := match rv with + | Regval_list v => just_list (List.map of_regval v) + | _ => None +end. + +Definition regval_of_list {a} (regval_of : a -> register_value) (xs : list a) : register_value := Regval_list (List.map regval_of xs). + +Definition option_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (option a) := match rv with + | Regval_option v => option_map of_regval v + | _ => None +end. + +Definition regval_of_option {a} (regval_of : a -> register_value) (v : option a) := Regval_option (option_map regval_of v). + + +Definition UART_RVALID_ref := {| + name := "UART_RVALID"; + read_from := (fun s => s.(UART_RVALID)); + write_to := (fun v s => ({[ s with UART_RVALID := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition UART_RDATA_ref := {| + name := "UART_RDATA"; + read_from := (fun s => s.(UART_RDATA)); + write_to := (fun v s => ({[ s with UART_RDATA := v ]})); + of_regval := (fun v => vector_8_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_8_dec_bit v) |}. + +Definition UART_WRITTEN_ref := {| + name := "UART_WRITTEN"; + read_from := (fun s => s.(UART_WRITTEN)); + write_to := (fun v s => ({[ s with UART_WRITTEN := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition UART_WDATA_ref := {| + name := "UART_WDATA"; + read_from := (fun s => s.(UART_WDATA)); + write_to := (fun v s => ({[ s with UART_WDATA := v ]})); + of_regval := (fun v => vector_8_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_8_dec_bit v) |}. + +Definition GPR_ref := {| + name := "GPR"; + read_from := (fun s => s.(GPR)); + write_to := (fun v s => ({[ s with GPR := v ]})); + of_regval := (fun v => vector_of_regval 32 (fun v => vector_64_dec_bit_of_regval v) v); + regval_of := (fun v => regval_of_vector (fun v => regval_of_vector_64_dec_bit v) 32 false v) |}. + +Definition LO_ref := {| + name := "LO"; + read_from := (fun s => s.(LO)); + write_to := (fun v s => ({[ s with LO := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition HI_ref := {| + name := "HI"; + read_from := (fun s => s.(HI)); + write_to := (fun v s => ({[ s with HI := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition DelayedPC_ref := {| + name := "DelayedPC"; + read_from := (fun s => s.(DelayedPC)); + write_to := (fun v s => ({[ s with DelayedPC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition BranchPending_ref := {| + name := "BranchPending"; + read_from := (fun s => s.(BranchPending)); + write_to := (fun v s => ({[ s with BranchPending := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition InBranchDelay_ref := {| + name := "InBranchDelay"; + read_from := (fun s => s.(InBranchDelay)); + write_to := (fun v s => ({[ s with InBranchDelay := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition NextInBranchDelay_ref := {| + name := "NextInBranchDelay"; + read_from := (fun s => s.(NextInBranchDelay)); + write_to := (fun v s => ({[ s with NextInBranchDelay := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition CP0Status_ref := {| + name := "CP0Status"; + read_from := (fun s => s.(CP0Status)); + write_to := (fun v s => ({[ s with CP0Status := v ]})); + of_regval := (fun v => StatusReg_of_regval v); + regval_of := (fun v => regval_of_StatusReg v) |}. + +Definition CP0ConfigK0_ref := {| + name := "CP0ConfigK0"; + read_from := (fun s => s.(CP0ConfigK0)); + write_to := (fun v s => ({[ s with CP0ConfigK0 := v ]})); + of_regval := (fun v => vector_3_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_3_dec_bit v) |}. + +Definition CP0UserLocal_ref := {| + name := "CP0UserLocal"; + read_from := (fun s => s.(CP0UserLocal)); + write_to := (fun v s => ({[ s with CP0UserLocal := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CP0HWREna_ref := {| + name := "CP0HWREna"; + read_from := (fun s => s.(CP0HWREna)); + write_to := (fun v s => ({[ s with CP0HWREna := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition CP0Count_ref := {| + name := "CP0Count"; + read_from := (fun s => s.(CP0Count)); + write_to := (fun v s => ({[ s with CP0Count := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition CP0BadInstrP_ref := {| + name := "CP0BadInstrP"; + read_from := (fun s => s.(CP0BadInstrP)); + write_to := (fun v s => ({[ s with CP0BadInstrP := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition CP0BadInstr_ref := {| + name := "CP0BadInstr"; + read_from := (fun s => s.(CP0BadInstr)); + write_to := (fun v s => ({[ s with CP0BadInstr := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition LastInstrBits_ref := {| + name := "LastInstrBits"; + read_from := (fun s => s.(LastInstrBits)); + write_to := (fun v s => ({[ s with LastInstrBits := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition CurrentInstrBits_ref := {| + name := "CurrentInstrBits"; + read_from := (fun s => s.(CurrentInstrBits)); + write_to := (fun v s => ({[ s with CurrentInstrBits := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition CP0BadVAddr_ref := {| + name := "CP0BadVAddr"; + read_from := (fun s => s.(CP0BadVAddr)); + write_to := (fun v s => ({[ s with CP0BadVAddr := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CP0LLAddr_ref := {| + name := "CP0LLAddr"; + read_from := (fun s => s.(CP0LLAddr)); + write_to := (fun v s => ({[ s with CP0LLAddr := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CP0LLBit_ref := {| + name := "CP0LLBit"; + read_from := (fun s => s.(CP0LLBit)); + write_to := (fun v s => ({[ s with CP0LLBit := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition CP0ErrorEPC_ref := {| + name := "CP0ErrorEPC"; + read_from := (fun s => s.(CP0ErrorEPC)); + write_to := (fun v s => ({[ s with CP0ErrorEPC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CP0EPC_ref := {| + name := "CP0EPC"; + read_from := (fun s => s.(CP0EPC)); + write_to := (fun v s => ({[ s with CP0EPC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CP0Cause_ref := {| + name := "CP0Cause"; + read_from := (fun s => s.(CP0Cause)); + write_to := (fun v s => ({[ s with CP0Cause := v ]})); + of_regval := (fun v => CauseReg_of_regval v); + regval_of := (fun v => regval_of_CauseReg v) |}. + +Definition CP0Compare_ref := {| + name := "CP0Compare"; + read_from := (fun s => s.(CP0Compare)); + write_to := (fun v s => ({[ s with CP0Compare := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition TLBEntry63_ref := {| + name := "TLBEntry63"; + read_from := (fun s => s.(TLBEntry63)); + write_to := (fun v s => ({[ s with TLBEntry63 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry62_ref := {| + name := "TLBEntry62"; + read_from := (fun s => s.(TLBEntry62)); + write_to := (fun v s => ({[ s with TLBEntry62 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry61_ref := {| + name := "TLBEntry61"; + read_from := (fun s => s.(TLBEntry61)); + write_to := (fun v s => ({[ s with TLBEntry61 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry60_ref := {| + name := "TLBEntry60"; + read_from := (fun s => s.(TLBEntry60)); + write_to := (fun v s => ({[ s with TLBEntry60 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry59_ref := {| + name := "TLBEntry59"; + read_from := (fun s => s.(TLBEntry59)); + write_to := (fun v s => ({[ s with TLBEntry59 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry58_ref := {| + name := "TLBEntry58"; + read_from := (fun s => s.(TLBEntry58)); + write_to := (fun v s => ({[ s with TLBEntry58 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry57_ref := {| + name := "TLBEntry57"; + read_from := (fun s => s.(TLBEntry57)); + write_to := (fun v s => ({[ s with TLBEntry57 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry56_ref := {| + name := "TLBEntry56"; + read_from := (fun s => s.(TLBEntry56)); + write_to := (fun v s => ({[ s with TLBEntry56 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry55_ref := {| + name := "TLBEntry55"; + read_from := (fun s => s.(TLBEntry55)); + write_to := (fun v s => ({[ s with TLBEntry55 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry54_ref := {| + name := "TLBEntry54"; + read_from := (fun s => s.(TLBEntry54)); + write_to := (fun v s => ({[ s with TLBEntry54 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry53_ref := {| + name := "TLBEntry53"; + read_from := (fun s => s.(TLBEntry53)); + write_to := (fun v s => ({[ s with TLBEntry53 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry52_ref := {| + name := "TLBEntry52"; + read_from := (fun s => s.(TLBEntry52)); + write_to := (fun v s => ({[ s with TLBEntry52 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry51_ref := {| + name := "TLBEntry51"; + read_from := (fun s => s.(TLBEntry51)); + write_to := (fun v s => ({[ s with TLBEntry51 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry50_ref := {| + name := "TLBEntry50"; + read_from := (fun s => s.(TLBEntry50)); + write_to := (fun v s => ({[ s with TLBEntry50 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry49_ref := {| + name := "TLBEntry49"; + read_from := (fun s => s.(TLBEntry49)); + write_to := (fun v s => ({[ s with TLBEntry49 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry48_ref := {| + name := "TLBEntry48"; + read_from := (fun s => s.(TLBEntry48)); + write_to := (fun v s => ({[ s with TLBEntry48 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry47_ref := {| + name := "TLBEntry47"; + read_from := (fun s => s.(TLBEntry47)); + write_to := (fun v s => ({[ s with TLBEntry47 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry46_ref := {| + name := "TLBEntry46"; + read_from := (fun s => s.(TLBEntry46)); + write_to := (fun v s => ({[ s with TLBEntry46 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry45_ref := {| + name := "TLBEntry45"; + read_from := (fun s => s.(TLBEntry45)); + write_to := (fun v s => ({[ s with TLBEntry45 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry44_ref := {| + name := "TLBEntry44"; + read_from := (fun s => s.(TLBEntry44)); + write_to := (fun v s => ({[ s with TLBEntry44 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry43_ref := {| + name := "TLBEntry43"; + read_from := (fun s => s.(TLBEntry43)); + write_to := (fun v s => ({[ s with TLBEntry43 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry42_ref := {| + name := "TLBEntry42"; + read_from := (fun s => s.(TLBEntry42)); + write_to := (fun v s => ({[ s with TLBEntry42 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry41_ref := {| + name := "TLBEntry41"; + read_from := (fun s => s.(TLBEntry41)); + write_to := (fun v s => ({[ s with TLBEntry41 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry40_ref := {| + name := "TLBEntry40"; + read_from := (fun s => s.(TLBEntry40)); + write_to := (fun v s => ({[ s with TLBEntry40 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry39_ref := {| + name := "TLBEntry39"; + read_from := (fun s => s.(TLBEntry39)); + write_to := (fun v s => ({[ s with TLBEntry39 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry38_ref := {| + name := "TLBEntry38"; + read_from := (fun s => s.(TLBEntry38)); + write_to := (fun v s => ({[ s with TLBEntry38 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry37_ref := {| + name := "TLBEntry37"; + read_from := (fun s => s.(TLBEntry37)); + write_to := (fun v s => ({[ s with TLBEntry37 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry36_ref := {| + name := "TLBEntry36"; + read_from := (fun s => s.(TLBEntry36)); + write_to := (fun v s => ({[ s with TLBEntry36 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry35_ref := {| + name := "TLBEntry35"; + read_from := (fun s => s.(TLBEntry35)); + write_to := (fun v s => ({[ s with TLBEntry35 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry34_ref := {| + name := "TLBEntry34"; + read_from := (fun s => s.(TLBEntry34)); + write_to := (fun v s => ({[ s with TLBEntry34 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry33_ref := {| + name := "TLBEntry33"; + read_from := (fun s => s.(TLBEntry33)); + write_to := (fun v s => ({[ s with TLBEntry33 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry32_ref := {| + name := "TLBEntry32"; + read_from := (fun s => s.(TLBEntry32)); + write_to := (fun v s => ({[ s with TLBEntry32 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry31_ref := {| + name := "TLBEntry31"; + read_from := (fun s => s.(TLBEntry31)); + write_to := (fun v s => ({[ s with TLBEntry31 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry30_ref := {| + name := "TLBEntry30"; + read_from := (fun s => s.(TLBEntry30)); + write_to := (fun v s => ({[ s with TLBEntry30 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry29_ref := {| + name := "TLBEntry29"; + read_from := (fun s => s.(TLBEntry29)); + write_to := (fun v s => ({[ s with TLBEntry29 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry28_ref := {| + name := "TLBEntry28"; + read_from := (fun s => s.(TLBEntry28)); + write_to := (fun v s => ({[ s with TLBEntry28 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry27_ref := {| + name := "TLBEntry27"; + read_from := (fun s => s.(TLBEntry27)); + write_to := (fun v s => ({[ s with TLBEntry27 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry26_ref := {| + name := "TLBEntry26"; + read_from := (fun s => s.(TLBEntry26)); + write_to := (fun v s => ({[ s with TLBEntry26 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry25_ref := {| + name := "TLBEntry25"; + read_from := (fun s => s.(TLBEntry25)); + write_to := (fun v s => ({[ s with TLBEntry25 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry24_ref := {| + name := "TLBEntry24"; + read_from := (fun s => s.(TLBEntry24)); + write_to := (fun v s => ({[ s with TLBEntry24 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry23_ref := {| + name := "TLBEntry23"; + read_from := (fun s => s.(TLBEntry23)); + write_to := (fun v s => ({[ s with TLBEntry23 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry22_ref := {| + name := "TLBEntry22"; + read_from := (fun s => s.(TLBEntry22)); + write_to := (fun v s => ({[ s with TLBEntry22 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry21_ref := {| + name := "TLBEntry21"; + read_from := (fun s => s.(TLBEntry21)); + write_to := (fun v s => ({[ s with TLBEntry21 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry20_ref := {| + name := "TLBEntry20"; + read_from := (fun s => s.(TLBEntry20)); + write_to := (fun v s => ({[ s with TLBEntry20 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry19_ref := {| + name := "TLBEntry19"; + read_from := (fun s => s.(TLBEntry19)); + write_to := (fun v s => ({[ s with TLBEntry19 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry18_ref := {| + name := "TLBEntry18"; + read_from := (fun s => s.(TLBEntry18)); + write_to := (fun v s => ({[ s with TLBEntry18 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry17_ref := {| + name := "TLBEntry17"; + read_from := (fun s => s.(TLBEntry17)); + write_to := (fun v s => ({[ s with TLBEntry17 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry16_ref := {| + name := "TLBEntry16"; + read_from := (fun s => s.(TLBEntry16)); + write_to := (fun v s => ({[ s with TLBEntry16 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry15_ref := {| + name := "TLBEntry15"; + read_from := (fun s => s.(TLBEntry15)); + write_to := (fun v s => ({[ s with TLBEntry15 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry14_ref := {| + name := "TLBEntry14"; + read_from := (fun s => s.(TLBEntry14)); + write_to := (fun v s => ({[ s with TLBEntry14 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry13_ref := {| + name := "TLBEntry13"; + read_from := (fun s => s.(TLBEntry13)); + write_to := (fun v s => ({[ s with TLBEntry13 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry12_ref := {| + name := "TLBEntry12"; + read_from := (fun s => s.(TLBEntry12)); + write_to := (fun v s => ({[ s with TLBEntry12 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry11_ref := {| + name := "TLBEntry11"; + read_from := (fun s => s.(TLBEntry11)); + write_to := (fun v s => ({[ s with TLBEntry11 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry10_ref := {| + name := "TLBEntry10"; + read_from := (fun s => s.(TLBEntry10)); + write_to := (fun v s => ({[ s with TLBEntry10 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry09_ref := {| + name := "TLBEntry09"; + read_from := (fun s => s.(TLBEntry09)); + write_to := (fun v s => ({[ s with TLBEntry09 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry08_ref := {| + name := "TLBEntry08"; + read_from := (fun s => s.(TLBEntry08)); + write_to := (fun v s => ({[ s with TLBEntry08 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry07_ref := {| + name := "TLBEntry07"; + read_from := (fun s => s.(TLBEntry07)); + write_to := (fun v s => ({[ s with TLBEntry07 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry06_ref := {| + name := "TLBEntry06"; + read_from := (fun s => s.(TLBEntry06)); + write_to := (fun v s => ({[ s with TLBEntry06 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry05_ref := {| + name := "TLBEntry05"; + read_from := (fun s => s.(TLBEntry05)); + write_to := (fun v s => ({[ s with TLBEntry05 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry04_ref := {| + name := "TLBEntry04"; + read_from := (fun s => s.(TLBEntry04)); + write_to := (fun v s => ({[ s with TLBEntry04 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry03_ref := {| + name := "TLBEntry03"; + read_from := (fun s => s.(TLBEntry03)); + write_to := (fun v s => ({[ s with TLBEntry03 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry02_ref := {| + name := "TLBEntry02"; + read_from := (fun s => s.(TLBEntry02)); + write_to := (fun v s => ({[ s with TLBEntry02 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry01_ref := {| + name := "TLBEntry01"; + read_from := (fun s => s.(TLBEntry01)); + write_to := (fun v s => ({[ s with TLBEntry01 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry00_ref := {| + name := "TLBEntry00"; + read_from := (fun s => s.(TLBEntry00)); + write_to := (fun v s => ({[ s with TLBEntry00 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBXContext_ref := {| + name := "TLBXContext"; + read_from := (fun s => s.(TLBXContext)); + write_to := (fun v s => ({[ s with TLBXContext := v ]})); + of_regval := (fun v => XContextReg_of_regval v); + regval_of := (fun v => regval_of_XContextReg v) |}. + +Definition TLBEntryHi_ref := {| + name := "TLBEntryHi"; + read_from := (fun s => s.(TLBEntryHi)); + write_to := (fun v s => ({[ s with TLBEntryHi := v ]})); + of_regval := (fun v => TLBEntryHiReg_of_regval v); + regval_of := (fun v => regval_of_TLBEntryHiReg v) |}. + +Definition TLBWired_ref := {| + name := "TLBWired"; + read_from := (fun s => s.(TLBWired)); + write_to := (fun v s => ({[ s with TLBWired := v ]})); + of_regval := (fun v => vector_6_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_6_dec_bit v) |}. + +Definition TLBPageMask_ref := {| + name := "TLBPageMask"; + read_from := (fun s => s.(TLBPageMask)); + write_to := (fun v s => ({[ s with TLBPageMask := v ]})); + of_regval := (fun v => vector_16_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_16_dec_bit v) |}. + +Definition TLBContext_ref := {| + name := "TLBContext"; + read_from := (fun s => s.(TLBContext)); + write_to := (fun v s => ({[ s with TLBContext := v ]})); + of_regval := (fun v => ContextReg_of_regval v); + regval_of := (fun v => regval_of_ContextReg v) |}. + +Definition TLBEntryLo1_ref := {| + name := "TLBEntryLo1"; + read_from := (fun s => s.(TLBEntryLo1)); + write_to := (fun v s => ({[ s with TLBEntryLo1 := v ]})); + of_regval := (fun v => TLBEntryLoReg_of_regval v); + regval_of := (fun v => regval_of_TLBEntryLoReg v) |}. + +Definition TLBEntryLo0_ref := {| + name := "TLBEntryLo0"; + read_from := (fun s => s.(TLBEntryLo0)); + write_to := (fun v s => ({[ s with TLBEntryLo0 := v ]})); + of_regval := (fun v => TLBEntryLoReg_of_regval v); + regval_of := (fun v => regval_of_TLBEntryLoReg v) |}. + +Definition TLBRandom_ref := {| + name := "TLBRandom"; + read_from := (fun s => s.(TLBRandom)); + write_to := (fun v s => ({[ s with TLBRandom := v ]})); + of_regval := (fun v => vector_6_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_6_dec_bit v) |}. + +Definition TLBIndex_ref := {| + name := "TLBIndex"; + read_from := (fun s => s.(TLBIndex)); + write_to := (fun v s => ({[ s with TLBIndex := v ]})); + of_regval := (fun v => vector_6_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_6_dec_bit v) |}. + +Definition TLBProbe_ref := {| + name := "TLBProbe"; + read_from := (fun s => s.(TLBProbe)); + write_to := (fun v s => ({[ s with TLBProbe := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition NextPC_ref := {| + name := "NextPC"; + read_from := (fun s => s.(NextPC)); + write_to := (fun v s => ({[ s with NextPC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition PC_ref := {| + name := "PC"; + read_from := (fun s => s.(PC)); + write_to := (fun v s => ({[ s with PC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Local Open Scope string. +Definition get_regval (reg_name : string) (s : regstate) : option register_value := + if string_dec reg_name "UART_RVALID" then Some (UART_RVALID_ref.(regval_of) (UART_RVALID_ref.(read_from) s)) else + if string_dec reg_name "UART_RDATA" then Some (UART_RDATA_ref.(regval_of) (UART_RDATA_ref.(read_from) s)) else + if string_dec reg_name "UART_WRITTEN" then Some (UART_WRITTEN_ref.(regval_of) (UART_WRITTEN_ref.(read_from) s)) else + if string_dec reg_name "UART_WDATA" then Some (UART_WDATA_ref.(regval_of) (UART_WDATA_ref.(read_from) s)) else + if string_dec reg_name "GPR" then Some (GPR_ref.(regval_of) (GPR_ref.(read_from) s)) else + if string_dec reg_name "LO" then Some (LO_ref.(regval_of) (LO_ref.(read_from) s)) else + if string_dec reg_name "HI" then Some (HI_ref.(regval_of) (HI_ref.(read_from) s)) else + if string_dec reg_name "DelayedPC" then Some (DelayedPC_ref.(regval_of) (DelayedPC_ref.(read_from) s)) else + if string_dec reg_name "BranchPending" then Some (BranchPending_ref.(regval_of) (BranchPending_ref.(read_from) s)) else + if string_dec reg_name "InBranchDelay" then Some (InBranchDelay_ref.(regval_of) (InBranchDelay_ref.(read_from) s)) else + if string_dec reg_name "NextInBranchDelay" then Some (NextInBranchDelay_ref.(regval_of) (NextInBranchDelay_ref.(read_from) s)) else + if string_dec reg_name "CP0Status" then Some (CP0Status_ref.(regval_of) (CP0Status_ref.(read_from) s)) else + if string_dec reg_name "CP0ConfigK0" then Some (CP0ConfigK0_ref.(regval_of) (CP0ConfigK0_ref.(read_from) s)) else + if string_dec reg_name "CP0UserLocal" then Some (CP0UserLocal_ref.(regval_of) (CP0UserLocal_ref.(read_from) s)) else + if string_dec reg_name "CP0HWREna" then Some (CP0HWREna_ref.(regval_of) (CP0HWREna_ref.(read_from) s)) else + if string_dec reg_name "CP0Count" then Some (CP0Count_ref.(regval_of) (CP0Count_ref.(read_from) s)) else + if string_dec reg_name "CP0BadInstrP" then Some (CP0BadInstrP_ref.(regval_of) (CP0BadInstrP_ref.(read_from) s)) else + if string_dec reg_name "CP0BadInstr" then Some (CP0BadInstr_ref.(regval_of) (CP0BadInstr_ref.(read_from) s)) else + if string_dec reg_name "LastInstrBits" then Some (LastInstrBits_ref.(regval_of) (LastInstrBits_ref.(read_from) s)) else + if string_dec reg_name "CurrentInstrBits" then Some (CurrentInstrBits_ref.(regval_of) (CurrentInstrBits_ref.(read_from) s)) else + if string_dec reg_name "CP0BadVAddr" then Some (CP0BadVAddr_ref.(regval_of) (CP0BadVAddr_ref.(read_from) s)) else + if string_dec reg_name "CP0LLAddr" then Some (CP0LLAddr_ref.(regval_of) (CP0LLAddr_ref.(read_from) s)) else + if string_dec reg_name "CP0LLBit" then Some (CP0LLBit_ref.(regval_of) (CP0LLBit_ref.(read_from) s)) else + if string_dec reg_name "CP0ErrorEPC" then Some (CP0ErrorEPC_ref.(regval_of) (CP0ErrorEPC_ref.(read_from) s)) else + if string_dec reg_name "CP0EPC" then Some (CP0EPC_ref.(regval_of) (CP0EPC_ref.(read_from) s)) else + if string_dec reg_name "CP0Cause" then Some (CP0Cause_ref.(regval_of) (CP0Cause_ref.(read_from) s)) else + if string_dec reg_name "CP0Compare" then Some (CP0Compare_ref.(regval_of) (CP0Compare_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry63" then Some (TLBEntry63_ref.(regval_of) (TLBEntry63_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry62" then Some (TLBEntry62_ref.(regval_of) (TLBEntry62_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry61" then Some (TLBEntry61_ref.(regval_of) (TLBEntry61_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry60" then Some (TLBEntry60_ref.(regval_of) (TLBEntry60_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry59" then Some (TLBEntry59_ref.(regval_of) (TLBEntry59_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry58" then Some (TLBEntry58_ref.(regval_of) (TLBEntry58_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry57" then Some (TLBEntry57_ref.(regval_of) (TLBEntry57_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry56" then Some (TLBEntry56_ref.(regval_of) (TLBEntry56_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry55" then Some (TLBEntry55_ref.(regval_of) (TLBEntry55_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry54" then Some (TLBEntry54_ref.(regval_of) (TLBEntry54_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry53" then Some (TLBEntry53_ref.(regval_of) (TLBEntry53_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry52" then Some (TLBEntry52_ref.(regval_of) (TLBEntry52_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry51" then Some (TLBEntry51_ref.(regval_of) (TLBEntry51_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry50" then Some (TLBEntry50_ref.(regval_of) (TLBEntry50_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry49" then Some (TLBEntry49_ref.(regval_of) (TLBEntry49_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry48" then Some (TLBEntry48_ref.(regval_of) (TLBEntry48_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry47" then Some (TLBEntry47_ref.(regval_of) (TLBEntry47_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry46" then Some (TLBEntry46_ref.(regval_of) (TLBEntry46_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry45" then Some (TLBEntry45_ref.(regval_of) (TLBEntry45_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry44" then Some (TLBEntry44_ref.(regval_of) (TLBEntry44_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry43" then Some (TLBEntry43_ref.(regval_of) (TLBEntry43_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry42" then Some (TLBEntry42_ref.(regval_of) (TLBEntry42_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry41" then Some (TLBEntry41_ref.(regval_of) (TLBEntry41_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry40" then Some (TLBEntry40_ref.(regval_of) (TLBEntry40_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry39" then Some (TLBEntry39_ref.(regval_of) (TLBEntry39_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry38" then Some (TLBEntry38_ref.(regval_of) (TLBEntry38_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry37" then Some (TLBEntry37_ref.(regval_of) (TLBEntry37_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry36" then Some (TLBEntry36_ref.(regval_of) (TLBEntry36_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry35" then Some (TLBEntry35_ref.(regval_of) (TLBEntry35_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry34" then Some (TLBEntry34_ref.(regval_of) (TLBEntry34_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry33" then Some (TLBEntry33_ref.(regval_of) (TLBEntry33_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry32" then Some (TLBEntry32_ref.(regval_of) (TLBEntry32_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry31" then Some (TLBEntry31_ref.(regval_of) (TLBEntry31_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry30" then Some (TLBEntry30_ref.(regval_of) (TLBEntry30_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry29" then Some (TLBEntry29_ref.(regval_of) (TLBEntry29_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry28" then Some (TLBEntry28_ref.(regval_of) (TLBEntry28_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry27" then Some (TLBEntry27_ref.(regval_of) (TLBEntry27_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry26" then Some (TLBEntry26_ref.(regval_of) (TLBEntry26_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry25" then Some (TLBEntry25_ref.(regval_of) (TLBEntry25_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry24" then Some (TLBEntry24_ref.(regval_of) (TLBEntry24_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry23" then Some (TLBEntry23_ref.(regval_of) (TLBEntry23_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry22" then Some (TLBEntry22_ref.(regval_of) (TLBEntry22_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry21" then Some (TLBEntry21_ref.(regval_of) (TLBEntry21_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry20" then Some (TLBEntry20_ref.(regval_of) (TLBEntry20_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry19" then Some (TLBEntry19_ref.(regval_of) (TLBEntry19_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry18" then Some (TLBEntry18_ref.(regval_of) (TLBEntry18_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry17" then Some (TLBEntry17_ref.(regval_of) (TLBEntry17_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry16" then Some (TLBEntry16_ref.(regval_of) (TLBEntry16_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry15" then Some (TLBEntry15_ref.(regval_of) (TLBEntry15_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry14" then Some (TLBEntry14_ref.(regval_of) (TLBEntry14_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry13" then Some (TLBEntry13_ref.(regval_of) (TLBEntry13_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry12" then Some (TLBEntry12_ref.(regval_of) (TLBEntry12_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry11" then Some (TLBEntry11_ref.(regval_of) (TLBEntry11_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry10" then Some (TLBEntry10_ref.(regval_of) (TLBEntry10_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry09" then Some (TLBEntry09_ref.(regval_of) (TLBEntry09_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry08" then Some (TLBEntry08_ref.(regval_of) (TLBEntry08_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry07" then Some (TLBEntry07_ref.(regval_of) (TLBEntry07_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry06" then Some (TLBEntry06_ref.(regval_of) (TLBEntry06_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry05" then Some (TLBEntry05_ref.(regval_of) (TLBEntry05_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry04" then Some (TLBEntry04_ref.(regval_of) (TLBEntry04_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry03" then Some (TLBEntry03_ref.(regval_of) (TLBEntry03_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry02" then Some (TLBEntry02_ref.(regval_of) (TLBEntry02_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry01" then Some (TLBEntry01_ref.(regval_of) (TLBEntry01_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry00" then Some (TLBEntry00_ref.(regval_of) (TLBEntry00_ref.(read_from) s)) else + if string_dec reg_name "TLBXContext" then Some (TLBXContext_ref.(regval_of) (TLBXContext_ref.(read_from) s)) else + if string_dec reg_name "TLBEntryHi" then Some (TLBEntryHi_ref.(regval_of) (TLBEntryHi_ref.(read_from) s)) else + if string_dec reg_name "TLBWired" then Some (TLBWired_ref.(regval_of) (TLBWired_ref.(read_from) s)) else + if string_dec reg_name "TLBPageMask" then Some (TLBPageMask_ref.(regval_of) (TLBPageMask_ref.(read_from) s)) else + if string_dec reg_name "TLBContext" then Some (TLBContext_ref.(regval_of) (TLBContext_ref.(read_from) s)) else + if string_dec reg_name "TLBEntryLo1" then Some (TLBEntryLo1_ref.(regval_of) (TLBEntryLo1_ref.(read_from) s)) else + if string_dec reg_name "TLBEntryLo0" then Some (TLBEntryLo0_ref.(regval_of) (TLBEntryLo0_ref.(read_from) s)) else + if string_dec reg_name "TLBRandom" then Some (TLBRandom_ref.(regval_of) (TLBRandom_ref.(read_from) s)) else + if string_dec reg_name "TLBIndex" then Some (TLBIndex_ref.(regval_of) (TLBIndex_ref.(read_from) s)) else + if string_dec reg_name "TLBProbe" then Some (TLBProbe_ref.(regval_of) (TLBProbe_ref.(read_from) s)) else + if string_dec reg_name "NextPC" then Some (NextPC_ref.(regval_of) (NextPC_ref.(read_from) s)) else + if string_dec reg_name "PC" then Some (PC_ref.(regval_of) (PC_ref.(read_from) s)) else + None. + +Definition set_regval (reg_name : string) (v : register_value) (s : regstate) : option regstate := + if string_dec reg_name "UART_RVALID" then option_map (fun v => UART_RVALID_ref.(write_to) v s) (UART_RVALID_ref.(of_regval) v) else + if string_dec reg_name "UART_RDATA" then option_map (fun v => UART_RDATA_ref.(write_to) v s) (UART_RDATA_ref.(of_regval) v) else + if string_dec reg_name "UART_WRITTEN" then option_map (fun v => UART_WRITTEN_ref.(write_to) v s) (UART_WRITTEN_ref.(of_regval) v) else + if string_dec reg_name "UART_WDATA" then option_map (fun v => UART_WDATA_ref.(write_to) v s) (UART_WDATA_ref.(of_regval) v) else + if string_dec reg_name "GPR" then option_map (fun v => GPR_ref.(write_to) v s) (GPR_ref.(of_regval) v) else + if string_dec reg_name "LO" then option_map (fun v => LO_ref.(write_to) v s) (LO_ref.(of_regval) v) else + if string_dec reg_name "HI" then option_map (fun v => HI_ref.(write_to) v s) (HI_ref.(of_regval) v) else + if string_dec reg_name "DelayedPC" then option_map (fun v => DelayedPC_ref.(write_to) v s) (DelayedPC_ref.(of_regval) v) else + if string_dec reg_name "BranchPending" then option_map (fun v => BranchPending_ref.(write_to) v s) (BranchPending_ref.(of_regval) v) else + if string_dec reg_name "InBranchDelay" then option_map (fun v => InBranchDelay_ref.(write_to) v s) (InBranchDelay_ref.(of_regval) v) else + if string_dec reg_name "NextInBranchDelay" then option_map (fun v => NextInBranchDelay_ref.(write_to) v s) (NextInBranchDelay_ref.(of_regval) v) else + if string_dec reg_name "CP0Status" then option_map (fun v => CP0Status_ref.(write_to) v s) (CP0Status_ref.(of_regval) v) else + if string_dec reg_name "CP0ConfigK0" then option_map (fun v => CP0ConfigK0_ref.(write_to) v s) (CP0ConfigK0_ref.(of_regval) v) else + if string_dec reg_name "CP0UserLocal" then option_map (fun v => CP0UserLocal_ref.(write_to) v s) (CP0UserLocal_ref.(of_regval) v) else + if string_dec reg_name "CP0HWREna" then option_map (fun v => CP0HWREna_ref.(write_to) v s) (CP0HWREna_ref.(of_regval) v) else + if string_dec reg_name "CP0Count" then option_map (fun v => CP0Count_ref.(write_to) v s) (CP0Count_ref.(of_regval) v) else + if string_dec reg_name "CP0BadInstrP" then option_map (fun v => CP0BadInstrP_ref.(write_to) v s) (CP0BadInstrP_ref.(of_regval) v) else + if string_dec reg_name "CP0BadInstr" then option_map (fun v => CP0BadInstr_ref.(write_to) v s) (CP0BadInstr_ref.(of_regval) v) else + if string_dec reg_name "LastInstrBits" then option_map (fun v => LastInstrBits_ref.(write_to) v s) (LastInstrBits_ref.(of_regval) v) else + if string_dec reg_name "CurrentInstrBits" then option_map (fun v => CurrentInstrBits_ref.(write_to) v s) (CurrentInstrBits_ref.(of_regval) v) else + if string_dec reg_name "CP0BadVAddr" then option_map (fun v => CP0BadVAddr_ref.(write_to) v s) (CP0BadVAddr_ref.(of_regval) v) else + if string_dec reg_name "CP0LLAddr" then option_map (fun v => CP0LLAddr_ref.(write_to) v s) (CP0LLAddr_ref.(of_regval) v) else + if string_dec reg_name "CP0LLBit" then option_map (fun v => CP0LLBit_ref.(write_to) v s) (CP0LLBit_ref.(of_regval) v) else + if string_dec reg_name "CP0ErrorEPC" then option_map (fun v => CP0ErrorEPC_ref.(write_to) v s) (CP0ErrorEPC_ref.(of_regval) v) else + if string_dec reg_name "CP0EPC" then option_map (fun v => CP0EPC_ref.(write_to) v s) (CP0EPC_ref.(of_regval) v) else + if string_dec reg_name "CP0Cause" then option_map (fun v => CP0Cause_ref.(write_to) v s) (CP0Cause_ref.(of_regval) v) else + if string_dec reg_name "CP0Compare" then option_map (fun v => CP0Compare_ref.(write_to) v s) (CP0Compare_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry63" then option_map (fun v => TLBEntry63_ref.(write_to) v s) (TLBEntry63_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry62" then option_map (fun v => TLBEntry62_ref.(write_to) v s) (TLBEntry62_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry61" then option_map (fun v => TLBEntry61_ref.(write_to) v s) (TLBEntry61_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry60" then option_map (fun v => TLBEntry60_ref.(write_to) v s) (TLBEntry60_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry59" then option_map (fun v => TLBEntry59_ref.(write_to) v s) (TLBEntry59_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry58" then option_map (fun v => TLBEntry58_ref.(write_to) v s) (TLBEntry58_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry57" then option_map (fun v => TLBEntry57_ref.(write_to) v s) (TLBEntry57_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry56" then option_map (fun v => TLBEntry56_ref.(write_to) v s) (TLBEntry56_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry55" then option_map (fun v => TLBEntry55_ref.(write_to) v s) (TLBEntry55_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry54" then option_map (fun v => TLBEntry54_ref.(write_to) v s) (TLBEntry54_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry53" then option_map (fun v => TLBEntry53_ref.(write_to) v s) (TLBEntry53_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry52" then option_map (fun v => TLBEntry52_ref.(write_to) v s) (TLBEntry52_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry51" then option_map (fun v => TLBEntry51_ref.(write_to) v s) (TLBEntry51_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry50" then option_map (fun v => TLBEntry50_ref.(write_to) v s) (TLBEntry50_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry49" then option_map (fun v => TLBEntry49_ref.(write_to) v s) (TLBEntry49_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry48" then option_map (fun v => TLBEntry48_ref.(write_to) v s) (TLBEntry48_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry47" then option_map (fun v => TLBEntry47_ref.(write_to) v s) (TLBEntry47_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry46" then option_map (fun v => TLBEntry46_ref.(write_to) v s) (TLBEntry46_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry45" then option_map (fun v => TLBEntry45_ref.(write_to) v s) (TLBEntry45_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry44" then option_map (fun v => TLBEntry44_ref.(write_to) v s) (TLBEntry44_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry43" then option_map (fun v => TLBEntry43_ref.(write_to) v s) (TLBEntry43_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry42" then option_map (fun v => TLBEntry42_ref.(write_to) v s) (TLBEntry42_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry41" then option_map (fun v => TLBEntry41_ref.(write_to) v s) (TLBEntry41_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry40" then option_map (fun v => TLBEntry40_ref.(write_to) v s) (TLBEntry40_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry39" then option_map (fun v => TLBEntry39_ref.(write_to) v s) (TLBEntry39_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry38" then option_map (fun v => TLBEntry38_ref.(write_to) v s) (TLBEntry38_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry37" then option_map (fun v => TLBEntry37_ref.(write_to) v s) (TLBEntry37_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry36" then option_map (fun v => TLBEntry36_ref.(write_to) v s) (TLBEntry36_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry35" then option_map (fun v => TLBEntry35_ref.(write_to) v s) (TLBEntry35_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry34" then option_map (fun v => TLBEntry34_ref.(write_to) v s) (TLBEntry34_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry33" then option_map (fun v => TLBEntry33_ref.(write_to) v s) (TLBEntry33_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry32" then option_map (fun v => TLBEntry32_ref.(write_to) v s) (TLBEntry32_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry31" then option_map (fun v => TLBEntry31_ref.(write_to) v s) (TLBEntry31_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry30" then option_map (fun v => TLBEntry30_ref.(write_to) v s) (TLBEntry30_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry29" then option_map (fun v => TLBEntry29_ref.(write_to) v s) (TLBEntry29_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry28" then option_map (fun v => TLBEntry28_ref.(write_to) v s) (TLBEntry28_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry27" then option_map (fun v => TLBEntry27_ref.(write_to) v s) (TLBEntry27_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry26" then option_map (fun v => TLBEntry26_ref.(write_to) v s) (TLBEntry26_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry25" then option_map (fun v => TLBEntry25_ref.(write_to) v s) (TLBEntry25_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry24" then option_map (fun v => TLBEntry24_ref.(write_to) v s) (TLBEntry24_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry23" then option_map (fun v => TLBEntry23_ref.(write_to) v s) (TLBEntry23_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry22" then option_map (fun v => TLBEntry22_ref.(write_to) v s) (TLBEntry22_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry21" then option_map (fun v => TLBEntry21_ref.(write_to) v s) (TLBEntry21_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry20" then option_map (fun v => TLBEntry20_ref.(write_to) v s) (TLBEntry20_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry19" then option_map (fun v => TLBEntry19_ref.(write_to) v s) (TLBEntry19_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry18" then option_map (fun v => TLBEntry18_ref.(write_to) v s) (TLBEntry18_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry17" then option_map (fun v => TLBEntry17_ref.(write_to) v s) (TLBEntry17_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry16" then option_map (fun v => TLBEntry16_ref.(write_to) v s) (TLBEntry16_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry15" then option_map (fun v => TLBEntry15_ref.(write_to) v s) (TLBEntry15_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry14" then option_map (fun v => TLBEntry14_ref.(write_to) v s) (TLBEntry14_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry13" then option_map (fun v => TLBEntry13_ref.(write_to) v s) (TLBEntry13_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry12" then option_map (fun v => TLBEntry12_ref.(write_to) v s) (TLBEntry12_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry11" then option_map (fun v => TLBEntry11_ref.(write_to) v s) (TLBEntry11_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry10" then option_map (fun v => TLBEntry10_ref.(write_to) v s) (TLBEntry10_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry09" then option_map (fun v => TLBEntry09_ref.(write_to) v s) (TLBEntry09_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry08" then option_map (fun v => TLBEntry08_ref.(write_to) v s) (TLBEntry08_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry07" then option_map (fun v => TLBEntry07_ref.(write_to) v s) (TLBEntry07_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry06" then option_map (fun v => TLBEntry06_ref.(write_to) v s) (TLBEntry06_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry05" then option_map (fun v => TLBEntry05_ref.(write_to) v s) (TLBEntry05_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry04" then option_map (fun v => TLBEntry04_ref.(write_to) v s) (TLBEntry04_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry03" then option_map (fun v => TLBEntry03_ref.(write_to) v s) (TLBEntry03_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry02" then option_map (fun v => TLBEntry02_ref.(write_to) v s) (TLBEntry02_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry01" then option_map (fun v => TLBEntry01_ref.(write_to) v s) (TLBEntry01_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry00" then option_map (fun v => TLBEntry00_ref.(write_to) v s) (TLBEntry00_ref.(of_regval) v) else + if string_dec reg_name "TLBXContext" then option_map (fun v => TLBXContext_ref.(write_to) v s) (TLBXContext_ref.(of_regval) v) else + if string_dec reg_name "TLBEntryHi" then option_map (fun v => TLBEntryHi_ref.(write_to) v s) (TLBEntryHi_ref.(of_regval) v) else + if string_dec reg_name "TLBWired" then option_map (fun v => TLBWired_ref.(write_to) v s) (TLBWired_ref.(of_regval) v) else + if string_dec reg_name "TLBPageMask" then option_map (fun v => TLBPageMask_ref.(write_to) v s) (TLBPageMask_ref.(of_regval) v) else + if string_dec reg_name "TLBContext" then option_map (fun v => TLBContext_ref.(write_to) v s) (TLBContext_ref.(of_regval) v) else + if string_dec reg_name "TLBEntryLo1" then option_map (fun v => TLBEntryLo1_ref.(write_to) v s) (TLBEntryLo1_ref.(of_regval) v) else + if string_dec reg_name "TLBEntryLo0" then option_map (fun v => TLBEntryLo0_ref.(write_to) v s) (TLBEntryLo0_ref.(of_regval) v) else + if string_dec reg_name "TLBRandom" then option_map (fun v => TLBRandom_ref.(write_to) v s) (TLBRandom_ref.(of_regval) v) else + if string_dec reg_name "TLBIndex" then option_map (fun v => TLBIndex_ref.(write_to) v s) (TLBIndex_ref.(of_regval) v) else + if string_dec reg_name "TLBProbe" then option_map (fun v => TLBProbe_ref.(write_to) v s) (TLBProbe_ref.(of_regval) v) else + if string_dec reg_name "NextPC" then option_map (fun v => NextPC_ref.(write_to) v s) (NextPC_ref.(of_regval) v) else + if string_dec reg_name "PC" then option_map (fun v => PC_ref.(write_to) v s) (PC_ref.(of_regval) v) else + None. + +Definition register_accessors := (get_regval, set_regval). + + +Definition MR a r := monadR register_value a r exception. +Definition M a := monad register_value a exception. diff --git a/snapshots/coq/clean b/snapshots/coq/clean index 0d6f8785..c37bb40f 100755 --- a/snapshots/coq/clean +++ b/snapshots/coq/clean @@ -1,11 +1,12 @@ #!/bin/bash -if [ ! -d mips ]; then +if [ ! -d cheri-mips ]; then echo Run clean from the coq directory exit 1 fi set -ex -rm -f mips/*.vo +rm -f cheri-mips/*.{vo,glob} cheri-mips/.*.aux +rm -f riscv/*.{vo,glob} riscv/.*.aux cd lib/coq make clean diff --git a/snapshots/coq/lib/coq/Makefile b/snapshots/coq/lib/coq/Makefile index 97869e3c..a5f2874b 100644 --- a/snapshots/coq/lib/coq/Makefile +++ b/snapshots/coq/lib/coq/Makefile @@ -1,6 +1,6 @@ BBV_DIR=../../../bbv/theories -SRC=Sail2_prompt_monad.v Sail2_prompt.v Sail2_impl_base.v Sail2_instr_kinds.v Sail2_operators_bitlists.v Sail2_operators_mwords.v Sail2_operators.v Sail2_values.v Sail2_state_monad.v Sail2_state.v +SRC=Sail2_prompt_monad.v Sail2_prompt.v Sail2_impl_base.v Sail2_instr_kinds.v Sail2_operators_bitlists.v Sail2_operators_mwords.v Sail2_operators.v Sail2_values.v Sail2_state_monad.v Sail2_state.v Sail2_string.v Sail2_real.v COQ_LIBS = -R . Sail -R "$(BBV_DIR)" bbv diff --git a/snapshots/coq/lib/coq/Sail2_impl_base.v b/snapshots/coq/lib/coq/Sail2_impl_base.v index 639083f6..464c2902 100644 --- a/snapshots/coq/lib/coq/Sail2_impl_base.v +++ b/snapshots/coq/lib/coq/Sail2_impl_base.v @@ -1,6 +1,51 @@ (*========================================================================*) -(* Copyright (c) 2018 Sail contributors. *) -(* This material is provided for anonymous review purposes only. *) +(* Sail *) +(* *) +(* Copyright (c) 2013-2017 *) +(* Kathyrn Gray *) +(* Shaked Flur *) +(* Stephen Kell *) +(* Gabriel Kerneis *) +(* Robert Norton-Wright *) +(* Christopher Pulte *) +(* Peter Sewell *) +(* Alasdair Armstrong *) +(* Brian Campbell *) +(* Thomas Bauereiss *) +(* Anthony Fox *) +(* Jon French *) +(* Dominic Mulligan *) +(* Stephen Kell *) +(* Mark Wassell *) +(* *) +(* All rights reserved. *) +(* *) +(* This software was developed by the University of Cambridge Computer *) +(* Laboratory as part of the Rigorous Engineering of Mainstream Systems *) +(* (REMS) project, funded by EPSRC grant EP/K008528/1. *) +(* *) +(* Redistribution and use in source and binary forms, with or without *) +(* modification, are permitted provided that the following conditions *) +(* are met: *) +(* 1. Redistributions of source code must retain the above copyright *) +(* notice, this list of conditions and the following disclaimer. *) +(* 2. Redistributions in binary form must reproduce the above copyright *) +(* notice, this list of conditions and the following disclaimer in *) +(* the documentation and/or other materials provided with the *) +(* distribution. *) +(* *) +(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *) +(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *) +(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *) +(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *) +(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *) +(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *) +(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *) +(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *) +(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *) +(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *) +(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *) +(* SUCH DAMAGE. *) (*========================================================================*) Require Import Sail2_instr_kinds. diff --git a/snapshots/coq/lib/coq/Sail2_instr_kinds.v b/snapshots/coq/lib/coq/Sail2_instr_kinds.v index 0145d8b3..c6fb866b 100644 --- a/snapshots/coq/lib/coq/Sail2_instr_kinds.v +++ b/snapshots/coq/lib/coq/Sail2_instr_kinds.v @@ -1,6 +1,51 @@ (*========================================================================*) -(* Copyright (c) 2018 Sail contributors. *) -(* This material is provided for anonymous review purposes only. *) +(* Sail *) +(* *) +(* Copyright (c) 2013-2017 *) +(* Kathyrn Gray *) +(* Shaked Flur *) +(* Stephen Kell *) +(* Gabriel Kerneis *) +(* Robert Norton-Wright *) +(* Christopher Pulte *) +(* Peter Sewell *) +(* Alasdair Armstrong *) +(* Brian Campbell *) +(* Thomas Bauereiss *) +(* Anthony Fox *) +(* Jon French *) +(* Dominic Mulligan *) +(* Stephen Kell *) +(* Mark Wassell *) +(* *) +(* All rights reserved. *) +(* *) +(* This software was developed by the University of Cambridge Computer *) +(* Laboratory as part of the Rigorous Engineering of Mainstream Systems *) +(* (REMS) project, funded by EPSRC grant EP/K008528/1. *) +(* *) +(* Redistribution and use in source and binary forms, with or without *) +(* modification, are permitted provided that the following conditions *) +(* are met: *) +(* 1. Redistributions of source code must retain the above copyright *) +(* notice, this list of conditions and the following disclaimer. *) +(* 2. Redistributions in binary form must reproduce the above copyright *) +(* notice, this list of conditions and the following disclaimer in *) +(* the documentation and/or other materials provided with the *) +(* distribution. *) +(* *) +(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *) +(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *) +(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *) +(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *) +(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *) +(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *) +(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *) +(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *) +(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *) +(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *) +(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *) +(* SUCH DAMAGE. *) (*========================================================================*) @@ -99,7 +144,7 @@ Inductive barrier_kind := (* AArch64 barriers *) | Barrier_DMB | Barrier_DMB_ST | Barrier_DMB_LD | Barrier_DSB | Barrier_DSB_ST | Barrier_DSB_LD | Barrier_ISB - | Barrier_TM_COMMIT + (* | Barrier_TM_COMMIT*) (* MIPS barriers *) | Barrier_MIPS_SYNC (* RISC-V barriers *) @@ -108,6 +153,11 @@ Inductive barrier_kind := | Barrier_RISCV_r_r | Barrier_RISCV_rw_w | Barrier_RISCV_w_w + | Barrier_RISCV_w_rw + | Barrier_RISCV_rw_r + | Barrier_RISCV_r_w + | Barrier_RISCV_w_r + | Barrier_RISCV_tso | Barrier_RISCV_i (* X86 *) | Barrier_x86_MFENCE. @@ -133,6 +183,11 @@ instance (Show barrier_kind) | Barrier_RISCV_r_r -> "Barrier_RISCV_r_r" | Barrier_RISCV_rw_w -> "Barrier_RISCV_rw_w" | Barrier_RISCV_w_w -> "Barrier_RISCV_w_w" + | Barrier_RISCV_w_rw -> "Barrier_RISCV_w_rw" + | Barrier_RISCV_rw_r -> "Barrier_RISCV_rw_r" + | Barrier_RISCV_r_w -> "Barrier_RISCV_r_w" + | Barrier_RISCV_w_r -> "Barrier_RISCV_w_r" + | Barrier_RISCV_tso -> "Barrier_RISCV_tso" | Barrier_RISCV_i -> "Barrier_RISCV_i" | Barrier_x86_MFENCE -> "Barrier_x86_MFENCE" end @@ -155,11 +210,11 @@ Inductive instruction_kind := | IK_mem_read : read_kind -> instruction_kind | IK_mem_write : write_kind -> instruction_kind | IK_mem_rmw : (read_kind * write_kind) -> instruction_kind - | IK_branch (* this includes conditional-branch (multiple nias, none of which is NIA_indirect_address), + | IK_branch : unit -> instruction_kind (* this includes conditional-branch (multiple nias, none of which is NIA_indirect_address), indirect/computed-branch (single nia of kind NIA_indirect_address) and branch/jump (single nia of kind NIA_concrete_address) *) | IK_trans : trans_kind -> instruction_kind - | IK_simple : instruction_kind. + | IK_simple : unit -> instruction_kind. (* instance (Show instruction_kind) @@ -246,8 +301,13 @@ instance (EnumerationType barrier_kind) | Barrier_RISCV_r_r -> 15 | Barrier_RISCV_rw_w -> 16 | Barrier_RISCV_w_w -> 17 - | Barrier_RISCV_i -> 18 - | Barrier_x86_MFENCE -> 19 + | Barrier_RISCV_w_rw -> 18 + | Barrier_RISCV_rw_r -> 19 + | Barrier_RISCV_r_w -> 20 + | Barrier_RISCV_w_r -> 21 + | Barrier_RISCV_tso -> 22 + | Barrier_RISCV_i -> 23 + | Barrier_x86_MFENCE -> 24 end end *) diff --git a/snapshots/coq/lib/coq/Sail2_operators.v b/snapshots/coq/lib/coq/Sail2_operators.v index 5a8b1119..ab02c4a8 100644 --- a/snapshots/coq/lib/coq/Sail2_operators.v +++ b/snapshots/coq/lib/coq/Sail2_operators.v @@ -1,8 +1,3 @@ -(*========================================================================*) -(* Copyright (c) 2018 Sail contributors. *) -(* This material is provided for anonymous review purposes only. *) -(*========================================================================*) - Require Import Sail2_values. Require List. Import List.ListNotations. diff --git a/snapshots/coq/lib/coq/Sail2_operators_bitlists.v b/snapshots/coq/lib/coq/Sail2_operators_bitlists.v index b0240c4e..dbd8215c 100644 --- a/snapshots/coq/lib/coq/Sail2_operators_bitlists.v +++ b/snapshots/coq/lib/coq/Sail2_operators_bitlists.v @@ -1,8 +1,3 @@ -(*========================================================================*) -(* Copyright (c) 2018 Sail contributors. *) -(* This material is provided for anonymous review purposes only. *) -(*========================================================================*) - Require Import Sail2_values. Require Import Sail2_operators. diff --git a/snapshots/coq/lib/coq/Sail2_operators_mwords.v b/snapshots/coq/lib/coq/Sail2_operators_mwords.v index fba23071..7e4abe29 100644 --- a/snapshots/coq/lib/coq/Sail2_operators_mwords.v +++ b/snapshots/coq/lib/coq/Sail2_operators_mwords.v @@ -1,8 +1,3 @@ -(*========================================================================*) -(* Copyright (c) 2018 Sail contributors. *) -(* This material is provided for anonymous review purposes only. *) -(*========================================================================*) - Require Import Sail2_values. Require Import Sail2_operators. Require Import Sail2_prompt_monad. @@ -14,49 +9,71 @@ Require Import ZArith. Require Import Omega. Require Import Eqdep_dec. -Module Z_eq_dec. -Definition U := Z. -Definition eq_dec := Z.eq_dec. -End Z_eq_dec. -Module ZEqdep := DecidableEqDep (Z_eq_dec). +Fixpoint cast_positive (T : positive -> Type) (p q : positive) : T p -> p = q -> T q. +refine ( +match p, q with +| xH, xH => fun x _ => x +| xO p', xO q' => fun x e => cast_positive (fun x => T (xO x)) p' q' x _ +| xI p', xI q' => fun x e => cast_positive (fun x => T (xI x)) p' q' x _ +| _, _ => _ +end); congruence. +Defined. -Definition cast_mword {m n} (x : mword m) (eq : m = n) : mword n. -rewrite <- eq. -exact x. +Definition cast_T {T : Z -> Type} {m n} : forall (x : T m) (eq : m = n), T n. +refine (match m,n with +| Z0, Z0 => fun x _ => x +| Zneg p1, Zneg p2 => fun x e => cast_positive (fun p => T (Zneg p)) p1 p2 x _ +| Zpos p1, Zpos p2 => fun x e => cast_positive (fun p => T (Zpos p)) p1 p2 x _ +| _,_ => _ +end); congruence. Defined. -Lemma cast_mword_refl {m} {H:m = m} (x : mword m) : cast_mword x H = x. -rewrite (ZEqdep.UIP _ _ H eq_refl). -reflexivity. +Lemma cast_positive_refl : forall p T x (e : p = p), + cast_positive T p p x e = x. +induction p. +* intros. simpl. rewrite IHp; auto. +* intros. simpl. rewrite IHp; auto. +* reflexivity. +Qed. + +Lemma cast_T_refl {T : Z -> Type} {m} {H:m = m} (x : T m) : cast_T x H = x. +destruct m. +* reflexivity. +* simpl. rewrite cast_positive_refl. reflexivity. +* simpl. rewrite cast_positive_refl. reflexivity. Qed. -Definition autocast {m n} (x : mword m) `{H:ArithFact (m = n)} : mword n := - cast_mword x (use_ArithFact H). +Definition autocast {T : Z -> Type} {m n} (x : T m) `{H:ArithFact (m = n)} : T n := + cast_T x (use_ArithFact H). Definition autocast_m {rv e m n} (x : monad rv (mword m) e) `{H:ArithFact (m = n)} : monad rv (mword n) e := - x >>= fun x => returnm (cast_mword x (use_ArithFact H)). + x >>= fun x => returnm (cast_T x (use_ArithFact H)). -Definition cast_word {m n} (x : Word.word m) (eq : m = n) : Word.word n. -rewrite <- eq. -exact x. -Defined. +Definition cast_word {m n} (x : Word.word m) (eq : m = n) : Word.word n := + DepEqNat.nat_cast _ eq x. Lemma cast_word_refl {m} {H:m = m} (x : word m) : cast_word x H = x. rewrite (UIP_refl_nat _ H). -reflexivity. +apply nat_cast_same. Qed. -Definition mword_of_nat {m} (x : Word.word m) : mword (Z.of_nat m). -destruct m. -- exact x. -- simpl. rewrite SuccNat2Pos.id_succ. exact x. +Definition mword_of_nat {m} : Word.word m -> mword (Z.of_nat m). +refine (match m return word m -> mword (Z.of_nat m) with +| O => fun x => x +| S m' => fun x => nat_cast _ _ x +end). +rewrite SuccNat2Pos.id_succ. +reflexivity. Defined. -Definition cast_to_mword {m n} (x : Word.word m) (eq : Z.of_nat m = n) : mword n. -destruct n. -- constructor. -- rewrite <- eq. exact (mword_of_nat x). -- exfalso. destruct m; simpl in *; congruence. +Definition cast_to_mword {m n} (x : Word.word m) : Z.of_nat m = n -> mword n. +refine (match n return Z.of_nat m = n -> mword n with +| Z0 => fun _ => WO +| Zpos p => fun eq => cast_T (mword_of_nat x) eq +| Zneg p => _ +end). +intro eq. +exfalso. destruct m; simpl in *; congruence. Defined. (* @@ -155,16 +172,32 @@ Definition zero_extend {a} (v : mword a) (n : Z) `{ArithFact (n >= a)} : mword n Definition sign_extend {a} (v : mword a) (n : Z) `{ArithFact (n >= a)} : mword n := exts_vec n v. +Definition zeros (n : Z) `{ArithFact (n >= 0)} : mword n. +refine (cast_to_mword (Word.wzero (Z.to_nat n)) _). +unwrap_ArithFacts. +apply Z2Nat.id. +auto with zarith. +Defined. + Lemma truncate_eq {m n} : m >= 0 -> m <= n -> (Z.to_nat n = Z.to_nat m + (Z.to_nat n - Z.to_nat m))%nat. intros. assert ((Z.to_nat m <= Z.to_nat n)%nat). { apply Z2Nat.inj_le; omega. } omega. Qed. +Lemma truncateLSB_eq {m n} : m >= 0 -> m <= n -> (Z.to_nat n = (Z.to_nat n - Z.to_nat m) + Z.to_nat m)%nat. +intros. +assert ((Z.to_nat m <= Z.to_nat n)%nat). +{ apply Z2Nat.inj_le; omega. } +omega. +Qed. Definition vector_truncate {n} (v : mword n) (m : Z) `{ArithFact (m >= 0)} `{ArithFact (m <= n)} : mword m := cast_to_mword (Word.split1 _ _ (cast_word (get_word v) (ltac:(unwrap_ArithFacts; apply truncate_eq; auto) : Z.to_nat n = Z.to_nat m + (Z.to_nat n - Z.to_nat m))%nat)) (ltac:(unwrap_ArithFacts; apply Z2Nat.id; omega) : Z.of_nat (Z.to_nat m) = m). +Definition vector_truncateLSB {n} (v : mword n) (m : Z) `{ArithFact (m >= 0)} `{ArithFact (m <= n)} : mword m := + cast_to_mword (Word.split2 _ _ (cast_word (get_word v) (ltac:(unwrap_ArithFacts; apply truncateLSB_eq; auto) : Z.to_nat n = (Z.to_nat n - Z.to_nat m) + Z.to_nat m)%nat)) (ltac:(unwrap_ArithFacts; apply Z2Nat.id; omega) : Z.of_nat (Z.to_nat m) = m). + Lemma concat_eq {a b} : a >= 0 -> b >= 0 -> Z.of_nat (Z.to_nat b + Z.to_nat a)%nat = a + b. intros. rewrite Nat2Z.inj_add. @@ -421,6 +454,20 @@ Definition sgteq_vec := sgteq_bv. *) +Definition eq_vec_dec {n} : forall (x y : mword n), {x = y} + {x <> y}. +refine (match n with +| Z0 => _ +| Zpos m => _ +| Zneg m => _ +end). +* simpl. apply Word.weq. +* simpl. apply Word.weq. +* simpl. destruct x. +Defined. + +Instance Decidable_eq_mword {n} : forall (x y : mword n), Decidable (x = y) := + Decidable_eq_from_dec eq_vec_dec. + Program Fixpoint reverse_endianness_word {n} (bits : word n) : word n := match n with | S (S (S (S (S (S (S (S m))))))) => @@ -436,3 +483,17 @@ Qed. Definition reverse_endianness {n} (bits : mword n) := with_word (P := id) reverse_endianness_word bits. Definition get_slice_int {a} `{ArithFact (a >= 0)} : Z -> Z -> Z -> mword a := get_slice_int_bv. + +Definition set_slice n m (v : mword n) x (w : mword m) : mword n := + update_subrange_vec_dec v (x + m - 1) x v. + +Definition set_slice_int len n lo (v : mword len) : Z := + let hi := lo + len - 1 in + (* We don't currently have a constraint on lo in the sail prelude, so let's + avoid one here. *) + if sumbool_of_bool (Z.gtb hi 0) then + let bs : mword (hi + 1) := mword_of_int n in + (int_of_mword true (update_subrange_vec_dec bs hi lo v)) + else n. + +Definition prerr_bits {a} (s : string) (bs : mword a) : unit := tt. diff --git a/snapshots/coq/lib/coq/Sail2_prompt.v b/snapshots/coq/lib/coq/Sail2_prompt.v index ab7d5bac..bd0d7750 100644 --- a/snapshots/coq/lib/coq/Sail2_prompt.v +++ b/snapshots/coq/lib/coq/Sail2_prompt.v @@ -1,12 +1,7 @@ -(*========================================================================*) -(* Copyright (c) 2018 Sail contributors. *) -(* This material is provided for anonymous review purposes only. *) -(*========================================================================*) - (*Require Import Sail_impl_base*) Require Import Sail2_values. Require Import Sail2_prompt_monad. - +Require Export ZArith.Zwf. Require Import List. Import ListNotations. (* @@ -35,7 +30,7 @@ match l with foreachM xs vars body end. -Fixpoint foreach_ZM_up' {rv e Vars} from to step off n `{ArithFact (from <= to)} `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e := +Fixpoint foreach_ZM_up' {rv e Vars} from to step off n `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e := if sumbool_of_bool (from + off <=? to) then match n with | O => returnm vars @@ -43,7 +38,7 @@ Fixpoint foreach_ZM_up' {rv e Vars} from to step off n `{ArithFact (from <= to)} end else returnm vars. -Fixpoint foreach_ZM_down' {rv e Vars} from to step off n `{ArithFact (to <= from)} `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e := +Fixpoint foreach_ZM_down' {rv e Vars} from to step off n `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e := if sumbool_of_bool (to <=? from + off) then match n with | O => returnm vars @@ -51,9 +46,9 @@ Fixpoint foreach_ZM_down' {rv e Vars} from to step off n `{ArithFact (to <= from end else returnm vars. -Definition foreach_ZM_up {rv e Vars} from to step vars body `{ArithFact (from <= to)} `{ArithFact (0 < step)} := +Definition foreach_ZM_up {rv e Vars} from to step vars body `{ArithFact (0 < step)} := foreach_ZM_up' (rv := rv) (e := e) (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body. -Definition foreach_ZM_down {rv e Vars} from to step vars body `{ArithFact (to <= from)} `{ArithFact (0 < step)} := +Definition foreach_ZM_down {rv e Vars} from to step vars body `{ArithFact (0 < step)} := foreach_ZM_down' (rv := rv) (e := e) (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body. (*declare {isabelle} termination_argument foreachM = automatic*) @@ -82,6 +77,35 @@ match b with | BU => undefined_bool tt end. +(* For termination of recursive functions. We don't name assertions, so use + the type class mechanism to find it. *) +Definition _limit_reduces {_limit} (_acc:Acc (Zwf 0) _limit) `{ArithFact (_limit >= 0)} : Acc (Zwf 0) (_limit - 1). +refine (Acc_inv _acc _). +destruct H. +red. +omega. +Defined. + +(* A version of well-foundedness of measures with a guard to ensure that + definitions can be reduced without inspecting proofs, based on a coq-club + thread featuring Barras, Gonthier and Gregoire, see + https://sympa.inria.fr/sympa/arc/coq-club/2007-07/msg00014.html *) + +Fixpoint pos_guard_wf {A:Type} {R:A -> A -> Prop} (p:positive) : well_founded R -> well_founded R := + match p with + | xH => fun wfR x => Acc_intro x (fun y _ => wfR y) + | xO p' => fun wfR x => let F := pos_guard_wf p' in Acc_intro x (fun y _ => F (F +wfR) y) + | xI p' => fun wfR x => let F := pos_guard_wf p' in Acc_intro x (fun y _ => F (F +wfR) y) + end. + +Definition Zwf_guarded (z:Z) : Acc (Zwf 0) z := + match z with + | Zpos p => pos_guard_wf p (Zwf_well_founded _) _ + | _ => Zwf_well_founded _ _ + end. + (*val whileM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) -> ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e @@ -120,3 +144,15 @@ let rec untilM vars cond body = write_reg r1 r1_v >> write_reg r2 r2_v*) *) + +(* If we need to build an existential after a monadic operation, assume that + we can do it entirely from the type. *) + +Definition build_ex_m {rv e} {T:Type} (x:monad rv T e) {P:T -> Prop} `{H:forall x, ArithFact (P x)} : monad rv {x : T & ArithFact (P x)} e := + x >>= fun y => returnm (existT _ y (H y)). + +Definition projT1_m {rv e} {T:Type} {P:T -> Prop} (x: monad rv {x : T & P x} e) : monad rv T e := + x >>= fun y => returnm (projT1 y). + +Definition derive_m {rv e} {T:Type} {P Q:T -> Prop} (x : monad rv {x : T & P x} e) `{forall x, ArithFact (P x) -> ArithFact (Q x)} : monad rv {x : T & (ArithFact (Q x))} e := + x >>= fun y => returnm (build_ex (projT1 y)). diff --git a/snapshots/coq/lib/coq/Sail2_prompt_monad.v b/snapshots/coq/lib/coq/Sail2_prompt_monad.v index 43e873f7..2715b5e7 100644 --- a/snapshots/coq/lib/coq/Sail2_prompt_monad.v +++ b/snapshots/coq/lib/coq/Sail2_prompt_monad.v @@ -1,8 +1,3 @@ -(*========================================================================*) -(* Copyright (c) 2018 Sail contributors. *) -(* This material is provided for anonymous review purposes only. *) -(*========================================================================*) - Require Import String. (*Require Import Sail_impl_base*) Require Import Sail2_instr_kinds. diff --git a/snapshots/coq/lib/coq/Sail2_real.v b/snapshots/coq/lib/coq/Sail2_real.v new file mode 100644 index 00000000..e4e4316e --- /dev/null +++ b/snapshots/coq/lib/coq/Sail2_real.v @@ -0,0 +1,24 @@ +Require Export Rbase. +Require Import Reals. +Require Export ROrderedType. +Require Import Sail2_values. + +(* "Decidable" in a classical sense... *) +Instance Decidable_eq_real : forall (x y : R), Decidable (x = y) := + Decidable_eq_from_dec Req_dec. + +Definition realFromFrac (num denom : Z) : R := Rdiv (IZR num) (IZR denom). + +Definition gteq_real (x y : R) : bool := if Rge_dec x y then true else false. +Definition lteq_real (x y : R) : bool := if Rle_dec x y then true else false. +Definition gt_real (x y : R) : bool := if Rgt_dec x y then true else false. +Definition lt_real (x y : R) : bool := if Rlt_dec x y then true else false. + +(* Export select definitions from outside of Rbase *) +Definition powerRZ := powerRZ. +Definition Rabs := Rabs. +Definition sqrt := sqrt. + +(* Use flocq definitions, but without making the whole library a dependency. *) +Definition Zfloor (x : R) := (up x - 1)%Z. +Definition Zceil (x : R) := (- Zfloor (- x))%Z. diff --git a/snapshots/coq/lib/coq/Sail2_state.v b/snapshots/coq/lib/coq/Sail2_state.v index 404309e0..1d5cb342 100644 --- a/snapshots/coq/lib/coq/Sail2_state.v +++ b/snapshots/coq/lib/coq/Sail2_state.v @@ -1,8 +1,3 @@ -(*========================================================================*) -(* Copyright (c) 2018 Sail contributors. *) -(* This material is provided for anonymous review purposes only. *) -(*========================================================================*) - (*Require Import Sail_impl_base*) Require Import Sail2_values. Require Import Sail2_prompt_monad. diff --git a/snapshots/coq/lib/coq/Sail2_state_monad.v b/snapshots/coq/lib/coq/Sail2_state_monad.v index 5258c37a..c48db31b 100644 --- a/snapshots/coq/lib/coq/Sail2_state_monad.v +++ b/snapshots/coq/lib/coq/Sail2_state_monad.v @@ -1,8 +1,3 @@ -(*========================================================================*) -(* Copyright (c) 2018 Sail contributors. *) -(* This material is provided for anonymous review purposes only. *) -(*========================================================================*) - Require Import Sail2_instr_kinds. Require Import Sail2_values. (* diff --git a/snapshots/coq/lib/coq/Sail2_string.v b/snapshots/coq/lib/coq/Sail2_string.v new file mode 100644 index 00000000..0a00f8d7 --- /dev/null +++ b/snapshots/coq/lib/coq/Sail2_string.v @@ -0,0 +1,190 @@ +Require Import Sail2_values. + +Definition string_sub (s : string) (start : Z) (len : Z) : string := + String.substring (Z.to_nat start) (Z.to_nat len) s. + +Definition string_startswith s expected := + let prefix := String.substring 0 (String.length expected) s in + generic_eq prefix expected. + +Definition string_drop s (n : Z) `{ArithFact (n >= 0)} := + let n := Z.to_nat n in + String.substring n (String.length s - n) s. + +Definition string_take s (n : Z) `{ArithFact (n >= 0)} := + let n := Z.to_nat n in + String.substring 0 n s. + +Definition string_length s : {n : Z & ArithFact (n >= 0)} := + build_ex (Z.of_nat (String.length s)). + +Definition string_append := String.append. + +Local Open Scope char_scope. +Local Definition hex_char (c : Ascii.ascii) : option Z := +match c with +| "0" => Some 0 +| "1" => Some 1 +| "2" => Some 2 +| "3" => Some 3 +| "4" => Some 4 +| "5" => Some 5 +| "6" => Some 6 +| "7" => Some 7 +| "8" => Some 8 +| "9" => Some 9 +| "a" => Some 10 +| "b" => Some 11 +| "c" => Some 12 +| "d" => Some 13 +| "e" => Some 14 +| "f" => Some 15 +| _ => None +end. +Local Close Scope char_scope. +Local Fixpoint more_digits (s : string) (base : Z) (acc : Z) (len : nat) : Z * nat := +match s with +| EmptyString => (acc, len) +| String "_" t => more_digits t base acc (S len) +| String h t => + match hex_char h with + | None => (acc, len) + | Some i => + if i = 0)}) := +match s with +| EmptyString => None +| String h t => + match hex_char h with + | None => None + | Some i => + if i = 0)}) := +match s with +| EmptyString => None +| String "0" (String ("x"|"X") t) => int_of t 16 2 +| String "0" (String ("o"|"O") t) => int_of t 8 2 +| String "0" (String ("b"|"B") t) => int_of t 2 2 +| String "0" (String "u" t) => int_of t 10 2 +| String "-" t => + match int_of t 10 1 with + | None => None + | Some (i,len) => Some (-i,len) + end +| _ => int_of s 10 0 +end. + +Definition maybe_int_of_string (s : string) : option Z := +match maybe_int_of_prefix s with +| None => None +| Some (i,len) => + if projT1 len =? projT1 (string_length s) + then Some i + else None +end. + +Fixpoint n_leading_spaces (s:string) : nat := + match s with + | EmptyString => 0 + | String " " t => S (n_leading_spaces t) + | _ => 0 + end. + +Definition opt_spc_matches_prefix s : option (unit * {n : Z & ArithFact (n >= 0)}) := + Some (tt, build_ex (Z.of_nat (n_leading_spaces s))). + +Definition spc_matches_prefix s : option (unit * {n : Z & ArithFact (n >= 0)}) := + match n_leading_spaces s with + | O => None + | S n => Some (tt, build_ex (Z.of_nat (S n))) + end. + +Definition hex_bits_n_matches_prefix sz `{ArithFact (sz >= 0)} s : option (mword sz * {n : Z & ArithFact (n >= 0)}) := + match maybe_int_of_prefix s with + | None => None + | Some (n, len) => + if andb (0 <=? n) (n acc +| S limit' => + let (d,m) := N.div_eucl n 10 in + let acc := String (Ascii.ascii_of_N (m + zero)) acc in + if N.ltb 0 d then string_of_N limit' d acc else acc +end. +Local Fixpoint pos_limit p := +match p with +| xH => S O +| xI p | xO p => S (pos_limit p) +end. +Definition string_of_int (z : Z) : string := +match z with +| Z0 => "0" +| Zpos p => string_of_N (pos_limit p) (Npos p) "" +| Zneg p => String "-" (string_of_N (pos_limit p) (Npos p) "") +end. + +Definition decimal_string_of_bv {a} `{Bitvector a} (bv : a) : string := + match unsigned bv with + | None => "?" + | Some i => string_of_int i + end. + +Definition decimal_string_of_bits {n} (bv : mword n) : string := decimal_string_of_bv bv. + + diff --git a/snapshots/coq/lib/coq/Sail2_values.v b/snapshots/coq/lib/coq/Sail2_values.v index f1f5f1de..219a6f84 100644 --- a/snapshots/coq/lib/coq/Sail2_values.v +++ b/snapshots/coq/lib/coq/Sail2_values.v @@ -1,8 +1,3 @@ -(*========================================================================*) -(* Copyright (c) 2018 Sail contributors. *) -(* This material is provided for anonymous review purposes only. *) -(*========================================================================*) - (* Version of sail_values.lem that uses Lems machine words library *) (*Require Import Sail_impl_base*) @@ -13,10 +8,19 @@ Require Import bbv.Word. Require Export List. Require Export Sumbool. Require Export DecidableClass. +Require Import Eqdep_dec. +Require Export Zeuclid. Import ListNotations. Open Scope Z. +Module Z_eq_dec. +Definition U := Z. +Definition eq_dec := Z.eq_dec. +End Z_eq_dec. +Module ZEqdep := DecidableEqDep (Z_eq_dec). + + (* Constraint solving basics. A HintDb which unfolding hints and lemmata can be added to, and a typeclass to wrap constraint arguments in to trigger automatic solving. *) @@ -26,7 +30,19 @@ Lemma use_ArithFact {P} `(ArithFact P) : P. apply fact. Defined. -Definition build_ex (n:Z) {P:Z -> Prop} `{H:ArithFact (P n)} : {x : Z & ArithFact (P x)} := +(* Allow setoid rewriting through ArithFact *) +Require Import Coq.Classes.Morphisms. +Require Import Coq.Program.Basics. +Require Import Coq.Program.Tactics. +Section Morphism. +Local Obligation Tactic := try solve [simpl_relation | firstorder auto]. + +Global Program Instance ArithFact_iff_morphism : + Proper (iff ==> iff) ArithFact. +End Morphism. + + +Definition build_ex {T:Type} (n:T) {P:T -> Prop} `{H:ArithFact (P n)} : {x : T & ArithFact (P x)} := existT _ n H. Definition generic_eq {T:Type} (x y:T) `{Decidable (x = y)} := Decidable_witness. @@ -59,18 +75,59 @@ Instance Decidable_eq_from_dec {T:Type} (eqdec: forall x y : T, {x = y} + {x <> Decidable_witness := proj1_sig (bool_of_sumbool (eqdec x y)) }. destruct (eqdec x y); simpl; split; congruence. +Defined. + +Instance Decidable_eq_string : forall (x y : string), Decidable (x = y) := + Decidable_eq_from_dec String.string_dec. + +Instance Decidable_eq_pair {A B : Type} `(DA : forall x y : A, Decidable (x = y), DB : forall x y : B, Decidable (x = y)) : forall x y : A*B, Decidable (x = y) := +{ Decidable_witness := andb (@Decidable_witness _ (DA (fst x) (fst y))) +(@Decidable_witness _ (DB (snd x) (snd y))) }. +destruct x as [x1 x2]. +destruct y as [y1 y2]. +simpl. +destruct (DA x1 y1) as [b1 H1]; +destruct (DB x2 y2) as [b2 H2]; +simpl. +split. +* intro H. + apply Bool.andb_true_iff in H. + destruct H as [H1b H2b]. + apply H1 in H1b. + apply H2 in H2b. + congruence. +* intro. inversion H. + subst. + apply Bool.andb_true_iff. + tauto. Qed. +Definition generic_dec {T:Type} (x y:T) `{Decidable (x = y)} : {x = y} + {x <> y}. +refine ((if Decidable_witness as b return (b = true <-> x = y -> _) then fun H' => _ else fun H' => _) Decidable_spec). +* left. tauto. +* right. intuition. +Defined. + +(* Used by generated code that builds Decidable equality instances for records. *) +Ltac cmp_record_field x y := + let H := fresh "H" in + case (generic_dec x y); + intro H; [ | + refine (Build_Decidable _ false _); + split; [congruence | intros Z; destruct H; injection Z; auto] + ]. + + (* Project away range constraints in comparisons *) -Definition ltb_range_l {P} (l : sigT P) r := Z.ltb (projT1 l) r. -Definition leb_range_l {P} (l : sigT P) r := Z.leb (projT1 l) r. -Definition gtb_range_l {P} (l : sigT P) r := Z.gtb (projT1 l) r. -Definition geb_range_l {P} (l : sigT P) r := Z.geb (projT1 l) r. -Definition ltb_range_r {P} l (r : sigT P) := Z.ltb l (projT1 r). -Definition leb_range_r {P} l (r : sigT P) := Z.leb l (projT1 r). -Definition gtb_range_r {P} l (r : sigT P) := Z.gtb l (projT1 r). -Definition geb_range_r {P} l (r : sigT P) := Z.geb l (projT1 r). +Definition ltb_range_l {lo hi} (l : {x & ArithFact (lo <= x /\ x <= hi)}) r := Z.ltb (projT1 l) r. +Definition leb_range_l {lo hi} (l : {x & ArithFact (lo <= x /\ x <= hi)}) r := Z.leb (projT1 l) r. +Definition gtb_range_l {lo hi} (l : {x & ArithFact (lo <= x /\ x <= hi)}) r := Z.gtb (projT1 l) r. +Definition geb_range_l {lo hi} (l : {x & ArithFact (lo <= x /\ x <= hi)}) r := Z.geb (projT1 l) r. +Definition ltb_range_r {lo hi} l (r : {x & ArithFact (lo <= x /\ x <= hi)}) := Z.ltb l (projT1 r). +Definition leb_range_r {lo hi} l (r : {x & ArithFact (lo <= x /\ x <= hi)}) := Z.leb l (projT1 r). +Definition gtb_range_r {lo hi} l (r : {x & ArithFact (lo <= x /\ x <= hi)}) := Z.gtb l (projT1 r). +Definition geb_range_r {lo hi} l (r : {x & ArithFact (lo <= x /\ x <= hi)}) := Z.geb l (projT1 r). Definition ii := Z. Definition nn := nat. @@ -78,7 +135,13 @@ Definition nn := nat. (*val pow : Z -> Z -> Z*) Definition pow m n := m ^ n. -Definition pow2 n := pow 2 n. +Program Definition pow2 n : {z : Z & ArithFact (2 ^ n <= z <= 2 ^ n)} := existT _ (pow 2 n) _. +Next Obligation. +constructor. +unfold pow. +auto using Z.le_refl. +Qed. + (* Definition inline lt := (<) Definition inline gt := (>) @@ -111,7 +174,15 @@ Definition negate_real r := realNegate r Definition abs_real r := realAbs r Definition power_real b e := realPowInteger b e*) +Definition print_endline (_ : string) : unit := tt. +Definition prerr_endline (_ : string) : unit := tt. +Definition prerr (_ : string) : unit := tt. Definition print_int (_ : string) (_ : Z) : unit := tt. +Definition prerr_int (_ : string) (_ : Z) : unit := tt. +Definition putchar (_ : Z) : unit := tt. + +Definition shl_int := Z.shiftl. +Definition shr_int := Z.shiftr. (* Definition or_bool l r := (l || r) @@ -238,9 +309,29 @@ f_equal. auto using just_list_length. Qed. +Fixpoint member_Z_list (x : Z) (l : list Z) : bool := +match l with +| [] => false +| h::t => if x =? h then true else member_Z_list x t +end. + +Lemma member_Z_list_In {x l} : member_Z_list x l = true <-> In x l. +induction l. +* simpl. split. congruence. tauto. +* simpl. destruct (x =? a) eqn:H. + + rewrite Z.eqb_eq in H. subst. tauto. + + rewrite Z.eqb_neq in H. split. + - intro Heq. right. apply IHl. assumption. + - intros [bad | good]. congruence. apply IHl. assumption. +Qed. + (*** Bits *) Inductive bitU := B0 | B1 | BU. +Scheme Equality for bitU. +Instance Decidable_eq_bit : forall (x y : bitU), Decidable (x = y) := + Decidable_eq_from_dec bitU_eq_dec. + Definition showBitU b := match b with | B0 => "O" @@ -829,42 +920,42 @@ val make_the_value : forall n. Z -> itself n Definition inline make_the_value x := the_value *) -Fixpoint bitlistFromWord {n} w := +Fixpoint bitlistFromWord_rev {n} w := match w with | WO => [] -| WS b w => b :: bitlistFromWord w +| WS b w => b :: bitlistFromWord_rev w end. +Definition bitlistFromWord {n} w := + List.rev (@bitlistFromWord_rev n w). -Fixpoint wordFromBitlist l : word (length l) := +Fixpoint wordFromBitlist_rev l : word (length l) := match l with | [] => WO -| b::t => WS b (wordFromBitlist t) +| b::t => WS b (wordFromBitlist_rev t) end. +Definition wordFromBitlist l : word (length l) := + nat_cast _ (List.rev_length l) (wordFromBitlist_rev (List.rev l)). Local Open Scope nat. -Program Definition fit_bbv_word {n m} (w : word n) : word m := -match Nat.compare m n with -| Gt => extz w (m - n) -| Eq => w -| Lt => split2 (n - m) m w -end. -Next Obligation. -symmetry in Heq_anonymous. -apply nat_compare_gt in Heq_anonymous. -omega. -Defined. -Next Obligation. -symmetry in Heq_anonymous. -apply nat_compare_eq in Heq_anonymous. -omega. -Defined. -Next Obligation. +Fixpoint nat_diff {T : nat -> Type} n m {struct n} : +forall + (lt : forall p, T n -> T (n + p)) + (eq : T m -> T m) + (gt : forall p, T (m + p) -> T m), T n -> T m := +(match n, m return (forall p, T n -> T (n + p)) -> (T m -> T m) -> (forall p, T (m + p) -> T m) -> T n -> T m with +| O, O => fun lt eq gt => eq +| S n', O => fun lt eq gt => gt _ +| O, S m' => fun lt eq gt => lt _ +| S n', S m' => @nat_diff (fun x => T (S x)) n' m' +end). + +Definition fit_bbv_word {n m} : word n -> word m := +nat_diff n m + (fun p w => nat_cast _ (Nat.add_comm _ _) (extz w p)) + (fun w => w) + (fun p w => split2 _ _ (nat_cast _ (Nat.add_comm _ _) w)). -symmetry in Heq_anonymous. -apply nat_compare_lt in Heq_anonymous. -omega. -Defined. Local Close Scope nat. (*** Bitvectors *) @@ -896,12 +987,10 @@ Class ReasonableSize (a : Z) : Prop := { isPositive : a >= 0 }. -Hint Resolve -> Z.gtb_lt Z.geb_le Z.ltb_lt Z.leb_le : zbool. -Hint Resolve <- Z.ge_le_iff Z.gt_lt_iff : zbool. - (* Omega doesn't know about In, but can handle disjunctions. *) Ltac unfold_In := repeat match goal with +| H:context [member_Z_list _ _ = true] |- _ => rewrite member_Z_list_In in H | H:context [In ?x (?y :: ?t)] |- _ => change (In x (y :: t)) with (y = x \/ In x t) in H | H:context [In ?x []] |- _ => change (In x []) with False in H end. @@ -912,6 +1001,11 @@ end. Ltac not_Z ty := match ty with Z => fail 1 | _ => idtac end. Ltac clear_non_Z_defns := repeat match goal with H := _ : ?X |- _ => not_Z X; clearbody H end. +Ltac clear_irrelevant_defns := +repeat match goal with X := _ |- _ => + match goal with |- context[X] => idtac end || + match goal with _ : context[X] |- _ => idtac end || clear X +end. Lemma ArithFact_mword (a : Z) (w : mword a) : ArithFact (a >= 0). constructor. @@ -921,7 +1015,7 @@ auto using Z.le_ge, Zle_0_pos. destruct w. Qed. Ltac unwrap_ArithFacts := - repeat match goal with H:(ArithFact _) |- _ => let H' := fresh H in case H as [H'] end. + repeat match goal with H:(ArithFact _) |- _ => let H' := fresh H in case H as [H']; clear H end. Ltac unbool_comparisons := repeat match goal with | H:context [Z.geb _ _] |- _ => rewrite Z.geb_leb in H @@ -933,20 +1027,47 @@ Ltac unbool_comparisons := | H:context [Z.ltb _ _ = false] |- _ => rewrite Z.ltb_ge in H | H:context [Z.eqb _ _ = false] |- _ => rewrite Z.eqb_neq in H | H:context [orb _ _ = true] |- _ => rewrite Bool.orb_true_iff in H - | H:context [andb _ _ = true] |- _ => apply andb_prop in H + | H:context [orb _ _ = false] |- _ => rewrite Bool.orb_false_iff in H + | H:context [andb _ _ = true] |- _ => rewrite Bool.andb_true_iff in H + | H:context [andb _ _ = false] |- _ => rewrite Bool.andb_false_iff in H + | H:context [negb _ = true] |- _ => rewrite Bool.negb_true_iff in H + | H:context [negb _ = false] |- _ => rewrite Bool.negb_false_iff in H | H:context [generic_eq _ _ = true] |- _ => apply generic_eq_true in H | H:context [generic_eq _ _ = false] |- _ => apply generic_eq_false in H | H:context [generic_neq _ _ = true] |- _ => apply generic_neq_true in H | H:context [generic_neq _ _ = false] |- _ => apply generic_neq_false in H end. + (* Split up dependent pairs to get at proofs of properties *) Ltac extract_properties := + (* Properties of local definitions *) repeat match goal with H := (projT1 ?X) |- _ => let x := fresh "x" in let Hx := fresh "Hx" in destruct X as [x Hx] in *; change (projT1 (existT _ x Hx)) with x in *; unfold H in * end; + (* Properties in the goal *) repeat match goal with |- context [projT1 ?X] => + let x := fresh "x" in + let Hx := fresh "Hx" in + destruct X as [x Hx] in *; + change (projT1 (existT _ x Hx)) with x in * end; + (* Properties with proofs embedded by build_ex; uses revert/generalize + rather than destruct because it seemed to be more efficient, but + some experimentation would be needed to be sure. + repeat ( + match goal with H:context [@build_ex ?T ?n ?P ?prf] |- _ => + let x := fresh "x" in + let zz := constr:(@build_ex T n P prf) in + revert dependent H(*; generalize zz; intros*) + end; + match goal with |- context [@build_ex ?T ?n ?P ?prf] => + let x := fresh "x" in + let zz := constr:(@build_ex T n P prf) in + generalize zz as x + end; + intros).*) + repeat match goal with _:context [projT1 ?X] |- _ => let x := fresh "x" in let Hx := fresh "Hx" in destruct X as [x Hx] in *; @@ -972,26 +1093,110 @@ Ltac dump_context := | H:=?X |- _ => idtac H ":=" X; fail | H:?X |- _ => idtac H ":" X; fail end; match goal with |- ?X => idtac "Goal:" X end. -Ltac solve_arithfact := +Ltac split_cases := + repeat match goal with + |- context [match ?X with _ => _ end] => destruct X + end. +Lemma True_left {P:Prop} : (True /\ P) <-> P. +tauto. +Qed. +Lemma True_right {P:Prop} : (P /\ True) <-> P. +tauto. +Qed. + +(* Turn exists into metavariables like eexists, except put in dummy values when + the variable is unused. This is used so that we can use eauto with a low + search bound that doesn't include the exists. (Not terribly happy with + how this works...) *) +Ltac drop_exists := +repeat + match goal with |- @ex Z ?p => + let a := eval hnf in (p 0) in + let b := eval hnf in (p 1) in + match a with b => exists 0 | _ => eexists end + end. +(* + match goal with |- @ex Z (fun x => @?p x) => + let xx := fresh "x" in + evar (xx : Z); + let a := eval hnf in (p xx) in + match a with context [xx] => eexists | _ => exists 0 end; + instantiate (xx := 0); + clear xx + end. +*) + +(* The linear solver doesn't like existentials. *) +Ltac destruct_exists := + repeat match goal with H:@ex Z _ |- _ => destruct H end. + +Ltac prepare_for_solver := (*dump_context;*) + clear_irrelevant_defns; clear_non_Z_defns; + autounfold with sail in * |- *; (* You can add Hint Unfold ... : sail to let omega see through fns *) + split_cases; extract_properties; repeat match goal with w:mword ?n |- _ => apply ArithFact_mword in w end; unwrap_ArithFacts; - unfold_In; - autounfold with sail in * |- *; (* You can add Hint Unfold ... : sail to let omega see through fns *) + destruct_exists; unbool_comparisons; + unfold_In; (* after unbool_comparisons to deal with && and || *) reduce_list_lengths; reduce_pow; + (* omega doesn't cope well with extra "True"s in the goal *) + repeat setoid_rewrite True_left; + repeat setoid_rewrite True_right. + +Lemma trivial_range {x : Z} : ArithFact (x <= x /\ x <= x). +constructor. +auto with zarith. +Qed. + +Lemma ArithFact_self_proof {P} : forall x : {y : Z & ArithFact (P y)}, ArithFact (P (projT1 x)). +intros [x H]. +exact H. +Qed. + +Ltac fill_in_evar_eq := + match goal with |- ArithFact (?x = ?y) => + (is_evar x || is_evar y); + (* compute to allow projections to remove proofs that might not be allowed in the evar *) +(* Disabled because cbn may reduce definitions, even after clearbody + let x := eval cbn in x in + let y := eval cbn in y in*) + idtac "Warning: unknown equality constraint"; constructor; exact (eq_refl _ : x = y) end. + +Ltac solve_arithfact := +(* Attempt a simple proof first to avoid lengthy preparation steps (especially + as the large proof terms can upset subsequent proofs). *) +intros; (* To solve implications for derive_m *) +try (exact trivial_range); +try fill_in_evar_eq; +try match goal with |- context [projT1 ?X] => apply (ArithFact_self_proof X) end; +try (constructor; omega); +prepare_for_solver; (*dump_context;*) - solve [apply ArithFact_mword; assumption - | constructor; omega with Z - (* The datatypes hints give us some list handling, esp In *) - | constructor; auto with datatypes zbool zarith sail]. -Hint Extern 0 (ArithFact _) => solve_arithfact : typeclass_instances. + solve + [ match goal with |- ArithFact (?x _) => is_evar x; idtac "Warning: unknown constraint"; constructor; exact (I : (fun _ => True) _) end + | apply ArithFact_mword; assumption + | constructor; omega with Z + (* Try sail hints before dropping the existential *) + | constructor; eauto 3 with zarith sail + (* The datatypes hints give us some list handling, esp In *) + | constructor; drop_exists; eauto 3 with datatypes zarith sail + | constructor; idtac "Unable to solve constraint"; dump_context; fail + ]. +(* Add an indirection so that you can redefine run_solver to fail to get + slow running constraints into proof mode. *) +Ltac run_solver := solve_arithfact. +Hint Extern 0 (ArithFact _) => run_solver : typeclass_instances. Hint Unfold length_mword : sail. +Definition neq_atom (x : Z) (y : Z) : bool := negb (Z.eqb x y). +Hint Unfold neq_atom : sail. + Lemma ReasonableSize_witness (a : Z) (w : mword a) : ReasonableSize a. constructor. destruct a. @@ -1002,6 +1207,10 @@ Qed. Hint Extern 0 (ReasonableSize ?A) => (unwrap_ArithFacts; solve [apply ReasonableSize_witness; assumption | constructor; omega]) : typeclass_instances. +Definition to_range (x : Z) : {y : Z & ArithFact (x <= y <= x)} := build_ex x. + + + Instance mword_Bitvector {a : Z} `{ArithFact (a >= 0)} : (Bitvector (mword a)) := { bits_of v := List.map bitU_of_bool (bitlistFromWord (get_word v)); of_bits v := option_map (fun bl => to_word isPositive (fit_bbv_word (wordFromBitlist bl))) (just_list (List.map bool_of_bitU v)); @@ -1335,7 +1544,7 @@ Fixpoint foreach_Z' {Vars} from to step n (vars : Vars) (body : Z -> Vars -> Var Definition foreach_Z {Vars} from to step vars body := foreach_Z' (Vars := Vars) from to step (S (Z.abs_nat (from - to))) vars body. -Fixpoint foreach_Z_up' {Vars} from to step off n `{ArithFact (from <= to)} `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> Vars) {struct n} : Vars := +Fixpoint foreach_Z_up' {Vars} from to step off n `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> Vars) {struct n} : Vars := if sumbool_of_bool (from + off <=? to) then match n with | O => vars @@ -1343,7 +1552,7 @@ Fixpoint foreach_Z_up' {Vars} from to step off n `{ArithFact (from <= to)} `{Ari end else vars. -Fixpoint foreach_Z_down' {Vars} from to step off n `{ArithFact (to <= from)} `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> Vars) {struct n} : Vars := +Fixpoint foreach_Z_down' {Vars} from to step off n `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> Vars) {struct n} : Vars := if sumbool_of_bool (to <=? from + off) then match n with | O => vars @@ -1351,9 +1560,9 @@ Fixpoint foreach_Z_down' {Vars} from to step off n `{ArithFact (to <= from)} `{A end else vars. -Definition foreach_Z_up {Vars} from to step vars body `{ArithFact (from <= to)} `{ArithFact (0 < step)} := +Definition foreach_Z_up {Vars} from to step vars body `{ArithFact (0 < step)} := foreach_Z_up' (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body. -Definition foreach_Z_down {Vars} from to step vars body `{ArithFact (to <= from)} `{ArithFact (0 < step)} := +Definition foreach_Z_down {Vars} from to step vars body `{ArithFact (0 < step)} := foreach_Z_down' (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body. (*val while : forall vars. vars -> (vars -> bool) -> (vars -> vars) -> vars @@ -1446,8 +1655,8 @@ end (* Arithmetic functions which return proofs that match the expected Sail types in smt.sail. *) -Definition div_with_eq n m : {o : Z & ArithFact (o = Z.quot n m)} := build_ex (Z.quot n m). -Definition mod_with_eq n m : {o : Z & ArithFact (o = Z.rem n m)} := build_ex (Z.rem n m). +Definition ediv_with_eq n m : {o : Z & ArithFact (o = ZEuclid.div n m)} := build_ex (ZEuclid.div n m). +Definition emod_with_eq n m : {o : Z & ArithFact (o = ZEuclid.modulo n m)} := build_ex (ZEuclid.modulo n m). Definition abs_with_eq n : {o : Z & ArithFact (o = Z.abs n)} := build_ex (Z.abs n). (* Similarly, for ranges (currently in MIPS) *) @@ -1559,6 +1768,20 @@ Qed. Definition list_of_vec {A n} (v : vec A n) : list A := projT1 v. +Definition vec_eq_dec {T n} (D : forall x y : T, {x = y} + {x <> y}) (x y : vec T n) : + {x = y} + {x <> y}. +refine (if List.list_eq_dec D (projT1 x) (projT1 y) then left _ else right _). +* apply eq_sigT_hprop; auto using ZEqdep.UIP. +* contradict n0. rewrite n0. reflexivity. +Defined. + +Instance Decidable_eq_vec {T : Type} {n} `(DT : forall x y : T, Decidable (x = y)) : + forall x y : vec T n, Decidable (x = y) := { + Decidable_witness := proj1_sig (bool_of_sumbool (vec_eq_dec (fun x y => generic_dec x y) x y)) +}. +destruct (vec_eq_dec _ x y); simpl; split; congruence. +Defined. + Program Definition vec_of_list {A} n (l : list A) : option (vec A n) := if sumbool_of_bool (n =? length_list l) then Some (existT _ l _) else None. Next Obligation. @@ -1573,4 +1796,17 @@ Definition map_bind {A B} (f : A -> option B) (a : option A) : option B := match a with | Some a' => f a' | None => None -end. \ No newline at end of file +end. + +Definition sub_nat (x : Z) `{ArithFact (x >= 0)} (y : Z) `{ArithFact (y >= 0)} : + {z : Z & ArithFact (z >= 0)} := + let z := x - y in + if sumbool_of_bool (z >=? 0) then build_ex z else build_ex 0. + +Definition min_nat (x : Z) `{ArithFact (x >= 0)} (y : Z) `{ArithFact (y >= 0)} : + {z : Z & ArithFact (z >= 0)} := + build_ex (Z.min x y). + +Definition max_nat (x : Z) `{ArithFact (x >= 0)} (y : Z) `{ArithFact (y >= 0)} : + {z : Z & ArithFact (z >= 0)} := + build_ex (Z.max x y). diff --git a/snapshots/coq/mips/_CoqProject b/snapshots/coq/mips/_CoqProject deleted file mode 100644 index ad38d28d..00000000 --- a/snapshots/coq/mips/_CoqProject +++ /dev/null @@ -1,2 +0,0 @@ --R ../../bbv/theories bbv --R ../lib/coq Sail \ No newline at end of file diff --git a/snapshots/coq/mips/mips.v b/snapshots/coq/mips/mips.v deleted file mode 100644 index 8d43a6e2..00000000 --- a/snapshots/coq/mips/mips.v +++ /dev/null @@ -1,5890 +0,0 @@ -(*Generated by Sail from mips.*) -Require Import Sail2_instr_kinds. -Require Import Sail2_values. -Require Import Sail2_operators_mwords. -Require Import Sail2_prompt_monad. -Require Import Sail2_prompt. -Require Import Sail2_state. -Require Import mips_types. -Require Import mips_extras. -Import ListNotations. -Open Scope string. -Section Content. - -Definition neq_atom (x : Z) (y : Z) `{ArithFact (x = x)} `{ArithFact (y = y)} -: bool := - negb (Z.eqb x y). - -Definition neq_range {n : Z} {m : Z} {o : Z} {p : Z} '((existT _ x _) : {rangevar : Z & ArithFact (n <= - rangevar /\ - rangevar <= m)}) '((existT _ y _) : {rangevar : Z & ArithFact (o <= rangevar /\ rangevar <= p)}) -: bool := - negb (eq_range (build_ex x) (build_ex y)). - -Definition neq_int (x : Z) (y : Z) : bool := negb (Z.eqb x y). - -Definition neq_bool (x : bool) (y : bool) : bool := negb (Bool.eqb x y). - -Definition undefined_option {a : Type} (typ_a : a) -: M (option a) := - undefined_unit tt >>= fun u_0 => - let u_1 : a := typ_a in - (internal_pick [Some u_1;None]) - : M (option a). - -Definition is_none {a : Type} (opt : option a) -: bool := - match opt with | Some (_) => false | None => true end. - -Definition is_some {a : Type} (opt : option a) -: bool := - match opt with | Some (_) => true | None => false end. - -Definition sail_mask {v0 : Z} (len : Z) (v : mword v0) `{ArithFact (len >= 0 /\ v0 >= 0)} `{ArithFact (len = - len)} -: mword len := - if sumbool_of_bool ((Z.leb len (length_mword v))) then vector_truncate v len - else zero_extend v len. - -Definition neq_vec {n : Z} (x : mword n) (y : mword n) : bool := negb (eq_vec x y). - - - -Definition cast_unit_vec (b : bitU) -: mword 1 := - match b with | B0 => (vec_of_bits [B0] : mword 1) | _ => (vec_of_bits [B1] : mword 1) end. - -Definition __MIPS_write (addr : mword 64) (width : Z) (data : mword (8 * width)) `{ArithFact (width = - width)} -: M (unit) := - (write_ram 64 width - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) addr data) - : M (unit). - -Definition __MIPS_read (addr : mword 64) (width : Z) `{ArithFact (width >= 0)} `{ArithFact (width = - width)} -: M (mword (8 * width)) := - (autocast_m (read_ram 64 width - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) addr)) - : M (mword (8 * width)). - -Definition zopz0zQzQ {n0 : Z} (bs : mword n0) (n : Z) `{ArithFact (n >= 0)} `{ArithFact (n = n)} -: mword (n0 * n) := - replicate_bits bs n. - -Definition undefined_exception '(tt : unit) -: M (exception) := - undefined_string tt >>= fun u_0 => - undefined_unit tt >>= fun u_1 => - (internal_pick - [ISAException u_1;Error_not_implemented u_0;Error_misaligned_access u_1;Error_EBREAK u_1;Error_internal_error u_1]) - : M (exception). - -Definition mips_sign_extend {n : Z} (m__tv : Z) (v : mword n) `{ArithFact (m__tv >= n)} -: mword m__tv := - sign_extend v m__tv. - -Definition mips_zero_extend {n : Z} (m__tv : Z) (v : mword n) `{ArithFact (m__tv >= n)} -: mword m__tv := - zero_extend v m__tv. - -Definition zeros (n__tv : Z) '(tt : unit) `{ArithFact (n__tv >= 0)} -: mword n__tv := - autocast (replicate_bits (vec_of_bits [B0] : mword 1) n__tv). -Arguments zeros _ _ {_}. - -Definition ones (n__tv : Z) '(tt : unit) `{ArithFact (n__tv >= 0)} -: mword n__tv := - autocast (replicate_bits (vec_of_bits [B1] : mword 1) n__tv). -Arguments ones _ _ {_}. - -Definition zopz0zI_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 1)} -: bool := - Z.ltb (projT1 (sint x)) (projT1 (sint y)). - -Definition zopz0zKzJ_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 1)} -: bool := - Z.geb (projT1 (sint x)) (projT1 (sint y)). - -Definition zopz0zI_u {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 0)} -: bool := - Z.ltb (projT1 (uint x)) (projT1 (uint y)). - -Definition zopz0zKzJ_u {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 0)} -: bool := - Z.geb (projT1 (uint x)) (projT1 (uint y)). - -Definition bool_to_bits (x : bool) -: mword 1 := - if (x) then (vec_of_bits [B1] : mword 1) - else (vec_of_bits [B0] : mword 1). - -Definition bit_to_bool (b : bitU) : bool := match b with | B1 => true | _ => false end. - -Definition bits_to_bool (x : mword 1) : bool := bit_to_bool (access_vec_dec x 0). - -Definition to_bits (l : Z) (n : Z) `{ArithFact (l >= 0)} `{ArithFact (l = l)} -: mword l := - get_slice_int l n 0. - -Definition mask {m : Z} (n__tv : Z) (bs : mword m) `{ArithFact (m >= n__tv /\ n__tv >= 1)} -: mword n__tv := - autocast (subrange_vec_dec bs (Z.sub n__tv 1) 0). - -Definition undefined_CauseReg '(tt : unit) -: M (CauseReg) := - undefined_bitvector 32 >>= fun w__0 => - returnm (({| CauseReg_CauseReg_chunk_0 := w__0 |}) - : CauseReg). - -Definition Mk_CauseReg (v : mword 32) -: CauseReg := - {| CauseReg_CauseReg_chunk_0 := (subrange_vec_dec v 31 0) |}. - -Definition _get_CauseReg_bits (v : CauseReg) -: mword 32 := - subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 0. - -Definition _set_CauseReg_bits (r_ref : register_ref regstate register_value CauseReg) (v : mword 32) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - CauseReg_CauseReg_chunk_0 := - (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]} - : CauseReg in - write_reg r_ref r - : M (unit). - -Definition _update_CauseReg_bits (v : CauseReg) (x : mword 32) -: CauseReg := - {[ v with - CauseReg_CauseReg_chunk_0 := - (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}. - -Definition _get_CauseReg_BD (v : CauseReg) -: mword 1 := - subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 31. - -Definition _set_CauseReg_BD (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - CauseReg_CauseReg_chunk_0 := - (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 31 31 (subrange_vec_dec v 0 0)) ]} - : CauseReg in - write_reg r_ref r - : M (unit). - -Definition _update_CauseReg_BD (v : CauseReg) (x : mword 1) -: CauseReg := - {[ v with - CauseReg_CauseReg_chunk_0 := - (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 31 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_CauseReg_CE (v : CauseReg) -: mword 2 := - subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 29 28. - -Definition _set_CauseReg_CE (r_ref : register_ref regstate register_value CauseReg) (v : mword 2) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - CauseReg_CauseReg_chunk_0 := - (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 29 28 (subrange_vec_dec v 1 0)) ]} - : CauseReg in - write_reg r_ref r - : M (unit). - -Definition _update_CauseReg_CE (v : CauseReg) (x : mword 2) -: CauseReg := - {[ v with - CauseReg_CauseReg_chunk_0 := - (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 29 28 (subrange_vec_dec x 1 0)) ]}. - -Definition _get_CauseReg_IV (v : CauseReg) -: mword 1 := - subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 23 23. - -Definition _set_CauseReg_IV (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - CauseReg_CauseReg_chunk_0 := - (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 23 23 (subrange_vec_dec v 0 0)) ]} - : CauseReg in - write_reg r_ref r - : M (unit). - -Definition _update_CauseReg_IV (v : CauseReg) (x : mword 1) -: CauseReg := - {[ v with - CauseReg_CauseReg_chunk_0 := - (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 23 23 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_CauseReg_WP (v : CauseReg) -: mword 1 := - subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 22 22. - -Definition _set_CauseReg_WP (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - CauseReg_CauseReg_chunk_0 := - (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]} - : CauseReg in - write_reg r_ref r - : M (unit). - -Definition _update_CauseReg_WP (v : CauseReg) (x : mword 1) -: CauseReg := - {[ v with - CauseReg_CauseReg_chunk_0 := - (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_CauseReg_IP (v : CauseReg) -: mword 8 := - subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 15 8. - -Definition _set_CauseReg_IP (r_ref : register_ref regstate register_value CauseReg) (v : mword 8) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - CauseReg_CauseReg_chunk_0 := - (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 15 8 (subrange_vec_dec v 7 0)) ]} - : CauseReg in - write_reg r_ref r - : M (unit). - -Definition _update_CauseReg_IP (v : CauseReg) (x : mword 8) -: CauseReg := - {[ v with - CauseReg_CauseReg_chunk_0 := - (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 15 8 (subrange_vec_dec x 7 0)) ]}. - -Definition _get_CauseReg_ExcCode (v : CauseReg) -: mword 5 := - subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 6 2. - -Definition _set_CauseReg_ExcCode (r_ref : register_ref regstate register_value CauseReg) (v : mword 5) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - CauseReg_CauseReg_chunk_0 := - (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 6 2 (subrange_vec_dec v 4 0)) ]} - : CauseReg in - write_reg r_ref r - : M (unit). - -Definition _update_CauseReg_ExcCode (v : CauseReg) (x : mword 5) -: CauseReg := - {[ v with - CauseReg_CauseReg_chunk_0 := - (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 6 2 (subrange_vec_dec x 4 0)) ]}. - -Definition undefined_TLBEntryLoReg '(tt : unit) -: M (TLBEntryLoReg) := - undefined_bitvector 64 >>= fun w__0 => - returnm (({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := w__0 |}) - : TLBEntryLoReg). - -Definition Mk_TLBEntryLoReg (v : mword 64) -: TLBEntryLoReg := - {| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := (subrange_vec_dec v 63 0) |}. - -Definition _get_TLBEntryLoReg_bits (v : TLBEntryLoReg) -: mword 64 := - subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 0. - -Definition _set_TLBEntryLoReg_bits (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 64) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntryLoReg_TLBEntryLoReg_chunk_0 := - (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 0 - (subrange_vec_dec v 63 0)) ]} - : TLBEntryLoReg in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntryLoReg_bits (v : TLBEntryLoReg) (x : mword 64) -: TLBEntryLoReg := - {[ v with - TLBEntryLoReg_TLBEntryLoReg_chunk_0 := - (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 0 - (subrange_vec_dec x 63 0)) ]}. - -Definition _get_TLBEntryLoReg_CapS (v : TLBEntryLoReg) -: mword 1 := - subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 63. - -Definition _set_TLBEntryLoReg_CapS (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntryLoReg_TLBEntryLoReg_chunk_0 := - (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 63 - (subrange_vec_dec v 0 0)) ]} - : TLBEntryLoReg in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntryLoReg_CapS (v : TLBEntryLoReg) (x : mword 1) -: TLBEntryLoReg := - {[ v with - TLBEntryLoReg_TLBEntryLoReg_chunk_0 := - (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 63 - (subrange_vec_dec x 0 0)) ]}. - -Definition _get_TLBEntryLoReg_CapL (v : TLBEntryLoReg) -: mword 1 := - subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 62 62. - -Definition _set_TLBEntryLoReg_CapL (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntryLoReg_TLBEntryLoReg_chunk_0 := - (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 62 62 - (subrange_vec_dec v 0 0)) ]} - : TLBEntryLoReg in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntryLoReg_CapL (v : TLBEntryLoReg) (x : mword 1) -: TLBEntryLoReg := - {[ v with - TLBEntryLoReg_TLBEntryLoReg_chunk_0 := - (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 62 62 - (subrange_vec_dec x 0 0)) ]}. - -Definition _get_TLBEntryLoReg_PFN (v : TLBEntryLoReg) -: mword 24 := - subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 29 6. - -Definition _set_TLBEntryLoReg_PFN (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 24) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntryLoReg_TLBEntryLoReg_chunk_0 := - (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 29 6 - (subrange_vec_dec v 23 0)) ]} - : TLBEntryLoReg in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntryLoReg_PFN (v : TLBEntryLoReg) (x : mword 24) -: TLBEntryLoReg := - {[ v with - TLBEntryLoReg_TLBEntryLoReg_chunk_0 := - (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 29 6 - (subrange_vec_dec x 23 0)) ]}. - -Definition _get_TLBEntryLoReg_C (v : TLBEntryLoReg) -: mword 3 := - subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 5 3. - -Definition _set_TLBEntryLoReg_C (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 3) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntryLoReg_TLBEntryLoReg_chunk_0 := - (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 5 3 - (subrange_vec_dec v 2 0)) ]} - : TLBEntryLoReg in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntryLoReg_C (v : TLBEntryLoReg) (x : mword 3) -: TLBEntryLoReg := - {[ v with - TLBEntryLoReg_TLBEntryLoReg_chunk_0 := - (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 5 3 (subrange_vec_dec x 2 0)) ]}. - -Definition _get_TLBEntryLoReg_D (v : TLBEntryLoReg) -: mword 1 := - subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 2 2. - -Definition _set_TLBEntryLoReg_D (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntryLoReg_TLBEntryLoReg_chunk_0 := - (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 2 2 - (subrange_vec_dec v 0 0)) ]} - : TLBEntryLoReg in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntryLoReg_D (v : TLBEntryLoReg) (x : mword 1) -: TLBEntryLoReg := - {[ v with - TLBEntryLoReg_TLBEntryLoReg_chunk_0 := - (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_TLBEntryLoReg_V (v : TLBEntryLoReg) -: mword 1 := - subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 1 1. - -Definition _set_TLBEntryLoReg_V (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntryLoReg_TLBEntryLoReg_chunk_0 := - (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 1 1 - (subrange_vec_dec v 0 0)) ]} - : TLBEntryLoReg in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntryLoReg_V (v : TLBEntryLoReg) (x : mword 1) -: TLBEntryLoReg := - {[ v with - TLBEntryLoReg_TLBEntryLoReg_chunk_0 := - (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_TLBEntryLoReg_G (v : TLBEntryLoReg) -: mword 1 := - subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 0 0. - -Definition _set_TLBEntryLoReg_G (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntryLoReg_TLBEntryLoReg_chunk_0 := - (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 0 0 - (subrange_vec_dec v 0 0)) ]} - : TLBEntryLoReg in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntryLoReg_G (v : TLBEntryLoReg) (x : mword 1) -: TLBEntryLoReg := - {[ v with - TLBEntryLoReg_TLBEntryLoReg_chunk_0 := - (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. - -Definition undefined_TLBEntryHiReg '(tt : unit) -: M (TLBEntryHiReg) := - undefined_bitvector 64 >>= fun w__0 => - returnm (({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := w__0 |}) - : TLBEntryHiReg). - -Definition Mk_TLBEntryHiReg (v : mword 64) -: TLBEntryHiReg := - {| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := (subrange_vec_dec v 63 0) |}. - -Definition _get_TLBEntryHiReg_bits (v : TLBEntryHiReg) -: mword 64 := - subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 0. - -Definition _set_TLBEntryHiReg_bits (r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 64) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntryHiReg_TLBEntryHiReg_chunk_0 := - (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 0 - (subrange_vec_dec v 63 0)) ]} - : TLBEntryHiReg in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntryHiReg_bits (v : TLBEntryHiReg) (x : mword 64) -: TLBEntryHiReg := - {[ v with - TLBEntryHiReg_TLBEntryHiReg_chunk_0 := - (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 0 - (subrange_vec_dec x 63 0)) ]}. - -Definition _get_TLBEntryHiReg_R (v : TLBEntryHiReg) -: mword 2 := - subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 62. - -Definition _set_TLBEntryHiReg_R (r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 2) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntryHiReg_TLBEntryHiReg_chunk_0 := - (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 62 - (subrange_vec_dec v 1 0)) ]} - : TLBEntryHiReg in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntryHiReg_R (v : TLBEntryHiReg) (x : mword 2) -: TLBEntryHiReg := - {[ v with - TLBEntryHiReg_TLBEntryHiReg_chunk_0 := - (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 62 - (subrange_vec_dec x 1 0)) ]}. - -Definition _get_TLBEntryHiReg_VPN2 (v : TLBEntryHiReg) -: mword 27 := - subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 39 13. - -Definition _set_TLBEntryHiReg_VPN2 (r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 27) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntryHiReg_TLBEntryHiReg_chunk_0 := - (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 39 13 - (subrange_vec_dec v 26 0)) ]} - : TLBEntryHiReg in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntryHiReg_VPN2 (v : TLBEntryHiReg) (x : mword 27) -: TLBEntryHiReg := - {[ v with - TLBEntryHiReg_TLBEntryHiReg_chunk_0 := - (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 39 13 - (subrange_vec_dec x 26 0)) ]}. - -Definition _get_TLBEntryHiReg_ASID (v : TLBEntryHiReg) -: mword 8 := - subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 7 0. - -Definition _set_TLBEntryHiReg_ASID (r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 8) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntryHiReg_TLBEntryHiReg_chunk_0 := - (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 7 0 - (subrange_vec_dec v 7 0)) ]} - : TLBEntryHiReg in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntryHiReg_ASID (v : TLBEntryHiReg) (x : mword 8) -: TLBEntryHiReg := - {[ v with - TLBEntryHiReg_TLBEntryHiReg_chunk_0 := - (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}. - -Definition undefined_ContextReg '(tt : unit) -: M (ContextReg) := - undefined_bitvector 64 >>= fun w__0 => - returnm (({| ContextReg_ContextReg_chunk_0 := w__0 |}) - : ContextReg). - -Definition Mk_ContextReg (v : mword 64) -: ContextReg := - {| ContextReg_ContextReg_chunk_0 := (subrange_vec_dec v 63 0) |}. - -Definition _get_ContextReg_bits (v : ContextReg) -: mword 64 := - subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 0. - -Definition _set_ContextReg_bits (r_ref : register_ref regstate register_value ContextReg) (v : mword 64) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - ContextReg_ContextReg_chunk_0 := - (update_subrange_vec_dec r.(ContextReg_ContextReg_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} - : ContextReg in - write_reg r_ref r - : M (unit). - -Definition _update_ContextReg_bits (v : ContextReg) (x : mword 64) -: ContextReg := - {[ v with - ContextReg_ContextReg_chunk_0 := - (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. - -Definition _get_ContextReg_PTEBase (v : ContextReg) -: mword 41 := - subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 23. - -Definition _set_ContextReg_PTEBase (r_ref : register_ref regstate register_value ContextReg) (v : mword 41) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - ContextReg_ContextReg_chunk_0 := - (update_subrange_vec_dec r.(ContextReg_ContextReg_chunk_0) 63 23 (subrange_vec_dec v 40 0)) ]} - : ContextReg in - write_reg r_ref r - : M (unit). - -Definition _update_ContextReg_PTEBase (v : ContextReg) (x : mword 41) -: ContextReg := - {[ v with - ContextReg_ContextReg_chunk_0 := - (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 23 (subrange_vec_dec x 40 0)) ]}. - -Definition _get_ContextReg_BadVPN2 (v : ContextReg) -: mword 19 := - subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 22 4. - -Definition _set_ContextReg_BadVPN2 (r_ref : register_ref regstate register_value ContextReg) (v : mword 19) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - ContextReg_ContextReg_chunk_0 := - (update_subrange_vec_dec r.(ContextReg_ContextReg_chunk_0) 22 4 (subrange_vec_dec v 18 0)) ]} - : ContextReg in - write_reg r_ref r - : M (unit). - -Definition _update_ContextReg_BadVPN2 (v : ContextReg) (x : mword 19) -: ContextReg := - {[ v with - ContextReg_ContextReg_chunk_0 := - (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 22 4 (subrange_vec_dec x 18 0)) ]}. - -Definition undefined_XContextReg '(tt : unit) -: M (XContextReg) := - undefined_bitvector 64 >>= fun w__0 => - returnm (({| XContextReg_XContextReg_chunk_0 := w__0 |}) - : XContextReg). - -Definition Mk_XContextReg (v : mword 64) -: XContextReg := - {| XContextReg_XContextReg_chunk_0 := (subrange_vec_dec v 63 0) |}. - -Definition _get_XContextReg_bits (v : XContextReg) -: mword 64 := - subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 0. - -Definition _set_XContextReg_bits (r_ref : register_ref regstate register_value XContextReg) (v : mword 64) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - XContextReg_XContextReg_chunk_0 := - (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} - : XContextReg in - write_reg r_ref r - : M (unit). - -Definition _update_XContextReg_bits (v : XContextReg) (x : mword 64) -: XContextReg := - {[ v with - XContextReg_XContextReg_chunk_0 := - (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. - -Definition _get_XContextReg_XPTEBase (v : XContextReg) -: mword 31 := - subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 33. - -Definition _set_XContextReg_XPTEBase (r_ref : register_ref regstate register_value XContextReg) (v : mword 31) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - XContextReg_XContextReg_chunk_0 := - (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 63 33 - (subrange_vec_dec v 30 0)) ]} - : XContextReg in - write_reg r_ref r - : M (unit). - -Definition _update_XContextReg_XPTEBase (v : XContextReg) (x : mword 31) -: XContextReg := - {[ v with - XContextReg_XContextReg_chunk_0 := - (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 33 (subrange_vec_dec x 30 0)) ]}. - -Definition _get_XContextReg_XR (v : XContextReg) -: mword 2 := - subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 32 31. - -Definition _set_XContextReg_XR (r_ref : register_ref regstate register_value XContextReg) (v : mword 2) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - XContextReg_XContextReg_chunk_0 := - (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 32 31 (subrange_vec_dec v 1 0)) ]} - : XContextReg in - write_reg r_ref r - : M (unit). - -Definition _update_XContextReg_XR (v : XContextReg) (x : mword 2) -: XContextReg := - {[ v with - XContextReg_XContextReg_chunk_0 := - (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 32 31 (subrange_vec_dec x 1 0)) ]}. - -Definition _get_XContextReg_XBadVPN2 (v : XContextReg) -: mword 27 := - subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 30 4. - -Definition _set_XContextReg_XBadVPN2 (r_ref : register_ref regstate register_value XContextReg) (v : mword 27) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - XContextReg_XContextReg_chunk_0 := - (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 30 4 (subrange_vec_dec v 26 0)) ]} - : XContextReg in - write_reg r_ref r - : M (unit). - -Definition _update_XContextReg_XBadVPN2 (v : XContextReg) (x : mword 27) -: XContextReg := - {[ v with - XContextReg_XContextReg_chunk_0 := - (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 30 4 (subrange_vec_dec x 26 0)) ]}. - -Definition TLBNumEntries := 64. - -Definition TLBIndexMax : TLBIndexT := (vec_of_bits [B1;B1;B1;B1;B1;B1] : mword 6). - -Definition MAX (n : Z) `{ArithFact (n = n)} : Z := Z.sub (pow2 n) 1. - -Definition MAX_U64 := MAX 64. - -Definition MAX_VA := MAX 40. - -Definition MAX_PA := MAX 36. - -Definition undefined_TLBEntry '(tt : unit) -: M (TLBEntry) := - undefined_bitvector 53 >>= fun w__0 => - undefined_bitvector 64 >>= fun w__1 => - returnm (({| TLBEntry_TLBEntry_chunk_1 := w__0; - TLBEntry_TLBEntry_chunk_0 := w__1 |}) - : TLBEntry). - -Definition Mk_TLBEntry (v : mword 117) -: TLBEntry := - {| TLBEntry_TLBEntry_chunk_1 := (subrange_vec_dec v 116 64); - TLBEntry_TLBEntry_chunk_0 := (subrange_vec_dec v 63 0) |}. - -Definition _get_TLBEntry_bits (v : TLBEntry) -: mword 117 := - concat_vec (subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 0) - (subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 0). - -Definition _set_TLBEntry_bits (r_ref : register_ref regstate register_value TLBEntry) (v : mword 117) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntry_TLBEntry_chunk_1 := - (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 52 0 (subrange_vec_dec v 116 64)) ]} - : TLBEntry in - let r := - {[ r with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} - : TLBEntry in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntry_bits (v : TLBEntry) (x : mword 117) -: TLBEntry := - let v := - {[ v with - TLBEntry_TLBEntry_chunk_1 := - (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 0 (subrange_vec_dec x 116 64)) ]} in - {[ v with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. - -Definition _get_TLBEntry_pagemask (v : TLBEntry) -: mword 16 := - subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 37. - -Definition _set_TLBEntry_pagemask (r_ref : register_ref regstate register_value TLBEntry) (v : mword 16) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntry_TLBEntry_chunk_1 := - (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 52 37 (subrange_vec_dec v 15 0)) ]} - : TLBEntry in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntry_pagemask (v : TLBEntry) (x : mword 16) -: TLBEntry := - {[ v with - TLBEntry_TLBEntry_chunk_1 := - (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 37 (subrange_vec_dec x 15 0)) ]}. - -Definition _get_TLBEntry_r (v : TLBEntry) -: mword 2 := - subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 36 35. - -Definition _set_TLBEntry_r (r_ref : register_ref regstate register_value TLBEntry) (v : mword 2) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntry_TLBEntry_chunk_1 := - (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 36 35 (subrange_vec_dec v 1 0)) ]} - : TLBEntry in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntry_r (v : TLBEntry) (x : mword 2) -: TLBEntry := - {[ v with - TLBEntry_TLBEntry_chunk_1 := - (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 36 35 (subrange_vec_dec x 1 0)) ]}. - -Definition _get_TLBEntry_vpn2 (v : TLBEntry) -: mword 27 := - subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 34 8. - -Definition _set_TLBEntry_vpn2 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 27) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntry_TLBEntry_chunk_1 := - (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 34 8 (subrange_vec_dec v 26 0)) ]} - : TLBEntry in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntry_vpn2 (v : TLBEntry) (x : mword 27) -: TLBEntry := - {[ v with - TLBEntry_TLBEntry_chunk_1 := - (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 34 8 (subrange_vec_dec x 26 0)) ]}. - -Definition _get_TLBEntry_asid (v : TLBEntry) -: mword 8 := - subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 7 0. - -Definition _set_TLBEntry_asid (r_ref : register_ref regstate register_value TLBEntry) (v : mword 8) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntry_TLBEntry_chunk_1 := - (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 7 0 (subrange_vec_dec v 7 0)) ]} - : TLBEntry in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntry_asid (v : TLBEntry) (x : mword 8) -: TLBEntry := - {[ v with - TLBEntry_TLBEntry_chunk_1 := - (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 7 0 (subrange_vec_dec x 7 0)) ]}. - -Definition _get_TLBEntry_g (v : TLBEntry) -: mword 1 := - subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 63. - -Definition _set_TLBEntry_g (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 63 63 (subrange_vec_dec v 0 0)) ]} - : TLBEntry in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntry_g (v : TLBEntry) (x : mword 1) -: TLBEntry := - {[ v with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 63 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_TLBEntry_valid (v : TLBEntry) -: mword 1 := - subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 62 62. - -Definition _set_TLBEntry_valid (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 62 62 (subrange_vec_dec v 0 0)) ]} - : TLBEntry in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntry_valid (v : TLBEntry) (x : mword 1) -: TLBEntry := - {[ v with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 62 62 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_TLBEntry_caps1 (v : TLBEntry) -: mword 1 := - subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 61 61. - -Definition _set_TLBEntry_caps1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 61 61 (subrange_vec_dec v 0 0)) ]} - : TLBEntry in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntry_caps1 (v : TLBEntry) (x : mword 1) -: TLBEntry := - {[ v with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 61 61 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_TLBEntry_capl1 (v : TLBEntry) -: mword 1 := - subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 60 60. - -Definition _set_TLBEntry_capl1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 60 60 (subrange_vec_dec v 0 0)) ]} - : TLBEntry in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntry_capl1 (v : TLBEntry) (x : mword 1) -: TLBEntry := - {[ v with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 60 60 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_TLBEntry_pfn1 (v : TLBEntry) -: mword 24 := - subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 59 36. - -Definition _set_TLBEntry_pfn1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 24) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 59 36 (subrange_vec_dec v 23 0)) ]} - : TLBEntry in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntry_pfn1 (v : TLBEntry) (x : mword 24) -: TLBEntry := - {[ v with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 59 36 (subrange_vec_dec x 23 0)) ]}. - -Definition _get_TLBEntry_c1 (v : TLBEntry) -: mword 3 := - subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 35 33. - -Definition _set_TLBEntry_c1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 3) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 35 33 (subrange_vec_dec v 2 0)) ]} - : TLBEntry in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntry_c1 (v : TLBEntry) (x : mword 3) -: TLBEntry := - {[ v with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 35 33 (subrange_vec_dec x 2 0)) ]}. - -Definition _get_TLBEntry_d1 (v : TLBEntry) -: mword 1 := - subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 32 32. - -Definition _set_TLBEntry_d1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 32 32 (subrange_vec_dec v 0 0)) ]} - : TLBEntry in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntry_d1 (v : TLBEntry) (x : mword 1) -: TLBEntry := - {[ v with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 32 32 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_TLBEntry_v1 (v : TLBEntry) -: mword 1 := - subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 31 31. - -Definition _set_TLBEntry_v1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 31 31 (subrange_vec_dec v 0 0)) ]} - : TLBEntry in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntry_v1 (v : TLBEntry) (x : mword 1) -: TLBEntry := - {[ v with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 31 31 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_TLBEntry_caps0 (v : TLBEntry) -: mword 1 := - subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 30 30. - -Definition _set_TLBEntry_caps0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 30 30 (subrange_vec_dec v 0 0)) ]} - : TLBEntry in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntry_caps0 (v : TLBEntry) (x : mword 1) -: TLBEntry := - {[ v with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 30 30 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_TLBEntry_capl0 (v : TLBEntry) -: mword 1 := - subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 29 29. - -Definition _set_TLBEntry_capl0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 29 29 (subrange_vec_dec v 0 0)) ]} - : TLBEntry in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntry_capl0 (v : TLBEntry) (x : mword 1) -: TLBEntry := - {[ v with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 29 29 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_TLBEntry_pfn0 (v : TLBEntry) -: mword 24 := - subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 28 5. - -Definition _set_TLBEntry_pfn0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 24) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 28 5 (subrange_vec_dec v 23 0)) ]} - : TLBEntry in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntry_pfn0 (v : TLBEntry) (x : mword 24) -: TLBEntry := - {[ v with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 28 5 (subrange_vec_dec x 23 0)) ]}. - -Definition _get_TLBEntry_c0 (v : TLBEntry) -: mword 3 := - subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 4 2. - -Definition _set_TLBEntry_c0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 3) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 4 2 (subrange_vec_dec v 2 0)) ]} - : TLBEntry in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntry_c0 (v : TLBEntry) (x : mword 3) -: TLBEntry := - {[ v with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 4 2 (subrange_vec_dec x 2 0)) ]}. - -Definition _get_TLBEntry_d0 (v : TLBEntry) -: mword 1 := - subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 1 1. - -Definition _set_TLBEntry_d0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} - : TLBEntry in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntry_d0 (v : TLBEntry) (x : mword 1) -: TLBEntry := - {[ v with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_TLBEntry_v0 (v : TLBEntry) -: mword 1 := - subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 0 0. - -Definition _set_TLBEntry_v0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} - : TLBEntry in - write_reg r_ref r - : M (unit). - -Definition _update_TLBEntry_v0 (v : TLBEntry) (x : mword 1) -: TLBEntry := - {[ v with - TLBEntry_TLBEntry_chunk_0 := - (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. - -Definition TLBEntries : vec (register_ref regstate register_value TLBEntry) 64 := -vec_of_list_len [TLBEntry63_ref;TLBEntry62_ref;TLBEntry61_ref;TLBEntry60_ref;TLBEntry59_ref;TLBEntry58_ref;TLBEntry57_ref;TLBEntry56_ref;TLBEntry55_ref;TLBEntry54_ref;TLBEntry53_ref;TLBEntry52_ref;TLBEntry51_ref;TLBEntry50_ref;TLBEntry49_ref;TLBEntry48_ref;TLBEntry47_ref;TLBEntry46_ref;TLBEntry45_ref;TLBEntry44_ref;TLBEntry43_ref; - TLBEntry42_ref;TLBEntry41_ref;TLBEntry40_ref;TLBEntry39_ref;TLBEntry38_ref;TLBEntry37_ref;TLBEntry36_ref;TLBEntry35_ref;TLBEntry34_ref;TLBEntry33_ref;TLBEntry32_ref;TLBEntry31_ref;TLBEntry30_ref;TLBEntry29_ref;TLBEntry28_ref;TLBEntry27_ref;TLBEntry26_ref;TLBEntry25_ref;TLBEntry24_ref;TLBEntry23_ref;TLBEntry22_ref; - TLBEntry21_ref;TLBEntry20_ref;TLBEntry19_ref;TLBEntry18_ref;TLBEntry17_ref;TLBEntry16_ref;TLBEntry15_ref;TLBEntry14_ref;TLBEntry13_ref;TLBEntry12_ref;TLBEntry11_ref;TLBEntry10_ref;TLBEntry09_ref;TLBEntry08_ref;TLBEntry07_ref;TLBEntry06_ref;TLBEntry05_ref;TLBEntry04_ref;TLBEntry03_ref;TLBEntry02_ref;TLBEntry01_ref; - TLBEntry00_ref]. - -Definition undefined_StatusReg '(tt : unit) -: M (StatusReg) := - undefined_bitvector 32 >>= fun w__0 => - returnm (({| StatusReg_StatusReg_chunk_0 := w__0 |}) - : StatusReg). - -Definition Mk_StatusReg (v : mword 32) -: StatusReg := - {| StatusReg_StatusReg_chunk_0 := (subrange_vec_dec v 31 0) |}. - -Definition _get_StatusReg_bits (v : StatusReg) -: mword 32 := - subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 0. - -Definition _set_StatusReg_bits (r_ref : register_ref regstate register_value StatusReg) (v : mword 32) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]} - : StatusReg in - write_reg r_ref r - : M (unit). - -Definition _update_StatusReg_bits (v : StatusReg) (x : mword 32) -: StatusReg := - {[ v with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}. - -Definition _get_StatusReg_CU (v : StatusReg) -: mword 4 := - subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 28. - -Definition _set_StatusReg_CU (r_ref : register_ref regstate register_value StatusReg) (v : mword 4) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 31 28 (subrange_vec_dec v 3 0)) ]} - : StatusReg in - write_reg r_ref r - : M (unit). - -Definition _update_StatusReg_CU (v : StatusReg) (x : mword 4) -: StatusReg := - {[ v with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 28 (subrange_vec_dec x 3 0)) ]}. - -Definition _get_StatusReg_BEV (v : StatusReg) -: mword 1 := - subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 22 22. - -Definition _set_StatusReg_BEV (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]} - : StatusReg in - write_reg r_ref r - : M (unit). - -Definition _update_StatusReg_BEV (v : StatusReg) (x : mword 1) -: StatusReg := - {[ v with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_StatusReg_IM (v : StatusReg) -: mword 8 := - subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 15 8. - -Definition _set_StatusReg_IM (r_ref : register_ref regstate register_value StatusReg) (v : mword 8) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 15 8 (subrange_vec_dec v 7 0)) ]} - : StatusReg in - write_reg r_ref r - : M (unit). - -Definition _update_StatusReg_IM (v : StatusReg) (x : mword 8) -: StatusReg := - {[ v with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 15 8 (subrange_vec_dec x 7 0)) ]}. - -Definition _get_StatusReg_KX (v : StatusReg) -: mword 1 := - subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 7 7. - -Definition _set_StatusReg_KX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} - : StatusReg in - write_reg r_ref r - : M (unit). - -Definition _update_StatusReg_KX (v : StatusReg) (x : mword 1) -: StatusReg := - {[ v with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_StatusReg_SX (v : StatusReg) -: mword 1 := - subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 6 6. - -Definition _set_StatusReg_SX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]} - : StatusReg in - write_reg r_ref r - : M (unit). - -Definition _update_StatusReg_SX (v : StatusReg) (x : mword 1) -: StatusReg := - {[ v with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_StatusReg_UX (v : StatusReg) -: mword 1 := - subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 5 5. - -Definition _set_StatusReg_UX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} - : StatusReg in - write_reg r_ref r - : M (unit). - -Definition _update_StatusReg_UX (v : StatusReg) (x : mword 1) -: StatusReg := - {[ v with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_StatusReg_KSU (v : StatusReg) -: mword 2 := - subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 4 3. - -Definition _set_StatusReg_KSU (r_ref : register_ref regstate register_value StatusReg) (v : mword 2) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 4 3 (subrange_vec_dec v 1 0)) ]} - : StatusReg in - write_reg r_ref r - : M (unit). - -Definition _update_StatusReg_KSU (v : StatusReg) (x : mword 2) -: StatusReg := - {[ v with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 4 3 (subrange_vec_dec x 1 0)) ]}. - -Definition _get_StatusReg_ERL (v : StatusReg) -: mword 1 := - subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 2 2. - -Definition _set_StatusReg_ERL (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]} - : StatusReg in - write_reg r_ref r - : M (unit). - -Definition _update_StatusReg_ERL (v : StatusReg) (x : mword 1) -: StatusReg := - {[ v with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_StatusReg_EXL (v : StatusReg) -: mword 1 := - subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 1 1. - -Definition _set_StatusReg_EXL (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} - : StatusReg in - write_reg r_ref r - : M (unit). - -Definition _update_StatusReg_EXL (v : StatusReg) (x : mword 1) -: StatusReg := - {[ v with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. - -Definition _get_StatusReg_IE (v : StatusReg) -: mword 1 := - subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 0 0. - -Definition _set_StatusReg_IE (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) -: M (unit) := - reg_deref r_ref >>= fun r => - let r := - {[ r with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} - : StatusReg in - write_reg r_ref r - : M (unit). - -Definition _update_StatusReg_IE (v : StatusReg) (x : mword 1) -: StatusReg := - {[ v with - StatusReg_StatusReg_chunk_0 := - (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. - -Definition execute_branch (pc : mword 64) -: M (unit) := - write_reg delayedPC_ref pc >> - write_reg branchPending_ref (vec_of_bits [B1] : mword 1) - : M (unit). - -Definition NotWordVal (word : mword 64) -: bool := - neq_vec (zopz0zQzQ ((cast_unit_vec (access_vec_dec word 31)) : mword 1) 32) - (subrange_vec_dec word 63 32). - -Definition rGPR (idx : mword 5) -: M (mword 64) := - let '(existT _ i _) := uint idx in - (if sumbool_of_bool ((Z.eqb i 0)) then - returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) - : mword 64) - else read_reg GPR_ref >>= fun w__0 => returnm ((vec_access_dec w__0 i) : mword 64)) - : M (mword 64). - -Definition wGPR (idx : mword 5) (v : mword 64) -: M (unit) := - let '(existT _ i _) := uint idx in - (if ((neq_atom i 0)) then - read_reg GPR_ref >>= fun w__0 => write_reg GPR_ref (vec_update_dec w__0 i v) : M (unit) - else returnm (tt : unit)) - : M (unit). - -Definition MEMr (addr : mword 64) (size : Z) `{ArithFact (size >= 0)} `{ArithFact (size = size)} -: M (mword (8 * size)) := - (autocast_m (__MIPS_read addr size)) - : M (mword (8 * size)). - -Definition MEMr_reserve (addr : mword 64) (size : Z) `{ArithFact (size >= 0)} `{ArithFact (size = - size)} -: M (mword (8 * size)) := - (autocast_m (__MIPS_read addr size)) - : M (mword (8 * size)). - -Definition MEM_sync '(tt : unit) : M (unit) := (skip tt) : M (unit). - -Definition MEMea (addr : mword 64) (size : Z) `{ArithFact (size = size)} -: M (unit) := - (skip tt) - : M (unit). - -Definition MEMea_conditional (addr : mword 64) (size : Z) `{ArithFact (size = size)} -: M (unit) := - (skip tt) - : M (unit). - -Definition MEMval (addr : mword 64) (size : Z) (data : mword (8 * size)) `{ArithFact (size = size)} -: M (unit) := - (__MIPS_write addr size data) - : M (unit). - -Definition MEMval_conditional (addr : mword 64) (size : Z) (data : mword (8 * size)) `{ArithFact (size = - size)} -: M (bool) := - __MIPS_write addr size data >> returnm (true : bool). - -Definition Exception_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 18)} `{ArithFact (arg_ = - arg_)} -: Exception := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then Interrupt - else if sumbool_of_bool ((Z.eqb p0_ 1)) then TLBMod - else if sumbool_of_bool ((Z.eqb p0_ 2)) then TLBL - else if sumbool_of_bool ((Z.eqb p0_ 3)) then TLBS - else if sumbool_of_bool ((Z.eqb p0_ 4)) then AdEL - else if sumbool_of_bool ((Z.eqb p0_ 5)) then AdES - else if sumbool_of_bool ((Z.eqb p0_ 6)) then Sys - else if sumbool_of_bool ((Z.eqb p0_ 7)) then Bp - else if sumbool_of_bool ((Z.eqb p0_ 8)) then ResI - else if sumbool_of_bool ((Z.eqb p0_ 9)) then CpU - else if sumbool_of_bool ((Z.eqb p0_ 10)) then Ov - else if sumbool_of_bool ((Z.eqb p0_ 11)) then Tr - else if sumbool_of_bool ((Z.eqb p0_ 12)) then C2E - else if sumbool_of_bool ((Z.eqb p0_ 13)) then C2Trap - else if sumbool_of_bool ((Z.eqb p0_ 14)) then XTLBRefillL - else if sumbool_of_bool ((Z.eqb p0_ 15)) then XTLBRefillS - else if sumbool_of_bool ((Z.eqb p0_ 16)) then XTLBInvL - else if sumbool_of_bool ((Z.eqb p0_ 17)) then XTLBInvS - else MCheck. - -Definition num_of_Exception (arg_ : Exception) -: {e : Z & ArithFact (0 <= e /\ e <= 18)} := - match arg_ with - | Interrupt => build_ex 0 - | TLBMod => build_ex 1 - | TLBL => build_ex 2 - | TLBS => build_ex 3 - | AdEL => build_ex 4 - | AdES => build_ex 5 - | Sys => build_ex 6 - | Bp => build_ex 7 - | ResI => build_ex 8 - | CpU => build_ex 9 - | Ov => build_ex 10 - | Tr => build_ex 11 - | C2E => build_ex 12 - | C2Trap => build_ex 13 - | XTLBRefillL => build_ex 14 - | XTLBRefillS => build_ex 15 - | XTLBInvL => build_ex 16 - | XTLBInvS => build_ex 17 - | MCheck => build_ex 18 - end. - -Definition undefined_Exception '(tt : unit) -: M (Exception) := - (internal_pick - [Interrupt;TLBMod;TLBL;TLBS;AdEL;AdES;Sys;Bp;ResI;CpU;Ov;Tr;C2E;C2Trap;XTLBRefillL;XTLBRefillS;XTLBInvL;XTLBInvS;MCheck]) - : M (Exception). - -Definition ExceptionCode (ex : Exception) -: mword 5 := - let x : bits 8 := - match ex with - | Interrupt => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8) - | TLBMod => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : mword 8) - | TLBL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : mword 8) - | TLBS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : mword 8) - | AdEL => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : mword 8) - | AdES => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : mword 8) - | Sys => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : mword 8) - | Bp => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : mword 8) - | ResI => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0] : mword 8) - | CpU => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1] : mword 8) - | Ov => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B0] : mword 8) - | Tr => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B1] : mword 8) - | C2E => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : mword 8) - | C2Trap => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : mword 8) - | XTLBRefillL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : mword 8) - | XTLBRefillS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : mword 8) - | XTLBInvL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : mword 8) - | XTLBInvS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : mword 8) - | MCheck => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0] : mword 8) - end in - subrange_vec_dec x 4 0. - -Definition SignalExceptionMIPS {o : Type} (ex : Exception) (kccBase : mword 64) -: M (o) := - read_reg CP0Status_ref >>= fun w__0 => - (if ((negb ((bits_to_bool (_get_StatusReg_EXL w__0)) : bool))) then - (read_reg inBranchDelay_ref : M (mword 1)) >>= fun w__1 => - (if (((bit_to_bool (access_vec_dec w__1 0)) : bool)) then - (read_reg PC_ref : M (mword 64)) >>= fun w__2 => - write_reg CP0EPC_ref (sub_vec_int w__2 4) >> - (_set_CauseReg_BD CP0Cause_ref (vec_of_bits [B1] : mword 1)) - : M (unit) - else - (read_reg PC_ref : M (mword 64)) >>= fun w__3 => - write_reg CP0EPC_ref w__3 >> - (_set_CauseReg_BD CP0Cause_ref (vec_of_bits [B0] : mword 1)) - : M (unit)) - : M (unit) - else returnm (tt : unit)) >> - read_reg CP0Status_ref >>= fun w__4 => - let vectorOffset := - if (((bits_to_bool (_get_StatusReg_EXL w__4)) : bool)) then - (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) - else if ((orb (generic_eq ex XTLBRefillL) (generic_eq ex XTLBRefillS))) then - (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) - else if ((generic_eq ex C2Trap)) then - (vec_of_bits [B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) - else (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) in - read_reg CP0Status_ref >>= fun w__5 => - let vectorBase : bits 64 := - if (((bits_to_bool (_get_StatusReg_BEV w__5)) : bool)) then - (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; - B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) - else - (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; - B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) in - write_reg nextPC_ref (sub_vec (add_vec vectorBase (mips_sign_extend 64 vectorOffset)) kccBase) >> - _set_CauseReg_ExcCode CP0Cause_ref (ExceptionCode ex) >> - _set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1] : mword 1) >> - (throw (ISAException tt)) - : M (o). - -Definition SignalException {o : Type} (ex : Exception) -: M (o) := - (SignalExceptionMIPS ex - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64)) - : M (o). - -Definition SignalExceptionBadAddr {o : Type} (ex : Exception) (badAddr : mword 64) -: M (o) := - write_reg CP0BadVAddr_ref badAddr >> (SignalException ex) : M (o). - -Definition SignalExceptionTLB {o : Type} (ex : Exception) (badAddr : mword 64) -: M (o) := - write_reg CP0BadVAddr_ref badAddr >> - _set_ContextReg_BadVPN2 TLBContext_ref (subrange_vec_dec badAddr 31 13) >> - _set_XContextReg_XBadVPN2 TLBXContext_ref (subrange_vec_dec badAddr 39 13) >> - _set_XContextReg_XR TLBXContext_ref (subrange_vec_dec badAddr 63 62) >> - _set_TLBEntryHiReg_R TLBEntryHi_ref (subrange_vec_dec badAddr 63 62) >> - _set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (subrange_vec_dec badAddr 39 13) >> - (SignalException ex) - : M (o). - -Definition MemAccessType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} `{ArithFact (arg_ = - arg_)} -: MemAccessType := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then Instruction - else if sumbool_of_bool ((Z.eqb p0_ 1)) then LoadData - else StoreData. - -Definition num_of_MemAccessType (arg_ : MemAccessType) -: {e : Z & ArithFact (0 <= e /\ e <= 2)} := - match arg_ with - | Instruction => build_ex 0 - | LoadData => build_ex 1 - | StoreData => build_ex 2 - end. - -Definition undefined_MemAccessType '(tt : unit) -: M (MemAccessType) := - (internal_pick [Instruction;LoadData;StoreData]) - : M (MemAccessType). - -Definition AccessLevel_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} `{ArithFact (arg_ = - arg_)} -: AccessLevel := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then User - else if sumbool_of_bool ((Z.eqb p0_ 1)) then Supervisor - else Kernel. - -Definition num_of_AccessLevel (arg_ : AccessLevel) -: {e : Z & ArithFact (0 <= e /\ e <= 2)} := - match arg_ with | User => build_ex 0 | Supervisor => build_ex 1 | Kernel => build_ex 2 end. - -Definition undefined_AccessLevel '(tt : unit) -: M (AccessLevel) := - (internal_pick [User;Supervisor;Kernel]) - : M (AccessLevel). - -Definition int_of_AccessLevel (level : AccessLevel) -: Z := - match level with | User => 0 | Supervisor => 1 | Kernel => 2 end. - -Definition grantsAccess (currentLevel : AccessLevel) (requiredLevel : AccessLevel) -: bool := - Z.geb (int_of_AccessLevel currentLevel) (int_of_AccessLevel requiredLevel). - -Definition getAccessLevel '(tt : unit) -: M (AccessLevel) := - or_boolM - (read_reg CP0Status_ref >>= fun w__0 => - returnm ((bits_to_bool (_get_StatusReg_EXL w__0)) - : bool)) - (read_reg CP0Status_ref >>= fun w__1 => - returnm ((bits_to_bool (_get_StatusReg_ERL w__1)) - : bool)) >>= fun w__2 => - (if (w__2) then returnm (Kernel : AccessLevel) - else - read_reg CP0Status_ref >>= fun w__3 => - let p__27 := _get_StatusReg_KSU w__3 in - let b__0 := p__27 in - returnm ((if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then Kernel - else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then Supervisor - else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then User - else User) - : AccessLevel)) - : M (AccessLevel). - -Definition checkCP0Access '(tt : unit) -: M (unit) := - getAccessLevel tt >>= fun accessLevel => - and_boolM (returnm ((generic_neq accessLevel Kernel) : bool)) - (read_reg CP0Status_ref >>= fun w__0 => - returnm ((negb ((bit_to_bool (access_vec_dec (_get_StatusReg_CU w__0) 0)) : bool)) - : bool)) >>= fun w__1 => - (if (w__1) then - _set_CauseReg_CE CP0Cause_ref (vec_of_bits [B0;B0] : mword 2) >> - (SignalException CpU) - : M (unit) - else returnm (tt : unit)) - : M (unit). - -Definition incrementCP0Count '(tt : unit) -: M (unit) := - (read_reg TLBRandom_ref : M (mword 6)) >>= fun w__0 => - (read_reg TLBWired_ref : M (mword 6)) >>= fun w__1 => - (if ((eq_vec w__0 w__1)) then returnm (TLBIndexMax : TLBIndexT) - else - (read_reg TLBRandom_ref : M (mword 6)) >>= fun w__2 => - returnm ((sub_vec_int w__2 1) - : TLBIndexT)) >>= fun w__3 => - write_reg TLBRandom_ref w__3 >> - (read_reg CP0Count_ref : M (mword 32)) >>= fun w__4 => - write_reg CP0Count_ref (add_vec_int w__4 1) >> - (read_reg CP0Count_ref : M (mword 32)) >>= fun w__5 => - (read_reg CP0Compare_ref : M (mword 32)) >>= fun w__6 => - (if ((eq_vec w__5 w__6)) then - read_reg CP0Cause_ref >>= fun w__7 => - (_set_CauseReg_IP CP0Cause_ref - (or_vec (_get_CauseReg_IP w__7) (vec_of_bits [B1;B0;B0;B0;B0;B0;B0;B0] : mword 8))) - : M (unit) - else returnm (tt : unit)) >> - read_reg CP0Status_ref >>= fun w__8 => - let ims := _get_StatusReg_IM w__8 in - read_reg CP0Cause_ref >>= fun w__9 => - let ips := _get_CauseReg_IP w__9 in - read_reg CP0Status_ref >>= fun w__10 => - let ie := _get_StatusReg_IE w__10 in - read_reg CP0Status_ref >>= fun w__11 => - let exl := _get_StatusReg_EXL w__11 in - read_reg CP0Status_ref >>= fun w__12 => - let erl := _get_StatusReg_ERL w__12 in - (if ((andb (negb ((bits_to_bool exl) : bool)) - (andb (negb ((bits_to_bool erl) : bool)) - (andb ((bits_to_bool ie) : bool) - (neq_vec (and_vec ips ims) (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8)))))) - then - (SignalException Interrupt) - : M (unit) - else returnm (tt : unit)) - : M (unit). - -Definition decode_failure_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} `{ArithFact (arg_ = - arg_)} -: decode_failure := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then no_matching_pattern - else if sumbool_of_bool ((Z.eqb p0_ 1)) then unsupported_instruction - else if sumbool_of_bool ((Z.eqb p0_ 2)) then illegal_instruction - else internal_error. - -Definition num_of_decode_failure (arg_ : decode_failure) -: {e : Z & ArithFact (0 <= e /\ e <= 3)} := - match arg_ with - | no_matching_pattern => build_ex 0 - | unsupported_instruction => build_ex 1 - | illegal_instruction => build_ex 2 - | internal_error => build_ex 3 - end. - -Definition undefined_decode_failure '(tt : unit) -: M (decode_failure) := - (internal_pick [no_matching_pattern;unsupported_instruction;illegal_instruction;internal_error]) - : M (decode_failure). - -Definition Comparison_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 7)} `{ArithFact (arg_ = - arg_)} -: Comparison := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then EQ' - else if sumbool_of_bool ((Z.eqb p0_ 1)) then NE - else if sumbool_of_bool ((Z.eqb p0_ 2)) then GE - else if sumbool_of_bool ((Z.eqb p0_ 3)) then GEU - else if sumbool_of_bool ((Z.eqb p0_ 4)) then GT' - else if sumbool_of_bool ((Z.eqb p0_ 5)) then LE - else if sumbool_of_bool ((Z.eqb p0_ 6)) then LT' - else LTU. - -Definition num_of_Comparison (arg_ : Comparison) -: {e : Z & ArithFact (0 <= e /\ e <= 7)} := - match arg_ with - | EQ' => build_ex 0 - | NE => build_ex 1 - | GE => build_ex 2 - | GEU => build_ex 3 - | GT' => build_ex 4 - | LE => build_ex 5 - | LT' => build_ex 6 - | LTU => build_ex 7 - end. - -Definition undefined_Comparison '(tt : unit) -: M (Comparison) := - (internal_pick [EQ';NE;GE;GEU;GT';LE;LT';LTU]) - : M (Comparison). - -Definition compare (cmp : Comparison) (valA : mword 64) (valB : mword 64) -: bool := - match cmp with - | EQ' => eq_vec valA valB - | NE => neq_vec valA valB - | GE => zopz0zKzJ_s valA valB - | GEU => zopz0zKzJ_u valA valB - | GT' => zopz0zI_s valB valA - | LE => zopz0zKzJ_s valB valA - | LT' => zopz0zI_s valA valB - | LTU => zopz0zI_u valA valB - end. - -Definition WordType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} `{ArithFact (arg_ = arg_)} -: WordType := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then B - else if sumbool_of_bool ((Z.eqb p0_ 1)) then H - else if sumbool_of_bool ((Z.eqb p0_ 2)) then W - else D. - -Definition num_of_WordType (arg_ : WordType) -: {e : Z & ArithFact (0 <= e /\ e <= 3)} := - match arg_ with | B => build_ex 0 | H => build_ex 1 | W => build_ex 2 | D => build_ex 3 end. - -Definition undefined_WordType '(tt : unit) -: M (WordType) := - (internal_pick [B;H;W;D]) - : M (WordType). - -Definition WordTypeUnaligned_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} `{ArithFact (arg_ = - arg_)} -: WordTypeUnaligned := - let p0_ := arg_ in - if sumbool_of_bool ((Z.eqb p0_ 0)) then WL - else if sumbool_of_bool ((Z.eqb p0_ 1)) then WR - else if sumbool_of_bool ((Z.eqb p0_ 2)) then DL - else DR. - -Definition num_of_WordTypeUnaligned (arg_ : WordTypeUnaligned) -: {e : Z & ArithFact (0 <= e /\ e <= 3)} := - match arg_ with | WL => build_ex 0 | WR => build_ex 1 | DL => build_ex 2 | DR => build_ex 3 end. - -Definition undefined_WordTypeUnaligned '(tt : unit) -: M (WordTypeUnaligned) := - (internal_pick [WL;WR;DL;DR]) - : M (WordTypeUnaligned). - -Definition wordWidthBytes (w : WordType) -: {rangevar : Z & ArithFact (1 <= rangevar /\ rangevar <= 8)} := - match w with | B => build_ex 1 | H => build_ex 2 | W => build_ex 4 | D => build_ex 8 end. - -Definition alignment_width := 16. - -Definition isAddressAligned (addr : mword 64) (wordType : WordType) -: bool := - let '(existT _ a _) := uint addr in - Z.eqb (projT1 (div_with_eq a alignment_width)) - (Z.quot (Z.sub (Z.add a (projT1 (wordWidthBytes wordType))) 1) alignment_width). - -Definition MEMr_wrapper (addr : mword 64) (size : Z) `{ArithFact (1 <= size /\ size <= 8)} `{ArithFact (size = - size)} -: M (mword (8 * size)) := - (if ((eq_vec addr - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64))) then - (read_reg UART_RVALID_ref : M (mword 1)) >>= fun rvalid => - write_reg UART_RVALID_ref (vec_of_bits [B0] : mword 1) >> - (read_reg UART_RDATA_ref : M (mword 8)) >>= fun w__0 => - returnm ((mask (Z.mul 8 size) - (concat_vec - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 32) - (concat_vec w__0 - (concat_vec rvalid - (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 16)))))) - : mword (8 * size)) - else if ((eq_vec addr - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0; - B0] - : mword 64))) then - returnm ((mask (Z.mul 8 size) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B1;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; - B1] - : mword 64)) - : mword (8 * size)) - else - autocast_m (MEMr addr size) >>= fun w__1 => - returnm ((autocast (reverse_endianness w__1)) - : mword (8 * size))) - : M (mword (8 * size)). - -Definition MEMr_reserve_wrapper (addr : mword 64) (size : Z) `{ArithFact (1 <= size /\ size <= 8)} `{ArithFact (size = - size)} -: M (mword (8 * size)) := - autocast_m (MEMr_reserve addr size) >>= fun w__0 => - returnm ((autocast (reverse_endianness w__0)) - : mword (8 * size)). - -Definition init_cp0_state '(tt : unit) -: M (unit) := - (_set_StatusReg_BEV CP0Status_ref ((cast_unit_vec B1) : mword 1)) - : M (unit). - -Definition tlbEntryMatch (r : mword 2) (vpn2 : mword 27) (asid : mword 8) (entry : TLBEntry) -: bool := - let entryValid := _get_TLBEntry_valid entry in - let entryR := _get_TLBEntry_r entry in - let entryMask := _get_TLBEntry_pagemask entry in - let entryVPN := _get_TLBEntry_vpn2 entry in - let entryASID := _get_TLBEntry_asid entry in - let entryG := _get_TLBEntry_g entry in - let vpnMask : bits 27 := not_vec (mips_zero_extend 27 entryMask) in - andb ((bits_to_bool entryValid) : bool) - (andb (eq_vec r entryR) - (andb (eq_vec (and_vec vpn2 vpnMask) (and_vec entryVPN vpnMask)) - (orb (eq_vec asid entryASID) ((bits_to_bool entryG) : bool)))). - -Definition tlbSearch (VAddr : mword 64) -: M (option (mword 6)) := - catch_early_return - (let r := subrange_vec_dec VAddr 63 62 in - let vpn2 := subrange_vec_dec VAddr 39 13 in - liftR (read_reg TLBEntryHi_ref) >>= fun w__0 => - let asid := _get_TLBEntryHiReg_ASID w__0 in - (foreach_ZM_up 0 63 1 tt - (fun idx _ unit_var => - liftR (reg_deref (vec_access_dec TLBEntries idx)) >>= fun w__1 => - (if ((tlbEntryMatch r vpn2 asid w__1)) then - (early_return ((Some (to_bits 6 idx)) : option (mword 6)) : MR unit (option (mword 6))) - : MR (unit) _ - else returnm (tt : unit)) - : MR (unit) _)) >> - returnm (None - : option (mword 6))). - -Definition TLBTranslate2 (vAddr : mword 64) (accessType : MemAccessType) -: M ((mword 64 * bool)) := - tlbSearch vAddr >>= fun idx => - (match idx with - | Some (idx) => - let '(existT _ i _) := uint idx in - reg_deref (vec_access_dec TLBEntries i) >>= fun entry => - let entryMask := _get_TLBEntry_pagemask entry in - let b__0 := entryMask in - (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16))) - then - returnm ((build_ex - 12) - : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)}) - else if ((eq_vec b__0 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 16))) - then - returnm ((build_ex - 14) - : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)}) - else if ((eq_vec b__0 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : mword 16))) - then - returnm ((build_ex - 16) - : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)}) - else if ((eq_vec b__0 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : mword 16))) - then - returnm ((build_ex - 18) - : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)}) - else if ((eq_vec b__0 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) - then - returnm ((build_ex - 20) - : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)}) - else if ((eq_vec b__0 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) - then - returnm ((build_ex - 22) - : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)}) - else if ((eq_vec b__0 - (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) - then - returnm ((build_ex - 24) - : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)}) - else if ((eq_vec b__0 - (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) - then - returnm ((build_ex - 26) - : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)}) - else if ((eq_vec b__0 - (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) - then - returnm ((build_ex - 28) - : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)}) - else - (undefined_range 12 28) - : M ({rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})) >>= fun '(existT _ evenOddBit _) => - let isOdd := access_vec_dec vAddr evenOddBit in - let '(caps, capl, pfn, d, v) := - if (((bit_to_bool isOdd) : bool)) then - (_get_TLBEntry_caps1 entry, - _get_TLBEntry_capl1 entry, - _get_TLBEntry_pfn1 entry, - _get_TLBEntry_d1 entry, - _get_TLBEntry_v1 entry) - else - (_get_TLBEntry_caps0 entry, - _get_TLBEntry_capl0 entry, - _get_TLBEntry_pfn0 entry, - _get_TLBEntry_d0 entry, - _get_TLBEntry_v0 entry) in - (if ((negb ((bits_to_bool v) : bool))) then - (SignalExceptionTLB (if ((generic_eq accessType StoreData)) then XTLBInvS else XTLBInvL) - vAddr) - : M ((mword 64 * bool)) - else if ((andb (generic_eq accessType StoreData) (negb ((bits_to_bool d) : bool)))) then - (SignalExceptionTLB TLBMod vAddr) - : M ((mword 64 * bool)) - else - let res : bits 64 := - mips_zero_extend 64 - (concat_vec (subrange_vec_dec pfn 23 (Z.sub evenOddBit 12)) - (subrange_vec_dec vAddr (Z.sub evenOddBit 1) 0)) in - returnm ((res, bits_to_bool (if ((generic_eq accessType StoreData)) then caps else capl)) - : (mword 64 * bool))) - : M ((mword 64 * bool)) - | None => - (SignalExceptionTLB - (if ((generic_eq accessType StoreData)) then XTLBRefillS - else XTLBRefillL) vAddr) - : M ((mword 64 * bool)) - end) - : M ((mword 64 * bool)). - -Definition TLBTranslateC (vAddr : mword 64) (accessType : MemAccessType) -: M ((mword 64 * bool)) := - getAccessLevel tt >>= fun currentAccessLevel => - let compat32 := - eq_vec (subrange_vec_dec vAddr 61 31) - (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; - B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] - : mword 31) in - let b__0 := subrange_vec_dec vAddr 63 62 in - let '(requiredLevel, addr) := - (if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then - match (compat32, subrange_vec_dec vAddr 30 29) with - | (true, b__1) => - if ((eq_vec b__1 (vec_of_bits [B1;B1] : mword 2))) then - (Kernel, None : option (bits 64)) - else if ((eq_vec b__1 (vec_of_bits [B1;B0] : mword 2))) then - (Supervisor, None : option (bits 64)) - else if ((eq_vec b__1 (vec_of_bits [B0;B1] : mword 2))) then - (Kernel, - Some (concat_vec - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 32) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) (subrange_vec_dec vAddr 28 0)))) - else if ((eq_vec b__1 (vec_of_bits [B0;B0] : mword 2))) then - (Kernel, - Some (concat_vec - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 32) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) (subrange_vec_dec vAddr 28 0)))) - else match (true, b__1) with | (g__25, g__26) => (Kernel, None : option (bits 64)) end - | (g__25, g__26) => (Kernel, None : option (bits 64)) - end - else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then - (Kernel, - Some (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) (subrange_vec_dec vAddr 58 0))) - else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then - (Supervisor, None : option (bits 64)) - else (User, None : option (bits 64))) - : (AccessLevel * option (bits 64)) in - (if ((negb (grantsAccess currentAccessLevel requiredLevel))) then - (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL) vAddr) - : M ((mword 64 * bool)) - else - match addr with - | Some (a) => returnm ((a, false) : (mword 64 * bool)) - | None => - (if ((andb (negb compat32) (gtb_range_l (uint (subrange_vec_dec vAddr 61 0)) MAX_VA))) then - (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL) - vAddr) - : M ((bits 64 * bool)) - else (TLBTranslate2 vAddr accessType) : M ((bits 64 * bool))) - : M ((mword 64 * bool)) - end >>= fun '(pa, c) => - (if ((gtb_range_l (uint pa) MAX_PA)) then - (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL) vAddr) - : M ((mword 64 * bool)) - else returnm ((pa, c) : (mword 64 * bool))) - : M ((mword 64 * bool))) - : M ((mword 64 * bool)). - -Definition TLBTranslate (vAddr : mword 64) (accessType : MemAccessType) -: M (mword 64) := - TLBTranslateC vAddr accessType >>= fun '(addr, c) => returnm (addr : mword 64). - -Definition MEMw_wrapper (addr : mword 64) (size : Z) (data : mword (8 * size)) `{ArithFact (1 <= - size /\ - size <= 8)} `{ArithFact (size = size)} -: M (unit) := - let ledata := autocast (reverse_endianness data) in - (if ((eq_vec addr - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64))) then - write_reg UART_WDATA_ref (subrange_vec_dec ledata 7 0) >> - write_reg UART_WRITTEN_ref ((cast_unit_vec B1) : bits 1) - : M (unit) - else MEMea addr size >> (MEMval addr size ledata) : M (unit)) - : M (unit). - -Definition MEMw_conditional_wrapper (addr : mword 64) (size : Z) (data : mword (8 * size)) `{ArithFact (1 <= - size /\ - size <= 8)} `{ArithFact (size = size)} -: M (bool) := - MEMea_conditional addr size >> - (MEMval_conditional addr size (autocast (reverse_endianness data))) - : M (bool). - -Definition addrWrapper (addr : mword 64) (accessType : MemAccessType) (width : WordType) -: mword 64 := - addr. - -Definition addrWrapperUnaligned (addr : mword 64) (accessType : MemAccessType) (width : WordTypeUnaligned) -: mword 64 := - addr. - -Definition TranslatePC (vAddr : mword 64) -: M (mword 64) := - incrementCP0Count tt >> - (if ((neq_vec (subrange_vec_dec vAddr 1 0) (vec_of_bits [B0;B0] : mword 2))) then - (SignalExceptionBadAddr AdEL vAddr) - : M (mword 64) - else (TLBTranslate vAddr Instruction) : M (mword 64)) - : M (mword 64). - -Definition have_cp2 := false. - -Definition ERETHook '(tt : unit) : unit := tt. - -Definition init_cp2_state '(tt : unit) : M (unit) := (skip tt) : M (unit). - -Definition cp2_next_pc '(tt : unit) : M (unit) := skip tt >> (skip tt) : M (unit). - -Definition dump_cp2_state '(tt : unit) : M (unit) := skip tt >> (skip tt) : M (unit). - -Definition undefined_ast '(tt : unit) -: M (ast) := - undefined_Comparison tt >>= fun u_0 => - undefined_WordType tt >>= fun u_1 => - undefined_bool tt >>= fun u_3 => - undefined_bool tt >>= fun u_2 => - undefined_bitvector 16 >>= fun u_4 => - undefined_bitvector 5 >>= fun u_7 => - undefined_bitvector 5 >>= fun u_6 => - undefined_bitvector 5 >>= fun u_5 => - undefined_unit tt >>= fun u_8 => - undefined_bitvector 3 >>= fun u_9 => - undefined_bitvector 16 >>= fun u_10 => - undefined_bitvector 26 >>= fun u_11 => - (internal_pick - [DADDIU (u_6,u_5,u_4);DADDU (u_7,u_6,u_5);DADDI (u_6,u_5,u_10);DADD (u_7,u_6,u_5);ADD (u_7,u_6,u_5);ADDI (u_6,u_5,u_10);ADDU (u_7,u_6,u_5);ADDIU (u_6,u_5,u_10);DSUBU (u_7,u_6,u_5);DSUB (u_7,u_6,u_5);SUB (u_7,u_6,u_5);SUBU (u_7,u_6,u_5);AND (u_7,u_6,u_5);ANDI (u_6,u_5,u_10);OR (u_7,u_6,u_5);ORI (u_6,u_5,u_10);NOR (u_7,u_6,u_5);XOR (u_7,u_6,u_5);XORI (u_6,u_5,u_10);LUI (u_5,u_4);DSLL (u_7,u_6,u_5);DSLL32 (u_7,u_6,u_5);DSLLV (u_7,u_6,u_5);DSRA (u_7,u_6,u_5);DSRA32 (u_7,u_6,u_5);DSRAV (u_7,u_6,u_5);DSRL (u_7,u_6,u_5);DSRL32 (u_7,u_6,u_5);DSRLV (u_7,u_6,u_5);SLL (u_7,u_6,u_5);SLLV (u_7,u_6,u_5);SRA (u_7,u_6,u_5);SRAV (u_7,u_6,u_5);SRL (u_7,u_6,u_5);SRLV (u_7,u_6,u_5);SLT (u_7,u_6,u_5);SLTI (u_6,u_5,u_10);SLTU (u_7,u_6,u_5);SLTIU (u_6,u_5,u_10);MOVN (u_7,u_6,u_5);MOVZ (u_7,u_6,u_5);MFHI u_5;MFLO u_5;MTHI u_5;MTLO u_5;MUL (u_7,u_6,u_5);MULT (u_6,u_5);MULTU (u_6,u_5);DMULT (u_6,u_5);DMULTU (u_6,u_5);MADD (u_6,u_5);MADDU (u_6,u_5);MSUB (u_6,u_5);MSUBU (u_6,u_5);DIV (u_6,u_5);DIVU (u_6,u_5);DDIV (u_6,u_5);DDIVU (u_6,u_5);J u_11;JAL u_11;JR u_5;JALR (u_6,u_5);BEQ (u_6,u_5,u_4,u_3,u_2);BCMPZ (u_5,u_4,u_0,u_3,u_2);SYSCALL u_8;BREAK u_8;WAIT u_8;TRAPREG (u_6,u_5,u_0);TRAPIMM (u_5,u_4,u_0);Load (u_1,u_3,u_2,u_6,u_5,u_4);Store (u_1,u_2,u_6,u_5,u_4);LWL (u_6,u_5,u_10);LWR (u_6,u_5,u_10);SWL (u_6,u_5,u_10);SWR (u_6,u_5,u_10);LDL (u_6,u_5,u_10);LDR (u_6,u_5,u_10);SDL (u_6,u_5,u_10);SDR (u_6,u_5,u_10);CACHE (u_6,u_5,u_10);SYNC u_8;MFC0 (u_6,u_5,u_9,u_2);HCF u_8;MTC0 (u_6,u_5,u_9,u_2);TLBWI u_8;TLBWR u_8;TLBR u_8;TLBP u_8;RDHWR (u_6,u_5);ERET u_8;RI u_8]) - : M (ast). - -Definition extendLoad {sz : Z} (memResult : mword sz) (sign : bool) `{ArithFact (sz <= 64)} -: mword 64 := - if (sign) then mips_sign_extend 64 memResult - else mips_zero_extend 64 memResult. - -Definition TLBWriteEntry (idx : mword 6) -: M (unit) := - (read_reg TLBPageMask_ref : M (mword 16)) >>= fun pagemask => - let b__0 := pagemask in - (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16))) - then - returnm (tt - : unit) - else if ((eq_vec b__0 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 16))) then - returnm (tt - : unit) - else if ((eq_vec b__0 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : mword 16))) then - returnm (tt - : unit) - else if ((eq_vec b__0 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : mword 16))) then - returnm (tt - : unit) - else if ((eq_vec b__0 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then - returnm (tt - : unit) - else if ((eq_vec b__0 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then - returnm (tt - : unit) - else if ((eq_vec b__0 - (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then - returnm (tt - : unit) - else if ((eq_vec b__0 - (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then - returnm (tt - : unit) - else if ((eq_vec b__0 - (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then - returnm (tt - : unit) - else (SignalException MCheck) : M (unit)) >> - let '(existT _ i _) := uint idx in - let entry := vec_access_dec TLBEntries i in - _set_TLBEntry_pagemask entry pagemask >> - read_reg TLBEntryHi_ref >>= fun w__0 => - _set_TLBEntry_r entry (_get_TLBEntryHiReg_R w__0) >> - read_reg TLBEntryHi_ref >>= fun w__1 => - _set_TLBEntry_vpn2 entry (_get_TLBEntryHiReg_VPN2 w__1) >> - read_reg TLBEntryHi_ref >>= fun w__2 => - _set_TLBEntry_asid entry (_get_TLBEntryHiReg_ASID w__2) >> - and_boolM - (read_reg TLBEntryLo0_ref >>= fun w__3 => - returnm ((bits_to_bool (_get_TLBEntryLoReg_G w__3)) - : bool)) - (read_reg TLBEntryLo1_ref >>= fun w__4 => - returnm ((bits_to_bool (_get_TLBEntryLoReg_G w__4)) - : bool)) >>= fun w__5 => - _set_TLBEntry_g entry ((bool_to_bits w__5) : mword 1) >> - _set_TLBEntry_valid entry ((cast_unit_vec B1) : mword 1) >> - read_reg TLBEntryLo0_ref >>= fun w__6 => - _set_TLBEntry_caps0 entry (_get_TLBEntryLoReg_CapS w__6) >> - read_reg TLBEntryLo0_ref >>= fun w__7 => - _set_TLBEntry_capl0 entry (_get_TLBEntryLoReg_CapL w__7) >> - read_reg TLBEntryLo0_ref >>= fun w__8 => - _set_TLBEntry_pfn0 entry (_get_TLBEntryLoReg_PFN w__8) >> - read_reg TLBEntryLo0_ref >>= fun w__9 => - _set_TLBEntry_c0 entry (_get_TLBEntryLoReg_C w__9) >> - read_reg TLBEntryLo0_ref >>= fun w__10 => - _set_TLBEntry_d0 entry (_get_TLBEntryLoReg_D w__10) >> - read_reg TLBEntryLo0_ref >>= fun w__11 => - _set_TLBEntry_v0 entry (_get_TLBEntryLoReg_V w__11) >> - read_reg TLBEntryLo1_ref >>= fun w__12 => - _set_TLBEntry_caps1 entry (_get_TLBEntryLoReg_CapS w__12) >> - read_reg TLBEntryLo1_ref >>= fun w__13 => - _set_TLBEntry_capl1 entry (_get_TLBEntryLoReg_CapL w__13) >> - read_reg TLBEntryLo1_ref >>= fun w__14 => - _set_TLBEntry_pfn1 entry (_get_TLBEntryLoReg_PFN w__14) >> - read_reg TLBEntryLo1_ref >>= fun w__15 => - _set_TLBEntry_c1 entry (_get_TLBEntryLoReg_C w__15) >> - read_reg TLBEntryLo1_ref >>= fun w__16 => - _set_TLBEntry_d1 entry (_get_TLBEntryLoReg_D w__16) >> - read_reg TLBEntryLo1_ref >>= fun w__17 => - (_set_TLBEntry_v1 entry (_get_TLBEntryLoReg_V w__17)) - : M (unit). - -Definition decode (v__0 : mword 32) -: option ast := - if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B0;B0;B1] : mword 6))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (DADDIU (rs,rt,imm)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B1] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (DADDU (rs,rt,rd)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B0;B0;B0] : mword 6))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (DADDI (rs,rt,imm)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (DADD (rs,rt,rd)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (ADD (rs,rt,rd)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B0;B0;B0] : mword 6))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (ADDI (rs,rt,imm)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (ADDU (rs,rt,rd)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B0;B0;B1] : mword 6))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (ADDIU (rs,rt,imm)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B1] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (DSUBU (rs,rt,rd)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (DSUB (rs,rt,rd)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (SUB (rs,rt,rd)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B1] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (SUBU (rs,rt,rd)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (AND (rs,rt,rd)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B1;B0;B0] : mword 6))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (ANDI (rs,rt,imm)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B1] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (OR (rs,rt,rd)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B1;B0;B1] : mword 6))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (ORI (rs,rt,imm)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B1] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (NOR (rs,rt,rd)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (XOR (rs,rt,rd)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B1;B1;B0] : mword 6))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (XORI (rs,rt,imm)) - else if ((eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0] : mword 11))) then - let rt : regno := subrange_vec_dec v__0 20 16 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (LUI (rt,imm)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B0;B0;B0] : mword 6)))) - then - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - let sa : bits 5 := subrange_vec_dec v__0 10 6 in - Some (DSLL (rt,rd,sa)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B1;B0;B0] : mword 6)))) - then - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - let sa : bits 5 := subrange_vec_dec v__0 10 6 in - Some (DSLL32 (rt,rd,sa)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (DSLLV (rs,rt,rd)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B0;B1;B1] : mword 6)))) - then - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - let sa : bits 5 := subrange_vec_dec v__0 10 6 in - Some (DSRA (rt,rd,sa)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B1;B1;B1] : mword 6)))) - then - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - let sa : bits 5 := subrange_vec_dec v__0 10 6 in - Some (DSRA32 (rt,rd,sa)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B1] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (DSRAV (rs,rt,rd)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B0;B1;B0] : mword 6)))) - then - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - let sa : bits 5 := subrange_vec_dec v__0 10 6 in - Some (DSRL (rt,rd,sa)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B1;B1;B0] : mword 6)))) - then - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - let sa : bits 5 := subrange_vec_dec v__0 10 6 in - Some (DSRL32 (rt,rd,sa)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (DSRLV (rs,rt,rd)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)))) - then - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - let sa : regno := subrange_vec_dec v__0 10 6 in - Some (SLL (rt,rd,sa)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (SLLV (rs,rt,rd)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B0;B0;B1;B1] : mword 6)))) - then - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - let sa : regno := subrange_vec_dec v__0 10 6 in - Some (SRA (rt,rd,sa)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (SRAV (rs,rt,rd)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B0;B0;B1;B0] : mword 6)))) - then - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - let sa : regno := subrange_vec_dec v__0 10 6 in - Some (SRL (rt,rd,sa)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (SRLV (rs,rt,rd)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (SLT (rs,rt,rd)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B0;B1;B0] : mword 6))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (SLTI (rs,rt,imm)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B1] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (SLTU (rs,rt,rd)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B0;B1;B1] : mword 6))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (SLTIU (rs,rt,imm)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (MOVN (rs,rt,rd)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (MOVZ (rs,rt,rd)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 16) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0] : mword 11)))) then - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (MFHI rd) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 16) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B0] : mword 11)))) then - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (MFLO rd) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B1] - : mword 21)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - Some (MTHI rs) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B1] - : mword 21)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - Some (MTLO rs) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (MUL (rs,rt,rd)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - Some (MULT (rs,rt)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - Some (MULTU (rs,rt)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - Some (DMULT (rs,rt)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B1] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - Some (DMULTU (rs,rt)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - Some (MADD (rs,rt)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - Some (MADDU (rs,rt)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - Some (MSUB (rs,rt)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - Some (MSUBU (rs,rt)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B0] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - Some (DIV (rs,rt)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - Some (DIVU (rs,rt)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B0] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - Some (DDIV (rs,rt)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - Some (DDIVU (rs,rt)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B1;B0] : mword 6))) - then - let offset : bits 26 := subrange_vec_dec v__0 25 0 in - Some (J offset) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B1;B1] : mword 6))) - then - let offset : bits 26 := subrange_vec_dec v__0 25 0 in - Some (JAL offset) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (andb - (eq_vec (subrange_vec_dec v__0 20 11) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 10)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B1;B0;B0;B0] : mword 6))))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - Some (JR rs) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (andb - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B1;B0;B0;B1] : mword 6))))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (JALR (rs,rd)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B1;B0;B0] : mword 6))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BEQ (rs,rt,imm,false,false)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B0;B1;B0;B0] : mword 6))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BEQ (rs,rt,imm,false,true)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B1;B0;B1] : mword 6))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BEQ (rs,rt,imm,true,false)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B0;B1;B0;B1] : mword 6))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BEQ (rs,rt,imm,true,true)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,LT',false,false)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,LT',true,false)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,LT',false,true)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B1;B0;B0;B1;B0] : mword 5)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,LT',true,true)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B1] : mword 5)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,GE,false,false)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B1;B0;B0;B0;B1] : mword 5)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,GE,true,false)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B1;B1] : mword 5)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,GE,false,true)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B1;B0;B0;B1;B1] : mword 5)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,GE,true,true)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B1;B1;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,GT',false,false)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B0;B1;B1;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,GT',false,true)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B1;B1;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,LE,false,false)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B0;B1;B1;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,LE,false,true)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B1;B1;B0;B0] : mword 6)))) - then - Some (SYSCALL tt) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B1;B1;B0;B1] : mword 6)))) - then - Some (BREAK tt) - else if ((eq_vec v__0 - (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0] - : mword 32))) then - Some (WAIT tt) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B0;B0;B0] : mword 6)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - Some (TRAPREG (rs,rt,GE)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B0;B0;B1] : mword 6)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - Some (TRAPREG (rs,rt,GEU)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B0;B1;B0] : mword 6)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - Some (TRAPREG (rs,rt,LT')) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B0;B1;B1] : mword 6)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - Some (TRAPREG (rs,rt,LTU)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B1;B0;B0] : mword 6)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - Some (TRAPREG (rs,rt,EQ')) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B1;B1;B0] : mword 6)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - Some (TRAPREG (rs,rt,NE)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B1;B0;B0] : mword 5)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (TRAPIMM (rs,imm,EQ')) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B1;B1;B0] : mword 5)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (TRAPIMM (rs,imm,NE)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (TRAPIMM (rs,imm,GE)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B0;B0;B1] : mword 5)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (TRAPIMM (rs,imm,GEU)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B0;B1;B0] : mword 5)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (TRAPIMM (rs,imm,LT')) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B0;B1;B1] : mword 5)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (TRAPIMM (rs,imm,LTU)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B0;B0;B0] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Load (B,true,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B1;B0;B0] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Load (B,false,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B0;B0;B1] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Load (H,true,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B1;B0;B1] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Load (H,false,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Load (W,true,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Load (W,false,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B0;B1;B1;B1] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Load (D,false,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B0;B0;B0;B0] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Load (W,true,true,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B0;B1;B0;B0] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Load (D,false,true,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B0;B0;B0] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Store (B,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B0;B0;B1] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Store (H,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B0;B1;B1] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Store (W,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B1;B1;B1;B1] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Store (D,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B1;B0;B0;B0] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Store (W,true,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B1;B1;B0;B0] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Store (D,true,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B0;B1;B0] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (LWL (base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B1;B1;B0] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (LWR (base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B0;B1;B0] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (SWL (base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B1;B1;B0] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (SWR (base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B0;B1;B0] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (LDL (base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B0;B1;B1] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (LDR (base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B1;B0;B0] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (SDL (base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B1;B0;B1] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (SDR (base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B1;B1;B1] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in - let op : regno := subrange_vec_dec v__0 20 16 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (CACHE (base,op,imm)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 11) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 21)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B1;B1;B1;B1] : mword 6)))) - then - Some (SYNC tt) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 10 3) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8)))) then - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - let sel : bits 3 := subrange_vec_dec v__0 2 0 in - Some (MFC0 (rt,rd,sel,false)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 11)) - (eq_vec (subrange_vec_dec v__0 10 3) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8)))) then - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - let sel : bits 3 := subrange_vec_dec v__0 2 0 in - Some (MFC0 (rt,rd,sel,true)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16)))) - then - Some (HCF tt) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B1;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16)))) - then - Some (HCF tt) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 10 3) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8)))) then - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - let sel : bits 3 := subrange_vec_dec v__0 2 0 in - Some (MTC0 (rt,rd,sel,false)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 11)) - (eq_vec (subrange_vec_dec v__0 10 3) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8)))) then - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - let sel : bits 3 := subrange_vec_dec v__0 2 0 in - Some (MTC0 (rt,rd,sel,true)) - else if ((eq_vec v__0 - (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] - : mword 32))) then - Some ((TLBWI tt) - : ast) - else if ((eq_vec v__0 - (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] - : mword 32))) then - Some ((TLBWR tt) - : ast) - else if ((eq_vec v__0 - (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] - : mword 32))) then - Some ((TLBR tt) - : ast) - else if ((eq_vec v__0 - (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0] - : mword 32))) then - Some ((TLBP tt) - : ast) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B0;B1;B1] : mword 11)))) then - let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (RDHWR (rt,rd)) - else if ((eq_vec v__0 - (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0] - : mword 32))) then - Some (ERET tt) - else Some (RI tt). - -Definition execute_XORI (rs : mword 5) (rt : mword 5) (imm : mword 16) -: M (unit) := - rGPR rs >>= fun w__0 => (wGPR rt (xor_vec w__0 (mips_zero_extend 64 imm))) : M (unit). - -Definition execute_XOR (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rs >>= fun w__0 => rGPR rt >>= fun w__1 => (wGPR rd (xor_vec w__0 w__1)) : M (unit). - -Definition execute_WAIT (g__16 : unit) -: M (unit) := - (read_reg PC_ref : M (mword 64)) >>= fun w__0 => write_reg nextPC_ref w__0 : M (unit). - -Definition execute_TRAPREG (rs : mword 5) (rt : mword 5) (cmp : Comparison) -: M (unit) := - rGPR rs >>= fun rs_val => - rGPR rt >>= fun rt_val => - let condition := compare cmp rs_val rt_val in - (if (condition) then (SignalException Tr) : M (unit) - else returnm (tt : unit)) - : M (unit). - -Definition execute_TRAPIMM (rs : mword 5) (imm : mword 16) (cmp : Comparison) -: M (unit) := - rGPR rs >>= fun rs_val => - let imm_val : bits 64 := mips_sign_extend 64 imm in - let condition := compare cmp rs_val imm_val in - (if (condition) then (SignalException Tr) : M (unit) - else returnm (tt : unit)) - : M (unit). - -Definition execute_TLBWR (g__20 : unit) -: M (unit) := - checkCP0Access tt >> - (read_reg TLBRandom_ref : M (mword 6)) >>= fun w__0 => (TLBWriteEntry w__0) : M (unit). - -Definition execute_TLBWI (g__19 : unit) -: M (unit) := - checkCP0Access tt >> - (read_reg TLBIndex_ref : M (mword 6)) >>= fun w__0 => (TLBWriteEntry w__0) : M (unit). - -Definition execute_TLBR (g__21 : unit) -: M (unit) := - checkCP0Access tt >> - (read_reg TLBIndex_ref : M (mword 6)) >>= fun w__0 => - let '(existT _ i _) := uint w__0 in - reg_deref (vec_access_dec TLBEntries i) >>= fun entry => - write_reg TLBPageMask_ref (_get_TLBEntry_pagemask entry) >> - _set_TLBEntryHiReg_R TLBEntryHi_ref (_get_TLBEntry_r entry) >> - _set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (_get_TLBEntry_vpn2 entry) >> - _set_TLBEntryHiReg_ASID TLBEntryHi_ref (_get_TLBEntry_asid entry) >> - _set_TLBEntryLoReg_CapS TLBEntryLo0_ref (_get_TLBEntry_caps0 entry) >> - _set_TLBEntryLoReg_CapL TLBEntryLo0_ref (_get_TLBEntry_capl0 entry) >> - _set_TLBEntryLoReg_PFN TLBEntryLo0_ref (_get_TLBEntry_pfn0 entry) >> - _set_TLBEntryLoReg_C TLBEntryLo0_ref (_get_TLBEntry_c0 entry) >> - _set_TLBEntryLoReg_D TLBEntryLo0_ref (_get_TLBEntry_d0 entry) >> - _set_TLBEntryLoReg_V TLBEntryLo0_ref (_get_TLBEntry_v0 entry) >> - _set_TLBEntryLoReg_G TLBEntryLo0_ref (_get_TLBEntry_g entry) >> - _set_TLBEntryLoReg_CapS TLBEntryLo1_ref (_get_TLBEntry_caps1 entry) >> - _set_TLBEntryLoReg_CapL TLBEntryLo1_ref (_get_TLBEntry_capl1 entry) >> - _set_TLBEntryLoReg_PFN TLBEntryLo1_ref (_get_TLBEntry_pfn1 entry) >> - _set_TLBEntryLoReg_C TLBEntryLo1_ref (_get_TLBEntry_c1 entry) >> - _set_TLBEntryLoReg_D TLBEntryLo1_ref (_get_TLBEntry_d1 entry) >> - _set_TLBEntryLoReg_V TLBEntryLo1_ref (_get_TLBEntry_v1 entry) >> - (_set_TLBEntryLoReg_G TLBEntryLo1_ref (_get_TLBEntry_g entry)) - : M (unit). - -Definition execute_TLBP (g__22 : unit) -: M (unit) := - checkCP0Access tt >> - read_reg TLBEntryHi_ref >>= fun w__0 => - tlbSearch (_get_TLBEntryHiReg_bits w__0) >>= fun result => - (match result with - | Some (idx) => - write_reg TLBProbe_ref (vec_of_bits [B0] : mword 1) >> - write_reg TLBIndex_ref idx - : M (unit) - | None => - write_reg TLBProbe_ref (vec_of_bits [B1] : mword 1) >> - write_reg TLBIndex_ref (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6) - : M (unit) - end) - : M (unit). - -Definition execute_Store (width : WordType) (conditional : bool) (base : mword 5) (rt : mword 5) (offset : mword 16) -: M (unit) := - rGPR base >>= fun w__0 => - let vAddr : bits 64 := addrWrapper (add_vec (mips_sign_extend 64 offset) w__0) StoreData width in - rGPR rt >>= fun rt_val => - (if ((negb (isAddressAligned vAddr width))) then (SignalExceptionBadAddr AdES vAddr) : M (unit) - else - TLBTranslate vAddr StoreData >>= fun pAddr => - (if (conditional) then - (read_reg CP0LLBit_ref : M (mword 1)) >>= fun w__1 => - (if (((bit_to_bool (access_vec_dec w__1 0)) : bool)) then - (match width with - | W => (MEMw_conditional_wrapper pAddr 4 (subrange_vec_dec rt_val 31 0)) : M (bool) - | D => (MEMw_conditional_wrapper pAddr 8 rt_val) : M (bool) - | _ => (throw (Error_internal_error tt)) : M (bool) - end) - : M (bool) - else returnm (false : bool)) >>= fun success => - (wGPR rt (mips_zero_extend 64 ((bool_to_bits success) : mword 1))) - : M (unit) - else - (match width with - | B => (MEMw_wrapper pAddr 1 (subrange_vec_dec rt_val 7 0)) : M (unit) - | H => (MEMw_wrapper pAddr 2 (subrange_vec_dec rt_val 15 0)) : M (unit) - | W => (MEMw_wrapper pAddr 4 (subrange_vec_dec rt_val 31 0)) : M (unit) - | D => (MEMw_wrapper pAddr 8 rt_val) : M (unit) - end) - : M (unit)) - : M (unit)) - : M (unit). - -Definition execute_SYSCALL (g__14 : unit) : M (unit) := (SignalException Sys) : M (unit). - -Definition execute_SYNC (g__17 : unit) : M (unit) := (MEM_sync tt) : M (unit). - -Definition execute_SWR (base : mword 5) (rt : mword 5) (offset : mword 16) -: M (unit) := - rGPR base >>= fun w__0 => - let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData WR in - TLBTranslate vAddr StoreData >>= fun pAddr => - let wordAddr := concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0] : mword 2) in - rGPR rt >>= fun reg_val => - let b__12 := subrange_vec_dec vAddr 1 0 in - (if ((eq_vec b__12 (vec_of_bits [B0;B0] : mword 2))) then - (MEMw_wrapper wordAddr 1 (subrange_vec_dec reg_val 7 0)) - : M (unit) - else if ((eq_vec b__12 (vec_of_bits [B0;B1] : mword 2))) then - (MEMw_wrapper wordAddr 2 (subrange_vec_dec reg_val 15 0)) - : M (unit) - else if ((eq_vec b__12 (vec_of_bits [B1;B0] : mword 2))) then - (MEMw_wrapper wordAddr 3 (subrange_vec_dec reg_val 23 0)) - : M (unit) - else (MEMw_wrapper wordAddr 4 (subrange_vec_dec reg_val 31 0)) : M (unit)) - : M (unit). - -Definition execute_SWL (base : mword 5) (rt : mword 5) (offset : mword 16) -: M (unit) := - rGPR base >>= fun w__0 => - let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData WL in - TLBTranslate vAddr StoreData >>= fun pAddr => - rGPR rt >>= fun reg_val => - let b__8 := subrange_vec_dec vAddr 1 0 in - (if ((eq_vec b__8 (vec_of_bits [B0;B0] : mword 2))) then - (MEMw_wrapper pAddr 4 (subrange_vec_dec reg_val 31 0)) - : M (unit) - else if ((eq_vec b__8 (vec_of_bits [B0;B1] : mword 2))) then - (MEMw_wrapper pAddr 3 (subrange_vec_dec reg_val 31 8)) - : M (unit) - else if ((eq_vec b__8 (vec_of_bits [B1;B0] : mword 2))) then - (MEMw_wrapper pAddr 2 (subrange_vec_dec reg_val 31 16)) - : M (unit) - else (MEMw_wrapper pAddr 1 (subrange_vec_dec reg_val 31 24)) : M (unit)) - : M (unit). - -Definition execute_SUBU (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rs >>= fun opA => - rGPR rt >>= fun opB => - (if ((orb (NotWordVal opA) (NotWordVal opB))) then - undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0) : M (unit) - else - (wGPR rd - (mips_sign_extend 64 (sub_vec (subrange_vec_dec opA 31 0) (subrange_vec_dec opB 31 0)))) - : M (unit)) - : M (unit). - -Definition execute_SUB (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rs >>= fun opA => - rGPR rt >>= fun opB => - (if ((orb (NotWordVal opA) (NotWordVal opB))) then - undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0) : M (unit) - else - let temp33 : bits 33 := - sub_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0)) - (mips_sign_extend 33 (subrange_vec_dec opB 31 0)) in - (if ((neq_bool ((bit_to_bool (access_vec_dec temp33 32)) : bool) - ((bit_to_bool (access_vec_dec temp33 31)) - : bool))) then - (SignalException Ov) - : M (unit) - else (wGPR rd (mips_sign_extend 64 (subrange_vec_dec temp33 31 0))) : M (unit)) - : M (unit)) - : M (unit). - -Definition execute_SRLV (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rt >>= fun temp => - rGPR rs >>= fun w__0 => - let sa := subrange_vec_dec w__0 4 0 in - (if ((NotWordVal temp)) then undefined_bitvector 64 >>= fun w__1 => (wGPR rd w__1) : M (unit) - else - let rt32 := subrange_vec_dec temp 31 0 in - shift_bits_right rt32 sa >>= fun w__2 => (wGPR rd (mips_sign_extend 64 w__2)) : M (unit)) - : M (unit). - -Definition execute_SRL (rt : mword 5) (rd : mword 5) (sa : mword 5) -: M (unit) := - rGPR rt >>= fun temp => - (if ((NotWordVal temp)) then undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0) : M (unit) - else - let rt32 := subrange_vec_dec temp 31 0 in - shift_bits_right rt32 sa >>= fun w__1 => (wGPR rd (mips_sign_extend 64 w__1)) : M (unit)) - : M (unit). - -Definition execute_SRAV (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rt >>= fun temp => - rGPR rs >>= fun w__0 => - let sa := subrange_vec_dec w__0 4 0 in - (if ((NotWordVal temp)) then undefined_bitvector 64 >>= fun w__1 => (wGPR rd w__1) : M (unit) - else - let rt32 := subrange_vec_dec temp 31 0 in - shift_bits_right_arith rt32 sa >>= fun w__2 => - (wGPR rd (mips_sign_extend 64 w__2)) - : M (unit)) - : M (unit). - -Definition execute_SRA (rt : mword 5) (rd : mword 5) (sa : mword 5) -: M (unit) := - rGPR rt >>= fun temp => - (if ((NotWordVal temp)) then undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0) : M (unit) - else - let rt32 := subrange_vec_dec temp 31 0 in - shift_bits_right_arith rt32 sa >>= fun w__1 => - (wGPR rd (mips_sign_extend 64 w__1)) - : M (unit)) - : M (unit). - -Definition execute_SLTU (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rs >>= fun rs_val => - rGPR rt >>= fun rt_val => - (wGPR rd - (mips_zero_extend 64 - (if ((zopz0zI_u rs_val rt_val)) then (vec_of_bits [B1] : mword 1) - else (vec_of_bits [B0] : mword 1)))) - : M (unit). - -Definition execute_SLTIU (rs : mword 5) (rt : mword 5) (imm : mword 16) -: M (unit) := - rGPR rs >>= fun rs_val => - let immext : bits 64 := mips_sign_extend 64 imm in - (wGPR rt - (mips_zero_extend 64 - (if ((zopz0zI_u rs_val immext)) then (vec_of_bits [B1] : mword 1) - else (vec_of_bits [B0] : mword 1)))) - : M (unit). - -Definition execute_SLTI (rs : mword 5) (rt : mword 5) (imm : mword 16) -: M (unit) := - let '(existT _ imm_val _) := sint imm in - rGPR rs >>= fun w__0 => - let '(existT _ rs_val _) := sint w__0 in - (wGPR rt - (mips_zero_extend 64 - (if sumbool_of_bool ((Z.ltb rs_val imm_val)) then (vec_of_bits [B1] : mword 1) - else (vec_of_bits [B0] : mword 1)))) - : M (unit). - -Definition execute_SLT (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rs >>= fun w__0 => - rGPR rt >>= fun w__1 => - (wGPR rd - (mips_zero_extend 64 - (if ((zopz0zI_s w__0 w__1)) then (vec_of_bits [B1] : mword 1) - else (vec_of_bits [B0] : mword 1)))) - : M (unit). - -Definition execute_SLLV (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rs >>= fun w__0 => - let sa := subrange_vec_dec w__0 4 0 in - rGPR rt >>= fun w__1 => - let rt32 := subrange_vec_dec w__1 31 0 in - shift_bits_left rt32 sa >>= fun w__2 => (wGPR rd (mips_sign_extend 64 w__2)) : M (unit). - -Definition execute_SLL (rt : mword 5) (rd : mword 5) (sa : mword 5) -: M (unit) := - rGPR rt >>= fun w__0 => - let rt32 := subrange_vec_dec w__0 31 0 in - shift_bits_left rt32 sa >>= fun w__1 => (wGPR rd (mips_sign_extend 64 w__1)) : M (unit). - -Definition execute_SDR (base : mword 5) (rt : mword 5) (offset : mword 16) -: M (unit) := - rGPR base >>= fun w__0 => - let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData DR in - TLBTranslate vAddr StoreData >>= fun pAddr => - rGPR rt >>= fun reg_val => - let wordAddr := concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0] : mword 3) in - let b__40 := subrange_vec_dec vAddr 2 0 in - (if ((eq_vec b__40 (vec_of_bits [B0;B0;B0] : mword 3))) then - (MEMw_wrapper wordAddr 1 (subrange_vec_dec reg_val 7 0)) - : M (unit) - else if ((eq_vec b__40 (vec_of_bits [B0;B0;B1] : mword 3))) then - (MEMw_wrapper wordAddr 2 (subrange_vec_dec reg_val 15 0)) - : M (unit) - else if ((eq_vec b__40 (vec_of_bits [B0;B1;B0] : mword 3))) then - (MEMw_wrapper wordAddr 3 (subrange_vec_dec reg_val 23 0)) - : M (unit) - else if ((eq_vec b__40 (vec_of_bits [B0;B1;B1] : mword 3))) then - (MEMw_wrapper wordAddr 4 (subrange_vec_dec reg_val 31 0)) - : M (unit) - else if ((eq_vec b__40 (vec_of_bits [B1;B0;B0] : mword 3))) then - (MEMw_wrapper wordAddr 5 (subrange_vec_dec reg_val 39 0)) - : M (unit) - else if ((eq_vec b__40 (vec_of_bits [B1;B0;B1] : mword 3))) then - (MEMw_wrapper wordAddr 6 (subrange_vec_dec reg_val 47 0)) - : M (unit) - else if ((eq_vec b__40 (vec_of_bits [B1;B1;B0] : mword 3))) then - (MEMw_wrapper wordAddr 7 (subrange_vec_dec reg_val 55 0)) - : M (unit) - else (MEMw_wrapper wordAddr 8 (subrange_vec_dec reg_val 63 0)) : M (unit)) - : M (unit). - -Definition execute_SDL (base : mword 5) (rt : mword 5) (offset : mword 16) -: M (unit) := - rGPR base >>= fun w__0 => - let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData DL in - TLBTranslate vAddr StoreData >>= fun pAddr => - rGPR rt >>= fun reg_val => - let b__32 := subrange_vec_dec vAddr 2 0 in - (if ((eq_vec b__32 (vec_of_bits [B0;B0;B0] : mword 3))) then - (MEMw_wrapper pAddr 8 (subrange_vec_dec reg_val 63 0)) - : M (unit) - else if ((eq_vec b__32 (vec_of_bits [B0;B0;B1] : mword 3))) then - (MEMw_wrapper pAddr 7 (subrange_vec_dec reg_val 63 8)) - : M (unit) - else if ((eq_vec b__32 (vec_of_bits [B0;B1;B0] : mword 3))) then - (MEMw_wrapper pAddr 6 (subrange_vec_dec reg_val 63 16)) - : M (unit) - else if ((eq_vec b__32 (vec_of_bits [B0;B1;B1] : mword 3))) then - (MEMw_wrapper pAddr 5 (subrange_vec_dec reg_val 63 24)) - : M (unit) - else if ((eq_vec b__32 (vec_of_bits [B1;B0;B0] : mword 3))) then - (MEMw_wrapper pAddr 4 (subrange_vec_dec reg_val 63 32)) - : M (unit) - else if ((eq_vec b__32 (vec_of_bits [B1;B0;B1] : mword 3))) then - (MEMw_wrapper pAddr 3 (subrange_vec_dec reg_val 63 40)) - : M (unit) - else if ((eq_vec b__32 (vec_of_bits [B1;B1;B0] : mword 3))) then - (MEMw_wrapper pAddr 2 (subrange_vec_dec reg_val 63 48)) - : M (unit) - else (MEMw_wrapper pAddr 1 (subrange_vec_dec reg_val 63 56)) : M (unit)) - : M (unit). - -Definition execute_RI (g__24 : unit) : M (unit) := (SignalException ResI) : M (unit). - -Definition execute_RDHWR (rt : mword 5) (rd : mword 5) -: M (unit) := - getAccessLevel tt >>= fun accessLevel => - let haveAccessLevel : bool := generic_eq accessLevel Kernel in - read_reg CP0Status_ref >>= fun w__0 => - let haveCU0 : bool := eq_bit B1 (access_vec_dec (_get_StatusReg_CU w__0) 0) in - let '(existT _ rdi _) := uint rd in - (read_reg CP0HWREna_ref : M (mword 32)) >>= fun w__1 => - let haveHWREna : bool := eq_bit B1 (access_vec_dec w__1 rdi) in - (if ((negb (orb haveAccessLevel (orb haveCU0 haveHWREna)))) then - (SignalException ResI) - : M (unit) - else returnm (tt : unit)) >> - let b__146 := rd in - (if ((eq_vec b__146 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))) then - returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) - : bits 64) - else if ((eq_vec b__146 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))) then - returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) - : bits 64) - else if ((eq_vec b__146 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5))) then - (read_reg CP0Count_ref : M (mword 32)) >>= fun w__2 => - returnm ((mips_zero_extend 64 w__2) - : bits 64) - else if ((eq_vec b__146 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5))) then - returnm ((mips_zero_extend 64 (vec_of_bits [B1] : mword 1)) - : bits 64) - else if ((eq_vec b__146 (vec_of_bits [B1;B1;B1;B0;B1] : mword 5))) then - (read_reg CP0UserLocal_ref : M (mword 64)) - : M (bits 64) - else (SignalException ResI) : M (bits 64)) >>= fun temp => - (wGPR rt temp) - : M (unit). - -Definition execute_ORI (rs : mword 5) (rt : mword 5) (imm : mword 16) -: M (unit) := - rGPR rs >>= fun w__0 => (wGPR rt (or_vec w__0 (mips_zero_extend 64 imm))) : M (unit). - -Definition execute_OR (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rs >>= fun w__0 => rGPR rt >>= fun w__1 => (wGPR rd (or_vec w__0 w__1)) : M (unit). - -Definition execute_NOR (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rs >>= fun w__0 => - rGPR rt >>= fun w__1 => (wGPR rd (not_vec (or_vec w__0 w__1))) : M (unit). - -Definition execute_MULTU (rs : mword 5) (rt : mword 5) -: M (unit) := - rGPR rs >>= fun rsVal => - rGPR rt >>= fun rtVal => - (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (bits 64) - else returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) : bits 64)) >>= fun result => - write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> - write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) - : M (unit). - -Definition execute_MULT (rs : mword 5) (rt : mword 5) -: M (unit) := - rGPR rs >>= fun rsVal => - rGPR rt >>= fun rtVal => - (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (bits 64) - else - returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) - : bits 64)) >>= fun result => - write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> - write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) - : M (unit). - -Definition execute_MUL (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rs >>= fun rsVal => - rGPR rt >>= fun rtVal => - let result : bits 64 := - mips_sign_extend 64 (mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) in - (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) - else returnm ((mips_sign_extend 64 (subrange_vec_dec result 31 0)) : mword 64)) >>= fun w__1 => - (wGPR rd w__1) - : M (unit). - -Definition execute_MTLO (rs : mword 5) -: M (unit) := - rGPR rs >>= fun w__0 => write_reg LO_ref w__0 : M (unit). - -Definition execute_MTHI (rs : mword 5) -: M (unit) := - rGPR rs >>= fun w__0 => write_reg HI_ref w__0 : M (unit). - -Definition execute_MTC0 (rt : mword 5) (rd : mword 5) (sel : mword 3) (double : bool) -: M (unit) := - checkCP0Access tt >> - rGPR rt >>= fun reg_val => - (match (rd, sel) with - | (b__108, b__109) => - (if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - write_reg TLBIndex_ref (mask 6 reg_val) - : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - returnm (tt - : unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (_set_TLBEntryLoReg_bits TLBEntryLo0_ref reg_val) - : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (_set_TLBEntryLoReg_bits TLBEntryLo1_ref reg_val) - : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (_set_ContextReg_PTEBase TLBContext_ref (subrange_vec_dec reg_val 63 23)) - : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B1;B0] : mword 3)))) then - write_reg CP0UserLocal_ref reg_val - : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B1;B0;B1] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - write_reg TLBPageMask_ref (subrange_vec_dec reg_val 28 13) - : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B1;B1;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - write_reg TLBWired_ref (mask 6 reg_val) >> write_reg TLBRandom_ref TLBIndexMax : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B1;B1;B1] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - write_reg - CP0HWREna_ref - (concat_vec (subrange_vec_dec reg_val 31 29) - (concat_vec - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0] - : mword 25) (subrange_vec_dec reg_val 3 0))) - : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - returnm (tt - : unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B0;B0;B1] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - write_reg CP0Count_ref (subrange_vec_dec reg_val 31 0) - : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B0;B1;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - _set_TLBEntryHiReg_R TLBEntryHi_ref (subrange_vec_dec reg_val 63 62) >> - _set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (subrange_vec_dec reg_val 39 13) >> - (_set_TLBEntryHiReg_ASID TLBEntryHi_ref (subrange_vec_dec reg_val 7 0)) - : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B0;B1;B1] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - write_reg CP0Compare_ref (subrange_vec_dec reg_val 31 0) >> - read_reg CP0Cause_ref >>= fun w__0 => - (_set_CauseReg_IP CP0Cause_ref - (and_vec (_get_CauseReg_IP w__0) (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1] : mword 8))) - : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - _set_StatusReg_CU CP0Status_ref (subrange_vec_dec reg_val 31 28) >> - _set_StatusReg_BEV CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 22)) : mword 1) >> - _set_StatusReg_IM CP0Status_ref (subrange_vec_dec reg_val 15 8) >> - _set_StatusReg_KX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 7)) : mword 1) >> - _set_StatusReg_SX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 6)) : mword 1) >> - _set_StatusReg_UX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 5)) : mword 1) >> - _set_StatusReg_KSU CP0Status_ref (subrange_vec_dec reg_val 4 3) >> - _set_StatusReg_ERL CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 2)) : mword 1) >> - _set_StatusReg_EXL CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 1)) : mword 1) >> - (_set_StatusReg_IE CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 0)) : mword 1)) - : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B1;B0;B1] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - _set_CauseReg_IV CP0Cause_ref ((cast_unit_vec (access_vec_dec reg_val 23)) : mword 1) >> - read_reg CP0Cause_ref >>= fun w__1 => - let ip := _get_CauseReg_IP w__1 in - (_set_CauseReg_IP CP0Cause_ref - (concat_vec (subrange_vec_dec ip 7 2) (subrange_vec_dec reg_val 9 8))) - : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B1;B1;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - write_reg CP0EPC_ref reg_val - : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - write_reg CP0ConfigK0_ref (subrange_vec_dec reg_val 2 0) - : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (_set_XContextReg_XPTEBase TLBXContext_ref (subrange_vec_dec reg_val 63 33)) - : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B1;B1;B1;B1;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - write_reg CP0ErrorEPC_ref reg_val - : M (unit) - else (SignalException ResI) : M (unit)) - : M (unit) - end) - : M (unit). - -Definition execute_MSUBU (rs : mword 5) (rt : mword 5) -: M (unit) := - rGPR rs >>= fun rsVal => - rGPR rt >>= fun rtVal => - (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (bits 64) - else returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) : bits 64)) >>= fun mul_result => - (read_reg HI_ref : M (mword 64)) >>= fun w__1 => - (read_reg LO_ref : M (mword 64)) >>= fun w__2 => - let result := - sub_vec (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) mul_result in - write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> - write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) - : M (unit). - -Definition execute_MSUB (rs : mword 5) (rt : mword 5) -: M (unit) := - rGPR rs >>= fun rsVal => - rGPR rt >>= fun rtVal => - (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (bits 64) - else - returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) - : bits 64)) >>= fun mul_result => - (read_reg HI_ref : M (mword 64)) >>= fun w__1 => - (read_reg LO_ref : M (mword 64)) >>= fun w__2 => - let result := - sub_vec (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) mul_result in - write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> - write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) - : M (unit). - -Definition execute_MOVZ (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rt >>= fun w__0 => - (if ((eq_vec w__0 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64))) then - rGPR rs >>= fun w__1 => (wGPR rd w__1) : M (unit) - else returnm (tt : unit)) - : M (unit). - -Definition execute_MOVN (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rt >>= fun w__0 => - (if ((neq_vec w__0 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64))) then - rGPR rs >>= fun w__1 => (wGPR rd w__1) : M (unit) - else returnm (tt : unit)) - : M (unit). - -Definition execute_MFLO (rd : mword 5) -: M (unit) := - (read_reg LO_ref : M (mword 64)) >>= fun w__0 => (wGPR rd w__0) : M (unit). - -Definition execute_MFHI (rd : mword 5) -: M (unit) := - (read_reg HI_ref : M (mword 64)) >>= fun w__0 => (wGPR rd w__0) : M (unit). - -Definition execute_MFC0 (rt : mword 5) (rd : mword 5) (sel : mword 3) (double : bool) -: M (unit) := - checkCP0Access tt >> - match (rd, sel) with - | (b__48, b__49) => - (if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg TLBIndex_ref : M (mword 6)) >>= fun w__0 => - let idx : bits 31 := mips_zero_extend 31 w__0 in - (read_reg TLBProbe_ref : M (mword 1)) >>= fun w__1 => - returnm ((concat_vec - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 32) (concat_vec w__1 idx)) - : mword 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg TLBRandom_ref : M (mword 6)) >>= fun w__2 => - returnm ((mips_zero_extend 64 w__2) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - read_reg TLBEntryLo0_ref >>= fun w__3 => - returnm ((_get_TLBEntryLoReg_bits w__3) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - read_reg TLBEntryLo1_ref >>= fun w__4 => - returnm ((_get_TLBEntryLoReg_bits w__4) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - read_reg TLBContext_ref >>= fun w__5 => returnm ((_get_ContextReg_bits w__5) : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B1;B0] : mword 3)))) then - (read_reg CP0UserLocal_ref : M (mword 64)) - : M (bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg TLBPageMask_ref : M (mword 16)) >>= fun w__7 => - returnm ((mips_zero_extend 64 - (concat_vec w__7 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B1;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg TLBWired_ref : M (mword 6)) >>= fun w__8 => - returnm ((mips_zero_extend 64 w__8) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B1;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg CP0HWREna_ref : M (mword 32)) >>= fun w__9 => - returnm ((mips_zero_extend 64 w__9) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg CP0BadVAddr_ref : M (mword 64)) - : M (bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B1] : mword 3)))) then - returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg CP0Count_ref : M (mword 32)) >>= fun w__11 => - returnm ((mips_zero_extend 64 w__11) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B1;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - read_reg TLBEntryHi_ref >>= fun w__12 => - returnm ((_get_TLBEntryHiReg_bits w__12) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B1;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg CP0Compare_ref : M (mword 32)) >>= fun w__13 => - returnm ((mips_zero_extend 64 w__13) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - read_reg CP0Status_ref >>= fun w__14 => - returnm ((mips_zero_extend 64 (_get_StatusReg_bits w__14)) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B0;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - read_reg CP0Cause_ref >>= fun w__15 => - returnm ((mips_zero_extend 64 (_get_CauseReg_bits w__15)) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg CP0EPC_ref : M (mword 64)) - : M (bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - returnm ((mips_zero_extend 64 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 32)) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B1;B1;B0] : mword 3)))) then - returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B1;B1;B1] : mword 3)))) then - returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg CP0ConfigK0_ref : M (mword 3)) >>= fun w__17 => - returnm ((mips_zero_extend 64 - (concat_vec (vec_of_bits [B1] : mword 1) - (concat_vec - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 15) - (concat_vec (vec_of_bits [B1] : mword 1) - (concat_vec (vec_of_bits [B1;B0] : mword 2) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) w__17)))))))) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B1] : mword 3)))) then - returnm ((mips_zero_extend 64 - (concat_vec (vec_of_bits [B1] : mword 1) - (concat_vec TLBIndexMax - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (bool_to_bits have_cp2) - (concat_vec (vec_of_bits [B0] : mword 1) - (concat_vec (vec_of_bits [B0] : mword 1) - (concat_vec (vec_of_bits [B0] : mword 1) - (concat_vec (vec_of_bits [B0] : mword 1) - (concat_vec - (vec_of_bits [B0] : mword 1) - (vec_of_bits [B0] : mword 1)))))))))))))))) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B1;B0] : mword 3)))) then - returnm ((mips_zero_extend 64 - (concat_vec (vec_of_bits [B1] : mword 1) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) - (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) - (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) - (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) - (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) - (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) - (vec_of_bits [B0;B0;B0;B0] : mword 4)))))))))) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B1;B1] : mword 3)))) then - returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) - : mword 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B1;B0;B1] : mword 3)))) then - returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) - : mword 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg CP0LLAddr_ref : M (mword 64)) - : M (bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B1;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B1;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - read_reg TLBXContext_ref >>= fun w__19 => - returnm ((_get_XContextReg_bits w__19) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B1;B1;B1;B1;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg CP0ErrorEPC_ref : M (mword 64)) - : M (bits 64) - else (SignalException ResI) : M (bits 64)) - : M (mword 64) - end >>= fun result => - (wGPR rt (if (double) then result else mips_sign_extend 64 (subrange_vec_dec result 31 0))) - : M (unit). - -Definition execute_MADDU (rs : mword 5) (rt : mword 5) -: M (unit) := - rGPR rs >>= fun rsVal => - rGPR rt >>= fun rtVal => - (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (bits 64) - else returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) : bits 64)) >>= fun mul_result => - (read_reg HI_ref : M (mword 64)) >>= fun w__1 => - (read_reg LO_ref : M (mword 64)) >>= fun w__2 => - let result := - add_vec mul_result (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) in - write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> - write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) - : M (unit). - -Definition execute_MADD (rs : mword 5) (rt : mword 5) -: M (unit) := - rGPR rs >>= fun rsVal => - rGPR rt >>= fun rtVal => - (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (bits 64) - else - returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) - : bits 64)) >>= fun mul_result => - (read_reg HI_ref : M (mword 64)) >>= fun w__1 => - (read_reg LO_ref : M (mword 64)) >>= fun w__2 => - let result := - add_vec mul_result (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) in - write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> - write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) - : M (unit). - -Definition execute_Load (width : WordType) (sign : bool) (linked : bool) (base : mword 5) (rt : mword 5) (offset : mword 16) -: M (unit) := - rGPR base >>= fun w__0 => - let vAddr : bits 64 := addrWrapper (add_vec (mips_sign_extend 64 offset) w__0) LoadData width in - (if ((negb (isAddressAligned vAddr width))) then (SignalExceptionBadAddr AdEL vAddr) : M (unit) - else - TLBTranslate vAddr LoadData >>= fun pAddr => - (if (linked) then - write_reg CP0LLBit_ref (vec_of_bits [B1] : mword 1) >> - write_reg CP0LLAddr_ref pAddr >> - (match width with - | W => - MEMr_reserve_wrapper pAddr 4 >>= fun w__1 => - returnm ((extendLoad w__1 sign) - : bits 64) - | D => - MEMr_reserve_wrapper pAddr 8 >>= fun w__2 => - returnm ((extendLoad w__2 sign) - : bits 64) - | _ => (throw (Error_internal_error tt)) : M (mword 64) - end) - : M (mword 64) - else - (match width with - | B => MEMr_wrapper pAddr 1 >>= fun w__5 => returnm ((extendLoad w__5 sign) : bits 64) - | H => MEMr_wrapper pAddr 2 >>= fun w__6 => returnm ((extendLoad w__6 sign) : bits 64) - | W => MEMr_wrapper pAddr 4 >>= fun w__7 => returnm ((extendLoad w__7 sign) : bits 64) - | D => MEMr_wrapper pAddr 8 >>= fun w__8 => returnm ((extendLoad w__8 sign) : bits 64) - end) - : M (mword 64)) >>= fun memResult => - (wGPR rt memResult) - : M (unit)) - : M (unit). - -Definition execute_LWR (base : mword 5) (rt : mword 5) (offset : mword 16) -: M (unit) := - rGPR base >>= fun w__0 => - let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData WR in - TLBTranslate vAddr LoadData >>= fun pAddr => - MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0] : mword 2)) 4 >>= fun mem_val => - rGPR rt >>= fun reg_val => - let b__4 := subrange_vec_dec vAddr 1 0 in - let result : bits 32 := - if ((eq_vec b__4 (vec_of_bits [B0;B0] : mword 2))) then - concat_vec (subrange_vec_dec reg_val 31 8) (subrange_vec_dec mem_val 31 24) - else if ((eq_vec b__4 (vec_of_bits [B0;B1] : mword 2))) then - concat_vec (subrange_vec_dec reg_val 31 16) (subrange_vec_dec mem_val 31 16) - else if ((eq_vec b__4 (vec_of_bits [B1;B0] : mword 2))) then - concat_vec (subrange_vec_dec reg_val 31 24) (subrange_vec_dec mem_val 31 8) - else mem_val in - (wGPR rt (mips_sign_extend 64 result)) - : M (unit). - -Definition execute_LWL (base : mword 5) (rt : mword 5) (offset : mword 16) -: M (unit) := - rGPR base >>= fun w__0 => - let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData WL in - TLBTranslate vAddr LoadData >>= fun pAddr => - MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0] : mword 2)) 4 >>= fun mem_val => - rGPR rt >>= fun reg_val => - let b__0 := subrange_vec_dec vAddr 1 0 in - let result : bits 32 := - if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then mem_val - else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then - concat_vec (subrange_vec_dec mem_val 23 0) (subrange_vec_dec reg_val 7 0) - else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then - concat_vec (subrange_vec_dec mem_val 15 0) (subrange_vec_dec reg_val 15 0) - else concat_vec (subrange_vec_dec mem_val 7 0) (subrange_vec_dec reg_val 23 0) in - (wGPR rt (mips_sign_extend 64 result)) - : M (unit). - -Definition execute_LUI (rt : mword 5) (imm : mword 16) -: M (unit) := - (wGPR rt - (mips_sign_extend 64 - (concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16)))) - : M (unit). - -Definition execute_LDR (base : mword 5) (rt : mword 5) (offset : mword 16) -: M (unit) := - rGPR base >>= fun w__0 => - let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData DR in - TLBTranslate vAddr LoadData >>= fun pAddr => - MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0] : mword 3)) 8 >>= fun mem_val => - rGPR rt >>= fun reg_val => - let b__24 := subrange_vec_dec vAddr 2 0 in - (wGPR rt - (if ((eq_vec b__24 (vec_of_bits [B0;B0;B0] : mword 3))) then - concat_vec (subrange_vec_dec reg_val 63 8) (subrange_vec_dec mem_val 63 56) - else if ((eq_vec b__24 (vec_of_bits [B0;B0;B1] : mword 3))) then - concat_vec (subrange_vec_dec reg_val 63 16) (subrange_vec_dec mem_val 63 48) - else if ((eq_vec b__24 (vec_of_bits [B0;B1;B0] : mword 3))) then - concat_vec (subrange_vec_dec reg_val 63 24) (subrange_vec_dec mem_val 63 40) - else if ((eq_vec b__24 (vec_of_bits [B0;B1;B1] : mword 3))) then - concat_vec (subrange_vec_dec reg_val 63 32) (subrange_vec_dec mem_val 63 32) - else if ((eq_vec b__24 (vec_of_bits [B1;B0;B0] : mword 3))) then - concat_vec (subrange_vec_dec reg_val 63 40) (subrange_vec_dec mem_val 63 24) - else if ((eq_vec b__24 (vec_of_bits [B1;B0;B1] : mword 3))) then - concat_vec (subrange_vec_dec reg_val 63 48) (subrange_vec_dec mem_val 63 16) - else if ((eq_vec b__24 (vec_of_bits [B1;B1;B0] : mword 3))) then - concat_vec (subrange_vec_dec reg_val 63 56) (subrange_vec_dec mem_val 63 8) - else mem_val)) - : M (unit). - -Definition execute_LDL (base : mword 5) (rt : mword 5) (offset : mword 16) -: M (unit) := - rGPR base >>= fun w__0 => - let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData DL in - TLBTranslate vAddr LoadData >>= fun pAddr => - MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0] : mword 3)) 8 >>= fun mem_val => - rGPR rt >>= fun reg_val => - let b__16 := subrange_vec_dec vAddr 2 0 in - (wGPR rt - (if ((eq_vec b__16 (vec_of_bits [B0;B0;B0] : mword 3))) then mem_val - else if ((eq_vec b__16 (vec_of_bits [B0;B0;B1] : mword 3))) then - concat_vec (subrange_vec_dec mem_val 55 0) (subrange_vec_dec reg_val 7 0) - else if ((eq_vec b__16 (vec_of_bits [B0;B1;B0] : mword 3))) then - concat_vec (subrange_vec_dec mem_val 47 0) (subrange_vec_dec reg_val 15 0) - else if ((eq_vec b__16 (vec_of_bits [B0;B1;B1] : mword 3))) then - concat_vec (subrange_vec_dec mem_val 39 0) (subrange_vec_dec reg_val 23 0) - else if ((eq_vec b__16 (vec_of_bits [B1;B0;B0] : mword 3))) then - concat_vec (subrange_vec_dec mem_val 31 0) (subrange_vec_dec reg_val 31 0) - else if ((eq_vec b__16 (vec_of_bits [B1;B0;B1] : mword 3))) then - concat_vec (subrange_vec_dec mem_val 23 0) (subrange_vec_dec reg_val 39 0) - else if ((eq_vec b__16 (vec_of_bits [B1;B1;B0] : mword 3))) then - concat_vec (subrange_vec_dec mem_val 15 0) (subrange_vec_dec reg_val 47 0) - else concat_vec (subrange_vec_dec mem_val 7 0) (subrange_vec_dec reg_val 55 0))) - : M (unit). - -Definition execute_JR (rs : mword 5) -: M (unit) := - rGPR rs >>= fun w__0 => (execute_branch w__0) : M (unit). - -Definition execute_JALR (rs : mword 5) (rd : mword 5) -: M (unit) := - rGPR rs >>= fun w__0 => - execute_branch w__0 >> - (read_reg PC_ref : M (mword 64)) >>= fun w__1 => (wGPR rd (add_vec_int w__1 8)) : M (unit). - -Definition execute_JAL (offset : mword 26) -: M (unit) := - (read_reg PC_ref : M (mword 64)) >>= fun w__0 => - execute_branch - (concat_vec (subrange_vec_dec (add_vec_int w__0 4) 63 28) - (concat_vec offset (vec_of_bits [B0;B0] : mword 2))) >> - (read_reg PC_ref : M (mword 64)) >>= fun w__1 => - (wGPR (vec_of_bits [B1;B1;B1;B1;B1] : mword 5) (add_vec_int w__1 8)) - : M (unit). - -Definition execute_J (offset : mword 26) -: M (unit) := - (read_reg PC_ref : M (mword 64)) >>= fun w__0 => - (execute_branch - (concat_vec (subrange_vec_dec (add_vec_int w__0 4) 63 28) - (concat_vec offset (vec_of_bits [B0;B0] : mword 2)))) - : M (unit). - -Definition execute_HCF (g__18 : unit) : unit := tt. - -Definition execute_ERET (g__23 : unit) -: M (unit) := - checkCP0Access tt >> - let '_ := (ERETHook tt) : unit in - write_reg CP0LLBit_ref (vec_of_bits [B0] : mword 1) >> - read_reg CP0Status_ref >>= fun w__0 => - (if ((Bool.eqb ((bits_to_bool (_get_StatusReg_ERL w__0)) : bool) ((bit_to_bool B1) : bool))) - then - (read_reg CP0ErrorEPC_ref : M (mword 64)) >>= fun w__1 => - write_reg nextPC_ref w__1 >> - (_set_StatusReg_ERL CP0Status_ref (vec_of_bits [B0] : mword 1)) - : M (unit) - else - (read_reg CP0EPC_ref : M (mword 64)) >>= fun w__2 => - write_reg nextPC_ref w__2 >> - (_set_StatusReg_EXL CP0Status_ref (vec_of_bits [B0] : mword 1)) - : M (unit)) - : M (unit). - -Definition execute_DSUBU (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rs >>= fun w__0 => rGPR rt >>= fun w__1 => (wGPR rd (sub_vec w__0 w__1)) : M (unit). - -Definition execute_DSUB (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rs >>= fun w__0 => - rGPR rt >>= fun w__1 => - let temp65 : bits 65 := sub_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 w__1) in - (if ((neq_bool ((bit_to_bool (access_vec_dec temp65 64)) : bool) - ((bit_to_bool (access_vec_dec temp65 63)) - : bool))) then - (SignalException Ov) - : M (unit) - else (wGPR rd (subrange_vec_dec temp65 63 0)) : M (unit)) - : M (unit). - -Definition execute_DSRLV (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rt >>= fun temp => - rGPR rs >>= fun w__0 => - let sa := subrange_vec_dec w__0 5 0 in - shift_bits_right temp sa >>= fun w__1 => (wGPR rd w__1) : M (unit). - -Definition execute_DSRL32 (rt : mword 5) (rd : mword 5) (sa : mword 5) -: M (unit) := - rGPR rt >>= fun temp => - let sa32 := concat_vec (vec_of_bits [B1] : mword 1) sa in - shift_bits_right temp sa32 >>= fun w__0 => (wGPR rd w__0) : M (unit). - -Definition execute_DSRL (rt : mword 5) (rd : mword 5) (sa : mword 5) -: M (unit) := - rGPR rt >>= fun temp => shift_bits_right temp sa >>= fun w__0 => (wGPR rd w__0) : M (unit). - -Definition execute_DSRAV (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rt >>= fun temp => - rGPR rs >>= fun w__0 => - let sa := subrange_vec_dec w__0 5 0 in - shift_bits_right_arith temp sa >>= fun w__1 => (wGPR rd w__1) : M (unit). - -Definition execute_DSRA32 (rt : mword 5) (rd : mword 5) (sa : mword 5) -: M (unit) := - rGPR rt >>= fun temp => - let sa32 := concat_vec (vec_of_bits [B1] : mword 1) sa in - shift_bits_right_arith temp sa32 >>= fun w__0 => (wGPR rd w__0) : M (unit). - -Definition execute_DSRA (rt : mword 5) (rd : mword 5) (sa : mword 5) -: M (unit) := - rGPR rt >>= fun temp => shift_bits_right_arith temp sa >>= fun w__0 => (wGPR rd w__0) : M (unit). - -Definition execute_DSLLV (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rt >>= fun w__0 => - rGPR rs >>= fun w__1 => - shift_bits_left w__0 (subrange_vec_dec w__1 5 0) >>= fun w__2 => (wGPR rd w__2) : M (unit). - -Definition execute_DSLL32 (rt : mword 5) (rd : mword 5) (sa : mword 5) -: M (unit) := - rGPR rt >>= fun w__0 => - shift_bits_left w__0 (concat_vec (vec_of_bits [B1] : mword 1) sa) >>= fun w__1 => - (wGPR rd w__1) - : M (unit). - -Definition execute_DSLL (rt : mword 5) (rd : mword 5) (sa : mword 5) -: M (unit) := - rGPR rt >>= fun w__0 => shift_bits_left w__0 sa >>= fun w__1 => (wGPR rd w__1) : M (unit). - -Definition execute_DMULTU (rs : mword 5) (rt : mword 5) -: M (unit) := - rGPR rs >>= fun w__0 => - rGPR rt >>= fun w__1 => - let result := mult_vec w__0 w__1 in - write_reg HI_ref (subrange_vec_dec result 127 64) >> - write_reg LO_ref (subrange_vec_dec result 63 0) - : M (unit). - -Definition execute_DMULT (rs : mword 5) (rt : mword 5) -: M (unit) := - rGPR rs >>= fun w__0 => - rGPR rt >>= fun w__1 => - let result := mults_vec w__0 w__1 in - write_reg HI_ref (subrange_vec_dec result 127 64) >> - write_reg LO_ref (subrange_vec_dec result 63 0) - : M (unit). - -Definition execute_DIVU (rs : mword 5) (rt : mword 5) -: M (unit) := - rGPR rs >>= fun rsVal => - rGPR rt >>= fun rtVal => - (if ((orb (NotWordVal rsVal) - (orb (NotWordVal rtVal) - (eq_vec rtVal - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64))))) then - undefined_bitvector 32 >>= fun w__0 => - undefined_bitvector 32 >>= fun w__1 => - returnm ((w__0 : bits 32, w__1 : bits 32) - : (bits 32 * bits 32)) - else - let '(existT _ si _) := uint (subrange_vec_dec rsVal 31 0) in - let '(existT _ ti _) := uint (subrange_vec_dec rtVal 31 0) in - let qi := Z.quot si ti in - let ri := Z.rem si ti in - returnm ((to_bits 32 qi, to_bits 32 ri) - : (mword 32 * mword 32))) >>= fun '(q, r) => - write_reg HI_ref (mips_sign_extend 64 r) >> write_reg LO_ref (mips_sign_extend 64 q) : M (unit). - -Definition execute_DIV (rs : mword 5) (rt : mword 5) -: M (unit) := - rGPR rs >>= fun rsVal => - rGPR rt >>= fun rtVal => - (if ((orb (NotWordVal rsVal) - (orb (NotWordVal rtVal) - (eq_vec rtVal - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64))))) then - undefined_bitvector 32 >>= fun w__0 => - undefined_bitvector 32 >>= fun w__1 => - returnm ((w__0 : bits 32, w__1 : bits 32) - : (bits 32 * bits 32)) - else - let '(existT _ si _) := sint (subrange_vec_dec rsVal 31 0) in - let '(existT _ ti _) := sint (subrange_vec_dec rtVal 31 0) in - let qi := Z.quot si ti in - let ri := Z.sub si (Z.mul ti qi) in - returnm ((to_bits 32 qi, to_bits 32 ri) - : (mword 32 * mword 32))) >>= fun '(q, r) => - write_reg HI_ref (mips_sign_extend 64 r) >> write_reg LO_ref (mips_sign_extend 64 q) : M (unit). - -Definition execute_DDIVU (rs : mword 5) (rt : mword 5) -: M (unit) := - rGPR rs >>= fun w__0 => - let '(existT _ rsVal _) := uint w__0 in - rGPR rt >>= fun w__1 => - let '(existT _ rtVal _) := uint w__1 in - (if ((eq_range (build_ex rtVal) (build_ex 0))) then - undefined_bitvector 64 >>= fun w__2 => - undefined_bitvector 64 >>= fun w__3 => - returnm ((w__2 : bits 64, w__3 : bits 64) - : (bits 64 * bits 64)) - else - let qi := Z.quot rsVal rtVal in - let ri := Z.rem rsVal rtVal in - returnm ((to_bits 64 qi, to_bits 64 ri) - : (mword 64 * mword 64))) >>= fun '(q, r) => - write_reg LO_ref q >> write_reg HI_ref r : M (unit). - -Definition execute_DDIV (rs : mword 5) (rt : mword 5) -: M (unit) := - rGPR rs >>= fun w__0 => - let '(existT _ rsVal _) := sint w__0 in - rGPR rt >>= fun w__1 => - let '(existT _ rtVal _) := sint w__1 in - (if ((eq_range (build_ex rtVal) (build_ex 0))) then - undefined_bitvector 64 >>= fun w__2 => - undefined_bitvector 64 >>= fun w__3 => - returnm ((w__2 : bits 64, w__3 : bits 64) - : (bits 64 * bits 64)) - else - let qi := Z.quot rsVal rtVal in - let ri := Z.sub rsVal (Z.mul qi rtVal) in - returnm ((to_bits 64 qi, to_bits 64 ri) - : (mword 64 * mword 64))) >>= fun '(q, r) => - write_reg LO_ref q >> write_reg HI_ref r : M (unit). - -Definition execute_DADDU (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rs >>= fun w__0 => rGPR rt >>= fun w__1 => (wGPR rd (add_vec w__0 w__1)) : M (unit). - -Definition execute_DADDIU (rs : mword 5) (rt : mword 5) (imm : mword 16) -: M (unit) := - rGPR rs >>= fun w__0 => (wGPR rt (add_vec w__0 (mips_sign_extend 64 imm))) : M (unit). - -Definition execute_DADDI (rs : mword 5) (rt : mword 5) (imm : mword 16) -: M (unit) := - rGPR rs >>= fun w__0 => - let sum65 : bits 65 := add_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 imm) in - (if ((neq_bool ((bit_to_bool (access_vec_dec sum65 64)) : bool) - ((bit_to_bool (access_vec_dec sum65 63)) - : bool))) then - (SignalException Ov) - : M (unit) - else (wGPR rt (subrange_vec_dec sum65 63 0)) : M (unit)) - : M (unit). - -Definition execute_DADD (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rs >>= fun w__0 => - rGPR rt >>= fun w__1 => - let sum65 : bits 65 := add_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 w__1) in - (if ((neq_bool ((bit_to_bool (access_vec_dec sum65 64)) : bool) - ((bit_to_bool (access_vec_dec sum65 63)) - : bool))) then - (SignalException Ov) - : M (unit) - else (wGPR rd (subrange_vec_dec sum65 63 0)) : M (unit)) - : M (unit). - -Definition execute_CACHE (base : mword 5) (op : mword 5) (imm : mword 16) -: M (unit) := - (checkCP0Access tt) - : M (unit). - -Definition execute_BREAK (g__15 : unit) : M (unit) := (SignalException Bp) : M (unit). - -Definition execute_BEQ (rs : mword 5) (rd : mword 5) (imm : mword 16) (ne : bool) (likely : bool) -: M (unit) := - rGPR rs >>= fun w__0 => - rGPR rd >>= fun w__1 => - (if (((bits_to_bool - (xor_vec ((bool_to_bits (eq_vec w__0 w__1)) : mword 1) ((bool_to_bits ne) : mword 1))) - : bool)) then - let offset : bits 64 := - add_vec_int (mips_sign_extend 64 (concat_vec imm (vec_of_bits [B0;B0] : mword 2))) 4 in - (read_reg PC_ref : M (mword 64)) >>= fun w__2 => - (execute_branch (add_vec w__2 offset)) - : M (unit) - else if (likely) then - (read_reg PC_ref : M (mword 64)) >>= fun w__3 => - write_reg nextPC_ref (add_vec_int w__3 8) - : M (unit) - else returnm (tt : unit)) - : M (unit). - -Definition execute_BCMPZ (rs : mword 5) (imm : mword 16) (cmp : Comparison) (link : bool) (likely : bool) -: M (unit) := - (read_reg PC_ref : M (mword 64)) >>= fun w__0 => - let linkVal := add_vec_int w__0 8 in - rGPR rs >>= fun regVal => - let condition := compare cmp regVal (mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) in - (if (condition) then - let offset : bits 64 := - add_vec_int (mips_sign_extend 64 (concat_vec imm (vec_of_bits [B0;B0] : mword 2))) 4 in - (read_reg PC_ref : M (mword 64)) >>= fun w__1 => - (execute_branch (add_vec w__1 offset)) - : M (unit) - else if (likely) then - (read_reg PC_ref : M (mword 64)) >>= fun w__2 => - write_reg nextPC_ref (add_vec_int w__2 8) - : M (unit) - else returnm (tt : unit)) >> - (if (link) then (wGPR (vec_of_bits [B1;B1;B1;B1;B1] : mword 5) linkVal) : M (unit) - else returnm (tt : unit)) - : M (unit). - -Definition execute_ANDI (rs : mword 5) (rt : mword 5) (imm : mword 16) -: M (unit) := - rGPR rs >>= fun w__0 => (wGPR rt (and_vec w__0 (mips_zero_extend 64 imm))) : M (unit). - -Definition execute_AND (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rs >>= fun w__0 => rGPR rt >>= fun w__1 => (wGPR rd (and_vec w__0 w__1)) : M (unit). - -Definition execute_ADDU (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rs >>= fun opA => - rGPR rt >>= fun opB => - (if ((orb (NotWordVal opA) (NotWordVal opB))) then - undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0) : M (unit) - else - (wGPR rd - (mips_sign_extend 64 (add_vec (subrange_vec_dec opA 31 0) (subrange_vec_dec opB 31 0)))) - : M (unit)) - : M (unit). - -Definition execute_ADDIU (rs : mword 5) (rt : mword 5) (imm : mword 16) -: M (unit) := - rGPR rs >>= fun opA => - (if ((NotWordVal opA)) then undefined_bitvector 64 >>= fun w__0 => (wGPR rt w__0) : M (unit) - else - (wGPR rt (mips_sign_extend 64 (add_vec (subrange_vec_dec opA 31 0) (mips_sign_extend 32 imm)))) - : M (unit)) - : M (unit). - -Definition execute_ADDI (rs : mword 5) (rt : mword 5) (imm : mword 16) -: M (unit) := - rGPR rs >>= fun opA => - (if ((NotWordVal opA)) then undefined_bitvector 64 >>= fun w__0 => (wGPR rt w__0) : M (unit) - else - let sum33 : bits 33 := - add_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0)) (mips_sign_extend 33 imm) in - (if ((neq_bool ((bit_to_bool (access_vec_dec sum33 32)) : bool) - ((bit_to_bool (access_vec_dec sum33 31)) - : bool))) then - (SignalException Ov) - : M (unit) - else (wGPR rt (mips_sign_extend 64 (subrange_vec_dec sum33 31 0))) : M (unit)) - : M (unit)) - : M (unit). - -Definition execute_ADD (rs : mword 5) (rt : mword 5) (rd : mword 5) -: M (unit) := - rGPR rs >>= fun opA => - rGPR rt >>= fun opB => - (if ((orb (NotWordVal opA) (NotWordVal opB))) then - undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0) : M (unit) - else - let sum33 : bits 33 := - add_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0)) - (mips_sign_extend 33 (subrange_vec_dec opB 31 0)) in - (if ((neq_bool ((bit_to_bool (access_vec_dec sum33 32)) : bool) - ((bit_to_bool (access_vec_dec sum33 31)) - : bool))) then - (SignalException Ov) - : M (unit) - else (wGPR rd (mips_sign_extend 64 (subrange_vec_dec sum33 31 0))) : M (unit)) - : M (unit)) - : M (unit). - -Definition execute (merge_var : ast) -: M (unit) := - match merge_var with - | DADDIU (rs,rt,imm) => (execute_DADDIU rs rt imm) : M (unit) - | DADDU (rs,rt,rd) => (execute_DADDU rs rt rd) : M (unit) - | DADDI (rs,rt,imm) => (execute_DADDI rs rt imm) : M (unit) - | DADD (rs,rt,rd) => (execute_DADD rs rt rd) : M (unit) - | ADD (rs,rt,rd) => (execute_ADD rs rt rd) : M (unit) - | ADDI (rs,rt,imm) => (execute_ADDI rs rt imm) : M (unit) - | ADDU (rs,rt,rd) => (execute_ADDU rs rt rd) : M (unit) - | ADDIU (rs,rt,imm) => (execute_ADDIU rs rt imm) : M (unit) - | DSUBU (rs,rt,rd) => (execute_DSUBU rs rt rd) : M (unit) - | DSUB (rs,rt,rd) => (execute_DSUB rs rt rd) : M (unit) - | SUB (rs,rt,rd) => (execute_SUB rs rt rd) : M (unit) - | SUBU (rs,rt,rd) => (execute_SUBU rs rt rd) : M (unit) - | AND (rs,rt,rd) => (execute_AND rs rt rd) : M (unit) - | ANDI (rs,rt,imm) => (execute_ANDI rs rt imm) : M (unit) - | OR (rs,rt,rd) => (execute_OR rs rt rd) : M (unit) - | ORI (rs,rt,imm) => (execute_ORI rs rt imm) : M (unit) - | NOR (rs,rt,rd) => (execute_NOR rs rt rd) : M (unit) - | XOR (rs,rt,rd) => (execute_XOR rs rt rd) : M (unit) - | XORI (rs,rt,imm) => (execute_XORI rs rt imm) : M (unit) - | LUI (rt,imm) => (execute_LUI rt imm) : M (unit) - | DSLL (rt,rd,sa) => (execute_DSLL rt rd sa) : M (unit) - | DSLL32 (rt,rd,sa) => (execute_DSLL32 rt rd sa) : M (unit) - | DSLLV (rs,rt,rd) => (execute_DSLLV rs rt rd) : M (unit) - | DSRA (rt,rd,sa) => (execute_DSRA rt rd sa) : M (unit) - | DSRA32 (rt,rd,sa) => (execute_DSRA32 rt rd sa) : M (unit) - | DSRAV (rs,rt,rd) => (execute_DSRAV rs rt rd) : M (unit) - | DSRL (rt,rd,sa) => (execute_DSRL rt rd sa) : M (unit) - | DSRL32 (rt,rd,sa) => (execute_DSRL32 rt rd sa) : M (unit) - | DSRLV (rs,rt,rd) => (execute_DSRLV rs rt rd) : M (unit) - | SLL (rt,rd,sa) => (execute_SLL rt rd sa) : M (unit) - | SLLV (rs,rt,rd) => (execute_SLLV rs rt rd) : M (unit) - | SRA (rt,rd,sa) => (execute_SRA rt rd sa) : M (unit) - | SRAV (rs,rt,rd) => (execute_SRAV rs rt rd) : M (unit) - | SRL (rt,rd,sa) => (execute_SRL rt rd sa) : M (unit) - | SRLV (rs,rt,rd) => (execute_SRLV rs rt rd) : M (unit) - | SLT (rs,rt,rd) => (execute_SLT rs rt rd) : M (unit) - | SLTI (rs,rt,imm) => (execute_SLTI rs rt imm) : M (unit) - | SLTU (rs,rt,rd) => (execute_SLTU rs rt rd) : M (unit) - | SLTIU (rs,rt,imm) => (execute_SLTIU rs rt imm) : M (unit) - | MOVN (rs,rt,rd) => (execute_MOVN rs rt rd) : M (unit) - | MOVZ (rs,rt,rd) => (execute_MOVZ rs rt rd) : M (unit) - | MFHI (rd) => (execute_MFHI rd) : M (unit) - | MFLO (rd) => (execute_MFLO rd) : M (unit) - | MTHI (rs) => (execute_MTHI rs) : M (unit) - | MTLO (rs) => (execute_MTLO rs) : M (unit) - | MUL (rs,rt,rd) => (execute_MUL rs rt rd) : M (unit) - | MULT (rs,rt) => (execute_MULT rs rt) : M (unit) - | MULTU (rs,rt) => (execute_MULTU rs rt) : M (unit) - | DMULT (rs,rt) => (execute_DMULT rs rt) : M (unit) - | DMULTU (rs,rt) => (execute_DMULTU rs rt) : M (unit) - | MADD (rs,rt) => (execute_MADD rs rt) : M (unit) - | MADDU (rs,rt) => (execute_MADDU rs rt) : M (unit) - | MSUB (rs,rt) => (execute_MSUB rs rt) : M (unit) - | MSUBU (rs,rt) => (execute_MSUBU rs rt) : M (unit) - | DIV (rs,rt) => (execute_DIV rs rt) : M (unit) - | DIVU (rs,rt) => (execute_DIVU rs rt) : M (unit) - | DDIV (rs,rt) => (execute_DDIV rs rt) : M (unit) - | DDIVU (rs,rt) => (execute_DDIVU rs rt) : M (unit) - | J (offset) => (execute_J offset) : M (unit) - | JAL (offset) => (execute_JAL offset) : M (unit) - | JR (rs) => (execute_JR rs) : M (unit) - | JALR (rs,rd) => (execute_JALR rs rd) : M (unit) - | BEQ (rs,rd,imm,ne,likely) => (execute_BEQ rs rd imm ne likely) : M (unit) - | BCMPZ (rs,imm,cmp,link,likely) => (execute_BCMPZ rs imm cmp link likely) : M (unit) - | SYSCALL (g__14) => (execute_SYSCALL g__14) : M (unit) - | BREAK (g__15) => (execute_BREAK g__15) : M (unit) - | WAIT (g__16) => (execute_WAIT g__16) : M (unit) - | TRAPREG (rs,rt,cmp) => (execute_TRAPREG rs rt cmp) : M (unit) - | TRAPIMM (rs,imm,cmp) => (execute_TRAPIMM rs imm cmp) : M (unit) - | Load (width,sign,linked,base,rt,offset) => - (execute_Load width sign linked base rt offset) : M (unit) - | Store (width,conditional,base,rt,offset) => - (execute_Store width conditional base rt offset) : M (unit) - | LWL (base,rt,offset) => (execute_LWL base rt offset) : M (unit) - | LWR (base,rt,offset) => (execute_LWR base rt offset) : M (unit) - | SWL (base,rt,offset) => (execute_SWL base rt offset) : M (unit) - | SWR (base,rt,offset) => (execute_SWR base rt offset) : M (unit) - | LDL (base,rt,offset) => (execute_LDL base rt offset) : M (unit) - | LDR (base,rt,offset) => (execute_LDR base rt offset) : M (unit) - | SDL (base,rt,offset) => (execute_SDL base rt offset) : M (unit) - | SDR (base,rt,offset) => (execute_SDR base rt offset) : M (unit) - | CACHE (base,op,imm) => (execute_CACHE base op imm) : M (unit) - | SYNC (g__17) => (execute_SYNC g__17) : M (unit) - | MFC0 (rt,rd,sel,double) => (execute_MFC0 rt rd sel double) : M (unit) - | HCF (g__18) => returnm ((execute_HCF g__18) : unit) - | MTC0 (rt,rd,sel,double) => (execute_MTC0 rt rd sel double) : M (unit) - | TLBWI (g__19) => (execute_TLBWI g__19) : M (unit) - | TLBWR (g__20) => (execute_TLBWR g__20) : M (unit) - | TLBR (g__21) => (execute_TLBR g__21) : M (unit) - | TLBP (g__22) => (execute_TLBP g__22) : M (unit) - | RDHWR (rt,rd) => (execute_RDHWR rt rd) : M (unit) - | ERET (g__23) => (execute_ERET g__23) : M (unit) - | RI (g__24) => (execute_RI g__24) : M (unit) - end. - -Definition supported_instructions (instr : ast) : option ast := Some instr. - -Definition initialize_registers '(tt : unit) -: M (unit) := - undefined_bitvector 64 >>= fun w__0 => - write_reg PC_ref w__0 >> - undefined_bitvector 64 >>= fun w__1 => - write_reg nextPC_ref w__1 >> - undefined_bitvector 1 >>= fun w__2 => - write_reg TLBProbe_ref w__2 >> - undefined_bitvector 6 >>= fun w__3 => - write_reg TLBIndex_ref w__3 >> - undefined_bitvector 6 >>= fun w__4 => - write_reg TLBRandom_ref w__4 >> - undefined_TLBEntryLoReg tt >>= fun w__5 => - write_reg TLBEntryLo0_ref w__5 >> - undefined_TLBEntryLoReg tt >>= fun w__6 => - write_reg TLBEntryLo1_ref w__6 >> - undefined_ContextReg tt >>= fun w__7 => - write_reg TLBContext_ref w__7 >> - undefined_bitvector 16 >>= fun w__8 => - write_reg TLBPageMask_ref w__8 >> - undefined_bitvector 6 >>= fun w__9 => - write_reg TLBWired_ref w__9 >> - undefined_TLBEntryHiReg tt >>= fun w__10 => - write_reg TLBEntryHi_ref w__10 >> - undefined_XContextReg tt >>= fun w__11 => - write_reg TLBXContext_ref w__11 >> - undefined_TLBEntry tt >>= fun w__12 => - write_reg TLBEntry00_ref w__12 >> - undefined_TLBEntry tt >>= fun w__13 => - write_reg TLBEntry01_ref w__13 >> - undefined_TLBEntry tt >>= fun w__14 => - write_reg TLBEntry02_ref w__14 >> - undefined_TLBEntry tt >>= fun w__15 => - write_reg TLBEntry03_ref w__15 >> - undefined_TLBEntry tt >>= fun w__16 => - write_reg TLBEntry04_ref w__16 >> - undefined_TLBEntry tt >>= fun w__17 => - write_reg TLBEntry05_ref w__17 >> - undefined_TLBEntry tt >>= fun w__18 => - write_reg TLBEntry06_ref w__18 >> - undefined_TLBEntry tt >>= fun w__19 => - write_reg TLBEntry07_ref w__19 >> - undefined_TLBEntry tt >>= fun w__20 => - write_reg TLBEntry08_ref w__20 >> - undefined_TLBEntry tt >>= fun w__21 => - write_reg TLBEntry09_ref w__21 >> - undefined_TLBEntry tt >>= fun w__22 => - write_reg TLBEntry10_ref w__22 >> - undefined_TLBEntry tt >>= fun w__23 => - write_reg TLBEntry11_ref w__23 >> - undefined_TLBEntry tt >>= fun w__24 => - write_reg TLBEntry12_ref w__24 >> - undefined_TLBEntry tt >>= fun w__25 => - write_reg TLBEntry13_ref w__25 >> - undefined_TLBEntry tt >>= fun w__26 => - write_reg TLBEntry14_ref w__26 >> - undefined_TLBEntry tt >>= fun w__27 => - write_reg TLBEntry15_ref w__27 >> - undefined_TLBEntry tt >>= fun w__28 => - write_reg TLBEntry16_ref w__28 >> - undefined_TLBEntry tt >>= fun w__29 => - write_reg TLBEntry17_ref w__29 >> - undefined_TLBEntry tt >>= fun w__30 => - write_reg TLBEntry18_ref w__30 >> - undefined_TLBEntry tt >>= fun w__31 => - write_reg TLBEntry19_ref w__31 >> - undefined_TLBEntry tt >>= fun w__32 => - write_reg TLBEntry20_ref w__32 >> - undefined_TLBEntry tt >>= fun w__33 => - write_reg TLBEntry21_ref w__33 >> - undefined_TLBEntry tt >>= fun w__34 => - write_reg TLBEntry22_ref w__34 >> - undefined_TLBEntry tt >>= fun w__35 => - write_reg TLBEntry23_ref w__35 >> - undefined_TLBEntry tt >>= fun w__36 => - write_reg TLBEntry24_ref w__36 >> - undefined_TLBEntry tt >>= fun w__37 => - write_reg TLBEntry25_ref w__37 >> - undefined_TLBEntry tt >>= fun w__38 => - write_reg TLBEntry26_ref w__38 >> - undefined_TLBEntry tt >>= fun w__39 => - write_reg TLBEntry27_ref w__39 >> - undefined_TLBEntry tt >>= fun w__40 => - write_reg TLBEntry28_ref w__40 >> - undefined_TLBEntry tt >>= fun w__41 => - write_reg TLBEntry29_ref w__41 >> - undefined_TLBEntry tt >>= fun w__42 => - write_reg TLBEntry30_ref w__42 >> - undefined_TLBEntry tt >>= fun w__43 => - write_reg TLBEntry31_ref w__43 >> - undefined_TLBEntry tt >>= fun w__44 => - write_reg TLBEntry32_ref w__44 >> - undefined_TLBEntry tt >>= fun w__45 => - write_reg TLBEntry33_ref w__45 >> - undefined_TLBEntry tt >>= fun w__46 => - write_reg TLBEntry34_ref w__46 >> - undefined_TLBEntry tt >>= fun w__47 => - write_reg TLBEntry35_ref w__47 >> - undefined_TLBEntry tt >>= fun w__48 => - write_reg TLBEntry36_ref w__48 >> - undefined_TLBEntry tt >>= fun w__49 => - write_reg TLBEntry37_ref w__49 >> - undefined_TLBEntry tt >>= fun w__50 => - write_reg TLBEntry38_ref w__50 >> - undefined_TLBEntry tt >>= fun w__51 => - write_reg TLBEntry39_ref w__51 >> - undefined_TLBEntry tt >>= fun w__52 => - write_reg TLBEntry40_ref w__52 >> - undefined_TLBEntry tt >>= fun w__53 => - write_reg TLBEntry41_ref w__53 >> - undefined_TLBEntry tt >>= fun w__54 => - write_reg TLBEntry42_ref w__54 >> - undefined_TLBEntry tt >>= fun w__55 => - write_reg TLBEntry43_ref w__55 >> - undefined_TLBEntry tt >>= fun w__56 => - write_reg TLBEntry44_ref w__56 >> - undefined_TLBEntry tt >>= fun w__57 => - write_reg TLBEntry45_ref w__57 >> - undefined_TLBEntry tt >>= fun w__58 => - write_reg TLBEntry46_ref w__58 >> - undefined_TLBEntry tt >>= fun w__59 => - write_reg TLBEntry47_ref w__59 >> - undefined_TLBEntry tt >>= fun w__60 => - write_reg TLBEntry48_ref w__60 >> - undefined_TLBEntry tt >>= fun w__61 => - write_reg TLBEntry49_ref w__61 >> - undefined_TLBEntry tt >>= fun w__62 => - write_reg TLBEntry50_ref w__62 >> - undefined_TLBEntry tt >>= fun w__63 => - write_reg TLBEntry51_ref w__63 >> - undefined_TLBEntry tt >>= fun w__64 => - write_reg TLBEntry52_ref w__64 >> - undefined_TLBEntry tt >>= fun w__65 => - write_reg TLBEntry53_ref w__65 >> - undefined_TLBEntry tt >>= fun w__66 => - write_reg TLBEntry54_ref w__66 >> - undefined_TLBEntry tt >>= fun w__67 => - write_reg TLBEntry55_ref w__67 >> - undefined_TLBEntry tt >>= fun w__68 => - write_reg TLBEntry56_ref w__68 >> - undefined_TLBEntry tt >>= fun w__69 => - write_reg TLBEntry57_ref w__69 >> - undefined_TLBEntry tt >>= fun w__70 => - write_reg TLBEntry58_ref w__70 >> - undefined_TLBEntry tt >>= fun w__71 => - write_reg TLBEntry59_ref w__71 >> - undefined_TLBEntry tt >>= fun w__72 => - write_reg TLBEntry60_ref w__72 >> - undefined_TLBEntry tt >>= fun w__73 => - write_reg TLBEntry61_ref w__73 >> - undefined_TLBEntry tt >>= fun w__74 => - write_reg TLBEntry62_ref w__74 >> - undefined_TLBEntry tt >>= fun w__75 => - write_reg TLBEntry63_ref w__75 >> - undefined_bitvector 32 >>= fun w__76 => - write_reg CP0Compare_ref w__76 >> - undefined_CauseReg tt >>= fun w__77 => - write_reg CP0Cause_ref w__77 >> - undefined_bitvector 64 >>= fun w__78 => - write_reg CP0EPC_ref w__78 >> - undefined_bitvector 64 >>= fun w__79 => - write_reg CP0ErrorEPC_ref w__79 >> - undefined_bitvector 1 >>= fun w__80 => - write_reg CP0LLBit_ref w__80 >> - undefined_bitvector 64 >>= fun w__81 => - write_reg CP0LLAddr_ref w__81 >> - undefined_bitvector 64 >>= fun w__82 => - write_reg CP0BadVAddr_ref w__82 >> - undefined_bitvector 32 >>= fun w__83 => - write_reg CP0Count_ref w__83 >> - undefined_bitvector 32 >>= fun w__84 => - write_reg CP0HWREna_ref w__84 >> - undefined_bitvector 64 >>= fun w__85 => - write_reg CP0UserLocal_ref w__85 >> - undefined_bitvector 3 >>= fun w__86 => - write_reg CP0ConfigK0_ref w__86 >> - undefined_StatusReg tt >>= fun w__87 => - write_reg CP0Status_ref w__87 >> - undefined_bitvector 1 >>= fun w__88 => - write_reg branchPending_ref w__88 >> - undefined_bitvector 1 >>= fun w__89 => - write_reg inBranchDelay_ref w__89 >> - undefined_bitvector 64 >>= fun w__90 => - write_reg delayedPC_ref w__90 >> - undefined_bitvector 64 >>= fun w__91 => - write_reg HI_ref w__91 >> - undefined_bitvector 64 >>= fun w__92 => - write_reg LO_ref w__92 >> - undefined_bitvector 64 >>= fun w__93 => - undefined_vector 32 w__93 >>= fun w__94 => - write_reg GPR_ref w__94 >> - undefined_bitvector 8 >>= fun w__95 => - write_reg UART_WDATA_ref w__95 >> - undefined_bitvector 1 >>= fun w__96 => - write_reg UART_WRITTEN_ref w__96 >> - undefined_bitvector 8 >>= fun w__97 => - write_reg UART_RDATA_ref w__97 >> - undefined_bitvector 1 >>= fun w__98 => write_reg UART_RVALID_ref w__98 : M (unit). - -Definition initial_regstate : regstate := -{| UART_RVALID := (vec_of_bits [B0] : mword 1); - UART_RDATA := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); - UART_WRITTEN := (vec_of_bits [B0] : mword 1); - UART_WDATA := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); - GPR := - (vec_of_list_len [(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64)]); - LO := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - HI := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - delayedPC := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - inBranchDelay := (vec_of_bits [B0] : mword 1); - branchPending := (vec_of_bits [B0] : mword 1); - CP0Status := - ({| StatusReg_StatusReg_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 32) |}); - CP0ConfigK0 := (vec_of_bits [B0;B0;B0] : mword 3); - CP0UserLocal := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - CP0HWREna := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 32); - CP0Count := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 32); - CP0BadVAddr := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - CP0LLAddr := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - CP0LLBit := (vec_of_bits [B0] : mword 1); - CP0ErrorEPC := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - CP0EPC := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - CP0Cause := - ({| CauseReg_CauseReg_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 32) |}); - CP0Compare := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 32); - TLBEntry63 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry62 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry61 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry60 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry59 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry58 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry57 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry56 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry55 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry54 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry53 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry52 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry51 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry50 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry49 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry48 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry47 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry46 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry45 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry44 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry43 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry42 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry41 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry40 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry39 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry38 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry37 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry36 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry35 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry34 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry33 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry32 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry31 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry30 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry29 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry28 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry27 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry26 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry25 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry24 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry23 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry22 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry21 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry20 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry19 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry18 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry17 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry16 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry15 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry14 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry13 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry12 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry11 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry10 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry09 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry08 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry07 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry06 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry05 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry04 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry03 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry02 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry01 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntry00 := - ({| TLBEntry_TLBEntry_chunk_1 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 53); - TLBEntry_TLBEntry_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBXContext := - ({| XContextReg_XContextReg_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntryHi := - ({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBWired := (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6); - TLBPageMask := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); - TLBContext := - ({| ContextReg_ContextReg_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntryLo1 := - ({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBEntryLo0 := - ({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}); - TLBRandom := (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6); - TLBIndex := (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6); - TLBProbe := (vec_of_bits [B0] : mword 1); - nextPC := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64); - PC := - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) |}. - - -End Content. diff --git a/snapshots/coq/mips/mips_extras.v b/snapshots/coq/mips/mips_extras.v deleted file mode 100644 index cc905f11..00000000 --- a/snapshots/coq/mips/mips_extras.v +++ /dev/null @@ -1,162 +0,0 @@ -Require Import Sail2_instr_kinds. -Require Import Sail2_values. -Require Import Sail2_operators_mwords. -Require Import Sail2_prompt_monad. -Require Import Sail2_prompt. -Require Import String. -Require Import List. -Import List.ListNotations. -(* -val MEMr : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e -val MEMr_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e -val MEMr_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e -val MEMr_tag_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e -*) -Definition MEMr {regval a b e} `{ArithFact (b >= 0)} (addr : mword a) size : monad regval (mword b) e := read_mem Read_plain addr size. -Definition MEMr_reserve {regval a b e} `{ArithFact (b >= 0)} (addr : mword a) size : monad regval (mword b) e := read_mem Read_reserve addr size. - -(*val read_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> monad 'regval bool 'e*) -Definition read_tag_bool {regval a e} (addr : mword a) : monad regval bool e := - read_tag addr >>= fun t => - maybe_fail "read_tag_bool" (bool_of_bitU t). - -(*val write_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> bool -> monad 'regval unit 'e*) -Definition write_tag_bool {regval a e} (addr : mword a) t : monad regval unit e := - write_tag addr (bitU_of_bool t) >>= fun _ => returnm tt. - -Definition MEMr_tag {regval a b e} `{ArithFact (b >= 0)} (addr : mword a) size : monad regval (bool * mword b) e := - read_mem Read_plain addr size >>= fun v => - read_tag_bool addr >>= fun t => - returnm (t, v). - -Definition MEMr_tag_reserve {regval a b e} `{ArithFact (b >= 0)} (addr : mword a) size : monad regval (bool * mword b) e := - read_mem Read_plain addr size >>= fun v => - read_tag_bool addr >>= fun t => - returnm (t, v). - -(* -val MEMea : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e -val MEMea_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e -val MEMea_tag : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e -val MEMea_tag_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e -*) -Definition MEMea {regval a e} (addr : mword a) size : monad regval unit e := write_mem_ea Write_plain addr size. -Definition MEMea_conditional {regval a e} (addr : mword a) size : monad regval unit e := write_mem_ea Write_conditional addr size. - -Definition MEMea_tag {regval a e} (addr : mword a) size : monad regval unit e := write_mem_ea Write_plain addr size. -Definition MEMea_tag_conditional {regval a e} (addr : mword a) size : monad regval unit e := write_mem_ea Write_conditional addr size. - -(* -val MEMval : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval unit 'e -val MEMval_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval bool 'e -val MEMval_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval unit 'e -val MEMval_tag_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval bool 'e -*) -Definition MEMval {regval a b e} (_ : mword a) (size : Z) (v : mword b) : monad regval unit e := write_mem_val v >>= fun _ => returnm tt. -Definition MEMval_conditional {regval a b e} (_ : mword a) (size : Z) (v : mword b) : monad regval bool e := write_mem_val v >>= fun b => returnm (if b then true else false). -Definition MEMval_tag {regval a b e} (addr : mword a) (size : Z) t (v : mword b) : monad regval unit e := write_mem_val v >>= fun _ => write_tag_bool addr t >>= fun _ => returnm tt. -Definition MEMval_tag_conditional {regval a b e} (addr : mword a) (size : Z) t (v : mword b) : monad regval bool e := write_mem_val v >>= fun b => write_tag_bool addr t >>= fun _ => returnm (if b then true else false). - -(*val MEM_sync : forall 'regval 'e. unit -> monad 'regval unit 'e*) - -Definition MEM_sync {regval e} (_:unit) : monad regval unit e := barrier Barrier_MIPS_SYNC. - -(* Some wrappers copied from aarch64_extras *) -(* TODO: Harmonise into a common library *) -(* -Definition get_slice_int_bl len n lo := - (* TODO: Is this the intended behaviour? *) - let hi := lo + len - 1 in - let bs := bools_of_int (hi + 1) n in - subrange_list false bs hi lo - -val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a -Definition get_slice_int len n lo := of_bools (get_slice_int_bl len n lo) -*) -Definition write_ram {rv e} m size (_ : mword m) (addr : mword m) (data : mword (8 * size)) : monad rv unit e := - MEMea addr size >> - MEMval addr size data. - -Definition read_ram {rv e} m size `{ArithFact (size >= 0)} (_ : mword m) (addr : mword m) : monad rv (mword (8 * size)) e := MEMr addr size. -(* -Definition string_of_bits bs := string_of_bv (bits_of bs). -Definition string_of_int := show - -Definition _sign_extend bits len := maybe_failwith (of_bits (exts_bv len bits)) -Definition _zero_extend bits len := maybe_failwith (of_bits (extz_bv len bits)) -*) -Definition shift_bits_left {rv e a b} (v : mword a) (n : mword b) : monad rv (mword a) e := - maybe_fail "shift_bits_left" (unsigned n) >>= fun n => - returnm (shiftl v n). - -Definition shift_bits_right {rv e a b} (v : mword a) (n : mword b) : monad rv (mword a) e := - maybe_fail "shift_bits_right" (unsigned n) >>= fun n => - returnm (shiftr v n). - -Definition shift_bits_right_arith {rv e a b} (v : mword a) (n : mword b) : monad rv (mword a) e := - maybe_fail "shift_bits_right" (unsigned n) >>= fun n => - returnm (arith_shiftr v n). - -(* Use constants for undefined values for now *) -Definition internal_pick {rv a e} (vs : list a) : monad rv a e := -match vs with -| (h::_) => returnm h -| _ => Fail "empty list in internal_pick" -end. -Definition undefined_string {rv e} (_:unit) : monad rv string e := returnm ""%string. -Definition undefined_unit {rv e} (_:unit) : monad rv unit e := returnm tt. -Definition undefined_int {rv e} (_:unit) : monad rv Z e := returnm (0:ii). -(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*) -Definition undefined_vector {rv a e} len (u : a) `{ArithFact (len >= 0)} : monad rv (vec a len) e := returnm (vec_init u len). -(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) -Definition undefined_bitvector {rv e} len `{ArithFact (len >= 0)} : monad rv (mword len) e := returnm (mword_of_int 0). -(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) -Definition undefined_bits {rv e} := @undefined_bitvector rv e. -Definition undefined_bit {rv e} (_:unit) : monad rv bitU e := returnm BU. -(*Definition undefined_real {rv e} (_:unit) : monad rv real e := returnm (realFromFrac 0 1).*) -Definition undefined_range {rv e} i j `{ArithFact (i <= j)} : monad rv {z : Z & ArithFact (i <= z /\ z <= j)} e := returnm (build_ex i). -Definition undefined_atom {rv e} i : monad rv Z e := returnm i. -Definition undefined_nat {rv e} (_:unit) : monad rv Z e := returnm (0:ii). - -Definition skip {rv e} (_:unit) : monad rv unit e := returnm tt. - -(*val elf_entry : unit -> integer*) -Definition elf_entry (_:unit) : Z := 0. -(*declare ocaml target_rep function elf_entry := `Elf_loader.elf_entry`*) - -(*Definition print_bits msg bs := prerr_endline (msg ^ (string_of_bits bs)) - -val get_time_ns : unit -> integer*) -Definition get_time_ns (_:unit) : Z := 0. -(*declare ocaml target_rep function get_time_ns := `(fun () -> Big_int.of_int (int_of_float (1e9 *. Unix.gettimeofday ())))`*) - -Definition eq_bit (x : bitU) (y : bitU) : bool := - match x, y with - | B0, B0 => true - | B1, B1 => true - | BU, BU => true - | _,_ => false - end. - -Require Import Zeuclid. -Definition euclid_modulo (m n : Z) `{ArithFact (n > 0)} : {z : Z & ArithFact (0 <= z <= n-1)}. -refine (build_ex (ZEuclid.modulo m n)). -constructor. -destruct H. -assert (Zabs n = n). { rewrite Zabs_eq; auto with zarith. } -rewrite <- H at 3. -lapply (ZEuclid.mod_always_pos m n); omega. -Qed. - -(* Override the more general version *) - -Definition mults_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mults_vec l r. -Definition mult_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mult_vec l r. - - -Definition print_endline (_:string) : unit := tt. -Definition prerr_endline (_:string) : unit := tt. -Definition prerr_string (_:string) : unit := tt. -Definition putchar {T} (_:T) : unit := tt. -Require DecimalString. -Definition string_of_int z := DecimalString.NilZero.string_of_int (Z.to_int z). diff --git a/snapshots/coq/mips/mips_types.v b/snapshots/coq/mips/mips_types.v deleted file mode 100644 index 12d7d6cd..00000000 --- a/snapshots/coq/mips/mips_types.v +++ /dev/null @@ -1,1441 +0,0 @@ -(*Generated by Sail from mips.*) -Require Import Sail2_instr_kinds. -Require Import Sail2_values. -Require Import Sail2_operators_mwords. -Require Import Sail2_prompt_monad. -Require Import Sail2_prompt. -Require Import Sail2_state. -Definition bits (n : Z) : Type := mword n. - - - -Inductive exception := - ISAException : unit -> exception - | Error_not_implemented : string -> exception - | Error_misaligned_access : unit -> exception - | Error_EBREAK : unit -> exception - | Error_internal_error : unit -> exception. -Arguments exception : clear implicits. - - - -Record CauseReg := { CauseReg_CauseReg_chunk_0 : mword 32; }. -Notation "{[ r 'with' 'CauseReg_CauseReg_chunk_0' := e ]}" := ({| CauseReg_CauseReg_chunk_0 := e |}). - -Record StatusReg := { StatusReg_StatusReg_chunk_0 : mword 32; }. -Notation "{[ r 'with' 'StatusReg_StatusReg_chunk_0' := e ]}" := ({| StatusReg_StatusReg_chunk_0 := e |}). - -Record TLBEntryLoReg := { TLBEntryLoReg_TLBEntryLoReg_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'TLBEntryLoReg_TLBEntryLoReg_chunk_0' := e ]}" := ({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := e |}). - -Record TLBEntryHiReg := { TLBEntryHiReg_TLBEntryHiReg_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'TLBEntryHiReg_TLBEntryHiReg_chunk_0' := e ]}" := ({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := e |}). - -Record ContextReg := { ContextReg_ContextReg_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'ContextReg_ContextReg_chunk_0' := e ]}" := ({| ContextReg_ContextReg_chunk_0 := e |}). - -Record XContextReg := { XContextReg_XContextReg_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'XContextReg_XContextReg_chunk_0' := e ]}" := ({| XContextReg_XContextReg_chunk_0 := e |}). - -Definition TLBIndexT : Type := bits 6. - -Record TLBEntry := { TLBEntry_TLBEntry_chunk_1 : mword 53; TLBEntry_TLBEntry_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'TLBEntry_TLBEntry_chunk_1' := e ]}" := ({| TLBEntry_TLBEntry_chunk_1 := e; TLBEntry_TLBEntry_chunk_0 := TLBEntry_TLBEntry_chunk_0 r |}). -Notation "{[ r 'with' 'TLBEntry_TLBEntry_chunk_0' := e ]}" := ({| TLBEntry_TLBEntry_chunk_0 := e; TLBEntry_TLBEntry_chunk_1 := TLBEntry_TLBEntry_chunk_1 r |}). - -Inductive Exception := - Interrupt - | TLBMod - | TLBL - | TLBS - | AdEL - | AdES - | Sys - | Bp - | ResI - | CpU - | Ov - | Tr - | C2E - | C2Trap - | XTLBRefillL - | XTLBRefillS - | XTLBInvL - | XTLBInvS - | MCheck. -Scheme Equality for Exception. -Instance Decidable_eq_Exception : forall (x y : Exception), Decidable (x = y) := -Decidable_eq_from_dec Exception_eq_dec. - - -Inductive MemAccessType := Instruction | LoadData | StoreData. -Scheme Equality for MemAccessType. -Instance Decidable_eq_MemAccessType : forall (x y : MemAccessType), Decidable (x = y) := -Decidable_eq_from_dec MemAccessType_eq_dec. - - -Inductive AccessLevel := User | Supervisor | Kernel. -Scheme Equality for AccessLevel. -Instance Decidable_eq_AccessLevel : forall (x y : AccessLevel), Decidable (x = y) := -Decidable_eq_from_dec AccessLevel_eq_dec. - - -Definition regno : Type := bits 5. - -Definition imm16 : Type := bits 16. - -Definition regregreg : Type := (regno * regno * regno). - -Definition regregimm16 : Type := (regno * regno * imm16). - -Inductive decode_failure := - no_matching_pattern | unsupported_instruction | illegal_instruction | internal_error. -Scheme Equality for decode_failure. -Instance Decidable_eq_decode_failure : forall (x y : decode_failure), Decidable (x = y) := -Decidable_eq_from_dec decode_failure_eq_dec. - - -Inductive Comparison := EQ' | NE | GE | GEU | GT' | LE | LT' | LTU. -Scheme Equality for Comparison. -Instance Decidable_eq_Comparison : forall (x y : Comparison), Decidable (x = y) := -Decidable_eq_from_dec Comparison_eq_dec. - - -Inductive WordType := B | H | W | D. -Scheme Equality for WordType. -Instance Decidable_eq_WordType : forall (x y : WordType), Decidable (x = y) := -Decidable_eq_from_dec WordType_eq_dec. - - -Inductive WordTypeUnaligned := WL | WR | DL | DR. -Scheme Equality for WordTypeUnaligned. -Instance Decidable_eq_WordTypeUnaligned : forall (x y : WordTypeUnaligned), Decidable (x = y) := -Decidable_eq_from_dec WordTypeUnaligned_eq_dec. - - -Inductive ast := - DADDIU : (regno * regno * imm16) -> ast - | DADDU : (regno * regno * regno) -> ast - | DADDI : (regno * regno * bits 16) -> ast - | DADD : (regno * regno * regno) -> ast - | ADD : (regno * regno * regno) -> ast - | ADDI : (regno * regno * bits 16) -> ast - | ADDU : (regno * regno * regno) -> ast - | ADDIU : (regno * regno * bits 16) -> ast - | DSUBU : (regno * regno * regno) -> ast - | DSUB : (regno * regno * regno) -> ast - | SUB : (regno * regno * regno) -> ast - | SUBU : (regno * regno * regno) -> ast - | AND : (regno * regno * regno) -> ast - | ANDI : (regno * regno * bits 16) -> ast - | OR : (regno * regno * regno) -> ast - | ORI : (regno * regno * bits 16) -> ast - | NOR : (regno * regno * regno) -> ast - | XOR : (regno * regno * regno) -> ast - | XORI : (regno * regno * bits 16) -> ast - | LUI : (regno * imm16) -> ast - | DSLL : (regno * regno * regno) -> ast - | DSLL32 : (regno * regno * regno) -> ast - | DSLLV : (regno * regno * regno) -> ast - | DSRA : (regno * regno * regno) -> ast - | DSRA32 : (regno * regno * regno) -> ast - | DSRAV : (regno * regno * regno) -> ast - | DSRL : (regno * regno * regno) -> ast - | DSRL32 : (regno * regno * regno) -> ast - | DSRLV : (regno * regno * regno) -> ast - | SLL : (regno * regno * regno) -> ast - | SLLV : (regno * regno * regno) -> ast - | SRA : (regno * regno * regno) -> ast - | SRAV : (regno * regno * regno) -> ast - | SRL : (regno * regno * regno) -> ast - | SRLV : (regno * regno * regno) -> ast - | SLT : (regno * regno * regno) -> ast - | SLTI : (regno * regno * bits 16) -> ast - | SLTU : (regno * regno * regno) -> ast - | SLTIU : (regno * regno * bits 16) -> ast - | MOVN : (regno * regno * regno) -> ast - | MOVZ : (regno * regno * regno) -> ast - | MFHI : regno -> ast - | MFLO : regno -> ast - | MTHI : regno -> ast - | MTLO : regno -> ast - | MUL : (regno * regno * regno) -> ast - | MULT : (regno * regno) -> ast - | MULTU : (regno * regno) -> ast - | DMULT : (regno * regno) -> ast - | DMULTU : (regno * regno) -> ast - | MADD : (regno * regno) -> ast - | MADDU : (regno * regno) -> ast - | MSUB : (regno * regno) -> ast - | MSUBU : (regno * regno) -> ast - | DIV : (regno * regno) -> ast - | DIVU : (regno * regno) -> ast - | DDIV : (regno * regno) -> ast - | DDIVU : (regno * regno) -> ast - | J : bits 26 -> ast - | JAL : bits 26 -> ast - | JR : regno -> ast - | JALR : (regno * regno) -> ast - | BEQ : (regno * regno * imm16 * bool * bool) -> ast - | BCMPZ : (regno * imm16 * Comparison * bool * bool) -> ast - | SYSCALL : unit -> ast - | BREAK : unit -> ast - | WAIT : unit -> ast - | TRAPREG : (regno * regno * Comparison) -> ast - | TRAPIMM : (regno * imm16 * Comparison) -> ast - | Load : (WordType * bool * bool * regno * regno * imm16) -> ast - | Store : (WordType * bool * regno * regno * imm16) -> ast - | LWL : (regno * regno * bits 16) -> ast - | LWR : (regno * regno * bits 16) -> ast - | SWL : (regno * regno * bits 16) -> ast - | SWR : (regno * regno * bits 16) -> ast - | LDL : (regno * regno * bits 16) -> ast - | LDR : (regno * regno * bits 16) -> ast - | SDL : (regno * regno * bits 16) -> ast - | SDR : (regno * regno * bits 16) -> ast - | CACHE : (regno * regno * bits 16) -> ast - | SYNC : unit -> ast - | MFC0 : (regno * regno * bits 3 * bool) -> ast - | HCF : unit -> ast - | MTC0 : (regno * regno * bits 3 * bool) -> ast - | TLBWI : unit -> ast - | TLBWR : unit -> ast - | TLBR : unit -> ast - | TLBP : unit -> ast - | RDHWR : (regno * regno) -> ast - | ERET : unit -> ast - | RI : unit -> ast. -Arguments ast : clear implicits. - - - -Inductive register_value := - Regval_vector : (Z * bool * list register_value) -> register_value - | Regval_list : list register_value -> register_value - | Regval_option : option register_value -> register_value - | Regval_CauseReg : CauseReg -> register_value - | Regval_ContextReg : ContextReg -> register_value - | Regval_StatusReg : StatusReg -> register_value - | Regval_TLBEntry : TLBEntry -> register_value - | Regval_TLBEntryHiReg : TLBEntryHiReg -> register_value - | Regval_TLBEntryLoReg : TLBEntryLoReg -> register_value - | Regval_XContextReg : XContextReg -> register_value - | Regval_vector_16_dec_bit : mword 16 -> register_value - | Regval_vector_1_dec_bit : mword 1 -> register_value - | Regval_vector_32_dec_bit : mword 32 -> register_value - | Regval_vector_3_dec_bit : mword 3 -> register_value - | Regval_vector_64_dec_bit : mword 64 -> register_value - | Regval_vector_6_dec_bit : mword 6 -> register_value - | Regval_vector_8_dec_bit : mword 8 -> register_value. -Arguments register_value : clear implicits. - - - -Record regstate := - { UART_RVALID : mword 1; - UART_RDATA : mword 8; - UART_WRITTEN : mword 1; - UART_WDATA : mword 8; - GPR : vec (mword 64) 32; - LO : mword 64; - HI : mword 64; - delayedPC : mword 64; - inBranchDelay : mword 1; - branchPending : mword 1; - CP0Status : StatusReg; - CP0ConfigK0 : mword 3; - CP0UserLocal : mword 64; - CP0HWREna : mword 32; - CP0Count : mword 32; - CP0BadVAddr : mword 64; - CP0LLAddr : mword 64; - CP0LLBit : mword 1; - CP0ErrorEPC : mword 64; - CP0EPC : mword 64; - CP0Cause : CauseReg; - CP0Compare : mword 32; - TLBEntry63 : TLBEntry; - TLBEntry62 : TLBEntry; - TLBEntry61 : TLBEntry; - TLBEntry60 : TLBEntry; - TLBEntry59 : TLBEntry; - TLBEntry58 : TLBEntry; - TLBEntry57 : TLBEntry; - TLBEntry56 : TLBEntry; - TLBEntry55 : TLBEntry; - TLBEntry54 : TLBEntry; - TLBEntry53 : TLBEntry; - TLBEntry52 : TLBEntry; - TLBEntry51 : TLBEntry; - TLBEntry50 : TLBEntry; - TLBEntry49 : TLBEntry; - TLBEntry48 : TLBEntry; - TLBEntry47 : TLBEntry; - TLBEntry46 : TLBEntry; - TLBEntry45 : TLBEntry; - TLBEntry44 : TLBEntry; - TLBEntry43 : TLBEntry; - TLBEntry42 : TLBEntry; - TLBEntry41 : TLBEntry; - TLBEntry40 : TLBEntry; - TLBEntry39 : TLBEntry; - TLBEntry38 : TLBEntry; - TLBEntry37 : TLBEntry; - TLBEntry36 : TLBEntry; - TLBEntry35 : TLBEntry; - TLBEntry34 : TLBEntry; - TLBEntry33 : TLBEntry; - TLBEntry32 : TLBEntry; - TLBEntry31 : TLBEntry; - TLBEntry30 : TLBEntry; - TLBEntry29 : TLBEntry; - TLBEntry28 : TLBEntry; - TLBEntry27 : TLBEntry; - TLBEntry26 : TLBEntry; - TLBEntry25 : TLBEntry; - TLBEntry24 : TLBEntry; - TLBEntry23 : TLBEntry; - TLBEntry22 : TLBEntry; - TLBEntry21 : TLBEntry; - TLBEntry20 : TLBEntry; - TLBEntry19 : TLBEntry; - TLBEntry18 : TLBEntry; - TLBEntry17 : TLBEntry; - TLBEntry16 : TLBEntry; - TLBEntry15 : TLBEntry; - TLBEntry14 : TLBEntry; - TLBEntry13 : TLBEntry; - TLBEntry12 : TLBEntry; - TLBEntry11 : TLBEntry; - TLBEntry10 : TLBEntry; - TLBEntry09 : TLBEntry; - TLBEntry08 : TLBEntry; - TLBEntry07 : TLBEntry; - TLBEntry06 : TLBEntry; - TLBEntry05 : TLBEntry; - TLBEntry04 : TLBEntry; - TLBEntry03 : TLBEntry; - TLBEntry02 : TLBEntry; - TLBEntry01 : TLBEntry; - TLBEntry00 : TLBEntry; - TLBXContext : XContextReg; - TLBEntryHi : TLBEntryHiReg; - TLBWired : mword 6; - TLBPageMask : mword 16; - TLBContext : ContextReg; - TLBEntryLo1 : TLBEntryLoReg; - TLBEntryLo0 : TLBEntryLoReg; - TLBRandom : mword 6; - TLBIndex : mword 6; - TLBProbe : mword 1; - nextPC : mword 64; - PC : mword 64; }. -Notation "{[ r 'with' 'UART_RVALID' := e ]}" := ({| UART_RVALID := e; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'UART_RDATA' := e ]}" := ({| UART_RDATA := e; UART_RVALID := UART_RVALID r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'UART_WRITTEN' := e ]}" := ({| UART_WRITTEN := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'UART_WDATA' := e ]}" := ({| UART_WDATA := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'GPR' := e ]}" := ({| GPR := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'LO' := e ]}" := ({| LO := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'HI' := e ]}" := ({| HI := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'delayedPC' := e ]}" := ({| delayedPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'inBranchDelay' := e ]}" := ({| inBranchDelay := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'branchPending' := e ]}" := ({| branchPending := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0Status' := e ]}" := ({| CP0Status := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0ConfigK0' := e ]}" := ({| CP0ConfigK0 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0UserLocal' := e ]}" := ({| CP0UserLocal := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0HWREna' := e ]}" := ({| CP0HWREna := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0Count' := e ]}" := ({| CP0Count := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0BadVAddr' := e ]}" := ({| CP0BadVAddr := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0LLAddr' := e ]}" := ({| CP0LLAddr := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0LLBit' := e ]}" := ({| CP0LLBit := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0ErrorEPC' := e ]}" := ({| CP0ErrorEPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0EPC' := e ]}" := ({| CP0EPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0Cause' := e ]}" := ({| CP0Cause := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0Compare' := e ]}" := ({| CP0Compare := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry63' := e ]}" := ({| TLBEntry63 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry62' := e ]}" := ({| TLBEntry62 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry61' := e ]}" := ({| TLBEntry61 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry60' := e ]}" := ({| TLBEntry60 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry59' := e ]}" := ({| TLBEntry59 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry58' := e ]}" := ({| TLBEntry58 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry57' := e ]}" := ({| TLBEntry57 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry56' := e ]}" := ({| TLBEntry56 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry55' := e ]}" := ({| TLBEntry55 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry54' := e ]}" := ({| TLBEntry54 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry53' := e ]}" := ({| TLBEntry53 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry52' := e ]}" := ({| TLBEntry52 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry51' := e ]}" := ({| TLBEntry51 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry50' := e ]}" := ({| TLBEntry50 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry49' := e ]}" := ({| TLBEntry49 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry48' := e ]}" := ({| TLBEntry48 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry47' := e ]}" := ({| TLBEntry47 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry46' := e ]}" := ({| TLBEntry46 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry45' := e ]}" := ({| TLBEntry45 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry44' := e ]}" := ({| TLBEntry44 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry43' := e ]}" := ({| TLBEntry43 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry42' := e ]}" := ({| TLBEntry42 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry41' := e ]}" := ({| TLBEntry41 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry40' := e ]}" := ({| TLBEntry40 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry39' := e ]}" := ({| TLBEntry39 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry38' := e ]}" := ({| TLBEntry38 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry37' := e ]}" := ({| TLBEntry37 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry36' := e ]}" := ({| TLBEntry36 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry35' := e ]}" := ({| TLBEntry35 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry34' := e ]}" := ({| TLBEntry34 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry33' := e ]}" := ({| TLBEntry33 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry32' := e ]}" := ({| TLBEntry32 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry31' := e ]}" := ({| TLBEntry31 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry30' := e ]}" := ({| TLBEntry30 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry29' := e ]}" := ({| TLBEntry29 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry28' := e ]}" := ({| TLBEntry28 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry27' := e ]}" := ({| TLBEntry27 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry26' := e ]}" := ({| TLBEntry26 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry25' := e ]}" := ({| TLBEntry25 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry24' := e ]}" := ({| TLBEntry24 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry23' := e ]}" := ({| TLBEntry23 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry22' := e ]}" := ({| TLBEntry22 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry21' := e ]}" := ({| TLBEntry21 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry20' := e ]}" := ({| TLBEntry20 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry19' := e ]}" := ({| TLBEntry19 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry18' := e ]}" := ({| TLBEntry18 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry17' := e ]}" := ({| TLBEntry17 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry16' := e ]}" := ({| TLBEntry16 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry15' := e ]}" := ({| TLBEntry15 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry14' := e ]}" := ({| TLBEntry14 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry13' := e ]}" := ({| TLBEntry13 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry12' := e ]}" := ({| TLBEntry12 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry11' := e ]}" := ({| TLBEntry11 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry10' := e ]}" := ({| TLBEntry10 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry09' := e ]}" := ({| TLBEntry09 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry08' := e ]}" := ({| TLBEntry08 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry07' := e ]}" := ({| TLBEntry07 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry06' := e ]}" := ({| TLBEntry06 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry05' := e ]}" := ({| TLBEntry05 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry04' := e ]}" := ({| TLBEntry04 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry03' := e ]}" := ({| TLBEntry03 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry02' := e ]}" := ({| TLBEntry02 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry01' := e ]}" := ({| TLBEntry01 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry00' := e ]}" := ({| TLBEntry00 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBXContext' := e ]}" := ({| TLBXContext := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntryHi' := e ]}" := ({| TLBEntryHi := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBWired' := e ]}" := ({| TLBWired := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBPageMask' := e ]}" := ({| TLBPageMask := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBContext' := e ]}" := ({| TLBContext := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntryLo1' := e ]}" := ({| TLBEntryLo1 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntryLo0' := e ]}" := ({| TLBEntryLo0 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBRandom' := e ]}" := ({| TLBRandom := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBIndex' := e ]}" := ({| TLBIndex := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBProbe' := e ]}" := ({| TLBProbe := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'nextPC' := e ]}" := ({| nextPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; PC := PC r |}). -Notation "{[ r 'with' 'PC' := e ]}" := ({| PC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r |}). - - - -Definition CauseReg_of_regval (merge_var : register_value) -: option CauseReg := - match merge_var with | Regval_CauseReg (v) => Some v | g__13 => None end. - -Definition regval_of_CauseReg (v : CauseReg) : register_value := Regval_CauseReg v. - -Definition ContextReg_of_regval (merge_var : register_value) -: option ContextReg := - match merge_var with | Regval_ContextReg (v) => Some v | g__12 => None end. - -Definition regval_of_ContextReg (v : ContextReg) : register_value := Regval_ContextReg v. - -Definition StatusReg_of_regval (merge_var : register_value) -: option StatusReg := - match merge_var with | Regval_StatusReg (v) => Some v | g__11 => None end. - -Definition regval_of_StatusReg (v : StatusReg) : register_value := Regval_StatusReg v. - -Definition TLBEntry_of_regval (merge_var : register_value) -: option TLBEntry := - match merge_var with | Regval_TLBEntry (v) => Some v | g__10 => None end. - -Definition regval_of_TLBEntry (v : TLBEntry) : register_value := Regval_TLBEntry v. - -Definition TLBEntryHiReg_of_regval (merge_var : register_value) -: option TLBEntryHiReg := - match merge_var with | Regval_TLBEntryHiReg (v) => Some v | g__9 => None end. - -Definition regval_of_TLBEntryHiReg (v : TLBEntryHiReg) : register_value := Regval_TLBEntryHiReg v. - -Definition TLBEntryLoReg_of_regval (merge_var : register_value) -: option TLBEntryLoReg := - match merge_var with | Regval_TLBEntryLoReg (v) => Some v | g__8 => None end. - -Definition regval_of_TLBEntryLoReg (v : TLBEntryLoReg) : register_value := Regval_TLBEntryLoReg v. - -Definition XContextReg_of_regval (merge_var : register_value) -: option XContextReg := - match merge_var with | Regval_XContextReg (v) => Some v | g__7 => None end. - -Definition regval_of_XContextReg (v : XContextReg) : register_value := Regval_XContextReg v. - -Definition vector_16_dec_bit_of_regval (merge_var : register_value) -: option (mword 16) := - match merge_var with | Regval_vector_16_dec_bit (v) => Some v | g__6 => None end. - -Definition regval_of_vector_16_dec_bit (v : mword 16) -: register_value := - Regval_vector_16_dec_bit v. - -Definition vector_1_dec_bit_of_regval (merge_var : register_value) -: option (mword 1) := - match merge_var with | Regval_vector_1_dec_bit (v) => Some v | g__5 => None end. - -Definition regval_of_vector_1_dec_bit (v : mword 1) : register_value := Regval_vector_1_dec_bit v. - -Definition vector_32_dec_bit_of_regval (merge_var : register_value) -: option (mword 32) := - match merge_var with | Regval_vector_32_dec_bit (v) => Some v | g__4 => None end. - -Definition regval_of_vector_32_dec_bit (v : mword 32) -: register_value := - Regval_vector_32_dec_bit v. - -Definition vector_3_dec_bit_of_regval (merge_var : register_value) -: option (mword 3) := - match merge_var with | Regval_vector_3_dec_bit (v) => Some v | g__3 => None end. - -Definition regval_of_vector_3_dec_bit (v : mword 3) : register_value := Regval_vector_3_dec_bit v. - -Definition vector_64_dec_bit_of_regval (merge_var : register_value) -: option (mword 64) := - match merge_var with | Regval_vector_64_dec_bit (v) => Some v | g__2 => None end. - -Definition regval_of_vector_64_dec_bit (v : mword 64) -: register_value := - Regval_vector_64_dec_bit v. - -Definition vector_6_dec_bit_of_regval (merge_var : register_value) -: option (mword 6) := - match merge_var with | Regval_vector_6_dec_bit (v) => Some v | g__1 => None end. - -Definition regval_of_vector_6_dec_bit (v : mword 6) : register_value := Regval_vector_6_dec_bit v. - -Definition vector_8_dec_bit_of_regval (merge_var : register_value) -: option (mword 8) := - match merge_var with | Regval_vector_8_dec_bit (v) => Some v | g__0 => None end. - -Definition regval_of_vector_8_dec_bit (v : mword 8) : register_value := Regval_vector_8_dec_bit v. - - - -Definition vector_of_regval {a} n (of_regval : register_value -> option a) (rv : register_value) : option (vec a n) := match rv with - | Regval_vector (n', _, v) => if n =? n' then map_bind (vec_of_list n) (just_list (List.map of_regval v)) else None - | _ => None -end. - -Definition regval_of_vector {a} (regval_of : a -> register_value) (size : Z) (is_inc : bool) (xs : vec a size) : register_value := Regval_vector (size, is_inc, List.map regval_of (list_of_vec xs)). - -Definition list_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (list a) := match rv with - | Regval_list v => just_list (List.map of_regval v) - | _ => None -end. - -Definition regval_of_list {a} (regval_of : a -> register_value) (xs : list a) : register_value := Regval_list (List.map regval_of xs). - -Definition option_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (option a) := match rv with - | Regval_option v => option_map of_regval v - | _ => None -end. - -Definition regval_of_option {a} (regval_of : a -> register_value) (v : option a) := Regval_option (option_map regval_of v). - - -Definition UART_RVALID_ref := {| - name := "UART_RVALID"; - read_from := (fun s => s.(UART_RVALID)); - write_to := (fun v s => ({[ s with UART_RVALID := v ]})); - of_regval := (fun v => vector_1_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. - -Definition UART_RDATA_ref := {| - name := "UART_RDATA"; - read_from := (fun s => s.(UART_RDATA)); - write_to := (fun v s => ({[ s with UART_RDATA := v ]})); - of_regval := (fun v => vector_8_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_8_dec_bit v) |}. - -Definition UART_WRITTEN_ref := {| - name := "UART_WRITTEN"; - read_from := (fun s => s.(UART_WRITTEN)); - write_to := (fun v s => ({[ s with UART_WRITTEN := v ]})); - of_regval := (fun v => vector_1_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. - -Definition UART_WDATA_ref := {| - name := "UART_WDATA"; - read_from := (fun s => s.(UART_WDATA)); - write_to := (fun v s => ({[ s with UART_WDATA := v ]})); - of_regval := (fun v => vector_8_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_8_dec_bit v) |}. - -Definition GPR_ref := {| - name := "GPR"; - read_from := (fun s => s.(GPR)); - write_to := (fun v s => ({[ s with GPR := v ]})); - of_regval := (fun v => vector_of_regval 32 (fun v => vector_64_dec_bit_of_regval v) v); - regval_of := (fun v => regval_of_vector (fun v => regval_of_vector_64_dec_bit v) 32 false v) |}. - -Definition LO_ref := {| - name := "LO"; - read_from := (fun s => s.(LO)); - write_to := (fun v s => ({[ s with LO := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition HI_ref := {| - name := "HI"; - read_from := (fun s => s.(HI)); - write_to := (fun v s => ({[ s with HI := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition delayedPC_ref := {| - name := "delayedPC"; - read_from := (fun s => s.(delayedPC)); - write_to := (fun v s => ({[ s with delayedPC := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition inBranchDelay_ref := {| - name := "inBranchDelay"; - read_from := (fun s => s.(inBranchDelay)); - write_to := (fun v s => ({[ s with inBranchDelay := v ]})); - of_regval := (fun v => vector_1_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. - -Definition branchPending_ref := {| - name := "branchPending"; - read_from := (fun s => s.(branchPending)); - write_to := (fun v s => ({[ s with branchPending := v ]})); - of_regval := (fun v => vector_1_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. - -Definition CP0Status_ref := {| - name := "CP0Status"; - read_from := (fun s => s.(CP0Status)); - write_to := (fun v s => ({[ s with CP0Status := v ]})); - of_regval := (fun v => StatusReg_of_regval v); - regval_of := (fun v => regval_of_StatusReg v) |}. - -Definition CP0ConfigK0_ref := {| - name := "CP0ConfigK0"; - read_from := (fun s => s.(CP0ConfigK0)); - write_to := (fun v s => ({[ s with CP0ConfigK0 := v ]})); - of_regval := (fun v => vector_3_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_3_dec_bit v) |}. - -Definition CP0UserLocal_ref := {| - name := "CP0UserLocal"; - read_from := (fun s => s.(CP0UserLocal)); - write_to := (fun v s => ({[ s with CP0UserLocal := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition CP0HWREna_ref := {| - name := "CP0HWREna"; - read_from := (fun s => s.(CP0HWREna)); - write_to := (fun v s => ({[ s with CP0HWREna := v ]})); - of_regval := (fun v => vector_32_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. - -Definition CP0Count_ref := {| - name := "CP0Count"; - read_from := (fun s => s.(CP0Count)); - write_to := (fun v s => ({[ s with CP0Count := v ]})); - of_regval := (fun v => vector_32_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. - -Definition CP0BadVAddr_ref := {| - name := "CP0BadVAddr"; - read_from := (fun s => s.(CP0BadVAddr)); - write_to := (fun v s => ({[ s with CP0BadVAddr := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition CP0LLAddr_ref := {| - name := "CP0LLAddr"; - read_from := (fun s => s.(CP0LLAddr)); - write_to := (fun v s => ({[ s with CP0LLAddr := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition CP0LLBit_ref := {| - name := "CP0LLBit"; - read_from := (fun s => s.(CP0LLBit)); - write_to := (fun v s => ({[ s with CP0LLBit := v ]})); - of_regval := (fun v => vector_1_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. - -Definition CP0ErrorEPC_ref := {| - name := "CP0ErrorEPC"; - read_from := (fun s => s.(CP0ErrorEPC)); - write_to := (fun v s => ({[ s with CP0ErrorEPC := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition CP0EPC_ref := {| - name := "CP0EPC"; - read_from := (fun s => s.(CP0EPC)); - write_to := (fun v s => ({[ s with CP0EPC := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition CP0Cause_ref := {| - name := "CP0Cause"; - read_from := (fun s => s.(CP0Cause)); - write_to := (fun v s => ({[ s with CP0Cause := v ]})); - of_regval := (fun v => CauseReg_of_regval v); - regval_of := (fun v => regval_of_CauseReg v) |}. - -Definition CP0Compare_ref := {| - name := "CP0Compare"; - read_from := (fun s => s.(CP0Compare)); - write_to := (fun v s => ({[ s with CP0Compare := v ]})); - of_regval := (fun v => vector_32_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. - -Definition TLBEntry63_ref := {| - name := "TLBEntry63"; - read_from := (fun s => s.(TLBEntry63)); - write_to := (fun v s => ({[ s with TLBEntry63 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry62_ref := {| - name := "TLBEntry62"; - read_from := (fun s => s.(TLBEntry62)); - write_to := (fun v s => ({[ s with TLBEntry62 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry61_ref := {| - name := "TLBEntry61"; - read_from := (fun s => s.(TLBEntry61)); - write_to := (fun v s => ({[ s with TLBEntry61 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry60_ref := {| - name := "TLBEntry60"; - read_from := (fun s => s.(TLBEntry60)); - write_to := (fun v s => ({[ s with TLBEntry60 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry59_ref := {| - name := "TLBEntry59"; - read_from := (fun s => s.(TLBEntry59)); - write_to := (fun v s => ({[ s with TLBEntry59 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry58_ref := {| - name := "TLBEntry58"; - read_from := (fun s => s.(TLBEntry58)); - write_to := (fun v s => ({[ s with TLBEntry58 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry57_ref := {| - name := "TLBEntry57"; - read_from := (fun s => s.(TLBEntry57)); - write_to := (fun v s => ({[ s with TLBEntry57 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry56_ref := {| - name := "TLBEntry56"; - read_from := (fun s => s.(TLBEntry56)); - write_to := (fun v s => ({[ s with TLBEntry56 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry55_ref := {| - name := "TLBEntry55"; - read_from := (fun s => s.(TLBEntry55)); - write_to := (fun v s => ({[ s with TLBEntry55 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry54_ref := {| - name := "TLBEntry54"; - read_from := (fun s => s.(TLBEntry54)); - write_to := (fun v s => ({[ s with TLBEntry54 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry53_ref := {| - name := "TLBEntry53"; - read_from := (fun s => s.(TLBEntry53)); - write_to := (fun v s => ({[ s with TLBEntry53 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry52_ref := {| - name := "TLBEntry52"; - read_from := (fun s => s.(TLBEntry52)); - write_to := (fun v s => ({[ s with TLBEntry52 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry51_ref := {| - name := "TLBEntry51"; - read_from := (fun s => s.(TLBEntry51)); - write_to := (fun v s => ({[ s with TLBEntry51 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry50_ref := {| - name := "TLBEntry50"; - read_from := (fun s => s.(TLBEntry50)); - write_to := (fun v s => ({[ s with TLBEntry50 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry49_ref := {| - name := "TLBEntry49"; - read_from := (fun s => s.(TLBEntry49)); - write_to := (fun v s => ({[ s with TLBEntry49 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry48_ref := {| - name := "TLBEntry48"; - read_from := (fun s => s.(TLBEntry48)); - write_to := (fun v s => ({[ s with TLBEntry48 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry47_ref := {| - name := "TLBEntry47"; - read_from := (fun s => s.(TLBEntry47)); - write_to := (fun v s => ({[ s with TLBEntry47 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry46_ref := {| - name := "TLBEntry46"; - read_from := (fun s => s.(TLBEntry46)); - write_to := (fun v s => ({[ s with TLBEntry46 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry45_ref := {| - name := "TLBEntry45"; - read_from := (fun s => s.(TLBEntry45)); - write_to := (fun v s => ({[ s with TLBEntry45 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry44_ref := {| - name := "TLBEntry44"; - read_from := (fun s => s.(TLBEntry44)); - write_to := (fun v s => ({[ s with TLBEntry44 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry43_ref := {| - name := "TLBEntry43"; - read_from := (fun s => s.(TLBEntry43)); - write_to := (fun v s => ({[ s with TLBEntry43 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry42_ref := {| - name := "TLBEntry42"; - read_from := (fun s => s.(TLBEntry42)); - write_to := (fun v s => ({[ s with TLBEntry42 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry41_ref := {| - name := "TLBEntry41"; - read_from := (fun s => s.(TLBEntry41)); - write_to := (fun v s => ({[ s with TLBEntry41 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry40_ref := {| - name := "TLBEntry40"; - read_from := (fun s => s.(TLBEntry40)); - write_to := (fun v s => ({[ s with TLBEntry40 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry39_ref := {| - name := "TLBEntry39"; - read_from := (fun s => s.(TLBEntry39)); - write_to := (fun v s => ({[ s with TLBEntry39 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry38_ref := {| - name := "TLBEntry38"; - read_from := (fun s => s.(TLBEntry38)); - write_to := (fun v s => ({[ s with TLBEntry38 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry37_ref := {| - name := "TLBEntry37"; - read_from := (fun s => s.(TLBEntry37)); - write_to := (fun v s => ({[ s with TLBEntry37 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry36_ref := {| - name := "TLBEntry36"; - read_from := (fun s => s.(TLBEntry36)); - write_to := (fun v s => ({[ s with TLBEntry36 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry35_ref := {| - name := "TLBEntry35"; - read_from := (fun s => s.(TLBEntry35)); - write_to := (fun v s => ({[ s with TLBEntry35 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry34_ref := {| - name := "TLBEntry34"; - read_from := (fun s => s.(TLBEntry34)); - write_to := (fun v s => ({[ s with TLBEntry34 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry33_ref := {| - name := "TLBEntry33"; - read_from := (fun s => s.(TLBEntry33)); - write_to := (fun v s => ({[ s with TLBEntry33 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry32_ref := {| - name := "TLBEntry32"; - read_from := (fun s => s.(TLBEntry32)); - write_to := (fun v s => ({[ s with TLBEntry32 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry31_ref := {| - name := "TLBEntry31"; - read_from := (fun s => s.(TLBEntry31)); - write_to := (fun v s => ({[ s with TLBEntry31 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry30_ref := {| - name := "TLBEntry30"; - read_from := (fun s => s.(TLBEntry30)); - write_to := (fun v s => ({[ s with TLBEntry30 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry29_ref := {| - name := "TLBEntry29"; - read_from := (fun s => s.(TLBEntry29)); - write_to := (fun v s => ({[ s with TLBEntry29 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry28_ref := {| - name := "TLBEntry28"; - read_from := (fun s => s.(TLBEntry28)); - write_to := (fun v s => ({[ s with TLBEntry28 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry27_ref := {| - name := "TLBEntry27"; - read_from := (fun s => s.(TLBEntry27)); - write_to := (fun v s => ({[ s with TLBEntry27 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry26_ref := {| - name := "TLBEntry26"; - read_from := (fun s => s.(TLBEntry26)); - write_to := (fun v s => ({[ s with TLBEntry26 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry25_ref := {| - name := "TLBEntry25"; - read_from := (fun s => s.(TLBEntry25)); - write_to := (fun v s => ({[ s with TLBEntry25 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry24_ref := {| - name := "TLBEntry24"; - read_from := (fun s => s.(TLBEntry24)); - write_to := (fun v s => ({[ s with TLBEntry24 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry23_ref := {| - name := "TLBEntry23"; - read_from := (fun s => s.(TLBEntry23)); - write_to := (fun v s => ({[ s with TLBEntry23 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry22_ref := {| - name := "TLBEntry22"; - read_from := (fun s => s.(TLBEntry22)); - write_to := (fun v s => ({[ s with TLBEntry22 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry21_ref := {| - name := "TLBEntry21"; - read_from := (fun s => s.(TLBEntry21)); - write_to := (fun v s => ({[ s with TLBEntry21 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry20_ref := {| - name := "TLBEntry20"; - read_from := (fun s => s.(TLBEntry20)); - write_to := (fun v s => ({[ s with TLBEntry20 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry19_ref := {| - name := "TLBEntry19"; - read_from := (fun s => s.(TLBEntry19)); - write_to := (fun v s => ({[ s with TLBEntry19 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry18_ref := {| - name := "TLBEntry18"; - read_from := (fun s => s.(TLBEntry18)); - write_to := (fun v s => ({[ s with TLBEntry18 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry17_ref := {| - name := "TLBEntry17"; - read_from := (fun s => s.(TLBEntry17)); - write_to := (fun v s => ({[ s with TLBEntry17 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry16_ref := {| - name := "TLBEntry16"; - read_from := (fun s => s.(TLBEntry16)); - write_to := (fun v s => ({[ s with TLBEntry16 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry15_ref := {| - name := "TLBEntry15"; - read_from := (fun s => s.(TLBEntry15)); - write_to := (fun v s => ({[ s with TLBEntry15 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry14_ref := {| - name := "TLBEntry14"; - read_from := (fun s => s.(TLBEntry14)); - write_to := (fun v s => ({[ s with TLBEntry14 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry13_ref := {| - name := "TLBEntry13"; - read_from := (fun s => s.(TLBEntry13)); - write_to := (fun v s => ({[ s with TLBEntry13 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry12_ref := {| - name := "TLBEntry12"; - read_from := (fun s => s.(TLBEntry12)); - write_to := (fun v s => ({[ s with TLBEntry12 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry11_ref := {| - name := "TLBEntry11"; - read_from := (fun s => s.(TLBEntry11)); - write_to := (fun v s => ({[ s with TLBEntry11 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry10_ref := {| - name := "TLBEntry10"; - read_from := (fun s => s.(TLBEntry10)); - write_to := (fun v s => ({[ s with TLBEntry10 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry09_ref := {| - name := "TLBEntry09"; - read_from := (fun s => s.(TLBEntry09)); - write_to := (fun v s => ({[ s with TLBEntry09 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry08_ref := {| - name := "TLBEntry08"; - read_from := (fun s => s.(TLBEntry08)); - write_to := (fun v s => ({[ s with TLBEntry08 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry07_ref := {| - name := "TLBEntry07"; - read_from := (fun s => s.(TLBEntry07)); - write_to := (fun v s => ({[ s with TLBEntry07 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry06_ref := {| - name := "TLBEntry06"; - read_from := (fun s => s.(TLBEntry06)); - write_to := (fun v s => ({[ s with TLBEntry06 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry05_ref := {| - name := "TLBEntry05"; - read_from := (fun s => s.(TLBEntry05)); - write_to := (fun v s => ({[ s with TLBEntry05 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry04_ref := {| - name := "TLBEntry04"; - read_from := (fun s => s.(TLBEntry04)); - write_to := (fun v s => ({[ s with TLBEntry04 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry03_ref := {| - name := "TLBEntry03"; - read_from := (fun s => s.(TLBEntry03)); - write_to := (fun v s => ({[ s with TLBEntry03 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry02_ref := {| - name := "TLBEntry02"; - read_from := (fun s => s.(TLBEntry02)); - write_to := (fun v s => ({[ s with TLBEntry02 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry01_ref := {| - name := "TLBEntry01"; - read_from := (fun s => s.(TLBEntry01)); - write_to := (fun v s => ({[ s with TLBEntry01 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry00_ref := {| - name := "TLBEntry00"; - read_from := (fun s => s.(TLBEntry00)); - write_to := (fun v s => ({[ s with TLBEntry00 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBXContext_ref := {| - name := "TLBXContext"; - read_from := (fun s => s.(TLBXContext)); - write_to := (fun v s => ({[ s with TLBXContext := v ]})); - of_regval := (fun v => XContextReg_of_regval v); - regval_of := (fun v => regval_of_XContextReg v) |}. - -Definition TLBEntryHi_ref := {| - name := "TLBEntryHi"; - read_from := (fun s => s.(TLBEntryHi)); - write_to := (fun v s => ({[ s with TLBEntryHi := v ]})); - of_regval := (fun v => TLBEntryHiReg_of_regval v); - regval_of := (fun v => regval_of_TLBEntryHiReg v) |}. - -Definition TLBWired_ref := {| - name := "TLBWired"; - read_from := (fun s => s.(TLBWired)); - write_to := (fun v s => ({[ s with TLBWired := v ]})); - of_regval := (fun v => vector_6_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_6_dec_bit v) |}. - -Definition TLBPageMask_ref := {| - name := "TLBPageMask"; - read_from := (fun s => s.(TLBPageMask)); - write_to := (fun v s => ({[ s with TLBPageMask := v ]})); - of_regval := (fun v => vector_16_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_16_dec_bit v) |}. - -Definition TLBContext_ref := {| - name := "TLBContext"; - read_from := (fun s => s.(TLBContext)); - write_to := (fun v s => ({[ s with TLBContext := v ]})); - of_regval := (fun v => ContextReg_of_regval v); - regval_of := (fun v => regval_of_ContextReg v) |}. - -Definition TLBEntryLo1_ref := {| - name := "TLBEntryLo1"; - read_from := (fun s => s.(TLBEntryLo1)); - write_to := (fun v s => ({[ s with TLBEntryLo1 := v ]})); - of_regval := (fun v => TLBEntryLoReg_of_regval v); - regval_of := (fun v => regval_of_TLBEntryLoReg v) |}. - -Definition TLBEntryLo0_ref := {| - name := "TLBEntryLo0"; - read_from := (fun s => s.(TLBEntryLo0)); - write_to := (fun v s => ({[ s with TLBEntryLo0 := v ]})); - of_regval := (fun v => TLBEntryLoReg_of_regval v); - regval_of := (fun v => regval_of_TLBEntryLoReg v) |}. - -Definition TLBRandom_ref := {| - name := "TLBRandom"; - read_from := (fun s => s.(TLBRandom)); - write_to := (fun v s => ({[ s with TLBRandom := v ]})); - of_regval := (fun v => vector_6_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_6_dec_bit v) |}. - -Definition TLBIndex_ref := {| - name := "TLBIndex"; - read_from := (fun s => s.(TLBIndex)); - write_to := (fun v s => ({[ s with TLBIndex := v ]})); - of_regval := (fun v => vector_6_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_6_dec_bit v) |}. - -Definition TLBProbe_ref := {| - name := "TLBProbe"; - read_from := (fun s => s.(TLBProbe)); - write_to := (fun v s => ({[ s with TLBProbe := v ]})); - of_regval := (fun v => vector_1_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. - -Definition nextPC_ref := {| - name := "nextPC"; - read_from := (fun s => s.(nextPC)); - write_to := (fun v s => ({[ s with nextPC := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition PC_ref := {| - name := "PC"; - read_from := (fun s => s.(PC)); - write_to := (fun v s => ({[ s with PC := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Local Open Scope string. -Definition get_regval (reg_name : string) (s : regstate) : option register_value := - if string_dec reg_name "UART_RVALID" then Some (UART_RVALID_ref.(regval_of) (UART_RVALID_ref.(read_from) s)) else - if string_dec reg_name "UART_RDATA" then Some (UART_RDATA_ref.(regval_of) (UART_RDATA_ref.(read_from) s)) else - if string_dec reg_name "UART_WRITTEN" then Some (UART_WRITTEN_ref.(regval_of) (UART_WRITTEN_ref.(read_from) s)) else - if string_dec reg_name "UART_WDATA" then Some (UART_WDATA_ref.(regval_of) (UART_WDATA_ref.(read_from) s)) else - if string_dec reg_name "GPR" then Some (GPR_ref.(regval_of) (GPR_ref.(read_from) s)) else - if string_dec reg_name "LO" then Some (LO_ref.(regval_of) (LO_ref.(read_from) s)) else - if string_dec reg_name "HI" then Some (HI_ref.(regval_of) (HI_ref.(read_from) s)) else - if string_dec reg_name "delayedPC" then Some (delayedPC_ref.(regval_of) (delayedPC_ref.(read_from) s)) else - if string_dec reg_name "inBranchDelay" then Some (inBranchDelay_ref.(regval_of) (inBranchDelay_ref.(read_from) s)) else - if string_dec reg_name "branchPending" then Some (branchPending_ref.(regval_of) (branchPending_ref.(read_from) s)) else - if string_dec reg_name "CP0Status" then Some (CP0Status_ref.(regval_of) (CP0Status_ref.(read_from) s)) else - if string_dec reg_name "CP0ConfigK0" then Some (CP0ConfigK0_ref.(regval_of) (CP0ConfigK0_ref.(read_from) s)) else - if string_dec reg_name "CP0UserLocal" then Some (CP0UserLocal_ref.(regval_of) (CP0UserLocal_ref.(read_from) s)) else - if string_dec reg_name "CP0HWREna" then Some (CP0HWREna_ref.(regval_of) (CP0HWREna_ref.(read_from) s)) else - if string_dec reg_name "CP0Count" then Some (CP0Count_ref.(regval_of) (CP0Count_ref.(read_from) s)) else - if string_dec reg_name "CP0BadVAddr" then Some (CP0BadVAddr_ref.(regval_of) (CP0BadVAddr_ref.(read_from) s)) else - if string_dec reg_name "CP0LLAddr" then Some (CP0LLAddr_ref.(regval_of) (CP0LLAddr_ref.(read_from) s)) else - if string_dec reg_name "CP0LLBit" then Some (CP0LLBit_ref.(regval_of) (CP0LLBit_ref.(read_from) s)) else - if string_dec reg_name "CP0ErrorEPC" then Some (CP0ErrorEPC_ref.(regval_of) (CP0ErrorEPC_ref.(read_from) s)) else - if string_dec reg_name "CP0EPC" then Some (CP0EPC_ref.(regval_of) (CP0EPC_ref.(read_from) s)) else - if string_dec reg_name "CP0Cause" then Some (CP0Cause_ref.(regval_of) (CP0Cause_ref.(read_from) s)) else - if string_dec reg_name "CP0Compare" then Some (CP0Compare_ref.(regval_of) (CP0Compare_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry63" then Some (TLBEntry63_ref.(regval_of) (TLBEntry63_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry62" then Some (TLBEntry62_ref.(regval_of) (TLBEntry62_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry61" then Some (TLBEntry61_ref.(regval_of) (TLBEntry61_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry60" then Some (TLBEntry60_ref.(regval_of) (TLBEntry60_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry59" then Some (TLBEntry59_ref.(regval_of) (TLBEntry59_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry58" then Some (TLBEntry58_ref.(regval_of) (TLBEntry58_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry57" then Some (TLBEntry57_ref.(regval_of) (TLBEntry57_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry56" then Some (TLBEntry56_ref.(regval_of) (TLBEntry56_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry55" then Some (TLBEntry55_ref.(regval_of) (TLBEntry55_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry54" then Some (TLBEntry54_ref.(regval_of) (TLBEntry54_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry53" then Some (TLBEntry53_ref.(regval_of) (TLBEntry53_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry52" then Some (TLBEntry52_ref.(regval_of) (TLBEntry52_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry51" then Some (TLBEntry51_ref.(regval_of) (TLBEntry51_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry50" then Some (TLBEntry50_ref.(regval_of) (TLBEntry50_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry49" then Some (TLBEntry49_ref.(regval_of) (TLBEntry49_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry48" then Some (TLBEntry48_ref.(regval_of) (TLBEntry48_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry47" then Some (TLBEntry47_ref.(regval_of) (TLBEntry47_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry46" then Some (TLBEntry46_ref.(regval_of) (TLBEntry46_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry45" then Some (TLBEntry45_ref.(regval_of) (TLBEntry45_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry44" then Some (TLBEntry44_ref.(regval_of) (TLBEntry44_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry43" then Some (TLBEntry43_ref.(regval_of) (TLBEntry43_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry42" then Some (TLBEntry42_ref.(regval_of) (TLBEntry42_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry41" then Some (TLBEntry41_ref.(regval_of) (TLBEntry41_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry40" then Some (TLBEntry40_ref.(regval_of) (TLBEntry40_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry39" then Some (TLBEntry39_ref.(regval_of) (TLBEntry39_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry38" then Some (TLBEntry38_ref.(regval_of) (TLBEntry38_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry37" then Some (TLBEntry37_ref.(regval_of) (TLBEntry37_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry36" then Some (TLBEntry36_ref.(regval_of) (TLBEntry36_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry35" then Some (TLBEntry35_ref.(regval_of) (TLBEntry35_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry34" then Some (TLBEntry34_ref.(regval_of) (TLBEntry34_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry33" then Some (TLBEntry33_ref.(regval_of) (TLBEntry33_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry32" then Some (TLBEntry32_ref.(regval_of) (TLBEntry32_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry31" then Some (TLBEntry31_ref.(regval_of) (TLBEntry31_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry30" then Some (TLBEntry30_ref.(regval_of) (TLBEntry30_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry29" then Some (TLBEntry29_ref.(regval_of) (TLBEntry29_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry28" then Some (TLBEntry28_ref.(regval_of) (TLBEntry28_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry27" then Some (TLBEntry27_ref.(regval_of) (TLBEntry27_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry26" then Some (TLBEntry26_ref.(regval_of) (TLBEntry26_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry25" then Some (TLBEntry25_ref.(regval_of) (TLBEntry25_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry24" then Some (TLBEntry24_ref.(regval_of) (TLBEntry24_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry23" then Some (TLBEntry23_ref.(regval_of) (TLBEntry23_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry22" then Some (TLBEntry22_ref.(regval_of) (TLBEntry22_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry21" then Some (TLBEntry21_ref.(regval_of) (TLBEntry21_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry20" then Some (TLBEntry20_ref.(regval_of) (TLBEntry20_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry19" then Some (TLBEntry19_ref.(regval_of) (TLBEntry19_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry18" then Some (TLBEntry18_ref.(regval_of) (TLBEntry18_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry17" then Some (TLBEntry17_ref.(regval_of) (TLBEntry17_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry16" then Some (TLBEntry16_ref.(regval_of) (TLBEntry16_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry15" then Some (TLBEntry15_ref.(regval_of) (TLBEntry15_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry14" then Some (TLBEntry14_ref.(regval_of) (TLBEntry14_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry13" then Some (TLBEntry13_ref.(regval_of) (TLBEntry13_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry12" then Some (TLBEntry12_ref.(regval_of) (TLBEntry12_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry11" then Some (TLBEntry11_ref.(regval_of) (TLBEntry11_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry10" then Some (TLBEntry10_ref.(regval_of) (TLBEntry10_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry09" then Some (TLBEntry09_ref.(regval_of) (TLBEntry09_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry08" then Some (TLBEntry08_ref.(regval_of) (TLBEntry08_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry07" then Some (TLBEntry07_ref.(regval_of) (TLBEntry07_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry06" then Some (TLBEntry06_ref.(regval_of) (TLBEntry06_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry05" then Some (TLBEntry05_ref.(regval_of) (TLBEntry05_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry04" then Some (TLBEntry04_ref.(regval_of) (TLBEntry04_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry03" then Some (TLBEntry03_ref.(regval_of) (TLBEntry03_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry02" then Some (TLBEntry02_ref.(regval_of) (TLBEntry02_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry01" then Some (TLBEntry01_ref.(regval_of) (TLBEntry01_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry00" then Some (TLBEntry00_ref.(regval_of) (TLBEntry00_ref.(read_from) s)) else - if string_dec reg_name "TLBXContext" then Some (TLBXContext_ref.(regval_of) (TLBXContext_ref.(read_from) s)) else - if string_dec reg_name "TLBEntryHi" then Some (TLBEntryHi_ref.(regval_of) (TLBEntryHi_ref.(read_from) s)) else - if string_dec reg_name "TLBWired" then Some (TLBWired_ref.(regval_of) (TLBWired_ref.(read_from) s)) else - if string_dec reg_name "TLBPageMask" then Some (TLBPageMask_ref.(regval_of) (TLBPageMask_ref.(read_from) s)) else - if string_dec reg_name "TLBContext" then Some (TLBContext_ref.(regval_of) (TLBContext_ref.(read_from) s)) else - if string_dec reg_name "TLBEntryLo1" then Some (TLBEntryLo1_ref.(regval_of) (TLBEntryLo1_ref.(read_from) s)) else - if string_dec reg_name "TLBEntryLo0" then Some (TLBEntryLo0_ref.(regval_of) (TLBEntryLo0_ref.(read_from) s)) else - if string_dec reg_name "TLBRandom" then Some (TLBRandom_ref.(regval_of) (TLBRandom_ref.(read_from) s)) else - if string_dec reg_name "TLBIndex" then Some (TLBIndex_ref.(regval_of) (TLBIndex_ref.(read_from) s)) else - if string_dec reg_name "TLBProbe" then Some (TLBProbe_ref.(regval_of) (TLBProbe_ref.(read_from) s)) else - if string_dec reg_name "nextPC" then Some (nextPC_ref.(regval_of) (nextPC_ref.(read_from) s)) else - if string_dec reg_name "PC" then Some (PC_ref.(regval_of) (PC_ref.(read_from) s)) else - None. - -Definition set_regval (reg_name : string) (v : register_value) (s : regstate) : option regstate := - if string_dec reg_name "UART_RVALID" then option_map (fun v => UART_RVALID_ref.(write_to) v s) (UART_RVALID_ref.(of_regval) v) else - if string_dec reg_name "UART_RDATA" then option_map (fun v => UART_RDATA_ref.(write_to) v s) (UART_RDATA_ref.(of_regval) v) else - if string_dec reg_name "UART_WRITTEN" then option_map (fun v => UART_WRITTEN_ref.(write_to) v s) (UART_WRITTEN_ref.(of_regval) v) else - if string_dec reg_name "UART_WDATA" then option_map (fun v => UART_WDATA_ref.(write_to) v s) (UART_WDATA_ref.(of_regval) v) else - if string_dec reg_name "GPR" then option_map (fun v => GPR_ref.(write_to) v s) (GPR_ref.(of_regval) v) else - if string_dec reg_name "LO" then option_map (fun v => LO_ref.(write_to) v s) (LO_ref.(of_regval) v) else - if string_dec reg_name "HI" then option_map (fun v => HI_ref.(write_to) v s) (HI_ref.(of_regval) v) else - if string_dec reg_name "delayedPC" then option_map (fun v => delayedPC_ref.(write_to) v s) (delayedPC_ref.(of_regval) v) else - if string_dec reg_name "inBranchDelay" then option_map (fun v => inBranchDelay_ref.(write_to) v s) (inBranchDelay_ref.(of_regval) v) else - if string_dec reg_name "branchPending" then option_map (fun v => branchPending_ref.(write_to) v s) (branchPending_ref.(of_regval) v) else - if string_dec reg_name "CP0Status" then option_map (fun v => CP0Status_ref.(write_to) v s) (CP0Status_ref.(of_regval) v) else - if string_dec reg_name "CP0ConfigK0" then option_map (fun v => CP0ConfigK0_ref.(write_to) v s) (CP0ConfigK0_ref.(of_regval) v) else - if string_dec reg_name "CP0UserLocal" then option_map (fun v => CP0UserLocal_ref.(write_to) v s) (CP0UserLocal_ref.(of_regval) v) else - if string_dec reg_name "CP0HWREna" then option_map (fun v => CP0HWREna_ref.(write_to) v s) (CP0HWREna_ref.(of_regval) v) else - if string_dec reg_name "CP0Count" then option_map (fun v => CP0Count_ref.(write_to) v s) (CP0Count_ref.(of_regval) v) else - if string_dec reg_name "CP0BadVAddr" then option_map (fun v => CP0BadVAddr_ref.(write_to) v s) (CP0BadVAddr_ref.(of_regval) v) else - if string_dec reg_name "CP0LLAddr" then option_map (fun v => CP0LLAddr_ref.(write_to) v s) (CP0LLAddr_ref.(of_regval) v) else - if string_dec reg_name "CP0LLBit" then option_map (fun v => CP0LLBit_ref.(write_to) v s) (CP0LLBit_ref.(of_regval) v) else - if string_dec reg_name "CP0ErrorEPC" then option_map (fun v => CP0ErrorEPC_ref.(write_to) v s) (CP0ErrorEPC_ref.(of_regval) v) else - if string_dec reg_name "CP0EPC" then option_map (fun v => CP0EPC_ref.(write_to) v s) (CP0EPC_ref.(of_regval) v) else - if string_dec reg_name "CP0Cause" then option_map (fun v => CP0Cause_ref.(write_to) v s) (CP0Cause_ref.(of_regval) v) else - if string_dec reg_name "CP0Compare" then option_map (fun v => CP0Compare_ref.(write_to) v s) (CP0Compare_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry63" then option_map (fun v => TLBEntry63_ref.(write_to) v s) (TLBEntry63_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry62" then option_map (fun v => TLBEntry62_ref.(write_to) v s) (TLBEntry62_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry61" then option_map (fun v => TLBEntry61_ref.(write_to) v s) (TLBEntry61_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry60" then option_map (fun v => TLBEntry60_ref.(write_to) v s) (TLBEntry60_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry59" then option_map (fun v => TLBEntry59_ref.(write_to) v s) (TLBEntry59_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry58" then option_map (fun v => TLBEntry58_ref.(write_to) v s) (TLBEntry58_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry57" then option_map (fun v => TLBEntry57_ref.(write_to) v s) (TLBEntry57_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry56" then option_map (fun v => TLBEntry56_ref.(write_to) v s) (TLBEntry56_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry55" then option_map (fun v => TLBEntry55_ref.(write_to) v s) (TLBEntry55_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry54" then option_map (fun v => TLBEntry54_ref.(write_to) v s) (TLBEntry54_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry53" then option_map (fun v => TLBEntry53_ref.(write_to) v s) (TLBEntry53_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry52" then option_map (fun v => TLBEntry52_ref.(write_to) v s) (TLBEntry52_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry51" then option_map (fun v => TLBEntry51_ref.(write_to) v s) (TLBEntry51_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry50" then option_map (fun v => TLBEntry50_ref.(write_to) v s) (TLBEntry50_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry49" then option_map (fun v => TLBEntry49_ref.(write_to) v s) (TLBEntry49_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry48" then option_map (fun v => TLBEntry48_ref.(write_to) v s) (TLBEntry48_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry47" then option_map (fun v => TLBEntry47_ref.(write_to) v s) (TLBEntry47_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry46" then option_map (fun v => TLBEntry46_ref.(write_to) v s) (TLBEntry46_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry45" then option_map (fun v => TLBEntry45_ref.(write_to) v s) (TLBEntry45_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry44" then option_map (fun v => TLBEntry44_ref.(write_to) v s) (TLBEntry44_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry43" then option_map (fun v => TLBEntry43_ref.(write_to) v s) (TLBEntry43_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry42" then option_map (fun v => TLBEntry42_ref.(write_to) v s) (TLBEntry42_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry41" then option_map (fun v => TLBEntry41_ref.(write_to) v s) (TLBEntry41_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry40" then option_map (fun v => TLBEntry40_ref.(write_to) v s) (TLBEntry40_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry39" then option_map (fun v => TLBEntry39_ref.(write_to) v s) (TLBEntry39_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry38" then option_map (fun v => TLBEntry38_ref.(write_to) v s) (TLBEntry38_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry37" then option_map (fun v => TLBEntry37_ref.(write_to) v s) (TLBEntry37_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry36" then option_map (fun v => TLBEntry36_ref.(write_to) v s) (TLBEntry36_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry35" then option_map (fun v => TLBEntry35_ref.(write_to) v s) (TLBEntry35_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry34" then option_map (fun v => TLBEntry34_ref.(write_to) v s) (TLBEntry34_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry33" then option_map (fun v => TLBEntry33_ref.(write_to) v s) (TLBEntry33_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry32" then option_map (fun v => TLBEntry32_ref.(write_to) v s) (TLBEntry32_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry31" then option_map (fun v => TLBEntry31_ref.(write_to) v s) (TLBEntry31_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry30" then option_map (fun v => TLBEntry30_ref.(write_to) v s) (TLBEntry30_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry29" then option_map (fun v => TLBEntry29_ref.(write_to) v s) (TLBEntry29_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry28" then option_map (fun v => TLBEntry28_ref.(write_to) v s) (TLBEntry28_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry27" then option_map (fun v => TLBEntry27_ref.(write_to) v s) (TLBEntry27_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry26" then option_map (fun v => TLBEntry26_ref.(write_to) v s) (TLBEntry26_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry25" then option_map (fun v => TLBEntry25_ref.(write_to) v s) (TLBEntry25_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry24" then option_map (fun v => TLBEntry24_ref.(write_to) v s) (TLBEntry24_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry23" then option_map (fun v => TLBEntry23_ref.(write_to) v s) (TLBEntry23_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry22" then option_map (fun v => TLBEntry22_ref.(write_to) v s) (TLBEntry22_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry21" then option_map (fun v => TLBEntry21_ref.(write_to) v s) (TLBEntry21_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry20" then option_map (fun v => TLBEntry20_ref.(write_to) v s) (TLBEntry20_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry19" then option_map (fun v => TLBEntry19_ref.(write_to) v s) (TLBEntry19_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry18" then option_map (fun v => TLBEntry18_ref.(write_to) v s) (TLBEntry18_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry17" then option_map (fun v => TLBEntry17_ref.(write_to) v s) (TLBEntry17_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry16" then option_map (fun v => TLBEntry16_ref.(write_to) v s) (TLBEntry16_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry15" then option_map (fun v => TLBEntry15_ref.(write_to) v s) (TLBEntry15_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry14" then option_map (fun v => TLBEntry14_ref.(write_to) v s) (TLBEntry14_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry13" then option_map (fun v => TLBEntry13_ref.(write_to) v s) (TLBEntry13_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry12" then option_map (fun v => TLBEntry12_ref.(write_to) v s) (TLBEntry12_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry11" then option_map (fun v => TLBEntry11_ref.(write_to) v s) (TLBEntry11_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry10" then option_map (fun v => TLBEntry10_ref.(write_to) v s) (TLBEntry10_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry09" then option_map (fun v => TLBEntry09_ref.(write_to) v s) (TLBEntry09_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry08" then option_map (fun v => TLBEntry08_ref.(write_to) v s) (TLBEntry08_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry07" then option_map (fun v => TLBEntry07_ref.(write_to) v s) (TLBEntry07_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry06" then option_map (fun v => TLBEntry06_ref.(write_to) v s) (TLBEntry06_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry05" then option_map (fun v => TLBEntry05_ref.(write_to) v s) (TLBEntry05_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry04" then option_map (fun v => TLBEntry04_ref.(write_to) v s) (TLBEntry04_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry03" then option_map (fun v => TLBEntry03_ref.(write_to) v s) (TLBEntry03_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry02" then option_map (fun v => TLBEntry02_ref.(write_to) v s) (TLBEntry02_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry01" then option_map (fun v => TLBEntry01_ref.(write_to) v s) (TLBEntry01_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry00" then option_map (fun v => TLBEntry00_ref.(write_to) v s) (TLBEntry00_ref.(of_regval) v) else - if string_dec reg_name "TLBXContext" then option_map (fun v => TLBXContext_ref.(write_to) v s) (TLBXContext_ref.(of_regval) v) else - if string_dec reg_name "TLBEntryHi" then option_map (fun v => TLBEntryHi_ref.(write_to) v s) (TLBEntryHi_ref.(of_regval) v) else - if string_dec reg_name "TLBWired" then option_map (fun v => TLBWired_ref.(write_to) v s) (TLBWired_ref.(of_regval) v) else - if string_dec reg_name "TLBPageMask" then option_map (fun v => TLBPageMask_ref.(write_to) v s) (TLBPageMask_ref.(of_regval) v) else - if string_dec reg_name "TLBContext" then option_map (fun v => TLBContext_ref.(write_to) v s) (TLBContext_ref.(of_regval) v) else - if string_dec reg_name "TLBEntryLo1" then option_map (fun v => TLBEntryLo1_ref.(write_to) v s) (TLBEntryLo1_ref.(of_regval) v) else - if string_dec reg_name "TLBEntryLo0" then option_map (fun v => TLBEntryLo0_ref.(write_to) v s) (TLBEntryLo0_ref.(of_regval) v) else - if string_dec reg_name "TLBRandom" then option_map (fun v => TLBRandom_ref.(write_to) v s) (TLBRandom_ref.(of_regval) v) else - if string_dec reg_name "TLBIndex" then option_map (fun v => TLBIndex_ref.(write_to) v s) (TLBIndex_ref.(of_regval) v) else - if string_dec reg_name "TLBProbe" then option_map (fun v => TLBProbe_ref.(write_to) v s) (TLBProbe_ref.(of_regval) v) else - if string_dec reg_name "nextPC" then option_map (fun v => nextPC_ref.(write_to) v s) (nextPC_ref.(of_regval) v) else - if string_dec reg_name "PC" then option_map (fun v => PC_ref.(write_to) v s) (PC_ref.(of_regval) v) else - None. - -Definition register_accessors := (get_regval, set_regval). - - -Definition MR a r := monadR register_value a r exception. -Definition M a := monad register_value a exception. diff --git a/snapshots/coq/riscv/riscv.v b/snapshots/coq/riscv/riscv.v new file mode 100644 index 00000000..620e5c37 --- /dev/null +++ b/snapshots/coq/riscv/riscv.v @@ -0,0 +1,37814 @@ +(*Generated by Sail from riscv.*) +Require Import Sail2_instr_kinds. +Require Import Sail2_values. +Require Import Sail2_string. +Require Import Sail2_real. +Require Import Sail2_operators_mwords. +Require Import Sail2_prompt_monad. +Require Import Sail2_prompt. +Require Import Sail2_state. +Require Import riscv_types. +Require Import riscv_extras. +Import ListNotations. +Open Scope string. +Open Scope bool. +Section Content. + +Definition eq_unit (g__147 : unit) (g__148 : unit) : bool := true. + +Definition neq_int (x : Z) (y : Z) : bool := negb (Z.eqb x y). + +Definition neq_bool (x : bool) (y : bool) : bool := negb (Bool.eqb x y). + +Axiom eq_real : forall (_ : R) (_ : R) , bool. + +Axiom lteq_real : forall (_ : R) (_ : R) , bool. + +Axiom lt_real : forall (_ : R) (_ : R) , bool. + +Axiom gteq_real : forall (_ : R) (_ : R) , bool. + +Axiom gt_real : forall (_ : R) (_ : R) , bool. + +Definition hex_bits_1_forwards_matches (bv : mword 1) : bool := true. + +Definition hex_bits_1_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_1_matches_prefix s) with + | Some (g__144,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__145 := Some ((g__144, n)) in + false + | g__145 => false + end)) then + true + else + let g__146 := s in + false + end. + +Definition hex_bits_1_backwards (s : string) +: M (mword 1) := + + (match (hex_bits_1_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 1) + | _ => exit tt : M (mword 1) + end) + : M (mword 1). + +Definition hex_bits_2_forwards_matches (bv : mword 2) : bool := true. + +Definition hex_bits_2_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_2_matches_prefix s) with + | Some (g__141,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__142 := Some ((g__141, n)) in + false + | g__142 => false + end)) then + true + else + let g__143 := s in + false + end. + +Definition hex_bits_2_backwards (s : string) +: M (mword 2) := + + (match (hex_bits_2_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 2) + | _ => exit tt : M (mword 2) + end) + : M (mword 2). + +Definition hex_bits_3_forwards_matches (bv : mword 3) : bool := true. + +Definition hex_bits_3_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_3_matches_prefix s) with + | Some (g__138,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__139 := Some ((g__138, n)) in + false + | g__139 => false + end)) then + true + else + let g__140 := s in + false + end. + +Definition hex_bits_3_backwards (s : string) +: M (mword 3) := + + (match (hex_bits_3_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 3) + | _ => exit tt : M (mword 3) + end) + : M (mword 3). + +Definition hex_bits_4_forwards_matches (bv : mword 4) : bool := true. + +Definition hex_bits_4_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_4_matches_prefix s) with + | Some (g__135,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__136 := Some ((g__135, n)) in + false + | g__136 => false + end)) then + true + else + let g__137 := s in + false + end. + +Definition hex_bits_4_backwards (s : string) +: M (mword 4) := + + (match (hex_bits_4_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 4) + | _ => exit tt : M (mword 4) + end) + : M (mword 4). + +Definition hex_bits_5_forwards_matches (bv : mword 5) : bool := true. + +Definition hex_bits_5_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_5_matches_prefix s) with + | Some (g__132,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__133 := Some ((g__132, n)) in + false + | g__133 => false + end)) then + true + else + let g__134 := s in + false + end. + +Definition hex_bits_5_backwards (s : string) +: M (mword 5) := + + (match (hex_bits_5_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 5) + | _ => exit tt : M (mword 5) + end) + : M (mword 5). + +Definition hex_bits_6_forwards_matches (bv : mword 6) : bool := true. + +Definition hex_bits_6_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_6_matches_prefix s) with + | Some (g__129,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__130 := Some ((g__129, n)) in + false + | g__130 => false + end)) then + true + else + let g__131 := s in + false + end. + +Definition hex_bits_6_backwards (s : string) +: M (mword 6) := + + (match (hex_bits_6_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 6) + | _ => exit tt : M (mword 6) + end) + : M (mword 6). + +Definition hex_bits_7_forwards_matches (bv : mword 7) : bool := true. + +Definition hex_bits_7_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_7_matches_prefix s) with + | Some (g__126,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__127 := Some ((g__126, n)) in + false + | g__127 => false + end)) then + true + else + let g__128 := s in + false + end. + +Definition hex_bits_7_backwards (s : string) +: M (mword 7) := + + (match (hex_bits_7_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 7) + | _ => exit tt : M (mword 7) + end) + : M (mword 7). + +Definition hex_bits_8_forwards_matches (bv : mword 8) : bool := true. + +Definition hex_bits_8_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_8_matches_prefix s) with + | Some (g__123,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__124 := Some ((g__123, n)) in + false + | g__124 => false + end)) then + true + else + let g__125 := s in + false + end. + +Definition hex_bits_8_backwards (s : string) +: M (mword 8) := + + (match (hex_bits_8_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 8) + | _ => exit tt : M (mword 8) + end) + : M (mword 8). + +Definition hex_bits_9_forwards_matches (bv : mword 9) : bool := true. + +Definition hex_bits_9_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_9_matches_prefix s) with + | Some (g__120,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__121 := Some ((g__120, n)) in + false + | g__121 => false + end)) then + true + else + let g__122 := s in + false + end. + +Definition hex_bits_9_backwards (s : string) +: M (mword 9) := + + (match (hex_bits_9_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 9) + | _ => exit tt : M (mword 9) + end) + : M (mword 9). + +Definition hex_bits_10_forwards_matches (bv : mword 10) : bool := true. + +Definition hex_bits_10_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_10_matches_prefix s) with + | Some (g__117,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__118 := Some ((g__117, n)) in + false + | g__118 => false + end)) then + true + else + let g__119 := s in + false + end. + +Definition hex_bits_10_backwards (s : string) +: M (mword 10) := + + (match (hex_bits_10_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 10) + | _ => exit tt : M (mword 10) + end) + : M (mword 10). + +Definition hex_bits_11_forwards_matches (bv : mword 11) : bool := true. + +Definition hex_bits_11_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_11_matches_prefix s) with + | Some (g__114,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__115 := Some ((g__114, n)) in + false + | g__115 => false + end)) then + true + else + let g__116 := s in + false + end. + +Definition hex_bits_11_backwards (s : string) +: M (mword 11) := + + (match (hex_bits_11_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 11) + | _ => exit tt : M (mword 11) + end) + : M (mword 11). + +Definition hex_bits_12_forwards_matches (bv : mword 12) : bool := true. + +Definition hex_bits_12_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_12_matches_prefix s) with + | Some (g__111,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__112 := Some ((g__111, n)) in + false + | g__112 => false + end)) then + true + else + let g__113 := s in + false + end. + +Definition hex_bits_12_backwards (s : string) +: M (mword 12) := + + (match (hex_bits_12_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 12) + | _ => exit tt : M (mword 12) + end) + : M (mword 12). + +Definition hex_bits_13_forwards_matches (bv : mword 13) : bool := true. + +Definition hex_bits_13_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_13_matches_prefix s) with + | Some (g__108,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__109 := Some ((g__108, n)) in + false + | g__109 => false + end)) then + true + else + let g__110 := s in + false + end. + +Definition hex_bits_13_backwards (s : string) +: M (mword 13) := + + (match (hex_bits_13_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 13) + | _ => exit tt : M (mword 13) + end) + : M (mword 13). + +Definition hex_bits_14_forwards_matches (bv : mword 14) : bool := true. + +Definition hex_bits_14_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_14_matches_prefix s) with + | Some (g__105,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__106 := Some ((g__105, n)) in + false + | g__106 => false + end)) then + true + else + let g__107 := s in + false + end. + +Definition hex_bits_14_backwards (s : string) +: M (mword 14) := + + (match (hex_bits_14_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 14) + | _ => exit tt : M (mword 14) + end) + : M (mword 14). + +Definition hex_bits_15_forwards_matches (bv : mword 15) : bool := true. + +Definition hex_bits_15_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_15_matches_prefix s) with + | Some (g__102,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__103 := Some ((g__102, n)) in + false + | g__103 => false + end)) then + true + else + let g__104 := s in + false + end. + +Definition hex_bits_15_backwards (s : string) +: M (mword 15) := + + (match (hex_bits_15_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 15) + | _ => exit tt : M (mword 15) + end) + : M (mword 15). + +Definition hex_bits_16_forwards_matches (bv : mword 16) : bool := true. + +Definition hex_bits_16_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_16_matches_prefix s) with + | Some (g__99,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__100 := Some ((g__99, n)) in + false + | g__100 => false + end)) then + true + else + let g__101 := s in + false + end. + +Definition hex_bits_16_backwards (s : string) +: M (mword 16) := + + (match (hex_bits_16_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 16) + | _ => exit tt : M (mword 16) + end) + : M (mword 16). + +Definition hex_bits_17_forwards_matches (bv : mword 17) : bool := true. + +Definition hex_bits_17_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_17_matches_prefix s) with + | Some (g__96,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__97 := Some ((g__96, n)) in + false + | g__97 => false + end)) then + true + else + let g__98 := s in + false + end. + +Definition hex_bits_17_backwards (s : string) +: M (mword 17) := + + (match (hex_bits_17_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 17) + | _ => exit tt : M (mword 17) + end) + : M (mword 17). + +Definition hex_bits_18_forwards_matches (bv : mword 18) : bool := true. + +Definition hex_bits_18_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_18_matches_prefix s) with + | Some (g__93,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__94 := Some ((g__93, n)) in + false + | g__94 => false + end)) then + true + else + let g__95 := s in + false + end. + +Definition hex_bits_18_backwards (s : string) +: M (mword 18) := + + (match (hex_bits_18_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 18) + | _ => exit tt : M (mword 18) + end) + : M (mword 18). + +Definition hex_bits_19_forwards_matches (bv : mword 19) : bool := true. + +Definition hex_bits_19_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_19_matches_prefix s) with + | Some (g__90,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__91 := Some ((g__90, n)) in + false + | g__91 => false + end)) then + true + else + let g__92 := s in + false + end. + +Definition hex_bits_19_backwards (s : string) +: M (mword 19) := + + (match (hex_bits_19_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 19) + | _ => exit tt : M (mword 19) + end) + : M (mword 19). + +Definition hex_bits_20_forwards_matches (bv : mword 20) : bool := true. + +Definition hex_bits_20_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_20_matches_prefix s) with + | Some (g__87,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__88 := Some ((g__87, n)) in + false + | g__88 => false + end)) then + true + else + let g__89 := s in + false + end. + +Definition hex_bits_20_backwards (s : string) +: M (mword 20) := + + (match (hex_bits_20_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 20) + | _ => exit tt : M (mword 20) + end) + : M (mword 20). + +Definition hex_bits_21_forwards_matches (bv : mword 21) : bool := true. + +Definition hex_bits_21_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_21_matches_prefix s) with + | Some (g__84,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__85 := Some ((g__84, n)) in + false + | g__85 => false + end)) then + true + else + let g__86 := s in + false + end. + +Definition hex_bits_21_backwards (s : string) +: M (mword 21) := + + (match (hex_bits_21_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 21) + | _ => exit tt : M (mword 21) + end) + : M (mword 21). + +Definition hex_bits_22_forwards_matches (bv : mword 22) : bool := true. + +Definition hex_bits_22_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_22_matches_prefix s) with + | Some (g__81,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__82 := Some ((g__81, n)) in + false + | g__82 => false + end)) then + true + else + let g__83 := s in + false + end. + +Definition hex_bits_22_backwards (s : string) +: M (mword 22) := + + (match (hex_bits_22_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 22) + | _ => exit tt : M (mword 22) + end) + : M (mword 22). + +Definition hex_bits_23_forwards_matches (bv : mword 23) : bool := true. + +Definition hex_bits_23_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_23_matches_prefix s) with + | Some (g__78,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__79 := Some ((g__78, n)) in + false + | g__79 => false + end)) then + true + else + let g__80 := s in + false + end. + +Definition hex_bits_23_backwards (s : string) +: M (mword 23) := + + (match (hex_bits_23_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 23) + | _ => exit tt : M (mword 23) + end) + : M (mword 23). + +Definition hex_bits_24_forwards_matches (bv : mword 24) : bool := true. + +Definition hex_bits_24_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_24_matches_prefix s) with + | Some (g__75,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__76 := Some ((g__75, n)) in + false + | g__76 => false + end)) then + true + else + let g__77 := s in + false + end. + +Definition hex_bits_24_backwards (s : string) +: M (mword 24) := + + (match (hex_bits_24_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 24) + | _ => exit tt : M (mword 24) + end) + : M (mword 24). + +Definition hex_bits_25_forwards_matches (bv : mword 25) : bool := true. + +Definition hex_bits_25_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_25_matches_prefix s) with + | Some (g__72,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__73 := Some ((g__72, n)) in + false + | g__73 => false + end)) then + true + else + let g__74 := s in + false + end. + +Definition hex_bits_25_backwards (s : string) +: M (mword 25) := + + (match (hex_bits_25_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 25) + | _ => exit tt : M (mword 25) + end) + : M (mword 25). + +Definition hex_bits_26_forwards_matches (bv : mword 26) : bool := true. + +Definition hex_bits_26_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_26_matches_prefix s) with + | Some (g__69,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__70 := Some ((g__69, n)) in + false + | g__70 => false + end)) then + true + else + let g__71 := s in + false + end. + +Definition hex_bits_26_backwards (s : string) +: M (mword 26) := + + (match (hex_bits_26_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 26) + | _ => exit tt : M (mword 26) + end) + : M (mword 26). + +Definition hex_bits_27_forwards_matches (bv : mword 27) : bool := true. + +Definition hex_bits_27_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_27_matches_prefix s) with + | Some (g__66,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__67 := Some ((g__66, n)) in + false + | g__67 => false + end)) then + true + else + let g__68 := s in + false + end. + +Definition hex_bits_27_backwards (s : string) +: M (mword 27) := + + (match (hex_bits_27_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 27) + | _ => exit tt : M (mword 27) + end) + : M (mword 27). + +Definition hex_bits_28_forwards_matches (bv : mword 28) : bool := true. + +Definition hex_bits_28_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_28_matches_prefix s) with + | Some (g__63,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__64 := Some ((g__63, n)) in + false + | g__64 => false + end)) then + true + else + let g__65 := s in + false + end. + +Definition hex_bits_28_backwards (s : string) +: M (mword 28) := + + (match (hex_bits_28_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 28) + | _ => exit tt : M (mword 28) + end) + : M (mword 28). + +Definition hex_bits_29_forwards_matches (bv : mword 29) : bool := true. + +Definition hex_bits_29_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_29_matches_prefix s) with + | Some (g__60,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__61 := Some ((g__60, n)) in + false + | g__61 => false + end)) then + true + else + let g__62 := s in + false + end. + +Definition hex_bits_29_backwards (s : string) +: M (mword 29) := + + (match (hex_bits_29_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 29) + | _ => exit tt : M (mword 29) + end) + : M (mword 29). + +Definition hex_bits_30_forwards_matches (bv : mword 30) : bool := true. + +Definition hex_bits_30_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_30_matches_prefix s) with + | Some (g__57,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__58 := Some ((g__57, n)) in + false + | g__58 => false + end)) then + true + else + let g__59 := s in + false + end. + +Definition hex_bits_30_backwards (s : string) +: M (mword 30) := + + (match (hex_bits_30_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 30) + | _ => exit tt : M (mword 30) + end) + : M (mword 30). + +Definition hex_bits_31_forwards_matches (bv : mword 31) : bool := true. + +Definition hex_bits_31_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_31_matches_prefix s) with + | Some (g__54,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__55 := Some ((g__54, n)) in + false + | g__55 => false + end)) then + true + else + let g__56 := s in + false + end. + +Definition hex_bits_31_backwards (s : string) +: M (mword 31) := + + (match (hex_bits_31_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 31) + | _ => exit tt : M (mword 31) + end) + : M (mword 31). + +Definition hex_bits_32_forwards_matches (bv : mword 32) : bool := true. + +Definition hex_bits_32_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_32_matches_prefix s) with + | Some (g__51,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__52 := Some ((g__51, n)) in + false + | g__52 => false + end)) then + true + else + let g__53 := s in + false + end. + +Definition hex_bits_32_backwards (s : string) +: M (mword 32) := + + (match (hex_bits_32_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 32) + | _ => exit tt : M (mword 32) + end) + : M (mword 32). + +Definition hex_bits_33_forwards_matches (bv : mword 33) : bool := true. + +Definition hex_bits_33_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_33_matches_prefix s) with + | Some (g__48,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__49 := Some ((g__48, n)) in + false + | g__49 => false + end)) then + true + else + let g__50 := s in + false + end. + +Definition hex_bits_33_backwards (s : string) +: M (mword 33) := + + (match (hex_bits_33_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 33) + | _ => exit tt : M (mword 33) + end) + : M (mword 33). + +Definition hex_bits_48_forwards_matches (bv : mword 48) : bool := true. + +Definition hex_bits_48_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_48_matches_prefix s) with + | Some (g__45,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__46 := Some ((g__45, n)) in + false + | g__46 => false + end)) then + true + else + let g__47 := s in + false + end. + +Definition hex_bits_48_backwards (s : string) +: M (mword 48) := + + (match (hex_bits_48_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 48) + | _ => exit tt : M (mword 48) + end) + : M (mword 48). + +Definition hex_bits_64_forwards_matches (bv : mword 64) : bool := true. + +Definition hex_bits_64_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_64_matches_prefix s) with + | Some (g__42,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__43 := Some ((g__42, n)) in + false + | g__43 => false + end)) then + true + else + let g__44 := s in + false + end. + +Definition hex_bits_64_backwards (s : string) +: M (mword 64) := + + (match (hex_bits_64_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 64) + | _ => exit tt : M (mword 64) + end) + : M (mword 64). + +Axiom vcons : forall {n : Z} {a : Type} (_ : a) (_ : vec a n) , vec a (n + 1). + +Axiom vector_concat : forall {n : Z} {m : Z} {a : Type} (_ : vec a n) (_ : vec a m) , vec a (n + m). + +Definition neq_vec {n : Z} (x : mword n) (y : mword n) : bool := negb (eq_vec x y). + + + +Axiom __raw_SetSlice_int : forall (w : Z) (_ : Z) (_ : Z) (_ : mword w) , Z. + +Definition __GetSlice_int (n : Z) (m : Z) (o : Z) `{ArithFact (n >= 0)} +: mword n := + + get_slice_int n m o. + +Axiom __raw_SetSlice_bits : forall (n : Z) (w : Z) (_ : mword n) (_ : Z) (_ : mword w) , mword n. + +Axiom __raw_GetSlice_bits : forall + +(n : Z) (w : Z) (_ : mword n) (_ : Z) +`{ArithFact (w >= 0)}, +mword w. + +Axiom __SignExtendSlice : forall {m : Z} (_ : mword m) (_ : Z) (_ : Z) , mword m. + +Axiom __ZeroExtendSlice : forall {m : Z} (_ : mword m) (_ : Z) (_ : Z) , mword m. + +Definition cast_unit_vec (b : bitU) +: M (mword 1) := + + (match b with + | B0 => returnm ((vec_of_bits [B0] : mword 1) : mword 1) + | B1 => returnm ((vec_of_bits [B1] : mword 1) : mword 1) + | _ => exit tt : M (mword 1) + end) + : M (mword 1). + +Axiom DecStr : forall (_ : Z) , string. + +Axiom HexStr : forall (_ : Z) , string. + +Axiom real_power : forall (_ : R) (_ : Z) , R. + +Axiom add_real : forall (_ : R) (_ : R) , R. + +Axiom sub_real : forall (_ : R) (_ : R) , R. + +Axiom negate_real : forall (_ : R) , R. + +Axiom mult_real : forall (_ : R) (_ : R) , R. + +Axiom Sqrt : forall (_ : R) , R. + +Axiom RoundDown : forall (_ : R) , Z. + +Axiom RoundUp : forall (_ : R) , Z. + +Axiom abs_real : forall (_ : R) , R. + +Axiom quotient_nat : forall + +(_ : {n : Z & ArithFact (n >= 0)}) (_ : {n : Z & ArithFact (n >= 0)}) +, +{n : Z & ArithFact (n >= 0)}. + +Axiom quotient_real : forall (_ : R) (_ : R) , R. + +Axiom quotient : forall (_ : Z) (_ : Z) , Z. + +Axiom quot_round_zero : forall (_ : Z) (_ : Z) , Z. + +Axiom rem_round_zero : forall (_ : Z) (_ : Z) , Z. + +Axiom modulus : forall (_ : Z) (_ : Z) , Z. + +Axiom Real : forall (_ : Z) , R. + +Definition __RISCV_write (addr : mword 64) (width : Z) (data : mword (8 * width)) +: M (bool) := + + (write_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr data) + : M (bool). + +Axiom __TraceMemoryWrite : forall {m : Z} (n : Z) (_ : mword m) (_ : mword (8 * n)) , unit. + +Definition __RISCV_read (addr : mword 64) (width : Z) (aq : bool) (rl : bool) (res : bool) +`{ArithFact (width >= 0)} +: M (option (mword (8 * width))) := + + (match (aq, rl, res) with + | (false, false, false) => + (read_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr) >>= fun w__0 : mword (8 * width) => + returnm ((Some + (w__0)) + : option (mword (8 * width))) + | (true, false, false) => + (read_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr) >>= fun w__1 : mword (8 * width) => + returnm ((Some + (w__1)) + : option (mword (8 * width))) + | (true, true, false) => + (read_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr) >>= fun w__2 : mword (8 * width) => + returnm ((Some + (w__2)) + : option (mword (8 * width))) + | (false, false, true) => + (read_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr) >>= fun w__3 : mword (8 * width) => + returnm ((Some + (w__3)) + : option (mword (8 * width))) + | (true, false, true) => + (read_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr) >>= fun w__4 : mword (8 * width) => + returnm ((Some + (w__4)) + : option (mword (8 * width))) + | (true, true, true) => + (read_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr) >>= fun w__5 : mword (8 * width) => + returnm ((Some + (w__5)) + : option (mword (8 * width))) + | (false, true, false) => returnm (None : option (mword (8 * width))) + | (false, true, true) => returnm (None : option (mword (8 * width))) + end) + : M (option (mword (8 * width))). + +Axiom __TraceMemoryRead : forall {m : Z} (n : Z) (_ : mword m) (_ : mword (8 * n)) , unit. + +Definition ex_nat {ex30597_ : Z} (n : Z) `{ArithFact (0 <= ex30597_)} `{ArithFact (n = ex30597_)} +: {syn_n : Z & ArithFact (syn_n >= 0)} := + + build_ex(n). + +Definition ex_int {ex30599_ : Z} (n : Z) `{ArithFact (n = ex30599_)} +: {syn_n : Z & ArithFact (True)} := + + build_ex(n). + +Definition coerce_int_nat {ex30601_ : Z} (x : Z) `{ArithFact (x = ex30601_)} +: M ({n : Z & ArithFact (n >= 0)}) := + + assert_exp' (x >=? 0) "file ""prelude.sail"", line 1034, character 29 to line 1034, character 29: constraint('x >= 0)" >>= fun _ => + returnm (build_ex (x + : Z)). + +Definition EXTS {n : Z} (m__tv : Z) (v : mword n) `{ArithFact (m__tv >= n)} +: mword m__tv := + + sign_extend v m__tv. + +Definition EXTZ {n : Z} (m__tv : Z) (v : mword n) `{ArithFact (m__tv >= n)} +: mword m__tv := + + zero_extend v m__tv. + +Definition zopz0zI_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= (0 + 1))} +: bool := + + Z.ltb (projT1 (sint x)) (projT1 (sint y)). + +Definition zopz0zKzJ_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= (0 + 1))} +: bool := + + Z.geb (projT1 (sint x)) (projT1 (sint y)). + +Definition zopz0zI_u {n : Z} (x : mword n) (y : mword n) +: bool := + + Z.ltb (projT1 (uint x)) (projT1 (uint y)). + +Definition zopz0zKzJ_u {n : Z} (x : mword n) (y : mword n) +: bool := + + Z.geb (projT1 (uint x)) (projT1 (uint y)). + +Definition zopz0zIzJ_u {n : Z} (x : mword n) (y : mword n) +: bool := + + Z.leb (projT1 (uint x)) (projT1 (uint y)). + +Definition bool_to_bits (x : bool) +: mword 1 := + + if (x) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1). + +Definition bit_to_bool (b : bitU) +: M (bool) := + + (match b with + | B1 => returnm (true : bool) + | B0 => returnm (false : bool) + | _ => exit tt : M (bool) + end) + : M (bool). + +Definition vector64 (n : Z) : mword 64 := get_slice_int 64 n 0. + +Definition to_bits (l : Z) (n : Z) `{ArithFact (l >= 0)} : mword l := get_slice_int l n 0. + +Axiom vector_update_subrange_inc : forall +{n : Z} +(_ : mword n) (m : Z) (o : Z) (_ : mword (o - (m - 1))) +, +mword n. + +Definition shift_right_arith64 (v : mword 64) (shift : mword 6) +: mword 64 := + + let v128 : bits 128 := EXTS 128 v in + subrange_vec_dec (shift_bits_right v128 shift) 63 0. + +Definition shift_right_arith32 (v : mword 32) (shift : mword 5) +: mword 32 := + + let v64 : bits 64 := EXTS 64 v in + subrange_vec_dec (shift_bits_right v64 shift) 31 0. + +Fixpoint _rec_n_leading_spaces (s : string) (_reclimit : Z) (_acc : Acc (Zwf 0) _reclimit) +{struct _acc} : M ({n : Z & ArithFact (n >= 0)}) := + + assert_exp' (Z.geb _reclimit 0) "recursion limit reached" >>= fun _ => + let p0_ := s in + (if ((generic_eq p0_ "")) then returnm (build_ex (0 : Z)) + else + let p0_ := string_take s 1 in + (if ((generic_eq p0_ " ")) then + (_rec_n_leading_spaces (string_drop s 1) (Z.sub _reclimit 1) (_limit_reduces _acc)) >>= fun '(existT _ w__0 _ : {n : Z & ArithFact (n >= + 0)}) => + returnm (build_ex (projT1 (build_ex (Z.add 1 w__0) + : {_atom : Z & ArithFact (exists ex21215_ , _atom = (1 + ex21215_) /\ 0 <= ex21215_)}))) + else returnm (build_ex (0 : Z))) + : M ({n : Z & ArithFact (n >= 0)})) + : M ({n : Z & ArithFact (n >= 0)}). + +Definition n_leading_spaces (s : string) +: M ({n : Z & ArithFact (n >= 0)}) := + + (_rec_n_leading_spaces s ((projT1 (string_length s)) : Z) (Zwf_guarded _)) + : M ({n : Z & ArithFact (n >= 0)}). + +Definition spc_forwards '(tt : unit) : string := " ". + +Definition spc_backwards (s : string) : unit := tt. + +Definition spc_matches_prefix (s : string) +: M (option ((unit * {n : Z & ArithFact (n >= 0)}))) := + + (n_leading_spaces s) >>= fun '(existT _ n _) => + let p0_ := n in + returnm ((if sumbool_of_bool ((Z.eqb p0_ 0)) then None + else Some ((tt, build_ex n))) + : option ((unit * {n : Z & ArithFact (n >= 0)}))). + +Definition opt_spc_forwards '(tt : unit) : string := "". + +Definition opt_spc_backwards (s : string) : unit := tt. + +Definition opt_spc_matches_prefix (s : string) +: M (option ((unit * {n : Z & ArithFact (n >= 0)}))) := + + (n_leading_spaces s) >>= fun '(existT _ w__0 _ : {n : Z & ArithFact (n >= 0)}) => + returnm ((Some + ((tt, build_ex w__0))) + : option ((unit * {n : Z & ArithFact (n >= 0)}))). + +Definition def_spc_forwards '(tt : unit) : string := " ". + +Definition def_spc_backwards (s : string) : unit := tt. + +Definition def_spc_matches_prefix (s : string) +: M (option ((unit * {n : Z & ArithFact (n >= 0)}))) := + + (opt_spc_matches_prefix s) + : M (option ((unit * {n : Z & ArithFact (n >= 0)}))). + +Definition xlen := 64. +Hint Unfold xlen : sail. +Definition xlen_max_unsigned := Z.sub (projT1 (pow2 xlen)) 1. +Hint Unfold xlen_max_unsigned : sail. +Definition xlen_max_signed := Z.sub (projT1 (pow2 (Z.sub xlen 1))) 1. +Hint Unfold xlen_max_signed : sail. +Definition xlen_min_signed := Z.sub 0 (projT1 (pow2 (Z.sub xlen 1))). +Hint Unfold xlen_min_signed : sail. +Definition regbits_to_regno (b : mword 5) +: {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)} := + + build_ex(let 'r := projT1 (uint b) in + r). + +Definition creg2reg_bits (creg : mword 3) +: mword 5 := + + concat_vec (vec_of_bits [B0;B1] : mword 2) creg. + +Definition zreg : regbits := (vec_of_bits [B0;B0;B0;B0;B0] : mword 5). +Hint Unfold zreg : sail. +Definition ra : regbits := (vec_of_bits [B0;B0;B0;B0;B1] : mword 5). +Hint Unfold ra : sail. +Definition sp : regbits := (vec_of_bits [B0;B0;B0;B1;B0] : mword 5). +Hint Unfold sp : sail. +Definition rX (r : Z) `{ArithFact (0 <= r /\ (r + 1) <= 32)} +: M (mword 64) := + + let p0_ := r in + (if sumbool_of_bool ((Z.eqb p0_ 0)) then + returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + : mword 64) + else if sumbool_of_bool ((Z.eqb p0_ 1)) then ((read_reg x1_ref) : M (mword 64)) : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 2)) then ((read_reg x2_ref) : M (mword 64)) : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 3)) then ((read_reg x3_ref) : M (mword 64)) : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 4)) then ((read_reg x4_ref) : M (mword 64)) : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 5)) then ((read_reg x5_ref) : M (mword 64)) : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 6)) then ((read_reg x6_ref) : M (mword 64)) : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 7)) then ((read_reg x7_ref) : M (mword 64)) : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 8)) then ((read_reg x8_ref) : M (mword 64)) : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 9)) then ((read_reg x9_ref) : M (mword 64)) : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 10)) then + ((read_reg x10_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 11)) then + ((read_reg x11_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 12)) then + ((read_reg x12_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 13)) then + ((read_reg x13_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 14)) then + ((read_reg x14_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 15)) then + ((read_reg x15_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 16)) then + ((read_reg x16_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 17)) then + ((read_reg x17_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 18)) then + ((read_reg x18_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 19)) then + ((read_reg x19_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 20)) then + ((read_reg x20_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 21)) then + ((read_reg x21_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 22)) then + ((read_reg x22_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 23)) then + ((read_reg x23_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 24)) then + ((read_reg x24_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 25)) then + ((read_reg x25_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 26)) then + ((read_reg x26_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 27)) then + ((read_reg x27_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 28)) then + ((read_reg x28_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 29)) then + ((read_reg x29_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 30)) then + ((read_reg x30_ref) : M (mword 64)) + : M (xlenbits) + else ((read_reg x31_ref) : M (mword 64)) : M (xlenbits)) + : M (mword 64). + +Definition rvfi_wX (r : Z) (v : mword 64) `{ArithFact (0 <= r /\ (r + 1) <= 32)} : unit := tt. + +Definition wX (r : Z) (v : mword 64) `{ArithFact (0 <= r /\ (r + 1) <= 32)} +: M (unit) := + + let p0_ := r in + (if sumbool_of_bool ((Z.eqb p0_ 0)) then returnm (tt : unit) + else if sumbool_of_bool ((Z.eqb p0_ 1)) then write_reg x1_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 2)) then write_reg x2_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 3)) then write_reg x3_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 4)) then write_reg x4_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 5)) then write_reg x5_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 6)) then write_reg x6_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 7)) then write_reg x7_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 8)) then write_reg x8_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 9)) then write_reg x9_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 10)) then write_reg x10_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 11)) then write_reg x11_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 12)) then write_reg x12_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 13)) then write_reg x13_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 14)) then write_reg x14_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 15)) then write_reg x15_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 16)) then write_reg x16_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 17)) then write_reg x17_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 18)) then write_reg x18_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 19)) then write_reg x19_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 20)) then write_reg x20_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 21)) then write_reg x21_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 22)) then write_reg x22_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 23)) then write_reg x23_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 24)) then write_reg x24_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 25)) then write_reg x25_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 26)) then write_reg x26_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 27)) then write_reg x27_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 28)) then write_reg x28_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 29)) then write_reg x29_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 30)) then write_reg x30_ref v : M (unit) + else write_reg x31_ref v : M (unit)) >> + returnm ((if ((neq_int r 0)) then + let '_ := (rvfi_wX r v) : unit in + print_endline + (String.append "x" + (String.append (string_of_int r) (String.append " <- " (string_of_bits v)))) + else tt) + : unit). + +Definition reg_name_abi (r : mword 5) +: string := + + let b__0 := r in + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))))) + then + "zero" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))))) + then + "ra" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : mword 5))))) + then + "sp" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : mword 5))))) + then + "gp" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : mword 5))))) + then + "tp" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B1] : mword 5))))) + then + "t0" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B0] : mword 5))))) + then + "t1" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B1] : mword 5))))) + then + "t2" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : mword 5))))) + then + "fp" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B1] : mword 5))))) + then + "s1" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B0] : mword 5))))) + then + "a0" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B1] : mword 5))))) + then + "a1" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : mword 5))))) + then + "a2" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B1] : mword 5))))) + then + "a3" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B0] : mword 5))))) + then + "a4" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B1] : mword 5))))) + then + "a5" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : mword 5))))) + then + "a6" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B1] : mword 5))))) + then + "a7" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B0] : mword 5))))) + then + "s2" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B1] : mword 5))))) + then + "s3" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : mword 5))))) + then + "s4" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B1] : mword 5))))) + then + "s5" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B0] : mword 5))))) + then + "s6" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B1] : mword 5))))) + then + "s7" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : mword 5))))) + then + "s8" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B1] : mword 5))))) + then + "s9" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B0] : mword 5))))) + then + "s10" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B1] : mword 5))))) + then + "s11" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : mword 5))))) + then + "t3" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B1] : mword 5))))) + then + "t4" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B1;B0] : mword 5))))) + then + "t5" + else "t6". + +Definition Architecture_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: Architecture := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then RV32 + else if sumbool_of_bool ((Z.eqb p0_ 1)) then RV64 + else RV128. + +Definition num_of_Architecture (arg_ : Architecture) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with | RV32 => 0 | RV64 => 1 | RV128 => 2 end). + +Definition architecture (a : mword 2) +: option Architecture := + + let b__0 := a in + if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then Some (RV32) + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then Some (RV64) + else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then Some (RV128) + else None. + +Definition arch_to_bits (a : Architecture) +: mword 2 := + + match a with + | RV32 => (vec_of_bits [B0;B1] : mword 2) + | RV64 => (vec_of_bits [B1;B0] : mword 2) + | RV128 => (vec_of_bits [B1;B1] : mword 2) + end. + +Definition Privilege_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: Privilege := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then User + else if sumbool_of_bool ((Z.eqb p0_ 1)) then Supervisor + else Machine. + +Definition num_of_Privilege (arg_ : Privilege) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with | User => 0 | Supervisor => 1 | Machine => 2 end). + +Definition privLevel_to_bits (p : Privilege) +: mword 2 := + + match p with + | User => (vec_of_bits [B0;B0] : mword 2) + | Supervisor => (vec_of_bits [B0;B1] : mword 2) + | Machine => (vec_of_bits [B1;B1] : mword 2) + end. + +Definition privLevel_of_bits (p : mword 2) +: Privilege := + + let b__0 := p in + if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then User + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then Supervisor + else Machine. + +Definition privLevel_to_str (p : Privilege) +: string := + + match p with | User => "U" | Supervisor => "S" | Machine => "M" end. + +Definition AccessType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} +: AccessType := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Read + else if sumbool_of_bool ((Z.eqb p0_ 1)) then Write + else if sumbool_of_bool ((Z.eqb p0_ 2)) then ReadWrite + else Execute. + +Definition num_of_AccessType (arg_ : AccessType) +: {e : Z & ArithFact (0 <= e /\ e <= 3)} := + + build_ex(match arg_ with | Read => 0 | Write => 1 | ReadWrite => 2 | Execute => 3 end). + +Definition accessType_to_str (a : AccessType) +: string := + + match a with | Read => "R" | Write => "W" | ReadWrite => "RW" | Execute => "X" end. + +Definition ReadType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 1)} +: ReadType := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Instruction + else Data. + +Definition num_of_ReadType (arg_ : ReadType) +: {e : Z & ArithFact (0 <= e /\ e <= 1)} := + + build_ex(match arg_ with | Instruction => 0 | Data => 1 end). + +Definition readType_to_str (r : ReadType) +: string := + + match r with | Instruction => "I" | Data => "D" end. + +Definition word_width_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} +: word_width := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then BYTE + else if sumbool_of_bool ((Z.eqb p0_ 1)) then HALF + else if sumbool_of_bool ((Z.eqb p0_ 2)) then WORD + else DOUBLE. + +Definition num_of_word_width (arg_ : word_width) +: {e : Z & ArithFact (0 <= e /\ e <= 3)} := + + build_ex(match arg_ with | BYTE => 0 | HALF => 1 | WORD => 2 | DOUBLE => 3 end). + +Definition InterruptType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 8)} +: InterruptType := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then I_U_Software + else if sumbool_of_bool ((Z.eqb p0_ 1)) then I_S_Software + else if sumbool_of_bool ((Z.eqb p0_ 2)) then I_M_Software + else if sumbool_of_bool ((Z.eqb p0_ 3)) then I_U_Timer + else if sumbool_of_bool ((Z.eqb p0_ 4)) then I_S_Timer + else if sumbool_of_bool ((Z.eqb p0_ 5)) then I_M_Timer + else if sumbool_of_bool ((Z.eqb p0_ 6)) then I_U_External + else if sumbool_of_bool ((Z.eqb p0_ 7)) then I_S_External + else I_M_External. + +Definition num_of_InterruptType (arg_ : InterruptType) +: {e : Z & ArithFact (0 <= e /\ e <= 8)} := + + build_ex(match arg_ with + | I_U_Software => 0 + | I_S_Software => 1 + | I_M_Software => 2 + | I_U_Timer => 3 + | I_S_Timer => 4 + | I_M_Timer => 5 + | I_U_External => 6 + | I_S_External => 7 + | I_M_External => 8 + end). + +Definition interruptType_to_bits (i : InterruptType) +: mword 4 := + + match i with + | I_U_Software => (vec_of_bits [B0;B0;B0;B0] : mword 4) + | I_S_Software => (vec_of_bits [B0;B0;B0;B1] : mword 4) + | I_M_Software => (vec_of_bits [B0;B0;B1;B1] : mword 4) + | I_U_Timer => (vec_of_bits [B0;B1;B0;B0] : mword 4) + | I_S_Timer => (vec_of_bits [B0;B1;B0;B1] : mword 4) + | I_M_Timer => (vec_of_bits [B0;B1;B1;B1] : mword 4) + | I_U_External => (vec_of_bits [B1;B0;B0;B0] : mword 4) + | I_S_External => (vec_of_bits [B1;B0;B0;B1] : mword 4) + | I_M_External => (vec_of_bits [B1;B0;B1;B1] : mword 4) + end. + +Definition ExceptionType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 15)} +: ExceptionType := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then E_Fetch_Addr_Align + else if sumbool_of_bool ((Z.eqb p0_ 1)) then E_Fetch_Access_Fault + else if sumbool_of_bool ((Z.eqb p0_ 2)) then E_Illegal_Instr + else if sumbool_of_bool ((Z.eqb p0_ 3)) then E_Breakpoint + else if sumbool_of_bool ((Z.eqb p0_ 4)) then E_Load_Addr_Align + else if sumbool_of_bool ((Z.eqb p0_ 5)) then E_Load_Access_Fault + else if sumbool_of_bool ((Z.eqb p0_ 6)) then E_SAMO_Addr_Align + else if sumbool_of_bool ((Z.eqb p0_ 7)) then E_SAMO_Access_Fault + else if sumbool_of_bool ((Z.eqb p0_ 8)) then E_U_EnvCall + else if sumbool_of_bool ((Z.eqb p0_ 9)) then E_S_EnvCall + else if sumbool_of_bool ((Z.eqb p0_ 10)) then E_Reserved_10 + else if sumbool_of_bool ((Z.eqb p0_ 11)) then E_M_EnvCall + else if sumbool_of_bool ((Z.eqb p0_ 12)) then E_Fetch_Page_Fault + else if sumbool_of_bool ((Z.eqb p0_ 13)) then E_Load_Page_Fault + else if sumbool_of_bool ((Z.eqb p0_ 14)) then E_Reserved_14 + else E_SAMO_Page_Fault. + +Definition num_of_ExceptionType (arg_ : ExceptionType) +: {e : Z & ArithFact (0 <= e /\ e <= 15)} := + + build_ex(match arg_ with + | E_Fetch_Addr_Align => 0 + | E_Fetch_Access_Fault => 1 + | E_Illegal_Instr => 2 + | E_Breakpoint => 3 + | E_Load_Addr_Align => 4 + | E_Load_Access_Fault => 5 + | E_SAMO_Addr_Align => 6 + | E_SAMO_Access_Fault => 7 + | E_U_EnvCall => 8 + | E_S_EnvCall => 9 + | E_Reserved_10 => 10 + | E_M_EnvCall => 11 + | E_Fetch_Page_Fault => 12 + | E_Load_Page_Fault => 13 + | E_Reserved_14 => 14 + | E_SAMO_Page_Fault => 15 + end). + +Definition exceptionType_to_bits (e : ExceptionType) +: mword 4 := + + match e with + | E_Fetch_Addr_Align => (vec_of_bits [B0;B0;B0;B0] : mword 4) + | E_Fetch_Access_Fault => (vec_of_bits [B0;B0;B0;B1] : mword 4) + | E_Illegal_Instr => (vec_of_bits [B0;B0;B1;B0] : mword 4) + | E_Breakpoint => (vec_of_bits [B0;B0;B1;B1] : mword 4) + | E_Load_Addr_Align => (vec_of_bits [B0;B1;B0;B0] : mword 4) + | E_Load_Access_Fault => (vec_of_bits [B0;B1;B0;B1] : mword 4) + | E_SAMO_Addr_Align => (vec_of_bits [B0;B1;B1;B0] : mword 4) + | E_SAMO_Access_Fault => (vec_of_bits [B0;B1;B1;B1] : mword 4) + | E_U_EnvCall => (vec_of_bits [B1;B0;B0;B0] : mword 4) + | E_S_EnvCall => (vec_of_bits [B1;B0;B0;B1] : mword 4) + | E_Reserved_10 => (vec_of_bits [B1;B0;B1;B0] : mword 4) + | E_M_EnvCall => (vec_of_bits [B1;B0;B1;B1] : mword 4) + | E_Fetch_Page_Fault => (vec_of_bits [B1;B1;B0;B0] : mword 4) + | E_Load_Page_Fault => (vec_of_bits [B1;B1;B0;B1] : mword 4) + | E_Reserved_14 => (vec_of_bits [B1;B1;B1;B0] : mword 4) + | E_SAMO_Page_Fault => (vec_of_bits [B1;B1;B1;B1] : mword 4) + end. + +Definition exceptionType_to_str (e : ExceptionType) +: string := + + match e with + | E_Fetch_Addr_Align => "misaligned-fetch" + | E_Fetch_Access_Fault => "fetch-access-fault" + | E_Illegal_Instr => "illegal-instruction" + | E_Breakpoint => "breakpoint" + | E_Load_Addr_Align => "misaligned-load" + | E_Load_Access_Fault => "load-access-fault" + | E_SAMO_Addr_Align => "misaliged-store/amo" + | E_SAMO_Access_Fault => "store/amo-access-fault" + | E_U_EnvCall => "u-call" + | E_S_EnvCall => "s-call" + | E_Reserved_10 => "reserved-0" + | E_M_EnvCall => "m-call" + | E_Fetch_Page_Fault => "fetch-page-fault" + | E_Load_Page_Fault => "load-page-fault" + | E_Reserved_14 => "reserved-1" + | E_SAMO_Page_Fault => "store/amo-page-fault" + end. + +Definition not_implemented {a : Type} (message : string) +: M (a) := + + (throw (Error_not_implemented + (message))) + : M (a). + +Definition internal_error {a : Type} (s : string) +: M (a) := + + assert_exp' false s >>= fun _ => (throw (Error_internal_error (tt))) : M (a). + +Definition TrapVectorMode_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: TrapVectorMode := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then TV_Direct + else if sumbool_of_bool ((Z.eqb p0_ 1)) then TV_Vector + else TV_Reserved. + +Definition num_of_TrapVectorMode (arg_ : TrapVectorMode) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with | TV_Direct => 0 | TV_Vector => 1 | TV_Reserved => 2 end). + +Definition trapVectorMode_of_bits (m : mword 2) +: TrapVectorMode := + + let b__0 := m in + if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then TV_Direct + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then TV_Vector + else TV_Reserved. + +Definition ExtStatus_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} +: ExtStatus := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Off + else if sumbool_of_bool ((Z.eqb p0_ 1)) then Initial + else if sumbool_of_bool ((Z.eqb p0_ 2)) then Clean + else Dirty. + +Definition num_of_ExtStatus (arg_ : ExtStatus) +: {e : Z & ArithFact (0 <= e /\ e <= 3)} := + + build_ex(match arg_ with | Off => 0 | Initial => 1 | Clean => 2 | Dirty => 3 end). + +Definition extStatus_to_bits (e : ExtStatus) +: mword 2 := + + match e with + | Off => (vec_of_bits [B0;B0] : mword 2) + | Initial => (vec_of_bits [B0;B1] : mword 2) + | Clean => (vec_of_bits [B1;B0] : mword 2) + | Dirty => (vec_of_bits [B1;B1] : mword 2) + end. + +Definition extStatus_of_bits (e : mword 2) +: ExtStatus := + + let b__0 := e in + if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then Off + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then Initial + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then Clean + else Dirty. + +Definition SATPMode_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: SATPMode := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Sbare + else if sumbool_of_bool ((Z.eqb p0_ 1)) then Sv32 + else Sv39. + +Definition num_of_SATPMode (arg_ : SATPMode) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with | Sbare => 0 | Sv32 => 1 | Sv39 => 2 end). + +Definition satpMode_of_bits (a : Architecture) (m : mword 4) +: option SATPMode := + + match (a, m) with + | (g__39, b__0) => + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0] : mword 4))) then Some (Sbare) + else + match (g__39, b__0) with + | (RV32, b__0) => + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1] : mword 4))) then Some (Sv32) + else match (RV32, b__0) with | (g__40, g__41) => None end + | (RV64, b__0) => + if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0] : mword 4))) then Some (Sv39) + else match (RV64, b__0) with | (g__40, g__41) => None end + | (g__40, g__41) => None + end + end. + +Definition uop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 1)} +: uop := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_LUI + else RISCV_AUIPC. + +Definition num_of_uop (arg_ : uop) +: {e : Z & ArithFact (0 <= e /\ e <= 1)} := + + build_ex(match arg_ with | RISCV_LUI => 0 | RISCV_AUIPC => 1 end). + +Definition bop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 5)} +: bop := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_BEQ + else if sumbool_of_bool ((Z.eqb p0_ 1)) then RISCV_BNE + else if sumbool_of_bool ((Z.eqb p0_ 2)) then RISCV_BLT + else if sumbool_of_bool ((Z.eqb p0_ 3)) then RISCV_BGE + else if sumbool_of_bool ((Z.eqb p0_ 4)) then RISCV_BLTU + else RISCV_BGEU. + +Definition num_of_bop (arg_ : bop) +: {e : Z & ArithFact (0 <= e /\ e <= 5)} := + + build_ex(match arg_ with + | RISCV_BEQ => 0 + | RISCV_BNE => 1 + | RISCV_BLT => 2 + | RISCV_BGE => 3 + | RISCV_BLTU => 4 + | RISCV_BGEU => 5 + end). + +Definition iop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 5)} +: iop := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_ADDI + else if sumbool_of_bool ((Z.eqb p0_ 1)) then RISCV_SLTI + else if sumbool_of_bool ((Z.eqb p0_ 2)) then RISCV_SLTIU + else if sumbool_of_bool ((Z.eqb p0_ 3)) then RISCV_XORI + else if sumbool_of_bool ((Z.eqb p0_ 4)) then RISCV_ORI + else RISCV_ANDI. + +Definition num_of_iop (arg_ : iop) +: {e : Z & ArithFact (0 <= e /\ e <= 5)} := + + build_ex(match arg_ with + | RISCV_ADDI => 0 + | RISCV_SLTI => 1 + | RISCV_SLTIU => 2 + | RISCV_XORI => 3 + | RISCV_ORI => 4 + | RISCV_ANDI => 5 + end). + +Definition sop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: sop := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_SLLI + else if sumbool_of_bool ((Z.eqb p0_ 1)) then RISCV_SRLI + else RISCV_SRAI. + +Definition num_of_sop (arg_ : sop) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with | RISCV_SLLI => 0 | RISCV_SRLI => 1 | RISCV_SRAI => 2 end). + +Definition rop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 9)} +: rop := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_ADD + else if sumbool_of_bool ((Z.eqb p0_ 1)) then RISCV_SUB + else if sumbool_of_bool ((Z.eqb p0_ 2)) then RISCV_SLL + else if sumbool_of_bool ((Z.eqb p0_ 3)) then RISCV_SLT + else if sumbool_of_bool ((Z.eqb p0_ 4)) then RISCV_SLTU + else if sumbool_of_bool ((Z.eqb p0_ 5)) then RISCV_XOR + else if sumbool_of_bool ((Z.eqb p0_ 6)) then RISCV_SRL + else if sumbool_of_bool ((Z.eqb p0_ 7)) then RISCV_SRA + else if sumbool_of_bool ((Z.eqb p0_ 8)) then RISCV_OR + else RISCV_AND. + +Definition num_of_rop (arg_ : rop) +: {e : Z & ArithFact (0 <= e /\ e <= 9)} := + + build_ex(match arg_ with + | RISCV_ADD => 0 + | RISCV_SUB => 1 + | RISCV_SLL => 2 + | RISCV_SLT => 3 + | RISCV_SLTU => 4 + | RISCV_XOR => 5 + | RISCV_SRL => 6 + | RISCV_SRA => 7 + | RISCV_OR => 8 + | RISCV_AND => 9 + end). + +Definition ropw_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 4)} +: ropw := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_ADDW + else if sumbool_of_bool ((Z.eqb p0_ 1)) then RISCV_SUBW + else if sumbool_of_bool ((Z.eqb p0_ 2)) then RISCV_SLLW + else if sumbool_of_bool ((Z.eqb p0_ 3)) then RISCV_SRLW + else RISCV_SRAW. + +Definition num_of_ropw (arg_ : ropw) +: {e : Z & ArithFact (0 <= e /\ e <= 4)} := + + build_ex(match arg_ with + | RISCV_ADDW => 0 + | RISCV_SUBW => 1 + | RISCV_SLLW => 2 + | RISCV_SRLW => 3 + | RISCV_SRAW => 4 + end). + +Definition sopw_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: sopw := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_SLLIW + else if sumbool_of_bool ((Z.eqb p0_ 1)) then RISCV_SRLIW + else RISCV_SRAIW. + +Definition num_of_sopw (arg_ : sopw) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with | RISCV_SLLIW => 0 | RISCV_SRLIW => 1 | RISCV_SRAIW => 2 end). + +Definition amoop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 8)} +: amoop := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then AMOSWAP + else if sumbool_of_bool ((Z.eqb p0_ 1)) then AMOADD + else if sumbool_of_bool ((Z.eqb p0_ 2)) then AMOXOR + else if sumbool_of_bool ((Z.eqb p0_ 3)) then AMOAND + else if sumbool_of_bool ((Z.eqb p0_ 4)) then AMOOR + else if sumbool_of_bool ((Z.eqb p0_ 5)) then AMOMIN + else if sumbool_of_bool ((Z.eqb p0_ 6)) then AMOMAX + else if sumbool_of_bool ((Z.eqb p0_ 7)) then AMOMINU + else AMOMAXU. + +Definition num_of_amoop (arg_ : amoop) +: {e : Z & ArithFact (0 <= e /\ e <= 8)} := + + build_ex(match arg_ with + | AMOSWAP => 0 + | AMOADD => 1 + | AMOXOR => 2 + | AMOAND => 3 + | AMOOR => 4 + | AMOMIN => 5 + | AMOMAX => 6 + | AMOMINU => 7 + | AMOMAXU => 8 + end). + +Definition csrop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: csrop := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then CSRRW + else if sumbool_of_bool ((Z.eqb p0_ 1)) then CSRRS + else CSRRC. + +Definition num_of_csrop (arg_ : csrop) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with | CSRRW => 0 | CSRRS => 1 | CSRRC => 2 end). + +Definition reg_name_forwards (arg_ : mword 5) +: string := + + let b__0 := arg_ in + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))))) + then + "zero" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))))) + then + "ra" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : mword 5))))) + then + "sp" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : mword 5))))) + then + "gp" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : mword 5))))) + then + "tp" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B1] : mword 5))))) + then + "t0" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B0] : mword 5))))) + then + "t1" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B1] : mword 5))))) + then + "t2" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : mword 5))))) + then + "fp" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B1] : mword 5))))) + then + "s1" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B0] : mword 5))))) + then + "a0" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B1] : mword 5))))) + then + "a1" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : mword 5))))) + then + "a2" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B1] : mword 5))))) + then + "a3" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B0] : mword 5))))) + then + "a4" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B1] : mword 5))))) + then + "a5" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : mword 5))))) + then + "a6" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B1] : mword 5))))) + then + "a7" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B0] : mword 5))))) + then + "s2" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B1] : mword 5))))) + then + "s3" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : mword 5))))) + then + "s4" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B1] : mword 5))))) + then + "s5" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B0] : mword 5))))) + then + "s6" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B1] : mword 5))))) + then + "s7" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : mword 5))))) + then + "s8" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B1] : mword 5))))) + then + "s9" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B0] : mword 5))))) + then + "s10" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B1] : mword 5))))) + then + "s11" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : mword 5))))) + then + "t3" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B1] : mword 5))))) + then + "t4" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B1;B0] : mword 5))))) + then + "t5" + else "t6". + +Definition reg_name_backwards (arg_ : string) +: mword 5 := + + let p0_ := arg_ in + if ((generic_eq p0_ "zero")) then (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + else if ((generic_eq p0_ "ra")) then (vec_of_bits [B0;B0;B0;B0;B1] : mword 5) + else if ((generic_eq p0_ "sp")) then (vec_of_bits [B0;B0;B0;B1;B0] : mword 5) + else if ((generic_eq p0_ "gp")) then (vec_of_bits [B0;B0;B0;B1;B1] : mword 5) + else if ((generic_eq p0_ "tp")) then (vec_of_bits [B0;B0;B1;B0;B0] : mword 5) + else if ((generic_eq p0_ "t0")) then (vec_of_bits [B0;B0;B1;B0;B1] : mword 5) + else if ((generic_eq p0_ "t1")) then (vec_of_bits [B0;B0;B1;B1;B0] : mword 5) + else if ((generic_eq p0_ "t2")) then (vec_of_bits [B0;B0;B1;B1;B1] : mword 5) + else if ((generic_eq p0_ "fp")) then (vec_of_bits [B0;B1;B0;B0;B0] : mword 5) + else if ((generic_eq p0_ "s1")) then (vec_of_bits [B0;B1;B0;B0;B1] : mword 5) + else if ((generic_eq p0_ "a0")) then (vec_of_bits [B0;B1;B0;B1;B0] : mword 5) + else if ((generic_eq p0_ "a1")) then (vec_of_bits [B0;B1;B0;B1;B1] : mword 5) + else if ((generic_eq p0_ "a2")) then (vec_of_bits [B0;B1;B1;B0;B0] : mword 5) + else if ((generic_eq p0_ "a3")) then (vec_of_bits [B0;B1;B1;B0;B1] : mword 5) + else if ((generic_eq p0_ "a4")) then (vec_of_bits [B0;B1;B1;B1;B0] : mword 5) + else if ((generic_eq p0_ "a5")) then (vec_of_bits [B0;B1;B1;B1;B1] : mword 5) + else if ((generic_eq p0_ "a6")) then (vec_of_bits [B1;B0;B0;B0;B0] : mword 5) + else if ((generic_eq p0_ "a7")) then (vec_of_bits [B1;B0;B0;B0;B1] : mword 5) + else if ((generic_eq p0_ "s2")) then (vec_of_bits [B1;B0;B0;B1;B0] : mword 5) + else if ((generic_eq p0_ "s3")) then (vec_of_bits [B1;B0;B0;B1;B1] : mword 5) + else if ((generic_eq p0_ "s4")) then (vec_of_bits [B1;B0;B1;B0;B0] : mword 5) + else if ((generic_eq p0_ "s5")) then (vec_of_bits [B1;B0;B1;B0;B1] : mword 5) + else if ((generic_eq p0_ "s6")) then (vec_of_bits [B1;B0;B1;B1;B0] : mword 5) + else if ((generic_eq p0_ "s7")) then (vec_of_bits [B1;B0;B1;B1;B1] : mword 5) + else if ((generic_eq p0_ "s8")) then (vec_of_bits [B1;B1;B0;B0;B0] : mword 5) + else if ((generic_eq p0_ "s9")) then (vec_of_bits [B1;B1;B0;B0;B1] : mword 5) + else if ((generic_eq p0_ "s10")) then (vec_of_bits [B1;B1;B0;B1;B0] : mword 5) + else if ((generic_eq p0_ "s11")) then (vec_of_bits [B1;B1;B0;B1;B1] : mword 5) + else if ((generic_eq p0_ "t3")) then (vec_of_bits [B1;B1;B1;B0;B0] : mword 5) + else if ((generic_eq p0_ "t4")) then (vec_of_bits [B1;B1;B1;B0;B1] : mword 5) + else if ((generic_eq p0_ "t5")) then (vec_of_bits [B1;B1;B1;B1;B0] : mword 5) + else (vec_of_bits [B1;B1;B1;B1;B1] : mword 5). + +Definition reg_name_forwards_matches (arg_ : mword 5) +: bool := + + let b__0 := arg_ in + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B1;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B1;B1] : mword 5))))) + then + true + else false. + +Definition reg_name_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "zero")) then true + else if ((generic_eq p0_ "ra")) then true + else if ((generic_eq p0_ "sp")) then true + else if ((generic_eq p0_ "gp")) then true + else if ((generic_eq p0_ "tp")) then true + else if ((generic_eq p0_ "t0")) then true + else if ((generic_eq p0_ "t1")) then true + else if ((generic_eq p0_ "t2")) then true + else if ((generic_eq p0_ "fp")) then true + else if ((generic_eq p0_ "s1")) then true + else if ((generic_eq p0_ "a0")) then true + else if ((generic_eq p0_ "a1")) then true + else if ((generic_eq p0_ "a2")) then true + else if ((generic_eq p0_ "a3")) then true + else if ((generic_eq p0_ "a4")) then true + else if ((generic_eq p0_ "a5")) then true + else if ((generic_eq p0_ "a6")) then true + else if ((generic_eq p0_ "a7")) then true + else if ((generic_eq p0_ "s2")) then true + else if ((generic_eq p0_ "s3")) then true + else if ((generic_eq p0_ "s4")) then true + else if ((generic_eq p0_ "s5")) then true + else if ((generic_eq p0_ "s6")) then true + else if ((generic_eq p0_ "s7")) then true + else if ((generic_eq p0_ "s8")) then true + else if ((generic_eq p0_ "s9")) then true + else if ((generic_eq p0_ "s10")) then true + else if ((generic_eq p0_ "s11")) then true + else if ((generic_eq p0_ "t3")) then true + else if ((generic_eq p0_ "t4")) then true + else if ((generic_eq p0_ "t5")) then true + else if ((generic_eq p0_ "t6")) then true + else false. + +Definition _s124_ (_s125_ : string) +: option string := + + let _s126_ := _s125_ in + if ((string_startswith _s126_ "t6")) then + match (string_drop _s126_ (projT1 (string_length "t6"))) with | s_ => Some (s_) end + else None. + +Definition _s120_ (_s121_ : string) +: option string := + + let _s122_ := _s121_ in + if ((string_startswith _s122_ "t5")) then + match (string_drop _s122_ (projT1 (string_length "t5"))) with | s_ => Some (s_) end + else None. + +Definition _s116_ (_s117_ : string) +: option string := + + let _s118_ := _s117_ in + if ((string_startswith _s118_ "t4")) then + match (string_drop _s118_ (projT1 (string_length "t4"))) with | s_ => Some (s_) end + else None. + +Definition _s112_ (_s113_ : string) +: option string := + + let _s114_ := _s113_ in + if ((string_startswith _s114_ "t3")) then + match (string_drop _s114_ (projT1 (string_length "t3"))) with | s_ => Some (s_) end + else None. + +Definition _s108_ (_s109_ : string) +: option string := + + let _s110_ := _s109_ in + if ((string_startswith _s110_ "s11")) then + match (string_drop _s110_ (projT1 (string_length "s11"))) with | s_ => Some (s_) end + else None. + +Definition _s104_ (_s105_ : string) +: option string := + + let _s106_ := _s105_ in + if ((string_startswith _s106_ "s10")) then + match (string_drop _s106_ (projT1 (string_length "s10"))) with | s_ => Some (s_) end + else None. + +Definition _s100_ (_s101_ : string) +: option string := + + let _s102_ := _s101_ in + if ((string_startswith _s102_ "s9")) then + match (string_drop _s102_ (projT1 (string_length "s9"))) with | s_ => Some (s_) end + else None. + +Definition _s96_ (_s97_ : string) +: option string := + + let _s98_ := _s97_ in + if ((string_startswith _s98_ "s8")) then + match (string_drop _s98_ (projT1 (string_length "s8"))) with | s_ => Some (s_) end + else None. + +Definition _s92_ (_s93_ : string) +: option string := + + let _s94_ := _s93_ in + if ((string_startswith _s94_ "s7")) then + match (string_drop _s94_ (projT1 (string_length "s7"))) with | s_ => Some (s_) end + else None. + +Definition _s88_ (_s89_ : string) +: option string := + + let _s90_ := _s89_ in + if ((string_startswith _s90_ "s6")) then + match (string_drop _s90_ (projT1 (string_length "s6"))) with | s_ => Some (s_) end + else None. + +Definition _s84_ (_s85_ : string) +: option string := + + let _s86_ := _s85_ in + if ((string_startswith _s86_ "s5")) then + match (string_drop _s86_ (projT1 (string_length "s5"))) with | s_ => Some (s_) end + else None. + +Definition _s80_ (_s81_ : string) +: option string := + + let _s82_ := _s81_ in + if ((string_startswith _s82_ "s4")) then + match (string_drop _s82_ (projT1 (string_length "s4"))) with | s_ => Some (s_) end + else None. + +Definition _s76_ (_s77_ : string) +: option string := + + let _s78_ := _s77_ in + if ((string_startswith _s78_ "s3")) then + match (string_drop _s78_ (projT1 (string_length "s3"))) with | s_ => Some (s_) end + else None. + +Definition _s72_ (_s73_ : string) +: option string := + + let _s74_ := _s73_ in + if ((string_startswith _s74_ "s2")) then + match (string_drop _s74_ (projT1 (string_length "s2"))) with | s_ => Some (s_) end + else None. + +Definition _s68_ (_s69_ : string) +: option string := + + let _s70_ := _s69_ in + if ((string_startswith _s70_ "a7")) then + match (string_drop _s70_ (projT1 (string_length "a7"))) with | s_ => Some (s_) end + else None. + +Definition _s64_ (_s65_ : string) +: option string := + + let _s66_ := _s65_ in + if ((string_startswith _s66_ "a6")) then + match (string_drop _s66_ (projT1 (string_length "a6"))) with | s_ => Some (s_) end + else None. + +Definition _s60_ (_s61_ : string) +: option string := + + let _s62_ := _s61_ in + if ((string_startswith _s62_ "a5")) then + match (string_drop _s62_ (projT1 (string_length "a5"))) with | s_ => Some (s_) end + else None. + +Definition _s56_ (_s57_ : string) +: option string := + + let _s58_ := _s57_ in + if ((string_startswith _s58_ "a4")) then + match (string_drop _s58_ (projT1 (string_length "a4"))) with | s_ => Some (s_) end + else None. + +Definition _s52_ (_s53_ : string) +: option string := + + let _s54_ := _s53_ in + if ((string_startswith _s54_ "a3")) then + match (string_drop _s54_ (projT1 (string_length "a3"))) with | s_ => Some (s_) end + else None. + +Definition _s48_ (_s49_ : string) +: option string := + + let _s50_ := _s49_ in + if ((string_startswith _s50_ "a2")) then + match (string_drop _s50_ (projT1 (string_length "a2"))) with | s_ => Some (s_) end + else None. + +Definition _s44_ (_s45_ : string) +: option string := + + let _s46_ := _s45_ in + if ((string_startswith _s46_ "a1")) then + match (string_drop _s46_ (projT1 (string_length "a1"))) with | s_ => Some (s_) end + else None. + +Definition _s40_ (_s41_ : string) +: option string := + + let _s42_ := _s41_ in + if ((string_startswith _s42_ "a0")) then + match (string_drop _s42_ (projT1 (string_length "a0"))) with | s_ => Some (s_) end + else None. + +Definition _s36_ (_s37_ : string) +: option string := + + let _s38_ := _s37_ in + if ((string_startswith _s38_ "s1")) then + match (string_drop _s38_ (projT1 (string_length "s1"))) with | s_ => Some (s_) end + else None. + +Definition _s32_ (_s33_ : string) +: option string := + + let _s34_ := _s33_ in + if ((string_startswith _s34_ "fp")) then + match (string_drop _s34_ (projT1 (string_length "fp"))) with | s_ => Some (s_) end + else None. + +Definition _s28_ (_s29_ : string) +: option string := + + let _s30_ := _s29_ in + if ((string_startswith _s30_ "t2")) then + match (string_drop _s30_ (projT1 (string_length "t2"))) with | s_ => Some (s_) end + else None. + +Definition _s24_ (_s25_ : string) +: option string := + + let _s26_ := _s25_ in + if ((string_startswith _s26_ "t1")) then + match (string_drop _s26_ (projT1 (string_length "t1"))) with | s_ => Some (s_) end + else None. + +Definition _s20_ (_s21_ : string) +: option string := + + let _s22_ := _s21_ in + if ((string_startswith _s22_ "t0")) then + match (string_drop _s22_ (projT1 (string_length "t0"))) with | s_ => Some (s_) end + else None. + +Definition _s16_ (_s17_ : string) +: option string := + + let _s18_ := _s17_ in + if ((string_startswith _s18_ "tp")) then + match (string_drop _s18_ (projT1 (string_length "tp"))) with | s_ => Some (s_) end + else None. + +Definition _s12_ (_s13_ : string) +: option string := + + let _s14_ := _s13_ in + if ((string_startswith _s14_ "gp")) then + match (string_drop _s14_ (projT1 (string_length "gp"))) with | s_ => Some (s_) end + else None. + +Definition _s8_ (_s9_ : string) +: option string := + + let _s10_ := _s9_ in + if ((string_startswith _s10_ "sp")) then + match (string_drop _s10_ (projT1 (string_length "sp"))) with | s_ => Some (s_) end + else None. + +Definition _s4_ (_s5_ : string) +: option string := + + let _s6_ := _s5_ in + if ((string_startswith _s6_ "ra")) then + match (string_drop _s6_ (projT1 (string_length "ra"))) with | s_ => Some (s_) end + else None. + +Definition _s0_ (_s1_ : string) +: option string := + + let _s2_ := _s1_ in + if ((string_startswith _s2_ "zero")) then + match (string_drop _s2_ (projT1 (string_length "zero"))) with | s_ => Some (s_) end + else None. + +Definition reg_name_matches_prefix (arg_ : string) +: M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) := + + let _s3_ := arg_ in + (if ((match (_s0_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s0_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s4_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s4_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s8_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s8_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s12_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s12_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s16_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s16_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B0;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s20_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s20_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B0;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s24_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s24_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s28_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s28_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s32_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s32_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B0;B0;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s36_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s36_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B0;B0;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s40_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s40_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B0;B1;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s44_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s44_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B0;B1;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s48_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s48_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B1;B0;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s52_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s52_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B1;B0;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s56_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s56_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B1;B1;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s60_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s60_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B1;B1;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s64_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s64_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B0;B0;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s68_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s68_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B0;B0;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s72_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s72_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B0;B1;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s76_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s76_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B0;B1;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s80_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s80_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B1;B0;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s84_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s84_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B1;B0;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s88_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s88_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B1;B1;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s92_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s92_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B1;B1;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s96_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s96_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0;B0;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s100_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s100_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0;B0;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s104_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s104_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0;B1;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s108_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s108_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0;B1;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s112_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s112_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B1;B0;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s116_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s116_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B1;B0;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s120_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s120_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B1;B1;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s124_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s124_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B1;B1;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))). + +Definition creg_name_forwards (arg_ : mword 3) +: string := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then "s0" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then "s1" + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then "a0" + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then "a1" + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then "a2" + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then "a3" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then "a4" + else "a5". + +Definition creg_name_backwards (arg_ : string) +: mword 3 := + + let p0_ := arg_ in + if ((generic_eq p0_ "s0")) then (vec_of_bits [B0;B0;B0] : mword 3) + else if ((generic_eq p0_ "s1")) then (vec_of_bits [B0;B0;B1] : mword 3) + else if ((generic_eq p0_ "a0")) then (vec_of_bits [B0;B1;B0] : mword 3) + else if ((generic_eq p0_ "a1")) then (vec_of_bits [B0;B1;B1] : mword 3) + else if ((generic_eq p0_ "a2")) then (vec_of_bits [B1;B0;B0] : mword 3) + else if ((generic_eq p0_ "a3")) then (vec_of_bits [B1;B0;B1] : mword 3) + else if ((generic_eq p0_ "a4")) then (vec_of_bits [B1;B1;B0] : mword 3) + else (vec_of_bits [B1;B1;B1] : mword 3). + +Definition creg_name_forwards_matches (arg_ : mword 3) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1] : mword 3))) then true + else false. + +Definition creg_name_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "s0")) then true + else if ((generic_eq p0_ "s1")) then true + else if ((generic_eq p0_ "a0")) then true + else if ((generic_eq p0_ "a1")) then true + else if ((generic_eq p0_ "a2")) then true + else if ((generic_eq p0_ "a3")) then true + else if ((generic_eq p0_ "a4")) then true + else if ((generic_eq p0_ "a5")) then true + else false. + +Definition _s156_ (_s157_ : string) +: option string := + + let _s158_ := _s157_ in + if ((string_startswith _s158_ "a5")) then + match (string_drop _s158_ (projT1 (string_length "a5"))) with | s_ => Some (s_) end + else None. + +Definition _s152_ (_s153_ : string) +: option string := + + let _s154_ := _s153_ in + if ((string_startswith _s154_ "a4")) then + match (string_drop _s154_ (projT1 (string_length "a4"))) with | s_ => Some (s_) end + else None. + +Definition _s148_ (_s149_ : string) +: option string := + + let _s150_ := _s149_ in + if ((string_startswith _s150_ "a3")) then + match (string_drop _s150_ (projT1 (string_length "a3"))) with | s_ => Some (s_) end + else None. + +Definition _s144_ (_s145_ : string) +: option string := + + let _s146_ := _s145_ in + if ((string_startswith _s146_ "a2")) then + match (string_drop _s146_ (projT1 (string_length "a2"))) with | s_ => Some (s_) end + else None. + +Definition _s140_ (_s141_ : string) +: option string := + + let _s142_ := _s141_ in + if ((string_startswith _s142_ "a1")) then + match (string_drop _s142_ (projT1 (string_length "a1"))) with | s_ => Some (s_) end + else None. + +Definition _s136_ (_s137_ : string) +: option string := + + let _s138_ := _s137_ in + if ((string_startswith _s138_ "a0")) then + match (string_drop _s138_ (projT1 (string_length "a0"))) with | s_ => Some (s_) end + else None. + +Definition _s132_ (_s133_ : string) +: option string := + + let _s134_ := _s133_ in + if ((string_startswith _s134_ "s1")) then + match (string_drop _s134_ (projT1 (string_length "s1"))) with | s_ => Some (s_) end + else None. + +Definition _s128_ (_s129_ : string) +: option string := + + let _s130_ := _s129_ in + if ((string_startswith _s130_ "s0")) then + match (string_drop _s130_ (projT1 (string_length "s0"))) with | s_ => Some (s_) end + else None. + +Definition creg_name_matches_prefix (arg_ : string) +: M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) := + + let _s131_ := arg_ in + (if ((match (_s128_ _s131_) with | Some (s_) => true | _ => false end)) then + (match (_s128_ _s131_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0] : mword 3), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s132_ _s131_) with | Some (s_) => true | _ => false end)) then + (match (_s132_ _s131_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1] : mword 3), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s136_ _s131_) with | Some (s_) => true | _ => false end)) then + (match (_s136_ _s131_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B0] : mword 3), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s140_ _s131_) with | Some (s_) => true | _ => false end)) then + (match (_s140_ _s131_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B1] : mword 3), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s144_ _s131_) with | Some (s_) => true | _ => false end)) then + (match (_s144_ _s131_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B0] : mword 3), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s148_ _s131_) with | Some (s_) => true | _ => false end)) then + (match (_s148_ _s131_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B1] : mword 3), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s152_ _s131_) with | Some (s_) => true | _ => false end)) then + (match (_s152_ _s131_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0] : mword 3), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s156_ _s131_) with | Some (s_) => true | _ => false end)) then + (match (_s156_ _s131_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B1] : mword 3), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((mword 3 * {n : Z & ArithFact (n >= 0)})))) + : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))). + +Definition sep_forwards (arg_ : unit) +: string := + + match arg_ with + | tt => + string_append (opt_spc_forwards tt) + (string_append "," (string_append (def_spc_forwards tt) "")) + end. + +Definition _s160_ (_s161_ : string) +: M (option unit) := + + (match _s161_ with + | _s162_ => + (opt_spc_matches_prefix _s162_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s163_ _)) => + let _s164_ := string_drop _s162_ _s163_ in + (if ((string_startswith _s164_ ",")) then + (match (string_drop _s164_ (projT1 (string_length ","))) with + | _s165_ => + (def_spc_matches_prefix _s165_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__1 with + | Some (tt,(existT _ _s166_ _)) => + let p0_ := string_drop _s165_ _s166_ in + if ((generic_eq p0_ "")) then Some (tt) + else None + | _ => None + end) + : option unit) + end) + : M (option unit) + else returnm (None : option unit)) + : M (option unit) + | _ => returnm (None : option unit) + end) + : M (option unit) + end) + : M (option unit). + +Definition sep_backwards (arg_ : string) +: M (unit) := + + let _s167_ := arg_ in + (_s160_ _s167_) >>= fun w__0 : option unit => + (match w__0 with | Some (tt) => returnm (tt : unit) | _ => exit tt : M (unit) end) + : M (unit). + +Definition sep_forwards_matches (arg_ : unit) : bool := match arg_ with | tt => true end. + +Definition _s168_ (_s169_ : string) +: M (option unit) := + + (match _s169_ with + | _s170_ => + (opt_spc_matches_prefix _s170_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s171_ _)) => + let _s172_ := string_drop _s170_ _s171_ in + (if ((string_startswith _s172_ ",")) then + (match (string_drop _s172_ (projT1 (string_length ","))) with + | _s173_ => + (def_spc_matches_prefix _s173_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__1 with + | Some (tt,(existT _ _s174_ _)) => + let p0_ := string_drop _s173_ _s174_ in + if ((generic_eq p0_ "")) then Some (tt) + else None + | _ => None + end) + : option unit) + end) + : M (option unit) + else returnm (None : option unit)) + : M (option unit) + | _ => returnm (None : option unit) + end) + : M (option unit) + end) + : M (option unit). + +Definition sep_backwards_matches (arg_ : string) +: M (bool) := + + let _s175_ := arg_ in + (_s168_ _s175_) >>= fun w__0 : option unit => + (if ((match w__0 with | Some (tt) => true | _ => false end)) then + (_s168_ _s175_) >>= fun w__1 : option unit => + (match w__1 with | Some (tt) => returnm (true : bool) | _ => exit tt : M (bool) end) + : M (bool) + else returnm (false : bool)) + : M (bool). + +Definition _s176_ (_s177_ : string) +: M (option string) := + + (match _s177_ with + | _s178_ => + (opt_spc_matches_prefix _s178_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s179_ _)) => + let _s180_ := string_drop _s178_ _s179_ in + (if ((string_startswith _s180_ ",")) then + (match (string_drop _s180_ (projT1 (string_length ","))) with + | _s181_ => + (def_spc_matches_prefix _s181_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__1 with + | Some (tt,(existT _ _s182_ _)) => + match (string_drop _s181_ _s182_) with | s_ => Some (s_) end + | _ => None + end) + : option string) + end) + : M (option string) + else returnm (None : option string)) + : M (option string) + | _ => returnm (None : option string) + end) + : M (option string) + end) + : M (option string). + +Definition sep_matches_prefix (arg_ : string) +: M (option ((unit * {n : Z & ArithFact (n >= 0)}))) := + + let _s183_ := arg_ in + (_s176_ _s183_) >>= fun w__0 : option string => + (if ((match w__0 with | Some (s_) => true | _ => false end)) then + (_s176_ _s183_) >>= fun w__1 : option string => + (match w__1 with + | Some (s_) => + returnm ((Some + ((tt, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((unit * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((unit * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((unit * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((unit * {n : Z & ArithFact (n >= 0)})))) + : M (option ((unit * {n : Z & ArithFact (n >= 0)}))). + +Definition bool_bits_forwards (arg_ : bool) +: mword 1 := + + match arg_ with + | true => (vec_of_bits [B1] : mword 1) + | false => (vec_of_bits [B0] : mword 1) + end. + +Definition bool_bits_backwards (arg_ : mword 1) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true + else false. + +Definition bool_bits_forwards_matches (arg_ : bool) +: bool := + + match arg_ with | true => true | false => true end. + +Definition bool_bits_backwards_matches (arg_ : mword 1) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true + else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true + else false. + +Definition bool_not_bits_forwards (arg_ : bool) +: mword 1 := + + match arg_ with + | true => (vec_of_bits [B0] : mword 1) + | false => (vec_of_bits [B1] : mword 1) + end. + +Definition bool_not_bits_backwards (arg_ : mword 1) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true + else false. + +Definition bool_not_bits_forwards_matches (arg_ : bool) +: bool := + + match arg_ with | true => true | false => true end. + +Definition bool_not_bits_backwards_matches (arg_ : mword 1) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true + else if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true + else false. + +Definition size_bits_forwards (arg_ : word_width) +: mword 2 := + + match arg_ with + | BYTE => (vec_of_bits [B0;B0] : mword 2) + | HALF => (vec_of_bits [B0;B1] : mword 2) + | WORD => (vec_of_bits [B1;B0] : mword 2) + | DOUBLE => (vec_of_bits [B1;B1] : mword 2) + end. + +Definition size_bits_backwards (arg_ : mword 2) +: word_width := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then BYTE + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then HALF + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then WORD + else DOUBLE. + +Definition size_bits_forwards_matches (arg_ : word_width) +: bool := + + match arg_ with | BYTE => true | HALF => true | WORD => true | DOUBLE => true end. + +Definition size_bits_backwards_matches (arg_ : mword 2) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then true + else false. + +Definition size_mnemonic_forwards (arg_ : word_width) +: string := + + match arg_ with | BYTE => "b" | HALF => "h" | WORD => "w" | DOUBLE => "d" end. + +Definition size_mnemonic_backwards (arg_ : string) +: word_width := + + let p0_ := arg_ in + if ((generic_eq p0_ "b")) then BYTE + else if ((generic_eq p0_ "h")) then HALF + else if ((generic_eq p0_ "w")) then WORD + else DOUBLE. + +Definition size_mnemonic_forwards_matches (arg_ : word_width) +: bool := + + match arg_ with | BYTE => true | HALF => true | WORD => true | DOUBLE => true end. + +Definition size_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "b")) then true + else if ((generic_eq p0_ "h")) then true + else if ((generic_eq p0_ "w")) then true + else if ((generic_eq p0_ "d")) then true + else false. + +Definition _s196_ (_s197_ : string) +: option string := + + let _s198_ := _s197_ in + if ((string_startswith _s198_ "d")) then + match (string_drop _s198_ (projT1 (string_length "d"))) with | s_ => Some (s_) end + else None. + +Definition _s192_ (_s193_ : string) +: option string := + + let _s194_ := _s193_ in + if ((string_startswith _s194_ "w")) then + match (string_drop _s194_ (projT1 (string_length "w"))) with | s_ => Some (s_) end + else None. + +Definition _s188_ (_s189_ : string) +: option string := + + let _s190_ := _s189_ in + if ((string_startswith _s190_ "h")) then + match (string_drop _s190_ (projT1 (string_length "h"))) with | s_ => Some (s_) end + else None. + +Definition _s184_ (_s185_ : string) +: option string := + + let _s186_ := _s185_ in + if ((string_startswith _s186_ "b")) then + match (string_drop _s186_ (projT1 (string_length "b"))) with | s_ => Some (s_) end + else None. + +Definition size_mnemonic_matches_prefix (arg_ : string) +: M (option ((word_width * {n : Z & ArithFact (n >= 0)}))) := + + let _s187_ := arg_ in + (if ((match (_s184_ _s187_) with | Some (s_) => true | _ => false end)) then + (match (_s184_ _s187_) with + | Some (s_) => + returnm ((Some + ((BYTE, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((word_width * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((word_width * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((word_width * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s188_ _s187_) with | Some (s_) => true | _ => false end)) then + (match (_s188_ _s187_) with + | Some (s_) => + returnm ((Some + ((HALF, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((word_width * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((word_width * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((word_width * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s192_ _s187_) with | Some (s_) => true | _ => false end)) then + (match (_s192_ _s187_) with + | Some (s_) => + returnm ((Some + ((WORD, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((word_width * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((word_width * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((word_width * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s196_ _s187_) with | Some (s_) => true | _ => false end)) then + (match (_s196_ _s187_) with + | Some (s_) => + returnm ((Some + ((DOUBLE, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((word_width * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((word_width * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((word_width * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((word_width * {n : Z & ArithFact (n >= 0)})))) + : M (option ((word_width * {n : Z & ArithFact (n >= 0)}))). + +Definition Mk_Misa (v : mword 64) : Misa := {| Misa_Misa_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_Misa_bits (v : Misa) : mword 64 := subrange_vec_dec v.(Misa_Misa_chunk_0) 63 0. + +Definition _set_Misa_bits (r_ref : register_ref regstate register_value Misa) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_bits (v : Misa) (x : mword 64) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_Misa_MXL (v : Misa) : mword 2 := subrange_vec_dec v.(Misa_Misa_chunk_0) 63 62. + +Definition _set_Misa_MXL (r_ref : register_ref regstate register_value Misa) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 63 62 (subrange_vec_dec v 1 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_MXL (v : Misa) (x : mword 2) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 63 62 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_Misa_Z (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 25 25. + +Definition _set_Misa_Z (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 25 25 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_Z (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 25 25 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_Y (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 24 24. + +Definition _set_Misa_Y (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 24 24 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_Y (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 24 24 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_X (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 23 23. + +Definition _set_Misa_X (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 23 23 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_X (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 23 23 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_W (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 22 22. + +Definition _set_Misa_W (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_W (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_V (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 21 21. + +Definition _set_Misa_V (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 21 21 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_V (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 21 21 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_U (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 20 20. + +Definition _set_Misa_U (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 20 20 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_U (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 20 20 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_T (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 19 19. + +Definition _set_Misa_T (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 19 19 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_T (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 19 19 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_S (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 18 18. + +Definition _set_Misa_S (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 18 18 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_S (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 18 18 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_R (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 17 17. + +Definition _set_Misa_R (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 17 17 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_R (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 17 17 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_Q (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 16 16. + +Definition _set_Misa_Q (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 16 16 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_Q (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 16 16 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_P (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 15 15. + +Definition _set_Misa_P (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 15 15 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_P (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 15 15 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_O (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 14 14. + +Definition _set_Misa_O (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 14 14 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_O (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 14 14 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_N (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 13 13. + +Definition _set_Misa_N (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 13 13 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_N (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 13 13 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_M (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 12 12. + +Definition _set_Misa_M (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 12 12 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_M (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 12 12 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_L (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 11 11. + +Definition _set_Misa_L (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 11 11 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_L (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 11 11 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_K (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 10 10. + +Definition _set_Misa_K (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 10 10 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_K (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 10 10 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_J (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 9 9. + +Definition _set_Misa_J (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 9 9 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_J (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 9 9 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_I (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 8 8. + +Definition _set_Misa_I (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_I (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_H (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 7 7. + +Definition _set_Misa_H (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_H (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_G (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 6 6. + +Definition _set_Misa_G (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_G (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_F (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 5 5. + +Definition _set_Misa_F (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_F (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_E (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 4 4. + +Definition _set_Misa_E (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_E (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_D (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 3 3. + +Definition _set_Misa_D (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_D (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_C (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 2 2. + +Definition _set_Misa_C (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_C (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_B (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 1 1. + +Definition _set_Misa_B (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_B (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_A (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 0 0. + +Definition _set_Misa_A (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_A (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition legalize_misa (m : Misa) (v : mword 64) +: M (Misa) := + + let v := Mk_Misa v in + (and_boolM (returnm ((eq_vec (_get_Misa_C v) ((bool_to_bits false) : mword 1)) : bool)) + (((read_reg nextPC_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + (bit_to_bool (access_vec_dec w__0 1)) >>= fun w__1 : bool => + returnm ((Bool.eqb (w__1 : bool) true) + : bool))) >>= fun w__2 : bool => + returnm ((if (w__2) then m + else _update_Misa_C m (_get_Misa_C v)) + : Misa). + +Definition Mk_Mstatus (v : mword 64) +: Mstatus := + + {| Mstatus_Mstatus_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_Mstatus_bits (v : Mstatus) +: mword 64 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 63 0. + +Definition _set_Mstatus_bits (r_ref : register_ref regstate register_value Mstatus) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_bits (v : Mstatus) (x : mword 64) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_Mstatus_SD (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 63 63. + +Definition _set_Mstatus_SD (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 63 63 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_SD (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 63 63 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_SXL (v : Mstatus) +: mword 2 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 35 34. + +Definition _set_Mstatus_SXL (r_ref : register_ref regstate register_value Mstatus) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 35 34 (subrange_vec_dec v 1 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_SXL (v : Mstatus) (x : mword 2) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 35 34 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_Mstatus_UXL (v : Mstatus) +: mword 2 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 33 32. + +Definition _set_Mstatus_UXL (r_ref : register_ref regstate register_value Mstatus) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 33 32 (subrange_vec_dec v 1 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_UXL (v : Mstatus) (x : mword 2) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 33 32 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_Mstatus_TSR (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 22 22. + +Definition _set_Mstatus_TSR (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_TSR (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_TW (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 21 21. + +Definition _set_Mstatus_TW (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 21 21 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_TW (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 21 21 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_TVM (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 20 20. + +Definition _set_Mstatus_TVM (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 20 20 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_TVM (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 20 20 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_MXR (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 19 19. + +Definition _set_Mstatus_MXR (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 19 19 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_MXR (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 19 19 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_SUM (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 18 18. + +Definition _set_Mstatus_SUM (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 18 18 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_SUM (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 18 18 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_MPRV (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 17 17. + +Definition _set_Mstatus_MPRV (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 17 17 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_MPRV (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 17 17 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_XS (v : Mstatus) +: mword 2 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 16 15. + +Definition _set_Mstatus_XS (r_ref : register_ref regstate register_value Mstatus) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 16 15 (subrange_vec_dec v 1 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_XS (v : Mstatus) (x : mword 2) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 16 15 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_Mstatus_FS (v : Mstatus) +: mword 2 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 14 13. + +Definition _set_Mstatus_FS (r_ref : register_ref regstate register_value Mstatus) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 14 13 (subrange_vec_dec v 1 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_FS (v : Mstatus) (x : mword 2) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 14 13 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_Mstatus_MPP (v : Mstatus) +: mword 2 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 12 11. + +Definition _set_Mstatus_MPP (r_ref : register_ref regstate register_value Mstatus) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 12 11 (subrange_vec_dec v 1 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_MPP (v : Mstatus) (x : mword 2) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 12 11 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_Mstatus_SPP (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 8 8. + +Definition _set_Mstatus_SPP (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_SPP (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_MPIE (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 7 7. + +Definition _set_Mstatus_MPIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_MPIE (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_SPIE (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 5 5. + +Definition _set_Mstatus_SPIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_SPIE (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_UPIE (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 4 4. + +Definition _set_Mstatus_UPIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_UPIE (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_MIE (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 3 3. + +Definition _set_Mstatus_MIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_MIE (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_SIE (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 1 1. + +Definition _set_Mstatus_SIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_SIE (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_UIE (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 0 0. + +Definition _set_Mstatus_UIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_UIE (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition legalize_mstatus (o : Mstatus) (v : mword 64) +: Mstatus := + + let m : Mstatus := Mk_Mstatus v in + let m := _update_Mstatus_XS m (extStatus_to_bits Off) in + let m := _update_Mstatus_FS m (extStatus_to_bits Off) in + let m := + _update_Mstatus_SD m + ((bool_to_bits + (orb + (eq_vec (extStatus_to_bits (extStatus_of_bits (_get_Mstatus_FS m))) + ((extStatus_to_bits Dirty) + : mword 2)) + (eq_vec (extStatus_to_bits (extStatus_of_bits (_get_Mstatus_XS m))) + ((extStatus_to_bits Dirty) + : mword 2)))) + : mword 1) in + let m := _update_Mstatus_SXL m (_get_Mstatus_SXL o) in + let m := _update_Mstatus_UXL m (_get_Mstatus_UXL o) in + let m := _update_Mstatus_UPIE m ((bool_to_bits false) : mword 1) in + _update_Mstatus_UIE m ((bool_to_bits false) : mword 1). + +Definition cur_Architecture '(tt : unit) +: M (Architecture) := + + read_reg cur_privilege_ref >>= fun w__0 : Privilege => + (match w__0 with + | Machine => read_reg misa_ref >>= fun w__1 : Misa => returnm ((_get_Misa_MXL w__1) : mword 2) + | Supervisor => + read_reg mstatus_ref >>= fun w__2 : Mstatus => returnm ((_get_Mstatus_SXL w__2) : mword 2) + | User => + read_reg mstatus_ref >>= fun w__3 : Mstatus => returnm ((_get_Mstatus_UXL w__3) : mword 2) + end) >>= fun a : arch_xlen => + (match (architecture a) with + | Some (a) => returnm (a : Architecture) + | None => (internal_error "Invalid current architecture") : M (Architecture) + end) + : M (Architecture). + +Definition in32BitMode '(tt : unit) +: M (bool) := + + (cur_Architecture tt) >>= fun w__0 : Architecture => returnm ((generic_eq w__0 RV32) : bool). + +Definition haveAtomics '(tt : unit) +: M (bool) := + + read_reg misa_ref >>= fun w__0 : Misa => + returnm ((eq_vec (_get_Misa_A w__0) ((bool_to_bits true) : mword 1)) + : bool). + +Definition haveRVC '(tt : unit) +: M (bool) := + + read_reg misa_ref >>= fun w__0 : Misa => + returnm ((eq_vec (_get_Misa_C w__0) ((bool_to_bits true) : mword 1)) + : bool). + +Definition haveMulDiv '(tt : unit) +: M (bool) := + + read_reg misa_ref >>= fun w__0 : Misa => + returnm ((eq_vec (_get_Misa_M w__0) ((bool_to_bits true) : mword 1)) + : bool). + +Definition haveFP '(tt : unit) +: M (bool) := + + (or_boolM + (read_reg misa_ref >>= fun w__0 : Misa => + returnm ((eq_vec (_get_Misa_F w__0) ((bool_to_bits true) : mword 1)) + : bool)) + (read_reg misa_ref >>= fun w__1 : Misa => + returnm ((eq_vec (_get_Misa_D w__1) ((bool_to_bits true) : mword 1)) + : bool))) + : M (bool). + +Definition Mk_Minterrupts (v : mword 64) +: Minterrupts := + + {| Minterrupts_Minterrupts_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_Minterrupts_bits (v : Minterrupts) +: mword 64 := + + subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 63 0. + +Definition _set_Minterrupts_bits +(r_ref : register_ref regstate register_value Minterrupts) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : Minterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Minterrupts_bits (v : Minterrupts) (x : mword 64) +: Minterrupts := + + {[ v with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_Minterrupts_MEI (v : Minterrupts) +: mword 1 := + + subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 11 11. + +Definition _set_Minterrupts_MEI +(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 11 11 (subrange_vec_dec v 0 0)) ]} + : Minterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Minterrupts_MEI (v : Minterrupts) (x : mword 1) +: Minterrupts := + + {[ v with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 11 11 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Minterrupts_SEI (v : Minterrupts) +: mword 1 := + + subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 9 9. + +Definition _set_Minterrupts_SEI +(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 9 9 (subrange_vec_dec v 0 0)) ]} + : Minterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Minterrupts_SEI (v : Minterrupts) (x : mword 1) +: Minterrupts := + + {[ v with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 9 9 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Minterrupts_UEI (v : Minterrupts) +: mword 1 := + + subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 8 8. + +Definition _set_Minterrupts_UEI +(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} + : Minterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Minterrupts_UEI (v : Minterrupts) (x : mword 1) +: Minterrupts := + + {[ v with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Minterrupts_MTI (v : Minterrupts) +: mword 1 := + + subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 7 7. + +Definition _set_Minterrupts_MTI +(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} + : Minterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Minterrupts_MTI (v : Minterrupts) (x : mword 1) +: Minterrupts := + + {[ v with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Minterrupts_STI (v : Minterrupts) +: mword 1 := + + subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 5 5. + +Definition _set_Minterrupts_STI +(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} + : Minterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Minterrupts_STI (v : Minterrupts) (x : mword 1) +: Minterrupts := + + {[ v with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Minterrupts_UTI (v : Minterrupts) +: mword 1 := + + subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 4 4. + +Definition _set_Minterrupts_UTI +(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} + : Minterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Minterrupts_UTI (v : Minterrupts) (x : mword 1) +: Minterrupts := + + {[ v with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Minterrupts_MSI (v : Minterrupts) +: mword 1 := + + subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 3 3. + +Definition _set_Minterrupts_MSI +(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]} + : Minterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Minterrupts_MSI (v : Minterrupts) (x : mword 1) +: Minterrupts := + + {[ v with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Minterrupts_SSI (v : Minterrupts) +: mword 1 := + + subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 1 1. + +Definition _set_Minterrupts_SSI +(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : Minterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Minterrupts_SSI (v : Minterrupts) (x : mword 1) +: Minterrupts := + + {[ v with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Minterrupts_USI (v : Minterrupts) +: mword 1 := + + subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 0 0. + +Definition _set_Minterrupts_USI +(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : Minterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Minterrupts_USI (v : Minterrupts) (x : mword 1) +: Minterrupts := + + {[ v with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition legalize_mip (o : Minterrupts) (v : mword 64) +: Minterrupts := + + let v := Mk_Minterrupts v in + let m := _update_Minterrupts_SEI o (_get_Minterrupts_SEI v) in + let m := _update_Minterrupts_STI m (_get_Minterrupts_STI v) in + _update_Minterrupts_SSI m (_get_Minterrupts_SSI v). + +Definition legalize_mie (o : Minterrupts) (v : mword 64) +: Minterrupts := + + let v := Mk_Minterrupts v in + let m := _update_Minterrupts_MEI o (_get_Minterrupts_MEI v) in + let m := _update_Minterrupts_MTI m (_get_Minterrupts_MTI v) in + let m := _update_Minterrupts_MSI m (_get_Minterrupts_MSI v) in + let m := _update_Minterrupts_SEI m (_get_Minterrupts_SEI v) in + let m := _update_Minterrupts_STI m (_get_Minterrupts_STI v) in + _update_Minterrupts_SSI m (_get_Minterrupts_SSI v). + +Definition legalize_mideleg (o : Minterrupts) (v : mword 64) +: Minterrupts := + + let m := Mk_Minterrupts v in + let m := _update_Minterrupts_MEI m ((bool_to_bits false) : mword 1) in + let m := _update_Minterrupts_MTI m ((bool_to_bits false) : mword 1) in + _update_Minterrupts_MSI m ((bool_to_bits false) : mword 1). + +Definition Mk_Medeleg (v : mword 64) +: Medeleg := + + {| Medeleg_Medeleg_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_Medeleg_bits (v : Medeleg) +: mword 64 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 63 0. + +Definition _set_Medeleg_bits (r_ref : register_ref regstate register_value Medeleg) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_bits (v : Medeleg) (x : mword 64) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_Medeleg_SAMO_Page_Fault (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 15 15. + +Definition _set_Medeleg_SAMO_Page_Fault +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 15 15 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_SAMO_Page_Fault (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 15 15 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_Load_Page_Fault (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 13 13. + +Definition _set_Medeleg_Load_Page_Fault +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 13 13 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_Load_Page_Fault (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 13 13 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_Fetch_Page_Fault (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 12 12. + +Definition _set_Medeleg_Fetch_Page_Fault +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 12 12 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_Fetch_Page_Fault (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 12 12 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_MEnvCall (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 10 10. + +Definition _set_Medeleg_MEnvCall +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 10 10 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_MEnvCall (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 10 10 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_SEnvCall (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 9 9. + +Definition _set_Medeleg_SEnvCall +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 9 9 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_SEnvCall (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 9 9 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_UEnvCall (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 8 8. + +Definition _set_Medeleg_UEnvCall +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_UEnvCall (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_SAMO_Access_Fault (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 7 7. + +Definition _set_Medeleg_SAMO_Access_Fault +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_SAMO_Access_Fault (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_SAMO_Addr_Align (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 6 6. + +Definition _set_Medeleg_SAMO_Addr_Align +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_SAMO_Addr_Align (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_Load_Access_Fault (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 5 5. + +Definition _set_Medeleg_Load_Access_Fault +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_Load_Access_Fault (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_Load_Addr_Align (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 4 4. + +Definition _set_Medeleg_Load_Addr_Align +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_Load_Addr_Align (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_Breakpoint (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 3 3. + +Definition _set_Medeleg_Breakpoint +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_Breakpoint (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_Illegal_Instr (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 2 2. + +Definition _set_Medeleg_Illegal_Instr +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_Illegal_Instr (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_Fetch_Access_Fault (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 1 1. + +Definition _set_Medeleg_Fetch_Access_Fault +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_Fetch_Access_Fault (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_Fetch_Addr_Align (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 0 0. + +Definition _set_Medeleg_Fetch_Addr_Align +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_Fetch_Addr_Align (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition legalize_medeleg (o : Medeleg) (v : mword 64) +: Medeleg := + + let m := Mk_Medeleg v in + _update_Medeleg_MEnvCall m ((bool_to_bits false) : mword 1). + +Definition Mk_Mtvec (v : mword 64) +: Mtvec := + + {| Mtvec_Mtvec_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_Mtvec_bits (v : Mtvec) +: mword 64 := + + subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 63 0. + +Definition _set_Mtvec_bits (r_ref : register_ref regstate register_value Mtvec) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mtvec_Mtvec_chunk_0 := + (update_subrange_vec_dec r.(Mtvec_Mtvec_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : Mtvec in + write_reg r_ref r + : M (unit). + +Definition _update_Mtvec_bits (v : Mtvec) (x : mword 64) +: Mtvec := + + {[ v with + Mtvec_Mtvec_chunk_0 := + (update_subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_Mtvec_Base (v : Mtvec) +: mword 62 := + + subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 63 2. + +Definition _set_Mtvec_Base (r_ref : register_ref regstate register_value Mtvec) (v : mword 62) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mtvec_Mtvec_chunk_0 := + (update_subrange_vec_dec r.(Mtvec_Mtvec_chunk_0) 63 2 (subrange_vec_dec v 61 0)) ]} + : Mtvec in + write_reg r_ref r + : M (unit). + +Definition _update_Mtvec_Base (v : Mtvec) (x : mword 62) +: Mtvec := + + {[ v with + Mtvec_Mtvec_chunk_0 := + (update_subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 63 2 (subrange_vec_dec x 61 0)) ]}. + +Definition _get_Mtvec_Mode (v : Mtvec) : mword 2 := subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 1 0. + +Definition _set_Mtvec_Mode (r_ref : register_ref regstate register_value Mtvec) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mtvec_Mtvec_chunk_0 := + (update_subrange_vec_dec r.(Mtvec_Mtvec_chunk_0) 1 0 (subrange_vec_dec v 1 0)) ]} + : Mtvec in + write_reg r_ref r + : M (unit). + +Definition _update_Mtvec_Mode (v : Mtvec) (x : mword 2) +: Mtvec := + + {[ v with + Mtvec_Mtvec_chunk_0 := + (update_subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 1 0 (subrange_vec_dec x 1 0)) ]}. + +Definition legalize_tvec (o : Mtvec) (v : mword 64) +: Mtvec := + + let v := Mk_Mtvec v in + match (trapVectorMode_of_bits (_get_Mtvec_Mode v)) with + | TV_Direct => v + | TV_Vector => v + | _ => _update_Mtvec_Mode v (_get_Mtvec_Mode o) + end. + +Definition Mk_Mcause (v : mword 64) +: Mcause := + + {| Mcause_Mcause_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_Mcause_bits (v : Mcause) +: mword 64 := + + subrange_vec_dec v.(Mcause_Mcause_chunk_0) 63 0. + +Definition _set_Mcause_bits (r_ref : register_ref regstate register_value Mcause) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mcause_Mcause_chunk_0 := + (update_subrange_vec_dec r.(Mcause_Mcause_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : Mcause in + write_reg r_ref r + : M (unit). + +Definition _update_Mcause_bits (v : Mcause) (x : mword 64) +: Mcause := + + {[ v with + Mcause_Mcause_chunk_0 := + (update_subrange_vec_dec v.(Mcause_Mcause_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_Mcause_IsInterrupt (v : Mcause) +: mword 1 := + + subrange_vec_dec v.(Mcause_Mcause_chunk_0) 63 63. + +Definition _set_Mcause_IsInterrupt +(r_ref : register_ref regstate register_value Mcause) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mcause_Mcause_chunk_0 := + (update_subrange_vec_dec r.(Mcause_Mcause_chunk_0) 63 63 (subrange_vec_dec v 0 0)) ]} + : Mcause in + write_reg r_ref r + : M (unit). + +Definition _update_Mcause_IsInterrupt (v : Mcause) (x : mword 1) +: Mcause := + + {[ v with + Mcause_Mcause_chunk_0 := + (update_subrange_vec_dec v.(Mcause_Mcause_chunk_0) 63 63 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mcause_Cause (v : Mcause) +: mword 63 := + + subrange_vec_dec v.(Mcause_Mcause_chunk_0) 62 0. + +Definition _set_Mcause_Cause (r_ref : register_ref regstate register_value Mcause) (v : mword 63) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mcause_Mcause_chunk_0 := + (update_subrange_vec_dec r.(Mcause_Mcause_chunk_0) 62 0 (subrange_vec_dec v 62 0)) ]} + : Mcause in + write_reg r_ref r + : M (unit). + +Definition _update_Mcause_Cause (v : Mcause) (x : mword 63) +: Mcause := + + {[ v with + Mcause_Mcause_chunk_0 := + (update_subrange_vec_dec v.(Mcause_Mcause_chunk_0) 62 0 (subrange_vec_dec x 62 0)) ]}. + +Definition tvec_addr (m : Mtvec) (c : Mcause) +: option (mword 64) := + + let base : xlenbits := concat_vec (_get_Mtvec_Base m) (vec_of_bits [B0;B0] : mword 2) in + match (trapVectorMode_of_bits (_get_Mtvec_Mode m)) with + | TV_Direct => Some (base) + | TV_Vector => + if ((eq_vec (_get_Mcause_IsInterrupt c) ((bool_to_bits true) : mword 1))) then + Some + (add_vec base + (shift_bits_left (EXTZ 64 (_get_Mcause_Cause c)) (vec_of_bits [B1;B0] : mword 2))) + else Some (base) + | TV_Reserved => None + end. + +Definition legalize_xepc (v : mword 64) +: M (mword 64) := + + (haveRVC tt) >>= fun w__0 : bool => + returnm ((and_vec v + (EXTS 64 + (if (w__0) then (vec_of_bits [B1;B1;B0] : mword 3) + else (vec_of_bits [B1;B0;B0] : mword 3)))) + : mword 64). + +Definition pc_alignment_mask '(tt : unit) +: M (mword 64) := + + read_reg misa_ref >>= fun w__0 : Misa => + returnm ((not_vec + (EXTZ 64 + (if ((eq_vec (_get_Misa_C w__0) ((bool_to_bits true) : mword 1))) then + (vec_of_bits [B0;B0] : mword 2) + else (vec_of_bits [B1;B0] : mword 2)))) + : mword 64). + +Definition Mk_Counteren (v : mword 32) +: Counteren := + + {| Counteren_Counteren_chunk_0 := (subrange_vec_dec v 31 0) |}. + +Definition _get_Counteren_bits (v : Counteren) +: mword 32 := + + subrange_vec_dec v.(Counteren_Counteren_chunk_0) 31 0. + +Definition _set_Counteren_bits +(r_ref : register_ref regstate register_value Counteren) (v : mword 32) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Counteren_Counteren_chunk_0 := + (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]} + : Counteren in + write_reg r_ref r + : M (unit). + +Definition _update_Counteren_bits (v : Counteren) (x : mword 32) +: Counteren := + + {[ v with + Counteren_Counteren_chunk_0 := + (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}. + +Definition _get_Counteren_HPM (v : Counteren) +: mword 29 := + + subrange_vec_dec v.(Counteren_Counteren_chunk_0) 31 3. + +Definition _set_Counteren_HPM +(r_ref : register_ref regstate register_value Counteren) (v : mword 29) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Counteren_Counteren_chunk_0 := + (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 31 3 (subrange_vec_dec v 28 0)) ]} + : Counteren in + write_reg r_ref r + : M (unit). + +Definition _update_Counteren_HPM (v : Counteren) (x : mword 29) +: Counteren := + + {[ v with + Counteren_Counteren_chunk_0 := + (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 31 3 (subrange_vec_dec x 28 0)) ]}. + +Definition _get_Counteren_IR (v : Counteren) +: mword 1 := + + subrange_vec_dec v.(Counteren_Counteren_chunk_0) 2 2. + +Definition _set_Counteren_IR (r_ref : register_ref regstate register_value Counteren) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Counteren_Counteren_chunk_0 := + (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]} + : Counteren in + write_reg r_ref r + : M (unit). + +Definition _update_Counteren_IR (v : Counteren) (x : mword 1) +: Counteren := + + {[ v with + Counteren_Counteren_chunk_0 := + (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Counteren_TM (v : Counteren) +: mword 1 := + + subrange_vec_dec v.(Counteren_Counteren_chunk_0) 1 1. + +Definition _set_Counteren_TM (r_ref : register_ref regstate register_value Counteren) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Counteren_Counteren_chunk_0 := + (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : Counteren in + write_reg r_ref r + : M (unit). + +Definition _update_Counteren_TM (v : Counteren) (x : mword 1) +: Counteren := + + {[ v with + Counteren_Counteren_chunk_0 := + (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Counteren_CY (v : Counteren) +: mword 1 := + + subrange_vec_dec v.(Counteren_Counteren_chunk_0) 0 0. + +Definition _set_Counteren_CY (r_ref : register_ref regstate register_value Counteren) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Counteren_Counteren_chunk_0 := + (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : Counteren in + write_reg r_ref r + : M (unit). + +Definition _update_Counteren_CY (v : Counteren) (x : mword 1) +: Counteren := + + {[ v with + Counteren_Counteren_chunk_0 := + (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition legalize_mcounteren (c : Counteren) (v : mword 64) +: M (Counteren) := + + (cast_unit_vec (access_vec_dec v 2)) >>= fun w__0 : mword 1 => + let c := _update_Counteren_IR c (w__0 : mword 1) in + (cast_unit_vec (access_vec_dec v 1)) >>= fun w__1 : mword 1 => + let c := _update_Counteren_TM c (w__1 : mword 1) in + (cast_unit_vec (access_vec_dec v 0)) >>= fun w__2 : mword 1 => + let c := _update_Counteren_CY c (w__2 : mword 1) in + returnm (c + : Counteren). + +Definition legalize_scounteren (c : Counteren) (v : mword 64) +: M (Counteren) := + + (cast_unit_vec (access_vec_dec v 2)) >>= fun w__0 : mword 1 => + let c := _update_Counteren_IR c (w__0 : mword 1) in + (cast_unit_vec (access_vec_dec v 1)) >>= fun w__1 : mword 1 => + let c := _update_Counteren_TM c (w__1 : mword 1) in + (cast_unit_vec (access_vec_dec v 0)) >>= fun w__2 : mword 1 => + let c := _update_Counteren_CY c (w__2 : mword 1) in + returnm (c + : Counteren). + +Definition retire_instruction '(tt : unit) +: M (unit) := + + read_reg minstret_written_ref >>= fun w__0 : bool => + (if ((Bool.eqb w__0 true)) then write_reg minstret_written_ref false : M (unit) + else + ((read_reg minstret_ref) : M (mword 64)) >>= fun w__1 : xlenbits => + write_reg minstret_ref (add_vec_int w__1 1) + : M (unit)) + : M (unit). + +Definition Mk_Sstatus (v : mword 64) +: Sstatus := + + {| Sstatus_Sstatus_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_Sstatus_bits (v : Sstatus) +: mword 64 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 63 0. + +Definition _set_Sstatus_bits (r_ref : register_ref regstate register_value Sstatus) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_bits (v : Sstatus) (x : mword 64) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_Sstatus_SD (v : Sstatus) +: mword 1 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 63 63. + +Definition _set_Sstatus_SD (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 63 63 (subrange_vec_dec v 0 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_SD (v : Sstatus) (x : mword 1) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 63 63 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sstatus_UXL (v : Sstatus) +: mword 2 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 33 32. + +Definition _set_Sstatus_UXL (r_ref : register_ref regstate register_value Sstatus) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 33 32 (subrange_vec_dec v 1 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_UXL (v : Sstatus) (x : mword 2) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 33 32 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_Sstatus_MXR (v : Sstatus) +: mword 1 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 19 19. + +Definition _set_Sstatus_MXR (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 19 19 (subrange_vec_dec v 0 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_MXR (v : Sstatus) (x : mword 1) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 19 19 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sstatus_SUM (v : Sstatus) +: mword 1 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 18 18. + +Definition _set_Sstatus_SUM (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 18 18 (subrange_vec_dec v 0 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_SUM (v : Sstatus) (x : mword 1) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 18 18 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sstatus_XS (v : Sstatus) +: mword 2 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 16 15. + +Definition _set_Sstatus_XS (r_ref : register_ref regstate register_value Sstatus) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 16 15 (subrange_vec_dec v 1 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_XS (v : Sstatus) (x : mword 2) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 16 15 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_Sstatus_FS (v : Sstatus) +: mword 2 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 14 13. + +Definition _set_Sstatus_FS (r_ref : register_ref regstate register_value Sstatus) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 14 13 (subrange_vec_dec v 1 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_FS (v : Sstatus) (x : mword 2) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 14 13 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_Sstatus_SPP (v : Sstatus) +: mword 1 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 8 8. + +Definition _set_Sstatus_SPP (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_SPP (v : Sstatus) (x : mword 1) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sstatus_SPIE (v : Sstatus) +: mword 1 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 5 5. + +Definition _set_Sstatus_SPIE (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_SPIE (v : Sstatus) (x : mword 1) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sstatus_UPIE (v : Sstatus) +: mword 1 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 4 4. + +Definition _set_Sstatus_UPIE (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_UPIE (v : Sstatus) (x : mword 1) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sstatus_SIE (v : Sstatus) +: mword 1 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 1 1. + +Definition _set_Sstatus_SIE (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_SIE (v : Sstatus) (x : mword 1) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sstatus_UIE (v : Sstatus) +: mword 1 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 0 0. + +Definition _set_Sstatus_UIE (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_UIE (v : Sstatus) (x : mword 1) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition lower_mstatus (m : Mstatus) +: Sstatus := + + let s := Mk_Sstatus (EXTZ 64 (vec_of_bits [B0] : mword 1)) in + let s := _update_Sstatus_SD s (_get_Mstatus_SD m) in + let s := _update_Sstatus_UXL s (_get_Mstatus_UXL m) in + let s := _update_Sstatus_MXR s (_get_Mstatus_MXR m) in + let s := _update_Sstatus_SUM s (_get_Mstatus_SUM m) in + let s := _update_Sstatus_XS s (_get_Mstatus_XS m) in + let s := _update_Sstatus_FS s (_get_Mstatus_FS m) in + let s := _update_Sstatus_SPP s (_get_Mstatus_SPP m) in + let s := _update_Sstatus_SPIE s (_get_Mstatus_SPIE m) in + let s := _update_Sstatus_UPIE s (_get_Mstatus_UPIE m) in + let s := _update_Sstatus_SIE s (_get_Mstatus_SIE m) in + _update_Sstatus_UIE s (_get_Mstatus_UIE m). + +Definition lift_sstatus (m : Mstatus) (s : Sstatus) +: Mstatus := + + let m := _update_Mstatus_MXR m (_get_Sstatus_MXR s) in + let m := _update_Mstatus_SUM m (_get_Sstatus_SUM s) in + let m := _update_Mstatus_XS m (_get_Sstatus_XS s) in + let m := _update_Mstatus_FS m (_get_Sstatus_FS s) in + let m := + _update_Mstatus_SD m + ((bool_to_bits + (orb + (eq_vec (extStatus_to_bits (extStatus_of_bits (_get_Mstatus_FS m))) + ((extStatus_to_bits Dirty) + : mword 2)) + (eq_vec (extStatus_to_bits (extStatus_of_bits (_get_Mstatus_XS m))) + ((extStatus_to_bits Dirty) + : mword 2)))) + : mword 1) in + let m := _update_Mstatus_SPP m (_get_Sstatus_SPP s) in + let m := _update_Mstatus_SPIE m (_get_Sstatus_SPIE s) in + let m := _update_Mstatus_UPIE m (_get_Sstatus_UPIE s) in + let m := _update_Mstatus_SIE m (_get_Sstatus_SIE s) in + _update_Mstatus_UIE m (_get_Sstatus_UIE s). + +Definition legalize_sstatus (m : Mstatus) (v : mword 64) +: Mstatus := + + lift_sstatus m (Mk_Sstatus v). + +Definition Mk_Sedeleg (v : mword 64) +: Sedeleg := + + {| Sedeleg_Sedeleg_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_Sedeleg_bits (v : Sedeleg) +: mword 64 := + + subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 63 0. + +Definition _set_Sedeleg_bits (r_ref : register_ref regstate register_value Sedeleg) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : Sedeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Sedeleg_bits (v : Sedeleg) (x : mword 64) +: Sedeleg := + + {[ v with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_Sedeleg_UEnvCall (v : Sedeleg) +: mword 1 := + + subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 8 8. + +Definition _set_Sedeleg_UEnvCall +(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} + : Sedeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Sedeleg_UEnvCall (v : Sedeleg) (x : mword 1) +: Sedeleg := + + {[ v with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sedeleg_SAMO_Access_Fault (v : Sedeleg) +: mword 1 := + + subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 7 7. + +Definition _set_Sedeleg_SAMO_Access_Fault +(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} + : Sedeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Sedeleg_SAMO_Access_Fault (v : Sedeleg) (x : mword 1) +: Sedeleg := + + {[ v with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sedeleg_SAMO_Addr_Align (v : Sedeleg) +: mword 1 := + + subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 6 6. + +Definition _set_Sedeleg_SAMO_Addr_Align +(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]} + : Sedeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Sedeleg_SAMO_Addr_Align (v : Sedeleg) (x : mword 1) +: Sedeleg := + + {[ v with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sedeleg_Load_Access_Fault (v : Sedeleg) +: mword 1 := + + subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 5 5. + +Definition _set_Sedeleg_Load_Access_Fault +(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} + : Sedeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Sedeleg_Load_Access_Fault (v : Sedeleg) (x : mword 1) +: Sedeleg := + + {[ v with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sedeleg_Load_Addr_Align (v : Sedeleg) +: mword 1 := + + subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 4 4. + +Definition _set_Sedeleg_Load_Addr_Align +(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} + : Sedeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Sedeleg_Load_Addr_Align (v : Sedeleg) (x : mword 1) +: Sedeleg := + + {[ v with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sedeleg_Breakpoint (v : Sedeleg) +: mword 1 := + + subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 3 3. + +Definition _set_Sedeleg_Breakpoint +(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]} + : Sedeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Sedeleg_Breakpoint (v : Sedeleg) (x : mword 1) +: Sedeleg := + + {[ v with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sedeleg_Illegal_Instr (v : Sedeleg) +: mword 1 := + + subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 2 2. + +Definition _set_Sedeleg_Illegal_Instr +(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]} + : Sedeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Sedeleg_Illegal_Instr (v : Sedeleg) (x : mword 1) +: Sedeleg := + + {[ v with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sedeleg_Fetch_Access_Fault (v : Sedeleg) +: mword 1 := + + subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 1 1. + +Definition _set_Sedeleg_Fetch_Access_Fault +(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : Sedeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Sedeleg_Fetch_Access_Fault (v : Sedeleg) (x : mword 1) +: Sedeleg := + + {[ v with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sedeleg_Fetch_Addr_Align (v : Sedeleg) +: mword 1 := + + subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 0 0. + +Definition _set_Sedeleg_Fetch_Addr_Align +(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : Sedeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Sedeleg_Fetch_Addr_Align (v : Sedeleg) (x : mword 1) +: Sedeleg := + + {[ v with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition legalize_sedeleg (s : Sedeleg) (v : mword 64) +: Sedeleg := + + Mk_Sedeleg (EXTZ 64 (subrange_vec_dec v 8 0)). + +Definition Mk_Sinterrupts (v : mword 64) +: Sinterrupts := + + {| Sinterrupts_Sinterrupts_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_Sinterrupts_bits (v : Sinterrupts) +: mword 64 := + + subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 63 0. + +Definition _set_Sinterrupts_bits +(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : Sinterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Sinterrupts_bits (v : Sinterrupts) (x : mword 64) +: Sinterrupts := + + {[ v with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_Sinterrupts_SEI (v : Sinterrupts) +: mword 1 := + + subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 9 9. + +Definition _set_Sinterrupts_SEI +(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 9 9 (subrange_vec_dec v 0 0)) ]} + : Sinterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Sinterrupts_SEI (v : Sinterrupts) (x : mword 1) +: Sinterrupts := + + {[ v with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 9 9 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sinterrupts_UEI (v : Sinterrupts) +: mword 1 := + + subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 8 8. + +Definition _set_Sinterrupts_UEI +(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} + : Sinterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Sinterrupts_UEI (v : Sinterrupts) (x : mword 1) +: Sinterrupts := + + {[ v with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sinterrupts_STI (v : Sinterrupts) +: mword 1 := + + subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 5 5. + +Definition _set_Sinterrupts_STI +(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} + : Sinterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Sinterrupts_STI (v : Sinterrupts) (x : mword 1) +: Sinterrupts := + + {[ v with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sinterrupts_UTI (v : Sinterrupts) +: mword 1 := + + subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 4 4. + +Definition _set_Sinterrupts_UTI +(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} + : Sinterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Sinterrupts_UTI (v : Sinterrupts) (x : mword 1) +: Sinterrupts := + + {[ v with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sinterrupts_SSI (v : Sinterrupts) +: mword 1 := + + subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 1 1. + +Definition _set_Sinterrupts_SSI +(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : Sinterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Sinterrupts_SSI (v : Sinterrupts) (x : mword 1) +: Sinterrupts := + + {[ v with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sinterrupts_USI (v : Sinterrupts) +: mword 1 := + + subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 0 0. + +Definition _set_Sinterrupts_USI +(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : Sinterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Sinterrupts_USI (v : Sinterrupts) (x : mword 1) +: Sinterrupts := + + {[ v with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition lower_mip (m : Minterrupts) (d : Minterrupts) +: Sinterrupts := + + let s : Sinterrupts := Mk_Sinterrupts (EXTZ 64 (vec_of_bits [B0] : mword 1)) in + let s := _update_Sinterrupts_SEI s (and_vec (_get_Minterrupts_SEI m) (_get_Minterrupts_SEI d)) in + let s := _update_Sinterrupts_STI s (and_vec (_get_Minterrupts_STI m) (_get_Minterrupts_STI d)) in + let s := _update_Sinterrupts_SSI s (and_vec (_get_Minterrupts_SSI m) (_get_Minterrupts_SSI d)) in + let s := _update_Sinterrupts_UEI s (and_vec (_get_Minterrupts_UEI m) (_get_Minterrupts_UEI d)) in + let s := _update_Sinterrupts_UTI s (and_vec (_get_Minterrupts_UTI m) (_get_Minterrupts_UTI d)) in + _update_Sinterrupts_USI s (and_vec (_get_Minterrupts_USI m) (_get_Minterrupts_USI d)). + +Definition lower_mie (m : Minterrupts) (d : Minterrupts) +: Sinterrupts := + + let s : Sinterrupts := Mk_Sinterrupts (EXTZ 64 (vec_of_bits [B0] : mword 1)) in + let s := _update_Sinterrupts_SEI s (and_vec (_get_Minterrupts_SEI m) (_get_Minterrupts_SEI d)) in + let s := _update_Sinterrupts_STI s (and_vec (_get_Minterrupts_STI m) (_get_Minterrupts_STI d)) in + let s := _update_Sinterrupts_SSI s (and_vec (_get_Minterrupts_SSI m) (_get_Minterrupts_SSI d)) in + let s := _update_Sinterrupts_UEI s (and_vec (_get_Minterrupts_UEI m) (_get_Minterrupts_UEI d)) in + let s := _update_Sinterrupts_UTI s (and_vec (_get_Minterrupts_UTI m) (_get_Minterrupts_UTI d)) in + _update_Sinterrupts_USI s (and_vec (_get_Minterrupts_USI m) (_get_Minterrupts_USI d)). + +Definition lift_sip (o : Minterrupts) (d : Minterrupts) (s : Sinterrupts) +: Minterrupts := + + let m : Minterrupts := o in + let m := _update_Minterrupts_SSI m (and_vec (_get_Sinterrupts_SSI s) (_get_Minterrupts_SSI d)) in + let m := _update_Minterrupts_UEI m (and_vec (_get_Minterrupts_UEI m) (_get_Minterrupts_UEI d)) in + _update_Minterrupts_USI m (and_vec (_get_Minterrupts_USI m) (_get_Minterrupts_USI d)). + +Definition legalize_sip (m : Minterrupts) (d : Minterrupts) (v : mword 64) +: Minterrupts := + + lift_sip m d (Mk_Sinterrupts v). + +Definition lift_sie (o : Minterrupts) (d : Minterrupts) (s : Sinterrupts) +: Minterrupts := + + let m : Minterrupts := o in + let m := + if ((eq_vec (_get_Minterrupts_SEI d) ((bool_to_bits true) : mword 1))) then + _update_Minterrupts_SEI m (_get_Sinterrupts_SEI s) + else m in + let m := + if ((eq_vec (_get_Minterrupts_STI d) ((bool_to_bits true) : mword 1))) then + _update_Minterrupts_STI m (_get_Sinterrupts_STI s) + else m in + let m := + if ((eq_vec (_get_Minterrupts_SSI d) ((bool_to_bits true) : mword 1))) then + _update_Minterrupts_SSI m (_get_Sinterrupts_SSI s) + else m in + let m := + if ((eq_vec (_get_Minterrupts_UEI d) ((bool_to_bits true) : mword 1))) then + _update_Minterrupts_UEI m (_get_Sinterrupts_UEI s) + else m in + let m := + if ((eq_vec (_get_Minterrupts_UTI d) ((bool_to_bits true) : mword 1))) then + _update_Minterrupts_UTI m (_get_Sinterrupts_UTI s) + else m in + if ((eq_vec (_get_Minterrupts_USI d) ((bool_to_bits true) : mword 1))) then + _update_Minterrupts_USI m (_get_Sinterrupts_USI s) + else m. + +Definition legalize_sie (m : Minterrupts) (d : Minterrupts) (v : mword 64) +: Minterrupts := + + lift_sie m d (Mk_Sinterrupts v). + +Definition Mk_Satp64 (v : mword 64) +: Satp64 := + + {| Satp64_Satp64_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_Satp64_bits (v : Satp64) +: mword 64 := + + subrange_vec_dec v.(Satp64_Satp64_chunk_0) 63 0. + +Definition _set_Satp64_bits (r_ref : register_ref regstate register_value Satp64) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Satp64_Satp64_chunk_0 := + (update_subrange_vec_dec r.(Satp64_Satp64_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : Satp64 in + write_reg r_ref r + : M (unit). + +Definition _update_Satp64_bits (v : Satp64) (x : mword 64) +: Satp64 := + + {[ v with + Satp64_Satp64_chunk_0 := + (update_subrange_vec_dec v.(Satp64_Satp64_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_Satp64_Mode (v : Satp64) +: mword 4 := + + subrange_vec_dec v.(Satp64_Satp64_chunk_0) 63 60. + +Definition _set_Satp64_Mode (r_ref : register_ref regstate register_value Satp64) (v : mword 4) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Satp64_Satp64_chunk_0 := + (update_subrange_vec_dec r.(Satp64_Satp64_chunk_0) 63 60 (subrange_vec_dec v 3 0)) ]} + : Satp64 in + write_reg r_ref r + : M (unit). + +Definition _update_Satp64_Mode (v : Satp64) (x : mword 4) +: Satp64 := + + {[ v with + Satp64_Satp64_chunk_0 := + (update_subrange_vec_dec v.(Satp64_Satp64_chunk_0) 63 60 (subrange_vec_dec x 3 0)) ]}. + +Definition _get_Satp64_Asid (v : Satp64) +: mword 16 := + + subrange_vec_dec v.(Satp64_Satp64_chunk_0) 59 44. + +Definition _set_Satp64_Asid (r_ref : register_ref regstate register_value Satp64) (v : mword 16) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Satp64_Satp64_chunk_0 := + (update_subrange_vec_dec r.(Satp64_Satp64_chunk_0) 59 44 (subrange_vec_dec v 15 0)) ]} + : Satp64 in + write_reg r_ref r + : M (unit). + +Definition _update_Satp64_Asid (v : Satp64) (x : mword 16) +: Satp64 := + + {[ v with + Satp64_Satp64_chunk_0 := + (update_subrange_vec_dec v.(Satp64_Satp64_chunk_0) 59 44 (subrange_vec_dec x 15 0)) ]}. + +Definition _get_Satp64_PPN (v : Satp64) +: mword 44 := + + subrange_vec_dec v.(Satp64_Satp64_chunk_0) 43 0. + +Definition _set_Satp64_PPN (r_ref : register_ref regstate register_value Satp64) (v : mword 44) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Satp64_Satp64_chunk_0 := + (update_subrange_vec_dec r.(Satp64_Satp64_chunk_0) 43 0 (subrange_vec_dec v 43 0)) ]} + : Satp64 in + write_reg r_ref r + : M (unit). + +Definition _update_Satp64_PPN (v : Satp64) (x : mword 44) +: Satp64 := + + {[ v with + Satp64_Satp64_chunk_0 := + (update_subrange_vec_dec v.(Satp64_Satp64_chunk_0) 43 0 (subrange_vec_dec x 43 0)) ]}. + +Definition legalize_satp (a : Architecture) (o : mword 64) (v : mword 64) +: mword 64 := + + let s := Mk_Satp64 v in + match (satpMode_of_bits a (_get_Satp64_Mode s)) with + | None => o + | Some (Sv32) => o + | Some (_) => _get_Satp64_bits s + end. + +Definition csr_name (csr : mword 12) +: string := + + let b__0 := csr in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then "ustatus" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + "uie" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + "utvec" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + "fflags" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "frm" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + "fcsr" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "cycle" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + "time" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "instret" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "cycleh" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + "timeh" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "instreth" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "sstatus" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "sedeleg" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + "sideleg" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + "sie" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + "stvec" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then + "scounteren" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + "sscratch" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + "sepc" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + "scause" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + "stval" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + "sip" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "satp" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then + "mvendorid" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then + "marchid" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then + "mimpid" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then + "mhartid" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "mstatus" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + "misa" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "medeleg" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + "mideleg" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + "mie" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + "mtvec" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then + "mcounteren" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + "mscratch" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + "mepc" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + "mcause" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + "mtval" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + "mip" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then + "pmpcfg0" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then + "pmpaddr0" + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "mcycle" + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "minstret" + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "mcycleh" + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "minstreth" + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then + "tselect" + else "UNKNOWN". + +Definition csr_name_map_forwards (arg_ : mword 12) +: string := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then "ustatus" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + "uie" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + "utvec" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + "uscratch" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + "uepc" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + "ucause" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + "utval" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + "uip" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + "fflags" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "frm" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + "fcsr" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "cycle" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + "time" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "instret" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "cycleh" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + "timeh" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "instreth" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "sstatus" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "sedeleg" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + "sideleg" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + "sie" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + "stvec" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then + "scounteren" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + "sscratch" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + "sepc" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + "scause" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + "stval" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + "sip" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "satp" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then + "mvendorid" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then + "marchid" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then + "mimpid" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then + "mhartid" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "mstatus" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + "misa" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "medeleg" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + "mideleg" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + "mie" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + "mtvec" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then + "mcounteren" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + "mscratch" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + "mepc" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + "mcause" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + "mtval" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + "mip" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then + "pmpcfg0" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then + "pmpcfg1" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then + "pmpcfg2" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12))) then + "pmpcfg3" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then + "pmpaddr0" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12))) then + "pmpaddr1" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12))) then + "pmpaddr2" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12))) then + "pmpaddr3" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12))) then + "pmpaddr4" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12))) then + "pmpaddr5" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12))) then + "pmpaddr6" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12))) then + "pmpaddr7" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12))) then + "pmpaddr8" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12))) then + "pmpaddr9" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12))) then + "pmpaddr10" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12))) then + "pmpaddr11" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12))) then + "pmpaddr12" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12))) then + "pmpaddr13" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12))) then + "pmpaddr14" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12))) then + "pmpaddr15" + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "mcycle" + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "minstret" + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "mcycleh" + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "minstreth" + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then + "tselect" + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then + "tdata1" + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then + "tdata2" + else "tdata3". + +Definition csr_name_map_backwards (arg_ : string) +: mword 12 := + + let p0_ := arg_ in + if ((generic_eq p0_ "ustatus")) then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "uie")) then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12) + else if ((generic_eq p0_ "utvec")) then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12) + else if ((generic_eq p0_ "uscratch")) then + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "uepc")) then + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "ucause")) then + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "utval")) then + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12) + else if ((generic_eq p0_ "uip")) then + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12) + else if ((generic_eq p0_ "fflags")) then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "frm")) then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "fcsr")) then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) + else if ((generic_eq p0_ "cycle")) then + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "time")) then + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "instret")) then + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "cycleh")) then + (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "timeh")) then + (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "instreth")) then + (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "sstatus")) then + (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "sedeleg")) then + (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "sideleg")) then + (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) + else if ((generic_eq p0_ "sie")) then + (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12) + else if ((generic_eq p0_ "stvec")) then + (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12) + else if ((generic_eq p0_ "scounteren")) then + (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12) + else if ((generic_eq p0_ "sscratch")) then + (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "sepc")) then + (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "scause")) then + (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "stval")) then + (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12) + else if ((generic_eq p0_ "sip")) then + (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12) + else if ((generic_eq p0_ "satp")) then + (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "mvendorid")) then + (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "marchid")) then + (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "mimpid")) then + (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12) + else if ((generic_eq p0_ "mhartid")) then + (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12) + else if ((generic_eq p0_ "mstatus")) then + (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "misa")) then + (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "medeleg")) then + (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "mideleg")) then + (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) + else if ((generic_eq p0_ "mie")) then + (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12) + else if ((generic_eq p0_ "mtvec")) then + (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12) + else if ((generic_eq p0_ "mcounteren")) then + (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12) + else if ((generic_eq p0_ "mscratch")) then + (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "mepc")) then + (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "mcause")) then + (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "mtval")) then + (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12) + else if ((generic_eq p0_ "mip")) then + (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12) + else if ((generic_eq p0_ "pmpcfg0")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "pmpcfg1")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "pmpcfg2")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "pmpcfg3")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12) + else if ((generic_eq p0_ "pmpaddr0")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "pmpaddr1")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "pmpaddr2")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "pmpaddr3")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12) + else if ((generic_eq p0_ "pmpaddr4")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12) + else if ((generic_eq p0_ "pmpaddr5")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12) + else if ((generic_eq p0_ "pmpaddr6")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12) + else if ((generic_eq p0_ "pmpaddr7")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12) + else if ((generic_eq p0_ "pmpaddr8")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "pmpaddr9")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "pmpaddr10")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "pmpaddr11")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12) + else if ((generic_eq p0_ "pmpaddr12")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12) + else if ((generic_eq p0_ "pmpaddr13")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12) + else if ((generic_eq p0_ "pmpaddr14")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12) + else if ((generic_eq p0_ "pmpaddr15")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12) + else if ((generic_eq p0_ "mcycle")) then + (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "minstret")) then + (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "mcycleh")) then + (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "minstreth")) then + (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "tselect")) then + (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "tdata1")) then + (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "tdata2")) then + (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12) + else (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12). + +Definition csr_name_map_forwards_matches (arg_ : mword 12) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12))) then true + else false. + +Definition csr_name_map_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "ustatus")) then true + else if ((generic_eq p0_ "uie")) then true + else if ((generic_eq p0_ "utvec")) then true + else if ((generic_eq p0_ "uscratch")) then true + else if ((generic_eq p0_ "uepc")) then true + else if ((generic_eq p0_ "ucause")) then true + else if ((generic_eq p0_ "utval")) then true + else if ((generic_eq p0_ "uip")) then true + else if ((generic_eq p0_ "fflags")) then true + else if ((generic_eq p0_ "frm")) then true + else if ((generic_eq p0_ "fcsr")) then true + else if ((generic_eq p0_ "cycle")) then true + else if ((generic_eq p0_ "time")) then true + else if ((generic_eq p0_ "instret")) then true + else if ((generic_eq p0_ "cycleh")) then true + else if ((generic_eq p0_ "timeh")) then true + else if ((generic_eq p0_ "instreth")) then true + else if ((generic_eq p0_ "sstatus")) then true + else if ((generic_eq p0_ "sedeleg")) then true + else if ((generic_eq p0_ "sideleg")) then true + else if ((generic_eq p0_ "sie")) then true + else if ((generic_eq p0_ "stvec")) then true + else if ((generic_eq p0_ "scounteren")) then true + else if ((generic_eq p0_ "sscratch")) then true + else if ((generic_eq p0_ "sepc")) then true + else if ((generic_eq p0_ "scause")) then true + else if ((generic_eq p0_ "stval")) then true + else if ((generic_eq p0_ "sip")) then true + else if ((generic_eq p0_ "satp")) then true + else if ((generic_eq p0_ "mvendorid")) then true + else if ((generic_eq p0_ "marchid")) then true + else if ((generic_eq p0_ "mimpid")) then true + else if ((generic_eq p0_ "mhartid")) then true + else if ((generic_eq p0_ "mstatus")) then true + else if ((generic_eq p0_ "misa")) then true + else if ((generic_eq p0_ "medeleg")) then true + else if ((generic_eq p0_ "mideleg")) then true + else if ((generic_eq p0_ "mie")) then true + else if ((generic_eq p0_ "mtvec")) then true + else if ((generic_eq p0_ "mcounteren")) then true + else if ((generic_eq p0_ "mscratch")) then true + else if ((generic_eq p0_ "mepc")) then true + else if ((generic_eq p0_ "mcause")) then true + else if ((generic_eq p0_ "mtval")) then true + else if ((generic_eq p0_ "mip")) then true + else if ((generic_eq p0_ "pmpcfg0")) then true + else if ((generic_eq p0_ "pmpcfg1")) then true + else if ((generic_eq p0_ "pmpcfg2")) then true + else if ((generic_eq p0_ "pmpcfg3")) then true + else if ((generic_eq p0_ "pmpaddr0")) then true + else if ((generic_eq p0_ "pmpaddr1")) then true + else if ((generic_eq p0_ "pmpaddr2")) then true + else if ((generic_eq p0_ "pmpaddr3")) then true + else if ((generic_eq p0_ "pmpaddr4")) then true + else if ((generic_eq p0_ "pmpaddr5")) then true + else if ((generic_eq p0_ "pmpaddr6")) then true + else if ((generic_eq p0_ "pmpaddr7")) then true + else if ((generic_eq p0_ "pmpaddr8")) then true + else if ((generic_eq p0_ "pmpaddr9")) then true + else if ((generic_eq p0_ "pmpaddr10")) then true + else if ((generic_eq p0_ "pmpaddr11")) then true + else if ((generic_eq p0_ "pmpaddr12")) then true + else if ((generic_eq p0_ "pmpaddr13")) then true + else if ((generic_eq p0_ "pmpaddr14")) then true + else if ((generic_eq p0_ "pmpaddr15")) then true + else if ((generic_eq p0_ "mcycle")) then true + else if ((generic_eq p0_ "minstret")) then true + else if ((generic_eq p0_ "mcycleh")) then true + else if ((generic_eq p0_ "minstreth")) then true + else if ((generic_eq p0_ "tselect")) then true + else if ((generic_eq p0_ "tdata1")) then true + else if ((generic_eq p0_ "tdata2")) then true + else if ((generic_eq p0_ "tdata3")) then true + else false. + +Definition _s488_ (_s489_ : string) +: option string := + + let _s490_ := _s489_ in + if ((string_startswith _s490_ "tdata3")) then + match (string_drop _s490_ (projT1 (string_length "tdata3"))) with | s_ => Some (s_) end + else None. + +Definition _s484_ (_s485_ : string) +: option string := + + let _s486_ := _s485_ in + if ((string_startswith _s486_ "tdata2")) then + match (string_drop _s486_ (projT1 (string_length "tdata2"))) with | s_ => Some (s_) end + else None. + +Definition _s480_ (_s481_ : string) +: option string := + + let _s482_ := _s481_ in + if ((string_startswith _s482_ "tdata1")) then + match (string_drop _s482_ (projT1 (string_length "tdata1"))) with | s_ => Some (s_) end + else None. + +Definition _s476_ (_s477_ : string) +: option string := + + let _s478_ := _s477_ in + if ((string_startswith _s478_ "tselect")) then + match (string_drop _s478_ (projT1 (string_length "tselect"))) with | s_ => Some (s_) end + else None. + +Definition _s472_ (_s473_ : string) +: option string := + + let _s474_ := _s473_ in + if ((string_startswith _s474_ "minstreth")) then + match (string_drop _s474_ (projT1 (string_length "minstreth"))) with | s_ => Some (s_) end + else None. + +Definition _s468_ (_s469_ : string) +: option string := + + let _s470_ := _s469_ in + if ((string_startswith _s470_ "mcycleh")) then + match (string_drop _s470_ (projT1 (string_length "mcycleh"))) with | s_ => Some (s_) end + else None. + +Definition _s464_ (_s465_ : string) +: option string := + + let _s466_ := _s465_ in + if ((string_startswith _s466_ "minstret")) then + match (string_drop _s466_ (projT1 (string_length "minstret"))) with | s_ => Some (s_) end + else None. + +Definition _s460_ (_s461_ : string) +: option string := + + let _s462_ := _s461_ in + if ((string_startswith _s462_ "mcycle")) then + match (string_drop _s462_ (projT1 (string_length "mcycle"))) with | s_ => Some (s_) end + else None. + +Definition _s456_ (_s457_ : string) +: option string := + + let _s458_ := _s457_ in + if ((string_startswith _s458_ "pmpaddr15")) then + match (string_drop _s458_ (projT1 (string_length "pmpaddr15"))) with | s_ => Some (s_) end + else None. + +Definition _s452_ (_s453_ : string) +: option string := + + let _s454_ := _s453_ in + if ((string_startswith _s454_ "pmpaddr14")) then + match (string_drop _s454_ (projT1 (string_length "pmpaddr14"))) with | s_ => Some (s_) end + else None. + +Definition _s448_ (_s449_ : string) +: option string := + + let _s450_ := _s449_ in + if ((string_startswith _s450_ "pmpaddr13")) then + match (string_drop _s450_ (projT1 (string_length "pmpaddr13"))) with | s_ => Some (s_) end + else None. + +Definition _s444_ (_s445_ : string) +: option string := + + let _s446_ := _s445_ in + if ((string_startswith _s446_ "pmpaddr12")) then + match (string_drop _s446_ (projT1 (string_length "pmpaddr12"))) with | s_ => Some (s_) end + else None. + +Definition _s440_ (_s441_ : string) +: option string := + + let _s442_ := _s441_ in + if ((string_startswith _s442_ "pmpaddr11")) then + match (string_drop _s442_ (projT1 (string_length "pmpaddr11"))) with | s_ => Some (s_) end + else None. + +Definition _s436_ (_s437_ : string) +: option string := + + let _s438_ := _s437_ in + if ((string_startswith _s438_ "pmpaddr10")) then + match (string_drop _s438_ (projT1 (string_length "pmpaddr10"))) with | s_ => Some (s_) end + else None. + +Definition _s432_ (_s433_ : string) +: option string := + + let _s434_ := _s433_ in + if ((string_startswith _s434_ "pmpaddr9")) then + match (string_drop _s434_ (projT1 (string_length "pmpaddr9"))) with | s_ => Some (s_) end + else None. + +Definition _s428_ (_s429_ : string) +: option string := + + let _s430_ := _s429_ in + if ((string_startswith _s430_ "pmpaddr8")) then + match (string_drop _s430_ (projT1 (string_length "pmpaddr8"))) with | s_ => Some (s_) end + else None. + +Definition _s424_ (_s425_ : string) +: option string := + + let _s426_ := _s425_ in + if ((string_startswith _s426_ "pmpaddr7")) then + match (string_drop _s426_ (projT1 (string_length "pmpaddr7"))) with | s_ => Some (s_) end + else None. + +Definition _s420_ (_s421_ : string) +: option string := + + let _s422_ := _s421_ in + if ((string_startswith _s422_ "pmpaddr6")) then + match (string_drop _s422_ (projT1 (string_length "pmpaddr6"))) with | s_ => Some (s_) end + else None. + +Definition _s416_ (_s417_ : string) +: option string := + + let _s418_ := _s417_ in + if ((string_startswith _s418_ "pmpaddr5")) then + match (string_drop _s418_ (projT1 (string_length "pmpaddr5"))) with | s_ => Some (s_) end + else None. + +Definition _s412_ (_s413_ : string) +: option string := + + let _s414_ := _s413_ in + if ((string_startswith _s414_ "pmpaddr4")) then + match (string_drop _s414_ (projT1 (string_length "pmpaddr4"))) with | s_ => Some (s_) end + else None. + +Definition _s408_ (_s409_ : string) +: option string := + + let _s410_ := _s409_ in + if ((string_startswith _s410_ "pmpaddr3")) then + match (string_drop _s410_ (projT1 (string_length "pmpaddr3"))) with | s_ => Some (s_) end + else None. + +Definition _s404_ (_s405_ : string) +: option string := + + let _s406_ := _s405_ in + if ((string_startswith _s406_ "pmpaddr2")) then + match (string_drop _s406_ (projT1 (string_length "pmpaddr2"))) with | s_ => Some (s_) end + else None. + +Definition _s400_ (_s401_ : string) +: option string := + + let _s402_ := _s401_ in + if ((string_startswith _s402_ "pmpaddr1")) then + match (string_drop _s402_ (projT1 (string_length "pmpaddr1"))) with | s_ => Some (s_) end + else None. + +Definition _s396_ (_s397_ : string) +: option string := + + let _s398_ := _s397_ in + if ((string_startswith _s398_ "pmpaddr0")) then + match (string_drop _s398_ (projT1 (string_length "pmpaddr0"))) with | s_ => Some (s_) end + else None. + +Definition _s392_ (_s393_ : string) +: option string := + + let _s394_ := _s393_ in + if ((string_startswith _s394_ "pmpcfg3")) then + match (string_drop _s394_ (projT1 (string_length "pmpcfg3"))) with | s_ => Some (s_) end + else None. + +Definition _s388_ (_s389_ : string) +: option string := + + let _s390_ := _s389_ in + if ((string_startswith _s390_ "pmpcfg2")) then + match (string_drop _s390_ (projT1 (string_length "pmpcfg2"))) with | s_ => Some (s_) end + else None. + +Definition _s384_ (_s385_ : string) +: option string := + + let _s386_ := _s385_ in + if ((string_startswith _s386_ "pmpcfg1")) then + match (string_drop _s386_ (projT1 (string_length "pmpcfg1"))) with | s_ => Some (s_) end + else None. + +Definition _s380_ (_s381_ : string) +: option string := + + let _s382_ := _s381_ in + if ((string_startswith _s382_ "pmpcfg0")) then + match (string_drop _s382_ (projT1 (string_length "pmpcfg0"))) with | s_ => Some (s_) end + else None. + +Definition _s376_ (_s377_ : string) +: option string := + + let _s378_ := _s377_ in + if ((string_startswith _s378_ "mip")) then + match (string_drop _s378_ (projT1 (string_length "mip"))) with | s_ => Some (s_) end + else None. + +Definition _s372_ (_s373_ : string) +: option string := + + let _s374_ := _s373_ in + if ((string_startswith _s374_ "mtval")) then + match (string_drop _s374_ (projT1 (string_length "mtval"))) with | s_ => Some (s_) end + else None. + +Definition _s368_ (_s369_ : string) +: option string := + + let _s370_ := _s369_ in + if ((string_startswith _s370_ "mcause")) then + match (string_drop _s370_ (projT1 (string_length "mcause"))) with | s_ => Some (s_) end + else None. + +Definition _s364_ (_s365_ : string) +: option string := + + let _s366_ := _s365_ in + if ((string_startswith _s366_ "mepc")) then + match (string_drop _s366_ (projT1 (string_length "mepc"))) with | s_ => Some (s_) end + else None. + +Definition _s360_ (_s361_ : string) +: option string := + + let _s362_ := _s361_ in + if ((string_startswith _s362_ "mscratch")) then + match (string_drop _s362_ (projT1 (string_length "mscratch"))) with | s_ => Some (s_) end + else None. + +Definition _s356_ (_s357_ : string) +: option string := + + let _s358_ := _s357_ in + if ((string_startswith _s358_ "mcounteren")) then + match (string_drop _s358_ (projT1 (string_length "mcounteren"))) with | s_ => Some (s_) end + else None. + +Definition _s352_ (_s353_ : string) +: option string := + + let _s354_ := _s353_ in + if ((string_startswith _s354_ "mtvec")) then + match (string_drop _s354_ (projT1 (string_length "mtvec"))) with | s_ => Some (s_) end + else None. + +Definition _s348_ (_s349_ : string) +: option string := + + let _s350_ := _s349_ in + if ((string_startswith _s350_ "mie")) then + match (string_drop _s350_ (projT1 (string_length "mie"))) with | s_ => Some (s_) end + else None. + +Definition _s344_ (_s345_ : string) +: option string := + + let _s346_ := _s345_ in + if ((string_startswith _s346_ "mideleg")) then + match (string_drop _s346_ (projT1 (string_length "mideleg"))) with | s_ => Some (s_) end + else None. + +Definition _s340_ (_s341_ : string) +: option string := + + let _s342_ := _s341_ in + if ((string_startswith _s342_ "medeleg")) then + match (string_drop _s342_ (projT1 (string_length "medeleg"))) with | s_ => Some (s_) end + else None. + +Definition _s336_ (_s337_ : string) +: option string := + + let _s338_ := _s337_ in + if ((string_startswith _s338_ "misa")) then + match (string_drop _s338_ (projT1 (string_length "misa"))) with | s_ => Some (s_) end + else None. + +Definition _s332_ (_s333_ : string) +: option string := + + let _s334_ := _s333_ in + if ((string_startswith _s334_ "mstatus")) then + match (string_drop _s334_ (projT1 (string_length "mstatus"))) with | s_ => Some (s_) end + else None. + +Definition _s328_ (_s329_ : string) +: option string := + + let _s330_ := _s329_ in + if ((string_startswith _s330_ "mhartid")) then + match (string_drop _s330_ (projT1 (string_length "mhartid"))) with | s_ => Some (s_) end + else None. + +Definition _s324_ (_s325_ : string) +: option string := + + let _s326_ := _s325_ in + if ((string_startswith _s326_ "mimpid")) then + match (string_drop _s326_ (projT1 (string_length "mimpid"))) with | s_ => Some (s_) end + else None. + +Definition _s320_ (_s321_ : string) +: option string := + + let _s322_ := _s321_ in + if ((string_startswith _s322_ "marchid")) then + match (string_drop _s322_ (projT1 (string_length "marchid"))) with | s_ => Some (s_) end + else None. + +Definition _s316_ (_s317_ : string) +: option string := + + let _s318_ := _s317_ in + if ((string_startswith _s318_ "mvendorid")) then + match (string_drop _s318_ (projT1 (string_length "mvendorid"))) with | s_ => Some (s_) end + else None. + +Definition _s312_ (_s313_ : string) +: option string := + + let _s314_ := _s313_ in + if ((string_startswith _s314_ "satp")) then + match (string_drop _s314_ (projT1 (string_length "satp"))) with | s_ => Some (s_) end + else None. + +Definition _s308_ (_s309_ : string) +: option string := + + let _s310_ := _s309_ in + if ((string_startswith _s310_ "sip")) then + match (string_drop _s310_ (projT1 (string_length "sip"))) with | s_ => Some (s_) end + else None. + +Definition _s304_ (_s305_ : string) +: option string := + + let _s306_ := _s305_ in + if ((string_startswith _s306_ "stval")) then + match (string_drop _s306_ (projT1 (string_length "stval"))) with | s_ => Some (s_) end + else None. + +Definition _s300_ (_s301_ : string) +: option string := + + let _s302_ := _s301_ in + if ((string_startswith _s302_ "scause")) then + match (string_drop _s302_ (projT1 (string_length "scause"))) with | s_ => Some (s_) end + else None. + +Definition _s296_ (_s297_ : string) +: option string := + + let _s298_ := _s297_ in + if ((string_startswith _s298_ "sepc")) then + match (string_drop _s298_ (projT1 (string_length "sepc"))) with | s_ => Some (s_) end + else None. + +Definition _s292_ (_s293_ : string) +: option string := + + let _s294_ := _s293_ in + if ((string_startswith _s294_ "sscratch")) then + match (string_drop _s294_ (projT1 (string_length "sscratch"))) with | s_ => Some (s_) end + else None. + +Definition _s288_ (_s289_ : string) +: option string := + + let _s290_ := _s289_ in + if ((string_startswith _s290_ "scounteren")) then + match (string_drop _s290_ (projT1 (string_length "scounteren"))) with | s_ => Some (s_) end + else None. + +Definition _s284_ (_s285_ : string) +: option string := + + let _s286_ := _s285_ in + if ((string_startswith _s286_ "stvec")) then + match (string_drop _s286_ (projT1 (string_length "stvec"))) with | s_ => Some (s_) end + else None. + +Definition _s280_ (_s281_ : string) +: option string := + + let _s282_ := _s281_ in + if ((string_startswith _s282_ "sie")) then + match (string_drop _s282_ (projT1 (string_length "sie"))) with | s_ => Some (s_) end + else None. + +Definition _s276_ (_s277_ : string) +: option string := + + let _s278_ := _s277_ in + if ((string_startswith _s278_ "sideleg")) then + match (string_drop _s278_ (projT1 (string_length "sideleg"))) with | s_ => Some (s_) end + else None. + +Definition _s272_ (_s273_ : string) +: option string := + + let _s274_ := _s273_ in + if ((string_startswith _s274_ "sedeleg")) then + match (string_drop _s274_ (projT1 (string_length "sedeleg"))) with | s_ => Some (s_) end + else None. + +Definition _s268_ (_s269_ : string) +: option string := + + let _s270_ := _s269_ in + if ((string_startswith _s270_ "sstatus")) then + match (string_drop _s270_ (projT1 (string_length "sstatus"))) with | s_ => Some (s_) end + else None. + +Definition _s264_ (_s265_ : string) +: option string := + + let _s266_ := _s265_ in + if ((string_startswith _s266_ "instreth")) then + match (string_drop _s266_ (projT1 (string_length "instreth"))) with | s_ => Some (s_) end + else None. + +Definition _s260_ (_s261_ : string) +: option string := + + let _s262_ := _s261_ in + if ((string_startswith _s262_ "timeh")) then + match (string_drop _s262_ (projT1 (string_length "timeh"))) with | s_ => Some (s_) end + else None. + +Definition _s256_ (_s257_ : string) +: option string := + + let _s258_ := _s257_ in + if ((string_startswith _s258_ "cycleh")) then + match (string_drop _s258_ (projT1 (string_length "cycleh"))) with | s_ => Some (s_) end + else None. + +Definition _s252_ (_s253_ : string) +: option string := + + let _s254_ := _s253_ in + if ((string_startswith _s254_ "instret")) then + match (string_drop _s254_ (projT1 (string_length "instret"))) with | s_ => Some (s_) end + else None. + +Definition _s248_ (_s249_ : string) +: option string := + + let _s250_ := _s249_ in + if ((string_startswith _s250_ "time")) then + match (string_drop _s250_ (projT1 (string_length "time"))) with | s_ => Some (s_) end + else None. + +Definition _s244_ (_s245_ : string) +: option string := + + let _s246_ := _s245_ in + if ((string_startswith _s246_ "cycle")) then + match (string_drop _s246_ (projT1 (string_length "cycle"))) with | s_ => Some (s_) end + else None. + +Definition _s240_ (_s241_ : string) +: option string := + + let _s242_ := _s241_ in + if ((string_startswith _s242_ "fcsr")) then + match (string_drop _s242_ (projT1 (string_length "fcsr"))) with | s_ => Some (s_) end + else None. + +Definition _s236_ (_s237_ : string) +: option string := + + let _s238_ := _s237_ in + if ((string_startswith _s238_ "frm")) then + match (string_drop _s238_ (projT1 (string_length "frm"))) with | s_ => Some (s_) end + else None. + +Definition _s232_ (_s233_ : string) +: option string := + + let _s234_ := _s233_ in + if ((string_startswith _s234_ "fflags")) then + match (string_drop _s234_ (projT1 (string_length "fflags"))) with | s_ => Some (s_) end + else None. + +Definition _s228_ (_s229_ : string) +: option string := + + let _s230_ := _s229_ in + if ((string_startswith _s230_ "uip")) then + match (string_drop _s230_ (projT1 (string_length "uip"))) with | s_ => Some (s_) end + else None. + +Definition _s224_ (_s225_ : string) +: option string := + + let _s226_ := _s225_ in + if ((string_startswith _s226_ "utval")) then + match (string_drop _s226_ (projT1 (string_length "utval"))) with | s_ => Some (s_) end + else None. + +Definition _s220_ (_s221_ : string) +: option string := + + let _s222_ := _s221_ in + if ((string_startswith _s222_ "ucause")) then + match (string_drop _s222_ (projT1 (string_length "ucause"))) with | s_ => Some (s_) end + else None. + +Definition _s216_ (_s217_ : string) +: option string := + + let _s218_ := _s217_ in + if ((string_startswith _s218_ "uepc")) then + match (string_drop _s218_ (projT1 (string_length "uepc"))) with | s_ => Some (s_) end + else None. + +Definition _s212_ (_s213_ : string) +: option string := + + let _s214_ := _s213_ in + if ((string_startswith _s214_ "uscratch")) then + match (string_drop _s214_ (projT1 (string_length "uscratch"))) with | s_ => Some (s_) end + else None. + +Definition _s208_ (_s209_ : string) +: option string := + + let _s210_ := _s209_ in + if ((string_startswith _s210_ "utvec")) then + match (string_drop _s210_ (projT1 (string_length "utvec"))) with | s_ => Some (s_) end + else None. + +Definition _s204_ (_s205_ : string) +: option string := + + let _s206_ := _s205_ in + if ((string_startswith _s206_ "uie")) then + match (string_drop _s206_ (projT1 (string_length "uie"))) with | s_ => Some (s_) end + else None. + +Definition _s200_ (_s201_ : string) +: option string := + + let _s202_ := _s201_ in + if ((string_startswith _s202_ "ustatus")) then + match (string_drop _s202_ (projT1 (string_length "ustatus"))) with | s_ => Some (s_) end + else None. + +Definition csr_name_map_matches_prefix (arg_ : string) +: M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) := + + let _s203_ := arg_ in + (if ((match (_s200_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s200_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s204_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s204_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s208_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s208_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s212_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s212_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s216_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s216_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s220_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s220_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s224_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s224_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s228_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s228_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s232_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s232_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s236_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s236_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s240_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s240_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s244_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s244_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s248_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s248_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s252_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s252_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s256_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s256_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s260_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s260_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s264_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s264_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s268_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s268_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s272_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s272_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s276_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s276_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s280_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s280_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s284_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s284_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s288_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s288_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s292_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s292_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s296_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s296_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s300_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s300_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s304_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s304_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s308_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s308_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s312_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s312_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s316_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s316_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s320_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s320_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s324_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s324_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s328_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s328_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s332_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s332_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s336_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s336_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s340_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s340_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s344_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s344_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s348_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s348_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s352_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s352_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s356_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s356_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s360_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s360_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s364_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s364_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s368_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s368_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s372_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s372_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s376_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s376_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s380_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s380_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s384_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s384_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s388_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s388_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s392_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s392_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s396_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s396_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s400_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s400_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s404_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s404_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s408_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s408_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s412_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s412_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s416_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s416_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s420_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s420_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s424_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s424_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s428_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s428_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s432_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s432_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s436_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s436_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s440_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s440_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s444_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s444_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s448_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s448_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s452_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s452_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s456_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s456_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s460_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s460_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s464_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s464_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s468_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s468_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s472_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s472_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s476_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s476_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s480_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s480_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s484_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s484_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s488_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s488_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))). + +Definition csrAccess (csr : mword 12) : mword 2 := subrange_vec_dec csr 11 10. + +Definition csrPriv (csr : mword 12) : mword 2 := subrange_vec_dec csr 9 8. + +Definition is_CSR_defined (csr : mword 12) (p : Privilege) +: bool := + + let b__0 := csr in + if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then + false + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else false. + +Definition check_CSR_access (csrrw : mword 2) (csrpr : mword 2) (p : Privilege) (isWrite : bool) +: bool := + + andb (negb (andb (Bool.eqb isWrite true) (eq_vec csrrw (vec_of_bits [B1;B1] : mword 2)))) + (zopz0zKzJ_u (privLevel_to_bits p) csrpr). + +Definition check_TVM_SATP (csr : mword 12) (p : Privilege) +: M (bool) := + + (and_boolM + (returnm ((eq_vec csr (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12)) + : bool)) + ((and_boolM + (returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + : bool)) + (read_reg mstatus_ref >>= fun w__0 : Mstatus => + returnm ((eq_vec (_get_Mstatus_TVM w__0) ((bool_to_bits true) : mword 1)) + : bool))) + : M (bool))) >>= fun w__2 : bool => + returnm ((negb w__2) + : bool). + +Definition check_Counteren (csr : mword 12) (p : Privilege) +: M (bool) := + + (match (csr, p) with + | (b__0, Supervisor) => + (if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + read_reg mcounteren_ref >>= fun w__0 : Counteren => + returnm ((eq_vec (_get_Counteren_CY w__0) ((bool_to_bits true) : mword 1)) + : bool) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + read_reg mcounteren_ref >>= fun w__1 : Counteren => + returnm ((eq_vec (_get_Counteren_TM w__1) ((bool_to_bits true) : mword 1)) + : bool) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + read_reg mcounteren_ref >>= fun w__2 : Counteren => + returnm ((eq_vec (_get_Counteren_IR w__2) ((bool_to_bits true) : mword 1)) + : bool) + else + returnm ((match (b__0, Supervisor) with + | (g__37, g__38) => + if ((andb + (zopz0zIzJ_u + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) csr) + (zopz0zIzJ_u csr + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : mword 12)))) + then + false + else true + end) + : bool)) + : M (bool) + | (b__3, User) => + (if ((eq_vec b__3 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + read_reg scounteren_ref >>= fun w__6 : Counteren => + returnm ((eq_vec (_get_Counteren_CY w__6) ((bool_to_bits true) : mword 1)) + : bool) + else if ((eq_vec b__3 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + read_reg scounteren_ref >>= fun w__7 : Counteren => + returnm ((eq_vec (_get_Counteren_TM w__7) ((bool_to_bits true) : mword 1)) + : bool) + else if ((eq_vec b__3 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + read_reg scounteren_ref >>= fun w__8 : Counteren => + returnm ((eq_vec (_get_Counteren_IR w__8) ((bool_to_bits true) : mword 1)) + : bool) + else + returnm ((match (b__3, User) with + | (g__37, g__38) => + if ((andb + (zopz0zIzJ_u + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) csr) + (zopz0zIzJ_u csr + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : mword 12)))) + then + false + else true + end) + : bool)) + : M (bool) + | (g__37, g__38) => + returnm ((if ((andb + (zopz0zIzJ_u (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) + csr) + (zopz0zIzJ_u csr + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : mword 12)))) then + false + else true) + : bool) + end) + : M (bool). + +Definition check_CSR (csr : mword 12) (p : Privilege) (isWrite : bool) +: M (bool) := + + (and_boolM (returnm ((is_CSR_defined csr p) : bool)) + ((and_boolM (returnm ((check_CSR_access (csrAccess csr) (csrPriv csr) p isWrite) : bool)) + ((and_boolM ((check_TVM_SATP csr p) : M (bool)) ((check_Counteren csr p) : M (bool))) + : M (bool))) + : M (bool))) + : M (bool). + +Axiom speculate_conditional : forall (_ : unit) , M (bool). + +Axiom load_reservation : forall (_ : mword 64) , unit. + +Axiom match_reservation : forall (_ : mword 64) , bool. + +Axiom cancel_reservation : forall (_ : unit) , unit. + +Definition exception_delegatee (e : ExceptionType) (p : Privilege) +: M (Privilege) := + + let 'idx := projT1 (num_of_ExceptionType e) in + read_reg medeleg_ref >>= fun w__0 : Medeleg => + let super := access_vec_dec (_get_Medeleg_bits w__0) idx in + read_reg sedeleg_ref >>= fun w__1 : Sedeleg => + let user := access_vec_dec (_get_Sedeleg_bits w__1) idx in + (and_boolM + (read_reg misa_ref >>= fun w__2 : Misa => + returnm ((eq_vec (_get_Misa_S w__2) ((bool_to_bits true) : mword 1)) + : bool)) ((bit_to_bool super) : M (bool))) >>= fun w__4 : bool => + let deleg := if (w__4) then Supervisor else Machine in + returnm ((if ((zopz0zI_u (privLevel_to_bits deleg) (privLevel_to_bits p))) then p + else deleg) + : Privilege). + +Definition findPendingInterrupt (ip : mword 64) +: option InterruptType := + + let ip := Mk_Minterrupts ip in + if ((eq_vec (_get_Minterrupts_MEI ip) ((bool_to_bits true) : mword 1))) then Some (I_M_External) + else if ((eq_vec (_get_Minterrupts_MSI ip) ((bool_to_bits true) : mword 1))) then + Some + (I_M_Software) + else if ((eq_vec (_get_Minterrupts_MTI ip) ((bool_to_bits true) : mword 1))) then + Some + (I_M_Timer) + else if ((eq_vec (_get_Minterrupts_SEI ip) ((bool_to_bits true) : mword 1))) then + Some + (I_S_External) + else if ((eq_vec (_get_Minterrupts_SSI ip) ((bool_to_bits true) : mword 1))) then + Some + (I_S_Software) + else if ((eq_vec (_get_Minterrupts_STI ip) ((bool_to_bits true) : mword 1))) then + Some + (I_S_Timer) + else if ((eq_vec (_get_Minterrupts_UEI ip) ((bool_to_bits true) : mword 1))) then + Some + (I_U_External) + else if ((eq_vec (_get_Minterrupts_USI ip) ((bool_to_bits true) : mword 1))) then + Some + (I_U_Software) + else if ((eq_vec (_get_Minterrupts_UTI ip) ((bool_to_bits true) : mword 1))) then + Some + (I_U_Timer) + else None. + +Definition curInterrupt +(priv : Privilege) (pend : Minterrupts) (enbl : Minterrupts) (delg : Minterrupts) +: M (option ((InterruptType * Privilege))) := + + let en_mip : xlenbits := and_vec (_get_Minterrupts_bits pend) (_get_Minterrupts_bits enbl) in + (if ((eq_vec en_mip (EXTZ 64 (vec_of_bits [B0] : mword 1)))) then + returnm (None + : option ((InterruptType * Privilege))) + else + (or_boolM + (returnm ((neq_vec (privLevel_to_bits priv) ((privLevel_to_bits Machine) : mword 2)) + : bool)) + ((and_boolM + (returnm ((eq_vec (privLevel_to_bits priv) ((privLevel_to_bits Machine) : mword 2)) + : bool)) + (read_reg mstatus_ref >>= fun w__0 : Mstatus => + returnm ((eq_vec (_get_Mstatus_MIE w__0) ((bool_to_bits true) : mword 1)) + : bool))) + : M (bool))) >>= fun eff_mie => + (or_boolM + (returnm ((eq_vec (privLevel_to_bits priv) ((privLevel_to_bits User) : mword 2)) + : bool)) + ((and_boolM + (returnm ((eq_vec (privLevel_to_bits priv) ((privLevel_to_bits Supervisor) : mword 2)) + : bool)) + (read_reg mstatus_ref >>= fun w__2 : Mstatus => + returnm ((eq_vec (_get_Mstatus_SIE w__2) ((bool_to_bits true) : mword 1)) + : bool))) + : M (bool))) >>= fun eff_sie => + let eff_mip := and_vec en_mip (not_vec (_get_Minterrupts_bits delg)) in + let eff_sip := and_vec en_mip (_get_Minterrupts_bits delg) in + (if ((andb eff_mie (neq_vec eff_mip (EXTZ 64 (vec_of_bits [B0] : mword 1))))) then + (match (findPendingInterrupt eff_mip) with + | Some (i) => + let r := (i, Machine) in + returnm ((Some + (r)) + : option ((InterruptType * Privilege))) + | None => + (internal_error + (String.append "non-zero eff_mip=" + (String.append (string_of_bits eff_mip) ", but nothing pending"))) + : M (option ((InterruptType * Privilege))) + end) + : M (option ((InterruptType * Privilege))) + else if ((andb eff_sie (neq_vec eff_sip (EXTZ 64 (vec_of_bits [B0] : mword 1))))) then + (match (findPendingInterrupt eff_sip) with + | Some (i) => + let r := (i, Supervisor) in + returnm ((Some + (r)) + : option ((InterruptType * Privilege))) + | None => + (internal_error + (String.append "non-zero eff_sip=" + (String.append (string_of_bits eff_sip) ", but nothing pending"))) + : M (option ((InterruptType * Privilege))) + end) + : M (option ((InterruptType * Privilege))) + else + let p := + if ((eq_vec (_get_Minterrupts_MTI pend) ((bool_to_bits true) : mword 1))) then "1" + else "0" in + let e := + if ((eq_vec (_get_Minterrupts_MTI enbl) ((bool_to_bits true) : mword 1))) then "1" + else "0" in + let d := + if ((eq_vec (_get_Minterrupts_MTI delg) ((bool_to_bits true) : mword 1))) then "1" + else "0" in + let '_ := + (print_endline + (String.append " MTI: pend=" + (String.append p + (String.append " enbl=" (String.append e (String.append " delg=" d)))))) + : unit in + let eff_mip := and_vec en_mip (not_vec (_get_Minterrupts_bits delg)) in + let eff_sip := and_vec en_mip (_get_Minterrupts_bits delg) in + read_reg mstatus_ref >>= fun w__8 : Mstatus => + read_reg mstatus_ref >>= fun w__9 : Mstatus => + read_reg mstatus_ref >>= fun w__10 : Mstatus => + let '_ := + (print_endline + (String.append "mstatus=" + (String.append (string_of_bits (_get_Mstatus_bits w__8)) + (String.append " mie,sie=" + (String.append (string_of_bits (_get_Mstatus_MIE w__9)) + (String.append "," + (String.append (string_of_bits (_get_Mstatus_SIE w__10)) + (String.append " en_mip=" + (String.append (string_of_bits en_mip) + (String.append " eff_mip=" + (String.append (string_of_bits eff_mip) + (String.append " eff_sip=" (string_of_bits eff_sip))))))))))))) + : unit in + returnm (None + : option ((InterruptType * Privilege)))) + : M (option ((InterruptType * Privilege)))) + : M (option ((InterruptType * Privilege))). + +Definition tval (excinfo : option (mword 64)) +: mword 64 := + + match excinfo with | Some (e) => e | None => EXTZ 64 (vec_of_bits [B0] : mword 1) end. + +Definition rvfi_trap '(tt : unit) : unit := tt. + +Definition handle_trap +(del_priv : Privilege) (intr : bool) (c : mword 4) (pc : mword 64) (info : option (mword 64)) +: M (mword 64) := + + let '_ := (rvfi_trap tt) : unit in + let '_ := + (print_endline + (String.append "handling " + (String.append (if (intr) then "int#" else "exc#") + (String.append (string_of_bits c) + (String.append " at priv " + (String.append ((privLevel_to_str del_priv) : string) + (String.append " with tval " (string_of_bits (tval info))))))))) + : unit in + (match del_priv with + | Machine => + (_set_Mcause_IsInterrupt mcause_ref ((bool_to_bits intr) : mword 1)) >> + (_set_Mcause_Cause mcause_ref (EXTZ 63 c)) >> + read_reg mstatus_ref >>= fun w__0 : Mstatus => + (_set_Mstatus_MPIE mstatus_ref (_get_Mstatus_MIE w__0)) >> + (_set_Mstatus_MIE mstatus_ref ((bool_to_bits false) : mword 1)) >> + read_reg cur_privilege_ref >>= fun w__1 : Privilege => + (_set_Mstatus_MPP mstatus_ref (privLevel_to_bits w__1)) >> + write_reg mtval_ref (tval info) >> + write_reg mepc_ref pc >> + write_reg cur_privilege_ref del_priv >> + read_reg mstatus_ref >>= fun w__2 : Mstatus => + read_reg mstatus_ref >>= fun w__3 : Mstatus => + let '_ := + (print_endline + (String.append "CSR mstatus <- " + (String.append (string_of_bits (_get_Mstatus_bits w__2)) + (String.append " (input: " + (String.append (string_of_bits (_get_Mstatus_bits w__3)) ")"))))) + : unit in + let '_ := (cancel_reservation tt) : unit in + read_reg mtvec_ref >>= fun w__4 : Mtvec => + read_reg mcause_ref >>= fun w__5 : Mcause => + (match (tvec_addr w__4 w__5) with + | Some (epc) => returnm (epc : mword 64) + | None => (internal_error "Invalid mtvec mode") : M (mword 64) + end) + : M (mword 64) + | Supervisor => + (_set_Mcause_IsInterrupt scause_ref ((bool_to_bits intr) : mword 1)) >> + (_set_Mcause_Cause scause_ref (EXTZ 63 c)) >> + read_reg mstatus_ref >>= fun w__8 : Mstatus => + (_set_Mstatus_SPIE mstatus_ref (_get_Mstatus_SIE w__8)) >> + (_set_Mstatus_SIE mstatus_ref ((bool_to_bits false) : mword 1)) >> + read_reg cur_privilege_ref >>= fun w__9 : Privilege => + (match w__9 with + | User => returnm ((bool_to_bits false) : mword 1) + | Supervisor => returnm ((bool_to_bits true) : mword 1) + | Machine => (internal_error "invalid privilege for s-mode trap") : M (mword 1) + end) >>= fun w__11 : mword 1 => + (_set_Mstatus_SPP mstatus_ref w__11) >> + write_reg stval_ref (tval info) >> + write_reg sepc_ref pc >> + write_reg cur_privilege_ref del_priv >> + read_reg mstatus_ref >>= fun w__12 : Mstatus => + read_reg mstatus_ref >>= fun w__13 : Mstatus => + let '_ := + (print_endline + (String.append "CSR mstatus <- " + (String.append (string_of_bits (_get_Mstatus_bits w__12)) + (String.append " (input: " + (String.append (string_of_bits (_get_Mstatus_bits w__13)) ")"))))) + : unit in + let '_ := (cancel_reservation tt) : unit in + read_reg stvec_ref >>= fun w__14 : Mtvec => + read_reg scause_ref >>= fun w__15 : Mcause => + (match (tvec_addr w__14 w__15) with + | Some (epc) => returnm (epc : mword 64) + | None => (internal_error "Invalid stvec mode") : M (mword 64) + end) + : M (mword 64) + | User => (internal_error "the N extension is currently unsupported") : M (mword 64) + end) + : M (mword 64). + +Definition handle_exception (cur_priv : Privilege) (ctl : ctl_result) (pc : mword 64) +: M (mword 64) := + + (match (cur_priv, ctl) with + | (_, CTL_TRAP (e)) => + (exception_delegatee e.(sync_exception_trap) cur_priv) >>= fun del_priv => + let '_ := + (print_endline + (String.append "trapping from " + (String.append ((privLevel_to_str cur_priv) : string) + (String.append " to " + (String.append ((privLevel_to_str del_priv) : string) + (String.append " to handle " + ((exceptionType_to_str e.(sync_exception_trap)) + : string))))))) + : unit in + (handle_trap del_priv false ((exceptionType_to_bits e.(sync_exception_trap)) : mword 4) pc + e.(sync_exception_excinfo)) + : M (mword 64) + | (_, CTL_MRET (tt)) => + read_reg cur_privilege_ref >>= fun prev_priv => + read_reg mstatus_ref >>= fun w__1 : Mstatus => + (_set_Mstatus_MIE mstatus_ref (_get_Mstatus_MPIE w__1)) >> + (_set_Mstatus_MPIE mstatus_ref ((bool_to_bits true) : mword 1)) >> + read_reg mstatus_ref >>= fun w__2 : Mstatus => + write_reg cur_privilege_ref (privLevel_of_bits (_get_Mstatus_MPP w__2)) >> + (_set_Mstatus_MPP mstatus_ref (privLevel_to_bits User)) >> + read_reg mstatus_ref >>= fun w__3 : Mstatus => + read_reg mstatus_ref >>= fun w__4 : Mstatus => + let '_ := + (print_endline + (String.append "CSR mstatus <- " + (String.append (string_of_bits (_get_Mstatus_bits w__3)) + (String.append " (input: " + (String.append (string_of_bits (_get_Mstatus_bits w__4)) ")"))))) + : unit in + read_reg cur_privilege_ref >>= fun w__5 : Privilege => + let '_ := + (print_endline + (String.append "ret-ing from " + (String.append ((privLevel_to_str prev_priv) : string) + (String.append " to " ((privLevel_to_str w__5) : string))))) + : unit in + let '_ := (cancel_reservation tt) : unit in + ((read_reg mepc_ref) : M (mword 64)) >>= fun w__6 : xlenbits => + (pc_alignment_mask tt) >>= fun w__7 : mword 64 => returnm ((and_vec w__6 w__7) : mword 64) + | (_, CTL_SRET (tt)) => + read_reg cur_privilege_ref >>= fun prev_priv => + read_reg mstatus_ref >>= fun w__8 : Mstatus => + (_set_Mstatus_SIE mstatus_ref (_get_Mstatus_SPIE w__8)) >> + (_set_Mstatus_SPIE mstatus_ref ((bool_to_bits true) : mword 1)) >> + read_reg mstatus_ref >>= fun w__9 : Mstatus => + write_reg + cur_privilege_ref + (if ((eq_vec (_get_Mstatus_SPP w__9) ((bool_to_bits true) : mword 1))) then Supervisor + else User) >> + (_set_Mstatus_SPP mstatus_ref ((bool_to_bits false) : mword 1)) >> + read_reg mstatus_ref >>= fun w__10 : Mstatus => + read_reg mstatus_ref >>= fun w__11 : Mstatus => + let '_ := + (print_endline + (String.append "CSR mstatus <- " + (String.append (string_of_bits (_get_Mstatus_bits w__10)) + (String.append " (input: " + (String.append (string_of_bits (_get_Mstatus_bits w__11)) ")"))))) + : unit in + read_reg cur_privilege_ref >>= fun w__12 : Privilege => + let '_ := + (print_endline + (String.append "ret-ing from " + (String.append ((privLevel_to_str prev_priv) : string) + (String.append " to " ((privLevel_to_str w__12) : string))))) + : unit in + let '_ := (cancel_reservation tt) : unit in + ((read_reg sepc_ref) : M (mword 64)) >>= fun w__13 : xlenbits => + (pc_alignment_mask tt) >>= fun w__14 : mword 64 => + returnm ((and_vec w__13 w__14) + : mword 64) + end) + : M (mword 64). + +Definition handle_mem_exception (addr : mword 64) (e : ExceptionType) +: M (unit) := + + let t : sync_exception := + {| sync_exception_trap := e; + sync_exception_excinfo := (Some (addr)) |} in + read_reg cur_privilege_ref >>= fun w__0 : Privilege => + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : xlenbits => + (handle_exception w__0 (CTL_TRAP (t)) w__1) >>= fun w__2 : mword 64 => + write_reg nextPC_ref w__2 + : M (unit). + +Definition handle_interrupt (i : InterruptType) (del_priv : Privilege) +: M (unit) := + + ((read_reg PC_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + (handle_trap del_priv true ((interruptType_to_bits i) : mword 4) w__0 None) >>= fun w__1 : mword 64 => + write_reg nextPC_ref w__1 + : M (unit). + +Definition init_sys '(tt : unit) +: M (unit) := + + write_reg cur_privilege_ref Machine >> + write_reg mhartid_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> + (_set_Misa_MXL misa_ref (arch_to_bits RV64)) >> + (_set_Misa_A misa_ref ((bool_to_bits true) : mword 1)) >> + (_set_Misa_C misa_ref ((bool_to_bits true) : mword 1)) >> + (_set_Misa_I misa_ref ((bool_to_bits true) : mword 1)) >> + (_set_Misa_M misa_ref ((bool_to_bits true) : mword 1)) >> + (_set_Misa_U misa_ref ((bool_to_bits true) : mword 1)) >> + (_set_Misa_S misa_ref ((bool_to_bits true) : mword 1)) >> + read_reg misa_ref >>= fun w__0 : Misa => + (_set_Mstatus_SXL mstatus_ref (_get_Misa_MXL w__0)) >> + read_reg misa_ref >>= fun w__1 : Misa => + (_set_Mstatus_UXL mstatus_ref (_get_Misa_MXL w__1)) >> + (_set_Mstatus_SD mstatus_ref ((bool_to_bits false) : mword 1)) >> + (_set_Minterrupts_bits mip_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))) >> + (_set_Minterrupts_bits mie_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))) >> + (_set_Minterrupts_bits mideleg_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))) >> + (_set_Medeleg_bits medeleg_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))) >> + (_set_Mtvec_bits mtvec_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))) >> + (_set_Mcause_bits mcause_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))) >> + write_reg mepc_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> + write_reg mtval_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> + write_reg mscratch_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> + write_reg mcycle_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> + write_reg mtime_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> + (_set_Counteren_bits mcounteren_ref (EXTZ 32 (vec_of_bits [B0] : mword 1))) >> + write_reg minstret_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> + write_reg minstret_written_ref false >> + read_reg mstatus_ref >>= fun w__2 : Mstatus => + returnm ((print_endline + (String.append "CSR mstatus <- " + (String.append (string_of_bits (_get_Mstatus_bits w__2)) + (String.append " (input: " + (String.append + (string_of_bits ((EXTZ 64 (vec_of_bits [B0] : mword 1)) : xlenbits)) + ")"))))) + : unit). + +Axiom plat_ram_base : forall (_ : unit) , mword 64. + +Axiom plat_ram_size : forall (_ : unit) , mword 64. + +Axiom plat_enable_dirty_update : forall (_ : unit) , bool. + +Axiom plat_enable_misaligned_access : forall (_ : unit) , bool. + +Axiom plat_mtval_has_illegal_inst_bits : forall (_ : unit) , bool. + +Axiom plat_rom_base : forall (_ : unit) , mword 64. + +Axiom plat_rom_size : forall (_ : unit) , mword 64. + +Axiom plat_clint_base : forall (_ : unit) , mword 64. + +Axiom plat_clint_size : forall (_ : unit) , mword 64. + +Axiom plat_htif_tohost : forall (_ : unit) , mword 64. + +Definition phys_mem_segments '(tt : unit) +: list ((mword 64 * mword 64)) := + + (plat_rom_base tt, plat_rom_size tt) :: (plat_ram_base tt, plat_ram_size tt) :: []. + +Definition within_phys_mem (addr : mword 64) (width : Z) +: bool := + + let ram_base := plat_ram_base tt in + let rom_base := plat_rom_base tt in + let ram_size := plat_ram_size tt in + let rom_size := plat_rom_size tt in + if ((andb (zopz0zIzJ_u ram_base addr) + (zopz0zIzJ_u (add_vec_int addr width) (add_vec ram_base ram_size)))) then + true + else if ((andb (zopz0zIzJ_u rom_base addr) + (zopz0zIzJ_u (add_vec_int addr width) (add_vec rom_base rom_size)))) then + true + else + let '_ := + (print_endline + (String.append "within_phys_mem: " + (String.append (string_of_bits addr) " not within phys-mem:"))) + : unit in + let '_ := (print_endline (String.append " plat_rom_base: " (string_of_bits rom_base))) : unit in + let '_ := (print_endline (String.append " plat_rom_size: " (string_of_bits rom_size))) : unit in + let '_ := (print_endline (String.append " plat_ram_base: " (string_of_bits ram_base))) : unit in + let '_ := (print_endline (String.append " plat_ram_size: " (string_of_bits ram_size))) : unit in + false. + +Definition within_clint (addr : mword 64) (width : Z) +: bool := + + andb (zopz0zIzJ_u (plat_clint_base tt) addr) + (zopz0zIzJ_u (add_vec_int addr width) (add_vec (plat_clint_base tt) (plat_clint_size tt))). + +Definition within_htif_writable (addr : mword 64) (width : Z) +: bool := + + eq_vec (plat_htif_tohost tt) addr. + +Definition within_htif_readable (addr : mword 64) (width : Z) +: bool := + + eq_vec (plat_htif_tohost tt) addr. + +Axiom plat_insns_per_tick : forall (_ : unit) , Z. + +Definition MSIP_BASE : xlenbits := +(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64). +Hint Unfold MSIP_BASE : sail. +Definition MTIMECMP_BASE : xlenbits := +(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64). +Hint Unfold MTIMECMP_BASE : sail. +Definition MTIME_BASE : xlenbits := +(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0; + B0] + : mword 64). +Hint Unfold MTIME_BASE : sail. +Definition clint_load (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + let addr := sub_vec addr (plat_clint_base tt) in + (if sumbool_of_bool ((andb (eq_vec addr MSIP_BASE) (orb (Z.eqb width 8) (Z.eqb width 4)))) then + read_reg mip_ref >>= fun w__0 : Minterrupts => + let '_ := + (print_endline + (String.append "clint[" + (String.append (string_of_bits addr) + (String.append "] -> " (string_of_bits (_get_Minterrupts_MSI w__0)))))) + : unit in + read_reg mip_ref >>= fun w__1 : Minterrupts => + returnm ((MemValue + (zero_extend (_get_Minterrupts_MSI w__1) (Z.mul 8 width))) + : MemoryOpResult (mword (8 * width))) + else if sumbool_of_bool ((andb (eq_vec addr MTIMECMP_BASE) (Z.eqb width 8))) then + ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__2 : xlenbits => + let '_ := + (print_endline + (String.append "clint[" + (String.append (string_of_bits addr) (String.append "] -> " (string_of_bits w__2))))) + : unit in + ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__3 : xlenbits => + returnm ((MemValue + (zero_extend w__3 _)) + : MemoryOpResult (mword (8 * width))) + else if sumbool_of_bool ((andb (eq_vec addr MTIME_BASE) (Z.eqb width 8))) then + ((read_reg mtime_ref) : M (mword 64)) >>= fun w__4 : xlenbits => + let '_ := + (print_endline + (String.append "clint[" + (String.append (string_of_bits addr) (String.append "] -> " (string_of_bits w__4))))) + : unit in + ((read_reg mtime_ref) : M (mword 64)) >>= fun w__5 : xlenbits => + returnm ((MemValue + (zero_extend w__5 _)) + : MemoryOpResult (mword (8 * width))) + else + let '_ := + (print_endline + (String.append "clint[" (String.append (string_of_bits addr) "] -> "))) + : unit in + returnm ((MemException + (E_Load_Access_Fault)) + : MemoryOpResult (mword (8 * width)))) + : M (MemoryOpResult (mword (8 * width))). + +Definition clint_dispatch '(tt : unit) +: M (unit) := + + ((read_reg mtime_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + let '_ := (print_endline (String.append "clint::tick mtime <- " (string_of_bits w__0))) : unit in + (_set_Minterrupts_MTI mip_ref ((bool_to_bits false) : mword 1)) >> + ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__1 : xlenbits => + ((read_reg mtime_ref) : M (mword 64)) >>= fun w__2 : xlenbits => + (if ((zopz0zIzJ_u w__1 w__2)) then + ((read_reg mtime_ref) : M (mword 64)) >>= fun w__3 : xlenbits => + let '_ := + (print_endline (String.append " clint timer pending at mtime " (string_of_bits w__3))) + : unit in + (_set_Minterrupts_MTI mip_ref ((bool_to_bits true) : mword 1)) + : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition clint_store (addr : mword 64) (width : Z) (data : mword (8 * width)) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult bool) := + + let addr := sub_vec addr (plat_clint_base tt) in + (if sumbool_of_bool ((andb (eq_vec addr MSIP_BASE) (orb (Z.eqb width 8) (Z.eqb width 4)))) then + (cast_unit_vec (access_vec_dec data 0)) >>= fun w__0 : mword 1 => + let '_ := + (print_endline + (String.append "clint[" + (String.append (string_of_bits addr) + (String.append "] <- " + (String.append (string_of_bits data) + (String.append " (mip.MSI <- " (String.append (string_of_bits w__0) ")"))))))) + : unit in + (cast_unit_vec (access_vec_dec data 0)) >>= fun w__1 : mword 1 => + (_set_Minterrupts_MSI mip_ref + ((bool_to_bits (eq_vec w__1 (vec_of_bits [B1] : mword 1))) + : mword 1)) >> + (clint_dispatch tt) >> returnm ((MemValue (true)) : MemoryOpResult bool) + else if sumbool_of_bool ((andb (eq_vec addr MTIMECMP_BASE) (Z.eqb width 8))) then + let '_ := + (print_endline + (String.append "clint[" + (String.append (string_of_bits addr) + (String.append "] <- " (String.append (string_of_bits data) " (mtimecmp)"))))) + : unit in + write_reg mtimecmp_ref (zero_extend data 64) >> + (clint_dispatch tt) >> returnm ((MemValue (true)) : MemoryOpResult bool) + else + let '_ := + (print_endline + (String.append "clint[" + (String.append (string_of_bits addr) + (String.append "] <- " (String.append (string_of_bits data) " ()"))))) + : unit in + returnm ((MemException + (E_SAMO_Access_Fault)) + : MemoryOpResult bool)) + : M (MemoryOpResult bool). + +Definition tick_clock '(tt : unit) +: M (unit) := + + ((read_reg mcycle_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + write_reg mcycle_ref (add_vec_int w__0 1) >> + ((read_reg mtime_ref) : M (mword 64)) >>= fun w__1 : xlenbits => + write_reg mtime_ref (add_vec_int w__1 1) >> (clint_dispatch tt) : M (unit). + +Axiom plat_term_write : forall (_ : mword 8) , unit. + +Axiom plat_term_read : forall (_ : unit) , mword 8. + +Definition Mk_htif_cmd (v : mword 64) +: htif_cmd := + + {| htif_cmd_htif_cmd_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_htif_cmd_bits (v : htif_cmd) +: mword 64 := + + subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 63 0. + +Definition _set_htif_cmd_bits (r_ref : register_ref regstate register_value htif_cmd) (v : mword 64) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + htif_cmd_htif_cmd_chunk_0 := + (update_subrange_vec_dec r.(htif_cmd_htif_cmd_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : htif_cmd in + write_reg r_ref r + : M (unit). + +Definition _update_htif_cmd_bits (v : htif_cmd) (x : mword 64) +: htif_cmd := + + {[ v with + htif_cmd_htif_cmd_chunk_0 := + (update_subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_htif_cmd_device (v : htif_cmd) +: mword 8 := + + subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 63 56. + +Definition _set_htif_cmd_device +(r_ref : register_ref regstate register_value htif_cmd) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + htif_cmd_htif_cmd_chunk_0 := + (update_subrange_vec_dec r.(htif_cmd_htif_cmd_chunk_0) 63 56 (subrange_vec_dec v 7 0)) ]} + : htif_cmd in + write_reg r_ref r + : M (unit). + +Definition _update_htif_cmd_device (v : htif_cmd) (x : mword 8) +: htif_cmd := + + {[ v with + htif_cmd_htif_cmd_chunk_0 := + (update_subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 63 56 (subrange_vec_dec x 7 0)) ]}. + +Definition _get_htif_cmd_cmd (v : htif_cmd) +: mword 8 := + + subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 55 48. + +Definition _set_htif_cmd_cmd (r_ref : register_ref regstate register_value htif_cmd) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + htif_cmd_htif_cmd_chunk_0 := + (update_subrange_vec_dec r.(htif_cmd_htif_cmd_chunk_0) 55 48 (subrange_vec_dec v 7 0)) ]} + : htif_cmd in + write_reg r_ref r + : M (unit). + +Definition _update_htif_cmd_cmd (v : htif_cmd) (x : mword 8) +: htif_cmd := + + {[ v with + htif_cmd_htif_cmd_chunk_0 := + (update_subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 55 48 (subrange_vec_dec x 7 0)) ]}. + +Definition _get_htif_cmd_payload (v : htif_cmd) +: mword 48 := + + subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 47 0. + +Definition _set_htif_cmd_payload +(r_ref : register_ref regstate register_value htif_cmd) (v : mword 48) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + htif_cmd_htif_cmd_chunk_0 := + (update_subrange_vec_dec r.(htif_cmd_htif_cmd_chunk_0) 47 0 (subrange_vec_dec v 47 0)) ]} + : htif_cmd in + write_reg r_ref r + : M (unit). + +Definition _update_htif_cmd_payload (v : htif_cmd) (x : mword 48) +: htif_cmd := + + {[ v with + htif_cmd_htif_cmd_chunk_0 := + (update_subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 47 0 (subrange_vec_dec x 47 0)) ]}. + +Definition htif_load (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + let '_ := + (print_endline + (String.append "htif[" + (String.append (string_of_bits addr) (String.append "] -> " (string_of_bits w__0))))) + : unit in + (if sumbool_of_bool ((Z.eqb width 8)) then + ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__1 : xlenbits => + returnm ((MemValue + (zero_extend w__1 _)) + : MemoryOpResult (mword (8 * width))) + else returnm ((MemException (E_Load_Access_Fault)) : MemoryOpResult (mword (8 * width)))) + : M (MemoryOpResult (mword (8 * width))). + +Definition htif_store (addr : mword 64) (width : Z) (data : mword (8 * width)) +`{ArithFact ((0 + 1) <= width /\ width <= 8)} +: M (MemoryOpResult bool) := + + let '_ := + (print_endline + (String.append "htif[" + (String.append (string_of_bits addr) (String.append "] <- " (string_of_bits data))))) + : unit in + let cbits : xlenbits := EXTZ 64 data in + write_reg htif_tohost_ref cbits >> + let cmd := Mk_htif_cmd cbits in + let b__0 := _get_htif_cmd_device cmd in + (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8))) then + let '_ := + (print_endline + (String.append "htif-syscall-proxy cmd: " (string_of_bits (_get_htif_cmd_payload cmd)))) + : unit in + (cast_unit_vec (access_vec_dec (_get_htif_cmd_payload cmd) 0)) >>= fun w__0 : mword 1 => + (if ((eq_vec w__0 (vec_of_bits [B1] : mword 1))) then + write_reg htif_done_ref true >> + write_reg + htif_exit_code_ref + ((shift_bits_right (zero_extend (_get_htif_cmd_payload cmd) xlen) + (vec_of_bits [B0;B1] : mword 2)) + : xlenbits) + : M (unit) + else returnm (tt : unit)) + : M (unit) + else + returnm ((if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : mword 8))) then + let '_ := + (print_endline + (String.append "htif-term cmd: " (string_of_bits (_get_htif_cmd_payload cmd)))) + : unit in + let b__2 := _get_htif_cmd_cmd cmd in + if ((eq_vec b__2 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8))) then tt + else if ((eq_vec b__2 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : mword 8))) then + plat_term_write (subrange_vec_dec (_get_htif_cmd_payload cmd) 7 0) + else print_endline (String.append "Unknown term cmd: " (string_of_bits b__2)) + else print_endline (String.append "htif-???? cmd: " (string_of_bits data))) + : unit)) >> + returnm ((MemValue + (true)) + : MemoryOpResult bool). + +Definition htif_tick '(tt : unit) +: M (unit) := + + ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + let '_ := (print_endline (String.append "htif::tick " (string_of_bits w__0))) : unit in + write_reg htif_tohost_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) + : M (unit). + +Definition within_mmio_readable (addr : mword 64) (width : Z) +: bool := + + orb (within_clint addr width) (andb (within_htif_readable addr width) (Z.leb 1 width)). + +Definition within_mmio_writable (addr : mword 64) (width : Z) +: bool := + + orb (within_clint addr width) (andb (within_htif_writable addr width) (Z.leb width 8)). + +Definition mmio_read (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + (if ((within_clint addr width)) then + (clint_load addr width) + : M (MemoryOpResult (mword (8 * width))) + else if sumbool_of_bool ((andb (within_htif_readable addr width) (Z.leb 1 width))) then + (htif_load addr width) + : M (MemoryOpResult (mword (8 * width))) + else returnm ((MemException (E_Load_Access_Fault)) : MemoryOpResult (mword (8 * width)))) + : M (MemoryOpResult (mword (8 * width))). + +Definition mmio_write (addr : mword 64) (width : Z) (data : mword (8 * width)) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult bool) := + + (if ((within_clint addr width)) then (clint_store addr width data) : M (MemoryOpResult bool) + else if sumbool_of_bool ((andb (within_htif_writable addr width) (Z.leb width 8))) then + (htif_store addr width data) + : M (MemoryOpResult bool) + else returnm ((MemException (E_SAMO_Access_Fault)) : MemoryOpResult bool)) + : M (MemoryOpResult bool). + +Definition init_platform '(tt : unit) +: M (unit) := + + write_reg htif_tohost_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> + write_reg htif_done_ref false >> + write_reg htif_exit_code_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) + : M (unit). + +Definition tick_platform '(tt : unit) +: M (unit) := + + let '_ := (cancel_reservation tt) : unit in + (htif_tick tt) + : M (unit). + +Definition handle_illegal '(tt : unit) +: M (unit) := + + (if ((plat_mtval_has_illegal_inst_bits tt)) then + ((read_reg instbits_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + returnm ((Some + (w__0)) + : option (mword 64)) + else returnm (None : option (mword 64))) >>= fun info => + let t : sync_exception := + {| sync_exception_trap := E_Illegal_Instr; + sync_exception_excinfo := info |} in + read_reg cur_privilege_ref >>= fun w__1 : Privilege => + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : xlenbits => + (handle_exception w__1 (CTL_TRAP (t)) w__2) >>= fun w__3 : mword 64 => + write_reg nextPC_ref w__3 + : M (unit). + +Definition platform_wfi '(tt : unit) +: M (unit) := + + ((read_reg mtime_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__1 : xlenbits => + (if ((zopz0zI_u w__0 w__1)) then + ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__2 : xlenbits => + write_reg mtime_ref w__2 >> + ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__3 : xlenbits => + write_reg mcycle_ref w__3 + : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition is_aligned_addr (addr : mword 64) (width : Z) +: bool := + + Z.eqb (modulus (projT1 (uint addr)) width) 0. + +Definition phys_mem_read +(t : ReadType) (addr : mword 64) (width : Z) (aq : bool) (rl : bool) (res : bool) +`{ArithFact (width >= 0)} +: M (MemoryOpResult (mword (8 * width))) := + + (__RISCV_read addr width aq rl res) >>= fun w__0 : option (mword (8 * width)) => + returnm ((match (t, w__0) with + | (Instruction, None) => MemException (E_Fetch_Access_Fault) + | (Data, None) => MemException (E_Load_Access_Fault) + | (_, Some (v)) => + let '_ := + (print_endline + (String.append "mem[" + (String.append ((readType_to_str t) : string) + (String.append "," + (String.append (string_of_bits addr) + (String.append "] -> " (string_of_bits v))))))) + : unit in + MemValue + (v) + end) + : MemoryOpResult (mword (8 * width))). + +Definition checked_mem_read +(t : ReadType) (addr : mword 64) (width : Z) (aq : bool) (rl : bool) (res : bool) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + (if ((andb (generic_eq ((readType_to_str t) : string) ((readType_to_str Data) : string)) + (within_mmio_readable addr width))) then + (mmio_read addr width) + : M (MemoryOpResult (mword (8 * width))) + else if ((within_phys_mem addr width)) then + (phys_mem_read t addr width aq rl res) + : M (MemoryOpResult (mword (8 * width))) + else returnm ((MemException (E_Load_Access_Fault)) : MemoryOpResult (mword (8 * width)))) + : M (MemoryOpResult (mword (8 * width))). + +Definition MEMr (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + (checked_mem_read Data addr width false false false) + : M (MemoryOpResult (mword (8 * width))). + +Definition MEMr_acquire (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + (checked_mem_read Data addr width true false false) + : M (MemoryOpResult (mword (8 * width))). + +Definition MEMr_strong_acquire (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + (checked_mem_read Data addr width true true false) + : M (MemoryOpResult (mword (8 * width))). + +Definition MEMr_reserved (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + (checked_mem_read Data addr width false false true) + : M (MemoryOpResult (mword (8 * width))). + +Definition MEMr_reserved_acquire (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + (checked_mem_read Data addr width true false true) + : M (MemoryOpResult (mword (8 * width))). + +Definition MEMr_reserved_strong_acquire (addr : mword 64) (width : Z) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + (checked_mem_read Data addr width true true true) + : M (MemoryOpResult (mword (8 * width))). + +Definition rvfi_read (addr : mword 64) (width : Z) (value : MemoryOpResult (mword (8 * width))) +`{ArithFact (width >= (0 + 1))} +: unit := + + tt. + +Definition mem_read (addr : mword 64) (width : Z) (aq : bool) (rl : bool) (res : bool) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + (if ((andb (orb aq res) (negb (is_aligned_addr addr width)))) then + returnm ((MemException + (E_Load_Addr_Align)) + : MemoryOpResult (mword (8 * width))) + else + (match (aq, rl, res) with + | (false, false, false) => + (checked_mem_read Data addr width false false false) + : M (MemoryOpResult (mword (8 * width))) + | (true, false, false) => (MEMr_acquire addr width) : M (MemoryOpResult (mword (8 * width))) + | (false, false, true) => + (MEMr_reserved addr width) : M (MemoryOpResult (mword (8 * width))) + | (true, false, true) => + (MEMr_reserved_acquire addr width) : M (MemoryOpResult (mword (8 * width))) + | (false, true, false) => + (throw (Error_not_implemented ("load.rl"))) : M (MemoryOpResult (mword (8 * width))) + | (true, true, false) => + (MEMr_strong_acquire addr width) : M (MemoryOpResult (mword (8 * width))) + | (false, true, true) => + (throw (Error_not_implemented ("lr.rl"))) : M (MemoryOpResult (mword (8 * width))) + | (true, true, true) => + (MEMr_reserved_strong_acquire addr width) : M (MemoryOpResult (mword (8 * width))) + end) + : M (MemoryOpResult (mword (8 * width)))) >>= fun result : MemoryOpResult (bits (8 * width)) => + let '_ := (rvfi_read addr width result) : unit in + returnm (result + : MemoryOpResult (mword (8 * width))). + +Definition mem_write_ea (addr : mword 64) (width : Z) (aq : bool) (rl : bool) (con : bool) +: M (MemoryOpResult unit) := + + (if ((andb (orb rl con) (negb (is_aligned_addr addr width)))) then + returnm ((MemException + (E_SAMO_Addr_Align)) + : MemoryOpResult unit) + else + (match (aq, rl, con) with + | (false, false, false) => + (MEMea addr width) >> returnm ((MemValue (tt)) : MemoryOpResult unit) + | (false, true, false) => + (MEMea_release addr width) >> returnm ((MemValue (tt)) : MemoryOpResult unit) + | (false, false, true) => + (MEMea_conditional addr width) >> returnm ((MemValue (tt)) : MemoryOpResult unit) + | (false, true, true) => + (MEMea_conditional_release addr width) >> returnm ((MemValue (tt)) : MemoryOpResult unit) + | (true, false, false) => + (throw (Error_not_implemented ("store.aq"))) : M (MemoryOpResult unit) + | (true, true, false) => + (MEMea_strong_release addr width) >> returnm ((MemValue (tt)) : MemoryOpResult unit) + | (true, false, true) => (throw (Error_not_implemented ("sc.aq"))) : M (MemoryOpResult unit) + | (true, true, true) => + (MEMea_conditional_strong_release addr width) >> + returnm ((MemValue + (tt)) + : MemoryOpResult unit) + end) + : M (MemoryOpResult unit)) + : M (MemoryOpResult unit). + +Definition phys_mem_write (addr : mword 64) (width : Z) (data : mword (8 * width)) +: M (MemoryOpResult bool) := + + let '_ := + (print_endline + (String.append "mem[" + (String.append (string_of_bits addr) (String.append "] <- " (string_of_bits data))))) + : unit in + (__RISCV_write addr width data) >>= fun w__0 : bool => + returnm ((MemValue + (w__0)) + : MemoryOpResult bool). + +Definition checked_mem_write (addr : mword 64) (width : Z) (data : mword (8 * width)) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult bool) := + + (if ((within_mmio_writable addr width)) then + (mmio_write addr width data) + : M (MemoryOpResult bool) + else if ((within_phys_mem addr width)) then + (phys_mem_write addr width data) + : M (MemoryOpResult bool) + else returnm ((MemException (E_SAMO_Access_Fault)) : MemoryOpResult bool)) + : M (MemoryOpResult bool). + +Definition MEMval (addr : mword 64) (width : Z) (data : mword (8 * width)) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult bool) := + + (checked_mem_write addr width data) + : M (MemoryOpResult bool). + +Definition MEMval_release (addr : mword 64) (width : Z) (data : mword (8 * width)) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult bool) := + + (checked_mem_write addr width data) + : M (MemoryOpResult bool). + +Definition MEMval_strong_release (addr : mword 64) (width : Z) (data : mword (8 * width)) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult bool) := + + (checked_mem_write addr width data) + : M (MemoryOpResult bool). + +Definition MEMval_conditional (addr : mword 64) (width : Z) (data : mword (8 * width)) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult bool) := + + (checked_mem_write addr width data) + : M (MemoryOpResult bool). + +Definition MEMval_conditional_release (addr : mword 64) (width : Z) (data : mword (8 * width)) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult bool) := + + (checked_mem_write addr width data) + : M (MemoryOpResult bool). + +Definition MEMval_conditional_strong_release +(addr : mword 64) (width : Z) (data : mword (8 * width)) `{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult bool) := + + (checked_mem_write addr width data) + : M (MemoryOpResult bool). + +Definition rvfi_write (addr : mword 64) (width : Z) (value : mword (8 * width)) +`{ArithFact (width >= (0 + 1))} +: unit := + + tt. + +Definition mem_write_value +(addr : mword 64) (width : Z) (value : mword (8 * width)) (aq : bool) (rl : bool) (con : bool) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult bool) := + + let '_ := (rvfi_write addr width value) : unit in + (if ((andb (orb rl con) (negb (is_aligned_addr addr width)))) then + returnm ((MemException + (E_SAMO_Addr_Align)) + : MemoryOpResult bool) + else + (match (aq, rl, con) with + | (false, false, false) => (checked_mem_write addr width value) : M (MemoryOpResult bool) + | (false, true, false) => (MEMval_release addr width value) : M (MemoryOpResult bool) + | (false, false, true) => (MEMval_conditional addr width value) : M (MemoryOpResult bool) + | (false, true, true) => + (MEMval_conditional_release addr width value) : M (MemoryOpResult bool) + | (true, false, false) => + (throw (Error_not_implemented ("store.aq"))) : M (MemoryOpResult bool) + | (true, true, false) => (MEMval_strong_release addr width value) : M (MemoryOpResult bool) + | (true, false, true) => (throw (Error_not_implemented ("sc.aq"))) : M (MemoryOpResult bool) + | (true, true, true) => + (MEMval_conditional_strong_release addr width value) : M (MemoryOpResult bool) + end) + : M (MemoryOpResult bool)) + : M (MemoryOpResult bool). + +Definition PAGESIZE_BITS := 12. +Hint Unfold PAGESIZE_BITS : sail. +Definition Mk_PTE_Bits (v : mword 8) +: PTE_Bits := + + {| PTE_Bits_PTE_Bits_chunk_0 := (subrange_vec_dec v 7 0) |}. + +Definition _get_PTE_Bits_bits (v : PTE_Bits) +: mword 8 := + + subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 7 0. + +Definition _set_PTE_Bits_bits (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 7 0 (subrange_vec_dec v 7 0)) ]} + : PTE_Bits in + write_reg r_ref r + : M (unit). + +Definition _update_PTE_Bits_bits (v : PTE_Bits) (x : mword 8) +: PTE_Bits := + + {[ v with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}. + +Definition _get_PTE_Bits_D (v : PTE_Bits) +: mword 1 := + + subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 7 7. + +Definition _set_PTE_Bits_D (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} + : PTE_Bits in + write_reg r_ref r + : M (unit). + +Definition _update_PTE_Bits_D (v : PTE_Bits) (x : mword 1) +: PTE_Bits := + + {[ v with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_PTE_Bits_A (v : PTE_Bits) +: mword 1 := + + subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 6 6. + +Definition _set_PTE_Bits_A (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]} + : PTE_Bits in + write_reg r_ref r + : M (unit). + +Definition _update_PTE_Bits_A (v : PTE_Bits) (x : mword 1) +: PTE_Bits := + + {[ v with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_PTE_Bits_G (v : PTE_Bits) +: mword 1 := + + subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 5 5. + +Definition _set_PTE_Bits_G (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} + : PTE_Bits in + write_reg r_ref r + : M (unit). + +Definition _update_PTE_Bits_G (v : PTE_Bits) (x : mword 1) +: PTE_Bits := + + {[ v with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_PTE_Bits_U (v : PTE_Bits) +: mword 1 := + + subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 4 4. + +Definition _set_PTE_Bits_U (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} + : PTE_Bits in + write_reg r_ref r + : M (unit). + +Definition _update_PTE_Bits_U (v : PTE_Bits) (x : mword 1) +: PTE_Bits := + + {[ v with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_PTE_Bits_X (v : PTE_Bits) +: mword 1 := + + subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 3 3. + +Definition _set_PTE_Bits_X (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]} + : PTE_Bits in + write_reg r_ref r + : M (unit). + +Definition _update_PTE_Bits_X (v : PTE_Bits) (x : mword 1) +: PTE_Bits := + + {[ v with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_PTE_Bits_W (v : PTE_Bits) +: mword 1 := + + subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 2 2. + +Definition _set_PTE_Bits_W (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]} + : PTE_Bits in + write_reg r_ref r + : M (unit). + +Definition _update_PTE_Bits_W (v : PTE_Bits) (x : mword 1) +: PTE_Bits := + + {[ v with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_PTE_Bits_R (v : PTE_Bits) +: mword 1 := + + subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 1 1. + +Definition _set_PTE_Bits_R (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : PTE_Bits in + write_reg r_ref r + : M (unit). + +Definition _update_PTE_Bits_R (v : PTE_Bits) (x : mword 1) +: PTE_Bits := + + {[ v with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_PTE_Bits_V (v : PTE_Bits) +: mword 1 := + + subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 0 0. + +Definition _set_PTE_Bits_V (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : PTE_Bits in + write_reg r_ref r + : M (unit). + +Definition _update_PTE_Bits_V (v : PTE_Bits) (x : mword 1) +: PTE_Bits := + + {[ v with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition isPTEPtr (p : mword 8) +: bool := + + let a := Mk_PTE_Bits p in + andb (eq_vec (_get_PTE_Bits_R a) ((bool_to_bits false) : mword 1)) + (andb (eq_vec (_get_PTE_Bits_W a) ((bool_to_bits false) : mword 1)) + (eq_vec (_get_PTE_Bits_X a) ((bool_to_bits false) : mword 1))). + +Definition isInvalidPTE (p : mword 8) +: bool := + + let a := Mk_PTE_Bits p in + orb (eq_vec (_get_PTE_Bits_V a) ((bool_to_bits false) : mword 1)) + (andb (eq_vec (_get_PTE_Bits_W a) ((bool_to_bits true) : mword 1)) + (eq_vec (_get_PTE_Bits_R a) ((bool_to_bits false) : mword 1))). + +Definition checkPTEPermission +(ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) (p : PTE_Bits) +: M (bool) := + + (match (ac, priv) with + | (Read, User) => + returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits true) : mword 1)) + (orb (eq_vec (_get_PTE_Bits_R p) ((bool_to_bits true) : mword 1)) + (andb (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)) mxr))) + : bool) + | (Write, User) => + returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits true) : mword 1)) + (eq_vec (_get_PTE_Bits_W p) ((bool_to_bits true) : mword 1))) + : bool) + | (ReadWrite, User) => + returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits true) : mword 1)) + (andb (eq_vec (_get_PTE_Bits_W p) ((bool_to_bits true) : mword 1)) + (orb (eq_vec (_get_PTE_Bits_R p) ((bool_to_bits true) : mword 1)) + (andb (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)) mxr)))) + : bool) + | (Execute, User) => + returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits true) : mword 1)) + (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1))) + : bool) + | (Read, Supervisor) => + returnm ((andb (orb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits false) : mword 1)) do_sum) + (orb (eq_vec (_get_PTE_Bits_R p) ((bool_to_bits true) : mword 1)) + (andb (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)) mxr))) + : bool) + | (Write, Supervisor) => + returnm ((andb (orb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits false) : mword 1)) do_sum) + (eq_vec (_get_PTE_Bits_W p) ((bool_to_bits true) : mword 1))) + : bool) + | (ReadWrite, Supervisor) => + returnm ((andb (orb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits false) : mword 1)) do_sum) + (andb (eq_vec (_get_PTE_Bits_W p) ((bool_to_bits true) : mword 1)) + (orb (eq_vec (_get_PTE_Bits_R p) ((bool_to_bits true) : mword 1)) + (andb (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)) mxr)))) + : bool) + | (Execute, Supervisor) => + returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits false) : mword 1)) + (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1))) + : bool) + | (_, Machine) => (internal_error "m-mode mem perm check") : M (bool) + end) + : M (bool). + +Definition update_PTE_Bits (p : PTE_Bits) (a : AccessType) +: option PTE_Bits := + + let update_d := + andb + (orb (generic_eq ((accessType_to_str a) : string) ((accessType_to_str Write) : string)) + (generic_eq ((accessType_to_str a) : string) ((accessType_to_str ReadWrite) : string))) + (eq_vec (_get_PTE_Bits_D p) ((bool_to_bits false) : mword 1)) in + let update_a := eq_vec (_get_PTE_Bits_A p) ((bool_to_bits false) : mword 1) in + if ((orb update_d update_a)) then + let np := _update_PTE_Bits_A p ((bool_to_bits true) : mword 1) in + let np := if (update_d) then _update_PTE_Bits_D np ((bool_to_bits true) : mword 1) else np in + Some + (np) + else None. + +Definition PTW_Error_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 4)} +: PTW_Error := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then PTW_Access + else if sumbool_of_bool ((Z.eqb p0_ 1)) then PTW_Invalid_PTE + else if sumbool_of_bool ((Z.eqb p0_ 2)) then PTW_No_Permission + else if sumbool_of_bool ((Z.eqb p0_ 3)) then PTW_Misaligned + else PTW_PTE_Update. + +Definition num_of_PTW_Error (arg_ : PTW_Error) +: {e : Z & ArithFact (0 <= e /\ e <= 4)} := + + build_ex(match arg_ with + | PTW_Access => 0 + | PTW_Invalid_PTE => 1 + | PTW_No_Permission => 2 + | PTW_Misaligned => 3 + | PTW_PTE_Update => 4 + end). + +Definition ptw_error_to_str (e : PTW_Error) +: string := + + match e with + | PTW_Access => "mem-access-error" + | PTW_Invalid_PTE => "invalid-pte" + | PTW_No_Permission => "no-permission" + | PTW_Misaligned => "misaligned-superpage" + | PTW_PTE_Update => "pte-update-needed" + end. + +Definition translationException (a : AccessType) (f : PTW_Error) +: ExceptionType := + + match (a, f) with + | (ReadWrite, PTW_Access) => E_SAMO_Access_Fault + | (ReadWrite, _) => E_SAMO_Page_Fault + | (Read, PTW_Access) => E_Load_Access_Fault + | (Read, _) => E_Load_Page_Fault + | (Write, PTW_Access) => E_SAMO_Access_Fault + | (Write, _) => E_SAMO_Page_Fault + | (Fetch, PTW_Access) => E_Fetch_Access_Fault + | (Fetch, _) => E_Fetch_Page_Fault + end. + +Definition SV39_LEVEL_BITS := 9. +Hint Unfold SV39_LEVEL_BITS : sail. +Definition SV39_LEVELS := 3. +Hint Unfold SV39_LEVELS : sail. +Definition PTE39_LOG_SIZE := 3. +Hint Unfold PTE39_LOG_SIZE : sail. +Definition PTE39_SIZE := 8. +Hint Unfold PTE39_SIZE : sail. +Definition Mk_SV39_Vaddr (v : mword 39) +: SV39_Vaddr := + + {| SV39_Vaddr_SV39_Vaddr_chunk_0 := (subrange_vec_dec v 38 0) |}. + +Definition _get_SV39_Vaddr_bits (v : SV39_Vaddr) +: mword 39 := + + subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 0. + +Definition _set_SV39_Vaddr_bits +(r_ref : register_ref regstate register_value SV39_Vaddr) (v : mword 39) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + SV39_Vaddr_SV39_Vaddr_chunk_0 := + (update_subrange_vec_dec r.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 0 (subrange_vec_dec v 38 0)) ]} + : SV39_Vaddr in + write_reg r_ref r + : M (unit). + +Definition _update_SV39_Vaddr_bits (v : SV39_Vaddr) (x : mword 39) +: SV39_Vaddr := + + {[ v with + SV39_Vaddr_SV39_Vaddr_chunk_0 := + (update_subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 0 (subrange_vec_dec x 38 0)) ]}. + +Definition _get_SV39_Vaddr_VPNi (v : SV39_Vaddr) +: mword 27 := + + subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 12. + +Definition _set_SV39_Vaddr_VPNi +(r_ref : register_ref regstate register_value SV39_Vaddr) (v : mword 27) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + SV39_Vaddr_SV39_Vaddr_chunk_0 := + (update_subrange_vec_dec r.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 12 (subrange_vec_dec v 26 0)) ]} + : SV39_Vaddr in + write_reg r_ref r + : M (unit). + +Definition _update_SV39_Vaddr_VPNi (v : SV39_Vaddr) (x : mword 27) +: SV39_Vaddr := + + {[ v with + SV39_Vaddr_SV39_Vaddr_chunk_0 := + (update_subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 12 (subrange_vec_dec x 26 0)) ]}. + +Definition _get_SV39_Vaddr_PgOfs (v : SV39_Vaddr) +: mword 12 := + + subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 11 0. + +Definition _set_SV39_Vaddr_PgOfs +(r_ref : register_ref regstate register_value SV39_Vaddr) (v : mword 12) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + SV39_Vaddr_SV39_Vaddr_chunk_0 := + (update_subrange_vec_dec r.(SV39_Vaddr_SV39_Vaddr_chunk_0) 11 0 (subrange_vec_dec v 11 0)) ]} + : SV39_Vaddr in + write_reg r_ref r + : M (unit). + +Definition _update_SV39_Vaddr_PgOfs (v : SV39_Vaddr) (x : mword 12) +: SV39_Vaddr := + + {[ v with + SV39_Vaddr_SV39_Vaddr_chunk_0 := + (update_subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 11 0 (subrange_vec_dec x 11 0)) ]}. + +Definition Mk_SV39_Paddr (v : mword 56) +: SV39_Paddr := + + {| SV39_Paddr_SV39_Paddr_chunk_0 := (subrange_vec_dec v 55 0) |}. + +Definition _get_SV39_Paddr_bits (v : SV39_Paddr) +: mword 56 := + + subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 55 0. + +Definition _set_SV39_Paddr_bits +(r_ref : register_ref regstate register_value SV39_Paddr) (v : mword 56) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + SV39_Paddr_SV39_Paddr_chunk_0 := + (update_subrange_vec_dec r.(SV39_Paddr_SV39_Paddr_chunk_0) 55 0 (subrange_vec_dec v 55 0)) ]} + : SV39_Paddr in + write_reg r_ref r + : M (unit). + +Definition _update_SV39_Paddr_bits (v : SV39_Paddr) (x : mword 56) +: SV39_Paddr := + + {[ v with + SV39_Paddr_SV39_Paddr_chunk_0 := + (update_subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 55 0 (subrange_vec_dec x 55 0)) ]}. + +Definition _get_SV39_Paddr_PPNi (v : SV39_Paddr) +: mword 44 := + + subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 55 12. + +Definition _set_SV39_Paddr_PPNi +(r_ref : register_ref regstate register_value SV39_Paddr) (v : mword 44) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + SV39_Paddr_SV39_Paddr_chunk_0 := + (update_subrange_vec_dec r.(SV39_Paddr_SV39_Paddr_chunk_0) 55 12 (subrange_vec_dec v 43 0)) ]} + : SV39_Paddr in + write_reg r_ref r + : M (unit). + +Definition _update_SV39_Paddr_PPNi (v : SV39_Paddr) (x : mword 44) +: SV39_Paddr := + + {[ v with + SV39_Paddr_SV39_Paddr_chunk_0 := + (update_subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 55 12 (subrange_vec_dec x 43 0)) ]}. + +Definition _get_SV39_Paddr_PgOfs (v : SV39_Paddr) +: mword 12 := + + subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 11 0. + +Definition _set_SV39_Paddr_PgOfs +(r_ref : register_ref regstate register_value SV39_Paddr) (v : mword 12) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + SV39_Paddr_SV39_Paddr_chunk_0 := + (update_subrange_vec_dec r.(SV39_Paddr_SV39_Paddr_chunk_0) 11 0 (subrange_vec_dec v 11 0)) ]} + : SV39_Paddr in + write_reg r_ref r + : M (unit). + +Definition _update_SV39_Paddr_PgOfs (v : SV39_Paddr) (x : mword 12) +: SV39_Paddr := + + {[ v with + SV39_Paddr_SV39_Paddr_chunk_0 := + (update_subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 11 0 (subrange_vec_dec x 11 0)) ]}. + +Definition Mk_SV39_PTE (v : mword 64) +: SV39_PTE := + + {| SV39_PTE_SV39_PTE_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_SV39_PTE_bits (v : SV39_PTE) +: mword 64 := + + subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 63 0. + +Definition _set_SV39_PTE_bits (r_ref : register_ref regstate register_value SV39_PTE) (v : mword 64) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + SV39_PTE_SV39_PTE_chunk_0 := + (update_subrange_vec_dec r.(SV39_PTE_SV39_PTE_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : SV39_PTE in + write_reg r_ref r + : M (unit). + +Definition _update_SV39_PTE_bits (v : SV39_PTE) (x : mword 64) +: SV39_PTE := + + {[ v with + SV39_PTE_SV39_PTE_chunk_0 := + (update_subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_SV39_PTE_PPNi (v : SV39_PTE) +: mword 44 := + + subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 53 10. + +Definition _set_SV39_PTE_PPNi (r_ref : register_ref regstate register_value SV39_PTE) (v : mword 44) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + SV39_PTE_SV39_PTE_chunk_0 := + (update_subrange_vec_dec r.(SV39_PTE_SV39_PTE_chunk_0) 53 10 (subrange_vec_dec v 43 0)) ]} + : SV39_PTE in + write_reg r_ref r + : M (unit). + +Definition _update_SV39_PTE_PPNi (v : SV39_PTE) (x : mword 44) +: SV39_PTE := + + {[ v with + SV39_PTE_SV39_PTE_chunk_0 := + (update_subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 53 10 (subrange_vec_dec x 43 0)) ]}. + +Definition _get_SV39_PTE_RSW (v : SV39_PTE) +: mword 2 := + + subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 9 8. + +Definition _set_SV39_PTE_RSW (r_ref : register_ref regstate register_value SV39_PTE) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + SV39_PTE_SV39_PTE_chunk_0 := + (update_subrange_vec_dec r.(SV39_PTE_SV39_PTE_chunk_0) 9 8 (subrange_vec_dec v 1 0)) ]} + : SV39_PTE in + write_reg r_ref r + : M (unit). + +Definition _update_SV39_PTE_RSW (v : SV39_PTE) (x : mword 2) +: SV39_PTE := + + {[ v with + SV39_PTE_SV39_PTE_chunk_0 := + (update_subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 9 8 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_SV39_PTE_BITS (v : SV39_PTE) +: mword 8 := + + subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 7 0. + +Definition _set_SV39_PTE_BITS (r_ref : register_ref regstate register_value SV39_PTE) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + SV39_PTE_SV39_PTE_chunk_0 := + (update_subrange_vec_dec r.(SV39_PTE_SV39_PTE_chunk_0) 7 0 (subrange_vec_dec v 7 0)) ]} + : SV39_PTE in + write_reg r_ref r + : M (unit). + +Definition _update_SV39_PTE_BITS (v : SV39_PTE) (x : mword 8) +: SV39_PTE := + + {[ v with + SV39_PTE_SV39_PTE_chunk_0 := + (update_subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}. + +Definition curAsid64 '(tt : unit) +: M (mword 16) := + + ((read_reg satp_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + let satp64 := Mk_Satp64 w__0 in + returnm ((_get_Satp64_Asid satp64) + : mword 16). + +Definition curPTB39 '(tt : unit) +: M (mword 56) := + + ((read_reg satp_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + let satp64 := Mk_Satp64 w__0 in + returnm ((EXTZ 56 (shiftl (_get_Satp64_PPN satp64) PAGESIZE_BITS)) + : mword 56). + +Fixpoint _rec_walk39 +(vaddr : mword 39) (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) +(ptb : mword 56) (level : Z) (global : bool) (_reclimit : Z) `{ArithFact (0 <= level)} +(_acc : Acc (Zwf 0) _reclimit) +{struct _acc} : M (PTW_Result) := + + assert_exp' (Z.geb _reclimit 0) "recursion limit reached" >>= fun _ => + let va := Mk_SV39_Vaddr vaddr in + let pt_ofs : paddr39 := + shiftl + (EXTZ 56 + (subrange_vec_dec (shiftr (_get_SV39_Vaddr_VPNi va) (Z.mul level SV39_LEVEL_BITS)) + (Z.sub SV39_LEVEL_BITS 1) 0)) PTE39_LOG_SIZE in + let pte_addr := add_vec ptb pt_ofs in + (phys_mem_read Data (EXTZ 64 pte_addr) 8 false false false) >>= fun w__0 : MemoryOpResult (mword (8 * 8)) => + (match w__0 with + | MemException (_) => returnm ((PTW_Failure (PTW_Access)) : PTW_Result ) + | MemValue (v) => + let pte := Mk_SV39_PTE v in + let pbits := _get_SV39_PTE_BITS pte in + let pattr := Mk_PTE_Bits pbits in + let is_global := orb global (eq_vec (_get_PTE_Bits_G pattr) ((bool_to_bits true) : mword 1)) in + (if ((isInvalidPTE pbits)) then returnm ((PTW_Failure (PTW_Invalid_PTE)) : PTW_Result ) + else if ((isPTEPtr pbits)) then + (if sumbool_of_bool ((Z.eqb level 0)) then + returnm ((PTW_Failure + (PTW_Invalid_PTE)) + : PTW_Result ) + else + (_rec_walk39 vaddr ac priv mxr do_sum + (EXTZ 56 (shiftl (_get_SV39_PTE_PPNi pte) PAGESIZE_BITS)) _ is_global + (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (PTW_Result)) + : M (PTW_Result) + else + (checkPTEPermission ac priv mxr do_sum pattr) >>= fun w__3 : bool => + returnm ((if ((negb w__3)) then PTW_Failure (PTW_No_Permission) + else if sumbool_of_bool ((Z.gtb level 0)) then + let mask := + sub_vec_int + (shiftl + (xor_vec (_get_SV39_PTE_PPNi pte) + (xor_vec (_get_SV39_PTE_PPNi pte) + (EXTZ 44 (vec_of_bits [B1] : mword 1)))) + (Z.mul level SV39_LEVEL_BITS)) 1 in + if ((neq_vec (and_vec (_get_SV39_PTE_PPNi pte) mask) + (EXTZ 44 (vec_of_bits [B0] : mword 1)))) then + PTW_Failure + (PTW_Misaligned) + else + let ppn := + or_vec (_get_SV39_PTE_PPNi pte) + (and_vec (EXTZ 44 (_get_SV39_Vaddr_VPNi va)) mask) in + PTW_Success + ((concat_vec ppn (_get_SV39_Vaddr_PgOfs va), pte, pte_addr, build_ex level, is_global)) + else + PTW_Success + ((concat_vec (_get_SV39_PTE_PPNi pte) (_get_SV39_Vaddr_PgOfs va), pte, pte_addr, build_ex level, is_global))) + : PTW_Result)) + : M (PTW_Result) + end) + : M (PTW_Result). + +Definition walk39 +(_arg0 : mword 39) (_arg1 : AccessType) (_arg2 : Privilege) (_arg3 : bool) (_arg4 : bool) +(_arg5 : mword 56) (level : Z) (_arg7 : bool) `{ArithFact (0 <= level)} +: M (PTW_Result) := + + (_rec_walk39 _arg0 _arg1 _arg2 _arg3 _arg4 _arg5 level _arg7 (level : Z) (Zwf_guarded _)) + : M (PTW_Result). + +Definition make_TLB39_Entry +(asid : mword 16) (global : bool) (vAddr : mword 39) (pAddr : mword 56) (pte : SV39_PTE) (level : Z) +(pteAddr : mword 56) `{ArithFact (0 <= level)} +: M (TLB39_Entry) := + + let 'shift := + projT1 (build_ex (Z.add PAGESIZE_BITS (Z.mul level SV39_LEVEL_BITS)) + : {n : Z & ArithFact (n >= 0)}) in + let vAddrMask : vaddr39 := + sub_vec_int + (shiftl (xor_vec vAddr (xor_vec vAddr (EXTZ 39 (vec_of_bits [B1] : mword 1)))) shift) 1 in + let vMatchMask : vaddr39 := not_vec vAddrMask in + ((read_reg mcycle_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + returnm (({| TLB39_Entry_asid := asid; + TLB39_Entry_global := global; + TLB39_Entry_pte := pte; + TLB39_Entry_pteAddr := pteAddr; + TLB39_Entry_vAddrMask := vAddrMask; + TLB39_Entry_vMatchMask := vMatchMask; + TLB39_Entry_vAddr := (and_vec vAddr vMatchMask); + TLB39_Entry_pAddr := (shiftl (shiftr pAddr shift) shift); + TLB39_Entry_age := w__0 |}) + : TLB39_Entry). + +Definition lookupTLB39 (asid : mword 16) (vaddr : mword 39) +: M (option ((Z * TLB39_Entry))) := + + read_reg tlb39_ref >>= fun w__0 : option TLB39_Entry => + returnm ((match w__0 with + | None => None + | Some (e) => + if ((andb (orb e.(TLB39_Entry_global) (eq_vec e.(TLB39_Entry_asid) asid)) + (eq_vec e.(TLB39_Entry_vAddr) (and_vec e.(TLB39_Entry_vMatchMask) vaddr)))) + then + Some + ((0, e)) + else None + end) + : option ((Z * TLB39_Entry))). + +Definition addToTLB39 +(asid : mword 16) (vAddr : mword 39) (pAddr : mword 56) (pte : SV39_PTE) (pteAddr : mword 56) +(level : Z) (global : bool) `{ArithFact (0 <= level)} +: M (unit) := + + (make_TLB39_Entry asid global vAddr pAddr pte level pteAddr) >>= fun ent => + write_reg tlb39_ref (Some (ent)) + : M (unit). + +Definition writeTLB39 (idx : Z) (ent : TLB39_Entry) +: M (unit) := + + write_reg tlb39_ref (Some (ent)) + : M (unit). + +Definition flushTLB (asid : option (mword 16)) (addr : option (mword 39)) +: M (unit) := + + read_reg tlb39_ref >>= fun w__0 : option TLB39_Entry => + let ent : option TLB39_Entry := + match (w__0, asid, addr) with + | (None, _, _) => None + | (Some (e), None, None) => None + | (Some (e), None, Some (a)) => + if ((eq_vec e.(TLB39_Entry_vAddr) (and_vec e.(TLB39_Entry_vMatchMask) a))) then None + else Some (e) + | (Some (e), Some (i), None) => + if ((andb (eq_vec e.(TLB39_Entry_asid) i) (negb e.(TLB39_Entry_global)))) then None + else Some (e) + | (Some (e), Some (i), Some (a)) => + if ((andb (eq_vec e.(TLB39_Entry_asid) i) + (andb (eq_vec e.(TLB39_Entry_vAddr) (and_vec a e.(TLB39_Entry_vMatchMask))) + (negb e.(TLB39_Entry_global))))) then + None + else Some (e) + end in + write_reg tlb39_ref ent + : M (unit). + +Definition translate39 +(vAddr : mword 39) (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) (level : Z) +`{ArithFact (0 <= level)} +: M (TR39_Result) := + + (curAsid64 tt) >>= fun asid => + (lookupTLB39 asid vAddr) >>= fun w__0 : option ((Z * TLB39_Entry)) => + (match w__0 with + | Some (idx,ent) => + let pteBits := Mk_PTE_Bits (_get_SV39_PTE_BITS ent.(TLB39_Entry_pte)) in + (checkPTEPermission ac priv mxr do_sum pteBits) >>= fun w__1 : bool => + (if ((negb w__1)) then returnm ((TR39_Failure (PTW_No_Permission)) : TR39_Result ) + else + (match (update_PTE_Bits pteBits ac) with + | None => + returnm ((TR39_Address + (or_vec ent.(TLB39_Entry_pAddr) + (EXTZ 56 (and_vec vAddr ent.(TLB39_Entry_vAddrMask))))) + : TR39_Result ) + | Some (pbits) => + (if ((negb (plat_enable_dirty_update tt))) then + returnm ((TR39_Failure + (PTW_PTE_Update)) + : TR39_Result ) + else + let n_ent : TLB39_Entry := ent in + let n_ent := + {[ n_ent with + TLB39_Entry_pte := + (_update_SV39_PTE_BITS ent.(TLB39_Entry_pte) (_get_PTE_Bits_bits pbits)) ]} + : TLB39_Entry in + (writeTLB39 idx n_ent) >> + (checked_mem_write (EXTZ 64 ent.(TLB39_Entry_pteAddr)) 8 + (_get_SV39_PTE_bits ent.(TLB39_Entry_pte))) >>= fun w__2 : MemoryOpResult bool => + (match w__2 with + | MemValue (_) => returnm (tt : unit) + | MemException (e) => + (internal_error "invalid physical address in TLB") : M (unit) + end) >> + returnm ((TR39_Address + (or_vec ent.(TLB39_Entry_pAddr) + (EXTZ 56 (and_vec vAddr ent.(TLB39_Entry_vAddrMask))))) + : TR39_Result)) + : M (TR39_Result) + end) + : M (TR39_Result)) + : M (TR39_Result) + | None => + (curPTB39 tt) >>= fun w__6 : mword 56 => + (walk39 vAddr ac priv mxr do_sum w__6 level false) >>= fun w__7 : PTW_Result => + (match w__7 with + | PTW_Failure (f) => returnm ((TR39_Failure (f)) : TR39_Result ) + | PTW_Success (pAddr,pte,pteAddr,(existT _ level _),global) => + (match (update_PTE_Bits (Mk_PTE_Bits (_get_SV39_PTE_BITS pte)) ac) with + | None => + (addToTLB39 asid vAddr pAddr pte pteAddr level global) >> + returnm ((TR39_Address + (pAddr)) + : TR39_Result ) + | Some (pbits) => + (if ((negb (plat_enable_dirty_update tt))) then + returnm ((TR39_Failure + (PTW_PTE_Update)) + : TR39_Result ) + else + let w_pte : SV39_PTE := _update_SV39_PTE_BITS pte (_get_PTE_Bits_bits pbits) in + (checked_mem_write (EXTZ 64 pteAddr) 8 (_get_SV39_PTE_bits w_pte)) >>= fun w__8 : MemoryOpResult bool => + (match w__8 with + | MemValue (_) => + (addToTLB39 asid vAddr pAddr w_pte pteAddr level global) >> + returnm ((TR39_Address + (pAddr)) + : TR39_Result ) + | MemException (e) => returnm ((TR39_Failure (PTW_Access)) : TR39_Result ) + end) + : M (TR39_Result)) + : M (TR39_Result) + end) + : M (TR39_Result) + end) + : M (TR39_Result) + end) + : M (TR39_Result). + +Definition translationMode (priv : Privilege) +: M (SATPMode) := + + (if ((eq_vec (privLevel_to_bits priv) ((privLevel_to_bits Machine) : mword 2))) then + returnm (Sbare + : SATPMode) + else + read_reg mstatus_ref >>= fun w__0 : Mstatus => + let arch := architecture (_get_Mstatus_SXL w__0) in + (match arch with + | Some (RV64) => + ((read_reg satp_ref) : M (mword 64)) >>= fun w__1 : xlenbits => + let mbits : satp_mode := _get_Satp64_Mode (Mk_Satp64 w__1) in + (match (satpMode_of_bits RV64 mbits) with + | Some (m) => returnm (m : SATPMode) + | None => (internal_error "invalid RV64 translation mode in satp") : M (SATPMode) + end) + : M (SATPMode) + | _ => (internal_error "unsupported address translation arch") : M (SATPMode) + end) + : M (SATPMode)) + : M (SATPMode). + +Definition translateAddr (vAddr : mword 64) (ac : AccessType) (rt : ReadType) +: M (TR_Result) := + + (match rt with + | Instruction => read_reg cur_privilege_ref : M (Privilege) + | Data => + read_reg mstatus_ref >>= fun w__1 : Mstatus => + (if ((eq_vec (_get_Mstatus_MPRV w__1) ((bool_to_bits true) : mword 1))) then + read_reg mstatus_ref >>= fun w__2 : Mstatus => + returnm ((privLevel_of_bits (_get_Mstatus_MPP w__2)) + : Privilege) + else read_reg cur_privilege_ref : M (Privilege)) + : M (Privilege) + end) >>= fun effPriv : Privilege => + read_reg mstatus_ref >>= fun w__5 : Mstatus => + let mxr : bool := eq_vec (_get_Mstatus_MXR w__5) ((bool_to_bits true) : mword 1) in + read_reg mstatus_ref >>= fun w__6 : Mstatus => + let do_sum : bool := eq_vec (_get_Mstatus_SUM w__6) ((bool_to_bits true) : mword 1) in + (translationMode effPriv) >>= fun mode : SATPMode => + (match mode with + | Sbare => returnm ((TR_Address (vAddr)) : TR_Result ) + | SV39 => + (translate39 (subrange_vec_dec vAddr 38 0) ac effPriv mxr do_sum (Z.sub SV39_LEVELS 1)) >>= fun w__7 : TR39_Result => + returnm ((match w__7 with + | TR39_Address (pa) => TR_Address (EXTZ 64 pa) + | TR39_Failure (f) => TR_Failure (translationException ac f) + end) + : TR_Result) + end) + : M (TR_Result). + +Definition encdec_uop_forwards (arg_ : uop) +: mword 7 := + + match arg_ with + | RISCV_LUI => (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : mword 7) + | RISCV_AUIPC => (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : mword 7) + end. + +Definition encdec_uop_backwards (arg_ : mword 7) +: uop := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : mword 7))) then RISCV_LUI + else RISCV_AUIPC. + +Definition encdec_uop_forwards_matches (arg_ : uop) +: bool := + + match arg_ with | RISCV_LUI => true | RISCV_AUIPC => true end. + +Definition encdec_uop_backwards_matches (arg_ : mword 7) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : mword 7))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : mword 7))) then true + else false. + +Definition utype_mnemonic_forwards (arg_ : uop) +: string := + + match arg_ with | RISCV_LUI => "lui" | RISCV_AUIPC => "auipc" end. + +Definition utype_mnemonic_backwards (arg_ : string) +: uop := + + let p0_ := arg_ in + if ((generic_eq p0_ "lui")) then RISCV_LUI + else RISCV_AUIPC. + +Definition utype_mnemonic_forwards_matches (arg_ : uop) +: bool := + + match arg_ with | RISCV_LUI => true | RISCV_AUIPC => true end. + +Definition utype_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "lui")) then true + else if ((generic_eq p0_ "auipc")) then true + else false. + +Definition _s496_ (_s497_ : string) +: option string := + + let _s498_ := _s497_ in + if ((string_startswith _s498_ "auipc")) then + match (string_drop _s498_ (projT1 (string_length "auipc"))) with | s_ => Some (s_) end + else None. + +Definition _s492_ (_s493_ : string) +: option string := + + let _s494_ := _s493_ in + if ((string_startswith _s494_ "lui")) then + match (string_drop _s494_ (projT1 (string_length "lui"))) with | s_ => Some (s_) end + else None. + +Definition utype_mnemonic_matches_prefix (arg_ : string) +: M (option ((uop * {n : Z & ArithFact (n >= 0)}))) := + + let _s495_ := arg_ in + (if ((match (_s492_ _s495_) with | Some (s_) => true | _ => false end)) then + (match (_s492_ _s495_) with + | Some (s_) => + returnm ((Some + ((RISCV_LUI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((uop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((uop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((uop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s496_ _s495_) with | Some (s_) => true | _ => false end)) then + (match (_s496_ _s495_) with + | Some (s_) => + returnm ((Some + ((RISCV_AUIPC, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((uop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((uop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((uop * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((uop * {n : Z & ArithFact (n >= 0)})))) + : M (option ((uop * {n : Z & ArithFact (n >= 0)}))). + +Definition encdec_bop_forwards (arg_ : bop) +: mword 3 := + + match arg_ with + | RISCV_BEQ => (vec_of_bits [B0;B0;B0] : mword 3) + | RISCV_BNE => (vec_of_bits [B0;B0;B1] : mword 3) + | RISCV_BLT => (vec_of_bits [B1;B0;B0] : mword 3) + | RISCV_BGE => (vec_of_bits [B1;B0;B1] : mword 3) + | RISCV_BLTU => (vec_of_bits [B1;B1;B0] : mword 3) + | RISCV_BGEU => (vec_of_bits [B1;B1;B1] : mword 3) + end. + +Definition encdec_bop_backwards (arg_ : mword 3) +: bop := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then RISCV_BEQ + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then RISCV_BNE + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then RISCV_BLT + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then RISCV_BGE + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then RISCV_BLTU + else RISCV_BGEU. + +Definition encdec_bop_forwards_matches (arg_ : bop) +: bool := + + match arg_ with + | RISCV_BEQ => true + | RISCV_BNE => true + | RISCV_BLT => true + | RISCV_BGE => true + | RISCV_BLTU => true + | RISCV_BGEU => true + end. + +Definition encdec_bop_backwards_matches (arg_ : mword 3) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1] : mword 3))) then true + else false. + +Definition btype_mnemonic_forwards (arg_ : bop) +: string := + + match arg_ with + | RISCV_BEQ => "beq" + | RISCV_BNE => "bne" + | RISCV_BLT => "blt" + | RISCV_BGE => "bge" + | RISCV_BLTU => "bltu" + | RISCV_BGEU => "bgeu" + end. + +Definition btype_mnemonic_backwards (arg_ : string) +: bop := + + let p0_ := arg_ in + if ((generic_eq p0_ "beq")) then RISCV_BEQ + else if ((generic_eq p0_ "bne")) then RISCV_BNE + else if ((generic_eq p0_ "blt")) then RISCV_BLT + else if ((generic_eq p0_ "bge")) then RISCV_BGE + else if ((generic_eq p0_ "bltu")) then RISCV_BLTU + else RISCV_BGEU. + +Definition btype_mnemonic_forwards_matches (arg_ : bop) +: bool := + + match arg_ with + | RISCV_BEQ => true + | RISCV_BNE => true + | RISCV_BLT => true + | RISCV_BGE => true + | RISCV_BLTU => true + | RISCV_BGEU => true + end. + +Definition btype_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "beq")) then true + else if ((generic_eq p0_ "bne")) then true + else if ((generic_eq p0_ "blt")) then true + else if ((generic_eq p0_ "bge")) then true + else if ((generic_eq p0_ "bltu")) then true + else if ((generic_eq p0_ "bgeu")) then true + else false. + +Definition _s520_ (_s521_ : string) +: option string := + + let _s522_ := _s521_ in + if ((string_startswith _s522_ "bgeu")) then + match (string_drop _s522_ (projT1 (string_length "bgeu"))) with | s_ => Some (s_) end + else None. + +Definition _s516_ (_s517_ : string) +: option string := + + let _s518_ := _s517_ in + if ((string_startswith _s518_ "bltu")) then + match (string_drop _s518_ (projT1 (string_length "bltu"))) with | s_ => Some (s_) end + else None. + +Definition _s512_ (_s513_ : string) +: option string := + + let _s514_ := _s513_ in + if ((string_startswith _s514_ "bge")) then + match (string_drop _s514_ (projT1 (string_length "bge"))) with | s_ => Some (s_) end + else None. + +Definition _s508_ (_s509_ : string) +: option string := + + let _s510_ := _s509_ in + if ((string_startswith _s510_ "blt")) then + match (string_drop _s510_ (projT1 (string_length "blt"))) with | s_ => Some (s_) end + else None. + +Definition _s504_ (_s505_ : string) +: option string := + + let _s506_ := _s505_ in + if ((string_startswith _s506_ "bne")) then + match (string_drop _s506_ (projT1 (string_length "bne"))) with | s_ => Some (s_) end + else None. + +Definition _s500_ (_s501_ : string) +: option string := + + let _s502_ := _s501_ in + if ((string_startswith _s502_ "beq")) then + match (string_drop _s502_ (projT1 (string_length "beq"))) with | s_ => Some (s_) end + else None. + +Definition btype_mnemonic_matches_prefix (arg_ : string) +: M (option ((bop * {n : Z & ArithFact (n >= 0)}))) := + + let _s503_ := arg_ in + (if ((match (_s500_ _s503_) with | Some (s_) => true | _ => false end)) then + (match (_s500_ _s503_) with + | Some (s_) => + returnm ((Some + ((RISCV_BEQ, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s504_ _s503_) with | Some (s_) => true | _ => false end)) then + (match (_s504_ _s503_) with + | Some (s_) => + returnm ((Some + ((RISCV_BNE, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s508_ _s503_) with | Some (s_) => true | _ => false end)) then + (match (_s508_ _s503_) with + | Some (s_) => + returnm ((Some + ((RISCV_BLT, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s512_ _s503_) with | Some (s_) => true | _ => false end)) then + (match (_s512_ _s503_) with + | Some (s_) => + returnm ((Some + ((RISCV_BGE, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s516_ _s503_) with | Some (s_) => true | _ => false end)) then + (match (_s516_ _s503_) with + | Some (s_) => + returnm ((Some + ((RISCV_BLTU, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s520_ _s503_) with | Some (s_) => true | _ => false end)) then + (match (_s520_ _s503_) with + | Some (s_) => + returnm ((Some + ((RISCV_BGEU, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((bop * {n : Z & ArithFact (n >= 0)})))) + : M (option ((bop * {n : Z & ArithFact (n >= 0)}))). + +Definition encdec_iop_forwards (arg_ : iop) +: mword 3 := + + match arg_ with + | RISCV_ADDI => (vec_of_bits [B0;B0;B0] : mword 3) + | RISCV_SLTI => (vec_of_bits [B0;B1;B0] : mword 3) + | RISCV_SLTIU => (vec_of_bits [B0;B1;B1] : mword 3) + | RISCV_XORI => (vec_of_bits [B1;B0;B0] : mword 3) + | RISCV_ORI => (vec_of_bits [B1;B1;B0] : mword 3) + | RISCV_ANDI => (vec_of_bits [B1;B1;B1] : mword 3) + end. + +Definition encdec_iop_backwards (arg_ : mword 3) +: iop := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then RISCV_ADDI + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then RISCV_SLTI + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then RISCV_SLTIU + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then RISCV_XORI + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then RISCV_ORI + else RISCV_ANDI. + +Definition encdec_iop_forwards_matches (arg_ : iop) +: bool := + + match arg_ with + | RISCV_ADDI => true + | RISCV_SLTI => true + | RISCV_SLTIU => true + | RISCV_XORI => true + | RISCV_ORI => true + | RISCV_ANDI => true + end. + +Definition encdec_iop_backwards_matches (arg_ : mword 3) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1] : mword 3))) then true + else false. + +Definition itype_mnemonic_forwards (arg_ : iop) +: string := + + match arg_ with + | RISCV_ADDI => "addi" + | RISCV_SLTI => "slti" + | RISCV_SLTIU => "sltiu" + | RISCV_XORI => "xori" + | RISCV_ORI => "ori" + | RISCV_ANDI => "andi" + end. + +Definition itype_mnemonic_backwards (arg_ : string) +: iop := + + let p0_ := arg_ in + if ((generic_eq p0_ "addi")) then RISCV_ADDI + else if ((generic_eq p0_ "slti")) then RISCV_SLTI + else if ((generic_eq p0_ "sltiu")) then RISCV_SLTIU + else if ((generic_eq p0_ "xori")) then RISCV_XORI + else if ((generic_eq p0_ "ori")) then RISCV_ORI + else RISCV_ANDI. + +Definition itype_mnemonic_forwards_matches (arg_ : iop) +: bool := + + match arg_ with + | RISCV_ADDI => true + | RISCV_SLTI => true + | RISCV_SLTIU => true + | RISCV_XORI => true + | RISCV_ORI => true + | RISCV_ANDI => true + end. + +Definition itype_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "addi")) then true + else if ((generic_eq p0_ "slti")) then true + else if ((generic_eq p0_ "sltiu")) then true + else if ((generic_eq p0_ "xori")) then true + else if ((generic_eq p0_ "ori")) then true + else if ((generic_eq p0_ "andi")) then true + else false. + +Definition _s544_ (_s545_ : string) +: option string := + + let _s546_ := _s545_ in + if ((string_startswith _s546_ "andi")) then + match (string_drop _s546_ (projT1 (string_length "andi"))) with | s_ => Some (s_) end + else None. + +Definition _s540_ (_s541_ : string) +: option string := + + let _s542_ := _s541_ in + if ((string_startswith _s542_ "ori")) then + match (string_drop _s542_ (projT1 (string_length "ori"))) with | s_ => Some (s_) end + else None. + +Definition _s536_ (_s537_ : string) +: option string := + + let _s538_ := _s537_ in + if ((string_startswith _s538_ "xori")) then + match (string_drop _s538_ (projT1 (string_length "xori"))) with | s_ => Some (s_) end + else None. + +Definition _s532_ (_s533_ : string) +: option string := + + let _s534_ := _s533_ in + if ((string_startswith _s534_ "sltiu")) then + match (string_drop _s534_ (projT1 (string_length "sltiu"))) with | s_ => Some (s_) end + else None. + +Definition _s528_ (_s529_ : string) +: option string := + + let _s530_ := _s529_ in + if ((string_startswith _s530_ "slti")) then + match (string_drop _s530_ (projT1 (string_length "slti"))) with | s_ => Some (s_) end + else None. + +Definition _s524_ (_s525_ : string) +: option string := + + let _s526_ := _s525_ in + if ((string_startswith _s526_ "addi")) then + match (string_drop _s526_ (projT1 (string_length "addi"))) with | s_ => Some (s_) end + else None. + +Definition itype_mnemonic_matches_prefix (arg_ : string) +: M (option ((iop * {n : Z & ArithFact (n >= 0)}))) := + + let _s527_ := arg_ in + (if ((match (_s524_ _s527_) with | Some (s_) => true | _ => false end)) then + (match (_s524_ _s527_) with + | Some (s_) => + returnm ((Some + ((RISCV_ADDI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((iop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s528_ _s527_) with | Some (s_) => true | _ => false end)) then + (match (_s528_ _s527_) with + | Some (s_) => + returnm ((Some + ((RISCV_SLTI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((iop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s532_ _s527_) with | Some (s_) => true | _ => false end)) then + (match (_s532_ _s527_) with + | Some (s_) => + returnm ((Some + ((RISCV_SLTIU, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((iop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s536_ _s527_) with | Some (s_) => true | _ => false end)) then + (match (_s536_ _s527_) with + | Some (s_) => + returnm ((Some + ((RISCV_XORI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((iop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s540_ _s527_) with | Some (s_) => true | _ => false end)) then + (match (_s540_ _s527_) with + | Some (s_) => + returnm ((Some + ((RISCV_ORI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((iop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s544_ _s527_) with | Some (s_) => true | _ => false end)) then + (match (_s544_ _s527_) with + | Some (s_) => + returnm ((Some + ((RISCV_ANDI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((iop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((iop * {n : Z & ArithFact (n >= 0)})))) + : M (option ((iop * {n : Z & ArithFact (n >= 0)}))). + +Definition encdec_sop_forwards (arg_ : sop) +: mword 3 := + + match arg_ with + | RISCV_SLLI => (vec_of_bits [B0;B0;B1] : mword 3) + | RISCV_SRLI => (vec_of_bits [B1;B0;B1] : mword 3) + | RISCV_SRAI => (vec_of_bits [B1;B0;B1] : mword 3) + end. + +Definition encdec_sop_backwards (arg_ : mword 3) +: sop := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then RISCV_SLLI + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then RISCV_SRLI + else RISCV_SRAI. + +Definition encdec_sop_forwards_matches (arg_ : sop) +: bool := + + match arg_ with | RISCV_SLLI => true | RISCV_SRLI => true | RISCV_SRAI => true end. + +Definition encdec_sop_backwards_matches (arg_ : mword 3) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then true + else false. + +Definition shiftiop_mnemonic_forwards (arg_ : sop) +: string := + + match arg_ with | RISCV_SLLI => "slli" | RISCV_SRLI => "srli" | RISCV_SRAI => "srai" end. + +Definition shiftiop_mnemonic_backwards (arg_ : string) +: sop := + + let p0_ := arg_ in + if ((generic_eq p0_ "slli")) then RISCV_SLLI + else if ((generic_eq p0_ "srli")) then RISCV_SRLI + else RISCV_SRAI. + +Definition shiftiop_mnemonic_forwards_matches (arg_ : sop) +: bool := + + match arg_ with | RISCV_SLLI => true | RISCV_SRLI => true | RISCV_SRAI => true end. + +Definition shiftiop_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "slli")) then true + else if ((generic_eq p0_ "srli")) then true + else if ((generic_eq p0_ "srai")) then true + else false. + +Definition _s556_ (_s557_ : string) +: option string := + + let _s558_ := _s557_ in + if ((string_startswith _s558_ "srai")) then + match (string_drop _s558_ (projT1 (string_length "srai"))) with | s_ => Some (s_) end + else None. + +Definition _s552_ (_s553_ : string) +: option string := + + let _s554_ := _s553_ in + if ((string_startswith _s554_ "srli")) then + match (string_drop _s554_ (projT1 (string_length "srli"))) with | s_ => Some (s_) end + else None. + +Definition _s548_ (_s549_ : string) +: option string := + + let _s550_ := _s549_ in + if ((string_startswith _s550_ "slli")) then + match (string_drop _s550_ (projT1 (string_length "slli"))) with | s_ => Some (s_) end + else None. + +Definition shiftiop_mnemonic_matches_prefix (arg_ : string) +: M (option ((sop * {n : Z & ArithFact (n >= 0)}))) := + + let _s551_ := arg_ in + (if ((match (_s548_ _s551_) with | Some (s_) => true | _ => false end)) then + (match (_s548_ _s551_) with + | Some (s_) => + returnm ((Some + ((RISCV_SLLI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((sop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s552_ _s551_) with | Some (s_) => true | _ => false end)) then + (match (_s552_ _s551_) with + | Some (s_) => + returnm ((Some + ((RISCV_SRLI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((sop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s556_ _s551_) with | Some (s_) => true | _ => false end)) then + (match (_s556_ _s551_) with + | Some (s_) => + returnm ((Some + ((RISCV_SRAI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((sop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((sop * {n : Z & ArithFact (n >= 0)})))) + : M (option ((sop * {n : Z & ArithFact (n >= 0)}))). + +Definition rtype_mnemonic_forwards (arg_ : rop) +: string := + + match arg_ with + | RISCV_ADD => "add" + | RISCV_SUB => "sub" + | RISCV_SLL => "sll" + | RISCV_SLT => "slt" + | RISCV_SLTU => "sltu" + | RISCV_XOR => "xor" + | RISCV_SRL => "srl" + | RISCV_SRA => "sra" + | RISCV_OR => "or" + | RISCV_AND => "and" + end. + +Definition rtype_mnemonic_backwards (arg_ : string) +: rop := + + let p0_ := arg_ in + if ((generic_eq p0_ "add")) then RISCV_ADD + else if ((generic_eq p0_ "sub")) then RISCV_SUB + else if ((generic_eq p0_ "sll")) then RISCV_SLL + else if ((generic_eq p0_ "slt")) then RISCV_SLT + else if ((generic_eq p0_ "sltu")) then RISCV_SLTU + else if ((generic_eq p0_ "xor")) then RISCV_XOR + else if ((generic_eq p0_ "srl")) then RISCV_SRL + else if ((generic_eq p0_ "sra")) then RISCV_SRA + else if ((generic_eq p0_ "or")) then RISCV_OR + else RISCV_AND. + +Definition rtype_mnemonic_forwards_matches (arg_ : rop) +: bool := + + match arg_ with + | RISCV_ADD => true + | RISCV_SUB => true + | RISCV_SLL => true + | RISCV_SLT => true + | RISCV_SLTU => true + | RISCV_XOR => true + | RISCV_SRL => true + | RISCV_SRA => true + | RISCV_OR => true + | RISCV_AND => true + end. + +Definition rtype_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "add")) then true + else if ((generic_eq p0_ "sub")) then true + else if ((generic_eq p0_ "sll")) then true + else if ((generic_eq p0_ "slt")) then true + else if ((generic_eq p0_ "sltu")) then true + else if ((generic_eq p0_ "xor")) then true + else if ((generic_eq p0_ "srl")) then true + else if ((generic_eq p0_ "sra")) then true + else if ((generic_eq p0_ "or")) then true + else if ((generic_eq p0_ "and")) then true + else false. + +Definition _s596_ (_s597_ : string) +: option string := + + let _s598_ := _s597_ in + if ((string_startswith _s598_ "and")) then + match (string_drop _s598_ (projT1 (string_length "and"))) with | s_ => Some (s_) end + else None. + +Definition _s592_ (_s593_ : string) +: option string := + + let _s594_ := _s593_ in + if ((string_startswith _s594_ "or")) then + match (string_drop _s594_ (projT1 (string_length "or"))) with | s_ => Some (s_) end + else None. + +Definition _s588_ (_s589_ : string) +: option string := + + let _s590_ := _s589_ in + if ((string_startswith _s590_ "sra")) then + match (string_drop _s590_ (projT1 (string_length "sra"))) with | s_ => Some (s_) end + else None. + +Definition _s584_ (_s585_ : string) +: option string := + + let _s586_ := _s585_ in + if ((string_startswith _s586_ "srl")) then + match (string_drop _s586_ (projT1 (string_length "srl"))) with | s_ => Some (s_) end + else None. + +Definition _s580_ (_s581_ : string) +: option string := + + let _s582_ := _s581_ in + if ((string_startswith _s582_ "xor")) then + match (string_drop _s582_ (projT1 (string_length "xor"))) with | s_ => Some (s_) end + else None. + +Definition _s576_ (_s577_ : string) +: option string := + + let _s578_ := _s577_ in + if ((string_startswith _s578_ "sltu")) then + match (string_drop _s578_ (projT1 (string_length "sltu"))) with | s_ => Some (s_) end + else None. + +Definition _s572_ (_s573_ : string) +: option string := + + let _s574_ := _s573_ in + if ((string_startswith _s574_ "slt")) then + match (string_drop _s574_ (projT1 (string_length "slt"))) with | s_ => Some (s_) end + else None. + +Definition _s568_ (_s569_ : string) +: option string := + + let _s570_ := _s569_ in + if ((string_startswith _s570_ "sll")) then + match (string_drop _s570_ (projT1 (string_length "sll"))) with | s_ => Some (s_) end + else None. + +Definition _s564_ (_s565_ : string) +: option string := + + let _s566_ := _s565_ in + if ((string_startswith _s566_ "sub")) then + match (string_drop _s566_ (projT1 (string_length "sub"))) with | s_ => Some (s_) end + else None. + +Definition _s560_ (_s561_ : string) +: option string := + + let _s562_ := _s561_ in + if ((string_startswith _s562_ "add")) then + match (string_drop _s562_ (projT1 (string_length "add"))) with | s_ => Some (s_) end + else None. + +Definition rtype_mnemonic_matches_prefix (arg_ : string) +: M (option ((rop * {n : Z & ArithFact (n >= 0)}))) := + + let _s563_ := arg_ in + (if ((match (_s560_ _s563_) with | Some (s_) => true | _ => false end)) then + (match (_s560_ _s563_) with + | Some (s_) => + returnm ((Some + ((RISCV_ADD, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((rop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s564_ _s563_) with | Some (s_) => true | _ => false end)) then + (match (_s564_ _s563_) with + | Some (s_) => + returnm ((Some + ((RISCV_SUB, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((rop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s568_ _s563_) with | Some (s_) => true | _ => false end)) then + (match (_s568_ _s563_) with + | Some (s_) => + returnm ((Some + ((RISCV_SLL, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((rop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s572_ _s563_) with | Some (s_) => true | _ => false end)) then + (match (_s572_ _s563_) with + | Some (s_) => + returnm ((Some + ((RISCV_SLT, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((rop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s576_ _s563_) with | Some (s_) => true | _ => false end)) then + (match (_s576_ _s563_) with + | Some (s_) => + returnm ((Some + ((RISCV_SLTU, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((rop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s580_ _s563_) with | Some (s_) => true | _ => false end)) then + (match (_s580_ _s563_) with + | Some (s_) => + returnm ((Some + ((RISCV_XOR, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((rop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s584_ _s563_) with | Some (s_) => true | _ => false end)) then + (match (_s584_ _s563_) with + | Some (s_) => + returnm ((Some + ((RISCV_SRL, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((rop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s588_ _s563_) with | Some (s_) => true | _ => false end)) then + (match (_s588_ _s563_) with + | Some (s_) => + returnm ((Some + ((RISCV_SRA, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((rop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s592_ _s563_) with | Some (s_) => true | _ => false end)) then + (match (_s592_ _s563_) with + | Some (s_) => + returnm ((Some + ((RISCV_OR, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((rop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s596_ _s563_) with | Some (s_) => true | _ => false end)) then + (match (_s596_ _s563_) with + | Some (s_) => + returnm ((Some + ((RISCV_AND, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((rop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((rop * {n : Z & ArithFact (n >= 0)})))) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))). + +Definition extend_value {n : Z} (is_unsigned : bool) (value : MemoryOpResult (mword (8 * n))) +`{ArithFact ((0 + 1) <= n /\ n <= 8)} +: MemoryOpResult (mword 64) := + + match value with + | MemValue (v) => MemValue (if (is_unsigned) then EXTZ 64 v else (EXTS 64 v) : xlenbits) + | MemException (e) => MemException (e) + end. + +Definition process_load {n : Z} +(rd : mword 5) (addr : mword 64) (value : MemoryOpResult (mword (8 * n))) (is_unsigned : bool) +`{ArithFact ((0 + 1) <= n /\ n <= 8)} +: M (bool) := + + (match (extend_value is_unsigned value) with + | MemValue (result) => (wX (projT1 (regbits_to_regno rd)) result) >> returnm (true : bool) + | MemException (e) => (handle_mem_exception addr e) >> returnm (false : bool) + end) + : M (bool). + +Definition check_misaligned (vaddr : mword 64) (width : word_width) +: M (bool) := + + (if ((plat_enable_misaligned_access tt)) then returnm (false : bool) + else + (match width with + | BYTE => returnm (false : bool) + | HALF => + (bit_to_bool (access_vec_dec vaddr 0)) >>= fun w__0 : bool => + returnm ((Bool.eqb (w__0 : bool) true) + : bool) + | WORD => + (or_boolM + ((bit_to_bool (access_vec_dec vaddr 0)) >>= fun w__1 : bool => + returnm ((Bool.eqb (w__1 : bool) true) + : bool)) + ((bit_to_bool (access_vec_dec vaddr 1)) >>= fun w__2 : bool => + returnm ((Bool.eqb (w__2 : bool) true) + : bool))) + : M (bool) + | DOUBLE => + (or_boolM + ((bit_to_bool (access_vec_dec vaddr 0)) >>= fun w__4 : bool => + returnm ((Bool.eqb (w__4 : bool) true) + : bool)) + ((or_boolM + ((bit_to_bool (access_vec_dec vaddr 1)) >>= fun w__5 : bool => + returnm ((Bool.eqb (w__5 : bool) true) + : bool)) + ((bit_to_bool (access_vec_dec vaddr 2)) >>= fun w__6 : bool => + returnm ((Bool.eqb (w__6 : bool) true) + : bool))) + : M (bool))) + : M (bool) + end) + : M (bool)) + : M (bool). + +Definition maybe_aq_forwards (arg_ : bool) +: string := + + match arg_ with | true => ".aq" | false => "" end. + +Definition maybe_aq_backwards (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ ".aq")) then true + else false. + +Definition maybe_aq_forwards_matches (arg_ : bool) +: bool := + + match arg_ with | true => true | false => true end. + +Definition maybe_aq_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ ".aq")) then true + else if ((generic_eq p0_ "")) then true + else false. + +Definition _s604_ (_s605_ : string) +: option string := + + let _s606_ := _s605_ in + if ((string_startswith _s606_ "")) then + match (string_drop _s606_ (projT1 (string_length ""))) with | s_ => Some (s_) end + else None. + +Definition _s600_ (_s601_ : string) +: option string := + + let _s602_ := _s601_ in + if ((string_startswith _s602_ ".aq")) then + match (string_drop _s602_ (projT1 (string_length ".aq"))) with | s_ => Some (s_) end + else None. + +Definition maybe_aq_matches_prefix (arg_ : string) +: M (option ((bool * {n : Z & ArithFact (n >= 0)}))) := + + let _s603_ := arg_ in + (if ((match (_s600_ _s603_) with | Some (s_) => true | _ => false end)) then + (match (_s600_ _s603_) with + | Some (s_) => + returnm ((Some + ((true, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bool * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s604_ _s603_) with | Some (s_) => true | _ => false end)) then + (match (_s604_ _s603_) with + | Some (s_) => + returnm ((Some + ((false, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bool * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((bool * {n : Z & ArithFact (n >= 0)})))) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))). + +Definition maybe_rl_forwards (arg_ : bool) +: string := + + match arg_ with | true => ".rl" | false => "" end. + +Definition maybe_rl_backwards (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ ".rl")) then true + else false. + +Definition maybe_rl_forwards_matches (arg_ : bool) +: bool := + + match arg_ with | true => true | false => true end. + +Definition maybe_rl_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ ".rl")) then true + else if ((generic_eq p0_ "")) then true + else false. + +Definition _s612_ (_s613_ : string) +: option string := + + let _s614_ := _s613_ in + if ((string_startswith _s614_ "")) then + match (string_drop _s614_ (projT1 (string_length ""))) with | s_ => Some (s_) end + else None. + +Definition _s608_ (_s609_ : string) +: option string := + + let _s610_ := _s609_ in + if ((string_startswith _s610_ ".rl")) then + match (string_drop _s610_ (projT1 (string_length ".rl"))) with | s_ => Some (s_) end + else None. + +Definition maybe_rl_matches_prefix (arg_ : string) +: M (option ((bool * {n : Z & ArithFact (n >= 0)}))) := + + let _s611_ := arg_ in + (if ((match (_s608_ _s611_) with | Some (s_) => true | _ => false end)) then + (match (_s608_ _s611_) with + | Some (s_) => + returnm ((Some + ((true, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bool * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s612_ _s611_) with | Some (s_) => true | _ => false end)) then + (match (_s612_ _s611_) with + | Some (s_) => + returnm ((Some + ((false, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bool * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((bool * {n : Z & ArithFact (n >= 0)})))) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))). + +Definition maybe_u_forwards (arg_ : bool) +: string := + + match arg_ with | true => "u" | false => "" end. + +Definition maybe_u_backwards (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "u")) then true + else false. + +Definition maybe_u_forwards_matches (arg_ : bool) +: bool := + + match arg_ with | true => true | false => true end. + +Definition maybe_u_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "u")) then true + else if ((generic_eq p0_ "")) then true + else false. + +Definition _s620_ (_s621_ : string) +: option string := + + let _s622_ := _s621_ in + if ((string_startswith _s622_ "")) then + match (string_drop _s622_ (projT1 (string_length ""))) with | s_ => Some (s_) end + else None. + +Definition _s616_ (_s617_ : string) +: option string := + + let _s618_ := _s617_ in + if ((string_startswith _s618_ "u")) then + match (string_drop _s618_ (projT1 (string_length "u"))) with | s_ => Some (s_) end + else None. + +Definition maybe_u_matches_prefix (arg_ : string) +: M (option ((bool * {n : Z & ArithFact (n >= 0)}))) := + + let _s619_ := arg_ in + (if ((match (_s616_ _s619_) with | Some (s_) => true | _ => false end)) then + (match (_s616_ _s619_) with + | Some (s_) => + returnm ((Some + ((true, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bool * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s620_ _s619_) with | Some (s_) => true | _ => false end)) then + (match (_s620_ _s619_) with + | Some (s_) => + returnm ((Some + ((false, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bool * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((bool * {n : Z & ArithFact (n >= 0)})))) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))). + +Definition shiftw_mnemonic_forwards (arg_ : sop) +: string := + + match arg_ with | RISCV_SLLI => "slli" | RISCV_SRLI => "srli" | RISCV_SRAI => "srai" end. + +Definition shiftw_mnemonic_backwards (arg_ : string) +: sop := + + let p0_ := arg_ in + if ((generic_eq p0_ "slli")) then RISCV_SLLI + else if ((generic_eq p0_ "srli")) then RISCV_SRLI + else RISCV_SRAI. + +Definition shiftw_mnemonic_forwards_matches (arg_ : sop) +: bool := + + match arg_ with | RISCV_SLLI => true | RISCV_SRLI => true | RISCV_SRAI => true end. + +Definition shiftw_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "slli")) then true + else if ((generic_eq p0_ "srli")) then true + else if ((generic_eq p0_ "srai")) then true + else false. + +Definition _s632_ (_s633_ : string) +: option string := + + let _s634_ := _s633_ in + if ((string_startswith _s634_ "srai")) then + match (string_drop _s634_ (projT1 (string_length "srai"))) with | s_ => Some (s_) end + else None. + +Definition _s628_ (_s629_ : string) +: option string := + + let _s630_ := _s629_ in + if ((string_startswith _s630_ "srli")) then + match (string_drop _s630_ (projT1 (string_length "srli"))) with | s_ => Some (s_) end + else None. + +Definition _s624_ (_s625_ : string) +: option string := + + let _s626_ := _s625_ in + if ((string_startswith _s626_ "slli")) then + match (string_drop _s626_ (projT1 (string_length "slli"))) with | s_ => Some (s_) end + else None. + +Definition shiftw_mnemonic_matches_prefix (arg_ : string) +: M (option ((sop * {n : Z & ArithFact (n >= 0)}))) := + + let _s627_ := arg_ in + (if ((match (_s624_ _s627_) with | Some (s_) => true | _ => false end)) then + (match (_s624_ _s627_) with + | Some (s_) => + returnm ((Some + ((RISCV_SLLI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((sop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s628_ _s627_) with | Some (s_) => true | _ => false end)) then + (match (_s628_ _s627_) with + | Some (s_) => + returnm ((Some + ((RISCV_SRLI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((sop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s632_ _s627_) with | Some (s_) => true | _ => false end)) then + (match (_s632_ _s627_) with + | Some (s_) => + returnm ((Some + ((RISCV_SRAI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((sop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((sop * {n : Z & ArithFact (n >= 0)})))) + : M (option ((sop * {n : Z & ArithFact (n >= 0)}))). + +Definition rtypew_mnemonic_forwards (arg_ : ropw) +: string := + + match arg_ with + | RISCV_ADDW => "addw" + | RISCV_SUBW => "subw" + | RISCV_SLLW => "sllw" + | RISCV_SRLW => "srlw" + | RISCV_SRAW => "sraw" + end. + +Definition rtypew_mnemonic_backwards (arg_ : string) +: ropw := + + let p0_ := arg_ in + if ((generic_eq p0_ "addw")) then RISCV_ADDW + else if ((generic_eq p0_ "subw")) then RISCV_SUBW + else if ((generic_eq p0_ "sllw")) then RISCV_SLLW + else if ((generic_eq p0_ "srlw")) then RISCV_SRLW + else RISCV_SRAW. + +Definition rtypew_mnemonic_forwards_matches (arg_ : ropw) +: bool := + + match arg_ with + | RISCV_ADDW => true + | RISCV_SUBW => true + | RISCV_SLLW => true + | RISCV_SRLW => true + | RISCV_SRAW => true + end. + +Definition rtypew_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "addw")) then true + else if ((generic_eq p0_ "subw")) then true + else if ((generic_eq p0_ "sllw")) then true + else if ((generic_eq p0_ "srlw")) then true + else if ((generic_eq p0_ "sraw")) then true + else false. + +Definition _s652_ (_s653_ : string) +: option string := + + let _s654_ := _s653_ in + if ((string_startswith _s654_ "sraw")) then + match (string_drop _s654_ (projT1 (string_length "sraw"))) with | s_ => Some (s_) end + else None. + +Definition _s648_ (_s649_ : string) +: option string := + + let _s650_ := _s649_ in + if ((string_startswith _s650_ "srlw")) then + match (string_drop _s650_ (projT1 (string_length "srlw"))) with | s_ => Some (s_) end + else None. + +Definition _s644_ (_s645_ : string) +: option string := + + let _s646_ := _s645_ in + if ((string_startswith _s646_ "sllw")) then + match (string_drop _s646_ (projT1 (string_length "sllw"))) with | s_ => Some (s_) end + else None. + +Definition _s640_ (_s641_ : string) +: option string := + + let _s642_ := _s641_ in + if ((string_startswith _s642_ "subw")) then + match (string_drop _s642_ (projT1 (string_length "subw"))) with | s_ => Some (s_) end + else None. + +Definition _s636_ (_s637_ : string) +: option string := + + let _s638_ := _s637_ in + if ((string_startswith _s638_ "addw")) then + match (string_drop _s638_ (projT1 (string_length "addw"))) with | s_ => Some (s_) end + else None. + +Definition rtypew_mnemonic_matches_prefix (arg_ : string) +: M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) := + + let _s639_ := arg_ in + (if ((match (_s636_ _s639_) with | Some (s_) => true | _ => false end)) then + (match (_s636_ _s639_) with + | Some (s_) => + returnm ((Some + ((RISCV_ADDW, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((ropw * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s640_ _s639_) with | Some (s_) => true | _ => false end)) then + (match (_s640_ _s639_) with + | Some (s_) => + returnm ((Some + ((RISCV_SUBW, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((ropw * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s644_ _s639_) with | Some (s_) => true | _ => false end)) then + (match (_s644_ _s639_) with + | Some (s_) => + returnm ((Some + ((RISCV_SLLW, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((ropw * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s648_ _s639_) with | Some (s_) => true | _ => false end)) then + (match (_s648_ _s639_) with + | Some (s_) => + returnm ((Some + ((RISCV_SRLW, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((ropw * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s652_ _s639_) with | Some (s_) => true | _ => false end)) then + (match (_s652_ _s639_) with + | Some (s_) => + returnm ((Some + ((RISCV_SRAW, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((ropw * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((ropw * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))). + +Definition shiftiwop_mnemonic_forwards (arg_ : sopw) +: string := + + match arg_ with | RISCV_SLLIW => "slliw" | RISCV_SRLIW => "srliw" | RISCV_SRAIW => "sraiw" end. + +Definition shiftiwop_mnemonic_backwards (arg_ : string) +: sopw := + + let p0_ := arg_ in + if ((generic_eq p0_ "slliw")) then RISCV_SLLIW + else if ((generic_eq p0_ "srliw")) then RISCV_SRLIW + else RISCV_SRAIW. + +Definition shiftiwop_mnemonic_forwards_matches (arg_ : sopw) +: bool := + + match arg_ with | RISCV_SLLIW => true | RISCV_SRLIW => true | RISCV_SRAIW => true end. + +Definition shiftiwop_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "slliw")) then true + else if ((generic_eq p0_ "srliw")) then true + else if ((generic_eq p0_ "sraiw")) then true + else false. + +Definition _s664_ (_s665_ : string) +: option string := + + let _s666_ := _s665_ in + if ((string_startswith _s666_ "sraiw")) then + match (string_drop _s666_ (projT1 (string_length "sraiw"))) with | s_ => Some (s_) end + else None. + +Definition _s660_ (_s661_ : string) +: option string := + + let _s662_ := _s661_ in + if ((string_startswith _s662_ "srliw")) then + match (string_drop _s662_ (projT1 (string_length "srliw"))) with | s_ => Some (s_) end + else None. + +Definition _s656_ (_s657_ : string) +: option string := + + let _s658_ := _s657_ in + if ((string_startswith _s658_ "slliw")) then + match (string_drop _s658_ (projT1 (string_length "slliw"))) with | s_ => Some (s_) end + else None. + +Definition shiftiwop_mnemonic_matches_prefix (arg_ : string) +: M (option ((sopw * {n : Z & ArithFact (n >= 0)}))) := + + let _s659_ := arg_ in + (if ((match (_s656_ _s659_) with | Some (s_) => true | _ => false end)) then + (match (_s656_ _s659_) with + | Some (s_) => + returnm ((Some + ((RISCV_SLLIW, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((sopw * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((sopw * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((sopw * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s660_ _s659_) with | Some (s_) => true | _ => false end)) then + (match (_s660_ _s659_) with + | Some (s_) => + returnm ((Some + ((RISCV_SRLIW, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((sopw * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((sopw * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((sopw * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s664_ _s659_) with | Some (s_) => true | _ => false end)) then + (match (_s664_ _s659_) with + | Some (s_) => + returnm ((Some + ((RISCV_SRAIW, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((sopw * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((sopw * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((sopw * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((sopw * {n : Z & ArithFact (n >= 0)})))) + : M (option ((sopw * {n : Z & ArithFact (n >= 0)}))). + +Definition encdec_mul_op_forwards (arg_ : (bool * bool * bool)) +: M (mword 3) := + + (match arg_ with + | (false, true, true) => returnm ((vec_of_bits [B0;B0;B0] : mword 3) : mword 3) + | (true, true, true) => returnm ((vec_of_bits [B0;B0;B1] : mword 3) : mword 3) + | (true, true, false) => returnm ((vec_of_bits [B0;B1;B0] : mword 3) : mword 3) + | (true, false, false) => returnm ((vec_of_bits [B0;B1;B1] : mword 3) : mword 3) + | _ => exit tt : M (mword 3) + end) + : M (mword 3). + +Definition encdec_mul_op_backwards (arg_ : mword 3) +: (bool * bool * bool) := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then (false, true, true) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then (true, true, true) + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then (true, true, false) + else (true, false, false). + +Definition encdec_mul_op_forwards_matches (arg_ : (bool * bool * bool)) +: bool := + + match arg_ with + | (false, true, true) => true + | (true, true, true) => true + | (true, true, false) => true + | (true, false, false) => true + | _ => false + end. + +Definition encdec_mul_op_backwards_matches (arg_ : mword 3) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then true + else false. + +Definition mul_mnemonic_forwards (arg_ : (bool * bool * bool)) +: M (string) := + + (match arg_ with + | (false, true, true) => returnm ("mul" : string) + | (true, true, true) => returnm ("mulh" : string) + | (true, true, false) => returnm ("mulhsu" : string) + | (true, false, false) => returnm ("mulhu" : string) + | _ => exit tt : M (string) + end) + : M (string). + +Definition mul_mnemonic_backwards (arg_ : string) +: (bool * bool * bool) := + + let p0_ := arg_ in + if ((generic_eq p0_ "mul")) then (false, true, true) + else if ((generic_eq p0_ "mulh")) then (true, true, true) + else if ((generic_eq p0_ "mulhsu")) then (true, true, false) + else (true, false, false). + +Definition mul_mnemonic_forwards_matches (arg_ : (bool * bool * bool)) +: bool := + + match arg_ with + | (false, true, true) => true + | (true, true, true) => true + | (true, true, false) => true + | (true, false, false) => true + | _ => false + end. + +Definition mul_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "mul")) then true + else if ((generic_eq p0_ "mulh")) then true + else if ((generic_eq p0_ "mulhsu")) then true + else if ((generic_eq p0_ "mulhu")) then true + else false. + +Definition _s680_ (_s681_ : string) +: option string := + + let _s682_ := _s681_ in + if ((string_startswith _s682_ "mulhu")) then + match (string_drop _s682_ (projT1 (string_length "mulhu"))) with | s_ => Some (s_) end + else None. + +Definition _s676_ (_s677_ : string) +: option string := + + let _s678_ := _s677_ in + if ((string_startswith _s678_ "mulhsu")) then + match (string_drop _s678_ (projT1 (string_length "mulhsu"))) with | s_ => Some (s_) end + else None. + +Definition _s672_ (_s673_ : string) +: option string := + + let _s674_ := _s673_ in + if ((string_startswith _s674_ "mulh")) then + match (string_drop _s674_ (projT1 (string_length "mulh"))) with | s_ => Some (s_) end + else None. + +Definition _s668_ (_s669_ : string) +: option string := + + let _s670_ := _s669_ in + if ((string_startswith _s670_ "mul")) then + match (string_drop _s670_ (projT1 (string_length "mul"))) with | s_ => Some (s_) end + else None. + +Definition mul_mnemonic_matches_prefix (arg_ : string) +: M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) := + + let _s671_ := arg_ in + (if ((match (_s668_ _s671_) with | Some (s_) => true | _ => false end)) then + (match (_s668_ _s671_) with + | Some (s_) => + returnm ((Some + (((false, true, true), build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s672_ _s671_) with | Some (s_) => true | _ => false end)) then + (match (_s672_ _s671_) with + | Some (s_) => + returnm ((Some + (((true, true, true), build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s676_ _s671_) with | Some (s_) => true | _ => false end)) then + (match (_s676_ _s671_) with + | Some (s_) => + returnm ((Some + (((true, true, false), build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s680_ _s671_) with | Some (s_) => true | _ => false end)) then + (match (_s680_ _s671_) with + | Some (s_) => + returnm ((Some + (((true, false, false), build_ex (projT1 (sub_nat + (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))) + : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))). + +Definition maybe_not_u_forwards (arg_ : bool) +: string := + + match arg_ with | false => "u" | true => "" end. + +Definition maybe_not_u_backwards (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "u")) then false + else true. + +Definition maybe_not_u_forwards_matches (arg_ : bool) +: bool := + + match arg_ with | false => true | true => true end. + +Definition maybe_not_u_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "u")) then true + else if ((generic_eq p0_ "")) then true + else false. + +Definition _s688_ (_s689_ : string) +: option string := + + let _s690_ := _s689_ in + if ((string_startswith _s690_ "")) then + match (string_drop _s690_ (projT1 (string_length ""))) with | s_ => Some (s_) end + else None. + +Definition _s684_ (_s685_ : string) +: option string := + + let _s686_ := _s685_ in + if ((string_startswith _s686_ "u")) then + match (string_drop _s686_ (projT1 (string_length "u"))) with | s_ => Some (s_) end + else None. + +Definition maybe_not_u_matches_prefix (arg_ : string) +: M (option ((bool * {n : Z & ArithFact (n >= 0)}))) := + + let _s687_ := arg_ in + (if ((match (_s684_ _s687_) with | Some (s_) => true | _ => false end)) then + (match (_s684_ _s687_) with + | Some (s_) => + returnm ((Some + ((false, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bool * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s688_ _s687_) with | Some (s_) => true | _ => false end)) then + (match (_s688_ _s687_) with + | Some (s_) => + returnm ((Some + ((true, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bool * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((bool * {n : Z & ArithFact (n >= 0)})))) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))). + +Definition bit_maybe_r_forwards (arg_ : mword 1) +: string := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then "r" + else "". + +Definition bit_maybe_r_backwards (arg_ : string) +: mword 1 := + + let p0_ := arg_ in + if ((generic_eq p0_ "r")) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1). + +Definition bit_maybe_r_forwards_matches (arg_ : mword 1) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true + else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true + else false. + +Definition bit_maybe_r_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "r")) then true + else if ((generic_eq p0_ "")) then true + else false. + +Definition _s696_ (_s697_ : string) +: option string := + + let _s698_ := _s697_ in + if ((string_startswith _s698_ "")) then + match (string_drop _s698_ (projT1 (string_length ""))) with | s_ => Some (s_) end + else None. + +Definition _s692_ (_s693_ : string) +: option string := + + let _s694_ := _s693_ in + if ((string_startswith _s694_ "r")) then + match (string_drop _s694_ (projT1 (string_length "r"))) with | s_ => Some (s_) end + else None. + +Definition bit_maybe_r_matches_prefix (arg_ : string) +: M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) := + + let _s695_ := arg_ in + (if ((match (_s692_ _s695_) with | Some (s_) => true | _ => false end)) then + (match (_s692_ _s695_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1] : mword 1), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length s_))))))) + : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s696_ _s695_) with | Some (s_) => true | _ => false end)) then + (match (_s696_ _s695_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0] : mword 1), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length s_))))))) + : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))). + +Definition bit_maybe_w_forwards (arg_ : mword 1) +: string := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then "w" + else "". + +Definition bit_maybe_w_backwards (arg_ : string) +: mword 1 := + + let p0_ := arg_ in + if ((generic_eq p0_ "w")) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1). + +Definition bit_maybe_w_forwards_matches (arg_ : mword 1) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true + else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true + else false. + +Definition bit_maybe_w_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "w")) then true + else if ((generic_eq p0_ "")) then true + else false. + +Definition _s704_ (_s705_ : string) +: option string := + + let _s706_ := _s705_ in + if ((string_startswith _s706_ "")) then + match (string_drop _s706_ (projT1 (string_length ""))) with | s_ => Some (s_) end + else None. + +Definition _s700_ (_s701_ : string) +: option string := + + let _s702_ := _s701_ in + if ((string_startswith _s702_ "w")) then + match (string_drop _s702_ (projT1 (string_length "w"))) with | s_ => Some (s_) end + else None. + +Definition bit_maybe_w_matches_prefix (arg_ : string) +: M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) := + + let _s703_ := arg_ in + (if ((match (_s700_ _s703_) with | Some (s_) => true | _ => false end)) then + (match (_s700_ _s703_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1] : mword 1), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length s_))))))) + : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s704_ _s703_) with | Some (s_) => true | _ => false end)) then + (match (_s704_ _s703_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0] : mword 1), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length s_))))))) + : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))). + +Definition bit_maybe_i_forwards (arg_ : mword 1) +: string := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then "i" + else "". + +Definition bit_maybe_i_backwards (arg_ : string) +: mword 1 := + + let p0_ := arg_ in + if ((generic_eq p0_ "i")) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1). + +Definition bit_maybe_i_forwards_matches (arg_ : mword 1) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true + else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true + else false. + +Definition bit_maybe_i_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "i")) then true + else if ((generic_eq p0_ "")) then true + else false. + +Definition _s712_ (_s713_ : string) +: option string := + + let _s714_ := _s713_ in + if ((string_startswith _s714_ "")) then + match (string_drop _s714_ (projT1 (string_length ""))) with | s_ => Some (s_) end + else None. + +Definition _s708_ (_s709_ : string) +: option string := + + let _s710_ := _s709_ in + if ((string_startswith _s710_ "i")) then + match (string_drop _s710_ (projT1 (string_length "i"))) with | s_ => Some (s_) end + else None. + +Definition bit_maybe_i_matches_prefix (arg_ : string) +: M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) := + + let _s711_ := arg_ in + (if ((match (_s708_ _s711_) with | Some (s_) => true | _ => false end)) then + (match (_s708_ _s711_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1] : mword 1), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length s_))))))) + : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s712_ _s711_) with | Some (s_) => true | _ => false end)) then + (match (_s712_ _s711_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0] : mword 1), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length s_))))))) + : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))). + +Definition bit_maybe_o_forwards (arg_ : mword 1) +: string := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then "o" + else "". + +Definition bit_maybe_o_backwards (arg_ : string) +: mword 1 := + + let p0_ := arg_ in + if ((generic_eq p0_ "o")) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1). + +Definition bit_maybe_o_forwards_matches (arg_ : mword 1) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true + else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true + else false. + +Definition bit_maybe_o_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "o")) then true + else if ((generic_eq p0_ "")) then true + else false. + +Definition _s720_ (_s721_ : string) +: option string := + + let _s722_ := _s721_ in + if ((string_startswith _s722_ "")) then + match (string_drop _s722_ (projT1 (string_length ""))) with | s_ => Some (s_) end + else None. + +Definition _s716_ (_s717_ : string) +: option string := + + let _s718_ := _s717_ in + if ((string_startswith _s718_ "o")) then + match (string_drop _s718_ (projT1 (string_length "o"))) with | s_ => Some (s_) end + else None. + +Definition bit_maybe_o_matches_prefix (arg_ : string) +: M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) := + + let _s719_ := arg_ in + (if ((match (_s716_ _s719_) with | Some (s_) => true | _ => false end)) then + (match (_s716_ _s719_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1] : mword 1), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length s_))))))) + : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s720_ _s719_) with | Some (s_) => true | _ => false end)) then + (match (_s720_ _s719_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0] : mword 1), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length s_))))))) + : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))). + +Definition fence_bits_forwards (arg_ : mword 4) +: string := + + match arg_ with + | v__0 => + let i : bits 1 := subrange_vec_dec v__0 3 3 in + let w : bits 1 := subrange_vec_dec v__0 0 0 in + let r : bits 1 := subrange_vec_dec v__0 1 1 in + let o : bits 1 := subrange_vec_dec v__0 2 2 in + let i : bits 1 := subrange_vec_dec v__0 3 3 in + string_append (bit_maybe_i_forwards i) + (string_append (bit_maybe_o_forwards o) + (string_append (bit_maybe_r_forwards r) (string_append (bit_maybe_w_forwards w) ""))) + end. + +Definition _s724_ (_s725_ : string) +: M (option ((mword 1 * mword 1 * mword 1 * mword 1))) := + + (match _s725_ with + | _s726_ => + (bit_maybe_i_matches_prefix _s726_) >>= fun w__0 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (i,(existT _ _s727_ _)) => + (match (string_drop _s726_ _s727_) with + | _s728_ => + (bit_maybe_o_matches_prefix _s728_) >>= fun w__1 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (o,(existT _ _s729_ _)) => + (match (string_drop _s728_ _s729_) with + | _s730_ => + (bit_maybe_r_matches_prefix _s730_) >>= fun w__2 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (r,(existT _ _s731_ _)) => + (match (string_drop _s730_ _s731_) with + | _s732_ => + (bit_maybe_w_matches_prefix _s732_) >>= fun w__3 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (w,(existT _ _s733_ _)) => + let p0_ := string_drop _s732_ _s733_ in + if ((generic_eq p0_ "")) then Some ((i, o, r, w)) + else None + | _ => None + end) + : option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))). + +Definition fence_bits_backwards (arg_ : string) +: M (mword 4) := + + let _s734_ := arg_ in + (_s724_ _s734_) >>= fun w__0 : option ((mword 1 * mword 1 * mword 1 * mword 1)) => + (match w__0 with + | Some (i,o,r,w) => + returnm ((concat_vec (i : bits 1) + (concat_vec (o : bits 1) (concat_vec (r : bits 1) (w : bits 1)))) + : mword (1 + (1 + (1 + 1)))) + | _ => exit tt : M (mword 4) + end) + : M (mword 4). + +Definition fence_bits_forwards_matches (arg_ : mword 4) +: bool := + + match arg_ with | v__1 => true end. + +Definition _s735_ (_s736_ : string) +: M (option ((mword 1 * mword 1 * mword 1 * mword 1))) := + + (match _s736_ with + | _s737_ => + (bit_maybe_i_matches_prefix _s737_) >>= fun w__0 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (i,(existT _ _s738_ _)) => + (match (string_drop _s737_ _s738_) with + | _s739_ => + (bit_maybe_o_matches_prefix _s739_) >>= fun w__1 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (o,(existT _ _s740_ _)) => + (match (string_drop _s739_ _s740_) with + | _s741_ => + (bit_maybe_r_matches_prefix _s741_) >>= fun w__2 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (r,(existT _ _s742_ _)) => + (match (string_drop _s741_ _s742_) with + | _s743_ => + (bit_maybe_w_matches_prefix _s743_) >>= fun w__3 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (w,(existT _ _s744_ _)) => + let p0_ := string_drop _s743_ _s744_ in + if ((generic_eq p0_ "")) then Some ((i, o, r, w)) + else None + | _ => None + end) + : option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))). + +Definition fence_bits_backwards_matches (arg_ : string) +: M (bool) := + + let _s745_ := arg_ in + (_s735_ _s745_) >>= fun w__0 : option ((mword 1 * mword 1 * mword 1 * mword 1)) => + (if ((match w__0 with | Some (i,o,r,w) => true | _ => false end)) then + (_s735_ _s745_) >>= fun w__1 : option ((mword 1 * mword 1 * mword 1 * mword 1)) => + (match w__1 with | Some (i,o,r,w) => returnm (true : bool) | _ => exit tt : M (bool) end) + : M (bool) + else returnm (false : bool)) + : M (bool). + +Definition _s746_ (_s747_ : string) +: M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) := + + (match _s747_ with + | _s748_ => + (bit_maybe_i_matches_prefix _s748_) >>= fun w__0 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (i,(existT _ _s749_ _)) => + (match (string_drop _s748_ _s749_) with + | _s750_ => + (bit_maybe_o_matches_prefix _s750_) >>= fun w__1 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (o,(existT _ _s751_ _)) => + (match (string_drop _s750_ _s751_) with + | _s752_ => + (bit_maybe_r_matches_prefix _s752_) >>= fun w__2 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (r,(existT _ _s753_ _)) => + (match (string_drop _s752_ _s753_) with + | _s754_ => + (bit_maybe_w_matches_prefix _s754_) >>= fun w__3 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (w,(existT _ _s755_ _)) => + match (string_drop _s754_ _s755_) with + | s_ => Some ((i, o, r, w, s_)) + end + | _ => None + end) + : option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) + | _ => + returnm (None + : option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) + | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) + | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string))). + +Definition fence_bits_matches_prefix (arg_ : string) +: M (option ((mword 4 * {n : Z & ArithFact (n >= 0)}))) := + + let _s756_ := arg_ in + (_s746_ _s756_) >>= fun w__0 : option ((mword 1 * mword 1 * mword 1 * mword 1 * string)) => + (if ((match w__0 with | Some (i,o,r,w,s_) => true | _ => false end)) then + (_s746_ _s756_) >>= fun w__1 : option ((mword 1 * mword 1 * mword 1 * mword 1 * string)) => + (match w__1 with + | Some (i,o,r,w,s_) => + returnm ((Some + ((concat_vec (i : bits 1) + (concat_vec (o : bits 1) (concat_vec (r : bits 1) (w : bits 1))), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 4 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 4 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 4 * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((mword 4 * {n : Z & ArithFact (n >= 0)})))) + : M (option ((mword 4 * {n : Z & ArithFact (n >= 0)}))). + +Definition aqrl_str (aq : bool) (rl : bool) +: string := + + match (aq, rl) with + | (false, false) => "" + | (false, true) => ".rl" + | (true, false) => ".aq" + | (true, true) => ".aqrl" + end. + +Definition lrsc_width_str (width : word_width) +: string := + + match width with | BYTE => ".b" | HALF => ".h" | WORD => ".w" | DOUBLE => ".d" end. + +Definition process_loadres {n : Z} +(rd : mword 5) (addr : mword 64) (value : MemoryOpResult (mword (8 * n))) (is_unsigned : bool) +`{ArithFact ((0 + 1) <= n /\ n <= 8)} +: M (bool) := + + (match (extend_value is_unsigned value) with + | MemValue (result) => + let '_ := (load_reservation addr) : unit in + (wX (projT1 (regbits_to_regno rd)) result) >> returnm (true : bool) + | MemException (e) => (handle_mem_exception addr e) >> returnm (false : bool) + end) + : M (bool). + +Definition encdec_amoop_forwards (arg_ : amoop) +: mword 5 := + + match arg_ with + | AMOSWAP => (vec_of_bits [B0;B0;B0;B0;B1] : mword 5) + | AMOADD => (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + | AMOXOR => (vec_of_bits [B0;B0;B1;B0;B0] : mword 5) + | AMOAND => (vec_of_bits [B0;B1;B1;B0;B0] : mword 5) + | AMOOR => (vec_of_bits [B0;B1;B0;B0;B0] : mword 5) + | AMOMIN => (vec_of_bits [B1;B0;B0;B0;B0] : mword 5) + | AMOMAX => (vec_of_bits [B1;B0;B1;B0;B0] : mword 5) + | AMOMINU => (vec_of_bits [B1;B1;B0;B0;B0] : mword 5) + | AMOMAXU => (vec_of_bits [B1;B1;B1;B0;B0] : mword 5) + end. + +Definition encdec_amoop_backwards (arg_ : mword 5) +: amoop := + + let b__0 := arg_ in + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))))) + then + AMOSWAP + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))))) + then + AMOADD + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : mword 5))))) + then + AMOXOR + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : mword 5))))) + then + AMOAND + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : mword 5))))) + then + AMOOR + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : mword 5))))) + then + AMOMIN + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : mword 5))))) + then + AMOMAX + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : mword 5))))) + then + AMOMINU + else AMOMAXU. + +Definition encdec_amoop_forwards_matches (arg_ : amoop) +: bool := + + match arg_ with + | AMOSWAP => true + | AMOADD => true + | AMOXOR => true + | AMOAND => true + | AMOOR => true + | AMOMIN => true + | AMOMAX => true + | AMOMINU => true + | AMOMAXU => true + end. + +Definition encdec_amoop_backwards_matches (arg_ : mword 5) +: bool := + + let b__0 := arg_ in + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : mword 5))))) + then + true + else false. + +Definition amo_mnemonic_forwards (arg_ : amoop) +: string := + + match arg_ with + | AMOSWAP => "amoswap" + | AMOADD => "amoadd" + | AMOXOR => "amoxor" + | AMOAND => "amoand" + | AMOOR => "amoor" + | AMOMIN => "amomin" + | AMOMAX => "amomax" + | AMOMINU => "amominu" + | AMOMAXU => "amomaxu" + end. + +Definition amo_mnemonic_backwards (arg_ : string) +: amoop := + + let p0_ := arg_ in + if ((generic_eq p0_ "amoswap")) then AMOSWAP + else if ((generic_eq p0_ "amoadd")) then AMOADD + else if ((generic_eq p0_ "amoxor")) then AMOXOR + else if ((generic_eq p0_ "amoand")) then AMOAND + else if ((generic_eq p0_ "amoor")) then AMOOR + else if ((generic_eq p0_ "amomin")) then AMOMIN + else if ((generic_eq p0_ "amomax")) then AMOMAX + else if ((generic_eq p0_ "amominu")) then AMOMINU + else AMOMAXU. + +Definition amo_mnemonic_forwards_matches (arg_ : amoop) +: bool := + + match arg_ with + | AMOSWAP => true + | AMOADD => true + | AMOXOR => true + | AMOAND => true + | AMOOR => true + | AMOMIN => true + | AMOMAX => true + | AMOMINU => true + | AMOMAXU => true + end. + +Definition amo_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "amoswap")) then true + else if ((generic_eq p0_ "amoadd")) then true + else if ((generic_eq p0_ "amoxor")) then true + else if ((generic_eq p0_ "amoand")) then true + else if ((generic_eq p0_ "amoor")) then true + else if ((generic_eq p0_ "amomin")) then true + else if ((generic_eq p0_ "amomax")) then true + else if ((generic_eq p0_ "amominu")) then true + else if ((generic_eq p0_ "amomaxu")) then true + else false. + +Definition _s789_ (_s790_ : string) +: option string := + + let _s791_ := _s790_ in + if ((string_startswith _s791_ "amomaxu")) then + match (string_drop _s791_ (projT1 (string_length "amomaxu"))) with | s_ => Some (s_) end + else None. + +Definition _s785_ (_s786_ : string) +: option string := + + let _s787_ := _s786_ in + if ((string_startswith _s787_ "amominu")) then + match (string_drop _s787_ (projT1 (string_length "amominu"))) with | s_ => Some (s_) end + else None. + +Definition _s781_ (_s782_ : string) +: option string := + + let _s783_ := _s782_ in + if ((string_startswith _s783_ "amomax")) then + match (string_drop _s783_ (projT1 (string_length "amomax"))) with | s_ => Some (s_) end + else None. + +Definition _s777_ (_s778_ : string) +: option string := + + let _s779_ := _s778_ in + if ((string_startswith _s779_ "amomin")) then + match (string_drop _s779_ (projT1 (string_length "amomin"))) with | s_ => Some (s_) end + else None. + +Definition _s773_ (_s774_ : string) +: option string := + + let _s775_ := _s774_ in + if ((string_startswith _s775_ "amoor")) then + match (string_drop _s775_ (projT1 (string_length "amoor"))) with | s_ => Some (s_) end + else None. + +Definition _s769_ (_s770_ : string) +: option string := + + let _s771_ := _s770_ in + if ((string_startswith _s771_ "amoand")) then + match (string_drop _s771_ (projT1 (string_length "amoand"))) with | s_ => Some (s_) end + else None. + +Definition _s765_ (_s766_ : string) +: option string := + + let _s767_ := _s766_ in + if ((string_startswith _s767_ "amoxor")) then + match (string_drop _s767_ (projT1 (string_length "amoxor"))) with | s_ => Some (s_) end + else None. + +Definition _s761_ (_s762_ : string) +: option string := + + let _s763_ := _s762_ in + if ((string_startswith _s763_ "amoadd")) then + match (string_drop _s763_ (projT1 (string_length "amoadd"))) with | s_ => Some (s_) end + else None. + +Definition _s757_ (_s758_ : string) +: option string := + + let _s759_ := _s758_ in + if ((string_startswith _s759_ "amoswap")) then + match (string_drop _s759_ (projT1 (string_length "amoswap"))) with | s_ => Some (s_) end + else None. + +Definition amo_mnemonic_matches_prefix (arg_ : string) +: M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) := + + let _s760_ := arg_ in + (if ((match (_s757_ _s760_) with | Some (s_) => true | _ => false end)) then + (match (_s757_ _s760_) with + | Some (s_) => + returnm ((Some + ((AMOSWAP, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((amoop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s761_ _s760_) with | Some (s_) => true | _ => false end)) then + (match (_s761_ _s760_) with + | Some (s_) => + returnm ((Some + ((AMOADD, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((amoop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s765_ _s760_) with | Some (s_) => true | _ => false end)) then + (match (_s765_ _s760_) with + | Some (s_) => + returnm ((Some + ((AMOXOR, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((amoop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s769_ _s760_) with | Some (s_) => true | _ => false end)) then + (match (_s769_ _s760_) with + | Some (s_) => + returnm ((Some + ((AMOAND, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((amoop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s773_ _s760_) with | Some (s_) => true | _ => false end)) then + (match (_s773_ _s760_) with + | Some (s_) => + returnm ((Some + ((AMOOR, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((amoop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s777_ _s760_) with | Some (s_) => true | _ => false end)) then + (match (_s777_ _s760_) with + | Some (s_) => + returnm ((Some + ((AMOMIN, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((amoop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s781_ _s760_) with | Some (s_) => true | _ => false end)) then + (match (_s781_ _s760_) with + | Some (s_) => + returnm ((Some + ((AMOMAX, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((amoop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s785_ _s760_) with | Some (s_) => true | _ => false end)) then + (match (_s785_ _s760_) with + | Some (s_) => + returnm ((Some + ((AMOMINU, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((amoop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s789_ _s760_) with | Some (s_) => true | _ => false end)) then + (match (_s789_ _s760_) with + | Some (s_) => + returnm ((Some + ((AMOMAXU, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((amoop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((amoop * {n : Z & ArithFact (n >= 0)})))) + : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))). + +Definition encdec_csrop_forwards (arg_ : csrop) +: mword 2 := + + match arg_ with + | CSRRW => (vec_of_bits [B0;B1] : mword 2) + | CSRRS => (vec_of_bits [B1;B0] : mword 2) + | CSRRC => (vec_of_bits [B1;B1] : mword 2) + end. + +Definition encdec_csrop_backwards (arg_ : mword 2) +: csrop := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then CSRRW + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then CSRRS + else CSRRC. + +Definition encdec_csrop_forwards_matches (arg_ : csrop) +: bool := + + match arg_ with | CSRRW => true | CSRRS => true | CSRRC => true end. + +Definition encdec_csrop_backwards_matches (arg_ : mword 2) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then true + else false. + +Definition readCSR (csr : mword 12) +: M (mword 64) := + + let b__0 := csr in + (if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then + ((read_reg mvendorid_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then + ((read_reg marchid_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then + ((read_reg mimpid_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then + ((read_reg mhartid_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + read_reg mstatus_ref >>= fun w__4 : Mstatus => returnm ((_get_Mstatus_bits w__4) : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + read_reg misa_ref >>= fun w__5 : Misa => returnm ((_get_Misa_bits w__5) : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + read_reg medeleg_ref >>= fun w__6 : Medeleg => returnm ((_get_Medeleg_bits w__6) : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + read_reg mideleg_ref >>= fun w__7 : Minterrupts => + returnm ((_get_Minterrupts_bits w__7) + : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + read_reg mie_ref >>= fun w__8 : Minterrupts => + returnm ((_get_Minterrupts_bits w__8) + : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + read_reg mtvec_ref >>= fun w__9 : Mtvec => returnm ((_get_Mtvec_bits w__9) : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then + read_reg mcounteren_ref >>= fun w__10 : Counteren => + returnm ((EXTZ 64 (_get_Counteren_bits w__10)) + : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + ((read_reg mscratch_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + ((read_reg mepc_ref) : M (mword 64)) >>= fun w__12 : xlenbits => + (pc_alignment_mask tt) >>= fun w__13 : mword 64 => returnm ((and_vec w__12 w__13) : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + read_reg mcause_ref >>= fun w__14 : Mcause => returnm ((_get_Mcause_bits w__14) : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + ((read_reg mtval_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + read_reg mip_ref >>= fun w__16 : Minterrupts => + returnm ((_get_Minterrupts_bits w__16) + : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then + ((read_reg pmpcfg0_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then + ((read_reg pmpaddr0_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + read_reg mstatus_ref >>= fun w__19 : Mstatus => + returnm ((_get_Sstatus_bits (lower_mstatus w__19)) + : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + read_reg sedeleg_ref >>= fun w__20 : Sedeleg => + returnm ((_get_Sedeleg_bits w__20) + : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + read_reg sideleg_ref >>= fun w__21 : Sinterrupts => + returnm ((_get_Sinterrupts_bits w__21) + : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + read_reg mie_ref >>= fun w__22 : Minterrupts => + read_reg mideleg_ref >>= fun w__23 : Minterrupts => + returnm ((_get_Sinterrupts_bits (lower_mie w__22 w__23)) + : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + read_reg stvec_ref >>= fun w__24 : Mtvec => returnm ((_get_Mtvec_bits w__24) : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then + read_reg scounteren_ref >>= fun w__25 : Counteren => + returnm ((EXTZ 64 (_get_Counteren_bits w__25)) + : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + ((read_reg sscratch_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + ((read_reg sepc_ref) : M (mword 64)) >>= fun w__27 : xlenbits => + (pc_alignment_mask tt) >>= fun w__28 : mword 64 => returnm ((and_vec w__27 w__28) : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + read_reg scause_ref >>= fun w__29 : Mcause => returnm ((_get_Mcause_bits w__29) : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + ((read_reg stval_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + read_reg mip_ref >>= fun w__31 : Minterrupts => + read_reg mideleg_ref >>= fun w__32 : Minterrupts => + returnm ((_get_Sinterrupts_bits (lower_mip w__31 w__32)) + : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + ((read_reg satp_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + ((read_reg mcycle_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + ((read_reg mtime_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + ((read_reg minstret_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then + ((read_reg tselect_ref) : M (mword 64)) >>= fun w__37 : xlenbits => + returnm ((not_vec w__37) + : mword 64) + else + let '_ := (print_bits "unhandled read to CSR " csr) : unit in + returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + : mword 64)) >>= fun res : xlenbits => + let '_ := + (print_endline + (String.append "CSR " + (String.append ((csr_name csr) : string) (String.append " -> " (string_of_bits res))))) + : unit in + returnm (res + : mword 64). + +Definition writeCSR (csr : mword 12) (value : mword 64) +: M (unit) := + + let b__0 := csr in + (if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + read_reg mstatus_ref >>= fun w__0 : Mstatus => + write_reg mstatus_ref (legalize_mstatus w__0 value) >> + read_reg mstatus_ref >>= fun w__1 : Mstatus => + returnm ((Some + (_get_Mstatus_bits w__1)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + read_reg misa_ref >>= fun w__2 : Misa => + (legalize_misa w__2 value) >>= fun w__3 : Misa => + write_reg misa_ref w__3 >> + read_reg misa_ref >>= fun w__4 : Misa => + returnm ((Some + (_get_Misa_bits w__4)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + read_reg medeleg_ref >>= fun w__5 : Medeleg => + write_reg medeleg_ref (legalize_medeleg w__5 value) >> + read_reg medeleg_ref >>= fun w__6 : Medeleg => + returnm ((Some + (_get_Medeleg_bits w__6)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + read_reg mideleg_ref >>= fun w__7 : Minterrupts => + write_reg mideleg_ref (legalize_mideleg w__7 value) >> + read_reg mideleg_ref >>= fun w__8 : Minterrupts => + returnm ((Some + (_get_Minterrupts_bits w__8)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + read_reg mie_ref >>= fun w__9 : Minterrupts => + write_reg mie_ref (legalize_mie w__9 value) >> + read_reg mie_ref >>= fun w__10 : Minterrupts => + returnm ((Some + (_get_Minterrupts_bits w__10)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + read_reg mtvec_ref >>= fun w__11 : Mtvec => + write_reg mtvec_ref (legalize_tvec w__11 value) >> + read_reg mtvec_ref >>= fun w__12 : Mtvec => + returnm ((Some + (_get_Mtvec_bits w__12)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then + read_reg mcounteren_ref >>= fun w__13 : Counteren => + (legalize_mcounteren w__13 value) >>= fun w__14 : Counteren => + write_reg mcounteren_ref w__14 >> + read_reg mcounteren_ref >>= fun w__15 : Counteren => + returnm ((Some + (EXTZ 64 (_get_Counteren_bits w__15))) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + write_reg mscratch_ref value >> + ((read_reg mscratch_ref) : M (mword 64)) >>= fun w__16 : xlenbits => + returnm ((Some + (w__16)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + (legalize_xepc value) >>= fun w__17 : mword 64 => + write_reg mepc_ref w__17 >> + ((read_reg mepc_ref) : M (mword 64)) >>= fun w__18 : xlenbits => + returnm ((Some + (w__18)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + (_set_Mcause_bits mcause_ref value) >> + read_reg mcause_ref >>= fun w__19 : Mcause => + returnm ((Some + (_get_Mcause_bits w__19)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + write_reg mtval_ref value >> + ((read_reg mtval_ref) : M (mword 64)) >>= fun w__20 : xlenbits => + returnm ((Some + (w__20)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + read_reg mip_ref >>= fun w__21 : Minterrupts => + write_reg mip_ref (legalize_mip w__21 value) >> + read_reg mip_ref >>= fun w__22 : Minterrupts => + returnm ((Some + (_get_Minterrupts_bits w__22)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then + write_reg pmpcfg0_ref value >> + ((read_reg pmpcfg0_ref) : M (mword 64)) >>= fun w__23 : xlenbits => + returnm ((Some + (w__23)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then + write_reg pmpaddr0_ref value >> + ((read_reg pmpaddr0_ref) : M (mword 64)) >>= fun w__24 : xlenbits => + returnm ((Some + (w__24)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + read_reg mstatus_ref >>= fun w__25 : Mstatus => + write_reg mstatus_ref (legalize_sstatus w__25 value) >> + read_reg mstatus_ref >>= fun w__26 : Mstatus => + returnm ((Some + (_get_Mstatus_bits w__26)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + read_reg sedeleg_ref >>= fun w__27 : Sedeleg => + write_reg sedeleg_ref (legalize_sedeleg w__27 value) >> + read_reg sedeleg_ref >>= fun w__28 : Sedeleg => + returnm ((Some + (_get_Sedeleg_bits w__28)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + (_set_Sinterrupts_bits sideleg_ref value) >> + read_reg sideleg_ref >>= fun w__29 : Sinterrupts => + returnm ((Some + (_get_Sinterrupts_bits w__29)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + read_reg mie_ref >>= fun w__30 : Minterrupts => + read_reg mideleg_ref >>= fun w__31 : Minterrupts => + write_reg mie_ref (legalize_sie w__30 w__31 value) >> + read_reg mie_ref >>= fun w__32 : Minterrupts => + returnm ((Some + (_get_Minterrupts_bits w__32)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + read_reg stvec_ref >>= fun w__33 : Mtvec => + write_reg stvec_ref (legalize_tvec w__33 value) >> + read_reg stvec_ref >>= fun w__34 : Mtvec => + returnm ((Some + (_get_Mtvec_bits w__34)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then + read_reg scounteren_ref >>= fun w__35 : Counteren => + (legalize_scounteren w__35 value) >>= fun w__36 : Counteren => + write_reg scounteren_ref w__36 >> + read_reg scounteren_ref >>= fun w__37 : Counteren => + returnm ((Some + (EXTZ 64 (_get_Counteren_bits w__37))) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + write_reg sscratch_ref value >> + ((read_reg sscratch_ref) : M (mword 64)) >>= fun w__38 : xlenbits => + returnm ((Some + (w__38)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + (legalize_xepc value) >>= fun w__39 : mword 64 => + write_reg sepc_ref w__39 >> + ((read_reg sepc_ref) : M (mword 64)) >>= fun w__40 : xlenbits => + returnm ((Some + (w__40)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + (_set_Mcause_bits scause_ref value) >> + read_reg scause_ref >>= fun w__41 : Mcause => + returnm ((Some + (_get_Mcause_bits w__41)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + write_reg stval_ref value >> + ((read_reg stval_ref) : M (mword 64)) >>= fun w__42 : xlenbits => + returnm ((Some + (w__42)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + read_reg mip_ref >>= fun w__43 : Minterrupts => + read_reg mideleg_ref >>= fun w__44 : Minterrupts => + write_reg mip_ref (legalize_sip w__43 w__44 value) >> + read_reg mip_ref >>= fun w__45 : Minterrupts => + returnm ((Some + (_get_Minterrupts_bits w__45)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + (cur_Architecture tt) >>= fun w__46 : Architecture => + ((read_reg satp_ref) : M (mword 64)) >>= fun w__47 : xlenbits => + write_reg satp_ref (legalize_satp w__46 w__47 value) >> + ((read_reg satp_ref) : M (mword 64)) >>= fun w__48 : xlenbits => + returnm ((Some + (w__48)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then + write_reg tselect_ref value >> + ((read_reg tselect_ref) : M (mword 64)) >>= fun w__49 : xlenbits => + returnm ((Some + (w__49)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + write_reg mcycle_ref value >> + ((read_reg mcycle_ref) : M (mword 64)) >>= fun w__50 : xlenbits => + returnm ((Some + (w__50)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + write_reg minstret_ref value >> + write_reg minstret_written_ref true >> + ((read_reg minstret_ref) : M (mword 64)) >>= fun w__51 : xlenbits => + returnm ((Some + (w__51)) + : option (mword 64)) + else returnm (None : option (mword 64))) >>= fun res : option xlenbits => + returnm ((match res with + | Some (v) => + print_endline + (String.append "CSR " + (String.append ((csr_name csr) : string) + (String.append " <- " + (String.append (string_of_bits v) + (String.append " (input: " (String.append (string_of_bits value) ")")))))) + | None => print_bits "unhandled write to CSR " csr + end) + : unit). + +Definition maybe_i_forwards (arg_ : bool) +: string := + + match arg_ with | true => "i" | false => "" end. + +Definition maybe_i_backwards (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "i")) then true + else false. + +Definition maybe_i_forwards_matches (arg_ : bool) +: bool := + + match arg_ with | true => true | false => true end. + +Definition maybe_i_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "i")) then true + else if ((generic_eq p0_ "")) then true + else false. + +Definition _s797_ (_s798_ : string) +: option string := + + let _s799_ := _s798_ in + if ((string_startswith _s799_ "")) then + match (string_drop _s799_ (projT1 (string_length ""))) with | s_ => Some (s_) end + else None. + +Definition _s793_ (_s794_ : string) +: option string := + + let _s795_ := _s794_ in + if ((string_startswith _s795_ "i")) then + match (string_drop _s795_ (projT1 (string_length "i"))) with | s_ => Some (s_) end + else None. + +Definition maybe_i_matches_prefix (arg_ : string) +: M (option ((bool * {n : Z & ArithFact (n >= 0)}))) := + + let _s796_ := arg_ in + (if ((match (_s793_ _s796_) with | Some (s_) => true | _ => false end)) then + (match (_s793_ _s796_) with + | Some (s_) => + returnm ((Some + ((true, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bool * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s797_ _s796_) with | Some (s_) => true | _ => false end)) then + (match (_s797_ _s796_) with + | Some (s_) => + returnm ((Some + ((false, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bool * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((bool * {n : Z & ArithFact (n >= 0)})))) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))). + +Definition csr_mnemonic_forwards (arg_ : csrop) +: string := + + match arg_ with | CSRRW => "csrrw" | CSRRS => "csrrs" | CSRRC => "csrrc" end. + +Definition csr_mnemonic_backwards (arg_ : string) +: csrop := + + let p0_ := arg_ in + if ((generic_eq p0_ "csrrw")) then CSRRW + else if ((generic_eq p0_ "csrrs")) then CSRRS + else CSRRC. + +Definition csr_mnemonic_forwards_matches (arg_ : csrop) +: bool := + + match arg_ with | CSRRW => true | CSRRS => true | CSRRC => true end. + +Definition csr_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "csrrw")) then true + else if ((generic_eq p0_ "csrrs")) then true + else if ((generic_eq p0_ "csrrc")) then true + else false. + +Definition _s809_ (_s810_ : string) +: option string := + + let _s811_ := _s810_ in + if ((string_startswith _s811_ "csrrc")) then + match (string_drop _s811_ (projT1 (string_length "csrrc"))) with | s_ => Some (s_) end + else None. + +Definition _s805_ (_s806_ : string) +: option string := + + let _s807_ := _s806_ in + if ((string_startswith _s807_ "csrrs")) then + match (string_drop _s807_ (projT1 (string_length "csrrs"))) with | s_ => Some (s_) end + else None. + +Definition _s801_ (_s802_ : string) +: option string := + + let _s803_ := _s802_ in + if ((string_startswith _s803_ "csrrw")) then + match (string_drop _s803_ (projT1 (string_length "csrrw"))) with | s_ => Some (s_) end + else None. + +Definition csr_mnemonic_matches_prefix (arg_ : string) +: M (option ((csrop * {n : Z & ArithFact (n >= 0)}))) := + + let _s804_ := arg_ in + (if ((match (_s801_ _s804_) with | Some (s_) => true | _ => false end)) then + (match (_s801_ _s804_) with + | Some (s_) => + returnm ((Some + ((CSRRW, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((csrop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((csrop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((csrop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s805_ _s804_) with | Some (s_) => true | _ => false end)) then + (match (_s805_ _s804_) with + | Some (s_) => + returnm ((Some + ((CSRRS, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((csrop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((csrop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((csrop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s809_ _s804_) with | Some (s_) => true | _ => false end)) then + (match (_s809_ _s804_) with + | Some (s_) => + returnm ((Some + ((CSRRC, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((csrop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((csrop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((csrop * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((csrop * {n : Z & ArithFact (n >= 0)})))) + : M (option ((csrop * {n : Z & ArithFact (n >= 0)}))). + +Definition encdec_forwards (arg_ : ast) +: M (mword 32) := + + (match arg_ with + | UTYPE (imm,rd,op) => + returnm ((concat_vec (imm : mword 20) (concat_vec (rd : mword 5) (encdec_uop_forwards op))) + : mword (20 + (5 + 7))) + | RISCV_JAL (v__2,rd) => + let imm_19 : bits 1 := subrange_vec_dec v__2 20 20 in + let imm_8 : bits 1 := subrange_vec_dec v__2 11 11 in + let imm_7_0 : bits 8 := subrange_vec_dec v__2 19 12 in + let imm_19 : bits 1 := subrange_vec_dec v__2 20 20 in + let imm_18_13 : bits 6 := subrange_vec_dec v__2 10 5 in + let imm_12_9 : bits 4 := subrange_vec_dec v__2 4 1 in + returnm ((concat_vec (imm_19 : bits 1) + (concat_vec (imm_18_13 : bits 6) + (concat_vec (imm_12_9 : bits 4) + (concat_vec (imm_8 : bits 1) + (concat_vec (imm_7_0 : bits 8) + (concat_vec (rd : mword 5) + (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : mword 7))))))) + : mword 32) + | RISCV_JALR (imm,rs1,rd) => + returnm ((concat_vec (imm : mword 12) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (rd : mword 5) (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : mword 7))))) + : mword (12 + (5 + (3 + (5 + 7))))) + | BTYPE (v__4,rs2,rs1,op) => + let imm7_6 : bits 1 := subrange_vec_dec v__4 12 12 in + let imm7_6 : bits 1 := subrange_vec_dec v__4 12 12 in + let imm7_5_0 : bits 6 := subrange_vec_dec v__4 10 5 in + let imm5_4_1 : bits 4 := subrange_vec_dec v__4 4 1 in + let imm5_0 : bits 1 := subrange_vec_dec v__4 11 11 in + returnm ((concat_vec (imm7_6 : bits 1) + (concat_vec (imm7_5_0 : bits 6) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (encdec_bop_forwards op) + (concat_vec (imm5_4_1 : bits 4) + (concat_vec (imm5_0 : bits 1) + (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : mword 7)))))))) + : mword 32) + | ITYPE (imm,rs1,rd,op) => + returnm ((concat_vec (imm : mword 12) + (concat_vec (rs1 : mword 5) + (concat_vec (encdec_iop_forwards op) + (concat_vec (rd : mword 5) (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7))))) + : mword (12 + (5 + (3 + (5 + 7))))) + | SHIFTIOP (shamt,rs1,rd,RISCV_SLLI) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6) + (concat_vec (shamt : mword 6) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (6 + (6 + (5 + (3 + (5 + 7)))))) + | SHIFTIOP (shamt,rs1,rd,RISCV_SRLI) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6) + (concat_vec (shamt : mword 6) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (6 + (6 + (5 + (3 + (5 + 7)))))) + | SHIFTIOP (shamt,rs1,rd,RISCV_SRAI) => + returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0] : mword 6) + (concat_vec (shamt : mword 6) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (6 + (6 + (5 + (3 + (5 + 7)))))) + | RTYPE (rs2,rs1,rd,RISCV_ADD) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPE (rs2,rs1,rd,RISCV_SUB) => + returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPE (rs2,rs1,rd,RISCV_SLL) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPE (rs2,rs1,rd,RISCV_SLT) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B1;B0] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPE (rs2,rs1,rd,RISCV_SLTU) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B1;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPE (rs2,rs1,rd,RISCV_XOR) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPE (rs2,rs1,rd,RISCV_SRL) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPE (rs2,rs1,rd,RISCV_SRA) => + returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPE (rs2,rs1,rd,RISCV_OR) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B1;B0] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPE (rs2,rs1,rd,RISCV_AND) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B1;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | LOAD (imm,rs1,rd,is_unsigned,size,false,false) => + returnm ((concat_vec (imm : mword 12) + (concat_vec (rs1 : mword 5) + (concat_vec (bool_bits_forwards is_unsigned) + (concat_vec (size_bits_forwards size) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : mword 7)))))) + : mword (12 + (5 + (1 + (2 + (5 + 7)))))) + | STORE (v__6,rs2,rs1,size,false,false) => + let imm7 : bits 7 := subrange_vec_dec v__6 11 5 in + let imm7 : bits 7 := subrange_vec_dec v__6 11 5 in + let imm5 : bits 5 := subrange_vec_dec v__6 4 0 in + returnm ((concat_vec (imm7 : bits 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (size_bits_forwards size) + (concat_vec (imm5 : bits 5) + (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : mword 7))))))) + : mword 32) + | ADDIW (imm,rs1,rd) => + returnm ((concat_vec (imm : mword 12) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (rd : mword 5) (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))) + : mword (12 + (5 + (3 + (5 + 7))))) + | SHIFTW (shamt,rs1,rd,RISCV_SLLI) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (shamt : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | SHIFTW (shamt,rs1,rd,RISCV_SRLI) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (shamt : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | SHIFTW (shamt,rs1,rd,RISCV_SRAI) => + returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (shamt : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPEW (rs2,rs1,rd,RISCV_ADDW) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPEW (rs2,rs1,rd,RISCV_SUBW) => + returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPEW (rs2,rs1,rd,RISCV_SLLW) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPEW (rs2,rs1,rd,RISCV_SRLW) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPEW (rs2,rs1,rd,RISCV_SRAW) => + returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | SHIFTIWOP (shamt,rs1,rd,RISCV_SLLIW) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (shamt : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | SHIFTIWOP (shamt,rs1,rd,RISCV_SRLIW) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (shamt : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | SHIFTIWOP (shamt,rs1,rd,RISCV_SRAIW) => + returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (shamt : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | MUL (rs2,rs1,rd,high,signed1,signed2) => + (encdec_mul_op_forwards (high, signed1, signed2)) >>= fun w__0 : mword 3 => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (w__0 : bits 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | DIV (rs2,rs1,rd,s) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0] : mword 2) + (concat_vec (bool_not_bits_forwards s) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))) + : mword (7 + (5 + (5 + (2 + (1 + (5 + 7))))))) + | REM (rs2,rs1,rd,s) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B1] : mword 2) + (concat_vec (bool_not_bits_forwards s) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))) + : mword (7 + (5 + (5 + (2 + (1 + (5 + 7))))))) + | MULW (rs2,rs1,rd) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | DIVW (rs2,rs1,rd,s) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0] : mword 2) + (concat_vec (bool_not_bits_forwards s) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))))) + : mword (7 + (5 + (5 + (2 + (1 + (5 + 7))))))) + | REMW (rs2,rs1,rd,s) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B1] : mword 2) + (concat_vec (bool_not_bits_forwards s) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))))) + : mword (7 + (5 + (5 + (2 + (1 + (5 + 7))))))) + | FENCE (pred,succ) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (pred : mword 4) + (concat_vec (succ : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : mword 7))))))) + : mword (4 + (4 + (4 + (5 + (3 + (5 + 7))))))) + | FENCE_TSO (pred,succ) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0;B0] : mword 4) + (concat_vec (pred : mword 4) + (concat_vec (succ : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : mword 7))))))) + : mword (4 + (4 + (4 + (5 + (3 + (5 + 7))))))) + | FENCEI (tt) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : mword 7))))) + : mword (12 + (5 + (3 + (5 + 7))))) + | ECALL (tt) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7))))) + : mword (12 + (5 + (3 + (5 + 7))))) + | MRET (tt) => + returnm ((concat_vec (vec_of_bits [B0;B0;B1;B1;B0;B0;B0] : mword 7) + (concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | SRET (tt) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B0] : mword 7) + (concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | EBREAK (tt) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7))))) + : mword (12 + (5 + (3 + (5 + 7))))) + | WFI (tt) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7))))) + : mword (12 + (5 + (3 + (5 + 7))))) + | SFENCE_VMA (rs1,rs2) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | LOADRES (aq,rl,rs1,size,rd) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5) + (concat_vec (bool_bits_forwards aq) + (concat_vec (bool_bits_forwards rl) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (size_bits_forwards size) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7))))))))) + : mword (5 + (1 + (1 + (5 + (5 + (1 + (2 + (5 + 7))))))))) + | STORECON (aq,rl,rs2,rs1,size,rd) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B1] : mword 5) + (concat_vec (bool_bits_forwards aq) + (concat_vec (bool_bits_forwards rl) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (size_bits_forwards size) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7))))))))) + : mword (5 + (1 + (1 + (5 + (5 + (1 + (2 + (5 + 7))))))))) + | AMO (op,aq,rl,rs2,rs1,size,rd) => + returnm ((concat_vec (encdec_amoop_forwards op) + (concat_vec (bool_bits_forwards aq) + (concat_vec (bool_bits_forwards rl) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (size_bits_forwards size) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7))))))))) + : mword (5 + (1 + (1 + (5 + (5 + (1 + (2 + (5 + 7))))))))) + | CSR (csr,rs1,rd,is_imm,op) => + returnm ((concat_vec (csr : mword 12) + (concat_vec (rs1 : mword 5) + (concat_vec (bool_bits_forwards is_imm) + (concat_vec (encdec_csrop_forwards op) + (concat_vec (rd : mword 5) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (12 + (5 + (1 + (2 + (5 + 7)))))) + | STOP_FETCHING (tt) => + returnm ((concat_vec + (vec_of_bits [B1;B1;B1;B1;B1;B0;B1;B0;B1;B1;B0;B1;B1;B1;B1;B0] : mword 16) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B0;B0] : mword 2) + (concat_vec (vec_of_bits [B0;B1;B0] : mword 3) + (vec_of_bits [B1;B1] : mword 2)))))) + : mword (16 + (8 + (1 + (2 + (3 + 2)))))) + | THREAD_START (tt) => + returnm ((concat_vec + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1;B1;B1;B0] : mword 16) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B0;B0] : mword 2) + (concat_vec (vec_of_bits [B0;B1;B0] : mword 3) + (vec_of_bits [B1;B1] : mword 2)))))) + : mword (16 + (8 + (1 + (2 + (3 + 2)))))) + | ILLEGAL (s) => returnm (s : mword 32) + | _ => exit tt : M (mword 32) + end) + : M (mword 32). + +Definition encdec_backwards (arg_ : mword 32) +: ast := + + let v__7 := arg_ in + if ((let _mappingpatterns_23_ : mword 7 := subrange_vec_dec v__7 6 0 in + andb (encdec_uop_backwards_matches _mappingpatterns_23_) + (if ((encdec_uop_backwards_matches _mappingpatterns_23_)) then + let op := encdec_uop_backwards _mappingpatterns_23_ in + true + else false))) then + let imm : mword 20 := subrange_vec_dec v__7 31 12 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let imm : mword 20 := subrange_vec_dec v__7 31 12 in + let _mappingpatterns_23_ : mword 7 := subrange_vec_dec v__7 6 0 in + let op := encdec_uop_backwards _mappingpatterns_23_ in + UTYPE + ((imm, rd, op)) + else if ((eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : mword (6 - 0 + 1)))) then + let imm_19 : bits 1 := subrange_vec_dec v__7 31 31 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let imm_8 : bits 1 := subrange_vec_dec v__7 20 20 in + let imm_7_0 : bits 8 := subrange_vec_dec v__7 19 12 in + let imm_19 : bits 1 := subrange_vec_dec v__7 31 31 in + let imm_18_13 : bits 6 := subrange_vec_dec v__7 30 25 in + let imm_12_9 : bits 4 := subrange_vec_dec v__7 24 21 in + RISCV_JAL + ((concat_vec (imm_19 : bits 1) + (concat_vec (imm_7_0 : bits 8) + (concat_vec (imm_8 : bits 1) + (concat_vec (imm_18_13 : bits 6) + (concat_vec (imm_12_9 : bits 4) (vec_of_bits [B0] : mword 1))))), rd)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 14 12) (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : mword (6 - 0 + 1))))) then + let imm : mword 12 := subrange_vec_dec v__7 31 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let imm : mword 12 := subrange_vec_dec v__7 31 20 in + RISCV_JALR + ((imm, rs1, rd)) + else if ((andb + (let _mappingpatterns_24_ : mword 3 := subrange_vec_dec v__7 14 12 in + andb (encdec_bop_backwards_matches _mappingpatterns_24_) + (if ((encdec_bop_backwards_matches _mappingpatterns_24_)) then + let op := encdec_bop_backwards _mappingpatterns_24_ in + true + else false)) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : mword (6 - 0 + 1))))) then + let imm7_6 : bits 1 := subrange_vec_dec v__7 31 31 in + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let imm7_6 : bits 1 := subrange_vec_dec v__7 31 31 in + let imm7_5_0 : bits 6 := subrange_vec_dec v__7 30 25 in + let imm5_4_1 : bits 4 := subrange_vec_dec v__7 11 8 in + let imm5_0 : bits 1 := subrange_vec_dec v__7 7 7 in + let _mappingpatterns_24_ : mword 3 := subrange_vec_dec v__7 14 12 in + let op := encdec_bop_backwards _mappingpatterns_24_ in + BTYPE + ((concat_vec (imm7_6 : bits 1) + (concat_vec (imm5_0 : bits 1) + (concat_vec (imm7_5_0 : bits 6) + (concat_vec (imm5_4_1 : bits 4) (vec_of_bits [B0] : mword 1)))), rs2, rs1, op)) + else if ((andb + (let _mappingpatterns_25_ : mword 3 := subrange_vec_dec v__7 14 12 in + andb (encdec_iop_backwards_matches _mappingpatterns_25_) + (if ((encdec_iop_backwards_matches _mappingpatterns_25_)) then + let op := encdec_iop_backwards _mappingpatterns_25_ in + true + else false)) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))) then + let imm : mword 12 := subrange_vec_dec v__7 31 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let imm : mword 12 := subrange_vec_dec v__7 31 20 in + let _mappingpatterns_25_ : mword 3 := subrange_vec_dec v__7 14 12 in + let op := encdec_iop_backwards _mappingpatterns_25_ in + ITYPE + ((imm, rs1, rd, op)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let shamt : mword 6 := subrange_vec_dec v__7 25 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + SHIFTIOP + ((shamt, rs1, rd, RISCV_SLLI)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let shamt : mword 6 := subrange_vec_dec v__7 25 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + SHIFTIOP + ((shamt, rs1, rd, RISCV_SRLI)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 26) + (vec_of_bits [B0;B1;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let shamt : mword 6 := subrange_vec_dec v__7 25 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + SHIFTIOP + ((shamt, rs1, rd, RISCV_SRAI)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPE + ((rs2, rs1, rd, RISCV_ADD)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPE + ((rs2, rs1, rd, RISCV_SUB)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPE + ((rs2, rs1, rd, RISCV_SLL)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B1;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPE + ((rs2, rs1, rd, RISCV_SLT)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B1;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPE + ((rs2, rs1, rd, RISCV_SLTU)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPE + ((rs2, rs1, rd, RISCV_XOR)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPE + ((rs2, rs1, rd, RISCV_SRL)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPE + ((rs2, rs1, rd, RISCV_SRA)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B1;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPE + ((rs2, rs1, rd, RISCV_OR)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B1;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPE + ((rs2, rs1, rd, RISCV_AND)) + else if ((andb + (let _mappingpatterns_27_ : mword 2 := subrange_vec_dec v__7 13 12 in + let _mappingpatterns_26_ : mword 1 := subrange_vec_dec v__7 14 14 in + andb (size_bits_backwards_matches _mappingpatterns_27_) + (if ((size_bits_backwards_matches _mappingpatterns_27_)) then + let size := size_bits_backwards _mappingpatterns_27_ in + andb (bool_bits_backwards_matches _mappingpatterns_26_) + (if ((bool_bits_backwards_matches _mappingpatterns_26_)) then + let is_unsigned := bool_bits_backwards _mappingpatterns_26_ in + orb (neq_vec (size_bits_forwards size) (vec_of_bits [B1;B1] : mword 2)) + (negb is_unsigned) + else false) + else false)) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : mword (6 - 0 + 1))))) then + let imm : mword 12 := subrange_vec_dec v__7 31 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let imm : mword 12 := subrange_vec_dec v__7 31 20 in + let _mappingpatterns_27_ : mword 2 := subrange_vec_dec v__7 13 12 in + let _mappingpatterns_26_ : mword 1 := subrange_vec_dec v__7 14 14 in + let size := size_bits_backwards _mappingpatterns_27_ in + let is_unsigned := bool_bits_backwards _mappingpatterns_26_ in + LOAD + ((imm, rs1, rd, is_unsigned, size, false, false)) + else if ((andb + (let _mappingpatterns_28_ : mword 2 := subrange_vec_dec v__7 13 12 in + andb (size_bits_backwards_matches _mappingpatterns_28_) + (if ((size_bits_backwards_matches _mappingpatterns_28_)) then + let size := size_bits_backwards _mappingpatterns_28_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__7 14 14) (vec_of_bits [B0] : mword (14 - 14 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let imm7 : bits 7 := subrange_vec_dec v__7 31 25 in + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let imm7 : bits 7 := subrange_vec_dec v__7 31 25 in + let imm5 : bits 5 := subrange_vec_dec v__7 11 7 in + let _mappingpatterns_28_ : mword 2 := subrange_vec_dec v__7 13 12 in + let size := size_bits_backwards _mappingpatterns_28_ in + STORE + ((concat_vec (imm7 : bits 7) (imm5 : bits 5), rs2, rs1, size, false, false)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 14 12) (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1))))) then + let imm : mword 12 := subrange_vec_dec v__7 31 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let imm : mword 12 := subrange_vec_dec v__7 31 20 in + ADDIW + ((imm, rs1, rd)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let shamt : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + SHIFTW + ((shamt, rs1, rd, RISCV_SLLI)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let shamt : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + SHIFTW + ((shamt, rs1, rd, RISCV_SRLI)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let shamt : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + SHIFTW + ((shamt, rs1, rd, RISCV_SRAI)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPEW + ((rs2, rs1, rd, RISCV_ADDW)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPEW + ((rs2, rs1, rd, RISCV_SUBW)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPEW + ((rs2, rs1, rd, RISCV_SLLW)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPEW + ((rs2, rs1, rd, RISCV_SRLW)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPEW + ((rs2, rs1, rd, RISCV_SRAW)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let shamt : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + SHIFTIWOP + ((shamt, rs1, rd, RISCV_SLLIW)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let shamt : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + SHIFTIWOP + ((shamt, rs1, rd, RISCV_SRLIW)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let shamt : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + SHIFTIWOP + ((shamt, rs1, rd, RISCV_SRAIW)) + else if ((andb + (let _mappingpatterns_29_ : bits 3 := subrange_vec_dec v__7 14 12 in + andb (encdec_mul_op_backwards_matches _mappingpatterns_29_) + (if ((encdec_mul_op_backwards_matches _mappingpatterns_29_)) then + let '(high, signed1, signed2) := encdec_mul_op_backwards _mappingpatterns_29_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let _mappingpatterns_29_ : bits 3 := subrange_vec_dec v__7 14 12 in + let '(high, signed1, signed2) := encdec_mul_op_backwards _mappingpatterns_29_ in + MUL + ((rs2, rs1, rd, high, signed1, signed2)) + else if ((andb + (let _mappingpatterns_30_ : mword 1 := subrange_vec_dec v__7 12 12 in + andb (bool_not_bits_backwards_matches _mappingpatterns_30_) + (if ((bool_not_bits_backwards_matches _mappingpatterns_30_)) then + let s := bool_not_bits_backwards _mappingpatterns_30_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 13) + (vec_of_bits [B1;B0] : mword (14 - 13 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let _mappingpatterns_30_ : mword 1 := subrange_vec_dec v__7 12 12 in + let s := bool_not_bits_backwards _mappingpatterns_30_ in + DIV + ((rs2, rs1, rd, s)) + else if ((andb + (let _mappingpatterns_31_ : mword 1 := subrange_vec_dec v__7 12 12 in + andb (bool_not_bits_backwards_matches _mappingpatterns_31_) + (if ((bool_not_bits_backwards_matches _mappingpatterns_31_)) then + let s := bool_not_bits_backwards _mappingpatterns_31_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 13) + (vec_of_bits [B1;B1] : mword (14 - 13 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let _mappingpatterns_31_ : mword 1 := subrange_vec_dec v__7 12 12 in + let s := bool_not_bits_backwards _mappingpatterns_31_ in + REM + ((rs2, rs1, rd, s)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + MULW + ((rs2, rs1, rd)) + else if ((andb + (let _mappingpatterns_32_ : mword 1 := subrange_vec_dec v__7 12 12 in + andb (bool_not_bits_backwards_matches _mappingpatterns_32_) + (if ((bool_not_bits_backwards_matches _mappingpatterns_32_)) then + let s := bool_not_bits_backwards _mappingpatterns_32_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 13) + (vec_of_bits [B1;B0] : mword (14 - 13 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1))))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let _mappingpatterns_32_ : mword 1 := subrange_vec_dec v__7 12 12 in + let s := bool_not_bits_backwards _mappingpatterns_32_ in + DIVW + ((rs2, rs1, rd, s)) + else if ((andb + (let _mappingpatterns_33_ : mword 1 := subrange_vec_dec v__7 12 12 in + andb (bool_not_bits_backwards_matches _mappingpatterns_33_) + (if ((bool_not_bits_backwards_matches _mappingpatterns_33_)) then + let s := bool_not_bits_backwards _mappingpatterns_33_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 13) + (vec_of_bits [B1;B1] : mword (14 - 13 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1))))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let _mappingpatterns_33_ : mword 1 := subrange_vec_dec v__7 12 12 in + let s := bool_not_bits_backwards _mappingpatterns_33_ in + REMW + ((rs2, rs1, rd, s)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 28) + (vec_of_bits [B0;B0;B0;B0] : mword (31 - 28 + 1))) + (eq_vec (subrange_vec_dec v__7 19 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] + : mword (19 - 0 + 1))))) then + let succ : mword 4 := subrange_vec_dec v__7 23 20 in + let pred : mword 4 := subrange_vec_dec v__7 27 24 in + FENCE + ((pred, succ)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 28) + (vec_of_bits [B1;B0;B0;B0] : mword (31 - 28 + 1))) + (eq_vec (subrange_vec_dec v__7 19 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] + : mword (19 - 0 + 1))))) then + let succ : mword 4 := subrange_vec_dec v__7 23 20 in + let pred : mword 4 := subrange_vec_dec v__7 27 24 in + FENCE_TSO + ((pred, succ)) + else if ((eq_vec v__7 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0; + B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] + : mword 32))) then + FENCEI + (tt) + else if ((eq_vec v__7 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : mword 32))) then + ECALL + (tt) + else if ((eq_vec v__7 + (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : mword 32))) then + MRET + (tt) + else if ((eq_vec v__7 + (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : mword 32))) then + SRET + (tt) + else if ((eq_vec v__7 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : mword 32))) then + EBREAK + (tt) + else if ((eq_vec v__7 + (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : mword 32))) then + WFI + (tt) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : mword (31 - 25 + 1))) + (eq_vec (subrange_vec_dec v__7 14 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] : mword (14 - 0 + 1))))) + then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + SFENCE_VMA + ((rs1, rs2)) + else if sumbool_of_bool ((andb + (let _mappingpatterns_36_ : mword 2 := subrange_vec_dec v__7 13 12 in + let _mappingpatterns_35_ : mword 1 := subrange_vec_dec v__7 25 25 in + let _mappingpatterns_34_ : mword 1 := subrange_vec_dec v__7 26 26 in + andb (size_bits_backwards_matches _mappingpatterns_36_) + (if ((size_bits_backwards_matches _mappingpatterns_36_)) then + let size := size_bits_backwards _mappingpatterns_36_ in + andb (bool_bits_backwards_matches _mappingpatterns_35_) + (if ((bool_bits_backwards_matches _mappingpatterns_35_)) then + let rl := bool_bits_backwards _mappingpatterns_35_ in + andb (bool_bits_backwards_matches _mappingpatterns_34_) + (if ((bool_bits_backwards_matches _mappingpatterns_34_)) + then + let aq := bool_bits_backwards _mappingpatterns_34_ in + true + else false) + else false) + else false)) + (andb + (Z.eqb (projT1 (regbits_to_regno (subrange_vec_dec v__7 31 27))) + (projT1 (regbits_to_regno + (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)))) + (andb + (Z.eqb + (projT1 (regbits_to_regno (subrange_vec_dec v__7 24 20))) + (projT1 (regbits_to_regno + (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)))) + (andb + (eq_vec (subrange_vec_dec v__7 14 14) + (vec_of_bits [B0] : mword (14 - 14 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword (6 - 0 + 1)))))))) + then + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let _mappingpatterns_36_ : mword 2 := subrange_vec_dec v__7 13 12 in + let _mappingpatterns_35_ : mword 1 := subrange_vec_dec v__7 25 25 in + let _mappingpatterns_34_ : mword 1 := subrange_vec_dec v__7 26 26 in + let size := size_bits_backwards _mappingpatterns_36_ in + let rl := bool_bits_backwards _mappingpatterns_35_ in + let aq := bool_bits_backwards _mappingpatterns_34_ in + LOADRES + ((aq, rl, rs1, size, rd)) + else if sumbool_of_bool ((andb + (let _mappingpatterns_39_ : mword 2 := subrange_vec_dec v__7 13 12 in + let _mappingpatterns_38_ : mword 1 := subrange_vec_dec v__7 25 25 in + let _mappingpatterns_37_ : mword 1 := subrange_vec_dec v__7 26 26 in + andb (size_bits_backwards_matches _mappingpatterns_39_) + (if ((size_bits_backwards_matches _mappingpatterns_39_)) then + let size := size_bits_backwards _mappingpatterns_39_ in + andb (bool_bits_backwards_matches _mappingpatterns_38_) + (if ((bool_bits_backwards_matches _mappingpatterns_38_)) then + let rl := bool_bits_backwards _mappingpatterns_38_ in + andb (bool_bits_backwards_matches _mappingpatterns_37_) + (if ((bool_bits_backwards_matches _mappingpatterns_37_)) + then + let aq := bool_bits_backwards _mappingpatterns_37_ in + true + else false) + else false) + else false)) + (andb + (Z.eqb (projT1 (regbits_to_regno (subrange_vec_dec v__7 31 27))) + (projT1 (regbits_to_regno + (vec_of_bits [B0;B0;B0;B1;B1] : mword 5)))) + (andb + (eq_vec (subrange_vec_dec v__7 14 14) + (vec_of_bits [B0] : mword (14 - 14 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword (6 - 0 + 1))))))) + then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let _mappingpatterns_39_ : mword 2 := subrange_vec_dec v__7 13 12 in + let _mappingpatterns_38_ : mword 1 := subrange_vec_dec v__7 25 25 in + let _mappingpatterns_37_ : mword 1 := subrange_vec_dec v__7 26 26 in + let size := size_bits_backwards _mappingpatterns_39_ in + let rl := bool_bits_backwards _mappingpatterns_38_ in + let aq := bool_bits_backwards _mappingpatterns_37_ in + STORECON + ((aq, rl, rs2, rs1, size, rd)) + else if ((andb + (let _mappingpatterns_40_ : mword 5 := subrange_vec_dec v__7 31 27 in + let _mappingpatterns_43_ : mword 2 := subrange_vec_dec v__7 13 12 in + let _mappingpatterns_42_ : mword 1 := subrange_vec_dec v__7 25 25 in + let _mappingpatterns_41_ : mword 1 := subrange_vec_dec v__7 26 26 in + let _mappingpatterns_40_ : mword 5 := subrange_vec_dec v__7 31 27 in + andb (size_bits_backwards_matches _mappingpatterns_43_) + (if ((size_bits_backwards_matches _mappingpatterns_43_)) then + let size := size_bits_backwards _mappingpatterns_43_ in + andb (bool_bits_backwards_matches _mappingpatterns_42_) + (if ((bool_bits_backwards_matches _mappingpatterns_42_)) then + let rl := bool_bits_backwards _mappingpatterns_42_ in + andb (bool_bits_backwards_matches _mappingpatterns_41_) + (if ((bool_bits_backwards_matches _mappingpatterns_41_)) then + let aq := bool_bits_backwards _mappingpatterns_41_ in + andb (encdec_amoop_backwards_matches _mappingpatterns_40_) + (if ((encdec_amoop_backwards_matches _mappingpatterns_40_)) then + let op := encdec_amoop_backwards _mappingpatterns_40_ in + true + else false) + else false) + else false) + else false)) + (andb + (eq_vec (subrange_vec_dec v__7 14 14) (vec_of_bits [B0] : mword (14 - 14 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword (6 - 0 + 1)))))) then + let _mappingpatterns_40_ : mword 5 := subrange_vec_dec v__7 31 27 in + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let _mappingpatterns_43_ : mword 2 := subrange_vec_dec v__7 13 12 in + let _mappingpatterns_42_ : mword 1 := subrange_vec_dec v__7 25 25 in + let _mappingpatterns_41_ : mword 1 := subrange_vec_dec v__7 26 26 in + let _mappingpatterns_40_ : mword 5 := subrange_vec_dec v__7 31 27 in + let size := size_bits_backwards _mappingpatterns_43_ in + let rl := bool_bits_backwards _mappingpatterns_42_ in + let aq := bool_bits_backwards _mappingpatterns_41_ in + let op := encdec_amoop_backwards _mappingpatterns_40_ in + AMO + ((op, aq, rl, rs2, rs1, size, rd)) + else if ((andb + (let _mappingpatterns_45_ : mword 2 := subrange_vec_dec v__7 13 12 in + let _mappingpatterns_44_ : mword 1 := subrange_vec_dec v__7 14 14 in + andb (encdec_csrop_backwards_matches _mappingpatterns_45_) + (if ((encdec_csrop_backwards_matches _mappingpatterns_45_)) then + let op := encdec_csrop_backwards _mappingpatterns_45_ in + andb (bool_bits_backwards_matches _mappingpatterns_44_) + (if ((bool_bits_backwards_matches _mappingpatterns_44_)) then + let is_imm := bool_bits_backwards _mappingpatterns_44_ in + true + else false) + else false)) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))) then + let csr : mword 12 := subrange_vec_dec v__7 31 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let csr : mword 12 := subrange_vec_dec v__7 31 20 in + let _mappingpatterns_45_ : mword 2 := subrange_vec_dec v__7 13 12 in + let _mappingpatterns_44_ : mword 1 := subrange_vec_dec v__7 14 14 in + let op := encdec_csrop_backwards _mappingpatterns_45_ in + let is_imm := bool_bits_backwards _mappingpatterns_44_ in + CSR + ((csr, rs1, rd, is_imm, op)) + else if ((eq_vec v__7 + (vec_of_bits [B1;B1;B1;B1;B1;B0;B1;B0;B1;B1;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] + : mword 32))) then + STOP_FETCHING + (tt) + else if ((eq_vec v__7 + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] + : mword 32))) then + THREAD_START + (tt) + else ILLEGAL (v__7). + +Definition encdec_forwards_matches (arg_ : ast) +: bool := + + match arg_ with + | UTYPE (imm,rd,op) => true + | RISCV_JAL (v__227,rd) => + if ((eq_vec (subrange_vec_dec v__227 0 0) (vec_of_bits [B0] : mword (0 - 0 + 1)))) then true + else + let g__36 := RISCV_JAL ((v__227, rd)) in + false + | RISCV_JALR (imm,rs1,rd) => true + | BTYPE (v__229,rs2,rs1,op) => + if ((eq_vec (subrange_vec_dec v__229 0 0) (vec_of_bits [B0] : mword (0 - 0 + 1)))) then true + else + let g__36 := BTYPE ((v__229, rs2, rs1, op)) in + false + | ITYPE (imm,rs1,rd,op) => true + | SHIFTIOP (shamt,rs1,rd,RISCV_SLLI) => true + | SHIFTIOP (shamt,rs1,rd,RISCV_SRLI) => true + | SHIFTIOP (shamt,rs1,rd,RISCV_SRAI) => true + | RTYPE (rs2,rs1,rd,RISCV_ADD) => true + | RTYPE (rs2,rs1,rd,RISCV_SUB) => true + | RTYPE (rs2,rs1,rd,RISCV_SLL) => true + | RTYPE (rs2,rs1,rd,RISCV_SLT) => true + | RTYPE (rs2,rs1,rd,RISCV_SLTU) => true + | RTYPE (rs2,rs1,rd,RISCV_XOR) => true + | RTYPE (rs2,rs1,rd,RISCV_SRL) => true + | RTYPE (rs2,rs1,rd,RISCV_SRA) => true + | RTYPE (rs2,rs1,rd,RISCV_OR) => true + | RTYPE (rs2,rs1,rd,RISCV_AND) => true + | LOAD (imm,rs1,rd,is_unsigned,size,false,false) => + if ((orb (neq_vec (size_bits_forwards size) (vec_of_bits [B1;B1] : mword 2)) + (negb is_unsigned))) then + true + else + let g__36 := LOAD ((imm, rs1, rd, is_unsigned, size, false, false)) in + false + | STORE (v__231,rs2,rs1,size,false,false) => true + | ADDIW (imm,rs1,rd) => true + | SHIFTW (shamt,rs1,rd,RISCV_SLLI) => true + | SHIFTW (shamt,rs1,rd,RISCV_SRLI) => true + | SHIFTW (shamt,rs1,rd,RISCV_SRAI) => true + | RTYPEW (rs2,rs1,rd,RISCV_ADDW) => true + | RTYPEW (rs2,rs1,rd,RISCV_SUBW) => true + | RTYPEW (rs2,rs1,rd,RISCV_SLLW) => true + | RTYPEW (rs2,rs1,rd,RISCV_SRLW) => true + | RTYPEW (rs2,rs1,rd,RISCV_SRAW) => true + | SHIFTIWOP (shamt,rs1,rd,RISCV_SLLIW) => true + | SHIFTIWOP (shamt,rs1,rd,RISCV_SRLIW) => true + | SHIFTIWOP (shamt,rs1,rd,RISCV_SRAIW) => true + | MUL (rs2,rs1,rd,high,signed1,signed2) => true + | DIV (rs2,rs1,rd,s) => true + | REM (rs2,rs1,rd,s) => true + | MULW (rs2,rs1,rd) => true + | DIVW (rs2,rs1,rd,s) => true + | REMW (rs2,rs1,rd,s) => true + | FENCE (pred,succ) => true + | FENCE_TSO (pred,succ) => true + | FENCEI (tt) => true + | ECALL (tt) => true + | MRET (tt) => true + | SRET (tt) => true + | EBREAK (tt) => true + | WFI (tt) => true + | SFENCE_VMA (rs1,rs2) => true + | LOADRES (aq,rl,rs1,size,rd) => true + | STORECON (aq,rl,rs2,rs1,size,rd) => true + | AMO (op,aq,rl,rs2,rs1,size,rd) => true + | CSR (csr,rs1,rd,is_imm,op) => true + | STOP_FETCHING (tt) => true + | THREAD_START (tt) => true + | ILLEGAL (s) => true + | g__36 => false + end. + +Definition encdec_backwards_matches (arg_ : mword 32) +: bool := + + let v__232 := arg_ in + if ((let _mappingpatterns_0_ : mword 7 := subrange_vec_dec v__232 6 0 in + andb (encdec_uop_backwards_matches _mappingpatterns_0_) + (if ((encdec_uop_backwards_matches _mappingpatterns_0_)) then + let op := encdec_uop_backwards _mappingpatterns_0_ in + true + else false))) then + let _mappingpatterns_0_ : mword 7 := subrange_vec_dec v__232 6 0 in + let op := encdec_uop_backwards _mappingpatterns_0_ in + true + else if ((eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : mword (6 - 0 + 1)))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : mword (6 - 0 + 1))))) then + true + else if ((andb + (let _mappingpatterns_1_ : mword 3 := subrange_vec_dec v__232 14 12 in + andb (encdec_bop_backwards_matches _mappingpatterns_1_) + (if ((encdec_bop_backwards_matches _mappingpatterns_1_)) then + let op := encdec_bop_backwards _mappingpatterns_1_ in + true + else false)) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : mword (6 - 0 + 1))))) then + let _mappingpatterns_1_ : mword 3 := subrange_vec_dec v__232 14 12 in + let op := encdec_bop_backwards _mappingpatterns_1_ in + true + else if ((andb + (let _mappingpatterns_2_ : mword 3 := subrange_vec_dec v__232 14 12 in + andb (encdec_iop_backwards_matches _mappingpatterns_2_) + (if ((encdec_iop_backwards_matches _mappingpatterns_2_)) then + let op := encdec_iop_backwards _mappingpatterns_2_ in + true + else false)) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))) then + let _mappingpatterns_2_ : mword 3 := subrange_vec_dec v__232 14 12 in + let op := encdec_iop_backwards _mappingpatterns_2_ in + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 26) + (vec_of_bits [B0;B1;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B1;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B1;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B1;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B1;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (let _mappingpatterns_4_ : mword 2 := subrange_vec_dec v__232 13 12 in + let _mappingpatterns_3_ : mword 1 := subrange_vec_dec v__232 14 14 in + andb (size_bits_backwards_matches _mappingpatterns_4_) + (if ((size_bits_backwards_matches _mappingpatterns_4_)) then + let size := size_bits_backwards _mappingpatterns_4_ in + andb (bool_bits_backwards_matches _mappingpatterns_3_) + (if ((bool_bits_backwards_matches _mappingpatterns_3_)) then + let is_unsigned := bool_bits_backwards _mappingpatterns_3_ in + orb (neq_vec (size_bits_forwards size) (vec_of_bits [B1;B1] : mword 2)) + (negb is_unsigned) + else false) + else false)) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : mword (6 - 0 + 1))))) then + let _mappingpatterns_4_ : mword 2 := subrange_vec_dec v__232 13 12 in + let _mappingpatterns_3_ : mword 1 := subrange_vec_dec v__232 14 14 in + let size := size_bits_backwards _mappingpatterns_4_ in + let is_unsigned := bool_bits_backwards _mappingpatterns_3_ in + true + else if ((andb + (let _mappingpatterns_5_ : mword 2 := subrange_vec_dec v__232 13 12 in + andb (size_bits_backwards_matches _mappingpatterns_5_) + (if ((size_bits_backwards_matches _mappingpatterns_5_)) then + let size := size_bits_backwards _mappingpatterns_5_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__232 14 14) (vec_of_bits [B0] : mword (14 - 14 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let _mappingpatterns_5_ : mword 2 := subrange_vec_dec v__232 13 12 in + let size := size_bits_backwards _mappingpatterns_5_ in + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (let _mappingpatterns_6_ : bits 3 := subrange_vec_dec v__232 14 12 in + andb (encdec_mul_op_backwards_matches _mappingpatterns_6_) + (if ((encdec_mul_op_backwards_matches _mappingpatterns_6_)) then + let '(high, signed1, signed2) := encdec_mul_op_backwards _mappingpatterns_6_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let _mappingpatterns_6_ : bits 3 := subrange_vec_dec v__232 14 12 in + let '(high, signed1, signed2) := encdec_mul_op_backwards _mappingpatterns_6_ in + true + else if ((andb + (let _mappingpatterns_7_ : mword 1 := subrange_vec_dec v__232 12 12 in + andb (bool_not_bits_backwards_matches _mappingpatterns_7_) + (if ((bool_not_bits_backwards_matches _mappingpatterns_7_)) then + let s := bool_not_bits_backwards _mappingpatterns_7_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 13) + (vec_of_bits [B1;B0] : mword (14 - 13 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))) then + let _mappingpatterns_7_ : mword 1 := subrange_vec_dec v__232 12 12 in + let s := bool_not_bits_backwards _mappingpatterns_7_ in + true + else if ((andb + (let _mappingpatterns_8_ : mword 1 := subrange_vec_dec v__232 12 12 in + andb (bool_not_bits_backwards_matches _mappingpatterns_8_) + (if ((bool_not_bits_backwards_matches _mappingpatterns_8_)) then + let s := bool_not_bits_backwards _mappingpatterns_8_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 13) + (vec_of_bits [B1;B1] : mword (14 - 13 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))) then + let _mappingpatterns_8_ : mword 1 := subrange_vec_dec v__232 12 12 in + let s := bool_not_bits_backwards _mappingpatterns_8_ in + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (let _mappingpatterns_9_ : mword 1 := subrange_vec_dec v__232 12 12 in + andb (bool_not_bits_backwards_matches _mappingpatterns_9_) + (if ((bool_not_bits_backwards_matches _mappingpatterns_9_)) then + let s := bool_not_bits_backwards _mappingpatterns_9_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 13) + (vec_of_bits [B1;B0] : mword (14 - 13 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1))))))) then + let _mappingpatterns_9_ : mword 1 := subrange_vec_dec v__232 12 12 in + let s := bool_not_bits_backwards _mappingpatterns_9_ in + true + else if ((andb + (let _mappingpatterns_10_ : mword 1 := subrange_vec_dec v__232 12 12 in + andb (bool_not_bits_backwards_matches _mappingpatterns_10_) + (if ((bool_not_bits_backwards_matches _mappingpatterns_10_)) then + let s := bool_not_bits_backwards _mappingpatterns_10_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 13) + (vec_of_bits [B1;B1] : mword (14 - 13 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1))))))) then + let _mappingpatterns_10_ : mword 1 := subrange_vec_dec v__232 12 12 in + let s := bool_not_bits_backwards _mappingpatterns_10_ in + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 28) + (vec_of_bits [B0;B0;B0;B0] : mword (31 - 28 + 1))) + (eq_vec (subrange_vec_dec v__232 19 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] + : mword (19 - 0 + 1))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 28) + (vec_of_bits [B1;B0;B0;B0] : mword (31 - 28 + 1))) + (eq_vec (subrange_vec_dec v__232 19 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] + : mword (19 - 0 + 1))))) then + true + else if ((eq_vec v__232 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0; + B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] + : mword 32))) then + true + else if ((eq_vec v__232 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : mword 32))) then + true + else if ((eq_vec v__232 + (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : mword 32))) then + true + else if ((eq_vec v__232 + (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : mword 32))) then + true + else if ((eq_vec v__232 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : mword 32))) then + true + else if ((eq_vec v__232 + (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : mword 32))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : mword (31 - 25 + 1))) + (eq_vec (subrange_vec_dec v__232 14 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] : mword (14 - 0 + 1))))) + then + true + else if sumbool_of_bool ((andb + (let _mappingpatterns_13_ : mword 2 := subrange_vec_dec v__232 13 12 in + let _mappingpatterns_12_ : mword 1 := subrange_vec_dec v__232 25 25 in + let _mappingpatterns_11_ : mword 1 := subrange_vec_dec v__232 26 26 in + andb (size_bits_backwards_matches _mappingpatterns_13_) + (if ((size_bits_backwards_matches _mappingpatterns_13_)) then + let size := size_bits_backwards _mappingpatterns_13_ in + andb (bool_bits_backwards_matches _mappingpatterns_12_) + (if ((bool_bits_backwards_matches _mappingpatterns_12_)) then + let rl := bool_bits_backwards _mappingpatterns_12_ in + andb (bool_bits_backwards_matches _mappingpatterns_11_) + (if ((bool_bits_backwards_matches _mappingpatterns_11_)) + then + let aq := bool_bits_backwards _mappingpatterns_11_ in + true + else false) + else false) + else false)) + (andb + (Z.eqb (projT1 (regbits_to_regno (subrange_vec_dec v__232 31 27))) + (projT1 (regbits_to_regno + (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)))) + (andb + (Z.eqb + (projT1 (regbits_to_regno (subrange_vec_dec v__232 24 20))) + (projT1 (regbits_to_regno + (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)))) + (andb + (eq_vec (subrange_vec_dec v__232 14 14) + (vec_of_bits [B0] : mword (14 - 14 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword (6 - 0 + 1)))))))) + then + let _mappingpatterns_13_ : mword 2 := subrange_vec_dec v__232 13 12 in + let _mappingpatterns_12_ : mword 1 := subrange_vec_dec v__232 25 25 in + let _mappingpatterns_11_ : mword 1 := subrange_vec_dec v__232 26 26 in + let size := size_bits_backwards _mappingpatterns_13_ in + let rl := bool_bits_backwards _mappingpatterns_12_ in + let aq := bool_bits_backwards _mappingpatterns_11_ in + true + else if sumbool_of_bool ((andb + (let _mappingpatterns_16_ : mword 2 := subrange_vec_dec v__232 13 12 in + let _mappingpatterns_15_ : mword 1 := subrange_vec_dec v__232 25 25 in + let _mappingpatterns_14_ : mword 1 := subrange_vec_dec v__232 26 26 in + andb (size_bits_backwards_matches _mappingpatterns_16_) + (if ((size_bits_backwards_matches _mappingpatterns_16_)) then + let size := size_bits_backwards _mappingpatterns_16_ in + andb (bool_bits_backwards_matches _mappingpatterns_15_) + (if ((bool_bits_backwards_matches _mappingpatterns_15_)) then + let rl := bool_bits_backwards _mappingpatterns_15_ in + andb (bool_bits_backwards_matches _mappingpatterns_14_) + (if ((bool_bits_backwards_matches _mappingpatterns_14_)) + then + let aq := bool_bits_backwards _mappingpatterns_14_ in + true + else false) + else false) + else false)) + (andb + (Z.eqb (projT1 (regbits_to_regno (subrange_vec_dec v__232 31 27))) + (projT1 (regbits_to_regno + (vec_of_bits [B0;B0;B0;B1;B1] : mword 5)))) + (andb + (eq_vec (subrange_vec_dec v__232 14 14) + (vec_of_bits [B0] : mword (14 - 14 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword (6 - 0 + 1))))))) + then + let _mappingpatterns_16_ : mword 2 := subrange_vec_dec v__232 13 12 in + let _mappingpatterns_15_ : mword 1 := subrange_vec_dec v__232 25 25 in + let _mappingpatterns_14_ : mword 1 := subrange_vec_dec v__232 26 26 in + let size := size_bits_backwards _mappingpatterns_16_ in + let rl := bool_bits_backwards _mappingpatterns_15_ in + let aq := bool_bits_backwards _mappingpatterns_14_ in + true + else if ((andb + (let _mappingpatterns_17_ : mword 5 := subrange_vec_dec v__232 31 27 in + let _mappingpatterns_20_ : mword 2 := subrange_vec_dec v__232 13 12 in + let _mappingpatterns_19_ : mword 1 := subrange_vec_dec v__232 25 25 in + let _mappingpatterns_18_ : mword 1 := subrange_vec_dec v__232 26 26 in + let _mappingpatterns_17_ : mword 5 := subrange_vec_dec v__232 31 27 in + andb (size_bits_backwards_matches _mappingpatterns_20_) + (if ((size_bits_backwards_matches _mappingpatterns_20_)) then + let size := size_bits_backwards _mappingpatterns_20_ in + andb (bool_bits_backwards_matches _mappingpatterns_19_) + (if ((bool_bits_backwards_matches _mappingpatterns_19_)) then + let rl := bool_bits_backwards _mappingpatterns_19_ in + andb (bool_bits_backwards_matches _mappingpatterns_18_) + (if ((bool_bits_backwards_matches _mappingpatterns_18_)) then + let aq := bool_bits_backwards _mappingpatterns_18_ in + andb (encdec_amoop_backwards_matches _mappingpatterns_17_) + (if ((encdec_amoop_backwards_matches _mappingpatterns_17_)) then + let op := encdec_amoop_backwards _mappingpatterns_17_ in + true + else false) + else false) + else false) + else false)) + (andb + (eq_vec (subrange_vec_dec v__232 14 14) (vec_of_bits [B0] : mword (14 - 14 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword (6 - 0 + 1)))))) then + let _mappingpatterns_17_ : mword 5 := subrange_vec_dec v__232 31 27 in + let _mappingpatterns_20_ : mword 2 := subrange_vec_dec v__232 13 12 in + let _mappingpatterns_19_ : mword 1 := subrange_vec_dec v__232 25 25 in + let _mappingpatterns_18_ : mword 1 := subrange_vec_dec v__232 26 26 in + let _mappingpatterns_17_ : mword 5 := subrange_vec_dec v__232 31 27 in + let size := size_bits_backwards _mappingpatterns_20_ in + let rl := bool_bits_backwards _mappingpatterns_19_ in + let aq := bool_bits_backwards _mappingpatterns_18_ in + let op := encdec_amoop_backwards _mappingpatterns_17_ in + true + else if ((andb + (let _mappingpatterns_22_ : mword 2 := subrange_vec_dec v__232 13 12 in + let _mappingpatterns_21_ : mword 1 := subrange_vec_dec v__232 14 14 in + andb (encdec_csrop_backwards_matches _mappingpatterns_22_) + (if ((encdec_csrop_backwards_matches _mappingpatterns_22_)) then + let op := encdec_csrop_backwards _mappingpatterns_22_ in + andb (bool_bits_backwards_matches _mappingpatterns_21_) + (if ((bool_bits_backwards_matches _mappingpatterns_21_)) then + let is_imm := bool_bits_backwards _mappingpatterns_21_ in + true + else false) + else false)) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))) then + let _mappingpatterns_22_ : mword 2 := subrange_vec_dec v__232 13 12 in + let _mappingpatterns_21_ : mword 1 := subrange_vec_dec v__232 14 14 in + let op := encdec_csrop_backwards _mappingpatterns_22_ in + let is_imm := bool_bits_backwards _mappingpatterns_21_ in + true + else if ((eq_vec v__232 + (vec_of_bits [B1;B1;B1;B1;B1;B0;B1;B0;B1;B1;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] + : mword 32))) then + true + else if ((eq_vec v__232 + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] + : mword 32))) then + true + else true. + +Definition encdec_compressed_forwards (arg_ : ast) +: M (mword 16) := + + (match arg_ with + | C_NOP (tt) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B0;B1] : mword 2))))) + : mword (3 + (1 + (5 + (5 + 2))))) + | C_ADDI4SPN (rd,v__452) => + let nz96 : bits 4 := subrange_vec_dec v__452 7 4 in + let nz96 : bits 4 := subrange_vec_dec v__452 7 4 in + let nz54 : bits 2 := subrange_vec_dec v__452 3 2 in + let nz3 : bits 1 := subrange_vec_dec v__452 1 1 in + let nz2 : bits 1 := subrange_vec_dec v__452 0 0 in + returnm ((concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (nz54 : bits 2) + (concat_vec (nz96 : bits 4) + (concat_vec (nz2 : bits 1) + (concat_vec (nz3 : bits 1) + (concat_vec (rd : cregbits) (vec_of_bits [B0;B0] : mword 2))))))) + : mword 16) + | C_LW (v__453,rs1,rd) => + let ui6 : bits 1 := subrange_vec_dec v__453 4 4 in + let ui6 : bits 1 := subrange_vec_dec v__453 4 4 in + let ui53 : bits 3 := subrange_vec_dec v__453 3 1 in + let ui2 : bits 1 := subrange_vec_dec v__453 0 0 in + returnm ((concat_vec (vec_of_bits [B0;B1;B0] : mword 3) + (concat_vec (ui53 : bits 3) + (concat_vec (rs1 : cregbits) + (concat_vec (ui2 : bits 1) + (concat_vec (ui6 : bits 1) + (concat_vec (rd : cregbits) (vec_of_bits [B0;B0] : mword 2))))))) + : mword 16) + | C_LD (v__454,rs1,rd) => + let ui76 : bits 2 := subrange_vec_dec v__454 4 3 in + let ui76 : bits 2 := subrange_vec_dec v__454 4 3 in + let ui53 : bits 3 := subrange_vec_dec v__454 2 0 in + returnm ((concat_vec (vec_of_bits [B0;B1;B1] : mword 3) + (concat_vec (ui53 : bits 3) + (concat_vec (rs1 : cregbits) + (concat_vec (ui76 : bits 2) + (concat_vec (rd : cregbits) (vec_of_bits [B0;B0] : mword 2)))))) + : mword 16) + | C_SW (v__455,rs1,rs2) => + let ui6 : bits 1 := subrange_vec_dec v__455 4 4 in + let ui6 : bits 1 := subrange_vec_dec v__455 4 4 in + let ui53 : bits 3 := subrange_vec_dec v__455 3 1 in + let ui2 : bits 1 := subrange_vec_dec v__455 0 0 in + returnm ((concat_vec (vec_of_bits [B1;B1;B0] : mword 3) + (concat_vec (ui53 : bits 3) + (concat_vec (rs1 : cregbits) + (concat_vec (ui2 : bits 1) + (concat_vec (ui6 : bits 1) + (concat_vec (rs2 : cregbits) (vec_of_bits [B0;B0] : mword 2))))))) + : mword 16) + | C_SD (v__456,rs1,rs2) => + let ui76 : bits 2 := subrange_vec_dec v__456 4 3 in + let ui76 : bits 2 := subrange_vec_dec v__456 4 3 in + let ui53 : bits 3 := subrange_vec_dec v__456 2 0 in + returnm ((concat_vec (vec_of_bits [B1;B1;B1] : mword 3) + (concat_vec (ui53 : bits 3) + (concat_vec (rs1 : bits 3) + (concat_vec (ui76 : bits 2) + (concat_vec (rs2 : bits 3) (vec_of_bits [B0;B0] : mword 2)))))) + : mword 16) + | C_ADDI (v__457,rsd) => + let nzi5 : bits 1 := subrange_vec_dec v__457 5 5 in + let nzi5 : bits 1 := subrange_vec_dec v__457 5 5 in + let nzi40 : bits 5 := subrange_vec_dec v__457 4 0 in + returnm ((concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (nzi5 : bits 1) + (concat_vec (rsd : regbits) + (concat_vec (nzi40 : bits 5) (vec_of_bits [B0;B1] : mword 2))))) + : mword 16) + | C_ADDIW (v__458,rsd) => + let imm5 : bits 1 := subrange_vec_dec v__458 5 5 in + let imm5 : bits 1 := subrange_vec_dec v__458 5 5 in + let imm40 : bits 5 := subrange_vec_dec v__458 4 0 in + returnm ((concat_vec (vec_of_bits [B0;B0;B1] : mword 3) + (concat_vec (imm5 : bits 1) + (concat_vec (rsd : regbits) + (concat_vec (imm40 : bits 5) (vec_of_bits [B0;B1] : mword 2))))) + : mword 16) + | C_LI (v__459,rd) => + let imm5 : bits 1 := subrange_vec_dec v__459 5 5 in + let imm5 : bits 1 := subrange_vec_dec v__459 5 5 in + let imm40 : bits 5 := subrange_vec_dec v__459 4 0 in + returnm ((concat_vec (vec_of_bits [B0;B1;B0] : mword 3) + (concat_vec (imm5 : bits 1) + (concat_vec (rd : regbits) + (concat_vec (imm40 : bits 5) (vec_of_bits [B0;B1] : mword 2))))) + : mword 16) + | C_ADDI16SP (v__460) => + let nzi9 : bits 1 := subrange_vec_dec v__460 5 5 in + let nzi9 : bits 1 := subrange_vec_dec v__460 5 5 in + let nzi87 : bits 2 := subrange_vec_dec v__460 4 3 in + let nzi6 : bits 1 := subrange_vec_dec v__460 2 2 in + let nzi5 : bits 1 := subrange_vec_dec v__460 1 1 in + let nzi4 : bits 1 := subrange_vec_dec v__460 0 0 in + returnm ((concat_vec (vec_of_bits [B0;B1;B1] : mword 3) + (concat_vec (nzi9 : bits 1) + (concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5) + (concat_vec (nzi4 : bits 1) + (concat_vec (nzi6 : bits 1) + (concat_vec (nzi87 : bits 2) + (concat_vec (nzi5 : bits 1) (vec_of_bits [B0;B1] : mword 2)))))))) + : mword 16) + | C_LUI (v__461,rd) => + let imm17 : bits 1 := subrange_vec_dec v__461 5 5 in + let imm17 : bits 1 := subrange_vec_dec v__461 5 5 in + let imm1612 : bits 5 := subrange_vec_dec v__461 4 0 in + returnm ((concat_vec (vec_of_bits [B0;B1;B1] : mword 3) + (concat_vec (imm17 : bits 1) + (concat_vec (rd : regbits) + (concat_vec (imm1612 : bits 5) (vec_of_bits [B0;B1] : mword 2))))) + : mword 16) + | C_SRLI (v__462,rsd) => + let nzui5 : bits 1 := subrange_vec_dec v__462 5 5 in + let nzui5 : bits 1 := subrange_vec_dec v__462 5 5 in + let nzui40 : bits 5 := subrange_vec_dec v__462 4 0 in + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (nzui5 : bits 1) + (concat_vec (vec_of_bits [B0;B0] : mword 2) + (concat_vec (rsd : cregbits) + (concat_vec (nzui40 : bits 5) (vec_of_bits [B0;B1] : mword 2)))))) + : mword 16) + | C_SRAI (v__463,rsd) => + let nzui5 : bits 1 := subrange_vec_dec v__463 5 5 in + let nzui5 : bits 1 := subrange_vec_dec v__463 5 5 in + let nzui40 : bits 5 := subrange_vec_dec v__463 4 0 in + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (nzui5 : bits 1) + (concat_vec (vec_of_bits [B0;B1] : mword 2) + (concat_vec (rsd : cregbits) + (concat_vec (nzui40 : bits 5) (vec_of_bits [B0;B1] : mword 2)))))) + : mword 16) + | C_ANDI (v__464,rsd) => + let i5 : bits 1 := subrange_vec_dec v__464 5 5 in + let i5 : bits 1 := subrange_vec_dec v__464 5 5 in + let i40 : bits 5 := subrange_vec_dec v__464 4 0 in + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (i5 : bits 1) + (concat_vec (vec_of_bits [B1;B0] : mword 2) + (concat_vec (rsd : cregbits) + (concat_vec (i40 : bits 5) (vec_of_bits [B0;B1] : mword 2)))))) + : mword 16) + | C_SUB (rsd,rs2) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B1;B1] : mword 2) + (concat_vec (rsd : cregbits) + (concat_vec (vec_of_bits [B0;B0] : mword 2) + (concat_vec (rs2 : cregbits) (vec_of_bits [B0;B1] : mword 2))))))) + : mword (3 + (1 + (2 + (3 + (2 + (3 + 2))))))) + | C_XOR (rsd,rs2) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B1;B1] : mword 2) + (concat_vec (rsd : cregbits) + (concat_vec (vec_of_bits [B0;B1] : mword 2) + (concat_vec (rs2 : cregbits) (vec_of_bits [B0;B1] : mword 2))))))) + : mword (3 + (1 + (2 + (3 + (2 + (3 + 2))))))) + | C_OR (rsd,rs2) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B1;B1] : mword 2) + (concat_vec (rsd : cregbits) + (concat_vec (vec_of_bits [B1;B0] : mword 2) + (concat_vec (rs2 : cregbits) (vec_of_bits [B0;B1] : mword 2))))))) + : mword (3 + (1 + (2 + (3 + (2 + (3 + 2))))))) + | C_AND (rsd,rs2) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B1;B1] : mword 2) + (concat_vec (rsd : cregbits) + (concat_vec (vec_of_bits [B1;B1] : mword 2) + (concat_vec (rs2 : cregbits) (vec_of_bits [B0;B1] : mword 2))))))) + : mword (3 + (1 + (2 + (3 + (2 + (3 + 2))))))) + | C_SUBW (rsd,rs2) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec (vec_of_bits [B1;B1] : mword 2) + (concat_vec (rsd : cregbits) + (concat_vec (vec_of_bits [B0;B0] : mword 2) + (concat_vec (rs2 : cregbits) (vec_of_bits [B0;B1] : mword 2))))))) + : mword (3 + (1 + (2 + (3 + (2 + (3 + 2))))))) + | C_ADDW (rsd,rs2) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec (vec_of_bits [B1;B1] : mword 2) + (concat_vec (rsd : cregbits) + (concat_vec (vec_of_bits [B0;B1] : mword 2) + (concat_vec (rs2 : cregbits) (vec_of_bits [B0;B1] : mword 2))))))) + : mword (3 + (1 + (2 + (3 + (2 + (3 + 2))))))) + | C_J (v__465) => + let i11 : bits 1 := subrange_vec_dec v__465 10 10 in + let i98 : bits 2 := subrange_vec_dec v__465 8 7 in + let i7 : bits 1 := subrange_vec_dec v__465 6 6 in + let i6 : bits 1 := subrange_vec_dec v__465 5 5 in + let i5 : bits 1 := subrange_vec_dec v__465 4 4 in + let i4 : bits 1 := subrange_vec_dec v__465 3 3 in + let i31 : bits 3 := subrange_vec_dec v__465 2 0 in + let i11 : bits 1 := subrange_vec_dec v__465 10 10 in + let i10 : bits 1 := subrange_vec_dec v__465 9 9 in + returnm ((concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (i11 : bits 1) + (concat_vec (i4 : bits 1) + (concat_vec (i98 : bits 2) + (concat_vec (i10 : bits 1) + (concat_vec (i6 : bits 1) + (concat_vec (i7 : bits 1) + (concat_vec (i31 : bits 3) + (concat_vec (i5 : bits 1) (vec_of_bits [B0;B1] : mword 2)))))))))) + : mword 16) + | C_BEQZ (v__466,rs) => + let i8 : bits 1 := subrange_vec_dec v__466 7 7 in + let i8 : bits 1 := subrange_vec_dec v__466 7 7 in + let i76 : bits 2 := subrange_vec_dec v__466 6 5 in + let i5 : bits 1 := subrange_vec_dec v__466 4 4 in + let i43 : bits 2 := subrange_vec_dec v__466 3 2 in + let i21 : bits 2 := subrange_vec_dec v__466 1 0 in + returnm ((concat_vec (vec_of_bits [B1;B1;B0] : mword 3) + (concat_vec (i8 : bits 1) + (concat_vec (i43 : bits 2) + (concat_vec (rs : cregbits) + (concat_vec (i76 : bits 2) + (concat_vec (i21 : bits 2) + (concat_vec (i5 : bits 1) (vec_of_bits [B0;B1] : mword 2)))))))) + : mword 16) + | C_BNEZ (v__467,rs) => + let i8 : bits 1 := subrange_vec_dec v__467 7 7 in + let i8 : bits 1 := subrange_vec_dec v__467 7 7 in + let i76 : bits 2 := subrange_vec_dec v__467 6 5 in + let i5 : bits 1 := subrange_vec_dec v__467 4 4 in + let i43 : bits 2 := subrange_vec_dec v__467 3 2 in + let i21 : bits 2 := subrange_vec_dec v__467 1 0 in + returnm ((concat_vec (vec_of_bits [B1;B1;B1] : mword 3) + (concat_vec (i8 : bits 1) + (concat_vec (i43 : bits 2) + (concat_vec (rs : cregbits) + (concat_vec (i76 : bits 2) + (concat_vec (i21 : bits 2) + (concat_vec (i5 : bits 1) (vec_of_bits [B0;B1] : mword 2)))))))) + : mword 16) + | C_SLLI (v__468,rsd) => + let nzui5 : bits 1 := subrange_vec_dec v__468 5 5 in + let nzui5 : bits 1 := subrange_vec_dec v__468 5 5 in + let nzui40 : bits 5 := subrange_vec_dec v__468 4 0 in + returnm ((concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (nzui5 : bits 1) + (concat_vec (rsd : regbits) + (concat_vec (nzui40 : bits 5) (vec_of_bits [B1;B0] : mword 2))))) + : mword 16) + | C_LWSP (v__469,rd) => + let ui76 : bits 2 := subrange_vec_dec v__469 5 4 in + let ui76 : bits 2 := subrange_vec_dec v__469 5 4 in + let ui5 : bits 1 := subrange_vec_dec v__469 3 3 in + let ui42 : bits 3 := subrange_vec_dec v__469 2 0 in + returnm ((concat_vec (vec_of_bits [B0;B1;B0] : mword 3) + (concat_vec (ui5 : bits 1) + (concat_vec (rd : regbits) + (concat_vec (ui42 : bits 3) + (concat_vec (ui76 : bits 2) (vec_of_bits [B1;B0] : mword 2)))))) + : mword 16) + | C_LDSP (v__470,rd) => + let ui86 : bits 3 := subrange_vec_dec v__470 5 3 in + let ui86 : bits 3 := subrange_vec_dec v__470 5 3 in + let ui5 : bits 1 := subrange_vec_dec v__470 2 2 in + let ui43 : bits 2 := subrange_vec_dec v__470 1 0 in + returnm ((concat_vec (vec_of_bits [B0;B1;B1] : mword 3) + (concat_vec (ui5 : bits 1) + (concat_vec (rd : regbits) + (concat_vec (ui43 : bits 2) + (concat_vec (ui86 : bits 3) (vec_of_bits [B1;B0] : mword 2)))))) + : mword 16) + | C_SWSP (v__471,rs2) => + let ui76 : bits 2 := subrange_vec_dec v__471 5 4 in + let ui76 : bits 2 := subrange_vec_dec v__471 5 4 in + let ui52 : bits 4 := subrange_vec_dec v__471 3 0 in + returnm ((concat_vec (vec_of_bits [B1;B1;B0] : mword 3) + (concat_vec (ui52 : bits 4) + (concat_vec (ui76 : bits 2) + (concat_vec (rs2 : regbits) (vec_of_bits [B1;B0] : mword 2))))) + : mword 16) + | C_SDSP (v__472,rs2) => + let ui86 : bits 3 := subrange_vec_dec v__472 5 3 in + let ui86 : bits 3 := subrange_vec_dec v__472 5 3 in + let ui53 : bits 3 := subrange_vec_dec v__472 2 0 in + returnm ((concat_vec (vec_of_bits [B1;B1;B1] : mword 3) + (concat_vec (ui53 : bits 3) + (concat_vec (ui86 : bits 3) + (concat_vec (rs2 : regbits) (vec_of_bits [B1;B0] : mword 2))))) + : mword 16) + | C_JR (rs1) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (rs1 : regbits) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B1;B0] : mword 2))))) + : mword (3 + (1 + (5 + (5 + 2))))) + | C_JALR (rs1) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec (rs1 : regbits) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B1;B0] : mword 2))))) + : mword (3 + (1 + (5 + (5 + 2))))) + | C_MV (rd,rs2) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (rd : regbits) + (concat_vec (rs2 : regbits) (vec_of_bits [B1;B0] : mword 2))))) + : mword (3 + (1 + (5 + (5 + 2))))) + | C_EBREAK (tt) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B1;B0] : mword 2))))) + : mword (3 + (1 + (5 + (5 + 2))))) + | C_ADD (rsd,rs2) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec (rsd : regbits) + (concat_vec (rs2 : regbits) (vec_of_bits [B1;B0] : mword 2))))) + : mword (3 + (1 + (5 + (5 + 2))))) + | C_ILLEGAL (s) => returnm (s : mword 16) + | _ => exit tt : M (mword 16) + end) + : M (mword 16). + +Definition encdec_compressed_backwards (arg_ : mword 16) +: ast := + + let v__473 := arg_ in + if ((eq_vec v__473 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 16))) + then + C_NOP + (tt) + else if ((andb + (let nz96 : bits 4 := subrange_vec_dec v__473 10 7 in + let nz54 : bits 2 := subrange_vec_dec v__473 12 11 in + let nz3 : bits 1 := subrange_vec_dec v__473 5 5 in + let nz2 : bits 1 := subrange_vec_dec v__473 6 6 in + neq_vec (concat_vec nz96 (concat_vec nz54 (concat_vec nz3 nz2))) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (4 + (2 + (1 + 1))))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))))) + then + let rd : cregbits := subrange_vec_dec v__473 4 2 in + let nz96 : bits 4 := subrange_vec_dec v__473 10 7 in + let nz54 : bits 2 := subrange_vec_dec v__473 12 11 in + let nz3 : bits 1 := subrange_vec_dec v__473 5 5 in + let nz2 : bits 1 := subrange_vec_dec v__473 6 6 in + C_ADDI4SPN + ((rd, concat_vec (nz96 : bits 4) + (concat_vec (nz54 : bits 2) (concat_vec (nz3 : bits 1) (nz2 : bits 1))))) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) + then + let ui6 : bits 1 := subrange_vec_dec v__473 5 5 in + let ui53 : bits 3 := subrange_vec_dec v__473 12 10 in + let ui2 : bits 1 := subrange_vec_dec v__473 6 6 in + let rs1 : cregbits := subrange_vec_dec v__473 9 7 in + let rd : cregbits := subrange_vec_dec v__473 4 2 in + C_LW + ((concat_vec (ui6 : bits 1) (concat_vec (ui53 : bits 3) (ui2 : bits 1)), rs1, rd)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) + then + let ui76 : bits 2 := subrange_vec_dec v__473 6 5 in + let ui53 : bits 3 := subrange_vec_dec v__473 12 10 in + let rs1 : cregbits := subrange_vec_dec v__473 9 7 in + let rd : cregbits := subrange_vec_dec v__473 4 2 in + C_LD + ((concat_vec (ui76 : bits 2) (ui53 : bits 3), rs1, rd)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) + then + let ui6 : bits 1 := subrange_vec_dec v__473 5 5 in + let ui53 : bits 3 := subrange_vec_dec v__473 12 10 in + let ui2 : bits 1 := subrange_vec_dec v__473 6 6 in + let rs2 : cregbits := subrange_vec_dec v__473 4 2 in + let rs1 : cregbits := subrange_vec_dec v__473 9 7 in + C_SW + ((concat_vec (ui6 : bits 1) (concat_vec (ui53 : bits 3) (ui2 : bits 1)), rs1, rs2)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) + then + let ui76 : bits 2 := subrange_vec_dec v__473 6 5 in + let ui53 : bits 3 := subrange_vec_dec v__473 12 10 in + let rs2 : bits 3 := subrange_vec_dec v__473 4 2 in + let rs1 : bits 3 := subrange_vec_dec v__473 9 7 in + C_SD + ((concat_vec (ui76 : bits 2) (ui53 : bits 3), rs1, rs2)) + else if ((andb + (let rsd : regbits := subrange_vec_dec v__473 11 7 in + let nzi5 : bits 1 := subrange_vec_dec v__473 12 12 in + let nzi40 : bits 5 := subrange_vec_dec v__473 6 2 in + andb + (neq_vec (concat_vec nzi5 nzi40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))) + (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg)))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rsd : regbits := subrange_vec_dec v__473 11 7 in + let nzi5 : bits 1 := subrange_vec_dec v__473 12 12 in + let nzi40 : bits 5 := subrange_vec_dec v__473 6 2 in + C_ADDI + ((concat_vec (nzi5 : bits 1) (nzi40 : bits 5), rsd)) + else if ((andb + (let rsd : regbits := subrange_vec_dec v__473 11 7 in + neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B0;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rsd : regbits := subrange_vec_dec v__473 11 7 in + let imm5 : bits 1 := subrange_vec_dec v__473 12 12 in + let imm40 : bits 5 := subrange_vec_dec v__473 6 2 in + C_ADDIW + ((concat_vec (imm5 : bits 1) (imm40 : bits 5), rsd)) + else if ((andb + (let rd : regbits := subrange_vec_dec v__473 11 7 in + neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rd : regbits := subrange_vec_dec v__473 11 7 in + let imm5 : bits 1 := subrange_vec_dec v__473 12 12 in + let imm40 : bits 5 := subrange_vec_dec v__473 6 2 in + C_LI + ((concat_vec (imm5 : bits 1) (imm40 : bits 5), rd)) + else if sumbool_of_bool ((andb + (let nzi9 : bits 1 := subrange_vec_dec v__473 12 12 in + let nzi87 : bits 2 := subrange_vec_dec v__473 4 3 in + let nzi6 : bits 1 := subrange_vec_dec v__473 5 5 in + let nzi5 : bits 1 := subrange_vec_dec v__473 2 2 in + let nzi4 : bits 1 := subrange_vec_dec v__473 6 6 in + neq_vec + (concat_vec nzi9 + (concat_vec nzi87 (concat_vec nzi6 (concat_vec nzi5 nzi4)))) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + (2 + (1 + (1 + 1)))))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1))) + (andb + (Z.eqb + (projT1 (regbits_to_regno (subrange_vec_dec v__473 11 7))) + (projT1 (regbits_to_regno + (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)))) + (eq_vec (subrange_vec_dec v__473 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then + let nzi9 : bits 1 := subrange_vec_dec v__473 12 12 in + let nzi87 : bits 2 := subrange_vec_dec v__473 4 3 in + let nzi6 : bits 1 := subrange_vec_dec v__473 5 5 in + let nzi5 : bits 1 := subrange_vec_dec v__473 2 2 in + let nzi4 : bits 1 := subrange_vec_dec v__473 6 6 in + C_ADDI16SP + (concat_vec (nzi9 : bits 1) + (concat_vec (nzi87 : bits 2) + (concat_vec (nzi6 : bits 1) (concat_vec (nzi5 : bits 1) (nzi4 : bits 1))))) + else if ((andb + (let rd : regbits := subrange_vec_dec v__473 11 7 in + let imm17 : bits 1 := subrange_vec_dec v__473 12 12 in + let imm1612 : bits 5 := subrange_vec_dec v__473 6 2 in + andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno sp))) + (neq_vec (concat_vec imm17 imm1612) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rd : regbits := subrange_vec_dec v__473 11 7 in + let imm17 : bits 1 := subrange_vec_dec v__473 12 12 in + let imm1612 : bits 5 := subrange_vec_dec v__473 6 2 in + C_LUI + ((concat_vec (imm17 : bits 1) (imm1612 : bits 5), rd)) + else if ((andb + (let nzui5 : bits 1 := subrange_vec_dec v__473 12 12 in + let nzui40 : bits 5 := subrange_vec_dec v__473 6 2 in + neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1))) + (andb + (eq_vec (subrange_vec_dec v__473 11 10) + (vec_of_bits [B0;B0] : mword (11 - 10 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then + let rsd : cregbits := subrange_vec_dec v__473 9 7 in + let nzui5 : bits 1 := subrange_vec_dec v__473 12 12 in + let nzui40 : bits 5 := subrange_vec_dec v__473 6 2 in + C_SRLI + ((concat_vec (nzui5 : bits 1) (nzui40 : bits 5), rsd)) + else if ((andb + (let nzui5 : bits 1 := subrange_vec_dec v__473 12 12 in + let nzui40 : bits 5 := subrange_vec_dec v__473 6 2 in + neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1))) + (andb + (eq_vec (subrange_vec_dec v__473 11 10) + (vec_of_bits [B0;B1] : mword (11 - 10 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then + let rsd : cregbits := subrange_vec_dec v__473 9 7 in + let nzui5 : bits 1 := subrange_vec_dec v__473 12 12 in + let nzui40 : bits 5 := subrange_vec_dec v__473 6 2 in + C_SRAI + ((concat_vec (nzui5 : bits 1) (nzui40 : bits 5), rsd)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1))) + (andb + (eq_vec (subrange_vec_dec v__473 11 10) + (vec_of_bits [B1;B0] : mword (11 - 10 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rsd : cregbits := subrange_vec_dec v__473 9 7 in + let i5 : bits 1 := subrange_vec_dec v__473 12 12 in + let i40 : bits 5 := subrange_vec_dec v__473 6 2 in + C_ANDI + ((concat_vec (i5 : bits 1) (i40 : bits 5), rsd)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 10) + (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__473 6 5) (vec_of_bits [B0;B0] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rsd : cregbits := subrange_vec_dec v__473 9 7 in + let rs2 : cregbits := subrange_vec_dec v__473 4 2 in + C_SUB + ((rsd, rs2)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 10) + (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__473 6 5) (vec_of_bits [B0;B1] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rsd : cregbits := subrange_vec_dec v__473 9 7 in + let rs2 : cregbits := subrange_vec_dec v__473 4 2 in + C_XOR + ((rsd, rs2)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 10) + (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__473 6 5) (vec_of_bits [B1;B0] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rsd : cregbits := subrange_vec_dec v__473 9 7 in + let rs2 : cregbits := subrange_vec_dec v__473 4 2 in + C_OR + ((rsd, rs2)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 10) + (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__473 6 5) (vec_of_bits [B1;B1] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rsd : cregbits := subrange_vec_dec v__473 9 7 in + let rs2 : cregbits := subrange_vec_dec v__473 4 2 in + C_AND + ((rsd, rs2)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 10) + (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__473 6 5) (vec_of_bits [B0;B0] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rsd : cregbits := subrange_vec_dec v__473 9 7 in + let rs2 : cregbits := subrange_vec_dec v__473 4 2 in + C_SUBW + ((rsd, rs2)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 10) + (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__473 6 5) (vec_of_bits [B0;B1] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rsd : cregbits := subrange_vec_dec v__473 9 7 in + let rs2 : cregbits := subrange_vec_dec v__473 4 2 in + C_ADDW + ((rsd, rs2)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B1;B0;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) + then + let i98 : bits 2 := subrange_vec_dec v__473 10 9 in + let i7 : bits 1 := subrange_vec_dec v__473 6 6 in + let i6 : bits 1 := subrange_vec_dec v__473 7 7 in + let i5 : bits 1 := subrange_vec_dec v__473 2 2 in + let i4 : bits 1 := subrange_vec_dec v__473 11 11 in + let i31 : bits 3 := subrange_vec_dec v__473 5 3 in + let i11 : bits 1 := subrange_vec_dec v__473 12 12 in + let i10 : bits 1 := subrange_vec_dec v__473 8 8 in + C_J + (concat_vec (i11 : bits 1) + (concat_vec (i10 : bits 1) + (concat_vec (i98 : bits 2) + (concat_vec (i7 : bits 1) + (concat_vec (i6 : bits 1) + (concat_vec (i5 : bits 1) (concat_vec (i4 : bits 1) (i31 : bits 3)))))))) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) + then + let rs : cregbits := subrange_vec_dec v__473 9 7 in + let i8 : bits 1 := subrange_vec_dec v__473 12 12 in + let i76 : bits 2 := subrange_vec_dec v__473 6 5 in + let i5 : bits 1 := subrange_vec_dec v__473 2 2 in + let i43 : bits 2 := subrange_vec_dec v__473 11 10 in + let i21 : bits 2 := subrange_vec_dec v__473 4 3 in + C_BEQZ + ((concat_vec (i8 : bits 1) + (concat_vec (i76 : bits 2) + (concat_vec (i5 : bits 1) (concat_vec (i43 : bits 2) (i21 : bits 2)))), rs)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) + then + let rs : cregbits := subrange_vec_dec v__473 9 7 in + let i8 : bits 1 := subrange_vec_dec v__473 12 12 in + let i76 : bits 2 := subrange_vec_dec v__473 6 5 in + let i5 : bits 1 := subrange_vec_dec v__473 2 2 in + let i43 : bits 2 := subrange_vec_dec v__473 11 10 in + let i21 : bits 2 := subrange_vec_dec v__473 4 3 in + C_BNEZ + ((concat_vec (i8 : bits 1) + (concat_vec (i76 : bits 2) + (concat_vec (i5 : bits 1) (concat_vec (i43 : bits 2) (i21 : bits 2)))), rs)) + else if ((andb + (let rsd : regbits := subrange_vec_dec v__473 11 7 in + let nzui5 : bits 1 := subrange_vec_dec v__473 12 12 in + let nzui40 : bits 5 := subrange_vec_dec v__473 6 2 in + andb + (neq_vec (concat_vec nzui5 nzui40) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))) + (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg)))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) + then + let rsd : regbits := subrange_vec_dec v__473 11 7 in + let nzui5 : bits 1 := subrange_vec_dec v__473 12 12 in + let nzui40 : bits 5 := subrange_vec_dec v__473 6 2 in + C_SLLI + ((concat_vec (nzui5 : bits 1) (nzui40 : bits 5), rsd)) + else if ((andb + (let rd : regbits := subrange_vec_dec v__473 11 7 in + neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) + then + let ui76 : bits 2 := subrange_vec_dec v__473 3 2 in + let ui5 : bits 1 := subrange_vec_dec v__473 12 12 in + let ui42 : bits 3 := subrange_vec_dec v__473 6 4 in + let rd : regbits := subrange_vec_dec v__473 11 7 in + C_LWSP + ((concat_vec (ui76 : bits 2) (concat_vec (ui5 : bits 1) (ui42 : bits 3)), rd)) + else if ((andb + (let rd : regbits := subrange_vec_dec v__473 11 7 in + neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) + then + let ui86 : bits 3 := subrange_vec_dec v__473 4 2 in + let ui5 : bits 1 := subrange_vec_dec v__473 12 12 in + let ui43 : bits 2 := subrange_vec_dec v__473 6 5 in + let rd : regbits := subrange_vec_dec v__473 11 7 in + C_LDSP + ((concat_vec (ui86 : bits 3) (concat_vec (ui5 : bits 1) (ui43 : bits 2)), rd)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) + then + let ui76 : bits 2 := subrange_vec_dec v__473 8 7 in + let ui52 : bits 4 := subrange_vec_dec v__473 12 9 in + let rs2 : regbits := subrange_vec_dec v__473 6 2 in + C_SWSP + ((concat_vec (ui76 : bits 2) (ui52 : bits 4), rs2)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) + then + let ui86 : bits 3 := subrange_vec_dec v__473 9 7 in + let ui53 : bits 3 := subrange_vec_dec v__473 12 10 in + let rs2 : regbits := subrange_vec_dec v__473 6 2 in + C_SDSP + ((concat_vec (ui86 : bits 3) (ui53 : bits 3), rs2)) + else if ((andb + (let rs1 : regbits := subrange_vec_dec v__473 11 7 in + neq_int (projT1 (regbits_to_regno rs1)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__473 15 12) + (vec_of_bits [B1;B0;B0;B0] : mword (15 - 12 + 1))) + (eq_vec (subrange_vec_dec v__473 6 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : mword (6 - 0 + 1)))))) then + let rs1 : regbits := subrange_vec_dec v__473 11 7 in + C_JR + (rs1) + else if ((andb + (let rs1 : regbits := subrange_vec_dec v__473 11 7 in + neq_int (projT1 (regbits_to_regno rs1)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__473 15 12) + (vec_of_bits [B1;B0;B0;B1] : mword (15 - 12 + 1))) + (eq_vec (subrange_vec_dec v__473 6 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : mword (6 - 0 + 1)))))) then + let rs1 : regbits := subrange_vec_dec v__473 11 7 in + C_JALR + (rs1) + else if ((andb + (let rs2 : regbits := subrange_vec_dec v__473 6 2 in + let rd : regbits := subrange_vec_dec v__473 11 7 in + andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (neq_int (projT1 (regbits_to_regno rs2)) (projT1 (regbits_to_regno zreg)))) + (andb + (eq_vec (subrange_vec_dec v__473 15 12) + (vec_of_bits [B1;B0;B0;B0] : mword (15 - 12 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) + then + let rs2 : regbits := subrange_vec_dec v__473 6 2 in + let rd : regbits := subrange_vec_dec v__473 11 7 in + C_MV + ((rd, rs2)) + else if ((eq_vec v__473 + (vec_of_bits [B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 16))) then + C_EBREAK + (tt) + else if ((andb + (let rsd : regbits := subrange_vec_dec v__473 11 7 in + let rs2 : regbits := subrange_vec_dec v__473 6 2 in + andb (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg))) + (neq_int (projT1 (regbits_to_regno rs2)) (projT1 (regbits_to_regno zreg)))) + (andb + (eq_vec (subrange_vec_dec v__473 15 12) + (vec_of_bits [B1;B0;B0;B1] : mword (15 - 12 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) + then + let rsd : regbits := subrange_vec_dec v__473 11 7 in + let rs2 : regbits := subrange_vec_dec v__473 6 2 in + C_ADD + ((rsd, rs2)) + else C_ILLEGAL (v__473). + +Definition encdec_compressed_forwards_matches (arg_ : ast) +: bool := + + match arg_ with + | C_NOP (tt) => true + | C_ADDI4SPN (rd,v__606) => + if ((let nz96 : bits 4 := subrange_vec_dec v__606 7 4 in + let nz96 : bits 4 := subrange_vec_dec v__606 7 4 in + let nz54 : bits 2 := subrange_vec_dec v__606 3 2 in + let nz3 : bits 1 := subrange_vec_dec v__606 1 1 in + let nz2 : bits 1 := subrange_vec_dec v__606 0 0 in + neq_vec (concat_vec nz96 (concat_vec nz54 (concat_vec nz3 nz2))) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (4 + (2 + (1 + 1)))))) then + true + else + let g__35 := C_ADDI4SPN ((rd, v__606)) in + false + | C_LW (v__607,rs1,rd) => true + | C_LD (v__608,rs1,rd) => true + | C_SW (v__609,rs1,rs2) => true + | C_SD (v__610,rs1,rs2) => true + | C_ADDI (v__611,rsd) => + if ((let nzi5 : bits 1 := subrange_vec_dec v__611 5 5 in + let nzi5 : bits 1 := subrange_vec_dec v__611 5 5 in + let nzi40 : bits 5 := subrange_vec_dec v__611 4 0 in + andb (neq_vec (concat_vec nzi5 nzi40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))) + (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg))))) then + true + else + let g__35 := C_ADDI ((v__611, rsd)) in + false + | C_ADDIW (v__612,rsd) => + if ((neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__35 := C_ADDIW ((v__612, rsd)) in + false + | C_LI (v__613,rd) => + if ((neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__35 := C_LI ((v__613, rd)) in + false + | C_ADDI16SP (v__614) => + if ((let nzi9 : bits 1 := subrange_vec_dec v__614 5 5 in + let nzi9 : bits 1 := subrange_vec_dec v__614 5 5 in + let nzi87 : bits 2 := subrange_vec_dec v__614 4 3 in + let nzi6 : bits 1 := subrange_vec_dec v__614 2 2 in + let nzi5 : bits 1 := subrange_vec_dec v__614 1 1 in + let nzi4 : bits 1 := subrange_vec_dec v__614 0 0 in + neq_vec (concat_vec nzi9 (concat_vec nzi87 (concat_vec nzi6 (concat_vec nzi5 nzi4)))) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + (2 + (1 + (1 + 1))))))) then + true + else + let g__35 := C_ADDI16SP (v__614) in + false + | C_LUI (v__615,rd) => + if ((let imm17 : bits 1 := subrange_vec_dec v__615 5 5 in + let imm17 : bits 1 := subrange_vec_dec v__615 5 5 in + let imm1612 : bits 5 := subrange_vec_dec v__615 4 0 in + andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno sp))) + (neq_vec (concat_vec imm17 imm1612) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))))) + then + true + else + let g__35 := C_LUI ((v__615, rd)) in + false + | C_SRLI (v__616,rsd) => + if ((let nzui5 : bits 1 := subrange_vec_dec v__616 5 5 in + let nzui5 : bits 1 := subrange_vec_dec v__616 5 5 in + let nzui40 : bits 5 := subrange_vec_dec v__616 4 0 in + neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))) then + true + else + let g__35 := C_SRLI ((v__616, rsd)) in + false + | C_SRAI (v__617,rsd) => + if ((let nzui5 : bits 1 := subrange_vec_dec v__617 5 5 in + let nzui5 : bits 1 := subrange_vec_dec v__617 5 5 in + let nzui40 : bits 5 := subrange_vec_dec v__617 4 0 in + neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))) then + true + else + let g__35 := C_SRAI ((v__617, rsd)) in + false + | C_ANDI (v__618,rsd) => true + | C_SUB (rsd,rs2) => true + | C_XOR (rsd,rs2) => true + | C_OR (rsd,rs2) => true + | C_AND (rsd,rs2) => true + | C_SUBW (rsd,rs2) => true + | C_ADDW (rsd,rs2) => true + | C_J (v__619) => true + | C_BEQZ (v__620,rs) => true + | C_BNEZ (v__621,rs) => true + | C_SLLI (v__622,rsd) => + if ((let nzui5 : bits 1 := subrange_vec_dec v__622 5 5 in + let nzui5 : bits 1 := subrange_vec_dec v__622 5 5 in + let nzui40 : bits 5 := subrange_vec_dec v__622 4 0 in + andb (neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))) + (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg))))) then + true + else + let g__35 := C_SLLI ((v__622, rsd)) in + false + | C_LWSP (v__623,rd) => + if ((neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__35 := C_LWSP ((v__623, rd)) in + false + | C_LDSP (v__624,rd) => + if ((neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__35 := C_LDSP ((v__624, rd)) in + false + | C_SWSP (v__625,rs2) => true + | C_SDSP (v__626,rs2) => true + | C_JR (rs1) => + if ((neq_int (projT1 (regbits_to_regno rs1)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__35 := C_JR (rs1) in + false + | C_JALR (rs1) => + if ((neq_int (projT1 (regbits_to_regno rs1)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__35 := C_JALR (rs1) in + false + | C_MV (rd,rs2) => + if ((andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (neq_int (projT1 (regbits_to_regno rs2)) (projT1 (regbits_to_regno zreg))))) then + true + else + let g__35 := C_MV ((rd, rs2)) in + false + | C_EBREAK (tt) => true + | C_ADD (rsd,rs2) => + if ((andb (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg))) + (neq_int (projT1 (regbits_to_regno rs2)) (projT1 (regbits_to_regno zreg))))) then + true + else + let g__35 := C_ADD ((rsd, rs2)) in + false + | C_ILLEGAL (s) => true + | g__35 => false + end. + +Definition encdec_compressed_backwards_matches (arg_ : mword 16) +: bool := + + let v__627 := arg_ in + if ((eq_vec v__627 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 16))) + then + true + else if ((andb + (let nz96 : bits 4 := subrange_vec_dec v__627 10 7 in + let nz54 : bits 2 := subrange_vec_dec v__627 12 11 in + let nz3 : bits 1 := subrange_vec_dec v__627 5 5 in + let nz2 : bits 1 := subrange_vec_dec v__627 6 6 in + neq_vec (concat_vec nz96 (concat_vec nz54 (concat_vec nz3 nz2))) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (4 + (2 + (1 + 1))))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) + then + true + else if ((andb + (let rsd : regbits := subrange_vec_dec v__627 11 7 in + let nzi5 : bits 1 := subrange_vec_dec v__627 12 12 in + let nzi40 : bits 5 := subrange_vec_dec v__627 6 2 in + andb + (neq_vec (concat_vec nzi5 nzi40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))) + (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg)))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (let rsd : regbits := subrange_vec_dec v__627 11 7 in + neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B0;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (let rd : regbits := subrange_vec_dec v__627 11 7 in + neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if sumbool_of_bool ((andb + (let nzi9 : bits 1 := subrange_vec_dec v__627 12 12 in + let nzi87 : bits 2 := subrange_vec_dec v__627 4 3 in + let nzi6 : bits 1 := subrange_vec_dec v__627 5 5 in + let nzi5 : bits 1 := subrange_vec_dec v__627 2 2 in + let nzi4 : bits 1 := subrange_vec_dec v__627 6 6 in + neq_vec + (concat_vec nzi9 + (concat_vec nzi87 (concat_vec nzi6 (concat_vec nzi5 nzi4)))) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + (2 + (1 + (1 + 1)))))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1))) + (andb + (Z.eqb + (projT1 (regbits_to_regno (subrange_vec_dec v__627 11 7))) + (projT1 (regbits_to_regno + (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)))) + (eq_vec (subrange_vec_dec v__627 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then + true + else if ((andb + (let rd : regbits := subrange_vec_dec v__627 11 7 in + let imm17 : bits 1 := subrange_vec_dec v__627 12 12 in + let imm1612 : bits 5 := subrange_vec_dec v__627 6 2 in + andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno sp))) + (neq_vec (concat_vec imm17 imm1612) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (let nzui5 : bits 1 := subrange_vec_dec v__627 12 12 in + let nzui40 : bits 5 := subrange_vec_dec v__627 6 2 in + neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1))) + (andb + (eq_vec (subrange_vec_dec v__627 11 10) + (vec_of_bits [B0;B0] : mword (11 - 10 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then + true + else if ((andb + (let nzui5 : bits 1 := subrange_vec_dec v__627 12 12 in + let nzui40 : bits 5 := subrange_vec_dec v__627 6 2 in + neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1))) + (andb + (eq_vec (subrange_vec_dec v__627 11 10) + (vec_of_bits [B0;B1] : mword (11 - 10 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1))) + (andb + (eq_vec (subrange_vec_dec v__627 11 10) + (vec_of_bits [B1;B0] : mword (11 - 10 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 10) + (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__627 6 5) (vec_of_bits [B0;B0] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 10) + (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__627 6 5) (vec_of_bits [B0;B1] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 10) + (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__627 6 5) (vec_of_bits [B1;B0] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 10) + (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__627 6 5) (vec_of_bits [B1;B1] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 10) + (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__627 6 5) (vec_of_bits [B0;B0] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 10) + (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__627 6 5) (vec_of_bits [B0;B1] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B1;B0;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) + then + true + else if ((andb + (let rsd : regbits := subrange_vec_dec v__627 11 7 in + let nzui5 : bits 1 := subrange_vec_dec v__627 12 12 in + let nzui40 : bits 5 := subrange_vec_dec v__627 6 2 in + andb + (neq_vec (concat_vec nzui5 nzui40) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))) + (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg)))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (let rd : regbits := subrange_vec_dec v__627 11 7 in + neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (let rd : regbits := subrange_vec_dec v__627 11 7 in + neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) + then + true + else if ((andb + (let rs1 : regbits := subrange_vec_dec v__627 11 7 in + neq_int (projT1 (regbits_to_regno rs1)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__627 15 12) + (vec_of_bits [B1;B0;B0;B0] : mword (15 - 12 + 1))) + (eq_vec (subrange_vec_dec v__627 6 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (let rs1 : regbits := subrange_vec_dec v__627 11 7 in + neq_int (projT1 (regbits_to_regno rs1)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__627 15 12) + (vec_of_bits [B1;B0;B0;B1] : mword (15 - 12 + 1))) + (eq_vec (subrange_vec_dec v__627 6 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (let rs2 : regbits := subrange_vec_dec v__627 6 2 in + let rd : regbits := subrange_vec_dec v__627 11 7 in + andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (neq_int (projT1 (regbits_to_regno rs2)) (projT1 (regbits_to_regno zreg)))) + (andb + (eq_vec (subrange_vec_dec v__627 15 12) + (vec_of_bits [B1;B0;B0;B0] : mword (15 - 12 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) + then + true + else if ((eq_vec v__627 + (vec_of_bits [B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 16))) then + true + else if ((andb + (let rsd : regbits := subrange_vec_dec v__627 11 7 in + let rs2 : regbits := subrange_vec_dec v__627 6 2 in + andb (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg))) + (neq_int (projT1 (regbits_to_regno rs2)) (projT1 (regbits_to_regno zreg)))) + (andb + (eq_vec (subrange_vec_dec v__627 15 12) + (vec_of_bits [B1;B0;B0;B1] : mword (15 - 12 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) + then + true + else true. + +Definition assembly_forwards (arg_ : ast) +: M (string) := + + (match arg_ with + | UTYPE (imm,rd,op) => + returnm ((string_append (utype_mnemonic_forwards op) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))) + : string) + | RISCV_JAL (imm,rd) => + returnm ((string_append "jal" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))) + : string) + | RISCV_JALR (imm,rs1,rd) => + returnm ((string_append "jalr" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))))) + : string) + | BTYPE (imm,rs2,rs1,op) => + returnm ((string_append (btype_mnemonic_forwards op) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))))) + : string) + | ITYPE (imm,rs1,rd,op) => + returnm ((string_append (itype_mnemonic_forwards op) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))))) + : string) + | SHIFTIOP (shamt,rs1,rd,op) => + returnm ((string_append (shiftiop_mnemonic_forwards op) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (decimal_string_of_bits shamt) "")))))) + : string) + | RTYPE (rs2,rs1,rd,op) => + returnm ((string_append (rtype_mnemonic_forwards op) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) ""))))))) + : string) + | LOAD (imm,rs1,rd,is_unsigned,size,aq,rl) => + returnm ((string_append "l" + (string_append (size_mnemonic_forwards size) + (string_append (maybe_u_forwards is_unsigned) + (string_append (maybe_aq_forwards aq) + (string_append (maybe_rl_forwards rl) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))))))))) + : string) + | STORE (imm,rs1,rd,size,aq,rl) => + returnm ((string_append "s" + (string_append (size_mnemonic_forwards size) + (string_append (maybe_aq_forwards aq) + (string_append (maybe_rl_forwards rl) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) "")))))))))) + : string) + | ADDIW (imm,rs1,rd) => + returnm ((string_append "addiw" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))))) + : string) + | SHIFTW (shamt,rs1,rd,op) => + returnm ((string_append (shiftw_mnemonic_forwards op) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits shamt) ""))))))) + : string) + | RTYPEW (rs2,rs1,rd,op) => + returnm ((string_append (rtypew_mnemonic_forwards op) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) ""))))))) + : string) + | SHIFTIWOP (shamt,rs1,rd,op) => + returnm ((string_append (shiftiwop_mnemonic_forwards op) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (decimal_string_of_bits shamt) "")))))) + : string) + | MUL (rs2,rs1,rd,high,signed1,signed2) => + (mul_mnemonic_forwards (high, signed1, signed2)) >>= fun w__0 : string => + returnm ((string_append w__0 + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) ""))))))) + : string) + | DIV (rs2,rs1,rd,s) => + returnm ((string_append "div" + (string_append (maybe_not_u_forwards s) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) "")))))))) + : string) + | REM (rs2,rs1,rd,s) => + returnm ((string_append "rem" + (string_append (maybe_not_u_forwards s) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) "")))))))) + : string) + | MULW (rs2,rs1,rd) => + returnm ((string_append "mulw" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) ""))))))) + : string) + | DIVW (rs2,rs1,rd,s) => + returnm ((string_append "div" + (string_append (maybe_not_u_forwards s) + (string_append "w" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) ""))))))))) + : string) + | REMW (rs2,rs1,rd,s) => + returnm ((string_append "rem" + (string_append (maybe_not_u_forwards s) + (string_append "w" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) ""))))))))) + : string) + | FENCE (pred,succ) => + returnm ((string_append "fence" + (string_append (spc_forwards tt) + (string_append (fence_bits_forwards pred) + (string_append (sep_forwards tt) + (string_append (fence_bits_forwards succ) ""))))) + : string) + | FENCE_TSO (pred,succ) => + returnm ((string_append "fence.tso" + (string_append (spc_forwards tt) + (string_append (fence_bits_forwards pred) + (string_append (sep_forwards tt) + (string_append (fence_bits_forwards succ) ""))))) + : string) + | FENCEI (tt) => returnm ("fence.i" : string) + | ECALL (tt) => returnm ("ecall" : string) + | MRET (tt) => returnm ("mret" : string) + | SRET (tt) => returnm ("sret" : string) + | EBREAK (tt) => returnm ("ebreak" : string) + | WFI (tt) => returnm ("wfi" : string) + | SFENCE_VMA (rs1,rs2) => + returnm ((string_append "sfence.vma" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) (string_append (reg_name_forwards rs2) ""))))) + : string) + | LOADRES (aq,rl,rs1,size,rd) => + returnm ((string_append "lr." + (string_append (size_mnemonic_forwards size) + (string_append (maybe_aq_forwards aq) + (string_append (maybe_rl_forwards rl) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) "")))))))) + : string) + | STORECON (aq,rl,rs2,rs1,size,rd) => + returnm ((string_append "sc." + (string_append (size_mnemonic_forwards size) + (string_append (maybe_aq_forwards aq) + (string_append (maybe_rl_forwards rl) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) "")))))))))) + : string) + | AMO (op,aq,rl,rs2,rs1,width,rd) => + returnm ((string_append (amo_mnemonic_forwards op) + (string_append "." + (string_append (size_mnemonic_forwards width) + (string_append (maybe_aq_forwards aq) + (string_append (maybe_rl_forwards rl) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) ""))))))))))) + : string) + | CSR (csr,rs1,rd,true,op) => + returnm ((string_append (csr_mnemonic_forwards op) + (string_append "i" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits rs1) + (string_append (sep_forwards tt) + (string_append (csr_name_map_forwards csr) "")))))))) + : string) + | CSR (csr,rs1,rd,false,op) => + returnm ((string_append (csr_mnemonic_forwards op) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (csr_name_map_forwards csr) ""))))))) + : string) + | C_NOP (tt) => returnm ("c.nop" : string) + | C_ADDI4SPN (rdc,nzimm) => + returnm ((string_append "c.addi4spn" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rdc) + (string_append (sep_forwards tt) + (string_append + (decimal_string_of_bits + (concat_vec (nzimm : mword 8) (vec_of_bits [B0;B0] : mword 2))) + ""))))) + : string) + | C_LW (uimm,rsc,rdc) => + returnm ((string_append "c.lw" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rdc) + (string_append (sep_forwards tt) + (string_append (creg_name_forwards rsc) + (string_append (sep_forwards tt) + (string_append + (decimal_string_of_bits + (concat_vec (uimm : mword 5) + (vec_of_bits [B0;B0] : mword 2))) ""))))))) + : string) + | C_LD (uimm,rsc,rdc) => + returnm ((string_append "c.ld" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rdc) + (string_append (sep_forwards tt) + (string_append (creg_name_forwards rsc) + (string_append (sep_forwards tt) + (string_append + (decimal_string_of_bits + (concat_vec (uimm : mword 5) + (vec_of_bits [B0;B0;B0] : mword 3))) ""))))))) + : string) + | C_SW (uimm,rsc1,rsc2) => + returnm ((string_append "c.sw" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsc1) + (string_append (sep_forwards tt) + (string_append (creg_name_forwards rsc2) + (string_append (sep_forwards tt) + (string_append + (decimal_string_of_bits + (concat_vec (uimm : mword 5) + (vec_of_bits [B0;B0] : mword 2))) ""))))))) + : string) + | C_SD (uimm,rsc1,rsc2) => + returnm ((string_append "c.sd" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsc1) + (string_append (sep_forwards tt) + (string_append (creg_name_forwards rsc2) + (string_append (sep_forwards tt) + (string_append + (decimal_string_of_bits + (concat_vec (uimm : mword 5) + (vec_of_bits [B0;B0;B0] : mword 3))) ""))))))) + : string) + | C_ADDI (nzi,rsd) => + returnm ((string_append "c.addi" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits nzi) ""))))) + : string) + | C_JAL (imm) => + returnm ((string_append "c.jal" + (string_append (spc_forwards tt) + (string_append + (decimal_string_of_bits + (concat_vec (imm : mword 11) (vec_of_bits [B0] : mword 1))) ""))) + : string) + | C_ADDIW (imm,rsd) => + returnm ((string_append "c.addiw" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))) + : string) + | C_LI (imm,rd) => + returnm ((string_append "c.li" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))) + : string) + | C_ADDI16SP (imm) => + returnm ((string_append "c.addi16sp" + (string_append (spc_forwards tt) (string_append (decimal_string_of_bits imm) ""))) + : string) + | C_LUI (imm,rd) => + returnm ((string_append "c.lui" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))) + : string) + | C_SRLI (shamt,rsd) => + returnm ((string_append "c.srli" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits shamt) ""))))) + : string) + | C_SRAI (shamt,rsd) => + returnm ((string_append "c.srai" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits shamt) ""))))) + : string) + | C_ANDI (imm,rsd) => + returnm ((string_append "c.andi" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))) + : string) + | C_SUB (rsd,rs2) => + returnm ((string_append "c.sub" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (creg_name_forwards rs2) ""))))) + : string) + | C_XOR (rsd,rs2) => + returnm ((string_append "c.xor" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (creg_name_forwards rs2) ""))))) + : string) + | C_OR (rsd,rs2) => + returnm ((string_append "c.or" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (creg_name_forwards rs2) ""))))) + : string) + | C_AND (rsd,rs2) => + returnm ((string_append "c.and" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (creg_name_forwards rs2) ""))))) + : string) + | C_SUBW (rsd,rs2) => + returnm ((string_append "c.subw" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (creg_name_forwards rs2) ""))))) + : string) + | C_ADDW (rsd,rs2) => + returnm ((string_append "c.addw" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (creg_name_forwards rs2) ""))))) + : string) + | C_J (imm) => + returnm ((string_append "c.j" + (string_append (spc_forwards tt) (string_append (decimal_string_of_bits imm) ""))) + : string) + | C_BEQZ (imm,rs) => + returnm ((string_append "c.beqz" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rs) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))) + : string) + | C_BNEZ (imm,rs) => + returnm ((string_append "c.bnez" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rs) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))) + : string) + | C_SLLI (shamt,rsd) => + returnm ((string_append "c.slli" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits shamt) ""))))) + : string) + | C_LWSP (uimm,rd) => + returnm ((string_append "c.lwsp" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits uimm) ""))))) + : string) + | C_LDSP (uimm,rd) => + returnm ((string_append "c.ldsp" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits uimm) ""))))) + : string) + | C_SWSP (uimm,rd) => + returnm ((string_append "c.swsp" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits uimm) ""))))) + : string) + | C_SDSP (uimm,rs2) => + returnm ((string_append "c.sdsp" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rs2) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits uimm) ""))))) + : string) + | C_JR (rs1) => + returnm ((string_append "c.jr" + (string_append (spc_forwards tt) (string_append (reg_name_forwards rs1) ""))) + : string) + | C_JALR (rs1) => + returnm ((string_append "c.jalr" + (string_append (spc_forwards tt) (string_append (reg_name_forwards rs1) ""))) + : string) + | C_MV (rd,rs2) => + returnm ((string_append "c.mv" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) (string_append (reg_name_forwards rs2) ""))))) + : string) + | C_EBREAK (tt) => returnm ("c.ebreak" : string) + | C_ADD (rsd,rs2) => + returnm ((string_append "c.add" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rsd) + (string_append (sep_forwards tt) (string_append (reg_name_forwards rs2) ""))))) + : string) + | STOP_FETCHING (tt) => returnm ("stop_fetching" : string) + | THREAD_START (tt) => returnm ("thread_start" : string) + | ILLEGAL (s) => + returnm ((string_append "illegal" + (string_append (spc_forwards tt) (string_append (decimal_string_of_bits s) ""))) + : string) + | C_ILLEGAL (s) => + returnm ((string_append "c.illegal" + (string_append (spc_forwards tt) (string_append (decimal_string_of_bits s) ""))) + : string) + end) + : M (string). + +Definition _s1661_ (_s1662_ : string) +: M (option (mword 16)) := + + let _s1663_ := _s1662_ in + (if ((string_startswith _s1663_ "c.illegal")) then + (match (string_drop _s1663_ (projT1 (string_length "c.illegal"))) with + | _s1664_ => + (spc_matches_prefix _s1664_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s1665_ _)) => + match (string_drop _s1664_ _s1665_) with + | _s1666_ => + match (hex_bits_16_matches_prefix _s1666_) with + | Some (s,(existT _ _s1667_ _)) => + let p0_ := string_drop _s1666_ _s1667_ in + if ((generic_eq p0_ "")) then Some (s) + else None + | _ => None + end + end + | _ => None + end) + : option (mword 16)) + end) + : M (option (mword 16)) + else returnm (None : option (mword 16))) + : M (option (mword 16)). + +Definition _s1653_ (_s1654_ : string) +: M (option (mword 32)) := + + let _s1655_ := _s1654_ in + (if ((string_startswith _s1655_ "illegal")) then + (match (string_drop _s1655_ (projT1 (string_length "illegal"))) with + | _s1656_ => + (spc_matches_prefix _s1656_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s1657_ _)) => + match (string_drop _s1656_ _s1657_) with + | _s1658_ => + match (hex_bits_32_matches_prefix _s1658_) with + | Some (s,(existT _ _s1659_ _)) => + let p0_ := string_drop _s1658_ _s1659_ in + if ((generic_eq p0_ "")) then Some (s) + else None + | _ => None + end + end + | _ => None + end) + : option (mword 32)) + end) + : M (option (mword 32)) + else returnm (None : option (mword 32))) + : M (option (mword 32)). + +Definition _s1641_ (_s1642_ : string) +: M (option ((mword 5 * mword 5))) := + + let _s1643_ := _s1642_ in + (if ((string_startswith _s1643_ "c.add")) then + (match (string_drop _s1643_ (projT1 (string_length "c.add"))) with + | _s1644_ => + (spc_matches_prefix _s1644_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1645_ _)) => + (match (string_drop _s1644_ _s1645_) with + | _s1646_ => + (reg_name_matches_prefix _s1646_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1647_ _)) => + (match (string_drop _s1646_ _s1647_) with + | _s1648_ => + (sep_matches_prefix _s1648_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1649_ _)) => + (match (string_drop _s1648_ _s1649_) with + | _s1650_ => + (reg_name_matches_prefix _s1650_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s1651_ _)) => + let p0_ := string_drop _s1650_ _s1651_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + else returnm (None : option ((mword 5 * mword 5)))) + : M (option ((mword 5 * mword 5))). + +Definition _s1629_ (_s1630_ : string) +: M (option ((mword 5 * mword 5))) := + + let _s1631_ := _s1630_ in + (if ((string_startswith _s1631_ "c.mv")) then + (match (string_drop _s1631_ (projT1 (string_length "c.mv"))) with + | _s1632_ => + (spc_matches_prefix _s1632_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1633_ _)) => + (match (string_drop _s1632_ _s1633_) with + | _s1634_ => + (reg_name_matches_prefix _s1634_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1635_ _)) => + (match (string_drop _s1634_ _s1635_) with + | _s1636_ => + (sep_matches_prefix _s1636_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1637_ _)) => + (match (string_drop _s1636_ _s1637_) with + | _s1638_ => + (reg_name_matches_prefix _s1638_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s1639_ _)) => + let p0_ := string_drop _s1638_ _s1639_ in + if ((generic_eq p0_ "")) then Some ((rd, rs2)) + else None + | _ => None + end) + : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + else returnm (None : option ((mword 5 * mword 5)))) + : M (option ((mword 5 * mword 5))). + +Definition _s1621_ (_s1622_ : string) +: M (option (mword 5)) := + + let _s1623_ := _s1622_ in + (if ((string_startswith _s1623_ "c.jalr")) then + (match (string_drop _s1623_ (projT1 (string_length "c.jalr"))) with + | _s1624_ => + (spc_matches_prefix _s1624_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1625_ _)) => + (match (string_drop _s1624_ _s1625_) with + | _s1626_ => + (reg_name_matches_prefix _s1626_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__1 with + | Some (rs1,(existT _ _s1627_ _)) => + let p0_ := string_drop _s1626_ _s1627_ in + if ((generic_eq p0_ "")) then Some (rs1) + else None + | _ => None + end) + : option (mword 5)) + end) + : M (option (mword 5)) + | _ => returnm (None : option (mword 5)) + end) + : M (option (mword 5)) + end) + : M (option (mword 5)) + else returnm (None : option (mword 5))) + : M (option (mword 5)). + +Definition _s1613_ (_s1614_ : string) +: M (option (mword 5)) := + + let _s1615_ := _s1614_ in + (if ((string_startswith _s1615_ "c.jr")) then + (match (string_drop _s1615_ (projT1 (string_length "c.jr"))) with + | _s1616_ => + (spc_matches_prefix _s1616_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1617_ _)) => + (match (string_drop _s1616_ _s1617_) with + | _s1618_ => + (reg_name_matches_prefix _s1618_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__1 with + | Some (rs1,(existT _ _s1619_ _)) => + let p0_ := string_drop _s1618_ _s1619_ in + if ((generic_eq p0_ "")) then Some (rs1) + else None + | _ => None + end) + : option (mword 5)) + end) + : M (option (mword 5)) + | _ => returnm (None : option (mword 5)) + end) + : M (option (mword 5)) + end) + : M (option (mword 5)) + else returnm (None : option (mword 5))) + : M (option (mword 5)). + +Definition _s1601_ (_s1602_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s1603_ := _s1602_ in + (if ((string_startswith _s1603_ "c.sdsp")) then + (match (string_drop _s1603_ (projT1 (string_length "c.sdsp"))) with + | _s1604_ => + (spc_matches_prefix _s1604_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1605_ _)) => + (match (string_drop _s1604_ _s1605_) with + | _s1606_ => + (reg_name_matches_prefix _s1606_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs2,(existT _ _s1607_ _)) => + (match (string_drop _s1606_ _s1607_) with + | _s1608_ => + (sep_matches_prefix _s1608_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1609_ _)) => + match (string_drop _s1608_ _s1609_) with + | _s1610_ => + match (hex_bits_6_matches_prefix _s1610_) with + | Some (uimm,(existT _ _s1611_ _)) => + let p0_ := string_drop _s1610_ _s1611_ in + if ((generic_eq p0_ "")) then Some ((rs2, uimm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s1589_ (_s1590_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s1591_ := _s1590_ in + (if ((string_startswith _s1591_ "c.swsp")) then + (match (string_drop _s1591_ (projT1 (string_length "c.swsp"))) with + | _s1592_ => + (spc_matches_prefix _s1592_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1593_ _)) => + (match (string_drop _s1592_ _s1593_) with + | _s1594_ => + (reg_name_matches_prefix _s1594_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1595_ _)) => + (match (string_drop _s1594_ _s1595_) with + | _s1596_ => + (sep_matches_prefix _s1596_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1597_ _)) => + match (string_drop _s1596_ _s1597_) with + | _s1598_ => + match (hex_bits_6_matches_prefix _s1598_) with + | Some (uimm,(existT _ _s1599_ _)) => + let p0_ := string_drop _s1598_ _s1599_ in + if ((generic_eq p0_ "")) then Some ((rd, uimm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s1577_ (_s1578_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s1579_ := _s1578_ in + (if ((string_startswith _s1579_ "c.ldsp")) then + (match (string_drop _s1579_ (projT1 (string_length "c.ldsp"))) with + | _s1580_ => + (spc_matches_prefix _s1580_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1581_ _)) => + (match (string_drop _s1580_ _s1581_) with + | _s1582_ => + (reg_name_matches_prefix _s1582_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1583_ _)) => + (match (string_drop _s1582_ _s1583_) with + | _s1584_ => + (sep_matches_prefix _s1584_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1585_ _)) => + match (string_drop _s1584_ _s1585_) with + | _s1586_ => + match (hex_bits_6_matches_prefix _s1586_) with + | Some (uimm,(existT _ _s1587_ _)) => + let p0_ := string_drop _s1586_ _s1587_ in + if ((generic_eq p0_ "")) then Some ((rd, uimm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s1565_ (_s1566_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s1567_ := _s1566_ in + (if ((string_startswith _s1567_ "c.lwsp")) then + (match (string_drop _s1567_ (projT1 (string_length "c.lwsp"))) with + | _s1568_ => + (spc_matches_prefix _s1568_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1569_ _)) => + (match (string_drop _s1568_ _s1569_) with + | _s1570_ => + (reg_name_matches_prefix _s1570_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1571_ _)) => + (match (string_drop _s1570_ _s1571_) with + | _s1572_ => + (sep_matches_prefix _s1572_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1573_ _)) => + match (string_drop _s1572_ _s1573_) with + | _s1574_ => + match (hex_bits_6_matches_prefix _s1574_) with + | Some (uimm,(existT _ _s1575_ _)) => + let p0_ := string_drop _s1574_ _s1575_ in + if ((generic_eq p0_ "")) then Some ((rd, uimm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s1553_ (_s1554_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s1555_ := _s1554_ in + (if ((string_startswith _s1555_ "c.slli")) then + (match (string_drop _s1555_ (projT1 (string_length "c.slli"))) with + | _s1556_ => + (spc_matches_prefix _s1556_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1557_ _)) => + (match (string_drop _s1556_ _s1557_) with + | _s1558_ => + (reg_name_matches_prefix _s1558_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1559_ _)) => + (match (string_drop _s1558_ _s1559_) with + | _s1560_ => + (sep_matches_prefix _s1560_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1561_ _)) => + match (string_drop _s1560_ _s1561_) with + | _s1562_ => + match (hex_bits_6_matches_prefix _s1562_) with + | Some (shamt,(existT _ _s1563_ _)) => + let p0_ := string_drop _s1562_ _s1563_ in + if ((generic_eq p0_ "")) then Some ((rsd, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s1541_ (_s1542_ : string) +: M (option ((mword 3 * mword 8))) := + + let _s1543_ := _s1542_ in + (if ((string_startswith _s1543_ "c.bnez")) then + (match (string_drop _s1543_ (projT1 (string_length "c.bnez"))) with + | _s1544_ => + (spc_matches_prefix _s1544_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1545_ _)) => + (match (string_drop _s1544_ _s1545_) with + | _s1546_ => + (creg_name_matches_prefix _s1546_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs,(existT _ _s1547_ _)) => + (match (string_drop _s1546_ _s1547_) with + | _s1548_ => + (sep_matches_prefix _s1548_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1549_ _)) => + match (string_drop _s1548_ _s1549_) with + | _s1550_ => + match (hex_bits_8_matches_prefix _s1550_) with + | Some (imm,(existT _ _s1551_ _)) => + let p0_ := string_drop _s1550_ _s1551_ in + if ((generic_eq p0_ "")) then Some ((rs, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + else returnm (None : option ((mword 3 * mword 8)))) + : M (option ((mword 3 * mword 8))). + +Definition _s1529_ (_s1530_ : string) +: M (option ((mword 3 * mword 8))) := + + let _s1531_ := _s1530_ in + (if ((string_startswith _s1531_ "c.beqz")) then + (match (string_drop _s1531_ (projT1 (string_length "c.beqz"))) with + | _s1532_ => + (spc_matches_prefix _s1532_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1533_ _)) => + (match (string_drop _s1532_ _s1533_) with + | _s1534_ => + (creg_name_matches_prefix _s1534_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs,(existT _ _s1535_ _)) => + (match (string_drop _s1534_ _s1535_) with + | _s1536_ => + (sep_matches_prefix _s1536_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1537_ _)) => + match (string_drop _s1536_ _s1537_) with + | _s1538_ => + match (hex_bits_8_matches_prefix _s1538_) with + | Some (imm,(existT _ _s1539_ _)) => + let p0_ := string_drop _s1538_ _s1539_ in + if ((generic_eq p0_ "")) then Some ((rs, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + else returnm (None : option ((mword 3 * mword 8)))) + : M (option ((mword 3 * mword 8))). + +Definition _s1521_ (_s1522_ : string) +: M (option (mword 11)) := + + let _s1523_ := _s1522_ in + (if ((string_startswith _s1523_ "c.j")) then + (match (string_drop _s1523_ (projT1 (string_length "c.j"))) with + | _s1524_ => + (spc_matches_prefix _s1524_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s1525_ _)) => + match (string_drop _s1524_ _s1525_) with + | _s1526_ => + match (hex_bits_11_matches_prefix _s1526_) with + | Some (imm,(existT _ _s1527_ _)) => + let p0_ := string_drop _s1526_ _s1527_ in + if ((generic_eq p0_ "")) then Some (imm) + else None + | _ => None + end + end + | _ => None + end) + : option (mword 11)) + end) + : M (option (mword 11)) + else returnm (None : option (mword 11))) + : M (option (mword 11)). + +Definition _s1509_ (_s1510_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s1511_ := _s1510_ in + (if ((string_startswith _s1511_ "c.addw")) then + (match (string_drop _s1511_ (projT1 (string_length "c.addw"))) with + | _s1512_ => + (spc_matches_prefix _s1512_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1513_ _)) => + (match (string_drop _s1512_ _s1513_) with + | _s1514_ => + (creg_name_matches_prefix _s1514_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1515_ _)) => + (match (string_drop _s1514_ _s1515_) with + | _s1516_ => + (sep_matches_prefix _s1516_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1517_ _)) => + (match (string_drop _s1516_ _s1517_) with + | _s1518_ => + (creg_name_matches_prefix _s1518_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s1519_ _)) => + let p0_ := string_drop _s1518_ _s1519_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s1497_ (_s1498_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s1499_ := _s1498_ in + (if ((string_startswith _s1499_ "c.subw")) then + (match (string_drop _s1499_ (projT1 (string_length "c.subw"))) with + | _s1500_ => + (spc_matches_prefix _s1500_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1501_ _)) => + (match (string_drop _s1500_ _s1501_) with + | _s1502_ => + (creg_name_matches_prefix _s1502_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1503_ _)) => + (match (string_drop _s1502_ _s1503_) with + | _s1504_ => + (sep_matches_prefix _s1504_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1505_ _)) => + (match (string_drop _s1504_ _s1505_) with + | _s1506_ => + (creg_name_matches_prefix _s1506_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s1507_ _)) => + let p0_ := string_drop _s1506_ _s1507_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s1485_ (_s1486_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s1487_ := _s1486_ in + (if ((string_startswith _s1487_ "c.and")) then + (match (string_drop _s1487_ (projT1 (string_length "c.and"))) with + | _s1488_ => + (spc_matches_prefix _s1488_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1489_ _)) => + (match (string_drop _s1488_ _s1489_) with + | _s1490_ => + (creg_name_matches_prefix _s1490_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1491_ _)) => + (match (string_drop _s1490_ _s1491_) with + | _s1492_ => + (sep_matches_prefix _s1492_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1493_ _)) => + (match (string_drop _s1492_ _s1493_) with + | _s1494_ => + (creg_name_matches_prefix _s1494_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s1495_ _)) => + let p0_ := string_drop _s1494_ _s1495_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s1473_ (_s1474_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s1475_ := _s1474_ in + (if ((string_startswith _s1475_ "c.or")) then + (match (string_drop _s1475_ (projT1 (string_length "c.or"))) with + | _s1476_ => + (spc_matches_prefix _s1476_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1477_ _)) => + (match (string_drop _s1476_ _s1477_) with + | _s1478_ => + (creg_name_matches_prefix _s1478_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1479_ _)) => + (match (string_drop _s1478_ _s1479_) with + | _s1480_ => + (sep_matches_prefix _s1480_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1481_ _)) => + (match (string_drop _s1480_ _s1481_) with + | _s1482_ => + (creg_name_matches_prefix _s1482_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s1483_ _)) => + let p0_ := string_drop _s1482_ _s1483_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s1461_ (_s1462_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s1463_ := _s1462_ in + (if ((string_startswith _s1463_ "c.xor")) then + (match (string_drop _s1463_ (projT1 (string_length "c.xor"))) with + | _s1464_ => + (spc_matches_prefix _s1464_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1465_ _)) => + (match (string_drop _s1464_ _s1465_) with + | _s1466_ => + (creg_name_matches_prefix _s1466_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1467_ _)) => + (match (string_drop _s1466_ _s1467_) with + | _s1468_ => + (sep_matches_prefix _s1468_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1469_ _)) => + (match (string_drop _s1468_ _s1469_) with + | _s1470_ => + (creg_name_matches_prefix _s1470_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s1471_ _)) => + let p0_ := string_drop _s1470_ _s1471_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s1449_ (_s1450_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s1451_ := _s1450_ in + (if ((string_startswith _s1451_ "c.sub")) then + (match (string_drop _s1451_ (projT1 (string_length "c.sub"))) with + | _s1452_ => + (spc_matches_prefix _s1452_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1453_ _)) => + (match (string_drop _s1452_ _s1453_) with + | _s1454_ => + (creg_name_matches_prefix _s1454_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1455_ _)) => + (match (string_drop _s1454_ _s1455_) with + | _s1456_ => + (sep_matches_prefix _s1456_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1457_ _)) => + (match (string_drop _s1456_ _s1457_) with + | _s1458_ => + (creg_name_matches_prefix _s1458_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s1459_ _)) => + let p0_ := string_drop _s1458_ _s1459_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s1437_ (_s1438_ : string) +: M (option ((mword 3 * mword 6))) := + + let _s1439_ := _s1438_ in + (if ((string_startswith _s1439_ "c.andi")) then + (match (string_drop _s1439_ (projT1 (string_length "c.andi"))) with + | _s1440_ => + (spc_matches_prefix _s1440_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1441_ _)) => + (match (string_drop _s1440_ _s1441_) with + | _s1442_ => + (creg_name_matches_prefix _s1442_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1443_ _)) => + (match (string_drop _s1442_ _s1443_) with + | _s1444_ => + (sep_matches_prefix _s1444_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1445_ _)) => + match (string_drop _s1444_ _s1445_) with + | _s1446_ => + match (hex_bits_6_matches_prefix _s1446_) with + | Some (imm,(existT _ _s1447_ _)) => + let p0_ := string_drop _s1446_ _s1447_ in + if ((generic_eq p0_ "")) then Some ((rsd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + else returnm (None : option ((mword 3 * mword 6)))) + : M (option ((mword 3 * mword 6))). + +Definition _s1425_ (_s1426_ : string) +: M (option ((mword 3 * mword 6))) := + + let _s1427_ := _s1426_ in + (if ((string_startswith _s1427_ "c.srai")) then + (match (string_drop _s1427_ (projT1 (string_length "c.srai"))) with + | _s1428_ => + (spc_matches_prefix _s1428_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1429_ _)) => + (match (string_drop _s1428_ _s1429_) with + | _s1430_ => + (creg_name_matches_prefix _s1430_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1431_ _)) => + (match (string_drop _s1430_ _s1431_) with + | _s1432_ => + (sep_matches_prefix _s1432_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1433_ _)) => + match (string_drop _s1432_ _s1433_) with + | _s1434_ => + match (hex_bits_6_matches_prefix _s1434_) with + | Some (shamt,(existT _ _s1435_ _)) => + let p0_ := string_drop _s1434_ _s1435_ in + if ((generic_eq p0_ "")) then Some ((rsd, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + else returnm (None : option ((mword 3 * mword 6)))) + : M (option ((mword 3 * mword 6))). + +Definition _s1413_ (_s1414_ : string) +: M (option ((mword 3 * mword 6))) := + + let _s1415_ := _s1414_ in + (if ((string_startswith _s1415_ "c.srli")) then + (match (string_drop _s1415_ (projT1 (string_length "c.srli"))) with + | _s1416_ => + (spc_matches_prefix _s1416_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1417_ _)) => + (match (string_drop _s1416_ _s1417_) with + | _s1418_ => + (creg_name_matches_prefix _s1418_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1419_ _)) => + (match (string_drop _s1418_ _s1419_) with + | _s1420_ => + (sep_matches_prefix _s1420_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1421_ _)) => + match (string_drop _s1420_ _s1421_) with + | _s1422_ => + match (hex_bits_6_matches_prefix _s1422_) with + | Some (shamt,(existT _ _s1423_ _)) => + let p0_ := string_drop _s1422_ _s1423_ in + if ((generic_eq p0_ "")) then Some ((rsd, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + else returnm (None : option ((mword 3 * mword 6)))) + : M (option ((mword 3 * mword 6))). + +Definition _s1401_ (_s1402_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s1403_ := _s1402_ in + (if ((string_startswith _s1403_ "c.lui")) then + (match (string_drop _s1403_ (projT1 (string_length "c.lui"))) with + | _s1404_ => + (spc_matches_prefix _s1404_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1405_ _)) => + (match (string_drop _s1404_ _s1405_) with + | _s1406_ => + (reg_name_matches_prefix _s1406_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1407_ _)) => + (match (string_drop _s1406_ _s1407_) with + | _s1408_ => + (sep_matches_prefix _s1408_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1409_ _)) => + match (string_drop _s1408_ _s1409_) with + | _s1410_ => + match (hex_bits_6_matches_prefix _s1410_) with + | Some (imm,(existT _ _s1411_ _)) => + let p0_ := string_drop _s1410_ _s1411_ in + if ((generic_eq p0_ "")) then Some ((rd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s1393_ (_s1394_ : string) +: M (option (mword 6)) := + + let _s1395_ := _s1394_ in + (if ((string_startswith _s1395_ "c.addi16sp")) then + (match (string_drop _s1395_ (projT1 (string_length "c.addi16sp"))) with + | _s1396_ => + (spc_matches_prefix _s1396_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s1397_ _)) => + match (string_drop _s1396_ _s1397_) with + | _s1398_ => + match (hex_bits_6_matches_prefix _s1398_) with + | Some (imm,(existT _ _s1399_ _)) => + let p0_ := string_drop _s1398_ _s1399_ in + if ((generic_eq p0_ "")) then Some (imm) + else None + | _ => None + end + end + | _ => None + end) + : option (mword 6)) + end) + : M (option (mword 6)) + else returnm (None : option (mword 6))) + : M (option (mword 6)). + +Definition _s1381_ (_s1382_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s1383_ := _s1382_ in + (if ((string_startswith _s1383_ "c.li")) then + (match (string_drop _s1383_ (projT1 (string_length "c.li"))) with + | _s1384_ => + (spc_matches_prefix _s1384_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1385_ _)) => + (match (string_drop _s1384_ _s1385_) with + | _s1386_ => + (reg_name_matches_prefix _s1386_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1387_ _)) => + (match (string_drop _s1386_ _s1387_) with + | _s1388_ => + (sep_matches_prefix _s1388_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1389_ _)) => + match (string_drop _s1388_ _s1389_) with + | _s1390_ => + match (hex_bits_6_matches_prefix _s1390_) with + | Some (imm,(existT _ _s1391_ _)) => + let p0_ := string_drop _s1390_ _s1391_ in + if ((generic_eq p0_ "")) then Some ((rd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s1369_ (_s1370_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s1371_ := _s1370_ in + (if ((string_startswith _s1371_ "c.addiw")) then + (match (string_drop _s1371_ (projT1 (string_length "c.addiw"))) with + | _s1372_ => + (spc_matches_prefix _s1372_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1373_ _)) => + (match (string_drop _s1372_ _s1373_) with + | _s1374_ => + (reg_name_matches_prefix _s1374_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1375_ _)) => + (match (string_drop _s1374_ _s1375_) with + | _s1376_ => + (sep_matches_prefix _s1376_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1377_ _)) => + match (string_drop _s1376_ _s1377_) with + | _s1378_ => + match (hex_bits_6_matches_prefix _s1378_) with + | Some (imm,(existT _ _s1379_ _)) => + let p0_ := string_drop _s1378_ _s1379_ in + if ((generic_eq p0_ "")) then Some ((rsd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s1361_ (_s1362_ : string) +: M (option (mword 11)) := + + let _s1363_ := _s1362_ in + (if ((string_startswith _s1363_ "c.jal")) then + (match (string_drop _s1363_ (projT1 (string_length "c.jal"))) with + | _s1364_ => + (spc_matches_prefix _s1364_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s1365_ _)) => + match (string_drop _s1364_ _s1365_) with + | _s1366_ => + match (hex_bits_12_matches_prefix _s1366_) with + | Some (v__760,(existT _ _s1367_ _)) => + if ((eq_vec (subrange_vec_dec v__760 0 0) + (vec_of_bits [B0] : mword (0 - 0 + 1)))) then + let imm : mword 11 := subrange_vec_dec v__760 11 1 in + let imm : mword 11 := subrange_vec_dec v__760 11 1 in + let p0_ := string_drop _s1366_ _s1367_ in + if ((generic_eq p0_ "")) then Some (imm) + else None + else + let g__34 := Some ((v__760, _s1367_)) in + None + | g__34 => None + end + end + | _ => None + end) + : option (mword 11)) + end) + : M (option (mword 11)) + else returnm (None : option (mword 11))) + : M (option (mword 11)). + +Definition _s1349_ (_s1350_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s1351_ := _s1350_ in + (if ((string_startswith _s1351_ "c.addi")) then + (match (string_drop _s1351_ (projT1 (string_length "c.addi"))) with + | _s1352_ => + (spc_matches_prefix _s1352_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1353_ _)) => + (match (string_drop _s1352_ _s1353_) with + | _s1354_ => + (reg_name_matches_prefix _s1354_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1355_ _)) => + (match (string_drop _s1354_ _s1355_) with + | _s1356_ => + (sep_matches_prefix _s1356_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1357_ _)) => + match (string_drop _s1356_ _s1357_) with + | _s1358_ => + match (hex_bits_6_matches_prefix _s1358_) with + | Some (nzi,(existT _ _s1359_ _)) => + let p0_ := string_drop _s1358_ _s1359_ in + if ((generic_eq p0_ "")) then Some ((rsd, nzi)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s1333_ (_s1334_ : string) +: M (option ((mword 3 * mword 3 * mword 5))) := + + let _s1335_ := _s1334_ in + (if ((string_startswith _s1335_ "c.sd")) then + (match (string_drop _s1335_ (projT1 (string_length "c.sd"))) with + | _s1336_ => + (spc_matches_prefix _s1336_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1337_ _)) => + (match (string_drop _s1336_ _s1337_) with + | _s1338_ => + (creg_name_matches_prefix _s1338_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsc1,(existT _ _s1339_ _)) => + (match (string_drop _s1338_ _s1339_) with + | _s1340_ => + (sep_matches_prefix _s1340_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1341_ _)) => + (match (string_drop _s1340_ _s1341_) with + | _s1342_ => + (creg_name_matches_prefix _s1342_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc2,(existT _ _s1343_ _)) => + (match (string_drop _s1342_ _s1343_) with + | _s1344_ => + (sep_matches_prefix _s1344_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s1345_ _)) => + match (string_drop _s1344_ _s1345_) with + | _s1346_ => + match (hex_bits_8_matches_prefix _s1346_) with + | Some (v__762,(existT _ _s1347_ _)) => + if ((eq_vec + (subrange_vec_dec v__762 2 0) + (vec_of_bits [B0;B0;B0] + : mword (2 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__762 7 3 in + let uimm : mword 5 := + subrange_vec_dec v__762 7 3 in + let p0_ := + string_drop _s1346_ _s1347_ in + if ((generic_eq p0_ "")) then + Some + ((rsc1, rsc2, uimm)) + else None + else + let g__33 := Some ((v__762, _s1347_)) in + None + | g__33 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + else returnm (None : option ((mword 3 * mword 3 * mword 5)))) + : M (option ((mword 3 * mword 3 * mword 5))). + +Definition _s1317_ (_s1318_ : string) +: M (option ((mword 3 * mword 3 * mword 5))) := + + let _s1319_ := _s1318_ in + (if ((string_startswith _s1319_ "c.sw")) then + (match (string_drop _s1319_ (projT1 (string_length "c.sw"))) with + | _s1320_ => + (spc_matches_prefix _s1320_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1321_ _)) => + (match (string_drop _s1320_ _s1321_) with + | _s1322_ => + (creg_name_matches_prefix _s1322_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsc1,(existT _ _s1323_ _)) => + (match (string_drop _s1322_ _s1323_) with + | _s1324_ => + (sep_matches_prefix _s1324_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1325_ _)) => + (match (string_drop _s1324_ _s1325_) with + | _s1326_ => + (creg_name_matches_prefix _s1326_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc2,(existT _ _s1327_ _)) => + (match (string_drop _s1326_ _s1327_) with + | _s1328_ => + (sep_matches_prefix _s1328_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s1329_ _)) => + match (string_drop _s1328_ _s1329_) with + | _s1330_ => + match (hex_bits_7_matches_prefix _s1330_) with + | Some (v__764,(existT _ _s1331_ _)) => + if ((eq_vec + (subrange_vec_dec v__764 1 0) + (vec_of_bits [B0;B0] + : mword (1 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__764 6 2 in + let uimm : mword 5 := + subrange_vec_dec v__764 6 2 in + let p0_ := + string_drop _s1330_ _s1331_ in + if ((generic_eq p0_ "")) then + Some + ((rsc1, rsc2, uimm)) + else None + else + let g__32 := Some ((v__764, _s1331_)) in + None + | g__32 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + else returnm (None : option ((mword 3 * mword 3 * mword 5)))) + : M (option ((mword 3 * mword 3 * mword 5))). + +Definition _s1301_ (_s1302_ : string) +: M (option ((mword 3 * mword 3 * mword 5))) := + + let _s1303_ := _s1302_ in + (if ((string_startswith _s1303_ "c.ld")) then + (match (string_drop _s1303_ (projT1 (string_length "c.ld"))) with + | _s1304_ => + (spc_matches_prefix _s1304_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1305_ _)) => + (match (string_drop _s1304_ _s1305_) with + | _s1306_ => + (creg_name_matches_prefix _s1306_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rdc,(existT _ _s1307_ _)) => + (match (string_drop _s1306_ _s1307_) with + | _s1308_ => + (sep_matches_prefix _s1308_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1309_ _)) => + (match (string_drop _s1308_ _s1309_) with + | _s1310_ => + (creg_name_matches_prefix _s1310_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc,(existT _ _s1311_ _)) => + (match (string_drop _s1310_ _s1311_) with + | _s1312_ => + (sep_matches_prefix _s1312_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s1313_ _)) => + match (string_drop _s1312_ _s1313_) with + | _s1314_ => + match (hex_bits_8_matches_prefix _s1314_) with + | Some (v__766,(existT _ _s1315_ _)) => + if ((eq_vec + (subrange_vec_dec v__766 2 0) + (vec_of_bits [B0;B0;B0] + : mword (2 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__766 7 3 in + let uimm : mword 5 := + subrange_vec_dec v__766 7 3 in + let p0_ := + string_drop _s1314_ _s1315_ in + if ((generic_eq p0_ "")) then + Some + ((rdc, rsc, uimm)) + else None + else + let g__31 := Some ((v__766, _s1315_)) in + None + | g__31 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + else returnm (None : option ((mword 3 * mword 3 * mword 5)))) + : M (option ((mword 3 * mword 3 * mword 5))). + +Definition _s1285_ (_s1286_ : string) +: M (option ((mword 3 * mword 3 * mword 5))) := + + let _s1287_ := _s1286_ in + (if ((string_startswith _s1287_ "c.lw")) then + (match (string_drop _s1287_ (projT1 (string_length "c.lw"))) with + | _s1288_ => + (spc_matches_prefix _s1288_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1289_ _)) => + (match (string_drop _s1288_ _s1289_) with + | _s1290_ => + (creg_name_matches_prefix _s1290_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rdc,(existT _ _s1291_ _)) => + (match (string_drop _s1290_ _s1291_) with + | _s1292_ => + (sep_matches_prefix _s1292_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1293_ _)) => + (match (string_drop _s1292_ _s1293_) with + | _s1294_ => + (creg_name_matches_prefix _s1294_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc,(existT _ _s1295_ _)) => + (match (string_drop _s1294_ _s1295_) with + | _s1296_ => + (sep_matches_prefix _s1296_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s1297_ _)) => + match (string_drop _s1296_ _s1297_) with + | _s1298_ => + match (hex_bits_7_matches_prefix _s1298_) with + | Some (v__768,(existT _ _s1299_ _)) => + if ((eq_vec + (subrange_vec_dec v__768 1 0) + (vec_of_bits [B0;B0] + : mword (1 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__768 6 2 in + let uimm : mword 5 := + subrange_vec_dec v__768 6 2 in + let p0_ := + string_drop _s1298_ _s1299_ in + if ((generic_eq p0_ "")) then + Some + ((rdc, rsc, uimm)) + else None + else + let g__30 := Some ((v__768, _s1299_)) in + None + | g__30 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + else returnm (None : option ((mword 3 * mword 3 * mword 5)))) + : M (option ((mword 3 * mword 3 * mword 5))). + +Definition _s1273_ (_s1274_ : string) +: M (option ((mword 3 * mword 8))) := + + let _s1275_ := _s1274_ in + (if ((string_startswith _s1275_ "c.addi4spn")) then + (match (string_drop _s1275_ (projT1 (string_length "c.addi4spn"))) with + | _s1276_ => + (spc_matches_prefix _s1276_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1277_ _)) => + (match (string_drop _s1276_ _s1277_) with + | _s1278_ => + (creg_name_matches_prefix _s1278_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rdc,(existT _ _s1279_ _)) => + (match (string_drop _s1278_ _s1279_) with + | _s1280_ => + (sep_matches_prefix _s1280_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1281_ _)) => + match (string_drop _s1280_ _s1281_) with + | _s1282_ => + match (hex_bits_10_matches_prefix _s1282_) with + | Some (v__770,(existT _ _s1283_ _)) => + if ((eq_vec (subrange_vec_dec v__770 1 0) + (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) + then + let nzimm : mword 8 := subrange_vec_dec v__770 9 2 in + let nzimm : mword 8 := subrange_vec_dec v__770 9 2 in + let p0_ := string_drop _s1282_ _s1283_ in + if ((generic_eq p0_ "")) then Some ((rdc, nzimm)) + else None + else + let g__29 := Some ((v__770, _s1283_)) in + None + | g__29 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + else returnm (None : option ((mword 3 * mword 8)))) + : M (option ((mword 3 * mword 8))). + +Definition _s1256_ (_s1257_ : string) +: M (option ((csrop * mword 5 * mword 5 * mword 12))) := + + (match _s1257_ with + | _s1258_ => + (csr_mnemonic_matches_prefix _s1258_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1259_ _)) => + (match (string_drop _s1258_ _s1259_) with + | _s1260_ => + (spc_matches_prefix _s1260_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1261_ _)) => + (match (string_drop _s1260_ _s1261_) with + | _s1262_ => + (reg_name_matches_prefix _s1262_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1263_ _)) => + (match (string_drop _s1262_ _s1263_) with + | _s1264_ => + (sep_matches_prefix _s1264_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1265_ _)) => + (match (string_drop _s1264_ _s1265_) with + | _s1266_ => + (reg_name_matches_prefix _s1266_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1267_ _)) => + (match (string_drop _s1266_ _s1267_) with + | _s1268_ => + (sep_matches_prefix _s1268_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1269_ _)) => + (match (string_drop _s1268_ _s1269_) with + | _s1270_ => + (csr_name_map_matches_prefix _s1270_) >>= fun w__6 : option ((mword 12 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (csr,(existT _ _s1271_ _)) => + let p0_ := + string_drop _s1270_ _s1271_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, csr)) + else None + | _ => None + end) + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))). + +Definition _s1238_ (_s1239_ : string) +: M (option ((csrop * mword 5 * mword 5 * mword 12))) := + + (match _s1239_ with + | _s1240_ => + (csr_mnemonic_matches_prefix _s1240_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1241_ _)) => + let _s1242_ := string_drop _s1240_ _s1241_ in + (if ((string_startswith _s1242_ "i")) then + (match (string_drop _s1242_ (projT1 (string_length "i"))) with + | _s1243_ => + (spc_matches_prefix _s1243_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1244_ _)) => + (match (string_drop _s1243_ _s1244_) with + | _s1245_ => + (reg_name_matches_prefix _s1245_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1246_ _)) => + (match (string_drop _s1245_ _s1246_) with + | _s1247_ => + (sep_matches_prefix _s1247_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1248_ _)) => + (match (string_drop _s1247_ _s1248_) with + | _s1249_ => + (match (hex_bits_5_matches_prefix _s1249_) with + | Some (rs1,(existT _ _s1250_ _)) => + (match (string_drop _s1249_ _s1250_) with + | _s1251_ => + (sep_matches_prefix _s1251_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s1252_ _)) => + (match (string_drop _s1251_ _s1252_) with + | _s1253_ => + (csr_name_map_matches_prefix _s1253_) >>= fun w__5 : option ((mword 12 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some + (csr,(existT _ _s1254_ _)) => + let p0_ := + string_drop _s1253_ _s1254_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, csr)) + else None + | _ => None + end) + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + else returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))). + +Definition _s1214_ (_s1215_ : string) +: M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) := + + (match _s1215_ with + | _s1216_ => + (amo_mnemonic_matches_prefix _s1216_) >>= fun w__0 : option ((amoop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1217_ _)) => + let _s1218_ := string_drop _s1216_ _s1217_ in + (if ((string_startswith _s1218_ ".")) then + (match (string_drop _s1218_ (projT1 (string_length "."))) with + | _s1219_ => + (size_mnemonic_matches_prefix _s1219_) >>= fun w__1 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (width,(existT _ _s1220_ _)) => + (match (string_drop _s1219_ _s1220_) with + | _s1221_ => + (maybe_aq_matches_prefix _s1221_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (aq,(existT _ _s1222_ _)) => + (match (string_drop _s1221_ _s1222_) with + | _s1223_ => + (maybe_rl_matches_prefix _s1223_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rl,(existT _ _s1224_ _)) => + (match (string_drop _s1223_ _s1224_) with + | _s1225_ => + (spc_matches_prefix _s1225_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s1226_ _)) => + (match (string_drop _s1225_ _s1226_) with + | _s1227_ => + (reg_name_matches_prefix _s1227_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (rd,(existT _ _s1228_ _)) => + (match (string_drop _s1227_ _s1228_) with + | _s1229_ => + (sep_matches_prefix _s1229_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (tt,(existT _ _s1230_ _)) => + (match (string_drop _s1229_ _s1230_) with + | _s1231_ => + (reg_name_matches_prefix _s1231_) >>= fun w__7 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__7 with + | Some (rs1,(existT _ _s1232_ _)) => + (match (string_drop _s1231_ + _s1232_) with + | _s1233_ => + (sep_matches_prefix + _s1233_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__8 with + | Some + (tt,(existT _ _s1234_ _)) => + (match (string_drop + _s1233_ + _s1234_) with + | _s1235_ => + (reg_name_matches_prefix + _s1235_) >>= fun w__9 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__9 with + | Some + (rs2,(existT _ _s1236_ _)) => + let p0_ := + string_drop + _s1235_ + _s1236_ in + if ((generic_eq + p0_ + "")) + then + Some + ((op, width, aq, rl, rd, rs1, rs2)) + else + None + | _ => + None + end) + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + else + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))). + +Definition _s1192_ (_s1193_ : string) +: M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) := + + let _s1194_ := _s1193_ in + (if ((string_startswith _s1194_ "sc.")) then + (match (string_drop _s1194_ (projT1 (string_length "sc."))) with + | _s1195_ => + (size_mnemonic_matches_prefix _s1195_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s1196_ _)) => + (match (string_drop _s1195_ _s1196_) with + | _s1197_ => + (maybe_aq_matches_prefix _s1197_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (aq,(existT _ _s1198_ _)) => + (match (string_drop _s1197_ _s1198_) with + | _s1199_ => + (maybe_rl_matches_prefix _s1199_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rl,(existT _ _s1200_ _)) => + (match (string_drop _s1199_ _s1200_) with + | _s1201_ => + (spc_matches_prefix _s1201_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1202_ _)) => + (match (string_drop _s1201_ _s1202_) with + | _s1203_ => + (reg_name_matches_prefix _s1203_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rd,(existT _ _s1204_ _)) => + (match (string_drop _s1203_ _s1204_) with + | _s1205_ => + (sep_matches_prefix _s1205_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1206_ _)) => + (match (string_drop _s1205_ _s1206_) with + | _s1207_ => + (reg_name_matches_prefix _s1207_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (rs1,(existT _ _s1208_ _)) => + (match (string_drop _s1207_ _s1208_) with + | _s1209_ => + (sep_matches_prefix _s1209_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__7 with + | Some (tt,(existT _ _s1210_ _)) => + (match (string_drop _s1209_ + _s1210_) with + | _s1211_ => + (reg_name_matches_prefix + _s1211_) >>= fun w__8 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__8 with + | Some + (rs2,(existT _ _s1212_ _)) => + let p0_ := + string_drop + _s1211_ + _s1212_ in + if ((generic_eq + p0_ "")) + then + Some + ((size, aq, rl, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))). + +Definition _s1174_ (_s1175_ : string) +: M (option ((word_width * bool * bool * mword 5 * mword 5))) := + + let _s1176_ := _s1175_ in + (if ((string_startswith _s1176_ "lr.")) then + (match (string_drop _s1176_ (projT1 (string_length "lr."))) with + | _s1177_ => + (size_mnemonic_matches_prefix _s1177_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s1178_ _)) => + (match (string_drop _s1177_ _s1178_) with + | _s1179_ => + (maybe_aq_matches_prefix _s1179_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (aq,(existT _ _s1180_ _)) => + (match (string_drop _s1179_ _s1180_) with + | _s1181_ => + (maybe_rl_matches_prefix _s1181_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rl,(existT _ _s1182_ _)) => + (match (string_drop _s1181_ _s1182_) with + | _s1183_ => + (spc_matches_prefix _s1183_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1184_ _)) => + (match (string_drop _s1183_ _s1184_) with + | _s1185_ => + (reg_name_matches_prefix _s1185_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rd,(existT _ _s1186_ _)) => + (match (string_drop _s1185_ _s1186_) with + | _s1187_ => + (sep_matches_prefix _s1187_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1188_ _)) => + (match (string_drop _s1187_ _s1188_) with + | _s1189_ => + (reg_name_matches_prefix _s1189_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs1,(existT _ _s1190_ _)) => + let p0_ := + string_drop _s1189_ _s1190_ in + if ((generic_eq p0_ "")) then + Some + ((size, aq, rl, rd, rs1)) + else None + | _ => None + end) + : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => returnm (None : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => returnm (None : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5)))) + : M (option ((word_width * bool * bool * mword 5 * mword 5))). + +Definition _s1162_ (_s1163_ : string) +: M (option ((mword 5 * mword 5))) := + + let _s1164_ := _s1163_ in + (if ((string_startswith _s1164_ "sfence.vma")) then + (match (string_drop _s1164_ (projT1 (string_length "sfence.vma"))) with + | _s1165_ => + (spc_matches_prefix _s1165_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1166_ _)) => + (match (string_drop _s1165_ _s1166_) with + | _s1167_ => + (reg_name_matches_prefix _s1167_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs1,(existT _ _s1168_ _)) => + (match (string_drop _s1167_ _s1168_) with + | _s1169_ => + (sep_matches_prefix _s1169_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1170_ _)) => + (match (string_drop _s1169_ _s1170_) with + | _s1171_ => + (reg_name_matches_prefix _s1171_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s1172_ _)) => + let p0_ := string_drop _s1171_ _s1172_ in + if ((generic_eq p0_ "")) then Some ((rs1, rs2)) + else None + | _ => None + end) + : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + else returnm (None : option ((mword 5 * mword 5)))) + : M (option ((mword 5 * mword 5))). + +Definition _s1150_ (_s1151_ : string) +: M (option ((mword 4 * mword 4))) := + + let _s1152_ := _s1151_ in + (if ((string_startswith _s1152_ "fence.tso")) then + (match (string_drop _s1152_ (projT1 (string_length "fence.tso"))) with + | _s1153_ => + (spc_matches_prefix _s1153_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1154_ _)) => + (match (string_drop _s1153_ _s1154_) with + | _s1155_ => + (fence_bits_matches_prefix _s1155_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (pred,(existT _ _s1156_ _)) => + (match (string_drop _s1155_ _s1156_) with + | _s1157_ => + (sep_matches_prefix _s1157_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1158_ _)) => + (match (string_drop _s1157_ _s1158_) with + | _s1159_ => + (fence_bits_matches_prefix _s1159_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (succ,(existT _ _s1160_ _)) => + let p0_ := string_drop _s1159_ _s1160_ in + if ((generic_eq p0_ "")) then Some ((pred, succ)) + else None + | _ => None + end) + : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + else returnm (None : option ((mword 4 * mword 4)))) + : M (option ((mword 4 * mword 4))). + +Definition _s1138_ (_s1139_ : string) +: M (option ((mword 4 * mword 4))) := + + let _s1140_ := _s1139_ in + (if ((string_startswith _s1140_ "fence")) then + (match (string_drop _s1140_ (projT1 (string_length "fence"))) with + | _s1141_ => + (spc_matches_prefix _s1141_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1142_ _)) => + (match (string_drop _s1141_ _s1142_) with + | _s1143_ => + (fence_bits_matches_prefix _s1143_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (pred,(existT _ _s1144_ _)) => + (match (string_drop _s1143_ _s1144_) with + | _s1145_ => + (sep_matches_prefix _s1145_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1146_ _)) => + (match (string_drop _s1145_ _s1146_) with + | _s1147_ => + (fence_bits_matches_prefix _s1147_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (succ,(existT _ _s1148_ _)) => + let p0_ := string_drop _s1147_ _s1148_ in + if ((generic_eq p0_ "")) then Some ((pred, succ)) + else None + | _ => None + end) + : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + else returnm (None : option ((mword 4 * mword 4)))) + : M (option ((mword 4 * mword 4))). + +Definition _s1119_ (_s1120_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5))) := + + let _s1121_ := _s1120_ in + (if ((string_startswith _s1121_ "rem")) then + (match (string_drop _s1121_ (projT1 (string_length "rem"))) with + | _s1122_ => + (maybe_not_u_matches_prefix _s1122_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s1123_ _)) => + let _s1124_ := string_drop _s1122_ _s1123_ in + (if ((string_startswith _s1124_ "w")) then + (match (string_drop _s1124_ (projT1 (string_length "w"))) with + | _s1125_ => + (spc_matches_prefix _s1125_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1126_ _)) => + (match (string_drop _s1125_ _s1126_) with + | _s1127_ => + (reg_name_matches_prefix _s1127_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1128_ _)) => + (match (string_drop _s1127_ _s1128_) with + | _s1129_ => + (sep_matches_prefix _s1129_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1130_ _)) => + (match (string_drop _s1129_ _s1130_) with + | _s1131_ => + (reg_name_matches_prefix _s1131_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1132_ _)) => + (match (string_drop _s1131_ _s1132_) with + | _s1133_ => + (sep_matches_prefix _s1133_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1134_ _)) => + (match (string_drop _s1133_ _s1134_) with + | _s1135_ => + (reg_name_matches_prefix _s1135_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s1136_ _)) => + let p0_ := + string_drop _s1135_ + _s1136_ in + if ((generic_eq p0_ "")) + then + Some + ((s, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))). + +Definition _s1100_ (_s1101_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5))) := + + let _s1102_ := _s1101_ in + (if ((string_startswith _s1102_ "div")) then + (match (string_drop _s1102_ (projT1 (string_length "div"))) with + | _s1103_ => + (maybe_not_u_matches_prefix _s1103_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s1104_ _)) => + let _s1105_ := string_drop _s1103_ _s1104_ in + (if ((string_startswith _s1105_ "w")) then + (match (string_drop _s1105_ (projT1 (string_length "w"))) with + | _s1106_ => + (spc_matches_prefix _s1106_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1107_ _)) => + (match (string_drop _s1106_ _s1107_) with + | _s1108_ => + (reg_name_matches_prefix _s1108_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1109_ _)) => + (match (string_drop _s1108_ _s1109_) with + | _s1110_ => + (sep_matches_prefix _s1110_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1111_ _)) => + (match (string_drop _s1110_ _s1111_) with + | _s1112_ => + (reg_name_matches_prefix _s1112_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1113_ _)) => + (match (string_drop _s1112_ _s1113_) with + | _s1114_ => + (sep_matches_prefix _s1114_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1115_ _)) => + (match (string_drop _s1114_ _s1115_) with + | _s1116_ => + (reg_name_matches_prefix _s1116_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s1117_ _)) => + let p0_ := + string_drop _s1116_ + _s1117_ in + if ((generic_eq p0_ "")) + then + Some + ((s, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))). + +Definition _s1084_ (_s1085_ : string) +: M (option ((mword 5 * mword 5 * mword 5))) := + + let _s1086_ := _s1085_ in + (if ((string_startswith _s1086_ "mulw")) then + (match (string_drop _s1086_ (projT1 (string_length "mulw"))) with + | _s1087_ => + (spc_matches_prefix _s1087_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1088_ _)) => + (match (string_drop _s1087_ _s1088_) with + | _s1089_ => + (reg_name_matches_prefix _s1089_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1090_ _)) => + (match (string_drop _s1089_ _s1090_) with + | _s1091_ => + (sep_matches_prefix _s1091_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1092_ _)) => + (match (string_drop _s1091_ _s1092_) with + | _s1093_ => + (reg_name_matches_prefix _s1093_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rs1,(existT _ _s1094_ _)) => + (match (string_drop _s1093_ _s1094_) with + | _s1095_ => + (sep_matches_prefix _s1095_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s1096_ _)) => + (match (string_drop _s1095_ _s1096_) with + | _s1097_ => + (reg_name_matches_prefix _s1097_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (rs2,(existT _ _s1098_ _)) => + let p0_ := + string_drop _s1097_ _s1098_ in + if ((generic_eq p0_ "")) then + Some + ((rd, rs1, rs2)) + else None + | _ => None + end) + : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + else returnm (None : option ((mword 5 * mword 5 * mword 5)))) + : M (option ((mword 5 * mword 5 * mword 5))). + +Definition _s1066_ (_s1067_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5))) := + + let _s1068_ := _s1067_ in + (if ((string_startswith _s1068_ "rem")) then + (match (string_drop _s1068_ (projT1 (string_length "rem"))) with + | _s1069_ => + (maybe_not_u_matches_prefix _s1069_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s1070_ _)) => + (match (string_drop _s1069_ _s1070_) with + | _s1071_ => + (spc_matches_prefix _s1071_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1072_ _)) => + (match (string_drop _s1071_ _s1072_) with + | _s1073_ => + (reg_name_matches_prefix _s1073_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1074_ _)) => + (match (string_drop _s1073_ _s1074_) with + | _s1075_ => + (sep_matches_prefix _s1075_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1076_ _)) => + (match (string_drop _s1075_ _s1076_) with + | _s1077_ => + (reg_name_matches_prefix _s1077_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1078_ _)) => + (match (string_drop _s1077_ _s1078_) with + | _s1079_ => + (sep_matches_prefix _s1079_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1080_ _)) => + (match (string_drop _s1079_ _s1080_) with + | _s1081_ => + (reg_name_matches_prefix _s1081_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s1082_ _)) => + let p0_ := + string_drop _s1081_ _s1082_ in + if ((generic_eq p0_ "")) then + Some + ((s, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))). + +Definition _s1048_ (_s1049_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5))) := + + let _s1050_ := _s1049_ in + (if ((string_startswith _s1050_ "div")) then + (match (string_drop _s1050_ (projT1 (string_length "div"))) with + | _s1051_ => + (maybe_not_u_matches_prefix _s1051_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s1052_ _)) => + (match (string_drop _s1051_ _s1052_) with + | _s1053_ => + (spc_matches_prefix _s1053_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1054_ _)) => + (match (string_drop _s1053_ _s1054_) with + | _s1055_ => + (reg_name_matches_prefix _s1055_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1056_ _)) => + (match (string_drop _s1055_ _s1056_) with + | _s1057_ => + (sep_matches_prefix _s1057_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1058_ _)) => + (match (string_drop _s1057_ _s1058_) with + | _s1059_ => + (reg_name_matches_prefix _s1059_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1060_ _)) => + (match (string_drop _s1059_ _s1060_) with + | _s1061_ => + (sep_matches_prefix _s1061_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1062_ _)) => + (match (string_drop _s1061_ _s1062_) with + | _s1063_ => + (reg_name_matches_prefix _s1063_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s1064_ _)) => + let p0_ := + string_drop _s1063_ _s1064_ in + if ((generic_eq p0_ "")) then + Some + ((s, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))). + +Definition _s1031_ (_s1032_ : string) +: M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) := + + (match _s1032_ with + | _s1033_ => + (mul_mnemonic_matches_prefix _s1033_) >>= fun w__0 : option (((bool * bool * bool) * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some ((high, signed1, signed2),(existT _ _s1034_ _)) => + (match (string_drop _s1033_ _s1034_) with + | _s1035_ => + (spc_matches_prefix _s1035_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1036_ _)) => + (match (string_drop _s1035_ _s1036_) with + | _s1037_ => + (reg_name_matches_prefix _s1037_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1038_ _)) => + (match (string_drop _s1037_ _s1038_) with + | _s1039_ => + (sep_matches_prefix _s1039_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1040_ _)) => + (match (string_drop _s1039_ _s1040_) with + | _s1041_ => + (reg_name_matches_prefix _s1041_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1042_ _)) => + (match (string_drop _s1041_ _s1042_) with + | _s1043_ => + (sep_matches_prefix _s1043_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1044_ _)) => + (match (string_drop _s1043_ _s1044_) with + | _s1045_ => + (reg_name_matches_prefix _s1045_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (rs2,(existT _ _s1046_ _)) => + let p0_ := + string_drop _s1045_ _s1046_ in + if ((generic_eq p0_ "")) then + Some + ((high, signed1, signed2, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))). + +Definition _s1016_ (_s1017_ : string) +: M (option ((sopw * mword 5 * mword 5 * mword 5))) := + + (match _s1017_ with + | _s1018_ => + (shiftiwop_mnemonic_matches_prefix _s1018_) >>= fun w__0 : option ((sopw * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1019_ _)) => + (match (string_drop _s1018_ _s1019_) with + | _s1020_ => + (spc_matches_prefix _s1020_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1021_ _)) => + (match (string_drop _s1020_ _s1021_) with + | _s1022_ => + (reg_name_matches_prefix _s1022_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1023_ _)) => + (match (string_drop _s1022_ _s1023_) with + | _s1024_ => + (sep_matches_prefix _s1024_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1025_ _)) => + (match (string_drop _s1024_ _s1025_) with + | _s1026_ => + (reg_name_matches_prefix _s1026_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (rs1,(existT _ _s1027_ _)) => + match (string_drop _s1026_ _s1027_) with + | _s1028_ => + match (hex_bits_5_matches_prefix _s1028_) with + | Some (shamt,(existT _ _s1029_ _)) => + let p0_ := string_drop _s1028_ _s1029_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None : option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))). + +Definition _s999_ (_s1000_ : string) +: M (option ((ropw * mword 5 * mword 5 * mword 5))) := + + (match _s1000_ with + | _s1001_ => + (rtypew_mnemonic_matches_prefix _s1001_) >>= fun w__0 : option ((ropw * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1002_ _)) => + (match (string_drop _s1001_ _s1002_) with + | _s1003_ => + (spc_matches_prefix _s1003_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1004_ _)) => + (match (string_drop _s1003_ _s1004_) with + | _s1005_ => + (reg_name_matches_prefix _s1005_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1006_ _)) => + (match (string_drop _s1005_ _s1006_) with + | _s1007_ => + (sep_matches_prefix _s1007_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1008_ _)) => + (match (string_drop _s1007_ _s1008_) with + | _s1009_ => + (reg_name_matches_prefix _s1009_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1010_ _)) => + (match (string_drop _s1009_ _s1010_) with + | _s1011_ => + (sep_matches_prefix _s1011_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1012_ _)) => + (match (string_drop _s1011_ _s1012_) with + | _s1013_ => + (reg_name_matches_prefix _s1013_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (rs2,(existT _ _s1014_ _)) => + let p0_ := + string_drop _s1013_ _s1014_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))). + +Definition _s982_ (_s983_ : string) +: M (option ((sop * mword 5 * mword 5 * mword 5))) := + + (match _s983_ with + | _s984_ => + (shiftw_mnemonic_matches_prefix _s984_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s985_ _)) => + (match (string_drop _s984_ _s985_) with + | _s986_ => + (spc_matches_prefix _s986_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__1 with + | Some (tt,(existT _ _s987_ _)) => + (match (string_drop _s986_ _s987_) with + | _s988_ => + (reg_name_matches_prefix _s988_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s989_ _)) => + (match (string_drop _s988_ _s989_) with + | _s990_ => + (sep_matches_prefix _s990_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s991_ _)) => + (match (string_drop _s990_ _s991_) with + | _s992_ => + (reg_name_matches_prefix _s992_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s993_ _)) => + (match (string_drop _s992_ _s993_) with + | _s994_ => + (sep_matches_prefix _s994_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (tt,(existT _ _s995_ _)) => + match (string_drop _s994_ _s995_) with + | _s996_ => + match (hex_bits_5_matches_prefix + _s996_) with + | Some (shamt,(existT _ _s997_ _)) => + let p0_ := + string_drop _s996_ _s997_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))). + +Definition _s966_ (_s967_ : string) +: M (option ((mword 5 * mword 5 * mword 12))) := + + let _s968_ := _s967_ in + (if ((string_startswith _s968_ "addiw")) then + (match (string_drop _s968_ (projT1 (string_length "addiw"))) with + | _s969_ => + (spc_matches_prefix _s969_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s970_ _)) => + (match (string_drop _s969_ _s970_) with + | _s971_ => + (reg_name_matches_prefix _s971_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s972_ _)) => + (match (string_drop _s971_ _s972_) with + | _s973_ => + (sep_matches_prefix _s973_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s974_ _)) => + (match (string_drop _s973_ _s974_) with + | _s975_ => + (reg_name_matches_prefix _s975_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rs1,(existT _ _s976_ _)) => + (match (string_drop _s975_ _s976_) with + | _s977_ => + (sep_matches_prefix _s977_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s978_ _)) => + match (string_drop _s977_ _s978_) with + | _s979_ => + match (hex_bits_12_matches_prefix _s979_) with + | Some (imm,(existT _ _s980_ _)) => + let p0_ := string_drop _s979_ _s980_ in + if ((generic_eq p0_ "")) then + Some + ((rd, rs1, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + else returnm (None : option ((mword 5 * mword 5 * mword 12)))) + : M (option ((mword 5 * mword 5 * mword 12))). + +Definition _s944_ (_s945_ : string) +: M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) := + + let _s946_ := _s945_ in + (if ((string_startswith _s946_ "s")) then + (match (string_drop _s946_ (projT1 (string_length "s"))) with + | _s947_ => + (size_mnemonic_matches_prefix _s947_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s948_ _)) => + (match (string_drop _s947_ _s948_) with + | _s949_ => + (maybe_aq_matches_prefix _s949_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (aq,(existT _ _s950_ _)) => + (match (string_drop _s949_ _s950_) with + | _s951_ => + (maybe_rl_matches_prefix _s951_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rl,(existT _ _s952_ _)) => + (match (string_drop _s951_ _s952_) with + | _s953_ => + (spc_matches_prefix _s953_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s954_ _)) => + (match (string_drop _s953_ _s954_) with + | _s955_ => + (reg_name_matches_prefix _s955_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rd,(existT _ _s956_ _)) => + (match (string_drop _s955_ _s956_) with + | _s957_ => + (sep_matches_prefix _s957_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s958_ _)) => + (match (string_drop _s957_ _s958_) with + | _s959_ => + (reg_name_matches_prefix _s959_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (rs1,(existT _ _s960_ _)) => + (match (string_drop _s959_ _s960_) with + | _s961_ => + (sep_matches_prefix _s961_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__7 with + | Some + (tt,(existT _ _s962_ _)) => + match (string_drop + _s961_ + _s962_) with + | _s963_ => + match (hex_bits_12_matches_prefix + _s963_) with + | Some + (imm,(existT _ _s964_ _)) => + let p0_ := + string_drop + _s963_ + _s964_ in + if ((generic_eq + p0_ "")) + then + Some + ((size, aq, rl, rd, rs1, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12)))) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))). + +Definition _s920_ (_s921_ : string) +: M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) := + + let _s922_ := _s921_ in + (if ((string_startswith _s922_ "l")) then + (match (string_drop _s922_ (projT1 (string_length "l"))) with + | _s923_ => + (size_mnemonic_matches_prefix _s923_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s924_ _)) => + (match (string_drop _s923_ _s924_) with + | _s925_ => + (maybe_u_matches_prefix _s925_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (is_unsigned,(existT _ _s926_ _)) => + (match (string_drop _s925_ _s926_) with + | _s927_ => + (maybe_aq_matches_prefix _s927_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (aq,(existT _ _s928_ _)) => + (match (string_drop _s927_ _s928_) with + | _s929_ => + (maybe_rl_matches_prefix _s929_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rl,(existT _ _s930_ _)) => + (match (string_drop _s929_ _s930_) with + | _s931_ => + (spc_matches_prefix _s931_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s932_ _)) => + (match (string_drop _s931_ _s932_) with + | _s933_ => + (reg_name_matches_prefix _s933_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (rd,(existT _ _s934_ _)) => + (match (string_drop _s933_ _s934_) with + | _s935_ => + (sep_matches_prefix _s935_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (tt,(existT _ _s936_ _)) => + (match (string_drop _s935_ _s936_) with + | _s937_ => + (reg_name_matches_prefix _s937_) >>= fun w__7 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__7 with + | Some (rs1,(existT _ _s938_ _)) => + (match (string_drop _s937_ + _s938_) with + | _s939_ => + (sep_matches_prefix _s939_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__8 with + | Some + (tt,(existT _ _s940_ _)) => + match (string_drop + _s939_ + _s940_) with + | _s941_ => + match (hex_bits_12_matches_prefix + _s941_) with + | Some + (imm,(existT _ _s942_ _)) => + let p0_ := + string_drop + _s941_ + _s942_ in + if ((generic_eq + p0_ + "")) + then + Some + ((size, is_unsigned, aq, rl, rd, rs1, imm)) + else + None + | _ => + None + end + end + | _ => None + end) + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + else returnm (None : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12)))) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))). + +Definition _s903_ (_s904_ : string) +: M (option ((rop * mword 5 * mword 5 * mword 5))) := + + (match _s904_ with + | _s905_ => + (rtype_mnemonic_matches_prefix _s905_) >>= fun w__0 : option ((rop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s906_ _)) => + (match (string_drop _s905_ _s906_) with + | _s907_ => + (spc_matches_prefix _s907_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__1 with + | Some (tt,(existT _ _s908_ _)) => + (match (string_drop _s907_ _s908_) with + | _s909_ => + (reg_name_matches_prefix _s909_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s910_ _)) => + (match (string_drop _s909_ _s910_) with + | _s911_ => + (sep_matches_prefix _s911_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s912_ _)) => + (match (string_drop _s911_ _s912_) with + | _s913_ => + (reg_name_matches_prefix _s913_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s914_ _)) => + (match (string_drop _s913_ _s914_) with + | _s915_ => + (sep_matches_prefix _s915_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s916_ _)) => + (match (string_drop _s915_ _s916_) with + | _s917_ => + (reg_name_matches_prefix _s917_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (rs2,(existT _ _s918_ _)) => + let p0_ := + string_drop _s917_ _s918_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))). + +Definition _s888_ (_s889_ : string) +: M (option ((sop * mword 5 * mword 5 * mword 6))) := + + (match _s889_ with + | _s890_ => + (shiftiop_mnemonic_matches_prefix _s890_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s891_ _)) => + (match (string_drop _s890_ _s891_) with + | _s892_ => + (spc_matches_prefix _s892_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__1 with + | Some (tt,(existT _ _s893_ _)) => + (match (string_drop _s892_ _s893_) with + | _s894_ => + (reg_name_matches_prefix _s894_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s895_ _)) => + (match (string_drop _s894_ _s895_) with + | _s896_ => + (sep_matches_prefix _s896_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s897_ _)) => + (match (string_drop _s896_ _s897_) with + | _s898_ => + (reg_name_matches_prefix _s898_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (rs1,(existT _ _s899_ _)) => + match (string_drop _s898_ _s899_) with + | _s900_ => + match (hex_bits_6_matches_prefix _s900_) with + | Some (shamt,(existT _ _s901_ _)) => + let p0_ := string_drop _s900_ _s901_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + | _ => + returnm (None : option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))). + +Definition _s871_ (_s872_ : string) +: M (option ((iop * mword 5 * mword 5 * mword 12))) := + + (match _s872_ with + | _s873_ => + (itype_mnemonic_matches_prefix _s873_) >>= fun w__0 : option ((iop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s874_ _)) => + (match (string_drop _s873_ _s874_) with + | _s875_ => + (spc_matches_prefix _s875_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__1 with + | Some (tt,(existT _ _s876_ _)) => + (match (string_drop _s875_ _s876_) with + | _s877_ => + (reg_name_matches_prefix _s877_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s878_ _)) => + (match (string_drop _s877_ _s878_) with + | _s879_ => + (sep_matches_prefix _s879_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s880_ _)) => + (match (string_drop _s879_ _s880_) with + | _s881_ => + (reg_name_matches_prefix _s881_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s882_ _)) => + (match (string_drop _s881_ _s882_) with + | _s883_ => + (sep_matches_prefix _s883_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (tt,(existT _ _s884_ _)) => + match (string_drop _s883_ _s884_) with + | _s885_ => + match (hex_bits_12_matches_prefix + _s885_) with + | Some (imm,(existT _ _s886_ _)) => + let p0_ := + string_drop _s885_ _s886_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))). + +Definition _s854_ (_s855_ : string) +: M (option ((bop * mword 5 * mword 5 * mword 13))) := + + (match _s855_ with + | _s856_ => + (btype_mnemonic_matches_prefix _s856_) >>= fun w__0 : option ((bop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s857_ _)) => + (match (string_drop _s856_ _s857_) with + | _s858_ => + (spc_matches_prefix _s858_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__1 with + | Some (tt,(existT _ _s859_ _)) => + (match (string_drop _s858_ _s859_) with + | _s860_ => + (reg_name_matches_prefix _s860_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rs1,(existT _ _s861_ _)) => + (match (string_drop _s860_ _s861_) with + | _s862_ => + (sep_matches_prefix _s862_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s863_ _)) => + (match (string_drop _s862_ _s863_) with + | _s864_ => + (reg_name_matches_prefix _s864_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs2,(existT _ _s865_ _)) => + (match (string_drop _s864_ _s865_) with + | _s866_ => + (sep_matches_prefix _s866_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (tt,(existT _ _s867_ _)) => + match (string_drop _s866_ _s867_) with + | _s868_ => + match (hex_bits_13_matches_prefix + _s868_) with + | Some (imm,(existT _ _s869_ _)) => + let p0_ := + string_drop _s868_ _s869_ in + if ((generic_eq p0_ "")) then + Some + ((op, rs1, rs2, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + | _ => + returnm (None + : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + | _ => + returnm (None : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))). + +Definition _s838_ (_s839_ : string) +: M (option ((mword 5 * mword 5 * mword 12))) := + + let _s840_ := _s839_ in + (if ((string_startswith _s840_ "jalr")) then + (match (string_drop _s840_ (projT1 (string_length "jalr"))) with + | _s841_ => + (spc_matches_prefix _s841_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s842_ _)) => + (match (string_drop _s841_ _s842_) with + | _s843_ => + (reg_name_matches_prefix _s843_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s844_ _)) => + (match (string_drop _s843_ _s844_) with + | _s845_ => + (sep_matches_prefix _s845_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s846_ _)) => + (match (string_drop _s845_ _s846_) with + | _s847_ => + (reg_name_matches_prefix _s847_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rs1,(existT _ _s848_ _)) => + (match (string_drop _s847_ _s848_) with + | _s849_ => + (sep_matches_prefix _s849_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s850_ _)) => + match (string_drop _s849_ _s850_) with + | _s851_ => + match (hex_bits_12_matches_prefix _s851_) with + | Some (imm,(existT _ _s852_ _)) => + let p0_ := string_drop _s851_ _s852_ in + if ((generic_eq p0_ "")) then + Some + ((rd, rs1, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + else returnm (None : option ((mword 5 * mword 5 * mword 12)))) + : M (option ((mword 5 * mword 5 * mword 12))). + +Definition _s826_ (_s827_ : string) +: M (option ((mword 5 * mword 21))) := + + let _s828_ := _s827_ in + (if ((string_startswith _s828_ "jal")) then + (match (string_drop _s828_ (projT1 (string_length "jal"))) with + | _s829_ => + (spc_matches_prefix _s829_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s830_ _)) => + (match (string_drop _s829_ _s830_) with + | _s831_ => + (reg_name_matches_prefix _s831_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s832_ _)) => + (match (string_drop _s831_ _s832_) with + | _s833_ => + (sep_matches_prefix _s833_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s834_ _)) => + match (string_drop _s833_ _s834_) with + | _s835_ => + match (hex_bits_21_matches_prefix _s835_) with + | Some (imm,(existT _ _s836_ _)) => + let p0_ := string_drop _s835_ _s836_ in + if ((generic_eq p0_ "")) then Some ((rd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 21))) + end) + : M (option ((mword 5 * mword 21))) + | _ => returnm (None : option ((mword 5 * mword 21))) + end) + : M (option ((mword 5 * mword 21))) + end) + : M (option ((mword 5 * mword 21))) + | _ => returnm (None : option ((mword 5 * mword 21))) + end) + : M (option ((mword 5 * mword 21))) + end) + : M (option ((mword 5 * mword 21))) + else returnm (None : option ((mword 5 * mword 21)))) + : M (option ((mword 5 * mword 21))). + +Definition _s813_ (_s814_ : string) +: M (option ((uop * mword 5 * mword 20))) := + + (match _s814_ with + | _s815_ => + (utype_mnemonic_matches_prefix _s815_) >>= fun w__0 : option ((uop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s816_ _)) => + (match (string_drop _s815_ _s816_) with + | _s817_ => + (spc_matches_prefix _s817_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__1 with + | Some (tt,(existT _ _s818_ _)) => + (match (string_drop _s817_ _s818_) with + | _s819_ => + (reg_name_matches_prefix _s819_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s820_ _)) => + (match (string_drop _s819_ _s820_) with + | _s821_ => + (sep_matches_prefix _s821_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (tt,(existT _ _s822_ _)) => + match (string_drop _s821_ _s822_) with + | _s823_ => + match (hex_bits_20_matches_prefix _s823_) with + | Some (imm,(existT _ _s824_ _)) => + let p0_ := string_drop _s823_ _s824_ in + if ((generic_eq p0_ "")) then Some ((op, rd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + | _ => returnm (None : option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + | _ => returnm (None : option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + | _ => returnm (None : option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))). + +Definition assembly_backwards (arg_ : string) +: M (ast) := + + let _s825_ := arg_ in + (_s813_ _s825_) >>= fun w__0 : option ((uop * mword 5 * mword 20)) => + (if ((match w__0 with | Some (op,rd,imm) => true | _ => false end)) then + (_s813_ _s825_) >>= fun w__1 : option ((uop * mword 5 * mword 20)) => + (match w__1 with + | Some (op,rd,imm) => returnm ((UTYPE ((imm, rd, op))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s826_ _s825_) >>= fun w__4 : option ((mword 5 * mword 21)) => + (if ((match w__4 with | Some (rd,imm) => true | _ => false end)) then + (_s826_ _s825_) >>= fun w__5 : option ((mword 5 * mword 21)) => + (match w__5 with + | Some (rd,imm) => returnm ((RISCV_JAL ((imm, rd))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s838_ _s825_) >>= fun w__8 : option ((mword 5 * mword 5 * mword 12)) => + (if ((match w__8 with | Some (rd,rs1,imm) => true | _ => false end)) then + (_s838_ _s825_) >>= fun w__9 : option ((mword 5 * mword 5 * mword 12)) => + (match w__9 with + | Some (rd,rs1,imm) => returnm ((RISCV_JALR ((imm, rs1, rd))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s854_ _s825_) >>= fun w__12 : option ((bop * mword 5 * mword 5 * mword 13)) => + (if ((match w__12 with | Some (op,rs1,rs2,imm) => true | _ => false end)) then + (_s854_ _s825_) >>= fun w__13 : option ((bop * mword 5 * mword 5 * mword 13)) => + (match w__13 with + | Some (op,rs1,rs2,imm) => returnm ((BTYPE ((imm, rs2, rs1, op))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s871_ _s825_) >>= fun w__16 : option ((iop * mword 5 * mword 5 * mword 12)) => + (if ((match w__16 with | Some (op,rd,rs1,imm) => true | _ => false end)) then + (_s871_ _s825_) >>= fun w__17 : option ((iop * mword 5 * mword 5 * mword 12)) => + (match w__17 with + | Some (op,rd,rs1,imm) => returnm ((ITYPE ((imm, rs1, rd, op))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s888_ _s825_) >>= fun w__20 : option ((sop * mword 5 * mword 5 * mword 6)) => + (if ((match w__20 with | Some (op,rd,rs1,shamt) => true | _ => false end)) then + (_s888_ _s825_) >>= fun w__21 : option ((sop * mword 5 * mword 5 * mword 6)) => + (match w__21 with + | Some (op,rd,rs1,shamt) => + returnm ((SHIFTIOP ((shamt, rs1, rd, op))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s903_ _s825_) >>= fun w__24 : option ((rop * mword 5 * mword 5 * mword 5)) => + (if ((match w__24 with | Some (op,rd,rs1,rs2) => true | _ => false end)) then + (_s903_ _s825_) >>= fun w__25 : option ((rop * mword 5 * mword 5 * mword 5)) => + (match w__25 with + | Some (op,rd,rs1,rs2) => returnm ((RTYPE ((rs2, rs1, rd, op))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s920_ _s825_) >>= fun w__28 : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12)) => + (if ((match w__28 with + | Some (size,is_unsigned,aq,rl,rd,rs1,imm) => true + | _ => false + end)) then + (_s920_ _s825_) >>= fun w__29 : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12)) => + (match w__29 with + | Some (size,is_unsigned,aq,rl,rd,rs1,imm) => + returnm ((LOAD ((imm, rs1, rd, is_unsigned, size, aq, rl))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s944_ _s825_) >>= fun w__32 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12)) => + (if ((match w__32 with + | Some (size,aq,rl,rd,rs1,imm) => true + | _ => false + end)) then + (_s944_ _s825_) >>= fun w__33 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12)) => + (match w__33 with + | Some (size,aq,rl,rd,rs1,imm) => + returnm ((STORE ((imm, rs1, rd, size, aq, rl))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s966_ _s825_) >>= fun w__36 : option ((mword 5 * mword 5 * mword 12)) => + (if ((match w__36 with | Some (rd,rs1,imm) => true | _ => false end)) + then + (_s966_ _s825_) >>= fun w__37 : option ((mword 5 * mword 5 * mword 12)) => + (match w__37 with + | Some (rd,rs1,imm) => returnm ((ADDIW ((imm, rs1, rd))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s982_ _s825_) >>= fun w__40 : option ((sop * mword 5 * mword 5 * mword 5)) => + (if ((match w__40 with + | Some (op,rd,rs1,shamt) => true + | _ => false + end)) then + (_s982_ _s825_) >>= fun w__41 : option ((sop * mword 5 * mword 5 * mword 5)) => + (match w__41 with + | Some (op,rd,rs1,shamt) => + returnm ((SHIFTW ((shamt, rs1, rd, op))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s999_ _s825_) >>= fun w__44 : option ((ropw * mword 5 * mword 5 * mword 5)) => + (if ((match w__44 with + | Some (op,rd,rs1,rs2) => true + | _ => false + end)) then + (_s999_ _s825_) >>= fun w__45 : option ((ropw * mword 5 * mword 5 * mword 5)) => + (match w__45 with + | Some (op,rd,rs1,rs2) => + returnm ((RTYPEW ((rs2, rs1, rd, op))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1016_ _s825_) >>= fun w__48 : option ((sopw * mword 5 * mword 5 * mword 5)) => + (if ((match w__48 with + | Some (op,rd,rs1,shamt) => true + | _ => false + end)) then + (_s1016_ _s825_) >>= fun w__49 : option ((sopw * mword 5 * mword 5 * mword 5)) => + (match w__49 with + | Some (op,rd,rs1,shamt) => + returnm ((SHIFTIWOP ((shamt, rs1, rd, op))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1031_ _s825_) >>= fun w__52 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__52 with + | Some (high,signed1,signed2,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1031_ _s825_) >>= fun w__53 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)) => + (match w__53 with + | Some (high,signed1,signed2,rd,rs1,rs2) => + returnm ((MUL + ((rs2, rs1, rd, high, signed1, signed2))) + : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1048_ _s825_) >>= fun w__56 : option ((bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__56 with + | Some (s,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1048_ _s825_) >>= fun w__57 : option ((bool * mword 5 * mword 5 * mword 5)) => + (match w__57 with + | Some (s,rd,rs1,rs2) => + returnm ((DIV ((rs2, rs1, rd, s))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1066_ _s825_) >>= fun w__60 : option ((bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__60 with + | Some (s,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1066_ _s825_) >>= fun w__61 : option ((bool * mword 5 * mword 5 * mword 5)) => + (match w__61 with + | Some (s,rd,rs1,rs2) => + returnm ((REM ((rs2, rs1, rd, s))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1084_ _s825_) >>= fun w__64 : option ((mword 5 * mword 5 * mword 5)) => + (if ((match w__64 with + | Some (rd,rs1,rs2) => true + | _ => false + end)) then + (_s1084_ _s825_) >>= fun w__65 : option ((mword 5 * mword 5 * mword 5)) => + (match w__65 with + | Some (rd,rs1,rs2) => + returnm ((MULW ((rs2, rs1, rd))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1100_ _s825_) >>= fun w__68 : option ((bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__68 with + | Some (s,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1100_ _s825_) >>= fun w__69 : option ((bool * mword 5 * mword 5 * mword 5)) => + (match w__69 with + | Some (s,rd,rs1,rs2) => + returnm ((DIVW + ((rs2, rs1, rd, s))) + : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1119_ _s825_) >>= fun w__72 : option ((bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__72 with + | Some (s,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1119_ _s825_) >>= fun w__73 : option ((bool * mword 5 * mword 5 * mword 5)) => + (match w__73 with + | Some (s,rd,rs1,rs2) => + returnm ((REMW + ((rs2, rs1, rd, s))) + : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1138_ _s825_) >>= fun w__76 : option ((mword 4 * mword 4)) => + (if ((match w__76 with + | Some (pred,succ) => true + | _ => false + end)) then + (_s1138_ _s825_) >>= fun w__77 : option ((mword 4 * mword 4)) => + (match w__77 with + | Some (pred,succ) => + returnm ((FENCE + ((pred, succ))) + : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1150_ _s825_) >>= fun w__80 : option ((mword 4 * mword 4)) => + (if ((match w__80 with + | Some (pred,succ) => true + | _ => false + end)) then + (_s1150_ _s825_) >>= fun w__81 : option ((mword 4 * mword 4)) => + (match w__81 with + | Some (pred,succ) => + returnm ((FENCE_TSO + ((pred, succ))) + : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else if ((generic_eq _s825_ + "fence.i")) then + returnm ((FENCEI + (tt)) + : ast ) + else if ((generic_eq _s825_ "ecall")) + then + returnm ((ECALL + (tt)) + : ast ) + else if ((generic_eq _s825_ "mret")) + then + returnm ((MRET + (tt)) + : ast ) + else if ((generic_eq _s825_ "sret")) + then + returnm ((SRET + (tt)) + : ast ) + else if ((generic_eq _s825_ "ebreak")) + then + returnm ((EBREAK + (tt)) + : ast ) + else if ((generic_eq _s825_ "wfi")) + then + returnm ((WFI + (tt)) + : ast ) + else + (_s1162_ _s825_) >>= fun w__84 : option ((mword 5 * mword 5)) => + (if ((match w__84 with + | Some (rs1,rs2) => true + | _ => false + end)) then + (_s1162_ _s825_) >>= fun w__85 : option ((mword 5 * mword 5)) => + (match w__85 with + | Some (rs1,rs2) => + returnm ((SFENCE_VMA + ((rs1, rs2))) + : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1174_ _s825_) >>= fun w__88 : option ((word_width * bool * bool * mword 5 * mword 5)) => + (if ((match w__88 with + | Some + (size,aq,rl,rd,rs1) => + true + | _ => false + end)) then + (_s1174_ _s825_) >>= fun w__89 : option ((word_width * bool * bool * mword 5 * mword 5)) => + (match w__89 with + | Some (size,aq,rl,rd,rs1) => + returnm ((LOADRES + ((aq, rl, rs1, size, rd))) + : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1192_ _s825_) >>= fun w__92 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__92 with + | Some + (size,aq,rl,rd,rs1,rs2) => + true + | _ => false + end)) then + (_s1192_ _s825_) >>= fun w__93 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)) => + (match w__93 with + | Some + (size,aq,rl,rd,rs1,rs2) => + returnm ((STORECON + ((aq, rl, rs2, rs1, size, rd))) + : ast ) + | _ => + exit tt : M (ast) + end) + : M (ast) + else + (_s1214_ _s825_) >>= fun w__96 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__96 with + | Some + (op,width,aq,rl,rd,rs1,rs2) => + true + | _ => false + end)) then + (_s1214_ _s825_) >>= fun w__97 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)) => + (match w__97 with + | Some + (op,width,aq,rl,rd,rs1,rs2) => + returnm ((AMO + ((op, aq, rl, rs2, rs1, width, rd))) + : ast ) + | _ => + exit tt : M (ast) + end) + : M (ast) + else + (_s1238_ _s825_) >>= fun w__100 : option ((csrop * mword 5 * mword 5 * mword 12)) => + (if ((match w__100 with + | Some + (op,rd,rs1,csr) => + true + | _ => false + end)) then + (_s1238_ _s825_) >>= fun w__101 : option ((csrop * mword 5 * mword 5 * mword 12)) => + (match w__101 with + | Some + (op,rd,rs1,csr) => + returnm ((CSR + ((csr, rs1, rd, true, op))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1256_ _s825_) >>= fun w__104 : option ((csrop * mword 5 * mword 5 * mword 12)) => + (if ((match w__104 with + | Some + (op,rd,rs1,csr) => + true + | _ => false + end)) then + (_s1256_ _s825_) >>= fun w__105 : option ((csrop * mword 5 * mword 5 * mword 12)) => + (match w__105 with + | Some + (op,rd,rs1,csr) => + returnm ((CSR + ((csr, rs1, rd, false, op))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else if ((generic_eq + _s825_ + "c.nop")) + then + returnm ((C_NOP + (tt)) + : ast ) + else + (_s1273_ _s825_) >>= fun w__108 : option ((mword 3 * mword 8)) => + (if ((match w__108 with + | Some + (rdc,nzimm) => + neq_vec + nzimm + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] + : mword 8) + | _ => + false + end)) then + (_s1273_ + _s825_) >>= fun w__109 : option ((mword 3 * mword 8)) => + (match w__109 with + | Some + (rdc,nzimm) => + returnm ((C_ADDI4SPN + ((rdc, nzimm))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1285_ + _s825_) >>= fun w__112 : option ((mword 3 * mword 3 * mword 5)) => + (if ((match w__112 with + | Some + (rdc,rsc,uimm) => + true + | _ => + false + end)) + then + (_s1285_ + _s825_) >>= fun w__113 : option ((mword 3 * mword 3 * mword 5)) => + (match w__113 with + | Some + (rdc,rsc,uimm) => + returnm ((C_LW + ((uimm, rsc, rdc))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1301_ + _s825_) >>= fun w__116 : option ((mword 3 * mword 3 * mword 5)) => + (if ((match w__116 with + | Some + (rdc,rsc,uimm) => + true + | _ => + false + end)) + then + (_s1301_ + _s825_) >>= fun w__117 : option ((mword 3 * mword 3 * mword 5)) => + (match w__117 with + | Some + (rdc,rsc,uimm) => + returnm ((C_LD + ((uimm, rsc, rdc))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1317_ + _s825_) >>= fun w__120 : option ((mword 3 * mword 3 * mword 5)) => + (if ((match w__120 with + | Some + (rsc1,rsc2,uimm) => + true + | _ => + false + end)) + then + (_s1317_ + _s825_) >>= fun w__121 : option ((mword 3 * mword 3 * mword 5)) => + (match w__121 with + | Some + (rsc1,rsc2,uimm) => + returnm ((C_SW + ((uimm, rsc1, rsc2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1333_ + _s825_) >>= fun w__124 : option ((mword 3 * mword 3 * mword 5)) => + (if ((match w__124 with + | Some + (rsc1,rsc2,uimm) => + true + | _ => + false + end)) + then + (_s1333_ + _s825_) >>= fun w__125 : option ((mword 3 * mword 3 * mword 5)) => + (match w__125 with + | Some + (rsc1,rsc2,uimm) => + returnm ((C_SD + ((uimm, rsc1, rsc2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1349_ + _s825_) >>= fun w__128 : option ((mword 5 * mword 6)) => + (if + ((match w__128 with + | Some + (rsd,nzi) => + andb + (neq_vec + nzi + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6)) + (neq_int + (projT1 (regbits_to_regno + rsd)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s1349_ + _s825_) >>= fun w__129 : option ((mword 5 * mword 6)) => + (match w__129 with + | Some + (rsd,nzi) => + returnm ((C_ADDI + ((nzi, rsd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1361_ + _s825_) >>= fun w__132 : option (mword 11) => + (if + ((match w__132 with + | Some + (imm) => + true + | _ => + false + end)) + then + (_s1361_ + _s825_) >>= fun w__133 : option (mword 11) => + (match w__133 with + | Some + (imm) => + returnm ((C_JAL + (imm)) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1369_ + _s825_) >>= fun w__136 : option ((mword 5 * mword 6)) => + (if + ((match w__136 with + | Some + (rsd,imm) => + true + | _ => + false + end)) + then + (_s1369_ + _s825_) >>= fun w__137 : option ((mword 5 * mword 6)) => + (match w__137 with + | Some + (rsd,imm) => + returnm ((C_ADDIW + ((imm, rsd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1381_ + _s825_) >>= fun w__140 : option ((mword 5 * mword 6)) => + (if + ((match w__140 with + | Some + (rd,imm) => + neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s1381_ + _s825_) >>= fun w__141 : option ((mword 5 * mword 6)) => + (match w__141 with + | Some + (rd,imm) => + returnm ((C_LI + ((imm, rd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1393_ + _s825_) >>= fun w__144 : option (mword 6) => + (if + ((match w__144 with + | Some + (imm) => + neq_vec + imm + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6) + | _ => + false + end)) + then + (_s1393_ + _s825_) >>= fun w__145 : option (mword 6) => + (match w__145 with + | Some + (imm) => + returnm ((C_ADDI16SP + (imm)) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1401_ + _s825_) >>= fun w__148 : option ((mword 5 * mword 6)) => + (if + ((match w__148 with + | Some + (rd,imm) => + andb + (neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg))) + (andb + (neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + sp))) + (neq_vec + imm + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6))) + | _ => + false + end)) + then + (_s1401_ + _s825_) >>= fun w__149 : option ((mword 5 * mword 6)) => + (match w__149 with + | Some + (rd,imm) => + returnm ((C_LUI + ((imm, rd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1413_ + _s825_) >>= fun w__152 : option ((mword 3 * mword 6)) => + (if + ((match w__152 with + | Some + (rsd,shamt) => + neq_vec + shamt + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6) + | _ => + false + end)) + then + (_s1413_ + _s825_) >>= fun w__153 : option ((mword 3 * mword 6)) => + (match w__153 with + | Some + (rsd,shamt) => + returnm ((C_SRLI + ((shamt, rsd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1425_ + _s825_) >>= fun w__156 : option ((mword 3 * mword 6)) => + (if + ((match w__156 with + | Some + (rsd,shamt) => + neq_vec + shamt + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6) + | _ => + false + end)) + then + (_s1425_ + _s825_) >>= fun w__157 : option ((mword 3 * mword 6)) => + (match w__157 with + | Some + (rsd,shamt) => + returnm ((C_SRAI + ((shamt, rsd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1437_ + _s825_) >>= fun w__160 : option ((mword 3 * mword 6)) => + (if + ((match w__160 with + | Some + (rsd,imm) => + true + | _ => + false + end)) + then + (_s1437_ + _s825_) >>= fun w__161 : option ((mword 3 * mword 6)) => + (match w__161 with + | Some + (rsd,imm) => + returnm ((C_ANDI + ((imm, rsd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1449_ + _s825_) >>= fun w__164 : option ((mword 3 * mword 3)) => + (if + ((match w__164 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s1449_ + _s825_) >>= fun w__165 : option ((mword 3 * mword 3)) => + (match w__165 with + | Some + (rsd,rs2) => + returnm ((C_SUB + ((rsd, rs2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1461_ + _s825_) >>= fun w__168 : option ((mword 3 * mword 3)) => + (if + ((match w__168 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s1461_ + _s825_) >>= fun w__169 : option ((mword 3 * mword 3)) => + (match w__169 with + | Some + (rsd,rs2) => + returnm ((C_XOR + ((rsd, rs2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1473_ + _s825_) >>= fun w__172 : option ((mword 3 * mword 3)) => + (if + ((match w__172 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s1473_ + _s825_) >>= fun w__173 : option ((mword 3 * mword 3)) => + (match w__173 with + | Some + (rsd,rs2) => + returnm ((C_OR + ((rsd, rs2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1485_ + _s825_) >>= fun w__176 : option ((mword 3 * mword 3)) => + (if + ((match w__176 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s1485_ + _s825_) >>= fun w__177 : option ((mword 3 * mword 3)) => + (match w__177 with + | Some + (rsd,rs2) => + returnm ((C_AND + ((rsd, rs2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1497_ + _s825_) >>= fun w__180 : option ((mword 3 * mword 3)) => + (if + ((match w__180 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s1497_ + _s825_) >>= fun w__181 : option ((mword 3 * mword 3)) => + (match w__181 with + | Some + (rsd,rs2) => + returnm ((C_SUBW + ((rsd, rs2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1509_ + _s825_) >>= fun w__184 : option ((mword 3 * mword 3)) => + (if + ((match w__184 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s1509_ + _s825_) >>= fun w__185 : option ((mword 3 * mword 3)) => + (match w__185 with + | Some + (rsd,rs2) => + returnm ((C_ADDW + ((rsd, rs2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1521_ + _s825_) >>= fun w__188 : option (mword 11) => + (if + ((match w__188 with + | Some + (imm) => + true + | _ => + false + end)) + then + (_s1521_ + _s825_) >>= fun w__189 : option (mword 11) => + (match w__189 with + | Some + (imm) => + returnm ((C_J + (imm)) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1529_ + _s825_) >>= fun w__192 : option ((mword 3 * mword 8)) => + (if + ((match w__192 with + | Some + (rs,imm) => + true + | _ => + false + end)) + then + (_s1529_ + _s825_) >>= fun w__193 : option ((mword 3 * mword 8)) => + (match w__193 with + | Some + (rs,imm) => + returnm ((C_BEQZ + ((imm, rs))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1541_ + _s825_) >>= fun w__196 : option ((mword 3 * mword 8)) => + (if + ((match w__196 with + | Some + (rs,imm) => + true + | _ => + false + end)) + then + (_s1541_ + _s825_) >>= fun w__197 : option ((mword 3 * mword 8)) => + (match w__197 with + | Some + (rs,imm) => + returnm ((C_BNEZ + ((imm, rs))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1553_ + _s825_) >>= fun w__200 : option ((mword 5 * mword 6)) => + (if + ((match w__200 with + | Some + (rsd,shamt) => + andb + (neq_vec + shamt + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6)) + (neq_int + (projT1 (regbits_to_regno + rsd)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s1553_ + _s825_) >>= fun w__201 : option ((mword 5 * mword 6)) => + (match w__201 with + | Some + (rsd,shamt) => + returnm ((C_SLLI + ((shamt, rsd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1565_ + _s825_) >>= fun w__204 : option ((mword 5 * mword 6)) => + (if + ((match w__204 with + | Some + (rd,uimm) => + neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s1565_ + _s825_) >>= fun w__205 : option ((mword 5 * mword 6)) => + (match w__205 with + | Some + (rd,uimm) => + returnm ((C_LWSP + ((uimm, rd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1577_ + _s825_) >>= fun w__208 : option ((mword 5 * mword 6)) => + (if + ((match w__208 with + | Some + (rd,uimm) => + neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s1577_ + _s825_) >>= fun w__209 : option ((mword 5 * mword 6)) => + (match w__209 with + | Some + (rd,uimm) => + returnm ((C_LDSP + ((uimm, rd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1589_ + _s825_) >>= fun w__212 : option ((mword 5 * mword 6)) => + (if + ((match w__212 with + | Some + (rd,uimm) => + true + | _ => + false + end)) + then + (_s1589_ + _s825_) >>= fun w__213 : option ((mword 5 * mword 6)) => + (match w__213 with + | Some + (rd,uimm) => + returnm ((C_SWSP + ((uimm, rd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1601_ + _s825_) >>= fun w__216 : option ((mword 5 * mword 6)) => + (if + ((match w__216 with + | Some + (rs2,uimm) => + true + | _ => + false + end)) + then + (_s1601_ + _s825_) >>= fun w__217 : option ((mword 5 * mword 6)) => + (match w__217 with + | Some + (rs2,uimm) => + returnm ((C_SDSP + ((uimm, rs2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1613_ + _s825_) >>= fun w__220 : option (mword 5) => + (if + ((match w__220 with + | Some + (rs1) => + neq_int + (projT1 (regbits_to_regno + rs1)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s1613_ + _s825_) >>= fun w__221 : option (mword 5) => + (match w__221 with + | Some + (rs1) => + returnm ((C_JR + (rs1)) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1621_ + _s825_) >>= fun w__224 : option (mword 5) => + (if + ((match w__224 with + | Some + (rs1) => + neq_int + (projT1 (regbits_to_regno + rs1)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s1621_ + _s825_) >>= fun w__225 : option (mword 5) => + (match w__225 with + | Some + (rs1) => + returnm ((C_JALR + (rs1)) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1629_ + _s825_) >>= fun w__228 : option ((mword 5 * mword 5)) => + (if + ((match w__228 with + | Some + (rd,rs2) => + andb + (neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg))) + (neq_int + (projT1 (regbits_to_regno + rs2)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s1629_ + _s825_) >>= fun w__229 : option ((mword 5 * mword 5)) => + (match w__229 with + | Some + (rd,rs2) => + returnm ((C_MV + ((rd, rs2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else if + ((generic_eq + _s825_ + "c.ebreak")) + then + returnm ((C_EBREAK + (tt)) + : ast ) + else + (_s1641_ + _s825_) >>= fun w__232 : option ((mword 5 * mword 5)) => + (if + ((match w__232 with + | Some + (rsd,rs2) => + andb + (neq_int + (projT1 (regbits_to_regno + rsd)) + (projT1 (regbits_to_regno + zreg))) + (neq_int + (projT1 (regbits_to_regno + rs2)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s1641_ + _s825_) >>= fun w__233 : option ((mword 5 * mword 5)) => + (match w__233 with + | Some + (rsd,rs2) => + returnm ((C_ADD + ((rsd, rs2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else if + ((generic_eq + _s825_ + "stop_fetching")) + then + returnm ((STOP_FETCHING + (tt)) + : ast ) + else if + ((generic_eq + _s825_ + "thread_start")) + then + returnm ((THREAD_START + (tt)) + : ast ) + else + (_s1653_ + _s825_) >>= fun w__236 : option (mword 32) => + (if + ((match w__236 with + | Some + (s) => + true + | _ => + false + end)) + then + (_s1653_ + _s825_) >>= fun w__237 : option (mword 32) => + (match w__237 with + | Some + (s) => + returnm ((ILLEGAL + (s)) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1661_ + _s825_) >>= fun w__240 : option (mword 16) => + (match w__240 with + | Some + (s) => + returnm ((C_ILLEGAL + (s)) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast). + +Definition assembly_forwards_matches (arg_ : ast) +: bool := + + match arg_ with + | UTYPE (imm,rd,op) => true + | RISCV_JAL (imm,rd) => true + | RISCV_JALR (imm,rs1,rd) => true + | BTYPE (imm,rs2,rs1,op) => true + | ITYPE (imm,rs1,rd,op) => true + | SHIFTIOP (shamt,rs1,rd,op) => true + | RTYPE (rs2,rs1,rd,op) => true + | LOAD (imm,rs1,rd,is_unsigned,size,aq,rl) => true + | STORE (imm,rs1,rd,size,aq,rl) => true + | ADDIW (imm,rs1,rd) => true + | SHIFTW (shamt,rs1,rd,op) => true + | RTYPEW (rs2,rs1,rd,op) => true + | SHIFTIWOP (shamt,rs1,rd,op) => true + | MUL (rs2,rs1,rd,high,signed1,signed2) => true + | DIV (rs2,rs1,rd,s) => true + | REM (rs2,rs1,rd,s) => true + | MULW (rs2,rs1,rd) => true + | DIVW (rs2,rs1,rd,s) => true + | REMW (rs2,rs1,rd,s) => true + | FENCE (pred,succ) => true + | FENCE_TSO (pred,succ) => true + | FENCEI (tt) => true + | ECALL (tt) => true + | MRET (tt) => true + | SRET (tt) => true + | EBREAK (tt) => true + | WFI (tt) => true + | SFENCE_VMA (rs1,rs2) => true + | LOADRES (aq,rl,rs1,size,rd) => true + | STORECON (aq,rl,rs2,rs1,size,rd) => true + | AMO (op,aq,rl,rs2,rs1,width,rd) => true + | CSR (csr,rs1,rd,true,op) => true + | CSR (csr,rs1,rd,false,op) => true + | C_NOP (tt) => true + | C_ADDI4SPN (rdc,nzimm) => + if ((neq_vec nzimm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8))) then true + else + let g__28 := C_ADDI4SPN ((rdc, nzimm)) in + false + | C_LW (uimm,rsc,rdc) => true + | C_LD (uimm,rsc,rdc) => true + | C_SW (uimm,rsc1,rsc2) => true + | C_SD (uimm,rsc1,rsc2) => true + | C_ADDI (nzi,rsd) => + if ((andb (neq_vec nzi (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg))))) then + true + else + let g__28 := C_ADDI ((nzi, rsd)) in + false + | C_JAL (imm) => true + | C_ADDIW (imm,rsd) => true + | C_LI (imm,rd) => + if ((neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__28 := C_LI ((imm, rd)) in + false + | C_ADDI16SP (imm) => + if ((neq_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then true + else + let g__28 := C_ADDI16SP (imm) in + false + | C_LUI (imm,rd) => + if ((andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno sp))) + (neq_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))))) then + true + else + let g__28 := C_LUI ((imm, rd)) in + false + | C_SRLI (shamt,rsd) => + if ((neq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then true + else + let g__28 := C_SRLI ((shamt, rsd)) in + false + | C_SRAI (shamt,rsd) => + if ((neq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then true + else + let g__28 := C_SRAI ((shamt, rsd)) in + false + | C_ANDI (imm,rsd) => true + | C_SUB (rsd,rs2) => true + | C_XOR (rsd,rs2) => true + | C_OR (rsd,rs2) => true + | C_AND (rsd,rs2) => true + | C_SUBW (rsd,rs2) => true + | C_ADDW (rsd,rs2) => true + | C_J (imm) => true + | C_BEQZ (imm,rs) => true + | C_BNEZ (imm,rs) => true + | C_SLLI (shamt,rsd) => + if ((andb (neq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg))))) then + true + else + let g__28 := C_SLLI ((shamt, rsd)) in + false + | C_LWSP (uimm,rd) => + if ((neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__28 := C_LWSP ((uimm, rd)) in + false + | C_LDSP (uimm,rd) => + if ((neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__28 := C_LDSP ((uimm, rd)) in + false + | C_SWSP (uimm,rd) => true + | C_SDSP (uimm,rs2) => true + | C_JR (rs1) => + if ((neq_int (projT1 (regbits_to_regno rs1)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__28 := C_JR (rs1) in + false + | C_JALR (rs1) => + if ((neq_int (projT1 (regbits_to_regno rs1)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__28 := C_JALR (rs1) in + false + | C_MV (rd,rs2) => + if ((andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (neq_int (projT1 (regbits_to_regno rs2)) (projT1 (regbits_to_regno zreg))))) then + true + else + let g__28 := C_MV ((rd, rs2)) in + false + | C_EBREAK (tt) => true + | C_ADD (rsd,rs2) => + if ((andb (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg))) + (neq_int (projT1 (regbits_to_regno rs2)) (projT1 (regbits_to_regno zreg))))) then + true + else + let g__28 := C_ADD ((rsd, rs2)) in + false + | STOP_FETCHING (tt) => true + | THREAD_START (tt) => true + | ILLEGAL (s) => true + | C_ILLEGAL (s) => true + end. + +Definition _s2517_ (_s2518_ : string) +: M (option (mword 16)) := + + let _s2519_ := _s2518_ in + (if ((string_startswith _s2519_ "c.illegal")) then + (match (string_drop _s2519_ (projT1 (string_length "c.illegal"))) with + | _s2520_ => + (spc_matches_prefix _s2520_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s2521_ _)) => + match (string_drop _s2520_ _s2521_) with + | _s2522_ => + match (hex_bits_16_matches_prefix _s2522_) with + | Some (s,(existT _ _s2523_ _)) => + let p0_ := string_drop _s2522_ _s2523_ in + if ((generic_eq p0_ "")) then Some (s) + else None + | _ => None + end + end + | _ => None + end) + : option (mword 16)) + end) + : M (option (mword 16)) + else returnm (None : option (mword 16))) + : M (option (mword 16)). + +Definition _s2509_ (_s2510_ : string) +: M (option (mword 32)) := + + let _s2511_ := _s2510_ in + (if ((string_startswith _s2511_ "illegal")) then + (match (string_drop _s2511_ (projT1 (string_length "illegal"))) with + | _s2512_ => + (spc_matches_prefix _s2512_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s2513_ _)) => + match (string_drop _s2512_ _s2513_) with + | _s2514_ => + match (hex_bits_32_matches_prefix _s2514_) with + | Some (s,(existT _ _s2515_ _)) => + let p0_ := string_drop _s2514_ _s2515_ in + if ((generic_eq p0_ "")) then Some (s) + else None + | _ => None + end + end + | _ => None + end) + : option (mword 32)) + end) + : M (option (mword 32)) + else returnm (None : option (mword 32))) + : M (option (mword 32)). + +Definition _s2497_ (_s2498_ : string) +: M (option ((mword 5 * mword 5))) := + + let _s2499_ := _s2498_ in + (if ((string_startswith _s2499_ "c.add")) then + (match (string_drop _s2499_ (projT1 (string_length "c.add"))) with + | _s2500_ => + (spc_matches_prefix _s2500_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2501_ _)) => + (match (string_drop _s2500_ _s2501_) with + | _s2502_ => + (reg_name_matches_prefix _s2502_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2503_ _)) => + (match (string_drop _s2502_ _s2503_) with + | _s2504_ => + (sep_matches_prefix _s2504_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2505_ _)) => + (match (string_drop _s2504_ _s2505_) with + | _s2506_ => + (reg_name_matches_prefix _s2506_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s2507_ _)) => + let p0_ := string_drop _s2506_ _s2507_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + else returnm (None : option ((mword 5 * mword 5)))) + : M (option ((mword 5 * mword 5))). + +Definition _s2485_ (_s2486_ : string) +: M (option ((mword 5 * mword 5))) := + + let _s2487_ := _s2486_ in + (if ((string_startswith _s2487_ "c.mv")) then + (match (string_drop _s2487_ (projT1 (string_length "c.mv"))) with + | _s2488_ => + (spc_matches_prefix _s2488_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2489_ _)) => + (match (string_drop _s2488_ _s2489_) with + | _s2490_ => + (reg_name_matches_prefix _s2490_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s2491_ _)) => + (match (string_drop _s2490_ _s2491_) with + | _s2492_ => + (sep_matches_prefix _s2492_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2493_ _)) => + (match (string_drop _s2492_ _s2493_) with + | _s2494_ => + (reg_name_matches_prefix _s2494_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s2495_ _)) => + let p0_ := string_drop _s2494_ _s2495_ in + if ((generic_eq p0_ "")) then Some ((rd, rs2)) + else None + | _ => None + end) + : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + else returnm (None : option ((mword 5 * mword 5)))) + : M (option ((mword 5 * mword 5))). + +Definition _s2477_ (_s2478_ : string) +: M (option (mword 5)) := + + let _s2479_ := _s2478_ in + (if ((string_startswith _s2479_ "c.jalr")) then + (match (string_drop _s2479_ (projT1 (string_length "c.jalr"))) with + | _s2480_ => + (spc_matches_prefix _s2480_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2481_ _)) => + (match (string_drop _s2480_ _s2481_) with + | _s2482_ => + (reg_name_matches_prefix _s2482_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__1 with + | Some (rs1,(existT _ _s2483_ _)) => + let p0_ := string_drop _s2482_ _s2483_ in + if ((generic_eq p0_ "")) then Some (rs1) + else None + | _ => None + end) + : option (mword 5)) + end) + : M (option (mword 5)) + | _ => returnm (None : option (mword 5)) + end) + : M (option (mword 5)) + end) + : M (option (mword 5)) + else returnm (None : option (mword 5))) + : M (option (mword 5)). + +Definition _s2469_ (_s2470_ : string) +: M (option (mword 5)) := + + let _s2471_ := _s2470_ in + (if ((string_startswith _s2471_ "c.jr")) then + (match (string_drop _s2471_ (projT1 (string_length "c.jr"))) with + | _s2472_ => + (spc_matches_prefix _s2472_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2473_ _)) => + (match (string_drop _s2472_ _s2473_) with + | _s2474_ => + (reg_name_matches_prefix _s2474_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__1 with + | Some (rs1,(existT _ _s2475_ _)) => + let p0_ := string_drop _s2474_ _s2475_ in + if ((generic_eq p0_ "")) then Some (rs1) + else None + | _ => None + end) + : option (mword 5)) + end) + : M (option (mword 5)) + | _ => returnm (None : option (mword 5)) + end) + : M (option (mword 5)) + end) + : M (option (mword 5)) + else returnm (None : option (mword 5))) + : M (option (mword 5)). + +Definition _s2457_ (_s2458_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s2459_ := _s2458_ in + (if ((string_startswith _s2459_ "c.sdsp")) then + (match (string_drop _s2459_ (projT1 (string_length "c.sdsp"))) with + | _s2460_ => + (spc_matches_prefix _s2460_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2461_ _)) => + (match (string_drop _s2460_ _s2461_) with + | _s2462_ => + (reg_name_matches_prefix _s2462_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs2,(existT _ _s2463_ _)) => + (match (string_drop _s2462_ _s2463_) with + | _s2464_ => + (sep_matches_prefix _s2464_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2465_ _)) => + match (string_drop _s2464_ _s2465_) with + | _s2466_ => + match (hex_bits_6_matches_prefix _s2466_) with + | Some (uimm,(existT _ _s2467_ _)) => + let p0_ := string_drop _s2466_ _s2467_ in + if ((generic_eq p0_ "")) then Some ((rs2, uimm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s2445_ (_s2446_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s2447_ := _s2446_ in + (if ((string_startswith _s2447_ "c.swsp")) then + (match (string_drop _s2447_ (projT1 (string_length "c.swsp"))) with + | _s2448_ => + (spc_matches_prefix _s2448_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2449_ _)) => + (match (string_drop _s2448_ _s2449_) with + | _s2450_ => + (reg_name_matches_prefix _s2450_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s2451_ _)) => + (match (string_drop _s2450_ _s2451_) with + | _s2452_ => + (sep_matches_prefix _s2452_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2453_ _)) => + match (string_drop _s2452_ _s2453_) with + | _s2454_ => + match (hex_bits_6_matches_prefix _s2454_) with + | Some (uimm,(existT _ _s2455_ _)) => + let p0_ := string_drop _s2454_ _s2455_ in + if ((generic_eq p0_ "")) then Some ((rd, uimm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s2433_ (_s2434_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s2435_ := _s2434_ in + (if ((string_startswith _s2435_ "c.ldsp")) then + (match (string_drop _s2435_ (projT1 (string_length "c.ldsp"))) with + | _s2436_ => + (spc_matches_prefix _s2436_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2437_ _)) => + (match (string_drop _s2436_ _s2437_) with + | _s2438_ => + (reg_name_matches_prefix _s2438_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s2439_ _)) => + (match (string_drop _s2438_ _s2439_) with + | _s2440_ => + (sep_matches_prefix _s2440_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2441_ _)) => + match (string_drop _s2440_ _s2441_) with + | _s2442_ => + match (hex_bits_6_matches_prefix _s2442_) with + | Some (uimm,(existT _ _s2443_ _)) => + let p0_ := string_drop _s2442_ _s2443_ in + if ((generic_eq p0_ "")) then Some ((rd, uimm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s2421_ (_s2422_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s2423_ := _s2422_ in + (if ((string_startswith _s2423_ "c.lwsp")) then + (match (string_drop _s2423_ (projT1 (string_length "c.lwsp"))) with + | _s2424_ => + (spc_matches_prefix _s2424_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2425_ _)) => + (match (string_drop _s2424_ _s2425_) with + | _s2426_ => + (reg_name_matches_prefix _s2426_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s2427_ _)) => + (match (string_drop _s2426_ _s2427_) with + | _s2428_ => + (sep_matches_prefix _s2428_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2429_ _)) => + match (string_drop _s2428_ _s2429_) with + | _s2430_ => + match (hex_bits_6_matches_prefix _s2430_) with + | Some (uimm,(existT _ _s2431_ _)) => + let p0_ := string_drop _s2430_ _s2431_ in + if ((generic_eq p0_ "")) then Some ((rd, uimm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s2409_ (_s2410_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s2411_ := _s2410_ in + (if ((string_startswith _s2411_ "c.slli")) then + (match (string_drop _s2411_ (projT1 (string_length "c.slli"))) with + | _s2412_ => + (spc_matches_prefix _s2412_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2413_ _)) => + (match (string_drop _s2412_ _s2413_) with + | _s2414_ => + (reg_name_matches_prefix _s2414_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2415_ _)) => + (match (string_drop _s2414_ _s2415_) with + | _s2416_ => + (sep_matches_prefix _s2416_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2417_ _)) => + match (string_drop _s2416_ _s2417_) with + | _s2418_ => + match (hex_bits_6_matches_prefix _s2418_) with + | Some (shamt,(existT _ _s2419_ _)) => + let p0_ := string_drop _s2418_ _s2419_ in + if ((generic_eq p0_ "")) then Some ((rsd, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s2397_ (_s2398_ : string) +: M (option ((mword 3 * mword 8))) := + + let _s2399_ := _s2398_ in + (if ((string_startswith _s2399_ "c.bnez")) then + (match (string_drop _s2399_ (projT1 (string_length "c.bnez"))) with + | _s2400_ => + (spc_matches_prefix _s2400_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2401_ _)) => + (match (string_drop _s2400_ _s2401_) with + | _s2402_ => + (creg_name_matches_prefix _s2402_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs,(existT _ _s2403_ _)) => + (match (string_drop _s2402_ _s2403_) with + | _s2404_ => + (sep_matches_prefix _s2404_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2405_ _)) => + match (string_drop _s2404_ _s2405_) with + | _s2406_ => + match (hex_bits_8_matches_prefix _s2406_) with + | Some (imm,(existT _ _s2407_ _)) => + let p0_ := string_drop _s2406_ _s2407_ in + if ((generic_eq p0_ "")) then Some ((rs, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + else returnm (None : option ((mword 3 * mword 8)))) + : M (option ((mword 3 * mword 8))). + +Definition _s2385_ (_s2386_ : string) +: M (option ((mword 3 * mword 8))) := + + let _s2387_ := _s2386_ in + (if ((string_startswith _s2387_ "c.beqz")) then + (match (string_drop _s2387_ (projT1 (string_length "c.beqz"))) with + | _s2388_ => + (spc_matches_prefix _s2388_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2389_ _)) => + (match (string_drop _s2388_ _s2389_) with + | _s2390_ => + (creg_name_matches_prefix _s2390_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs,(existT _ _s2391_ _)) => + (match (string_drop _s2390_ _s2391_) with + | _s2392_ => + (sep_matches_prefix _s2392_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2393_ _)) => + match (string_drop _s2392_ _s2393_) with + | _s2394_ => + match (hex_bits_8_matches_prefix _s2394_) with + | Some (imm,(existT _ _s2395_ _)) => + let p0_ := string_drop _s2394_ _s2395_ in + if ((generic_eq p0_ "")) then Some ((rs, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + else returnm (None : option ((mword 3 * mword 8)))) + : M (option ((mword 3 * mword 8))). + +Definition _s2377_ (_s2378_ : string) +: M (option (mword 11)) := + + let _s2379_ := _s2378_ in + (if ((string_startswith _s2379_ "c.j")) then + (match (string_drop _s2379_ (projT1 (string_length "c.j"))) with + | _s2380_ => + (spc_matches_prefix _s2380_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s2381_ _)) => + match (string_drop _s2380_ _s2381_) with + | _s2382_ => + match (hex_bits_11_matches_prefix _s2382_) with + | Some (imm,(existT _ _s2383_ _)) => + let p0_ := string_drop _s2382_ _s2383_ in + if ((generic_eq p0_ "")) then Some (imm) + else None + | _ => None + end + end + | _ => None + end) + : option (mword 11)) + end) + : M (option (mword 11)) + else returnm (None : option (mword 11))) + : M (option (mword 11)). + +Definition _s2365_ (_s2366_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s2367_ := _s2366_ in + (if ((string_startswith _s2367_ "c.addw")) then + (match (string_drop _s2367_ (projT1 (string_length "c.addw"))) with + | _s2368_ => + (spc_matches_prefix _s2368_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2369_ _)) => + (match (string_drop _s2368_ _s2369_) with + | _s2370_ => + (creg_name_matches_prefix _s2370_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2371_ _)) => + (match (string_drop _s2370_ _s2371_) with + | _s2372_ => + (sep_matches_prefix _s2372_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2373_ _)) => + (match (string_drop _s2372_ _s2373_) with + | _s2374_ => + (creg_name_matches_prefix _s2374_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s2375_ _)) => + let p0_ := string_drop _s2374_ _s2375_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s2353_ (_s2354_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s2355_ := _s2354_ in + (if ((string_startswith _s2355_ "c.subw")) then + (match (string_drop _s2355_ (projT1 (string_length "c.subw"))) with + | _s2356_ => + (spc_matches_prefix _s2356_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2357_ _)) => + (match (string_drop _s2356_ _s2357_) with + | _s2358_ => + (creg_name_matches_prefix _s2358_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2359_ _)) => + (match (string_drop _s2358_ _s2359_) with + | _s2360_ => + (sep_matches_prefix _s2360_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2361_ _)) => + (match (string_drop _s2360_ _s2361_) with + | _s2362_ => + (creg_name_matches_prefix _s2362_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s2363_ _)) => + let p0_ := string_drop _s2362_ _s2363_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s2341_ (_s2342_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s2343_ := _s2342_ in + (if ((string_startswith _s2343_ "c.and")) then + (match (string_drop _s2343_ (projT1 (string_length "c.and"))) with + | _s2344_ => + (spc_matches_prefix _s2344_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2345_ _)) => + (match (string_drop _s2344_ _s2345_) with + | _s2346_ => + (creg_name_matches_prefix _s2346_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2347_ _)) => + (match (string_drop _s2346_ _s2347_) with + | _s2348_ => + (sep_matches_prefix _s2348_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2349_ _)) => + (match (string_drop _s2348_ _s2349_) with + | _s2350_ => + (creg_name_matches_prefix _s2350_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s2351_ _)) => + let p0_ := string_drop _s2350_ _s2351_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s2329_ (_s2330_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s2331_ := _s2330_ in + (if ((string_startswith _s2331_ "c.or")) then + (match (string_drop _s2331_ (projT1 (string_length "c.or"))) with + | _s2332_ => + (spc_matches_prefix _s2332_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2333_ _)) => + (match (string_drop _s2332_ _s2333_) with + | _s2334_ => + (creg_name_matches_prefix _s2334_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2335_ _)) => + (match (string_drop _s2334_ _s2335_) with + | _s2336_ => + (sep_matches_prefix _s2336_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2337_ _)) => + (match (string_drop _s2336_ _s2337_) with + | _s2338_ => + (creg_name_matches_prefix _s2338_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s2339_ _)) => + let p0_ := string_drop _s2338_ _s2339_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s2317_ (_s2318_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s2319_ := _s2318_ in + (if ((string_startswith _s2319_ "c.xor")) then + (match (string_drop _s2319_ (projT1 (string_length "c.xor"))) with + | _s2320_ => + (spc_matches_prefix _s2320_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2321_ _)) => + (match (string_drop _s2320_ _s2321_) with + | _s2322_ => + (creg_name_matches_prefix _s2322_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2323_ _)) => + (match (string_drop _s2322_ _s2323_) with + | _s2324_ => + (sep_matches_prefix _s2324_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2325_ _)) => + (match (string_drop _s2324_ _s2325_) with + | _s2326_ => + (creg_name_matches_prefix _s2326_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s2327_ _)) => + let p0_ := string_drop _s2326_ _s2327_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s2305_ (_s2306_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s2307_ := _s2306_ in + (if ((string_startswith _s2307_ "c.sub")) then + (match (string_drop _s2307_ (projT1 (string_length "c.sub"))) with + | _s2308_ => + (spc_matches_prefix _s2308_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2309_ _)) => + (match (string_drop _s2308_ _s2309_) with + | _s2310_ => + (creg_name_matches_prefix _s2310_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2311_ _)) => + (match (string_drop _s2310_ _s2311_) with + | _s2312_ => + (sep_matches_prefix _s2312_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2313_ _)) => + (match (string_drop _s2312_ _s2313_) with + | _s2314_ => + (creg_name_matches_prefix _s2314_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s2315_ _)) => + let p0_ := string_drop _s2314_ _s2315_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s2293_ (_s2294_ : string) +: M (option ((mword 3 * mword 6))) := + + let _s2295_ := _s2294_ in + (if ((string_startswith _s2295_ "c.andi")) then + (match (string_drop _s2295_ (projT1 (string_length "c.andi"))) with + | _s2296_ => + (spc_matches_prefix _s2296_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2297_ _)) => + (match (string_drop _s2296_ _s2297_) with + | _s2298_ => + (creg_name_matches_prefix _s2298_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2299_ _)) => + (match (string_drop _s2298_ _s2299_) with + | _s2300_ => + (sep_matches_prefix _s2300_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2301_ _)) => + match (string_drop _s2300_ _s2301_) with + | _s2302_ => + match (hex_bits_6_matches_prefix _s2302_) with + | Some (imm,(existT _ _s2303_ _)) => + let p0_ := string_drop _s2302_ _s2303_ in + if ((generic_eq p0_ "")) then Some ((rsd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + else returnm (None : option ((mword 3 * mword 6)))) + : M (option ((mword 3 * mword 6))). + +Definition _s2281_ (_s2282_ : string) +: M (option ((mword 3 * mword 6))) := + + let _s2283_ := _s2282_ in + (if ((string_startswith _s2283_ "c.srai")) then + (match (string_drop _s2283_ (projT1 (string_length "c.srai"))) with + | _s2284_ => + (spc_matches_prefix _s2284_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2285_ _)) => + (match (string_drop _s2284_ _s2285_) with + | _s2286_ => + (creg_name_matches_prefix _s2286_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2287_ _)) => + (match (string_drop _s2286_ _s2287_) with + | _s2288_ => + (sep_matches_prefix _s2288_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2289_ _)) => + match (string_drop _s2288_ _s2289_) with + | _s2290_ => + match (hex_bits_6_matches_prefix _s2290_) with + | Some (shamt,(existT _ _s2291_ _)) => + let p0_ := string_drop _s2290_ _s2291_ in + if ((generic_eq p0_ "")) then Some ((rsd, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + else returnm (None : option ((mword 3 * mword 6)))) + : M (option ((mword 3 * mword 6))). + +Definition _s2269_ (_s2270_ : string) +: M (option ((mword 3 * mword 6))) := + + let _s2271_ := _s2270_ in + (if ((string_startswith _s2271_ "c.srli")) then + (match (string_drop _s2271_ (projT1 (string_length "c.srli"))) with + | _s2272_ => + (spc_matches_prefix _s2272_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2273_ _)) => + (match (string_drop _s2272_ _s2273_) with + | _s2274_ => + (creg_name_matches_prefix _s2274_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2275_ _)) => + (match (string_drop _s2274_ _s2275_) with + | _s2276_ => + (sep_matches_prefix _s2276_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2277_ _)) => + match (string_drop _s2276_ _s2277_) with + | _s2278_ => + match (hex_bits_6_matches_prefix _s2278_) with + | Some (shamt,(existT _ _s2279_ _)) => + let p0_ := string_drop _s2278_ _s2279_ in + if ((generic_eq p0_ "")) then Some ((rsd, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + else returnm (None : option ((mword 3 * mword 6)))) + : M (option ((mword 3 * mword 6))). + +Definition _s2257_ (_s2258_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s2259_ := _s2258_ in + (if ((string_startswith _s2259_ "c.lui")) then + (match (string_drop _s2259_ (projT1 (string_length "c.lui"))) with + | _s2260_ => + (spc_matches_prefix _s2260_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2261_ _)) => + (match (string_drop _s2260_ _s2261_) with + | _s2262_ => + (reg_name_matches_prefix _s2262_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s2263_ _)) => + (match (string_drop _s2262_ _s2263_) with + | _s2264_ => + (sep_matches_prefix _s2264_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2265_ _)) => + match (string_drop _s2264_ _s2265_) with + | _s2266_ => + match (hex_bits_6_matches_prefix _s2266_) with + | Some (imm,(existT _ _s2267_ _)) => + let p0_ := string_drop _s2266_ _s2267_ in + if ((generic_eq p0_ "")) then Some ((rd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s2249_ (_s2250_ : string) +: M (option (mword 6)) := + + let _s2251_ := _s2250_ in + (if ((string_startswith _s2251_ "c.addi16sp")) then + (match (string_drop _s2251_ (projT1 (string_length "c.addi16sp"))) with + | _s2252_ => + (spc_matches_prefix _s2252_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s2253_ _)) => + match (string_drop _s2252_ _s2253_) with + | _s2254_ => + match (hex_bits_6_matches_prefix _s2254_) with + | Some (imm,(existT _ _s2255_ _)) => + let p0_ := string_drop _s2254_ _s2255_ in + if ((generic_eq p0_ "")) then Some (imm) + else None + | _ => None + end + end + | _ => None + end) + : option (mword 6)) + end) + : M (option (mword 6)) + else returnm (None : option (mword 6))) + : M (option (mword 6)). + +Definition _s2237_ (_s2238_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s2239_ := _s2238_ in + (if ((string_startswith _s2239_ "c.li")) then + (match (string_drop _s2239_ (projT1 (string_length "c.li"))) with + | _s2240_ => + (spc_matches_prefix _s2240_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2241_ _)) => + (match (string_drop _s2240_ _s2241_) with + | _s2242_ => + (reg_name_matches_prefix _s2242_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s2243_ _)) => + (match (string_drop _s2242_ _s2243_) with + | _s2244_ => + (sep_matches_prefix _s2244_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2245_ _)) => + match (string_drop _s2244_ _s2245_) with + | _s2246_ => + match (hex_bits_6_matches_prefix _s2246_) with + | Some (imm,(existT _ _s2247_ _)) => + let p0_ := string_drop _s2246_ _s2247_ in + if ((generic_eq p0_ "")) then Some ((rd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s2225_ (_s2226_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s2227_ := _s2226_ in + (if ((string_startswith _s2227_ "c.addiw")) then + (match (string_drop _s2227_ (projT1 (string_length "c.addiw"))) with + | _s2228_ => + (spc_matches_prefix _s2228_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2229_ _)) => + (match (string_drop _s2228_ _s2229_) with + | _s2230_ => + (reg_name_matches_prefix _s2230_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2231_ _)) => + (match (string_drop _s2230_ _s2231_) with + | _s2232_ => + (sep_matches_prefix _s2232_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2233_ _)) => + match (string_drop _s2232_ _s2233_) with + | _s2234_ => + match (hex_bits_6_matches_prefix _s2234_) with + | Some (imm,(existT _ _s2235_ _)) => + let p0_ := string_drop _s2234_ _s2235_ in + if ((generic_eq p0_ "")) then Some ((rsd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s2217_ (_s2218_ : string) +: M (option (mword 11)) := + + let _s2219_ := _s2218_ in + (if ((string_startswith _s2219_ "c.jal")) then + (match (string_drop _s2219_ (projT1 (string_length "c.jal"))) with + | _s2220_ => + (spc_matches_prefix _s2220_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s2221_ _)) => + match (string_drop _s2220_ _s2221_) with + | _s2222_ => + match (hex_bits_12_matches_prefix _s2222_) with + | Some (v__772,(existT _ _s2223_ _)) => + if ((eq_vec (subrange_vec_dec v__772 0 0) + (vec_of_bits [B0] : mword (0 - 0 + 1)))) then + let imm : mword 11 := subrange_vec_dec v__772 11 1 in + let imm : mword 11 := subrange_vec_dec v__772 11 1 in + let p0_ := string_drop _s2222_ _s2223_ in + if ((generic_eq p0_ "")) then Some (imm) + else None + else + let g__27 := Some ((v__772, _s2223_)) in + None + | g__27 => None + end + end + | _ => None + end) + : option (mword 11)) + end) + : M (option (mword 11)) + else returnm (None : option (mword 11))) + : M (option (mword 11)). + +Definition _s2205_ (_s2206_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s2207_ := _s2206_ in + (if ((string_startswith _s2207_ "c.addi")) then + (match (string_drop _s2207_ (projT1 (string_length "c.addi"))) with + | _s2208_ => + (spc_matches_prefix _s2208_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2209_ _)) => + (match (string_drop _s2208_ _s2209_) with + | _s2210_ => + (reg_name_matches_prefix _s2210_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2211_ _)) => + (match (string_drop _s2210_ _s2211_) with + | _s2212_ => + (sep_matches_prefix _s2212_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2213_ _)) => + match (string_drop _s2212_ _s2213_) with + | _s2214_ => + match (hex_bits_6_matches_prefix _s2214_) with + | Some (nzi,(existT _ _s2215_ _)) => + let p0_ := string_drop _s2214_ _s2215_ in + if ((generic_eq p0_ "")) then Some ((rsd, nzi)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s2189_ (_s2190_ : string) +: M (option ((mword 3 * mword 3 * mword 5))) := + + let _s2191_ := _s2190_ in + (if ((string_startswith _s2191_ "c.sd")) then + (match (string_drop _s2191_ (projT1 (string_length "c.sd"))) with + | _s2192_ => + (spc_matches_prefix _s2192_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2193_ _)) => + (match (string_drop _s2192_ _s2193_) with + | _s2194_ => + (creg_name_matches_prefix _s2194_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsc1,(existT _ _s2195_ _)) => + (match (string_drop _s2194_ _s2195_) with + | _s2196_ => + (sep_matches_prefix _s2196_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2197_ _)) => + (match (string_drop _s2196_ _s2197_) with + | _s2198_ => + (creg_name_matches_prefix _s2198_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc2,(existT _ _s2199_ _)) => + (match (string_drop _s2198_ _s2199_) with + | _s2200_ => + (sep_matches_prefix _s2200_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s2201_ _)) => + match (string_drop _s2200_ _s2201_) with + | _s2202_ => + match (hex_bits_8_matches_prefix _s2202_) with + | Some (v__774,(existT _ _s2203_ _)) => + if ((eq_vec + (subrange_vec_dec v__774 2 0) + (vec_of_bits [B0;B0;B0] + : mword (2 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__774 7 3 in + let uimm : mword 5 := + subrange_vec_dec v__774 7 3 in + let p0_ := + string_drop _s2202_ _s2203_ in + if ((generic_eq p0_ "")) then + Some + ((rsc1, rsc2, uimm)) + else None + else + let g__26 := Some ((v__774, _s2203_)) in + None + | g__26 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + else returnm (None : option ((mword 3 * mword 3 * mword 5)))) + : M (option ((mword 3 * mword 3 * mword 5))). + +Definition _s2173_ (_s2174_ : string) +: M (option ((mword 3 * mword 3 * mword 5))) := + + let _s2175_ := _s2174_ in + (if ((string_startswith _s2175_ "c.sw")) then + (match (string_drop _s2175_ (projT1 (string_length "c.sw"))) with + | _s2176_ => + (spc_matches_prefix _s2176_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2177_ _)) => + (match (string_drop _s2176_ _s2177_) with + | _s2178_ => + (creg_name_matches_prefix _s2178_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsc1,(existT _ _s2179_ _)) => + (match (string_drop _s2178_ _s2179_) with + | _s2180_ => + (sep_matches_prefix _s2180_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2181_ _)) => + (match (string_drop _s2180_ _s2181_) with + | _s2182_ => + (creg_name_matches_prefix _s2182_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc2,(existT _ _s2183_ _)) => + (match (string_drop _s2182_ _s2183_) with + | _s2184_ => + (sep_matches_prefix _s2184_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s2185_ _)) => + match (string_drop _s2184_ _s2185_) with + | _s2186_ => + match (hex_bits_7_matches_prefix _s2186_) with + | Some (v__776,(existT _ _s2187_ _)) => + if ((eq_vec + (subrange_vec_dec v__776 1 0) + (vec_of_bits [B0;B0] + : mword (1 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__776 6 2 in + let uimm : mword 5 := + subrange_vec_dec v__776 6 2 in + let p0_ := + string_drop _s2186_ _s2187_ in + if ((generic_eq p0_ "")) then + Some + ((rsc1, rsc2, uimm)) + else None + else + let g__25 := Some ((v__776, _s2187_)) in + None + | g__25 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + else returnm (None : option ((mword 3 * mword 3 * mword 5)))) + : M (option ((mword 3 * mword 3 * mword 5))). + +Definition _s2157_ (_s2158_ : string) +: M (option ((mword 3 * mword 3 * mword 5))) := + + let _s2159_ := _s2158_ in + (if ((string_startswith _s2159_ "c.ld")) then + (match (string_drop _s2159_ (projT1 (string_length "c.ld"))) with + | _s2160_ => + (spc_matches_prefix _s2160_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2161_ _)) => + (match (string_drop _s2160_ _s2161_) with + | _s2162_ => + (creg_name_matches_prefix _s2162_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rdc,(existT _ _s2163_ _)) => + (match (string_drop _s2162_ _s2163_) with + | _s2164_ => + (sep_matches_prefix _s2164_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2165_ _)) => + (match (string_drop _s2164_ _s2165_) with + | _s2166_ => + (creg_name_matches_prefix _s2166_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc,(existT _ _s2167_ _)) => + (match (string_drop _s2166_ _s2167_) with + | _s2168_ => + (sep_matches_prefix _s2168_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s2169_ _)) => + match (string_drop _s2168_ _s2169_) with + | _s2170_ => + match (hex_bits_8_matches_prefix _s2170_) with + | Some (v__778,(existT _ _s2171_ _)) => + if ((eq_vec + (subrange_vec_dec v__778 2 0) + (vec_of_bits [B0;B0;B0] + : mword (2 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__778 7 3 in + let uimm : mword 5 := + subrange_vec_dec v__778 7 3 in + let p0_ := + string_drop _s2170_ _s2171_ in + if ((generic_eq p0_ "")) then + Some + ((rdc, rsc, uimm)) + else None + else + let g__24 := Some ((v__778, _s2171_)) in + None + | g__24 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + else returnm (None : option ((mword 3 * mword 3 * mword 5)))) + : M (option ((mword 3 * mword 3 * mword 5))). + +Definition _s2141_ (_s2142_ : string) +: M (option ((mword 3 * mword 3 * mword 5))) := + + let _s2143_ := _s2142_ in + (if ((string_startswith _s2143_ "c.lw")) then + (match (string_drop _s2143_ (projT1 (string_length "c.lw"))) with + | _s2144_ => + (spc_matches_prefix _s2144_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2145_ _)) => + (match (string_drop _s2144_ _s2145_) with + | _s2146_ => + (creg_name_matches_prefix _s2146_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rdc,(existT _ _s2147_ _)) => + (match (string_drop _s2146_ _s2147_) with + | _s2148_ => + (sep_matches_prefix _s2148_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2149_ _)) => + (match (string_drop _s2148_ _s2149_) with + | _s2150_ => + (creg_name_matches_prefix _s2150_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc,(existT _ _s2151_ _)) => + (match (string_drop _s2150_ _s2151_) with + | _s2152_ => + (sep_matches_prefix _s2152_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s2153_ _)) => + match (string_drop _s2152_ _s2153_) with + | _s2154_ => + match (hex_bits_7_matches_prefix _s2154_) with + | Some (v__780,(existT _ _s2155_ _)) => + if ((eq_vec + (subrange_vec_dec v__780 1 0) + (vec_of_bits [B0;B0] + : mword (1 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__780 6 2 in + let uimm : mword 5 := + subrange_vec_dec v__780 6 2 in + let p0_ := + string_drop _s2154_ _s2155_ in + if ((generic_eq p0_ "")) then + Some + ((rdc, rsc, uimm)) + else None + else + let g__23 := Some ((v__780, _s2155_)) in + None + | g__23 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + else returnm (None : option ((mword 3 * mword 3 * mword 5)))) + : M (option ((mword 3 * mword 3 * mword 5))). + +Definition _s2129_ (_s2130_ : string) +: M (option ((mword 3 * mword 8))) := + + let _s2131_ := _s2130_ in + (if ((string_startswith _s2131_ "c.addi4spn")) then + (match (string_drop _s2131_ (projT1 (string_length "c.addi4spn"))) with + | _s2132_ => + (spc_matches_prefix _s2132_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2133_ _)) => + (match (string_drop _s2132_ _s2133_) with + | _s2134_ => + (creg_name_matches_prefix _s2134_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rdc,(existT _ _s2135_ _)) => + (match (string_drop _s2134_ _s2135_) with + | _s2136_ => + (sep_matches_prefix _s2136_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2137_ _)) => + match (string_drop _s2136_ _s2137_) with + | _s2138_ => + match (hex_bits_10_matches_prefix _s2138_) with + | Some (v__782,(existT _ _s2139_ _)) => + if ((eq_vec (subrange_vec_dec v__782 1 0) + (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) + then + let nzimm : mword 8 := subrange_vec_dec v__782 9 2 in + let nzimm : mword 8 := subrange_vec_dec v__782 9 2 in + let p0_ := string_drop _s2138_ _s2139_ in + if ((generic_eq p0_ "")) then Some ((rdc, nzimm)) + else None + else + let g__22 := Some ((v__782, _s2139_)) in + None + | g__22 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + else returnm (None : option ((mword 3 * mword 8)))) + : M (option ((mword 3 * mword 8))). + +Definition _s2112_ (_s2113_ : string) +: M (option ((csrop * mword 5 * mword 5 * mword 12))) := + + (match _s2113_ with + | _s2114_ => + (csr_mnemonic_matches_prefix _s2114_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2115_ _)) => + (match (string_drop _s2114_ _s2115_) with + | _s2116_ => + (spc_matches_prefix _s2116_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2117_ _)) => + (match (string_drop _s2116_ _s2117_) with + | _s2118_ => + (reg_name_matches_prefix _s2118_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2119_ _)) => + (match (string_drop _s2118_ _s2119_) with + | _s2120_ => + (sep_matches_prefix _s2120_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2121_ _)) => + (match (string_drop _s2120_ _s2121_) with + | _s2122_ => + (reg_name_matches_prefix _s2122_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s2123_ _)) => + (match (string_drop _s2122_ _s2123_) with + | _s2124_ => + (sep_matches_prefix _s2124_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2125_ _)) => + (match (string_drop _s2124_ _s2125_) with + | _s2126_ => + (csr_name_map_matches_prefix _s2126_) >>= fun w__6 : option ((mword 12 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (csr,(existT _ _s2127_ _)) => + let p0_ := + string_drop _s2126_ _s2127_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, csr)) + else None + | _ => None + end) + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))). + +Definition _s2094_ (_s2095_ : string) +: M (option ((csrop * mword 5 * mword 5 * mword 12))) := + + (match _s2095_ with + | _s2096_ => + (csr_mnemonic_matches_prefix _s2096_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2097_ _)) => + let _s2098_ := string_drop _s2096_ _s2097_ in + (if ((string_startswith _s2098_ "i")) then + (match (string_drop _s2098_ (projT1 (string_length "i"))) with + | _s2099_ => + (spc_matches_prefix _s2099_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2100_ _)) => + (match (string_drop _s2099_ _s2100_) with + | _s2101_ => + (reg_name_matches_prefix _s2101_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2102_ _)) => + (match (string_drop _s2101_ _s2102_) with + | _s2103_ => + (sep_matches_prefix _s2103_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2104_ _)) => + (match (string_drop _s2103_ _s2104_) with + | _s2105_ => + (match (hex_bits_5_matches_prefix _s2105_) with + | Some (rs1,(existT _ _s2106_ _)) => + (match (string_drop _s2105_ _s2106_) with + | _s2107_ => + (sep_matches_prefix _s2107_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s2108_ _)) => + (match (string_drop _s2107_ _s2108_) with + | _s2109_ => + (csr_name_map_matches_prefix _s2109_) >>= fun w__5 : option ((mword 12 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some + (csr,(existT _ _s2110_ _)) => + let p0_ := + string_drop _s2109_ _s2110_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, csr)) + else None + | _ => None + end) + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + else returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))). + +Definition _s2070_ (_s2071_ : string) +: M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) := + + (match _s2071_ with + | _s2072_ => + (amo_mnemonic_matches_prefix _s2072_) >>= fun w__0 : option ((amoop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2073_ _)) => + let _s2074_ := string_drop _s2072_ _s2073_ in + (if ((string_startswith _s2074_ ".")) then + (match (string_drop _s2074_ (projT1 (string_length "."))) with + | _s2075_ => + (size_mnemonic_matches_prefix _s2075_) >>= fun w__1 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (width,(existT _ _s2076_ _)) => + (match (string_drop _s2075_ _s2076_) with + | _s2077_ => + (maybe_aq_matches_prefix _s2077_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (aq,(existT _ _s2078_ _)) => + (match (string_drop _s2077_ _s2078_) with + | _s2079_ => + (maybe_rl_matches_prefix _s2079_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rl,(existT _ _s2080_ _)) => + (match (string_drop _s2079_ _s2080_) with + | _s2081_ => + (spc_matches_prefix _s2081_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s2082_ _)) => + (match (string_drop _s2081_ _s2082_) with + | _s2083_ => + (reg_name_matches_prefix _s2083_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (rd,(existT _ _s2084_ _)) => + (match (string_drop _s2083_ _s2084_) with + | _s2085_ => + (sep_matches_prefix _s2085_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (tt,(existT _ _s2086_ _)) => + (match (string_drop _s2085_ _s2086_) with + | _s2087_ => + (reg_name_matches_prefix _s2087_) >>= fun w__7 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__7 with + | Some (rs1,(existT _ _s2088_ _)) => + (match (string_drop _s2087_ + _s2088_) with + | _s2089_ => + (sep_matches_prefix + _s2089_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__8 with + | Some + (tt,(existT _ _s2090_ _)) => + (match (string_drop + _s2089_ + _s2090_) with + | _s2091_ => + (reg_name_matches_prefix + _s2091_) >>= fun w__9 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__9 with + | Some + (rs2,(existT _ _s2092_ _)) => + let p0_ := + string_drop + _s2091_ + _s2092_ in + if ((generic_eq + p0_ + "")) + then + Some + ((op, width, aq, rl, rd, rs1, rs2)) + else + None + | _ => + None + end) + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + else + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))). + +Definition _s2048_ (_s2049_ : string) +: M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) := + + let _s2050_ := _s2049_ in + (if ((string_startswith _s2050_ "sc.")) then + (match (string_drop _s2050_ (projT1 (string_length "sc."))) with + | _s2051_ => + (size_mnemonic_matches_prefix _s2051_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s2052_ _)) => + (match (string_drop _s2051_ _s2052_) with + | _s2053_ => + (maybe_aq_matches_prefix _s2053_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (aq,(existT _ _s2054_ _)) => + (match (string_drop _s2053_ _s2054_) with + | _s2055_ => + (maybe_rl_matches_prefix _s2055_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rl,(existT _ _s2056_ _)) => + (match (string_drop _s2055_ _s2056_) with + | _s2057_ => + (spc_matches_prefix _s2057_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2058_ _)) => + (match (string_drop _s2057_ _s2058_) with + | _s2059_ => + (reg_name_matches_prefix _s2059_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rd,(existT _ _s2060_ _)) => + (match (string_drop _s2059_ _s2060_) with + | _s2061_ => + (sep_matches_prefix _s2061_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2062_ _)) => + (match (string_drop _s2061_ _s2062_) with + | _s2063_ => + (reg_name_matches_prefix _s2063_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (rs1,(existT _ _s2064_ _)) => + (match (string_drop _s2063_ _s2064_) with + | _s2065_ => + (sep_matches_prefix _s2065_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__7 with + | Some (tt,(existT _ _s2066_ _)) => + (match (string_drop _s2065_ + _s2066_) with + | _s2067_ => + (reg_name_matches_prefix + _s2067_) >>= fun w__8 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__8 with + | Some + (rs2,(existT _ _s2068_ _)) => + let p0_ := + string_drop + _s2067_ + _s2068_ in + if ((generic_eq + p0_ "")) + then + Some + ((size, aq, rl, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))). + +Definition _s2030_ (_s2031_ : string) +: M (option ((word_width * bool * bool * mword 5 * mword 5))) := + + let _s2032_ := _s2031_ in + (if ((string_startswith _s2032_ "lr.")) then + (match (string_drop _s2032_ (projT1 (string_length "lr."))) with + | _s2033_ => + (size_mnemonic_matches_prefix _s2033_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s2034_ _)) => + (match (string_drop _s2033_ _s2034_) with + | _s2035_ => + (maybe_aq_matches_prefix _s2035_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (aq,(existT _ _s2036_ _)) => + (match (string_drop _s2035_ _s2036_) with + | _s2037_ => + (maybe_rl_matches_prefix _s2037_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rl,(existT _ _s2038_ _)) => + (match (string_drop _s2037_ _s2038_) with + | _s2039_ => + (spc_matches_prefix _s2039_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2040_ _)) => + (match (string_drop _s2039_ _s2040_) with + | _s2041_ => + (reg_name_matches_prefix _s2041_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rd,(existT _ _s2042_ _)) => + (match (string_drop _s2041_ _s2042_) with + | _s2043_ => + (sep_matches_prefix _s2043_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2044_ _)) => + (match (string_drop _s2043_ _s2044_) with + | _s2045_ => + (reg_name_matches_prefix _s2045_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs1,(existT _ _s2046_ _)) => + let p0_ := + string_drop _s2045_ _s2046_ in + if ((generic_eq p0_ "")) then + Some + ((size, aq, rl, rd, rs1)) + else None + | _ => None + end) + : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => returnm (None : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => returnm (None : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5)))) + : M (option ((word_width * bool * bool * mword 5 * mword 5))). + +Definition _s2018_ (_s2019_ : string) +: M (option ((mword 5 * mword 5))) := + + let _s2020_ := _s2019_ in + (if ((string_startswith _s2020_ "sfence.vma")) then + (match (string_drop _s2020_ (projT1 (string_length "sfence.vma"))) with + | _s2021_ => + (spc_matches_prefix _s2021_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2022_ _)) => + (match (string_drop _s2021_ _s2022_) with + | _s2023_ => + (reg_name_matches_prefix _s2023_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs1,(existT _ _s2024_ _)) => + (match (string_drop _s2023_ _s2024_) with + | _s2025_ => + (sep_matches_prefix _s2025_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2026_ _)) => + (match (string_drop _s2025_ _s2026_) with + | _s2027_ => + (reg_name_matches_prefix _s2027_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s2028_ _)) => + let p0_ := string_drop _s2027_ _s2028_ in + if ((generic_eq p0_ "")) then Some ((rs1, rs2)) + else None + | _ => None + end) + : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + else returnm (None : option ((mword 5 * mword 5)))) + : M (option ((mword 5 * mword 5))). + +Definition _s2006_ (_s2007_ : string) +: M (option ((mword 4 * mword 4))) := + + let _s2008_ := _s2007_ in + (if ((string_startswith _s2008_ "fence.tso")) then + (match (string_drop _s2008_ (projT1 (string_length "fence.tso"))) with + | _s2009_ => + (spc_matches_prefix _s2009_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2010_ _)) => + (match (string_drop _s2009_ _s2010_) with + | _s2011_ => + (fence_bits_matches_prefix _s2011_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (pred,(existT _ _s2012_ _)) => + (match (string_drop _s2011_ _s2012_) with + | _s2013_ => + (sep_matches_prefix _s2013_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2014_ _)) => + (match (string_drop _s2013_ _s2014_) with + | _s2015_ => + (fence_bits_matches_prefix _s2015_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (succ,(existT _ _s2016_ _)) => + let p0_ := string_drop _s2015_ _s2016_ in + if ((generic_eq p0_ "")) then Some ((pred, succ)) + else None + | _ => None + end) + : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + else returnm (None : option ((mword 4 * mword 4)))) + : M (option ((mword 4 * mword 4))). + +Definition _s1994_ (_s1995_ : string) +: M (option ((mword 4 * mword 4))) := + + let _s1996_ := _s1995_ in + (if ((string_startswith _s1996_ "fence")) then + (match (string_drop _s1996_ (projT1 (string_length "fence"))) with + | _s1997_ => + (spc_matches_prefix _s1997_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1998_ _)) => + (match (string_drop _s1997_ _s1998_) with + | _s1999_ => + (fence_bits_matches_prefix _s1999_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (pred,(existT _ _s2000_ _)) => + (match (string_drop _s1999_ _s2000_) with + | _s2001_ => + (sep_matches_prefix _s2001_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2002_ _)) => + (match (string_drop _s2001_ _s2002_) with + | _s2003_ => + (fence_bits_matches_prefix _s2003_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (succ,(existT _ _s2004_ _)) => + let p0_ := string_drop _s2003_ _s2004_ in + if ((generic_eq p0_ "")) then Some ((pred, succ)) + else None + | _ => None + end) + : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + else returnm (None : option ((mword 4 * mword 4)))) + : M (option ((mword 4 * mword 4))). + +Definition _s1975_ (_s1976_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5))) := + + let _s1977_ := _s1976_ in + (if ((string_startswith _s1977_ "rem")) then + (match (string_drop _s1977_ (projT1 (string_length "rem"))) with + | _s1978_ => + (maybe_not_u_matches_prefix _s1978_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s1979_ _)) => + let _s1980_ := string_drop _s1978_ _s1979_ in + (if ((string_startswith _s1980_ "w")) then + (match (string_drop _s1980_ (projT1 (string_length "w"))) with + | _s1981_ => + (spc_matches_prefix _s1981_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1982_ _)) => + (match (string_drop _s1981_ _s1982_) with + | _s1983_ => + (reg_name_matches_prefix _s1983_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1984_ _)) => + (match (string_drop _s1983_ _s1984_) with + | _s1985_ => + (sep_matches_prefix _s1985_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1986_ _)) => + (match (string_drop _s1985_ _s1986_) with + | _s1987_ => + (reg_name_matches_prefix _s1987_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1988_ _)) => + (match (string_drop _s1987_ _s1988_) with + | _s1989_ => + (sep_matches_prefix _s1989_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1990_ _)) => + (match (string_drop _s1989_ _s1990_) with + | _s1991_ => + (reg_name_matches_prefix _s1991_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s1992_ _)) => + let p0_ := + string_drop _s1991_ + _s1992_ in + if ((generic_eq p0_ "")) + then + Some + ((s, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))). + +Definition _s1956_ (_s1957_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5))) := + + let _s1958_ := _s1957_ in + (if ((string_startswith _s1958_ "div")) then + (match (string_drop _s1958_ (projT1 (string_length "div"))) with + | _s1959_ => + (maybe_not_u_matches_prefix _s1959_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s1960_ _)) => + let _s1961_ := string_drop _s1959_ _s1960_ in + (if ((string_startswith _s1961_ "w")) then + (match (string_drop _s1961_ (projT1 (string_length "w"))) with + | _s1962_ => + (spc_matches_prefix _s1962_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1963_ _)) => + (match (string_drop _s1962_ _s1963_) with + | _s1964_ => + (reg_name_matches_prefix _s1964_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1965_ _)) => + (match (string_drop _s1964_ _s1965_) with + | _s1966_ => + (sep_matches_prefix _s1966_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1967_ _)) => + (match (string_drop _s1966_ _s1967_) with + | _s1968_ => + (reg_name_matches_prefix _s1968_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1969_ _)) => + (match (string_drop _s1968_ _s1969_) with + | _s1970_ => + (sep_matches_prefix _s1970_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1971_ _)) => + (match (string_drop _s1970_ _s1971_) with + | _s1972_ => + (reg_name_matches_prefix _s1972_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s1973_ _)) => + let p0_ := + string_drop _s1972_ + _s1973_ in + if ((generic_eq p0_ "")) + then + Some + ((s, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))). + +Definition _s1940_ (_s1941_ : string) +: M (option ((mword 5 * mword 5 * mword 5))) := + + let _s1942_ := _s1941_ in + (if ((string_startswith _s1942_ "mulw")) then + (match (string_drop _s1942_ (projT1 (string_length "mulw"))) with + | _s1943_ => + (spc_matches_prefix _s1943_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1944_ _)) => + (match (string_drop _s1943_ _s1944_) with + | _s1945_ => + (reg_name_matches_prefix _s1945_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1946_ _)) => + (match (string_drop _s1945_ _s1946_) with + | _s1947_ => + (sep_matches_prefix _s1947_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1948_ _)) => + (match (string_drop _s1947_ _s1948_) with + | _s1949_ => + (reg_name_matches_prefix _s1949_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rs1,(existT _ _s1950_ _)) => + (match (string_drop _s1949_ _s1950_) with + | _s1951_ => + (sep_matches_prefix _s1951_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s1952_ _)) => + (match (string_drop _s1951_ _s1952_) with + | _s1953_ => + (reg_name_matches_prefix _s1953_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (rs2,(existT _ _s1954_ _)) => + let p0_ := + string_drop _s1953_ _s1954_ in + if ((generic_eq p0_ "")) then + Some + ((rd, rs1, rs2)) + else None + | _ => None + end) + : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + else returnm (None : option ((mword 5 * mword 5 * mword 5)))) + : M (option ((mword 5 * mword 5 * mword 5))). + +Definition _s1922_ (_s1923_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5))) := + + let _s1924_ := _s1923_ in + (if ((string_startswith _s1924_ "rem")) then + (match (string_drop _s1924_ (projT1 (string_length "rem"))) with + | _s1925_ => + (maybe_not_u_matches_prefix _s1925_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s1926_ _)) => + (match (string_drop _s1925_ _s1926_) with + | _s1927_ => + (spc_matches_prefix _s1927_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1928_ _)) => + (match (string_drop _s1927_ _s1928_) with + | _s1929_ => + (reg_name_matches_prefix _s1929_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1930_ _)) => + (match (string_drop _s1929_ _s1930_) with + | _s1931_ => + (sep_matches_prefix _s1931_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1932_ _)) => + (match (string_drop _s1931_ _s1932_) with + | _s1933_ => + (reg_name_matches_prefix _s1933_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1934_ _)) => + (match (string_drop _s1933_ _s1934_) with + | _s1935_ => + (sep_matches_prefix _s1935_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1936_ _)) => + (match (string_drop _s1935_ _s1936_) with + | _s1937_ => + (reg_name_matches_prefix _s1937_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s1938_ _)) => + let p0_ := + string_drop _s1937_ _s1938_ in + if ((generic_eq p0_ "")) then + Some + ((s, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))). + +Definition _s1904_ (_s1905_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5))) := + + let _s1906_ := _s1905_ in + (if ((string_startswith _s1906_ "div")) then + (match (string_drop _s1906_ (projT1 (string_length "div"))) with + | _s1907_ => + (maybe_not_u_matches_prefix _s1907_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s1908_ _)) => + (match (string_drop _s1907_ _s1908_) with + | _s1909_ => + (spc_matches_prefix _s1909_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1910_ _)) => + (match (string_drop _s1909_ _s1910_) with + | _s1911_ => + (reg_name_matches_prefix _s1911_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1912_ _)) => + (match (string_drop _s1911_ _s1912_) with + | _s1913_ => + (sep_matches_prefix _s1913_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1914_ _)) => + (match (string_drop _s1913_ _s1914_) with + | _s1915_ => + (reg_name_matches_prefix _s1915_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1916_ _)) => + (match (string_drop _s1915_ _s1916_) with + | _s1917_ => + (sep_matches_prefix _s1917_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1918_ _)) => + (match (string_drop _s1917_ _s1918_) with + | _s1919_ => + (reg_name_matches_prefix _s1919_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s1920_ _)) => + let p0_ := + string_drop _s1919_ _s1920_ in + if ((generic_eq p0_ "")) then + Some + ((s, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))). + +Definition _s1887_ (_s1888_ : string) +: M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) := + + (match _s1888_ with + | _s1889_ => + (mul_mnemonic_matches_prefix _s1889_) >>= fun w__0 : option (((bool * bool * bool) * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some ((high, signed1, signed2),(existT _ _s1890_ _)) => + (match (string_drop _s1889_ _s1890_) with + | _s1891_ => + (spc_matches_prefix _s1891_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1892_ _)) => + (match (string_drop _s1891_ _s1892_) with + | _s1893_ => + (reg_name_matches_prefix _s1893_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1894_ _)) => + (match (string_drop _s1893_ _s1894_) with + | _s1895_ => + (sep_matches_prefix _s1895_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1896_ _)) => + (match (string_drop _s1895_ _s1896_) with + | _s1897_ => + (reg_name_matches_prefix _s1897_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1898_ _)) => + (match (string_drop _s1897_ _s1898_) with + | _s1899_ => + (sep_matches_prefix _s1899_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1900_ _)) => + (match (string_drop _s1899_ _s1900_) with + | _s1901_ => + (reg_name_matches_prefix _s1901_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (rs2,(existT _ _s1902_ _)) => + let p0_ := + string_drop _s1901_ _s1902_ in + if ((generic_eq p0_ "")) then + Some + ((high, signed1, signed2, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))). + +Definition _s1872_ (_s1873_ : string) +: M (option ((sopw * mword 5 * mword 5 * mword 5))) := + + (match _s1873_ with + | _s1874_ => + (shiftiwop_mnemonic_matches_prefix _s1874_) >>= fun w__0 : option ((sopw * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1875_ _)) => + (match (string_drop _s1874_ _s1875_) with + | _s1876_ => + (spc_matches_prefix _s1876_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1877_ _)) => + (match (string_drop _s1876_ _s1877_) with + | _s1878_ => + (reg_name_matches_prefix _s1878_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1879_ _)) => + (match (string_drop _s1878_ _s1879_) with + | _s1880_ => + (sep_matches_prefix _s1880_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1881_ _)) => + (match (string_drop _s1880_ _s1881_) with + | _s1882_ => + (reg_name_matches_prefix _s1882_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (rs1,(existT _ _s1883_ _)) => + match (string_drop _s1882_ _s1883_) with + | _s1884_ => + match (hex_bits_5_matches_prefix _s1884_) with + | Some (shamt,(existT _ _s1885_ _)) => + let p0_ := string_drop _s1884_ _s1885_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None : option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))). + +Definition _s1855_ (_s1856_ : string) +: M (option ((ropw * mword 5 * mword 5 * mword 5))) := + + (match _s1856_ with + | _s1857_ => + (rtypew_mnemonic_matches_prefix _s1857_) >>= fun w__0 : option ((ropw * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1858_ _)) => + (match (string_drop _s1857_ _s1858_) with + | _s1859_ => + (spc_matches_prefix _s1859_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1860_ _)) => + (match (string_drop _s1859_ _s1860_) with + | _s1861_ => + (reg_name_matches_prefix _s1861_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1862_ _)) => + (match (string_drop _s1861_ _s1862_) with + | _s1863_ => + (sep_matches_prefix _s1863_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1864_ _)) => + (match (string_drop _s1863_ _s1864_) with + | _s1865_ => + (reg_name_matches_prefix _s1865_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1866_ _)) => + (match (string_drop _s1865_ _s1866_) with + | _s1867_ => + (sep_matches_prefix _s1867_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1868_ _)) => + (match (string_drop _s1867_ _s1868_) with + | _s1869_ => + (reg_name_matches_prefix _s1869_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (rs2,(existT _ _s1870_ _)) => + let p0_ := + string_drop _s1869_ _s1870_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))). + +Definition _s1838_ (_s1839_ : string) +: M (option ((sop * mword 5 * mword 5 * mword 5))) := + + (match _s1839_ with + | _s1840_ => + (shiftw_mnemonic_matches_prefix _s1840_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1841_ _)) => + (match (string_drop _s1840_ _s1841_) with + | _s1842_ => + (spc_matches_prefix _s1842_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1843_ _)) => + (match (string_drop _s1842_ _s1843_) with + | _s1844_ => + (reg_name_matches_prefix _s1844_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1845_ _)) => + (match (string_drop _s1844_ _s1845_) with + | _s1846_ => + (sep_matches_prefix _s1846_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1847_ _)) => + (match (string_drop _s1846_ _s1847_) with + | _s1848_ => + (reg_name_matches_prefix _s1848_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1849_ _)) => + (match (string_drop _s1848_ _s1849_) with + | _s1850_ => + (sep_matches_prefix _s1850_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (tt,(existT _ _s1851_ _)) => + match (string_drop _s1850_ _s1851_) with + | _s1852_ => + match (hex_bits_5_matches_prefix + _s1852_) with + | Some (shamt,(existT _ _s1853_ _)) => + let p0_ := + string_drop _s1852_ _s1853_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))). + +Definition _s1822_ (_s1823_ : string) +: M (option ((mword 5 * mword 5 * mword 12))) := + + let _s1824_ := _s1823_ in + (if ((string_startswith _s1824_ "addiw")) then + (match (string_drop _s1824_ (projT1 (string_length "addiw"))) with + | _s1825_ => + (spc_matches_prefix _s1825_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1826_ _)) => + (match (string_drop _s1825_ _s1826_) with + | _s1827_ => + (reg_name_matches_prefix _s1827_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1828_ _)) => + (match (string_drop _s1827_ _s1828_) with + | _s1829_ => + (sep_matches_prefix _s1829_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1830_ _)) => + (match (string_drop _s1829_ _s1830_) with + | _s1831_ => + (reg_name_matches_prefix _s1831_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rs1,(existT _ _s1832_ _)) => + (match (string_drop _s1831_ _s1832_) with + | _s1833_ => + (sep_matches_prefix _s1833_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s1834_ _)) => + match (string_drop _s1833_ _s1834_) with + | _s1835_ => + match (hex_bits_12_matches_prefix _s1835_) with + | Some (imm,(existT _ _s1836_ _)) => + let p0_ := string_drop _s1835_ _s1836_ in + if ((generic_eq p0_ "")) then + Some + ((rd, rs1, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + else returnm (None : option ((mword 5 * mword 5 * mword 12)))) + : M (option ((mword 5 * mword 5 * mword 12))). + +Definition _s1800_ (_s1801_ : string) +: M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) := + + let _s1802_ := _s1801_ in + (if ((string_startswith _s1802_ "s")) then + (match (string_drop _s1802_ (projT1 (string_length "s"))) with + | _s1803_ => + (size_mnemonic_matches_prefix _s1803_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s1804_ _)) => + (match (string_drop _s1803_ _s1804_) with + | _s1805_ => + (maybe_aq_matches_prefix _s1805_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (aq,(existT _ _s1806_ _)) => + (match (string_drop _s1805_ _s1806_) with + | _s1807_ => + (maybe_rl_matches_prefix _s1807_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rl,(existT _ _s1808_ _)) => + (match (string_drop _s1807_ _s1808_) with + | _s1809_ => + (spc_matches_prefix _s1809_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1810_ _)) => + (match (string_drop _s1809_ _s1810_) with + | _s1811_ => + (reg_name_matches_prefix _s1811_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rd,(existT _ _s1812_ _)) => + (match (string_drop _s1811_ _s1812_) with + | _s1813_ => + (sep_matches_prefix _s1813_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1814_ _)) => + (match (string_drop _s1813_ _s1814_) with + | _s1815_ => + (reg_name_matches_prefix _s1815_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (rs1,(existT _ _s1816_ _)) => + (match (string_drop _s1815_ _s1816_) with + | _s1817_ => + (sep_matches_prefix _s1817_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__7 with + | Some + (tt,(existT _ _s1818_ _)) => + match (string_drop + _s1817_ + _s1818_) with + | _s1819_ => + match (hex_bits_12_matches_prefix + _s1819_) with + | Some + (imm,(existT _ _s1820_ _)) => + let p0_ := + string_drop + _s1819_ + _s1820_ in + if ((generic_eq + p0_ "")) + then + Some + ((size, aq, rl, rd, rs1, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12)))) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))). + +Definition _s1776_ (_s1777_ : string) +: M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) := + + let _s1778_ := _s1777_ in + (if ((string_startswith _s1778_ "l")) then + (match (string_drop _s1778_ (projT1 (string_length "l"))) with + | _s1779_ => + (size_mnemonic_matches_prefix _s1779_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s1780_ _)) => + (match (string_drop _s1779_ _s1780_) with + | _s1781_ => + (maybe_u_matches_prefix _s1781_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (is_unsigned,(existT _ _s1782_ _)) => + (match (string_drop _s1781_ _s1782_) with + | _s1783_ => + (maybe_aq_matches_prefix _s1783_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (aq,(existT _ _s1784_ _)) => + (match (string_drop _s1783_ _s1784_) with + | _s1785_ => + (maybe_rl_matches_prefix _s1785_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rl,(existT _ _s1786_ _)) => + (match (string_drop _s1785_ _s1786_) with + | _s1787_ => + (spc_matches_prefix _s1787_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s1788_ _)) => + (match (string_drop _s1787_ _s1788_) with + | _s1789_ => + (reg_name_matches_prefix _s1789_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (rd,(existT _ _s1790_ _)) => + (match (string_drop _s1789_ _s1790_) with + | _s1791_ => + (sep_matches_prefix _s1791_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (tt,(existT _ _s1792_ _)) => + (match (string_drop _s1791_ _s1792_) with + | _s1793_ => + (reg_name_matches_prefix _s1793_) >>= fun w__7 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__7 with + | Some (rs1,(existT _ _s1794_ _)) => + (match (string_drop _s1793_ + _s1794_) with + | _s1795_ => + (sep_matches_prefix + _s1795_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__8 with + | Some + (tt,(existT _ _s1796_ _)) => + match (string_drop + _s1795_ + _s1796_) with + | _s1797_ => + match (hex_bits_12_matches_prefix + _s1797_) with + | Some + (imm,(existT _ _s1798_ _)) => + let p0_ := + string_drop + _s1797_ + _s1798_ in + if ((generic_eq + p0_ + "")) + then + Some + ((size, is_unsigned, aq, rl, rd, rs1, imm)) + else + None + | _ => + None + end + end + | _ => None + end) + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + else returnm (None : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12)))) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))). + +Definition _s1759_ (_s1760_ : string) +: M (option ((rop * mword 5 * mword 5 * mword 5))) := + + (match _s1760_ with + | _s1761_ => + (rtype_mnemonic_matches_prefix _s1761_) >>= fun w__0 : option ((rop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1762_ _)) => + (match (string_drop _s1761_ _s1762_) with + | _s1763_ => + (spc_matches_prefix _s1763_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1764_ _)) => + (match (string_drop _s1763_ _s1764_) with + | _s1765_ => + (reg_name_matches_prefix _s1765_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1766_ _)) => + (match (string_drop _s1765_ _s1766_) with + | _s1767_ => + (sep_matches_prefix _s1767_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1768_ _)) => + (match (string_drop _s1767_ _s1768_) with + | _s1769_ => + (reg_name_matches_prefix _s1769_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1770_ _)) => + (match (string_drop _s1769_ _s1770_) with + | _s1771_ => + (sep_matches_prefix _s1771_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1772_ _)) => + (match (string_drop _s1771_ _s1772_) with + | _s1773_ => + (reg_name_matches_prefix _s1773_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (rs2,(existT _ _s1774_ _)) => + let p0_ := + string_drop _s1773_ _s1774_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))). + +Definition _s1744_ (_s1745_ : string) +: M (option ((sop * mword 5 * mword 5 * mword 6))) := + + (match _s1745_ with + | _s1746_ => + (shiftiop_mnemonic_matches_prefix _s1746_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1747_ _)) => + (match (string_drop _s1746_ _s1747_) with + | _s1748_ => + (spc_matches_prefix _s1748_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1749_ _)) => + (match (string_drop _s1748_ _s1749_) with + | _s1750_ => + (reg_name_matches_prefix _s1750_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1751_ _)) => + (match (string_drop _s1750_ _s1751_) with + | _s1752_ => + (sep_matches_prefix _s1752_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1753_ _)) => + (match (string_drop _s1752_ _s1753_) with + | _s1754_ => + (reg_name_matches_prefix _s1754_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (rs1,(existT _ _s1755_ _)) => + match (string_drop _s1754_ _s1755_) with + | _s1756_ => + match (hex_bits_6_matches_prefix _s1756_) with + | Some (shamt,(existT _ _s1757_ _)) => + let p0_ := string_drop _s1756_ _s1757_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + | _ => + returnm (None : option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))). + +Definition _s1727_ (_s1728_ : string) +: M (option ((iop * mword 5 * mword 5 * mword 12))) := + + (match _s1728_ with + | _s1729_ => + (itype_mnemonic_matches_prefix _s1729_) >>= fun w__0 : option ((iop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1730_ _)) => + (match (string_drop _s1729_ _s1730_) with + | _s1731_ => + (spc_matches_prefix _s1731_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1732_ _)) => + (match (string_drop _s1731_ _s1732_) with + | _s1733_ => + (reg_name_matches_prefix _s1733_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1734_ _)) => + (match (string_drop _s1733_ _s1734_) with + | _s1735_ => + (sep_matches_prefix _s1735_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1736_ _)) => + (match (string_drop _s1735_ _s1736_) with + | _s1737_ => + (reg_name_matches_prefix _s1737_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1738_ _)) => + (match (string_drop _s1737_ _s1738_) with + | _s1739_ => + (sep_matches_prefix _s1739_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (tt,(existT _ _s1740_ _)) => + match (string_drop _s1739_ _s1740_) with + | _s1741_ => + match (hex_bits_12_matches_prefix + _s1741_) with + | Some (imm,(existT _ _s1742_ _)) => + let p0_ := + string_drop _s1741_ _s1742_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))). + +Definition _s1710_ (_s1711_ : string) +: M (option ((bop * mword 5 * mword 5 * mword 13))) := + + (match _s1711_ with + | _s1712_ => + (btype_mnemonic_matches_prefix _s1712_) >>= fun w__0 : option ((bop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1713_ _)) => + (match (string_drop _s1712_ _s1713_) with + | _s1714_ => + (spc_matches_prefix _s1714_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1715_ _)) => + (match (string_drop _s1714_ _s1715_) with + | _s1716_ => + (reg_name_matches_prefix _s1716_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rs1,(existT _ _s1717_ _)) => + (match (string_drop _s1716_ _s1717_) with + | _s1718_ => + (sep_matches_prefix _s1718_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1719_ _)) => + (match (string_drop _s1718_ _s1719_) with + | _s1720_ => + (reg_name_matches_prefix _s1720_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs2,(existT _ _s1721_ _)) => + (match (string_drop _s1720_ _s1721_) with + | _s1722_ => + (sep_matches_prefix _s1722_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (tt,(existT _ _s1723_ _)) => + match (string_drop _s1722_ _s1723_) with + | _s1724_ => + match (hex_bits_13_matches_prefix + _s1724_) with + | Some (imm,(existT _ _s1725_ _)) => + let p0_ := + string_drop _s1724_ _s1725_ in + if ((generic_eq p0_ "")) then + Some + ((op, rs1, rs2, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + | _ => + returnm (None + : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + | _ => + returnm (None : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))). + +Definition _s1694_ (_s1695_ : string) +: M (option ((mword 5 * mword 5 * mword 12))) := + + let _s1696_ := _s1695_ in + (if ((string_startswith _s1696_ "jalr")) then + (match (string_drop _s1696_ (projT1 (string_length "jalr"))) with + | _s1697_ => + (spc_matches_prefix _s1697_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1698_ _)) => + (match (string_drop _s1697_ _s1698_) with + | _s1699_ => + (reg_name_matches_prefix _s1699_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1700_ _)) => + (match (string_drop _s1699_ _s1700_) with + | _s1701_ => + (sep_matches_prefix _s1701_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1702_ _)) => + (match (string_drop _s1701_ _s1702_) with + | _s1703_ => + (reg_name_matches_prefix _s1703_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rs1,(existT _ _s1704_ _)) => + (match (string_drop _s1703_ _s1704_) with + | _s1705_ => + (sep_matches_prefix _s1705_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s1706_ _)) => + match (string_drop _s1705_ _s1706_) with + | _s1707_ => + match (hex_bits_12_matches_prefix _s1707_) with + | Some (imm,(existT _ _s1708_ _)) => + let p0_ := string_drop _s1707_ _s1708_ in + if ((generic_eq p0_ "")) then + Some + ((rd, rs1, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + else returnm (None : option ((mword 5 * mword 5 * mword 12)))) + : M (option ((mword 5 * mword 5 * mword 12))). + +Definition _s1682_ (_s1683_ : string) +: M (option ((mword 5 * mword 21))) := + + let _s1684_ := _s1683_ in + (if ((string_startswith _s1684_ "jal")) then + (match (string_drop _s1684_ (projT1 (string_length "jal"))) with + | _s1685_ => + (spc_matches_prefix _s1685_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1686_ _)) => + (match (string_drop _s1685_ _s1686_) with + | _s1687_ => + (reg_name_matches_prefix _s1687_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1688_ _)) => + (match (string_drop _s1687_ _s1688_) with + | _s1689_ => + (sep_matches_prefix _s1689_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1690_ _)) => + match (string_drop _s1689_ _s1690_) with + | _s1691_ => + match (hex_bits_21_matches_prefix _s1691_) with + | Some (imm,(existT _ _s1692_ _)) => + let p0_ := string_drop _s1691_ _s1692_ in + if ((generic_eq p0_ "")) then Some ((rd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 21))) + end) + : M (option ((mword 5 * mword 21))) + | _ => returnm (None : option ((mword 5 * mword 21))) + end) + : M (option ((mword 5 * mword 21))) + end) + : M (option ((mword 5 * mword 21))) + | _ => returnm (None : option ((mword 5 * mword 21))) + end) + : M (option ((mword 5 * mword 21))) + end) + : M (option ((mword 5 * mword 21))) + else returnm (None : option ((mword 5 * mword 21)))) + : M (option ((mword 5 * mword 21))). + +Definition _s1669_ (_s1670_ : string) +: M (option ((uop * mword 5 * mword 20))) := + + (match _s1670_ with + | _s1671_ => + (utype_mnemonic_matches_prefix _s1671_) >>= fun w__0 : option ((uop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1672_ _)) => + (match (string_drop _s1671_ _s1672_) with + | _s1673_ => + (spc_matches_prefix _s1673_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1674_ _)) => + (match (string_drop _s1673_ _s1674_) with + | _s1675_ => + (reg_name_matches_prefix _s1675_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1676_ _)) => + (match (string_drop _s1675_ _s1676_) with + | _s1677_ => + (sep_matches_prefix _s1677_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (tt,(existT _ _s1678_ _)) => + match (string_drop _s1677_ _s1678_) with + | _s1679_ => + match (hex_bits_20_matches_prefix _s1679_) with + | Some (imm,(existT _ _s1680_ _)) => + let p0_ := string_drop _s1679_ _s1680_ in + if ((generic_eq p0_ "")) then Some ((op, rd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + | _ => returnm (None : option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + | _ => returnm (None : option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + | _ => returnm (None : option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))). + +Definition assembly_backwards_matches (arg_ : string) +: M (bool) := + + let _s1681_ := arg_ in + (_s1669_ _s1681_) >>= fun w__0 : option ((uop * mword 5 * mword 20)) => + (if ((match w__0 with | Some (op,rd,imm) => true | _ => false end)) then + (_s1669_ _s1681_) >>= fun w__1 : option ((uop * mword 5 * mword 20)) => + (match w__1 with | Some (op,rd,imm) => returnm (true : bool) | _ => exit tt : M (bool) end) + : M (bool) + else + (_s1682_ _s1681_) >>= fun w__4 : option ((mword 5 * mword 21)) => + (if ((match w__4 with | Some (rd,imm) => true | _ => false end)) then + (_s1682_ _s1681_) >>= fun w__5 : option ((mword 5 * mword 21)) => + (match w__5 with | Some (rd,imm) => returnm (true : bool) | _ => exit tt : M (bool) end) + : M (bool) + else + (_s1694_ _s1681_) >>= fun w__8 : option ((mword 5 * mword 5 * mword 12)) => + (if ((match w__8 with | Some (rd,rs1,imm) => true | _ => false end)) then + (_s1694_ _s1681_) >>= fun w__9 : option ((mword 5 * mword 5 * mword 12)) => + (match w__9 with + | Some (rd,rs1,imm) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1710_ _s1681_) >>= fun w__12 : option ((bop * mword 5 * mword 5 * mword 13)) => + (if ((match w__12 with | Some (op,rs1,rs2,imm) => true | _ => false end)) then + (_s1710_ _s1681_) >>= fun w__13 : option ((bop * mword 5 * mword 5 * mword 13)) => + (match w__13 with + | Some (op,rs1,rs2,imm) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1727_ _s1681_) >>= fun w__16 : option ((iop * mword 5 * mword 5 * mword 12)) => + (if ((match w__16 with | Some (op,rd,rs1,imm) => true | _ => false end)) then + (_s1727_ _s1681_) >>= fun w__17 : option ((iop * mword 5 * mword 5 * mword 12)) => + (match w__17 with + | Some (op,rd,rs1,imm) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1744_ _s1681_) >>= fun w__20 : option ((sop * mword 5 * mword 5 * mword 6)) => + (if ((match w__20 with | Some (op,rd,rs1,shamt) => true | _ => false end)) then + (_s1744_ _s1681_) >>= fun w__21 : option ((sop * mword 5 * mword 5 * mword 6)) => + (match w__21 with + | Some (op,rd,rs1,shamt) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1759_ _s1681_) >>= fun w__24 : option ((rop * mword 5 * mword 5 * mword 5)) => + (if ((match w__24 with | Some (op,rd,rs1,rs2) => true | _ => false end)) then + (_s1759_ _s1681_) >>= fun w__25 : option ((rop * mword 5 * mword 5 * mword 5)) => + (match w__25 with + | Some (op,rd,rs1,rs2) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1776_ _s1681_) >>= fun w__28 : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12)) => + (if ((match w__28 with + | Some (size,is_unsigned,aq,rl,rd,rs1,imm) => true + | _ => false + end)) then + (_s1776_ _s1681_) >>= fun w__29 : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12)) => + (match w__29 with + | Some (size,is_unsigned,aq,rl,rd,rs1,imm) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1800_ _s1681_) >>= fun w__32 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12)) => + (if ((match w__32 with + | Some (size,aq,rl,rd,rs1,imm) => true + | _ => false + end)) then + (_s1800_ _s1681_) >>= fun w__33 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12)) => + (match w__33 with + | Some (size,aq,rl,rd,rs1,imm) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1822_ _s1681_) >>= fun w__36 : option ((mword 5 * mword 5 * mword 12)) => + (if ((match w__36 with | Some (rd,rs1,imm) => true | _ => false end)) + then + (_s1822_ _s1681_) >>= fun w__37 : option ((mword 5 * mword 5 * mword 12)) => + (match w__37 with + | Some (rd,rs1,imm) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1838_ _s1681_) >>= fun w__40 : option ((sop * mword 5 * mword 5 * mword 5)) => + (if ((match w__40 with + | Some (op,rd,rs1,shamt) => true + | _ => false + end)) then + (_s1838_ _s1681_) >>= fun w__41 : option ((sop * mword 5 * mword 5 * mword 5)) => + (match w__41 with + | Some (op,rd,rs1,shamt) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1855_ _s1681_) >>= fun w__44 : option ((ropw * mword 5 * mword 5 * mword 5)) => + (if ((match w__44 with + | Some (op,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1855_ _s1681_) >>= fun w__45 : option ((ropw * mword 5 * mword 5 * mword 5)) => + (match w__45 with + | Some (op,rd,rs1,rs2) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1872_ _s1681_) >>= fun w__48 : option ((sopw * mword 5 * mword 5 * mword 5)) => + (if ((match w__48 with + | Some (op,rd,rs1,shamt) => true + | _ => false + end)) then + (_s1872_ _s1681_) >>= fun w__49 : option ((sopw * mword 5 * mword 5 * mword 5)) => + (match w__49 with + | Some (op,rd,rs1,shamt) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1887_ _s1681_) >>= fun w__52 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__52 with + | Some (high,signed1,signed2,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1887_ _s1681_) >>= fun w__53 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)) => + (match w__53 with + | Some (high,signed1,signed2,rd,rs1,rs2) => + returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1904_ _s1681_) >>= fun w__56 : option ((bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__56 with + | Some (s,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1904_ _s1681_) >>= fun w__57 : option ((bool * mword 5 * mword 5 * mword 5)) => + (match w__57 with + | Some (s,rd,rs1,rs2) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1922_ _s1681_) >>= fun w__60 : option ((bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__60 with + | Some (s,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1922_ _s1681_) >>= fun w__61 : option ((bool * mword 5 * mword 5 * mword 5)) => + (match w__61 with + | Some (s,rd,rs1,rs2) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1940_ _s1681_) >>= fun w__64 : option ((mword 5 * mword 5 * mword 5)) => + (if ((match w__64 with + | Some (rd,rs1,rs2) => true + | _ => false + end)) then + (_s1940_ _s1681_) >>= fun w__65 : option ((mword 5 * mword 5 * mword 5)) => + (match w__65 with + | Some (rd,rs1,rs2) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1956_ _s1681_) >>= fun w__68 : option ((bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__68 with + | Some (s,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1956_ _s1681_) >>= fun w__69 : option ((bool * mword 5 * mword 5 * mword 5)) => + (match w__69 with + | Some (s,rd,rs1,rs2) => + returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1975_ _s1681_) >>= fun w__72 : option ((bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__72 with + | Some (s,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1975_ _s1681_) >>= fun w__73 : option ((bool * mword 5 * mword 5 * mword 5)) => + (match w__73 with + | Some (s,rd,rs1,rs2) => + returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1994_ _s1681_) >>= fun w__76 : option ((mword 4 * mword 4)) => + (if ((match w__76 with + | Some (pred,succ) => true + | _ => false + end)) then + (_s1994_ _s1681_) >>= fun w__77 : option ((mword 4 * mword 4)) => + (match w__77 with + | Some (pred,succ) => + returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s2006_ _s1681_) >>= fun w__80 : option ((mword 4 * mword 4)) => + (if ((match w__80 with + | Some (pred,succ) => true + | _ => false + end)) then + (_s2006_ _s1681_) >>= fun w__81 : option ((mword 4 * mword 4)) => + (match w__81 with + | Some (pred,succ) => + returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else if ((generic_eq _s1681_ + "fence.i")) then + returnm (true + : bool) + else if ((generic_eq _s1681_ "ecall")) + then + returnm (true + : bool) + else if ((generic_eq _s1681_ "mret")) + then + returnm (true + : bool) + else if ((generic_eq _s1681_ "sret")) + then + returnm (true + : bool) + else if ((generic_eq _s1681_ + "ebreak")) then + returnm (true + : bool) + else if ((generic_eq _s1681_ "wfi")) + then + returnm (true + : bool) + else + (_s2018_ _s1681_) >>= fun w__84 : option ((mword 5 * mword 5)) => + (if ((match w__84 with + | Some (rs1,rs2) => true + | _ => false + end)) then + (_s2018_ _s1681_) >>= fun w__85 : option ((mword 5 * mword 5)) => + (match w__85 with + | Some (rs1,rs2) => + returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s2030_ _s1681_) >>= fun w__88 : option ((word_width * bool * bool * mword 5 * mword 5)) => + (if ((match w__88 with + | Some + (size,aq,rl,rd,rs1) => + true + | _ => false + end)) then + (_s2030_ _s1681_) >>= fun w__89 : option ((word_width * bool * bool * mword 5 * mword 5)) => + (match w__89 with + | Some (size,aq,rl,rd,rs1) => + returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s2048_ _s1681_) >>= fun w__92 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__92 with + | Some + (size,aq,rl,rd,rs1,rs2) => + true + | _ => false + end)) then + (_s2048_ _s1681_) >>= fun w__93 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)) => + (match w__93 with + | Some + (size,aq,rl,rd,rs1,rs2) => + returnm (true + : bool) + | _ => + exit tt : M (bool) + end) + : M (bool) + else + (_s2070_ _s1681_) >>= fun w__96 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__96 with + | Some + (op,width,aq,rl,rd,rs1,rs2) => + true + | _ => false + end)) then + (_s2070_ _s1681_) >>= fun w__97 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)) => + (match w__97 with + | Some + (op,width,aq,rl,rd,rs1,rs2) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2094_ _s1681_) >>= fun w__100 : option ((csrop * mword 5 * mword 5 * mword 12)) => + (if ((match w__100 with + | Some + (op,rd,rs1,csr) => + true + | _ => false + end)) then + (_s2094_ _s1681_) >>= fun w__101 : option ((csrop * mword 5 * mword 5 * mword 12)) => + (match w__101 with + | Some + (op,rd,rs1,csr) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2112_ _s1681_) >>= fun w__104 : option ((csrop * mword 5 * mword 5 * mword 12)) => + (if ((match w__104 with + | Some + (op,rd,rs1,csr) => + true + | _ => false + end)) then + (_s2112_ _s1681_) >>= fun w__105 : option ((csrop * mword 5 * mword 5 * mword 12)) => + (match w__105 with + | Some + (op,rd,rs1,csr) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else if ((generic_eq + _s1681_ + "c.nop")) + then + returnm (true + : bool) + else + (_s2129_ _s1681_) >>= fun w__108 : option ((mword 3 * mword 8)) => + (if ((match w__108 with + | Some + (rdc,nzimm) => + neq_vec + nzimm + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] + : mword 8) + | _ => + false + end)) then + (_s2129_ + _s1681_) >>= fun w__109 : option ((mword 3 * mword 8)) => + (match w__109 with + | Some + (rdc,nzimm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2141_ + _s1681_) >>= fun w__112 : option ((mword 3 * mword 3 * mword 5)) => + (if ((match w__112 with + | Some + (rdc,rsc,uimm) => + true + | _ => + false + end)) + then + (_s2141_ + _s1681_) >>= fun w__113 : option ((mword 3 * mword 3 * mword 5)) => + (match w__113 with + | Some + (rdc,rsc,uimm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2157_ + _s1681_) >>= fun w__116 : option ((mword 3 * mword 3 * mword 5)) => + (if ((match w__116 with + | Some + (rdc,rsc,uimm) => + true + | _ => + false + end)) + then + (_s2157_ + _s1681_) >>= fun w__117 : option ((mword 3 * mword 3 * mword 5)) => + (match w__117 with + | Some + (rdc,rsc,uimm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2173_ + _s1681_) >>= fun w__120 : option ((mword 3 * mword 3 * mword 5)) => + (if ((match w__120 with + | Some + (rsc1,rsc2,uimm) => + true + | _ => + false + end)) + then + (_s2173_ + _s1681_) >>= fun w__121 : option ((mword 3 * mword 3 * mword 5)) => + (match w__121 with + | Some + (rsc1,rsc2,uimm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2189_ + _s1681_) >>= fun w__124 : option ((mword 3 * mword 3 * mword 5)) => + (if ((match w__124 with + | Some + (rsc1,rsc2,uimm) => + true + | _ => + false + end)) + then + (_s2189_ + _s1681_) >>= fun w__125 : option ((mword 3 * mword 3 * mword 5)) => + (match w__125 with + | Some + (rsc1,rsc2,uimm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2205_ + _s1681_) >>= fun w__128 : option ((mword 5 * mword 6)) => + (if + ((match w__128 with + | Some + (rsd,nzi) => + andb + (neq_vec + nzi + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6)) + (neq_int + (projT1 (regbits_to_regno + rsd)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s2205_ + _s1681_) >>= fun w__129 : option ((mword 5 * mword 6)) => + (match w__129 with + | Some + (rsd,nzi) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2217_ + _s1681_) >>= fun w__132 : option (mword 11) => + (if + ((match w__132 with + | Some + (imm) => + true + | _ => + false + end)) + then + (_s2217_ + _s1681_) >>= fun w__133 : option (mword 11) => + (match w__133 with + | Some + (imm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2225_ + _s1681_) >>= fun w__136 : option ((mword 5 * mword 6)) => + (if + ((match w__136 with + | Some + (rsd,imm) => + true + | _ => + false + end)) + then + (_s2225_ + _s1681_) >>= fun w__137 : option ((mword 5 * mword 6)) => + (match w__137 with + | Some + (rsd,imm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2237_ + _s1681_) >>= fun w__140 : option ((mword 5 * mword 6)) => + (if + ((match w__140 with + | Some + (rd,imm) => + neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s2237_ + _s1681_) >>= fun w__141 : option ((mword 5 * mword 6)) => + (match w__141 with + | Some + (rd,imm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2249_ + _s1681_) >>= fun w__144 : option (mword 6) => + (if + ((match w__144 with + | Some + (imm) => + neq_vec + imm + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6) + | _ => + false + end)) + then + (_s2249_ + _s1681_) >>= fun w__145 : option (mword 6) => + (match w__145 with + | Some + (imm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2257_ + _s1681_) >>= fun w__148 : option ((mword 5 * mword 6)) => + (if + ((match w__148 with + | Some + (rd,imm) => + andb + (neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg))) + (andb + (neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + sp))) + (neq_vec + imm + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6))) + | _ => + false + end)) + then + (_s2257_ + _s1681_) >>= fun w__149 : option ((mword 5 * mword 6)) => + (match w__149 with + | Some + (rd,imm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2269_ + _s1681_) >>= fun w__152 : option ((mword 3 * mword 6)) => + (if + ((match w__152 with + | Some + (rsd,shamt) => + neq_vec + shamt + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6) + | _ => + false + end)) + then + (_s2269_ + _s1681_) >>= fun w__153 : option ((mword 3 * mword 6)) => + (match w__153 with + | Some + (rsd,shamt) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2281_ + _s1681_) >>= fun w__156 : option ((mword 3 * mword 6)) => + (if + ((match w__156 with + | Some + (rsd,shamt) => + neq_vec + shamt + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6) + | _ => + false + end)) + then + (_s2281_ + _s1681_) >>= fun w__157 : option ((mword 3 * mword 6)) => + (match w__157 with + | Some + (rsd,shamt) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2293_ + _s1681_) >>= fun w__160 : option ((mword 3 * mword 6)) => + (if + ((match w__160 with + | Some + (rsd,imm) => + true + | _ => + false + end)) + then + (_s2293_ + _s1681_) >>= fun w__161 : option ((mword 3 * mword 6)) => + (match w__161 with + | Some + (rsd,imm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2305_ + _s1681_) >>= fun w__164 : option ((mword 3 * mword 3)) => + (if + ((match w__164 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s2305_ + _s1681_) >>= fun w__165 : option ((mword 3 * mword 3)) => + (match w__165 with + | Some + (rsd,rs2) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2317_ + _s1681_) >>= fun w__168 : option ((mword 3 * mword 3)) => + (if + ((match w__168 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s2317_ + _s1681_) >>= fun w__169 : option ((mword 3 * mword 3)) => + (match w__169 with + | Some + (rsd,rs2) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2329_ + _s1681_) >>= fun w__172 : option ((mword 3 * mword 3)) => + (if + ((match w__172 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s2329_ + _s1681_) >>= fun w__173 : option ((mword 3 * mword 3)) => + (match w__173 with + | Some + (rsd,rs2) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2341_ + _s1681_) >>= fun w__176 : option ((mword 3 * mword 3)) => + (if + ((match w__176 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s2341_ + _s1681_) >>= fun w__177 : option ((mword 3 * mword 3)) => + (match w__177 with + | Some + (rsd,rs2) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2353_ + _s1681_) >>= fun w__180 : option ((mword 3 * mword 3)) => + (if + ((match w__180 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s2353_ + _s1681_) >>= fun w__181 : option ((mword 3 * mword 3)) => + (match w__181 with + | Some + (rsd,rs2) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2365_ + _s1681_) >>= fun w__184 : option ((mword 3 * mword 3)) => + (if + ((match w__184 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s2365_ + _s1681_) >>= fun w__185 : option ((mword 3 * mword 3)) => + (match w__185 with + | Some + (rsd,rs2) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2377_ + _s1681_) >>= fun w__188 : option (mword 11) => + (if + ((match w__188 with + | Some + (imm) => + true + | _ => + false + end)) + then + (_s2377_ + _s1681_) >>= fun w__189 : option (mword 11) => + (match w__189 with + | Some + (imm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2385_ + _s1681_) >>= fun w__192 : option ((mword 3 * mword 8)) => + (if + ((match w__192 with + | Some + (rs,imm) => + true + | _ => + false + end)) + then + (_s2385_ + _s1681_) >>= fun w__193 : option ((mword 3 * mword 8)) => + (match w__193 with + | Some + (rs,imm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2397_ + _s1681_) >>= fun w__196 : option ((mword 3 * mword 8)) => + (if + ((match w__196 with + | Some + (rs,imm) => + true + | _ => + false + end)) + then + (_s2397_ + _s1681_) >>= fun w__197 : option ((mword 3 * mword 8)) => + (match w__197 with + | Some + (rs,imm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2409_ + _s1681_) >>= fun w__200 : option ((mword 5 * mword 6)) => + (if + ((match w__200 with + | Some + (rsd,shamt) => + andb + (neq_vec + shamt + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6)) + (neq_int + (projT1 (regbits_to_regno + rsd)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s2409_ + _s1681_) >>= fun w__201 : option ((mword 5 * mword 6)) => + (match w__201 with + | Some + (rsd,shamt) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2421_ + _s1681_) >>= fun w__204 : option ((mword 5 * mword 6)) => + (if + ((match w__204 with + | Some + (rd,uimm) => + neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s2421_ + _s1681_) >>= fun w__205 : option ((mword 5 * mword 6)) => + (match w__205 with + | Some + (rd,uimm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2433_ + _s1681_) >>= fun w__208 : option ((mword 5 * mword 6)) => + (if + ((match w__208 with + | Some + (rd,uimm) => + neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s2433_ + _s1681_) >>= fun w__209 : option ((mword 5 * mword 6)) => + (match w__209 with + | Some + (rd,uimm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2445_ + _s1681_) >>= fun w__212 : option ((mword 5 * mword 6)) => + (if + ((match w__212 with + | Some + (rd,uimm) => + true + | _ => + false + end)) + then + (_s2445_ + _s1681_) >>= fun w__213 : option ((mword 5 * mword 6)) => + (match w__213 with + | Some + (rd,uimm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2457_ + _s1681_) >>= fun w__216 : option ((mword 5 * mword 6)) => + (if + ((match w__216 with + | Some + (rs2,uimm) => + true + | _ => + false + end)) + then + (_s2457_ + _s1681_) >>= fun w__217 : option ((mword 5 * mword 6)) => + (match w__217 with + | Some + (rs2,uimm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2469_ + _s1681_) >>= fun w__220 : option (mword 5) => + (if + ((match w__220 with + | Some + (rs1) => + neq_int + (projT1 (regbits_to_regno + rs1)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s2469_ + _s1681_) >>= fun w__221 : option (mword 5) => + (match w__221 with + | Some + (rs1) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2477_ + _s1681_) >>= fun w__224 : option (mword 5) => + (if + ((match w__224 with + | Some + (rs1) => + neq_int + (projT1 (regbits_to_regno + rs1)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s2477_ + _s1681_) >>= fun w__225 : option (mword 5) => + (match w__225 with + | Some + (rs1) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2485_ + _s1681_) >>= fun w__228 : option ((mword 5 * mword 5)) => + (if + ((match w__228 with + | Some + (rd,rs2) => + andb + (neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg))) + (neq_int + (projT1 (regbits_to_regno + rs2)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s2485_ + _s1681_) >>= fun w__229 : option ((mword 5 * mword 5)) => + (match w__229 with + | Some + (rd,rs2) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else if + ((generic_eq + _s1681_ + "c.ebreak")) + then + returnm (true + : bool) + else + (_s2497_ + _s1681_) >>= fun w__232 : option ((mword 5 * mword 5)) => + (if + ((match w__232 with + | Some + (rsd,rs2) => + andb + (neq_int + (projT1 (regbits_to_regno + rsd)) + (projT1 (regbits_to_regno + zreg))) + (neq_int + (projT1 (regbits_to_regno + rs2)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s2497_ + _s1681_) >>= fun w__233 : option ((mword 5 * mword 5)) => + (match w__233 with + | Some + (rsd,rs2) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else if + ((generic_eq + _s1681_ + "stop_fetching")) + then + returnm (true + : bool) + else if + ((generic_eq + _s1681_ + "thread_start")) + then + returnm (true + : bool) + else + (_s2509_ + _s1681_) >>= fun w__236 : option (mword 32) => + (if + ((match w__236 with + | Some + (s) => + true + | _ => + false + end)) + then + (_s2509_ + _s1681_) >>= fun w__237 : option (mword 32) => + (match w__237 with + | Some + (s) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2517_ + _s1681_) >>= fun w__240 : option (mword 16) => + (if + ((match w__240 with + | Some + (s) => + true + | _ => + false + end)) + then + (_s2517_ + _s1681_) >>= fun w__241 : option (mword 16) => + (match w__241 with + | Some + (s) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + returnm (false + : bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool). + +Definition _s3413_ (_s3414_ : string) +: M (option ((mword 16 * string))) := + + let _s3415_ := _s3414_ in + (if ((string_startswith _s3415_ "c.illegal")) then + (match (string_drop _s3415_ (projT1 (string_length "c.illegal"))) with + | _s3416_ => + (spc_matches_prefix _s3416_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s3417_ _)) => + match (string_drop _s3416_ _s3417_) with + | _s3418_ => + match (hex_bits_16_matches_prefix _s3418_) with + | Some (s,(existT _ _s3419_ _)) => + match (string_drop _s3418_ _s3419_) with | s_ => Some ((s, s_)) end + | _ => None + end + end + | _ => None + end) + : option ((mword 16 * string))) + end) + : M (option ((mword 16 * string))) + else returnm (None : option ((mword 16 * string)))) + : M (option ((mword 16 * string))). + +Definition _s3405_ (_s3406_ : string) +: M (option ((mword 32 * string))) := + + let _s3407_ := _s3406_ in + (if ((string_startswith _s3407_ "illegal")) then + (match (string_drop _s3407_ (projT1 (string_length "illegal"))) with + | _s3408_ => + (spc_matches_prefix _s3408_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s3409_ _)) => + match (string_drop _s3408_ _s3409_) with + | _s3410_ => + match (hex_bits_32_matches_prefix _s3410_) with + | Some (s,(existT _ _s3411_ _)) => + match (string_drop _s3410_ _s3411_) with | s_ => Some ((s, s_)) end + | _ => None + end + end + | _ => None + end) + : option ((mword 32 * string))) + end) + : M (option ((mword 32 * string))) + else returnm (None : option ((mword 32 * string)))) + : M (option ((mword 32 * string))). + +Definition _s3401_ (_s3402_ : string) +: option string := + + let _s3403_ := _s3402_ in + if ((string_startswith _s3403_ "thread_start")) then + match (string_drop _s3403_ (projT1 (string_length "thread_start"))) with | s_ => Some (s_) end + else None. + +Definition _s3397_ (_s3398_ : string) +: option string := + + let _s3399_ := _s3398_ in + if ((string_startswith _s3399_ "stop_fetching")) then + match (string_drop _s3399_ (projT1 (string_length "stop_fetching"))) with | s_ => Some (s_) end + else None. + +Definition _s3385_ (_s3386_ : string) +: M (option ((mword 5 * mword 5 * string))) := + + let _s3387_ := _s3386_ in + (if ((string_startswith _s3387_ "c.add")) then + (match (string_drop _s3387_ (projT1 (string_length "c.add"))) with + | _s3388_ => + (spc_matches_prefix _s3388_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3389_ _)) => + (match (string_drop _s3388_ _s3389_) with + | _s3390_ => + (reg_name_matches_prefix _s3390_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3391_ _)) => + (match (string_drop _s3390_ _s3391_) with + | _s3392_ => + (sep_matches_prefix _s3392_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3393_ _)) => + (match (string_drop _s3392_ _s3393_) with + | _s3394_ => + (reg_name_matches_prefix _s3394_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s3395_ _)) => + match (string_drop _s3394_ _s3395_) with + | s_ => Some ((rsd, rs2, s_)) + end + | _ => None + end) + : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + else returnm (None : option ((mword 5 * mword 5 * string)))) + : M (option ((mword 5 * mword 5 * string))). + +Definition _s3381_ (_s3382_ : string) +: option string := + + let _s3383_ := _s3382_ in + if ((string_startswith _s3383_ "c.ebreak")) then + match (string_drop _s3383_ (projT1 (string_length "c.ebreak"))) with | s_ => Some (s_) end + else None. + +Definition _s3369_ (_s3370_ : string) +: M (option ((mword 5 * mword 5 * string))) := + + let _s3371_ := _s3370_ in + (if ((string_startswith _s3371_ "c.mv")) then + (match (string_drop _s3371_ (projT1 (string_length "c.mv"))) with + | _s3372_ => + (spc_matches_prefix _s3372_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3373_ _)) => + (match (string_drop _s3372_ _s3373_) with + | _s3374_ => + (reg_name_matches_prefix _s3374_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s3375_ _)) => + (match (string_drop _s3374_ _s3375_) with + | _s3376_ => + (sep_matches_prefix _s3376_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3377_ _)) => + (match (string_drop _s3376_ _s3377_) with + | _s3378_ => + (reg_name_matches_prefix _s3378_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s3379_ _)) => + match (string_drop _s3378_ _s3379_) with + | s_ => Some ((rd, rs2, s_)) + end + | _ => None + end) + : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + else returnm (None : option ((mword 5 * mword 5 * string)))) + : M (option ((mword 5 * mword 5 * string))). + +Definition _s3361_ (_s3362_ : string) +: M (option ((mword 5 * string))) := + + let _s3363_ := _s3362_ in + (if ((string_startswith _s3363_ "c.jalr")) then + (match (string_drop _s3363_ (projT1 (string_length "c.jalr"))) with + | _s3364_ => + (spc_matches_prefix _s3364_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3365_ _)) => + (match (string_drop _s3364_ _s3365_) with + | _s3366_ => + (reg_name_matches_prefix _s3366_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__1 with + | Some (rs1,(existT _ _s3367_ _)) => + match (string_drop _s3366_ _s3367_) with | s_ => Some ((rs1, s_)) end + | _ => None + end) + : option ((mword 5 * string))) + end) + : M (option ((mword 5 * string))) + | _ => returnm (None : option ((mword 5 * string))) + end) + : M (option ((mword 5 * string))) + end) + : M (option ((mword 5 * string))) + else returnm (None : option ((mword 5 * string)))) + : M (option ((mword 5 * string))). + +Definition _s3353_ (_s3354_ : string) +: M (option ((mword 5 * string))) := + + let _s3355_ := _s3354_ in + (if ((string_startswith _s3355_ "c.jr")) then + (match (string_drop _s3355_ (projT1 (string_length "c.jr"))) with + | _s3356_ => + (spc_matches_prefix _s3356_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3357_ _)) => + (match (string_drop _s3356_ _s3357_) with + | _s3358_ => + (reg_name_matches_prefix _s3358_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__1 with + | Some (rs1,(existT _ _s3359_ _)) => + match (string_drop _s3358_ _s3359_) with | s_ => Some ((rs1, s_)) end + | _ => None + end) + : option ((mword 5 * string))) + end) + : M (option ((mword 5 * string))) + | _ => returnm (None : option ((mword 5 * string))) + end) + : M (option ((mword 5 * string))) + end) + : M (option ((mword 5 * string))) + else returnm (None : option ((mword 5 * string)))) + : M (option ((mword 5 * string))). + +Definition _s3341_ (_s3342_ : string) +: M (option ((mword 5 * mword 6 * string))) := + + let _s3343_ := _s3342_ in + (if ((string_startswith _s3343_ "c.sdsp")) then + (match (string_drop _s3343_ (projT1 (string_length "c.sdsp"))) with + | _s3344_ => + (spc_matches_prefix _s3344_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3345_ _)) => + (match (string_drop _s3344_ _s3345_) with + | _s3346_ => + (reg_name_matches_prefix _s3346_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs2,(existT _ _s3347_ _)) => + (match (string_drop _s3346_ _s3347_) with + | _s3348_ => + (sep_matches_prefix _s3348_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3349_ _)) => + match (string_drop _s3348_ _s3349_) with + | _s3350_ => + match (hex_bits_6_matches_prefix _s3350_) with + | Some (uimm,(existT _ _s3351_ _)) => + match (string_drop _s3350_ _s3351_) with + | s_ => Some ((rs2, uimm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + else returnm (None : option ((mword 5 * mword 6 * string)))) + : M (option ((mword 5 * mword 6 * string))). + +Definition _s3329_ (_s3330_ : string) +: M (option ((mword 5 * mword 6 * string))) := + + let _s3331_ := _s3330_ in + (if ((string_startswith _s3331_ "c.swsp")) then + (match (string_drop _s3331_ (projT1 (string_length "c.swsp"))) with + | _s3332_ => + (spc_matches_prefix _s3332_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3333_ _)) => + (match (string_drop _s3332_ _s3333_) with + | _s3334_ => + (reg_name_matches_prefix _s3334_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s3335_ _)) => + (match (string_drop _s3334_ _s3335_) with + | _s3336_ => + (sep_matches_prefix _s3336_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3337_ _)) => + match (string_drop _s3336_ _s3337_) with + | _s3338_ => + match (hex_bits_6_matches_prefix _s3338_) with + | Some (uimm,(existT _ _s3339_ _)) => + match (string_drop _s3338_ _s3339_) with + | s_ => Some ((rd, uimm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + else returnm (None : option ((mword 5 * mword 6 * string)))) + : M (option ((mword 5 * mword 6 * string))). + +Definition _s3317_ (_s3318_ : string) +: M (option ((mword 5 * mword 6 * string))) := + + let _s3319_ := _s3318_ in + (if ((string_startswith _s3319_ "c.ldsp")) then + (match (string_drop _s3319_ (projT1 (string_length "c.ldsp"))) with + | _s3320_ => + (spc_matches_prefix _s3320_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3321_ _)) => + (match (string_drop _s3320_ _s3321_) with + | _s3322_ => + (reg_name_matches_prefix _s3322_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s3323_ _)) => + (match (string_drop _s3322_ _s3323_) with + | _s3324_ => + (sep_matches_prefix _s3324_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3325_ _)) => + match (string_drop _s3324_ _s3325_) with + | _s3326_ => + match (hex_bits_6_matches_prefix _s3326_) with + | Some (uimm,(existT _ _s3327_ _)) => + match (string_drop _s3326_ _s3327_) with + | s_ => Some ((rd, uimm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + else returnm (None : option ((mword 5 * mword 6 * string)))) + : M (option ((mword 5 * mword 6 * string))). + +Definition _s3305_ (_s3306_ : string) +: M (option ((mword 5 * mword 6 * string))) := + + let _s3307_ := _s3306_ in + (if ((string_startswith _s3307_ "c.lwsp")) then + (match (string_drop _s3307_ (projT1 (string_length "c.lwsp"))) with + | _s3308_ => + (spc_matches_prefix _s3308_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3309_ _)) => + (match (string_drop _s3308_ _s3309_) with + | _s3310_ => + (reg_name_matches_prefix _s3310_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s3311_ _)) => + (match (string_drop _s3310_ _s3311_) with + | _s3312_ => + (sep_matches_prefix _s3312_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3313_ _)) => + match (string_drop _s3312_ _s3313_) with + | _s3314_ => + match (hex_bits_6_matches_prefix _s3314_) with + | Some (uimm,(existT _ _s3315_ _)) => + match (string_drop _s3314_ _s3315_) with + | s_ => Some ((rd, uimm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + else returnm (None : option ((mword 5 * mword 6 * string)))) + : M (option ((mword 5 * mword 6 * string))). + +Definition _s3293_ (_s3294_ : string) +: M (option ((mword 5 * mword 6 * string))) := + + let _s3295_ := _s3294_ in + (if ((string_startswith _s3295_ "c.slli")) then + (match (string_drop _s3295_ (projT1 (string_length "c.slli"))) with + | _s3296_ => + (spc_matches_prefix _s3296_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3297_ _)) => + (match (string_drop _s3296_ _s3297_) with + | _s3298_ => + (reg_name_matches_prefix _s3298_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3299_ _)) => + (match (string_drop _s3298_ _s3299_) with + | _s3300_ => + (sep_matches_prefix _s3300_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3301_ _)) => + match (string_drop _s3300_ _s3301_) with + | _s3302_ => + match (hex_bits_6_matches_prefix _s3302_) with + | Some (shamt,(existT _ _s3303_ _)) => + match (string_drop _s3302_ _s3303_) with + | s_ => Some ((rsd, shamt, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + else returnm (None : option ((mword 5 * mword 6 * string)))) + : M (option ((mword 5 * mword 6 * string))). + +Definition _s3281_ (_s3282_ : string) +: M (option ((mword 3 * mword 8 * string))) := + + let _s3283_ := _s3282_ in + (if ((string_startswith _s3283_ "c.bnez")) then + (match (string_drop _s3283_ (projT1 (string_length "c.bnez"))) with + | _s3284_ => + (spc_matches_prefix _s3284_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3285_ _)) => + (match (string_drop _s3284_ _s3285_) with + | _s3286_ => + (creg_name_matches_prefix _s3286_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs,(existT _ _s3287_ _)) => + (match (string_drop _s3286_ _s3287_) with + | _s3288_ => + (sep_matches_prefix _s3288_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3289_ _)) => + match (string_drop _s3288_ _s3289_) with + | _s3290_ => + match (hex_bits_8_matches_prefix _s3290_) with + | Some (imm,(existT _ _s3291_ _)) => + match (string_drop _s3290_ _s3291_) with + | s_ => Some ((rs, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + | _ => returnm (None : option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + | _ => returnm (None : option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + else returnm (None : option ((mword 3 * mword 8 * string)))) + : M (option ((mword 3 * mword 8 * string))). + +Definition _s3269_ (_s3270_ : string) +: M (option ((mword 3 * mword 8 * string))) := + + let _s3271_ := _s3270_ in + (if ((string_startswith _s3271_ "c.beqz")) then + (match (string_drop _s3271_ (projT1 (string_length "c.beqz"))) with + | _s3272_ => + (spc_matches_prefix _s3272_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3273_ _)) => + (match (string_drop _s3272_ _s3273_) with + | _s3274_ => + (creg_name_matches_prefix _s3274_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs,(existT _ _s3275_ _)) => + (match (string_drop _s3274_ _s3275_) with + | _s3276_ => + (sep_matches_prefix _s3276_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3277_ _)) => + match (string_drop _s3276_ _s3277_) with + | _s3278_ => + match (hex_bits_8_matches_prefix _s3278_) with + | Some (imm,(existT _ _s3279_ _)) => + match (string_drop _s3278_ _s3279_) with + | s_ => Some ((rs, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + | _ => returnm (None : option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + | _ => returnm (None : option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + else returnm (None : option ((mword 3 * mword 8 * string)))) + : M (option ((mword 3 * mword 8 * string))). + +Definition _s3261_ (_s3262_ : string) +: M (option ((mword 11 * string))) := + + let _s3263_ := _s3262_ in + (if ((string_startswith _s3263_ "c.j")) then + (match (string_drop _s3263_ (projT1 (string_length "c.j"))) with + | _s3264_ => + (spc_matches_prefix _s3264_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s3265_ _)) => + match (string_drop _s3264_ _s3265_) with + | _s3266_ => + match (hex_bits_11_matches_prefix _s3266_) with + | Some (imm,(existT _ _s3267_ _)) => + match (string_drop _s3266_ _s3267_) with | s_ => Some ((imm, s_)) end + | _ => None + end + end + | _ => None + end) + : option ((mword 11 * string))) + end) + : M (option ((mword 11 * string))) + else returnm (None : option ((mword 11 * string)))) + : M (option ((mword 11 * string))). + +Definition _s3249_ (_s3250_ : string) +: M (option ((mword 3 * mword 3 * string))) := + + let _s3251_ := _s3250_ in + (if ((string_startswith _s3251_ "c.addw")) then + (match (string_drop _s3251_ (projT1 (string_length "c.addw"))) with + | _s3252_ => + (spc_matches_prefix _s3252_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3253_ _)) => + (match (string_drop _s3252_ _s3253_) with + | _s3254_ => + (creg_name_matches_prefix _s3254_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3255_ _)) => + (match (string_drop _s3254_ _s3255_) with + | _s3256_ => + (sep_matches_prefix _s3256_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3257_ _)) => + (match (string_drop _s3256_ _s3257_) with + | _s3258_ => + (creg_name_matches_prefix _s3258_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s3259_ _)) => + match (string_drop _s3258_ _s3259_) with + | s_ => Some ((rsd, rs2, s_)) + end + | _ => None + end) + : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + else returnm (None : option ((mword 3 * mword 3 * string)))) + : M (option ((mword 3 * mword 3 * string))). + +Definition _s3237_ (_s3238_ : string) +: M (option ((mword 3 * mword 3 * string))) := + + let _s3239_ := _s3238_ in + (if ((string_startswith _s3239_ "c.subw")) then + (match (string_drop _s3239_ (projT1 (string_length "c.subw"))) with + | _s3240_ => + (spc_matches_prefix _s3240_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3241_ _)) => + (match (string_drop _s3240_ _s3241_) with + | _s3242_ => + (creg_name_matches_prefix _s3242_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3243_ _)) => + (match (string_drop _s3242_ _s3243_) with + | _s3244_ => + (sep_matches_prefix _s3244_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3245_ _)) => + (match (string_drop _s3244_ _s3245_) with + | _s3246_ => + (creg_name_matches_prefix _s3246_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s3247_ _)) => + match (string_drop _s3246_ _s3247_) with + | s_ => Some ((rsd, rs2, s_)) + end + | _ => None + end) + : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + else returnm (None : option ((mword 3 * mword 3 * string)))) + : M (option ((mword 3 * mword 3 * string))). + +Definition _s3225_ (_s3226_ : string) +: M (option ((mword 3 * mword 3 * string))) := + + let _s3227_ := _s3226_ in + (if ((string_startswith _s3227_ "c.and")) then + (match (string_drop _s3227_ (projT1 (string_length "c.and"))) with + | _s3228_ => + (spc_matches_prefix _s3228_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3229_ _)) => + (match (string_drop _s3228_ _s3229_) with + | _s3230_ => + (creg_name_matches_prefix _s3230_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3231_ _)) => + (match (string_drop _s3230_ _s3231_) with + | _s3232_ => + (sep_matches_prefix _s3232_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3233_ _)) => + (match (string_drop _s3232_ _s3233_) with + | _s3234_ => + (creg_name_matches_prefix _s3234_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s3235_ _)) => + match (string_drop _s3234_ _s3235_) with + | s_ => Some ((rsd, rs2, s_)) + end + | _ => None + end) + : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + else returnm (None : option ((mword 3 * mword 3 * string)))) + : M (option ((mword 3 * mword 3 * string))). + +Definition _s3213_ (_s3214_ : string) +: M (option ((mword 3 * mword 3 * string))) := + + let _s3215_ := _s3214_ in + (if ((string_startswith _s3215_ "c.or")) then + (match (string_drop _s3215_ (projT1 (string_length "c.or"))) with + | _s3216_ => + (spc_matches_prefix _s3216_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3217_ _)) => + (match (string_drop _s3216_ _s3217_) with + | _s3218_ => + (creg_name_matches_prefix _s3218_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3219_ _)) => + (match (string_drop _s3218_ _s3219_) with + | _s3220_ => + (sep_matches_prefix _s3220_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3221_ _)) => + (match (string_drop _s3220_ _s3221_) with + | _s3222_ => + (creg_name_matches_prefix _s3222_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s3223_ _)) => + match (string_drop _s3222_ _s3223_) with + | s_ => Some ((rsd, rs2, s_)) + end + | _ => None + end) + : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + else returnm (None : option ((mword 3 * mword 3 * string)))) + : M (option ((mword 3 * mword 3 * string))). + +Definition _s3201_ (_s3202_ : string) +: M (option ((mword 3 * mword 3 * string))) := + + let _s3203_ := _s3202_ in + (if ((string_startswith _s3203_ "c.xor")) then + (match (string_drop _s3203_ (projT1 (string_length "c.xor"))) with + | _s3204_ => + (spc_matches_prefix _s3204_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3205_ _)) => + (match (string_drop _s3204_ _s3205_) with + | _s3206_ => + (creg_name_matches_prefix _s3206_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3207_ _)) => + (match (string_drop _s3206_ _s3207_) with + | _s3208_ => + (sep_matches_prefix _s3208_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3209_ _)) => + (match (string_drop _s3208_ _s3209_) with + | _s3210_ => + (creg_name_matches_prefix _s3210_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s3211_ _)) => + match (string_drop _s3210_ _s3211_) with + | s_ => Some ((rsd, rs2, s_)) + end + | _ => None + end) + : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + else returnm (None : option ((mword 3 * mword 3 * string)))) + : M (option ((mword 3 * mword 3 * string))). + +Definition _s3189_ (_s3190_ : string) +: M (option ((mword 3 * mword 3 * string))) := + + let _s3191_ := _s3190_ in + (if ((string_startswith _s3191_ "c.sub")) then + (match (string_drop _s3191_ (projT1 (string_length "c.sub"))) with + | _s3192_ => + (spc_matches_prefix _s3192_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3193_ _)) => + (match (string_drop _s3192_ _s3193_) with + | _s3194_ => + (creg_name_matches_prefix _s3194_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3195_ _)) => + (match (string_drop _s3194_ _s3195_) with + | _s3196_ => + (sep_matches_prefix _s3196_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3197_ _)) => + (match (string_drop _s3196_ _s3197_) with + | _s3198_ => + (creg_name_matches_prefix _s3198_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s3199_ _)) => + match (string_drop _s3198_ _s3199_) with + | s_ => Some ((rsd, rs2, s_)) + end + | _ => None + end) + : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + else returnm (None : option ((mword 3 * mword 3 * string)))) + : M (option ((mword 3 * mword 3 * string))). + +Definition _s3177_ (_s3178_ : string) +: M (option ((mword 3 * mword 6 * string))) := + + let _s3179_ := _s3178_ in + (if ((string_startswith _s3179_ "c.andi")) then + (match (string_drop _s3179_ (projT1 (string_length "c.andi"))) with + | _s3180_ => + (spc_matches_prefix _s3180_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3181_ _)) => + (match (string_drop _s3180_ _s3181_) with + | _s3182_ => + (creg_name_matches_prefix _s3182_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3183_ _)) => + (match (string_drop _s3182_ _s3183_) with + | _s3184_ => + (sep_matches_prefix _s3184_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3185_ _)) => + match (string_drop _s3184_ _s3185_) with + | _s3186_ => + match (hex_bits_6_matches_prefix _s3186_) with + | Some (imm,(existT _ _s3187_ _)) => + match (string_drop _s3186_ _s3187_) with + | s_ => Some ((rsd, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + | _ => returnm (None : option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + | _ => returnm (None : option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + else returnm (None : option ((mword 3 * mword 6 * string)))) + : M (option ((mword 3 * mword 6 * string))). + +Definition _s3165_ (_s3166_ : string) +: M (option ((mword 3 * mword 6 * string))) := + + let _s3167_ := _s3166_ in + (if ((string_startswith _s3167_ "c.srai")) then + (match (string_drop _s3167_ (projT1 (string_length "c.srai"))) with + | _s3168_ => + (spc_matches_prefix _s3168_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3169_ _)) => + (match (string_drop _s3168_ _s3169_) with + | _s3170_ => + (creg_name_matches_prefix _s3170_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3171_ _)) => + (match (string_drop _s3170_ _s3171_) with + | _s3172_ => + (sep_matches_prefix _s3172_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3173_ _)) => + match (string_drop _s3172_ _s3173_) with + | _s3174_ => + match (hex_bits_6_matches_prefix _s3174_) with + | Some (shamt,(existT _ _s3175_ _)) => + match (string_drop _s3174_ _s3175_) with + | s_ => Some ((rsd, shamt, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + | _ => returnm (None : option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + | _ => returnm (None : option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + else returnm (None : option ((mword 3 * mword 6 * string)))) + : M (option ((mword 3 * mword 6 * string))). + +Definition _s3153_ (_s3154_ : string) +: M (option ((mword 3 * mword 6 * string))) := + + let _s3155_ := _s3154_ in + (if ((string_startswith _s3155_ "c.srli")) then + (match (string_drop _s3155_ (projT1 (string_length "c.srli"))) with + | _s3156_ => + (spc_matches_prefix _s3156_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3157_ _)) => + (match (string_drop _s3156_ _s3157_) with + | _s3158_ => + (creg_name_matches_prefix _s3158_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3159_ _)) => + (match (string_drop _s3158_ _s3159_) with + | _s3160_ => + (sep_matches_prefix _s3160_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3161_ _)) => + match (string_drop _s3160_ _s3161_) with + | _s3162_ => + match (hex_bits_6_matches_prefix _s3162_) with + | Some (shamt,(existT _ _s3163_ _)) => + match (string_drop _s3162_ _s3163_) with + | s_ => Some ((rsd, shamt, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + | _ => returnm (None : option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + | _ => returnm (None : option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + else returnm (None : option ((mword 3 * mword 6 * string)))) + : M (option ((mword 3 * mword 6 * string))). + +Definition _s3141_ (_s3142_ : string) +: M (option ((mword 5 * mword 6 * string))) := + + let _s3143_ := _s3142_ in + (if ((string_startswith _s3143_ "c.lui")) then + (match (string_drop _s3143_ (projT1 (string_length "c.lui"))) with + | _s3144_ => + (spc_matches_prefix _s3144_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3145_ _)) => + (match (string_drop _s3144_ _s3145_) with + | _s3146_ => + (reg_name_matches_prefix _s3146_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s3147_ _)) => + (match (string_drop _s3146_ _s3147_) with + | _s3148_ => + (sep_matches_prefix _s3148_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3149_ _)) => + match (string_drop _s3148_ _s3149_) with + | _s3150_ => + match (hex_bits_6_matches_prefix _s3150_) with + | Some (imm,(existT _ _s3151_ _)) => + match (string_drop _s3150_ _s3151_) with + | s_ => Some ((rd, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + else returnm (None : option ((mword 5 * mword 6 * string)))) + : M (option ((mword 5 * mword 6 * string))). + +Definition _s3133_ (_s3134_ : string) +: M (option ((mword 6 * string))) := + + let _s3135_ := _s3134_ in + (if ((string_startswith _s3135_ "c.addi16sp")) then + (match (string_drop _s3135_ (projT1 (string_length "c.addi16sp"))) with + | _s3136_ => + (spc_matches_prefix _s3136_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s3137_ _)) => + match (string_drop _s3136_ _s3137_) with + | _s3138_ => + match (hex_bits_6_matches_prefix _s3138_) with + | Some (imm,(existT _ _s3139_ _)) => + match (string_drop _s3138_ _s3139_) with | s_ => Some ((imm, s_)) end + | _ => None + end + end + | _ => None + end) + : option ((mword 6 * string))) + end) + : M (option ((mword 6 * string))) + else returnm (None : option ((mword 6 * string)))) + : M (option ((mword 6 * string))). + +Definition _s3121_ (_s3122_ : string) +: M (option ((mword 5 * mword 6 * string))) := + + let _s3123_ := _s3122_ in + (if ((string_startswith _s3123_ "c.li")) then + (match (string_drop _s3123_ (projT1 (string_length "c.li"))) with + | _s3124_ => + (spc_matches_prefix _s3124_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3125_ _)) => + (match (string_drop _s3124_ _s3125_) with + | _s3126_ => + (reg_name_matches_prefix _s3126_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s3127_ _)) => + (match (string_drop _s3126_ _s3127_) with + | _s3128_ => + (sep_matches_prefix _s3128_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3129_ _)) => + match (string_drop _s3128_ _s3129_) with + | _s3130_ => + match (hex_bits_6_matches_prefix _s3130_) with + | Some (imm,(existT _ _s3131_ _)) => + match (string_drop _s3130_ _s3131_) with + | s_ => Some ((rd, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + else returnm (None : option ((mword 5 * mword 6 * string)))) + : M (option ((mword 5 * mword 6 * string))). + +Definition _s3109_ (_s3110_ : string) +: M (option ((mword 5 * mword 6 * string))) := + + let _s3111_ := _s3110_ in + (if ((string_startswith _s3111_ "c.addiw")) then + (match (string_drop _s3111_ (projT1 (string_length "c.addiw"))) with + | _s3112_ => + (spc_matches_prefix _s3112_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3113_ _)) => + (match (string_drop _s3112_ _s3113_) with + | _s3114_ => + (reg_name_matches_prefix _s3114_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3115_ _)) => + (match (string_drop _s3114_ _s3115_) with + | _s3116_ => + (sep_matches_prefix _s3116_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3117_ _)) => + match (string_drop _s3116_ _s3117_) with + | _s3118_ => + match (hex_bits_6_matches_prefix _s3118_) with + | Some (imm,(existT _ _s3119_ _)) => + match (string_drop _s3118_ _s3119_) with + | s_ => Some ((rsd, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + else returnm (None : option ((mword 5 * mword 6 * string)))) + : M (option ((mword 5 * mword 6 * string))). + +Definition _s3101_ (_s3102_ : string) +: M (option ((mword 11 * string))) := + + let _s3103_ := _s3102_ in + (if ((string_startswith _s3103_ "c.jal")) then + (match (string_drop _s3103_ (projT1 (string_length "c.jal"))) with + | _s3104_ => + (spc_matches_prefix _s3104_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s3105_ _)) => + match (string_drop _s3104_ _s3105_) with + | _s3106_ => + match (hex_bits_12_matches_prefix _s3106_) with + | Some (v__784,(existT _ _s3107_ _)) => + if ((eq_vec (subrange_vec_dec v__784 0 0) + (vec_of_bits [B0] : mword (0 - 0 + 1)))) then + let imm : mword 11 := subrange_vec_dec v__784 11 1 in + let imm : mword 11 := subrange_vec_dec v__784 11 1 in + match (string_drop _s3106_ _s3107_) with | s_ => Some ((imm, s_)) end + else + let g__21 := Some ((v__784, _s3107_)) in + None + | g__21 => None + end + end + | _ => None + end) + : option ((mword 11 * string))) + end) + : M (option ((mword 11 * string))) + else returnm (None : option ((mword 11 * string)))) + : M (option ((mword 11 * string))). + +Definition _s3089_ (_s3090_ : string) +: M (option ((mword 5 * mword 6 * string))) := + + let _s3091_ := _s3090_ in + (if ((string_startswith _s3091_ "c.addi")) then + (match (string_drop _s3091_ (projT1 (string_length "c.addi"))) with + | _s3092_ => + (spc_matches_prefix _s3092_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3093_ _)) => + (match (string_drop _s3092_ _s3093_) with + | _s3094_ => + (reg_name_matches_prefix _s3094_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3095_ _)) => + (match (string_drop _s3094_ _s3095_) with + | _s3096_ => + (sep_matches_prefix _s3096_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3097_ _)) => + match (string_drop _s3096_ _s3097_) with + | _s3098_ => + match (hex_bits_6_matches_prefix _s3098_) with + | Some (nzi,(existT _ _s3099_ _)) => + match (string_drop _s3098_ _s3099_) with + | s_ => Some ((rsd, nzi, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + else returnm (None : option ((mword 5 * mword 6 * string)))) + : M (option ((mword 5 * mword 6 * string))). + +Definition _s3073_ (_s3074_ : string) +: M (option ((mword 3 * mword 3 * mword 5 * string))) := + + let _s3075_ := _s3074_ in + (if ((string_startswith _s3075_ "c.sd")) then + (match (string_drop _s3075_ (projT1 (string_length "c.sd"))) with + | _s3076_ => + (spc_matches_prefix _s3076_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3077_ _)) => + (match (string_drop _s3076_ _s3077_) with + | _s3078_ => + (creg_name_matches_prefix _s3078_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsc1,(existT _ _s3079_ _)) => + (match (string_drop _s3078_ _s3079_) with + | _s3080_ => + (sep_matches_prefix _s3080_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3081_ _)) => + (match (string_drop _s3080_ _s3081_) with + | _s3082_ => + (creg_name_matches_prefix _s3082_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc2,(existT _ _s3083_ _)) => + (match (string_drop _s3082_ _s3083_) with + | _s3084_ => + (sep_matches_prefix _s3084_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s3085_ _)) => + match (string_drop _s3084_ _s3085_) with + | _s3086_ => + match (hex_bits_8_matches_prefix _s3086_) with + | Some (v__786,(existT _ _s3087_ _)) => + if ((eq_vec + (subrange_vec_dec v__786 2 0) + (vec_of_bits [B0;B0;B0] + : mword (2 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__786 7 3 in + let uimm : mword 5 := + subrange_vec_dec v__786 7 3 in + match (string_drop _s3086_ _s3087_) with + | s_ => Some ((rsc1, rsc2, uimm, s_)) + end + else + let g__20 := Some ((v__786, _s3087_)) in + None + | g__20 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => + returnm (None + : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + else returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))) + : M (option ((mword 3 * mword 3 * mword 5 * string))). + +Definition _s3057_ (_s3058_ : string) +: M (option ((mword 3 * mword 3 * mword 5 * string))) := + + let _s3059_ := _s3058_ in + (if ((string_startswith _s3059_ "c.sw")) then + (match (string_drop _s3059_ (projT1 (string_length "c.sw"))) with + | _s3060_ => + (spc_matches_prefix _s3060_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3061_ _)) => + (match (string_drop _s3060_ _s3061_) with + | _s3062_ => + (creg_name_matches_prefix _s3062_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsc1,(existT _ _s3063_ _)) => + (match (string_drop _s3062_ _s3063_) with + | _s3064_ => + (sep_matches_prefix _s3064_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3065_ _)) => + (match (string_drop _s3064_ _s3065_) with + | _s3066_ => + (creg_name_matches_prefix _s3066_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc2,(existT _ _s3067_ _)) => + (match (string_drop _s3066_ _s3067_) with + | _s3068_ => + (sep_matches_prefix _s3068_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s3069_ _)) => + match (string_drop _s3068_ _s3069_) with + | _s3070_ => + match (hex_bits_7_matches_prefix _s3070_) with + | Some (v__788,(existT _ _s3071_ _)) => + if ((eq_vec + (subrange_vec_dec v__788 1 0) + (vec_of_bits [B0;B0] + : mword (1 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__788 6 2 in + let uimm : mword 5 := + subrange_vec_dec v__788 6 2 in + match (string_drop _s3070_ _s3071_) with + | s_ => Some ((rsc1, rsc2, uimm, s_)) + end + else + let g__19 := Some ((v__788, _s3071_)) in + None + | g__19 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => + returnm (None + : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + else returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))) + : M (option ((mword 3 * mword 3 * mword 5 * string))). + +Definition _s3041_ (_s3042_ : string) +: M (option ((mword 3 * mword 3 * mword 5 * string))) := + + let _s3043_ := _s3042_ in + (if ((string_startswith _s3043_ "c.ld")) then + (match (string_drop _s3043_ (projT1 (string_length "c.ld"))) with + | _s3044_ => + (spc_matches_prefix _s3044_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3045_ _)) => + (match (string_drop _s3044_ _s3045_) with + | _s3046_ => + (creg_name_matches_prefix _s3046_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rdc,(existT _ _s3047_ _)) => + (match (string_drop _s3046_ _s3047_) with + | _s3048_ => + (sep_matches_prefix _s3048_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3049_ _)) => + (match (string_drop _s3048_ _s3049_) with + | _s3050_ => + (creg_name_matches_prefix _s3050_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc,(existT _ _s3051_ _)) => + (match (string_drop _s3050_ _s3051_) with + | _s3052_ => + (sep_matches_prefix _s3052_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s3053_ _)) => + match (string_drop _s3052_ _s3053_) with + | _s3054_ => + match (hex_bits_8_matches_prefix _s3054_) with + | Some (v__790,(existT _ _s3055_ _)) => + if ((eq_vec + (subrange_vec_dec v__790 2 0) + (vec_of_bits [B0;B0;B0] + : mword (2 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__790 7 3 in + let uimm : mword 5 := + subrange_vec_dec v__790 7 3 in + match (string_drop _s3054_ _s3055_) with + | s_ => Some ((rdc, rsc, uimm, s_)) + end + else + let g__18 := Some ((v__790, _s3055_)) in + None + | g__18 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => + returnm (None + : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + else returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))) + : M (option ((mword 3 * mword 3 * mword 5 * string))). + +Definition _s3025_ (_s3026_ : string) +: M (option ((mword 3 * mword 3 * mword 5 * string))) := + + let _s3027_ := _s3026_ in + (if ((string_startswith _s3027_ "c.lw")) then + (match (string_drop _s3027_ (projT1 (string_length "c.lw"))) with + | _s3028_ => + (spc_matches_prefix _s3028_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3029_ _)) => + (match (string_drop _s3028_ _s3029_) with + | _s3030_ => + (creg_name_matches_prefix _s3030_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rdc,(existT _ _s3031_ _)) => + (match (string_drop _s3030_ _s3031_) with + | _s3032_ => + (sep_matches_prefix _s3032_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3033_ _)) => + (match (string_drop _s3032_ _s3033_) with + | _s3034_ => + (creg_name_matches_prefix _s3034_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc,(existT _ _s3035_ _)) => + (match (string_drop _s3034_ _s3035_) with + | _s3036_ => + (sep_matches_prefix _s3036_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s3037_ _)) => + match (string_drop _s3036_ _s3037_) with + | _s3038_ => + match (hex_bits_7_matches_prefix _s3038_) with + | Some (v__792,(existT _ _s3039_ _)) => + if ((eq_vec + (subrange_vec_dec v__792 1 0) + (vec_of_bits [B0;B0] + : mword (1 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__792 6 2 in + let uimm : mword 5 := + subrange_vec_dec v__792 6 2 in + match (string_drop _s3038_ _s3039_) with + | s_ => Some ((rdc, rsc, uimm, s_)) + end + else + let g__17 := Some ((v__792, _s3039_)) in + None + | g__17 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => + returnm (None + : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + else returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))) + : M (option ((mword 3 * mword 3 * mword 5 * string))). + +Definition _s3013_ (_s3014_ : string) +: M (option ((mword 3 * mword 8 * string))) := + + let _s3015_ := _s3014_ in + (if ((string_startswith _s3015_ "c.addi4spn")) then + (match (string_drop _s3015_ (projT1 (string_length "c.addi4spn"))) with + | _s3016_ => + (spc_matches_prefix _s3016_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3017_ _)) => + (match (string_drop _s3016_ _s3017_) with + | _s3018_ => + (creg_name_matches_prefix _s3018_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rdc,(existT _ _s3019_ _)) => + (match (string_drop _s3018_ _s3019_) with + | _s3020_ => + (sep_matches_prefix _s3020_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3021_ _)) => + match (string_drop _s3020_ _s3021_) with + | _s3022_ => + match (hex_bits_10_matches_prefix _s3022_) with + | Some (v__794,(existT _ _s3023_ _)) => + if ((eq_vec (subrange_vec_dec v__794 1 0) + (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) + then + let nzimm : mword 8 := subrange_vec_dec v__794 9 2 in + let nzimm : mword 8 := subrange_vec_dec v__794 9 2 in + match (string_drop _s3022_ _s3023_) with + | s_ => Some ((rdc, nzimm, s_)) + end + else + let g__16 := Some ((v__794, _s3023_)) in + None + | g__16 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + | _ => returnm (None : option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + | _ => returnm (None : option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + else returnm (None : option ((mword 3 * mword 8 * string)))) + : M (option ((mword 3 * mword 8 * string))). + +Definition _s3009_ (_s3010_ : string) +: option string := + + let _s3011_ := _s3010_ in + if ((string_startswith _s3011_ "c.nop")) then + match (string_drop _s3011_ (projT1 (string_length "c.nop"))) with | s_ => Some (s_) end + else None. + +Definition _s2992_ (_s2993_ : string) +: M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) := + + (match _s2993_ with + | _s2994_ => + (csr_mnemonic_matches_prefix _s2994_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2995_ _)) => + (match (string_drop _s2994_ _s2995_) with + | _s2996_ => + (spc_matches_prefix _s2996_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2997_ _)) => + (match (string_drop _s2996_ _s2997_) with + | _s2998_ => + (reg_name_matches_prefix _s2998_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2999_ _)) => + (match (string_drop _s2998_ _s2999_) with + | _s3000_ => + (sep_matches_prefix _s3000_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s3001_ _)) => + (match (string_drop _s3000_ _s3001_) with + | _s3002_ => + (reg_name_matches_prefix _s3002_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s3003_ _)) => + (match (string_drop _s3002_ _s3003_) with + | _s3004_ => + (sep_matches_prefix _s3004_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s3005_ _)) => + (match (string_drop _s3004_ _s3005_) with + | _s3006_ => + (csr_name_map_matches_prefix _s3006_) >>= fun w__6 : option ((mword 12 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (csr,(existT _ _s3007_ _)) => + match (string_drop _s3006_ + _s3007_) with + | s_ => + Some ((op, rd, rs1, csr, s_)) + end + | _ => None + end) + : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))). + +Definition _s2974_ (_s2975_ : string) +: M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) := + + (match _s2975_ with + | _s2976_ => + (csr_mnemonic_matches_prefix _s2976_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2977_ _)) => + let _s2978_ := string_drop _s2976_ _s2977_ in + (if ((string_startswith _s2978_ "i")) then + (match (string_drop _s2978_ (projT1 (string_length "i"))) with + | _s2979_ => + (spc_matches_prefix _s2979_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2980_ _)) => + (match (string_drop _s2979_ _s2980_) with + | _s2981_ => + (reg_name_matches_prefix _s2981_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2982_ _)) => + (match (string_drop _s2981_ _s2982_) with + | _s2983_ => + (sep_matches_prefix _s2983_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2984_ _)) => + (match (string_drop _s2983_ _s2984_) with + | _s2985_ => + (match (hex_bits_5_matches_prefix _s2985_) with + | Some (rs1,(existT _ _s2986_ _)) => + (match (string_drop _s2985_ _s2986_) with + | _s2987_ => + (sep_matches_prefix _s2987_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s2988_ _)) => + (match (string_drop _s2987_ _s2988_) with + | _s2989_ => + (csr_name_map_matches_prefix _s2989_) >>= fun w__5 : option ((mword 12 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some + (csr,(existT _ _s2990_ _)) => + match (string_drop _s2989_ + _s2990_) with + | s_ => + Some + ((op, rd, rs1, csr, s_)) + end + | _ => None + end) + : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + else returnm (None : option ((csrop * mword 5 * mword 5 * mword 12 * string)))) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))). + +Definition _s2950_ (_s2951_ : string) +: M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) := + + (match _s2951_ with + | _s2952_ => + (amo_mnemonic_matches_prefix _s2952_) >>= fun w__0 : option ((amoop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2953_ _)) => + let _s2954_ := string_drop _s2952_ _s2953_ in + (if ((string_startswith _s2954_ ".")) then + (match (string_drop _s2954_ (projT1 (string_length "."))) with + | _s2955_ => + (size_mnemonic_matches_prefix _s2955_) >>= fun w__1 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (width,(existT _ _s2956_ _)) => + (match (string_drop _s2955_ _s2956_) with + | _s2957_ => + (maybe_aq_matches_prefix _s2957_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (aq,(existT _ _s2958_ _)) => + (match (string_drop _s2957_ _s2958_) with + | _s2959_ => + (maybe_rl_matches_prefix _s2959_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rl,(existT _ _s2960_ _)) => + (match (string_drop _s2959_ _s2960_) with + | _s2961_ => + (spc_matches_prefix _s2961_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s2962_ _)) => + (match (string_drop _s2961_ _s2962_) with + | _s2963_ => + (reg_name_matches_prefix _s2963_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (rd,(existT _ _s2964_ _)) => + (match (string_drop _s2963_ _s2964_) with + | _s2965_ => + (sep_matches_prefix _s2965_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (tt,(existT _ _s2966_ _)) => + (match (string_drop _s2965_ _s2966_) with + | _s2967_ => + (reg_name_matches_prefix _s2967_) >>= fun w__7 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__7 with + | Some (rs1,(existT _ _s2968_ _)) => + (match (string_drop _s2967_ + _s2968_) with + | _s2969_ => + (sep_matches_prefix + _s2969_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__8 with + | Some + (tt,(existT _ _s2970_ _)) => + (match (string_drop + _s2969_ + _s2970_) with + | _s2971_ => + (reg_name_matches_prefix + _s2971_) >>= fun w__9 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__9 with + | Some + (rs2,(existT _ _s2972_ _)) => + match (string_drop + _s2971_ + _s2972_) with + | s_ => + Some + ((op, width, aq, rl, rd, rs1, rs2, s_)) + end + | _ => + None + end) + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + else + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2928_ (_s2929_ : string) +: M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) := + + let _s2930_ := _s2929_ in + (if ((string_startswith _s2930_ "sc.")) then + (match (string_drop _s2930_ (projT1 (string_length "sc."))) with + | _s2931_ => + (size_mnemonic_matches_prefix _s2931_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s2932_ _)) => + (match (string_drop _s2931_ _s2932_) with + | _s2933_ => + (maybe_aq_matches_prefix _s2933_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (aq,(existT _ _s2934_ _)) => + (match (string_drop _s2933_ _s2934_) with + | _s2935_ => + (maybe_rl_matches_prefix _s2935_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rl,(existT _ _s2936_ _)) => + (match (string_drop _s2935_ _s2936_) with + | _s2937_ => + (spc_matches_prefix _s2937_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2938_ _)) => + (match (string_drop _s2937_ _s2938_) with + | _s2939_ => + (reg_name_matches_prefix _s2939_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rd,(existT _ _s2940_ _)) => + (match (string_drop _s2939_ _s2940_) with + | _s2941_ => + (sep_matches_prefix _s2941_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2942_ _)) => + (match (string_drop _s2941_ _s2942_) with + | _s2943_ => + (reg_name_matches_prefix _s2943_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (rs1,(existT _ _s2944_ _)) => + (match (string_drop _s2943_ _s2944_) with + | _s2945_ => + (sep_matches_prefix _s2945_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__7 with + | Some (tt,(existT _ _s2946_ _)) => + (match (string_drop _s2945_ + _s2946_) with + | _s2947_ => + (reg_name_matches_prefix + _s2947_) >>= fun w__8 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__8 with + | Some + (rs2,(existT _ _s2948_ _)) => + match (string_drop + _s2947_ + _s2948_) with + | s_ => + Some + ((size, aq, rl, rd, rs1, rs2, s_)) + end + | _ => None + end) + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + else + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2910_ (_s2911_ : string) +: M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) := + + let _s2912_ := _s2911_ in + (if ((string_startswith _s2912_ "lr.")) then + (match (string_drop _s2912_ (projT1 (string_length "lr."))) with + | _s2913_ => + (size_mnemonic_matches_prefix _s2913_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s2914_ _)) => + (match (string_drop _s2913_ _s2914_) with + | _s2915_ => + (maybe_aq_matches_prefix _s2915_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (aq,(existT _ _s2916_ _)) => + (match (string_drop _s2915_ _s2916_) with + | _s2917_ => + (maybe_rl_matches_prefix _s2917_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rl,(existT _ _s2918_ _)) => + (match (string_drop _s2917_ _s2918_) with + | _s2919_ => + (spc_matches_prefix _s2919_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2920_ _)) => + (match (string_drop _s2919_ _s2920_) with + | _s2921_ => + (reg_name_matches_prefix _s2921_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rd,(existT _ _s2922_ _)) => + (match (string_drop _s2921_ _s2922_) with + | _s2923_ => + (sep_matches_prefix _s2923_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2924_ _)) => + (match (string_drop _s2923_ _s2924_) with + | _s2925_ => + (reg_name_matches_prefix _s2925_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs1,(existT _ _s2926_ _)) => + match (string_drop _s2925_ + _s2926_) with + | s_ => + Some + ((size, aq, rl, rd, rs1, s_)) + end + | _ => None + end) + : option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * string)))) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))). + +Definition _s2898_ (_s2899_ : string) +: M (option ((mword 5 * mword 5 * string))) := + + let _s2900_ := _s2899_ in + (if ((string_startswith _s2900_ "sfence.vma")) then + (match (string_drop _s2900_ (projT1 (string_length "sfence.vma"))) with + | _s2901_ => + (spc_matches_prefix _s2901_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2902_ _)) => + (match (string_drop _s2901_ _s2902_) with + | _s2903_ => + (reg_name_matches_prefix _s2903_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs1,(existT _ _s2904_ _)) => + (match (string_drop _s2903_ _s2904_) with + | _s2905_ => + (sep_matches_prefix _s2905_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2906_ _)) => + (match (string_drop _s2905_ _s2906_) with + | _s2907_ => + (reg_name_matches_prefix _s2907_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s2908_ _)) => + match (string_drop _s2907_ _s2908_) with + | s_ => Some ((rs1, rs2, s_)) + end + | _ => None + end) + : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + else returnm (None : option ((mword 5 * mword 5 * string)))) + : M (option ((mword 5 * mword 5 * string))). + +Definition _s2894_ (_s2895_ : string) +: option string := + + let _s2896_ := _s2895_ in + if ((string_startswith _s2896_ "wfi")) then + match (string_drop _s2896_ (projT1 (string_length "wfi"))) with | s_ => Some (s_) end + else None. + +Definition _s2890_ (_s2891_ : string) +: option string := + + let _s2892_ := _s2891_ in + if ((string_startswith _s2892_ "ebreak")) then + match (string_drop _s2892_ (projT1 (string_length "ebreak"))) with | s_ => Some (s_) end + else None. + +Definition _s2886_ (_s2887_ : string) +: option string := + + let _s2888_ := _s2887_ in + if ((string_startswith _s2888_ "sret")) then + match (string_drop _s2888_ (projT1 (string_length "sret"))) with | s_ => Some (s_) end + else None. + +Definition _s2882_ (_s2883_ : string) +: option string := + + let _s2884_ := _s2883_ in + if ((string_startswith _s2884_ "mret")) then + match (string_drop _s2884_ (projT1 (string_length "mret"))) with | s_ => Some (s_) end + else None. + +Definition _s2878_ (_s2879_ : string) +: option string := + + let _s2880_ := _s2879_ in + if ((string_startswith _s2880_ "ecall")) then + match (string_drop _s2880_ (projT1 (string_length "ecall"))) with | s_ => Some (s_) end + else None. + +Definition _s2874_ (_s2875_ : string) +: option string := + + let _s2876_ := _s2875_ in + if ((string_startswith _s2876_ "fence.i")) then + match (string_drop _s2876_ (projT1 (string_length "fence.i"))) with | s_ => Some (s_) end + else None. + +Definition _s2862_ (_s2863_ : string) +: M (option ((mword 4 * mword 4 * string))) := + + let _s2864_ := _s2863_ in + (if ((string_startswith _s2864_ "fence.tso")) then + (match (string_drop _s2864_ (projT1 (string_length "fence.tso"))) with + | _s2865_ => + (spc_matches_prefix _s2865_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2866_ _)) => + (match (string_drop _s2865_ _s2866_) with + | _s2867_ => + (fence_bits_matches_prefix _s2867_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (pred,(existT _ _s2868_ _)) => + (match (string_drop _s2867_ _s2868_) with + | _s2869_ => + (sep_matches_prefix _s2869_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2870_ _)) => + (match (string_drop _s2869_ _s2870_) with + | _s2871_ => + (fence_bits_matches_prefix _s2871_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (succ,(existT _ _s2872_ _)) => + match (string_drop _s2871_ _s2872_) with + | s_ => Some ((pred, succ, s_)) + end + | _ => None + end) + : option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + | _ => returnm (None : option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + | _ => returnm (None : option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + | _ => returnm (None : option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + else returnm (None : option ((mword 4 * mword 4 * string)))) + : M (option ((mword 4 * mword 4 * string))). + +Definition _s2850_ (_s2851_ : string) +: M (option ((mword 4 * mword 4 * string))) := + + let _s2852_ := _s2851_ in + (if ((string_startswith _s2852_ "fence")) then + (match (string_drop _s2852_ (projT1 (string_length "fence"))) with + | _s2853_ => + (spc_matches_prefix _s2853_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2854_ _)) => + (match (string_drop _s2853_ _s2854_) with + | _s2855_ => + (fence_bits_matches_prefix _s2855_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (pred,(existT _ _s2856_ _)) => + (match (string_drop _s2855_ _s2856_) with + | _s2857_ => + (sep_matches_prefix _s2857_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2858_ _)) => + (match (string_drop _s2857_ _s2858_) with + | _s2859_ => + (fence_bits_matches_prefix _s2859_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (succ,(existT _ _s2860_ _)) => + match (string_drop _s2859_ _s2860_) with + | s_ => Some ((pred, succ, s_)) + end + | _ => None + end) + : option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + | _ => returnm (None : option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + | _ => returnm (None : option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + | _ => returnm (None : option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + else returnm (None : option ((mword 4 * mword 4 * string)))) + : M (option ((mword 4 * mword 4 * string))). + +Definition _s2831_ (_s2832_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5 * string))) := + + let _s2833_ := _s2832_ in + (if ((string_startswith _s2833_ "rem")) then + (match (string_drop _s2833_ (projT1 (string_length "rem"))) with + | _s2834_ => + (maybe_not_u_matches_prefix _s2834_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s2835_ _)) => + let _s2836_ := string_drop _s2834_ _s2835_ in + (if ((string_startswith _s2836_ "w")) then + (match (string_drop _s2836_ (projT1 (string_length "w"))) with + | _s2837_ => + (spc_matches_prefix _s2837_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2838_ _)) => + (match (string_drop _s2837_ _s2838_) with + | _s2839_ => + (reg_name_matches_prefix _s2839_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2840_ _)) => + (match (string_drop _s2839_ _s2840_) with + | _s2841_ => + (sep_matches_prefix _s2841_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2842_ _)) => + (match (string_drop _s2841_ _s2842_) with + | _s2843_ => + (reg_name_matches_prefix _s2843_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s2844_ _)) => + (match (string_drop _s2843_ _s2844_) with + | _s2845_ => + (sep_matches_prefix _s2845_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2846_ _)) => + (match (string_drop _s2845_ _s2846_) with + | _s2847_ => + (reg_name_matches_prefix _s2847_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s2848_ _)) => + match (string_drop _s2847_ + _s2848_) with + | s_ => + Some + ((s, rd, rs1, rs2, s_)) + end + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2812_ (_s2813_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5 * string))) := + + let _s2814_ := _s2813_ in + (if ((string_startswith _s2814_ "div")) then + (match (string_drop _s2814_ (projT1 (string_length "div"))) with + | _s2815_ => + (maybe_not_u_matches_prefix _s2815_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s2816_ _)) => + let _s2817_ := string_drop _s2815_ _s2816_ in + (if ((string_startswith _s2817_ "w")) then + (match (string_drop _s2817_ (projT1 (string_length "w"))) with + | _s2818_ => + (spc_matches_prefix _s2818_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2819_ _)) => + (match (string_drop _s2818_ _s2819_) with + | _s2820_ => + (reg_name_matches_prefix _s2820_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2821_ _)) => + (match (string_drop _s2820_ _s2821_) with + | _s2822_ => + (sep_matches_prefix _s2822_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2823_ _)) => + (match (string_drop _s2822_ _s2823_) with + | _s2824_ => + (reg_name_matches_prefix _s2824_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s2825_ _)) => + (match (string_drop _s2824_ _s2825_) with + | _s2826_ => + (sep_matches_prefix _s2826_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2827_ _)) => + (match (string_drop _s2826_ _s2827_) with + | _s2828_ => + (reg_name_matches_prefix _s2828_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s2829_ _)) => + match (string_drop _s2828_ + _s2829_) with + | s_ => + Some + ((s, rd, rs1, rs2, s_)) + end + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2796_ (_s2797_ : string) +: M (option ((mword 5 * mword 5 * mword 5 * string))) := + + let _s2798_ := _s2797_ in + (if ((string_startswith _s2798_ "mulw")) then + (match (string_drop _s2798_ (projT1 (string_length "mulw"))) with + | _s2799_ => + (spc_matches_prefix _s2799_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2800_ _)) => + (match (string_drop _s2799_ _s2800_) with + | _s2801_ => + (reg_name_matches_prefix _s2801_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s2802_ _)) => + (match (string_drop _s2801_ _s2802_) with + | _s2803_ => + (sep_matches_prefix _s2803_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2804_ _)) => + (match (string_drop _s2803_ _s2804_) with + | _s2805_ => + (reg_name_matches_prefix _s2805_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rs1,(existT _ _s2806_ _)) => + (match (string_drop _s2805_ _s2806_) with + | _s2807_ => + (sep_matches_prefix _s2807_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s2808_ _)) => + (match (string_drop _s2807_ _s2808_) with + | _s2809_ => + (reg_name_matches_prefix _s2809_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (rs2,(existT _ _s2810_ _)) => + match (string_drop _s2809_ _s2810_) with + | s_ => Some ((rd, rs1, rs2, s_)) + end + | _ => None + end) + : option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + else returnm (None : option ((mword 5 * mword 5 * mword 5 * string)))) + : M (option ((mword 5 * mword 5 * mword 5 * string))). + +Definition _s2778_ (_s2779_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5 * string))) := + + let _s2780_ := _s2779_ in + (if ((string_startswith _s2780_ "rem")) then + (match (string_drop _s2780_ (projT1 (string_length "rem"))) with + | _s2781_ => + (maybe_not_u_matches_prefix _s2781_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s2782_ _)) => + (match (string_drop _s2781_ _s2782_) with + | _s2783_ => + (spc_matches_prefix _s2783_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2784_ _)) => + (match (string_drop _s2783_ _s2784_) with + | _s2785_ => + (reg_name_matches_prefix _s2785_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2786_ _)) => + (match (string_drop _s2785_ _s2786_) with + | _s2787_ => + (sep_matches_prefix _s2787_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2788_ _)) => + (match (string_drop _s2787_ _s2788_) with + | _s2789_ => + (reg_name_matches_prefix _s2789_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s2790_ _)) => + (match (string_drop _s2789_ _s2790_) with + | _s2791_ => + (sep_matches_prefix _s2791_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2792_ _)) => + (match (string_drop _s2791_ _s2792_) with + | _s2793_ => + (reg_name_matches_prefix _s2793_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s2794_ _)) => + match (string_drop _s2793_ + _s2794_) with + | s_ => + Some + ((s, rd, rs1, rs2, s_)) + end + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2760_ (_s2761_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5 * string))) := + + let _s2762_ := _s2761_ in + (if ((string_startswith _s2762_ "div")) then + (match (string_drop _s2762_ (projT1 (string_length "div"))) with + | _s2763_ => + (maybe_not_u_matches_prefix _s2763_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s2764_ _)) => + (match (string_drop _s2763_ _s2764_) with + | _s2765_ => + (spc_matches_prefix _s2765_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2766_ _)) => + (match (string_drop _s2765_ _s2766_) with + | _s2767_ => + (reg_name_matches_prefix _s2767_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2768_ _)) => + (match (string_drop _s2767_ _s2768_) with + | _s2769_ => + (sep_matches_prefix _s2769_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2770_ _)) => + (match (string_drop _s2769_ _s2770_) with + | _s2771_ => + (reg_name_matches_prefix _s2771_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s2772_ _)) => + (match (string_drop _s2771_ _s2772_) with + | _s2773_ => + (sep_matches_prefix _s2773_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2774_ _)) => + (match (string_drop _s2773_ _s2774_) with + | _s2775_ => + (reg_name_matches_prefix _s2775_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s2776_ _)) => + match (string_drop _s2775_ + _s2776_) with + | s_ => + Some + ((s, rd, rs1, rs2, s_)) + end + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2743_ (_s2744_ : string) +: M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) := + + (match _s2744_ with + | _s2745_ => + (mul_mnemonic_matches_prefix _s2745_) >>= fun w__0 : option (((bool * bool * bool) * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some ((high, signed1, signed2),(existT _ _s2746_ _)) => + (match (string_drop _s2745_ _s2746_) with + | _s2747_ => + (spc_matches_prefix _s2747_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2748_ _)) => + (match (string_drop _s2747_ _s2748_) with + | _s2749_ => + (reg_name_matches_prefix _s2749_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2750_ _)) => + (match (string_drop _s2749_ _s2750_) with + | _s2751_ => + (sep_matches_prefix _s2751_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2752_ _)) => + (match (string_drop _s2751_ _s2752_) with + | _s2753_ => + (reg_name_matches_prefix _s2753_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s2754_ _)) => + (match (string_drop _s2753_ _s2754_) with + | _s2755_ => + (sep_matches_prefix _s2755_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2756_ _)) => + (match (string_drop _s2755_ _s2756_) with + | _s2757_ => + (reg_name_matches_prefix _s2757_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (rs2,(existT _ _s2758_ _)) => + match (string_drop _s2757_ + _s2758_) with + | s_ => + Some + ((high, signed1, signed2, rd, rs1, rs2, s_)) + end + | _ => None + end) + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2728_ (_s2729_ : string) +: M (option ((sopw * mword 5 * mword 5 * mword 5 * string))) := + + (match _s2729_ with + | _s2730_ => + (shiftiwop_mnemonic_matches_prefix _s2730_) >>= fun w__0 : option ((sopw * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2731_ _)) => + (match (string_drop _s2730_ _s2731_) with + | _s2732_ => + (spc_matches_prefix _s2732_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2733_ _)) => + (match (string_drop _s2732_ _s2733_) with + | _s2734_ => + (reg_name_matches_prefix _s2734_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2735_ _)) => + (match (string_drop _s2734_ _s2735_) with + | _s2736_ => + (sep_matches_prefix _s2736_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2737_ _)) => + (match (string_drop _s2736_ _s2737_) with + | _s2738_ => + (reg_name_matches_prefix _s2738_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (rs1,(existT _ _s2739_ _)) => + match (string_drop _s2738_ _s2739_) with + | _s2740_ => + match (hex_bits_5_matches_prefix _s2740_) with + | Some (shamt,(existT _ _s2741_ _)) => + match (string_drop _s2740_ _s2741_) with + | s_ => Some ((op, rd, rs1, shamt, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((sopw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((sopw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None : option ((sopw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2711_ (_s2712_ : string) +: M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) := + + (match _s2712_ with + | _s2713_ => + (rtypew_mnemonic_matches_prefix _s2713_) >>= fun w__0 : option ((ropw * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2714_ _)) => + (match (string_drop _s2713_ _s2714_) with + | _s2715_ => + (spc_matches_prefix _s2715_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2716_ _)) => + (match (string_drop _s2715_ _s2716_) with + | _s2717_ => + (reg_name_matches_prefix _s2717_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2718_ _)) => + (match (string_drop _s2717_ _s2718_) with + | _s2719_ => + (sep_matches_prefix _s2719_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2720_ _)) => + (match (string_drop _s2719_ _s2720_) with + | _s2721_ => + (reg_name_matches_prefix _s2721_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s2722_ _)) => + (match (string_drop _s2721_ _s2722_) with + | _s2723_ => + (sep_matches_prefix _s2723_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2724_ _)) => + (match (string_drop _s2723_ _s2724_) with + | _s2725_ => + (reg_name_matches_prefix _s2725_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (rs2,(existT _ _s2726_ _)) => + match (string_drop _s2725_ + _s2726_) with + | s_ => + Some ((op, rd, rs1, rs2, s_)) + end + | _ => None + end) + : option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None : option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2694_ (_s2695_ : string) +: M (option ((sop * mword 5 * mword 5 * mword 5 * string))) := + + (match _s2695_ with + | _s2696_ => + (shiftw_mnemonic_matches_prefix _s2696_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2697_ _)) => + (match (string_drop _s2696_ _s2697_) with + | _s2698_ => + (spc_matches_prefix _s2698_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2699_ _)) => + (match (string_drop _s2698_ _s2699_) with + | _s2700_ => + (reg_name_matches_prefix _s2700_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2701_ _)) => + (match (string_drop _s2700_ _s2701_) with + | _s2702_ => + (sep_matches_prefix _s2702_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2703_ _)) => + (match (string_drop _s2702_ _s2703_) with + | _s2704_ => + (reg_name_matches_prefix _s2704_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s2705_ _)) => + (match (string_drop _s2704_ _s2705_) with + | _s2706_ => + (sep_matches_prefix _s2706_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (tt,(existT _ _s2707_ _)) => + match (string_drop _s2706_ _s2707_) with + | _s2708_ => + match (hex_bits_5_matches_prefix + _s2708_) with + | Some (shamt,(existT _ _s2709_ _)) => + match (string_drop _s2708_ _s2709_) with + | s_ => + Some ((op, rd, rs1, shamt, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None : option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2678_ (_s2679_ : string) +: M (option ((mword 5 * mword 5 * mword 12 * string))) := + + let _s2680_ := _s2679_ in + (if ((string_startswith _s2680_ "addiw")) then + (match (string_drop _s2680_ (projT1 (string_length "addiw"))) with + | _s2681_ => + (spc_matches_prefix _s2681_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2682_ _)) => + (match (string_drop _s2681_ _s2682_) with + | _s2683_ => + (reg_name_matches_prefix _s2683_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s2684_ _)) => + (match (string_drop _s2683_ _s2684_) with + | _s2685_ => + (sep_matches_prefix _s2685_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2686_ _)) => + (match (string_drop _s2685_ _s2686_) with + | _s2687_ => + (reg_name_matches_prefix _s2687_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rs1,(existT _ _s2688_ _)) => + (match (string_drop _s2687_ _s2688_) with + | _s2689_ => + (sep_matches_prefix _s2689_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s2690_ _)) => + match (string_drop _s2689_ _s2690_) with + | _s2691_ => + match (hex_bits_12_matches_prefix _s2691_) with + | Some (imm,(existT _ _s2692_ _)) => + match (string_drop _s2691_ _s2692_) with + | s_ => Some ((rd, rs1, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + else returnm (None : option ((mword 5 * mword 5 * mword 12 * string)))) + : M (option ((mword 5 * mword 5 * mword 12 * string))). + +Definition _s2656_ (_s2657_ : string) +: M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) := + + let _s2658_ := _s2657_ in + (if ((string_startswith _s2658_ "s")) then + (match (string_drop _s2658_ (projT1 (string_length "s"))) with + | _s2659_ => + (size_mnemonic_matches_prefix _s2659_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s2660_ _)) => + (match (string_drop _s2659_ _s2660_) with + | _s2661_ => + (maybe_aq_matches_prefix _s2661_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (aq,(existT _ _s2662_ _)) => + (match (string_drop _s2661_ _s2662_) with + | _s2663_ => + (maybe_rl_matches_prefix _s2663_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rl,(existT _ _s2664_ _)) => + (match (string_drop _s2663_ _s2664_) with + | _s2665_ => + (spc_matches_prefix _s2665_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2666_ _)) => + (match (string_drop _s2665_ _s2666_) with + | _s2667_ => + (reg_name_matches_prefix _s2667_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rd,(existT _ _s2668_ _)) => + (match (string_drop _s2667_ _s2668_) with + | _s2669_ => + (sep_matches_prefix _s2669_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2670_ _)) => + (match (string_drop _s2669_ _s2670_) with + | _s2671_ => + (reg_name_matches_prefix _s2671_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (rs1,(existT _ _s2672_ _)) => + (match (string_drop _s2671_ _s2672_) with + | _s2673_ => + (sep_matches_prefix _s2673_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__7 with + | Some + (tt,(existT _ _s2674_ _)) => + match (string_drop + _s2673_ + _s2674_) with + | _s2675_ => + match (hex_bits_12_matches_prefix + _s2675_) with + | Some + (imm,(existT _ _s2676_ _)) => + match (string_drop + _s2675_ + _s2676_) with + | s_ => + Some + ((size, aq, rl, rd, rs1, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + else + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string)))) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))). + +Definition _s2632_ (_s2633_ : string) +: M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) := + + let _s2634_ := _s2633_ in + (if ((string_startswith _s2634_ "l")) then + (match (string_drop _s2634_ (projT1 (string_length "l"))) with + | _s2635_ => + (size_mnemonic_matches_prefix _s2635_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s2636_ _)) => + (match (string_drop _s2635_ _s2636_) with + | _s2637_ => + (maybe_u_matches_prefix _s2637_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (is_unsigned,(existT _ _s2638_ _)) => + (match (string_drop _s2637_ _s2638_) with + | _s2639_ => + (maybe_aq_matches_prefix _s2639_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (aq,(existT _ _s2640_ _)) => + (match (string_drop _s2639_ _s2640_) with + | _s2641_ => + (maybe_rl_matches_prefix _s2641_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rl,(existT _ _s2642_ _)) => + (match (string_drop _s2641_ _s2642_) with + | _s2643_ => + (spc_matches_prefix _s2643_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s2644_ _)) => + (match (string_drop _s2643_ _s2644_) with + | _s2645_ => + (reg_name_matches_prefix _s2645_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (rd,(existT _ _s2646_ _)) => + (match (string_drop _s2645_ _s2646_) with + | _s2647_ => + (sep_matches_prefix _s2647_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (tt,(existT _ _s2648_ _)) => + (match (string_drop _s2647_ _s2648_) with + | _s2649_ => + (reg_name_matches_prefix _s2649_) >>= fun w__7 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__7 with + | Some (rs1,(existT _ _s2650_ _)) => + (match (string_drop _s2649_ + _s2650_) with + | _s2651_ => + (sep_matches_prefix + _s2651_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__8 with + | Some + (tt,(existT _ _s2652_ _)) => + match (string_drop + _s2651_ + _s2652_) with + | _s2653_ => + match (hex_bits_12_matches_prefix + _s2653_) with + | Some + (imm,(existT _ _s2654_ _)) => + match (string_drop + _s2653_ + _s2654_) with + | s_ => + Some + ((size, is_unsigned, aq, rl, rd, rs1, imm, s_)) + end + | _ => + None + end + end + | _ => None + end) + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + else + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string)))) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))). + +Definition _s2615_ (_s2616_ : string) +: M (option ((rop * mword 5 * mword 5 * mword 5 * string))) := + + (match _s2616_ with + | _s2617_ => + (rtype_mnemonic_matches_prefix _s2617_) >>= fun w__0 : option ((rop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2618_ _)) => + (match (string_drop _s2617_ _s2618_) with + | _s2619_ => + (spc_matches_prefix _s2619_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2620_ _)) => + (match (string_drop _s2619_ _s2620_) with + | _s2621_ => + (reg_name_matches_prefix _s2621_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2622_ _)) => + (match (string_drop _s2621_ _s2622_) with + | _s2623_ => + (sep_matches_prefix _s2623_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2624_ _)) => + (match (string_drop _s2623_ _s2624_) with + | _s2625_ => + (reg_name_matches_prefix _s2625_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s2626_ _)) => + (match (string_drop _s2625_ _s2626_) with + | _s2627_ => + (sep_matches_prefix _s2627_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2628_ _)) => + (match (string_drop _s2627_ _s2628_) with + | _s2629_ => + (reg_name_matches_prefix _s2629_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (rs2,(existT _ _s2630_ _)) => + match (string_drop _s2629_ + _s2630_) with + | s_ => + Some ((op, rd, rs1, rs2, s_)) + end + | _ => None + end) + : option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None : option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2600_ (_s2601_ : string) +: M (option ((sop * mword 5 * mword 5 * mword 6 * string))) := + + (match _s2601_ with + | _s2602_ => + (shiftiop_mnemonic_matches_prefix _s2602_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2603_ _)) => + (match (string_drop _s2602_ _s2603_) with + | _s2604_ => + (spc_matches_prefix _s2604_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2605_ _)) => + (match (string_drop _s2604_ _s2605_) with + | _s2606_ => + (reg_name_matches_prefix _s2606_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2607_ _)) => + (match (string_drop _s2606_ _s2607_) with + | _s2608_ => + (sep_matches_prefix _s2608_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2609_ _)) => + (match (string_drop _s2608_ _s2609_) with + | _s2610_ => + (reg_name_matches_prefix _s2610_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (rs1,(existT _ _s2611_ _)) => + match (string_drop _s2610_ _s2611_) with + | _s2612_ => + match (hex_bits_6_matches_prefix _s2612_) with + | Some (shamt,(existT _ _s2613_ _)) => + match (string_drop _s2612_ _s2613_) with + | s_ => Some ((op, rd, rs1, shamt, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((sop * mword 5 * mword 5 * mword 6 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6 * string))) + | _ => + returnm (None + : option ((sop * mword 5 * mword 5 * mword 6 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6 * string))) + | _ => + returnm (None : option ((sop * mword 5 * mword 5 * mword 6 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6 * string))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6 * string))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6 * string))). + +Definition _s2583_ (_s2584_ : string) +: M (option ((iop * mword 5 * mword 5 * mword 12 * string))) := + + (match _s2584_ with + | _s2585_ => + (itype_mnemonic_matches_prefix _s2585_) >>= fun w__0 : option ((iop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2586_ _)) => + (match (string_drop _s2585_ _s2586_) with + | _s2587_ => + (spc_matches_prefix _s2587_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2588_ _)) => + (match (string_drop _s2587_ _s2588_) with + | _s2589_ => + (reg_name_matches_prefix _s2589_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2590_ _)) => + (match (string_drop _s2589_ _s2590_) with + | _s2591_ => + (sep_matches_prefix _s2591_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2592_ _)) => + (match (string_drop _s2591_ _s2592_) with + | _s2593_ => + (reg_name_matches_prefix _s2593_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s2594_ _)) => + (match (string_drop _s2593_ _s2594_) with + | _s2595_ => + (sep_matches_prefix _s2595_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (tt,(existT _ _s2596_ _)) => + match (string_drop _s2595_ _s2596_) with + | _s2597_ => + match (hex_bits_12_matches_prefix + _s2597_) with + | Some (imm,(existT _ _s2598_ _)) => + match (string_drop _s2597_ _s2598_) with + | s_ => + Some ((op, rd, rs1, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None : option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))). + +Definition _s2566_ (_s2567_ : string) +: M (option ((bop * mword 5 * mword 5 * mword 13 * string))) := + + (match _s2567_ with + | _s2568_ => + (btype_mnemonic_matches_prefix _s2568_) >>= fun w__0 : option ((bop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2569_ _)) => + (match (string_drop _s2568_ _s2569_) with + | _s2570_ => + (spc_matches_prefix _s2570_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2571_ _)) => + (match (string_drop _s2570_ _s2571_) with + | _s2572_ => + (reg_name_matches_prefix _s2572_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rs1,(existT _ _s2573_ _)) => + (match (string_drop _s2572_ _s2573_) with + | _s2574_ => + (sep_matches_prefix _s2574_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2575_ _)) => + (match (string_drop _s2574_ _s2575_) with + | _s2576_ => + (reg_name_matches_prefix _s2576_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs2,(existT _ _s2577_ _)) => + (match (string_drop _s2576_ _s2577_) with + | _s2578_ => + (sep_matches_prefix _s2578_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (tt,(existT _ _s2579_ _)) => + match (string_drop _s2578_ _s2579_) with + | _s2580_ => + match (hex_bits_13_matches_prefix + _s2580_) with + | Some (imm,(existT _ _s2581_ _)) => + match (string_drop _s2580_ _s2581_) with + | s_ => + Some ((op, rs1, rs2, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))) + | _ => + returnm (None + : option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))) + | _ => + returnm (None + : option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))) + | _ => + returnm (None : option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))) + | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))) + | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))). + +Definition _s2550_ (_s2551_ : string) +: M (option ((mword 5 * mword 5 * mword 12 * string))) := + + let _s2552_ := _s2551_ in + (if ((string_startswith _s2552_ "jalr")) then + (match (string_drop _s2552_ (projT1 (string_length "jalr"))) with + | _s2553_ => + (spc_matches_prefix _s2553_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2554_ _)) => + (match (string_drop _s2553_ _s2554_) with + | _s2555_ => + (reg_name_matches_prefix _s2555_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s2556_ _)) => + (match (string_drop _s2555_ _s2556_) with + | _s2557_ => + (sep_matches_prefix _s2557_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2558_ _)) => + (match (string_drop _s2557_ _s2558_) with + | _s2559_ => + (reg_name_matches_prefix _s2559_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rs1,(existT _ _s2560_ _)) => + (match (string_drop _s2559_ _s2560_) with + | _s2561_ => + (sep_matches_prefix _s2561_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s2562_ _)) => + match (string_drop _s2561_ _s2562_) with + | _s2563_ => + match (hex_bits_12_matches_prefix _s2563_) with + | Some (imm,(existT _ _s2564_ _)) => + match (string_drop _s2563_ _s2564_) with + | s_ => Some ((rd, rs1, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + else returnm (None : option ((mword 5 * mword 5 * mword 12 * string)))) + : M (option ((mword 5 * mword 5 * mword 12 * string))). + +Definition _s2538_ (_s2539_ : string) +: M (option ((mword 5 * mword 21 * string))) := + + let _s2540_ := _s2539_ in + (if ((string_startswith _s2540_ "jal")) then + (match (string_drop _s2540_ (projT1 (string_length "jal"))) with + | _s2541_ => + (spc_matches_prefix _s2541_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2542_ _)) => + (match (string_drop _s2541_ _s2542_) with + | _s2543_ => + (reg_name_matches_prefix _s2543_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s2544_ _)) => + (match (string_drop _s2543_ _s2544_) with + | _s2545_ => + (sep_matches_prefix _s2545_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2546_ _)) => + match (string_drop _s2545_ _s2546_) with + | _s2547_ => + match (hex_bits_21_matches_prefix _s2547_) with + | Some (imm,(existT _ _s2548_ _)) => + match (string_drop _s2547_ _s2548_) with + | s_ => Some ((rd, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 21 * string))) + end) + : M (option ((mword 5 * mword 21 * string))) + | _ => returnm (None : option ((mword 5 * mword 21 * string))) + end) + : M (option ((mword 5 * mword 21 * string))) + end) + : M (option ((mword 5 * mword 21 * string))) + | _ => returnm (None : option ((mword 5 * mword 21 * string))) + end) + : M (option ((mword 5 * mword 21 * string))) + end) + : M (option ((mword 5 * mword 21 * string))) + else returnm (None : option ((mword 5 * mword 21 * string)))) + : M (option ((mword 5 * mword 21 * string))). + +Definition _s2525_ (_s2526_ : string) +: M (option ((uop * mword 5 * mword 20 * string))) := + + (match _s2526_ with + | _s2527_ => + (utype_mnemonic_matches_prefix _s2527_) >>= fun w__0 : option ((uop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2528_ _)) => + (match (string_drop _s2527_ _s2528_) with + | _s2529_ => + (spc_matches_prefix _s2529_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2530_ _)) => + (match (string_drop _s2529_ _s2530_) with + | _s2531_ => + (reg_name_matches_prefix _s2531_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2532_ _)) => + (match (string_drop _s2531_ _s2532_) with + | _s2533_ => + (sep_matches_prefix _s2533_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (tt,(existT _ _s2534_ _)) => + match (string_drop _s2533_ _s2534_) with + | _s2535_ => + match (hex_bits_20_matches_prefix _s2535_) with + | Some (imm,(existT _ _s2536_ _)) => + match (string_drop _s2535_ _s2536_) with + | s_ => Some ((op, rd, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((uop * mword 5 * mword 20 * string))) + end) + : M (option ((uop * mword 5 * mword 20 * string))) + | _ => returnm (None : option ((uop * mword 5 * mword 20 * string))) + end) + : M (option ((uop * mword 5 * mword 20 * string))) + end) + : M (option ((uop * mword 5 * mword 20 * string))) + | _ => returnm (None : option ((uop * mword 5 * mword 20 * string))) + end) + : M (option ((uop * mword 5 * mword 20 * string))) + end) + : M (option ((uop * mword 5 * mword 20 * string))) + | _ => returnm (None : option ((uop * mword 5 * mword 20 * string))) + end) + : M (option ((uop * mword 5 * mword 20 * string))) + end) + : M (option ((uop * mword 5 * mword 20 * string))). + +Definition assembly_matches_prefix (arg_ : string) +: M (option ((ast * {n : Z & ArithFact (n >= 0)}))) := + + let _s2537_ := arg_ in + (_s2525_ _s2537_) >>= fun w__0 : option ((uop * mword 5 * mword 20 * string)) => + (if ((match w__0 with | Some (op,rd,imm,s_) => true | _ => false end)) then + (_s2525_ _s2537_) >>= fun w__1 : option ((uop * mword 5 * mword 20 * string)) => + (match w__1 with + | Some (op,rd,imm,s_) => + returnm ((Some + ((UTYPE + ((imm, rd, op)), build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2538_ _s2537_) >>= fun w__4 : option ((mword 5 * mword 21 * string)) => + (if ((match w__4 with | Some (rd,imm,s_) => true | _ => false end)) then + (_s2538_ _s2537_) >>= fun w__5 : option ((mword 5 * mword 21 * string)) => + (match w__5 with + | Some (rd,imm,s_) => + returnm ((Some + ((RISCV_JAL + ((imm, rd)), build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2550_ _s2537_) >>= fun w__8 : option ((mword 5 * mword 5 * mword 12 * string)) => + (if ((match w__8 with | Some (rd,rs1,imm,s_) => true | _ => false end)) then + (_s2550_ _s2537_) >>= fun w__9 : option ((mword 5 * mword 5 * mword 12 * string)) => + (match w__9 with + | Some (rd,rs1,imm,s_) => + returnm ((Some + ((RISCV_JALR + ((imm, rs1, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2566_ _s2537_) >>= fun w__12 : option ((bop * mword 5 * mword 5 * mword 13 * string)) => + (if ((match w__12 with | Some (op,rs1,rs2,imm,s_) => true | _ => false end)) then + (_s2566_ _s2537_) >>= fun w__13 : option ((bop * mword 5 * mword 5 * mword 13 * string)) => + (match w__13 with + | Some (op,rs1,rs2,imm,s_) => + returnm ((Some + ((BTYPE + ((imm, rs2, rs1, op)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2583_ _s2537_) >>= fun w__16 : option ((iop * mword 5 * mword 5 * mword 12 * string)) => + (if ((match w__16 with | Some (op,rd,rs1,imm,s_) => true | _ => false end)) then + (_s2583_ _s2537_) >>= fun w__17 : option ((iop * mword 5 * mword 5 * mword 12 * string)) => + (match w__17 with + | Some (op,rd,rs1,imm,s_) => + returnm ((Some + ((ITYPE + ((imm, rs1, rd, op)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2600_ _s2537_) >>= fun w__20 : option ((sop * mword 5 * mword 5 * mword 6 * string)) => + (if ((match w__20 with | Some (op,rd,rs1,shamt,s_) => true | _ => false end)) then + (_s2600_ _s2537_) >>= fun w__21 : option ((sop * mword 5 * mword 5 * mword 6 * string)) => + (match w__21 with + | Some (op,rd,rs1,shamt,s_) => + returnm ((Some + ((SHIFTIOP + ((shamt, rs1, rd, op)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2615_ _s2537_) >>= fun w__24 : option ((rop * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__24 with | Some (op,rd,rs1,rs2,s_) => true | _ => false end)) + then + (_s2615_ _s2537_) >>= fun w__25 : option ((rop * mword 5 * mword 5 * mword 5 * string)) => + (match w__25 with + | Some (op,rd,rs1,rs2,s_) => + returnm ((Some + ((RTYPE + ((rs2, rs1, rd, op)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2632_ _s2537_) >>= fun w__28 : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string)) => + (if ((match w__28 with + | Some (size,is_unsigned,aq,rl,rd,rs1,imm,s_) => true + | _ => false + end)) then + (_s2632_ _s2537_) >>= fun w__29 : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string)) => + (match w__29 with + | Some (size,is_unsigned,aq,rl,rd,rs1,imm,s_) => + returnm ((Some + ((LOAD + ((imm, rs1, rd, is_unsigned, size, aq, rl)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2656_ _s2537_) >>= fun w__32 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string)) => + (if ((match w__32 with + | Some (size,aq,rl,rd,rs1,imm,s_) => true + | _ => false + end)) then + (_s2656_ _s2537_) >>= fun w__33 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string)) => + (match w__33 with + | Some (size,aq,rl,rd,rs1,imm,s_) => + returnm ((Some + ((STORE + ((imm, rs1, rd, size, aq, rl)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2678_ _s2537_) >>= fun w__36 : option ((mword 5 * mword 5 * mword 12 * string)) => + (if ((match w__36 with | Some (rd,rs1,imm,s_) => true | _ => false end)) + then + (_s2678_ _s2537_) >>= fun w__37 : option ((mword 5 * mword 5 * mword 12 * string)) => + (match w__37 with + | Some (rd,rs1,imm,s_) => + returnm ((Some + ((ADDIW + ((imm, rs1, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => + exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2694_ _s2537_) >>= fun w__40 : option ((sop * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__40 with + | Some (op,rd,rs1,shamt,s_) => true + | _ => false + end)) then + (_s2694_ _s2537_) >>= fun w__41 : option ((sop * mword 5 * mword 5 * mword 5 * string)) => + (match w__41 with + | Some (op,rd,rs1,shamt,s_) => + returnm ((Some + ((SHIFTW + ((shamt, rs1, rd, op)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => + exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2711_ _s2537_) >>= fun w__44 : option ((ropw * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__44 with + | Some (op,rd,rs1,rs2,s_) => true + | _ => false + end)) then + (_s2711_ _s2537_) >>= fun w__45 : option ((ropw * mword 5 * mword 5 * mword 5 * string)) => + (match w__45 with + | Some (op,rd,rs1,rs2,s_) => + returnm ((Some + ((RTYPEW + ((rs2, rs1, rd, op)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2728_ _s2537_) >>= fun w__48 : option ((sopw * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__48 with + | Some (op,rd,rs1,shamt,s_) => true + | _ => false + end)) then + (_s2728_ _s2537_) >>= fun w__49 : option ((sopw * mword 5 * mword 5 * mword 5 * string)) => + (match w__49 with + | Some (op,rd,rs1,shamt,s_) => + returnm ((Some + ((SHIFTIWOP + ((shamt, rs1, rd, op)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2743_ _s2537_) >>= fun w__52 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__52 with + | Some (high,signed1,signed2,rd,rs1,rs2,s_) => true + | _ => false + end)) then + (_s2743_ _s2537_) >>= fun w__53 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)) => + (match w__53 with + | Some (high,signed1,signed2,rd,rs1,rs2,s_) => + returnm ((Some + ((MUL + ((rs2, rs1, rd, high, signed1, signed2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2760_ _s2537_) >>= fun w__56 : option ((bool * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__56 with + | Some (s,rd,rs1,rs2,s_) => true + | _ => false + end)) then + (_s2760_ _s2537_) >>= fun w__57 : option ((bool * mword 5 * mword 5 * mword 5 * string)) => + (match w__57 with + | Some (s,rd,rs1,rs2,s_) => + returnm ((Some + ((DIV + ((rs2, rs1, rd, s)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2778_ _s2537_) >>= fun w__60 : option ((bool * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__60 with + | Some (s,rd,rs1,rs2,s_) => true + | _ => false + end)) then + (_s2778_ _s2537_) >>= fun w__61 : option ((bool * mword 5 * mword 5 * mword 5 * string)) => + (match w__61 with + | Some (s,rd,rs1,rs2,s_) => + returnm ((Some + ((REM + ((rs2, rs1, rd, s)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2796_ _s2537_) >>= fun w__64 : option ((mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__64 with + | Some (rd,rs1,rs2,s_) => true + | _ => false + end)) then + (_s2796_ _s2537_) >>= fun w__65 : option ((mword 5 * mword 5 * mword 5 * string)) => + (match w__65 with + | Some (rd,rs1,rs2,s_) => + returnm ((Some + ((MULW + ((rs2, rs1, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s2812_ _s2537_) >>= fun w__68 : option ((bool * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__68 with + | Some (s,rd,rs1,rs2,s_) => true + | _ => false + end)) then + (_s2812_ _s2537_) >>= fun w__69 : option ((bool * mword 5 * mword 5 * mword 5 * string)) => + (match w__69 with + | Some (s,rd,rs1,rs2,s_) => + returnm ((Some + ((DIVW + ((rs2, rs1, rd, s)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s2831_ _s2537_) >>= fun w__72 : option ((bool * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__72 with + | Some (s,rd,rs1,rs2,s_) => true + | _ => false + end)) then + (_s2831_ _s2537_) >>= fun w__73 : option ((bool * mword 5 * mword 5 * mword 5 * string)) => + (match w__73 with + | Some (s,rd,rs1,rs2,s_) => + returnm ((Some + ((REMW + ((rs2, rs1, rd, s)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s2850_ _s2537_) >>= fun w__76 : option ((mword 4 * mword 4 * string)) => + (if ((match w__76 with + | Some (pred,succ,s_) => true + | _ => false + end)) then + (_s2850_ _s2537_) >>= fun w__77 : option ((mword 4 * mword 4 * string)) => + (match w__77 with + | Some (pred,succ,s_) => + returnm ((Some + ((FENCE + ((pred, succ)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s2862_ _s2537_) >>= fun w__80 : option ((mword 4 * mword 4 * string)) => + (if ((match w__80 with + | Some (pred,succ,s_) => true + | _ => false + end)) then + (_s2862_ _s2537_) >>= fun w__81 : option ((mword 4 * mword 4 * string)) => + (match w__81 with + | Some (pred,succ,s_) => + returnm ((Some + ((FENCE_TSO + ((pred, succ)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else if ((match (_s2874_ _s2537_) with + | Some (s_) => true + | _ => false + end)) then + (match (_s2874_ _s2537_) with + | Some (s_) => + returnm ((Some + ((FENCEI + (tt), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else if ((match (_s2878_ _s2537_) with + | Some (s_) => true + | _ => false + end)) then + (match (_s2878_ _s2537_) with + | Some (s_) => + returnm ((Some + ((ECALL + (tt), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else if ((match (_s2882_ _s2537_) with + | Some (s_) => true + | _ => false + end)) then + (match (_s2882_ _s2537_) with + | Some (s_) => + returnm ((Some + ((MRET + (tt), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else if ((match (_s2886_ _s2537_) with + | Some (s_) => true + | _ => false + end)) then + (match (_s2886_ _s2537_) with + | Some (s_) => + returnm ((Some + ((SRET + (tt), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else if ((match (_s2890_ _s2537_) with + | Some (s_) => true + | _ => false + end)) then + (match (_s2890_ _s2537_) with + | Some (s_) => + returnm ((Some + ((EBREAK + (tt), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else if ((match (_s2894_ _s2537_) with + | Some (s_) => true + | _ => false + end)) then + (match (_s2894_ _s2537_) with + | Some (s_) => + returnm ((Some + ((WFI + (tt), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s2898_ _s2537_) >>= fun w__96 : option ((mword 5 * mword 5 * string)) => + (if ((match w__96 with + | Some (rs1,rs2,s_) => true + | _ => false + end)) then + (_s2898_ _s2537_) >>= fun w__97 : option ((mword 5 * mword 5 * string)) => + (match w__97 with + | Some (rs1,rs2,s_) => + returnm ((Some + ((SFENCE_VMA + ((rs1, rs2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s2910_ _s2537_) >>= fun w__100 : option ((word_width * bool * bool * mword 5 * mword 5 * string)) => + (if ((match w__100 with + | Some + (size,aq,rl,rd,rs1,s_) => + true + | _ => false + end)) then + (_s2910_ _s2537_) >>= fun w__101 : option ((word_width * bool * bool * mword 5 * mword 5 * string)) => + (match w__101 with + | Some + (size,aq,rl,rd,rs1,s_) => + returnm ((Some + ((LOADRES + ((aq, rl, rs1, size, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s2928_ _s2537_) >>= fun w__104 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__104 with + | Some + (size,aq,rl,rd,rs1,rs2,s_) => + true + | _ => false + end)) then + (_s2928_ _s2537_) >>= fun w__105 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)) => + (match w__105 with + | Some + (size,aq,rl,rd,rs1,rs2,s_) => + returnm ((Some + ((STORECON + ((aq, rl, rs2, rs1, size, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s2950_ _s2537_) >>= fun w__108 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__108 with + | Some + (op,width,aq,rl,rd,rs1,rs2,s_) => + true + | _ => false + end)) then + (_s2950_ _s2537_) >>= fun w__109 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)) => + (match w__109 with + | Some + (op,width,aq,rl,rd,rs1,rs2,s_) => + returnm ((Some + ((AMO + ((op, aq, rl, rs2, rs1, width, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s2974_ _s2537_) >>= fun w__112 : option ((csrop * mword 5 * mword 5 * mword 12 * string)) => + (if ((match w__112 with + | Some + (op,rd,rs1,csr,s_) => + true + | _ => false + end)) then + (_s2974_ _s2537_) >>= fun w__113 : option ((csrop * mword 5 * mword 5 * mword 12 * string)) => + (match w__113 with + | Some + (op,rd,rs1,csr,s_) => + returnm ((Some + ((CSR + ((csr, rs1, rd, true, op)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s2992_ _s2537_) >>= fun w__116 : option ((csrop * mword 5 * mword 5 * mword 12 * string)) => + (if ((match w__116 with + | Some + (op,rd,rs1,csr,s_) => + true + | _ => false + end)) then + (_s2992_ _s2537_) >>= fun w__117 : option ((csrop * mword 5 * mword 5 * mword 12 * string)) => + (match w__117 with + | Some + (op,rd,rs1,csr,s_) => + returnm ((Some + ((CSR + ((csr, rs1, rd, false, op)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else if ((match (_s3009_ + _s2537_) with + | Some + (s_) => + true + | _ => + false + end)) + then + (match (_s3009_ + _s2537_) with + | Some (s_) => + returnm ((Some + ((C_NOP + (tt), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3013_ _s2537_) >>= fun w__122 : option ((mword 3 * mword 8 * string)) => + (if ((match w__122 with + | Some + (rdc,nzimm,s_) => + neq_vec + nzimm + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] + : mword 8) + | _ => + false + end)) then + (_s3013_ + _s2537_) >>= fun w__123 : option ((mword 3 * mword 8 * string)) => + (match w__123 with + | Some + (rdc,nzimm,s_) => + returnm ((Some + ((C_ADDI4SPN + ((rdc, nzimm)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3025_ + _s2537_) >>= fun w__126 : option ((mword 3 * mword 3 * mword 5 * string)) => + (if ((match w__126 with + | Some + (rdc,rsc,uimm,s_) => + true + | _ => + false + end)) + then + (_s3025_ + _s2537_) >>= fun w__127 : option ((mword 3 * mword 3 * mword 5 * string)) => + (match w__127 with + | Some + (rdc,rsc,uimm,s_) => + returnm ((Some + ((C_LW + ((uimm, rsc, rdc)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3041_ + _s2537_) >>= fun w__130 : option ((mword 3 * mword 3 * mword 5 * string)) => + (if ((match w__130 with + | Some + (rdc,rsc,uimm,s_) => + true + | _ => + false + end)) + then + (_s3041_ + _s2537_) >>= fun w__131 : option ((mword 3 * mword 3 * mword 5 * string)) => + (match w__131 with + | Some + (rdc,rsc,uimm,s_) => + returnm ((Some + ((C_LD + ((uimm, rsc, rdc)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3057_ + _s2537_) >>= fun w__134 : option ((mword 3 * mword 3 * mword 5 * string)) => + (if ((match w__134 with + | Some + (rsc1,rsc2,uimm,s_) => + true + | _ => + false + end)) + then + (_s3057_ + _s2537_) >>= fun w__135 : option ((mword 3 * mword 3 * mword 5 * string)) => + (match w__135 with + | Some + (rsc1,rsc2,uimm,s_) => + returnm ((Some + ((C_SW + ((uimm, rsc1, rsc2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3073_ + _s2537_) >>= fun w__138 : option ((mword 3 * mword 3 * mword 5 * string)) => + (if ((match w__138 with + | Some + (rsc1,rsc2,uimm,s_) => + true + | _ => + false + end)) + then + (_s3073_ + _s2537_) >>= fun w__139 : option ((mword 3 * mword 3 * mword 5 * string)) => + (match w__139 with + | Some + (rsc1,rsc2,uimm,s_) => + returnm ((Some + ((C_SD + ((uimm, rsc1, rsc2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3089_ + _s2537_) >>= fun w__142 : option ((mword 5 * mword 6 * string)) => + (if + ((match w__142 with + | Some + (rsd,nzi,s_) => + andb + (neq_vec + nzi + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6)) + (neq_int + (projT1 (regbits_to_regno + rsd)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s3089_ + _s2537_) >>= fun w__143 : option ((mword 5 * mword 6 * string)) => + (match w__143 with + | Some + (rsd,nzi,s_) => + returnm ((Some + ((C_ADDI + ((nzi, rsd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3101_ + _s2537_) >>= fun w__146 : option ((mword 11 * string)) => + (if + ((match w__146 with + | Some + (imm,s_) => + true + | _ => + false + end)) + then + (_s3101_ + _s2537_) >>= fun w__147 : option ((mword 11 * string)) => + (match w__147 with + | Some + (imm,s_) => + returnm ((Some + ((C_JAL + (imm), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3109_ + _s2537_) >>= fun w__150 : option ((mword 5 * mword 6 * string)) => + (if + ((match w__150 with + | Some + (rsd,imm,s_) => + true + | _ => + false + end)) + then + (_s3109_ + _s2537_) >>= fun w__151 : option ((mword 5 * mword 6 * string)) => + (match w__151 with + | Some + (rsd,imm,s_) => + returnm ((Some + ((C_ADDIW + ((imm, rsd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3121_ + _s2537_) >>= fun w__154 : option ((mword 5 * mword 6 * string)) => + (if + ((match w__154 with + | Some + (rd,imm,s_) => + neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s3121_ + _s2537_) >>= fun w__155 : option ((mword 5 * mword 6 * string)) => + (match w__155 with + | Some + (rd,imm,s_) => + returnm ((Some + ((C_LI + ((imm, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3133_ + _s2537_) >>= fun w__158 : option ((mword 6 * string)) => + (if + ((match w__158 with + | Some + (imm,s_) => + neq_vec + imm + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6) + | _ => + false + end)) + then + (_s3133_ + _s2537_) >>= fun w__159 : option ((mword 6 * string)) => + (match w__159 with + | Some + (imm,s_) => + returnm ((Some + ((C_ADDI16SP + (imm), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3141_ + _s2537_) >>= fun w__162 : option ((mword 5 * mword 6 * string)) => + (if + ((match w__162 with + | Some + (rd,imm,s_) => + andb + (neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg))) + (andb + (neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + sp))) + (neq_vec + imm + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6))) + | _ => + false + end)) + then + (_s3141_ + _s2537_) >>= fun w__163 : option ((mword 5 * mword 6 * string)) => + (match w__163 with + | Some + (rd,imm,s_) => + returnm ((Some + ((C_LUI + ((imm, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3153_ + _s2537_) >>= fun w__166 : option ((mword 3 * mword 6 * string)) => + (if + ((match w__166 with + | Some + (rsd,shamt,s_) => + neq_vec + shamt + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6) + | _ => + false + end)) + then + (_s3153_ + _s2537_) >>= fun w__167 : option ((mword 3 * mword 6 * string)) => + (match w__167 with + | Some + (rsd,shamt,s_) => + returnm ((Some + ((C_SRLI + ((shamt, rsd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3165_ + _s2537_) >>= fun w__170 : option ((mword 3 * mword 6 * string)) => + (if + ((match w__170 with + | Some + (rsd,shamt,s_) => + neq_vec + shamt + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6) + | _ => + false + end)) + then + (_s3165_ + _s2537_) >>= fun w__171 : option ((mword 3 * mword 6 * string)) => + (match w__171 with + | Some + (rsd,shamt,s_) => + returnm ((Some + ((C_SRAI + ((shamt, rsd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3177_ + _s2537_) >>= fun w__174 : option ((mword 3 * mword 6 * string)) => + (if + ((match w__174 with + | Some + (rsd,imm,s_) => + true + | _ => + false + end)) + then + (_s3177_ + _s2537_) >>= fun w__175 : option ((mword 3 * mword 6 * string)) => + (match w__175 with + | Some + (rsd,imm,s_) => + returnm ((Some + ((C_ANDI + ((imm, rsd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3189_ + _s2537_) >>= fun w__178 : option ((mword 3 * mword 3 * string)) => + (if + ((match w__178 with + | Some + (rsd,rs2,s_) => + true + | _ => + false + end)) + then + (_s3189_ + _s2537_) >>= fun w__179 : option ((mword 3 * mword 3 * string)) => + (match w__179 with + | Some + (rsd,rs2,s_) => + returnm ((Some + ((C_SUB + ((rsd, rs2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3201_ + _s2537_) >>= fun w__182 : option ((mword 3 * mword 3 * string)) => + (if + ((match w__182 with + | Some + (rsd,rs2,s_) => + true + | _ => + false + end)) + then + (_s3201_ + _s2537_) >>= fun w__183 : option ((mword 3 * mword 3 * string)) => + (match w__183 with + | Some + (rsd,rs2,s_) => + returnm ((Some + ((C_XOR + ((rsd, rs2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3213_ + _s2537_) >>= fun w__186 : option ((mword 3 * mword 3 * string)) => + (if + ((match w__186 with + | Some + (rsd,rs2,s_) => + true + | _ => + false + end)) + then + (_s3213_ + _s2537_) >>= fun w__187 : option ((mword 3 * mword 3 * string)) => + (match w__187 with + | Some + (rsd,rs2,s_) => + returnm ((Some + ((C_OR + ((rsd, rs2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3225_ + _s2537_) >>= fun w__190 : option ((mword 3 * mword 3 * string)) => + (if + ((match w__190 with + | Some + (rsd,rs2,s_) => + true + | _ => + false + end)) + then + (_s3225_ + _s2537_) >>= fun w__191 : option ((mword 3 * mword 3 * string)) => + (match w__191 with + | Some + (rsd,rs2,s_) => + returnm ((Some + ((C_AND + ((rsd, rs2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3237_ + _s2537_) >>= fun w__194 : option ((mword 3 * mword 3 * string)) => + (if + ((match w__194 with + | Some + (rsd,rs2,s_) => + true + | _ => + false + end)) + then + (_s3237_ + _s2537_) >>= fun w__195 : option ((mword 3 * mword 3 * string)) => + (match w__195 with + | Some + (rsd,rs2,s_) => + returnm ((Some + ((C_SUBW + ((rsd, rs2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3249_ + _s2537_) >>= fun w__198 : option ((mword 3 * mword 3 * string)) => + (if + ((match w__198 with + | Some + (rsd,rs2,s_) => + true + | _ => + false + end)) + then + (_s3249_ + _s2537_) >>= fun w__199 : option ((mword 3 * mword 3 * string)) => + (match w__199 with + | Some + (rsd,rs2,s_) => + returnm ((Some + ((C_ADDW + ((rsd, rs2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3261_ + _s2537_) >>= fun w__202 : option ((mword 11 * string)) => + (if + ((match w__202 with + | Some + (imm,s_) => + true + | _ => + false + end)) + then + (_s3261_ + _s2537_) >>= fun w__203 : option ((mword 11 * string)) => + (match w__203 with + | Some + (imm,s_) => + returnm ((Some + ((C_J + (imm), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3269_ + _s2537_) >>= fun w__206 : option ((mword 3 * mword 8 * string)) => + (if + ((match w__206 with + | Some + (rs,imm,s_) => + true + | _ => + false + end)) + then + (_s3269_ + _s2537_) >>= fun w__207 : option ((mword 3 * mword 8 * string)) => + (match w__207 with + | Some + (rs,imm,s_) => + returnm ((Some + ((C_BEQZ + ((imm, rs)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3281_ + _s2537_) >>= fun w__210 : option ((mword 3 * mword 8 * string)) => + (if + ((match w__210 with + | Some + (rs,imm,s_) => + true + | _ => + false + end)) + then + (_s3281_ + _s2537_) >>= fun w__211 : option ((mword 3 * mword 8 * string)) => + (match w__211 with + | Some + (rs,imm,s_) => + returnm ((Some + ((C_BNEZ + ((imm, rs)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3293_ + _s2537_) >>= fun w__214 : option ((mword 5 * mword 6 * string)) => + (if + ((match w__214 with + | Some + (rsd,shamt,s_) => + andb + (neq_vec + shamt + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6)) + (neq_int + (projT1 (regbits_to_regno + rsd)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s3293_ + _s2537_) >>= fun w__215 : option ((mword 5 * mword 6 * string)) => + (match w__215 with + | Some + (rsd,shamt,s_) => + returnm ((Some + ((C_SLLI + ((shamt, rsd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3305_ + _s2537_) >>= fun w__218 : option ((mword 5 * mword 6 * string)) => + (if + ((match w__218 with + | Some + (rd,uimm,s_) => + neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s3305_ + _s2537_) >>= fun w__219 : option ((mword 5 * mword 6 * string)) => + (match w__219 with + | Some + (rd,uimm,s_) => + returnm ((Some + ((C_LWSP + ((uimm, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3317_ + _s2537_) >>= fun w__222 : option ((mword 5 * mword 6 * string)) => + (if + ((match w__222 with + | Some + (rd,uimm,s_) => + neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s3317_ + _s2537_) >>= fun w__223 : option ((mword 5 * mword 6 * string)) => + (match w__223 with + | Some + (rd,uimm,s_) => + returnm ((Some + ((C_LDSP + ((uimm, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3329_ + _s2537_) >>= fun w__226 : option ((mword 5 * mword 6 * string)) => + (if + ((match w__226 with + | Some + (rd,uimm,s_) => + true + | _ => + false + end)) + then + (_s3329_ + _s2537_) >>= fun w__227 : option ((mword 5 * mword 6 * string)) => + (match w__227 with + | Some + (rd,uimm,s_) => + returnm ((Some + ((C_SWSP + ((uimm, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3341_ + _s2537_) >>= fun w__230 : option ((mword 5 * mword 6 * string)) => + (if + ((match w__230 with + | Some + (rs2,uimm,s_) => + true + | _ => + false + end)) + then + (_s3341_ + _s2537_) >>= fun w__231 : option ((mword 5 * mword 6 * string)) => + (match w__231 with + | Some + (rs2,uimm,s_) => + returnm ((Some + ((C_SDSP + ((uimm, rs2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3353_ + _s2537_) >>= fun w__234 : option ((mword 5 * string)) => + (if + ((match w__234 with + | Some + (rs1,s_) => + neq_int + (projT1 (regbits_to_regno + rs1)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s3353_ + _s2537_) >>= fun w__235 : option ((mword 5 * string)) => + (match w__235 with + | Some + (rs1,s_) => + returnm ((Some + ((C_JR + (rs1), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3361_ + _s2537_) >>= fun w__238 : option ((mword 5 * string)) => + (if + ((match w__238 with + | Some + (rs1,s_) => + neq_int + (projT1 (regbits_to_regno + rs1)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s3361_ + _s2537_) >>= fun w__239 : option ((mword 5 * string)) => + (match w__239 with + | Some + (rs1,s_) => + returnm ((Some + ((C_JALR + (rs1), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3369_ + _s2537_) >>= fun w__242 : option ((mword 5 * mword 5 * string)) => + (if + ((match w__242 with + | Some + (rd,rs2,s_) => + andb + (neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg))) + (neq_int + (projT1 (regbits_to_regno + rs2)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s3369_ + _s2537_) >>= fun w__243 : option ((mword 5 * mword 5 * string)) => + (match w__243 with + | Some + (rd,rs2,s_) => + returnm ((Some + ((C_MV + ((rd, rs2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else if + ((match (_s3381_ + _s2537_) with + | Some + (s_) => + true + | _ => + false + end)) + then + (match (_s3381_ + _s2537_) with + | Some + (s_) => + returnm ((Some + ((C_EBREAK + (tt), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3385_ + _s2537_) >>= fun w__248 : option ((mword 5 * mword 5 * string)) => + (if + ((match w__248 with + | Some + (rsd,rs2,s_) => + andb + (neq_int + (projT1 (regbits_to_regno + rsd)) + (projT1 (regbits_to_regno + zreg))) + (neq_int + (projT1 (regbits_to_regno + rs2)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s3385_ + _s2537_) >>= fun w__249 : option ((mword 5 * mword 5 * string)) => + (match w__249 with + | Some + (rsd,rs2,s_) => + returnm ((Some + ((C_ADD + ((rsd, rs2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else if + ((match (_s3397_ + _s2537_) with + | Some + (s_) => + true + | _ => + false + end)) + then + (match (_s3397_ + _s2537_) with + | Some + (s_) => + returnm ((Some + ((STOP_FETCHING + (tt), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else if + ((match (_s3401_ + _s2537_) with + | Some + (s_) => + true + | _ => + false + end)) + then + (match (_s3401_ + _s2537_) with + | Some + (s_) => + returnm ((Some + ((THREAD_START + (tt), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3405_ + _s2537_) >>= fun w__256 : option ((mword 32 * string)) => + (if + ((match w__256 with + | Some + (s,s_) => + true + | _ => + false + end)) + then + (_s3405_ + _s2537_) >>= fun w__257 : option ((mword 32 * string)) => + (match w__257 with + | Some + (s,s_) => + returnm ((Some + ((ILLEGAL + (s), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3413_ + _s2537_) >>= fun w__260 : option ((mword 16 * string)) => + (if + ((match w__260 with + | Some + (s,s_) => + true + | _ => + false + end)) + then + (_s3413_ + _s2537_) >>= fun w__261 : option ((mword 16 * string)) => + (match w__261 with + | Some + (s,s_) => + returnm ((Some + ((C_ILLEGAL + (s), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + returnm (None + : option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))). + +Definition execute_WFI '(tt : unit) +: M (bool) := + + read_reg cur_privilege_ref >>= fun w__0 : Privilege => + (match w__0 with + | Machine => (platform_wfi tt) >> returnm (true : bool) + | Supervisor => + read_reg mstatus_ref >>= fun w__1 : Mstatus => + (if ((eq_vec (_get_Mstatus_TW w__1) ((bool_to_bits true) : mword 1))) then + (handle_illegal tt) >> returnm (false : bool) + else (platform_wfi tt) >> returnm (true : bool)) + : M (bool) + | User => (handle_illegal tt) >> returnm (false : bool) + end) + : M (bool). + +Definition execute_UTYPE (imm : mword 20) (rd : mword 5) (op : uop) +: M (bool) := + + let off : xlenbits := + EXTS 64 (concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12)) in + (match op with + | RISCV_LUI => returnm (off : xlenbits) + | RISCV_AUIPC => + ((read_reg PC_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + returnm ((add_vec w__0 off) + : mword 64) + end) >>= fun ret : xlenbits => + (wX (projT1 (regbits_to_regno rd)) ret) >> returnm (true : bool). + +Definition execute_THREAD_START '(tt : unit) : bool := true. + +Definition execute_STORECON +(aq : bool) (rl : bool) (rs2 : mword 5) (rs1 : mword 5) (width : word_width) (rd : mword 5) +: M (bool) := + + (speculate_conditional tt) >>= fun w__0 : bool => + (if ((Bool.eqb w__0 false)) then + (wX (projT1 (regbits_to_regno rd)) (EXTZ 64 (vec_of_bits [B1] : mword 1))) >> + returnm (true + : bool) + else + (rX (projT1 (regbits_to_regno rs1))) >>= fun vaddr : xlenbits => + (match width with + | BYTE => returnm (true : bool) + | HALF => + (cast_unit_vec (access_vec_dec vaddr 0)) >>= fun w__1 : mword 1 => + returnm ((eq_vec w__1 (vec_of_bits [B0] : mword 1)) + : bool) + | WORD => + returnm ((eq_vec (subrange_vec_dec vaddr 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))) + : bool) + | DOUBLE => + returnm ((eq_vec (subrange_vec_dec vaddr 2 0) + (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1))) + : bool) + end) >>= fun aligned : bool => + (if ((negb aligned)) then + (handle_mem_exception vaddr E_SAMO_Addr_Align) >> returnm (false : bool) + else if ((Bool.eqb (match_reservation vaddr) false)) then + (wX (projT1 (regbits_to_regno rd)) (EXTZ 64 (vec_of_bits [B1] : mword 1))) >> + returnm (true + : bool) + else + (translateAddr vaddr Write Data) >>= fun w__2 : TR_Result => + (match w__2 with + | TR_Failure (e) => (handle_mem_exception vaddr e) >> returnm (false : bool) + | TR_Address (addr) => + (match width with + | WORD => (mem_write_ea addr 4 aq rl true) : M (MemoryOpResult unit) + | DOUBLE => (mem_write_ea addr 8 aq rl true) : M (MemoryOpResult unit) + | _ => (internal_error "STORECON expected word or double") : M (MemoryOpResult unit) + end) >>= fun eares : MemoryOpResult unit => + (match eares with + | MemException (e) => (handle_mem_exception addr e) >> returnm (false : bool) + | MemValue (_) => + (rX (projT1 (regbits_to_regno rs2))) >>= fun rs2_val => + (match width with + | WORD => + (mem_write_value addr 4 (subrange_vec_dec rs2_val 31 0) aq rl true) + : M (MemoryOpResult bool) + | DOUBLE => (mem_write_value addr 8 rs2_val aq rl true) : M (MemoryOpResult bool) + | _ => + (internal_error "STORECON expected word or double") : M (MemoryOpResult bool) + end) >>= fun res : MemoryOpResult bool => + (match res with + | MemValue (true) => + (wX (projT1 (regbits_to_regno rd)) (EXTZ 64 (vec_of_bits [B0] : mword 1))) >> + let '_ := (cancel_reservation tt) : unit in + returnm (true + : bool) + | MemValue (false) => + (wX (projT1 (regbits_to_regno rd)) (EXTZ 64 (vec_of_bits [B1] : mword 1))) >> + let '_ := (cancel_reservation tt) : unit in + returnm (true + : bool) + | MemException (e) => (handle_mem_exception addr e) >> returnm (false : bool) + end) + : M (bool) + end) + : M (bool) + end) + : M (bool)) + : M (bool)) + : M (bool). + +Definition execute_STORE +(imm : mword 12) (rs2 : mword 5) (rs1 : mword 5) (width : word_width) (aq : bool) (rl : bool) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun w__0 : mword 64 => + let vaddr : xlenbits := add_vec w__0 (EXTS 64 imm) in + (check_misaligned vaddr width) >>= fun w__1 : bool => + (if (w__1) then (handle_mem_exception vaddr E_SAMO_Addr_Align) >> returnm (false : bool) + else + (translateAddr vaddr Write Data) >>= fun w__2 : TR_Result => + (match w__2 with + | TR_Failure (e) => (handle_mem_exception vaddr e) >> returnm (false : bool) + | TR_Address (addr) => + (match width with + | BYTE => (mem_write_ea addr 1 aq rl false) : M (MemoryOpResult unit) + | HALF => (mem_write_ea addr 2 aq rl false) : M (MemoryOpResult unit) + | WORD => (mem_write_ea addr 4 aq rl false) : M (MemoryOpResult unit) + | DOUBLE => (mem_write_ea addr 8 aq rl false) : M (MemoryOpResult unit) + end) >>= fun eares : MemoryOpResult unit => + (match eares with + | MemException (e) => (handle_mem_exception addr e) >> returnm (false : bool) + | MemValue (_) => + (rX (projT1 (regbits_to_regno rs2))) >>= fun rs2_val => + (match width with + | BYTE => + (mem_write_value addr 1 (subrange_vec_dec rs2_val 7 0) aq rl false) + : M (MemoryOpResult bool) + | HALF => + (mem_write_value addr 2 (subrange_vec_dec rs2_val 15 0) aq rl false) + : M (MemoryOpResult bool) + | WORD => + (mem_write_value addr 4 (subrange_vec_dec rs2_val 31 0) aq rl false) + : M (MemoryOpResult bool) + | DOUBLE => (mem_write_value addr 8 rs2_val aq rl false) : M (MemoryOpResult bool) + end) >>= fun res : MemoryOpResult bool => + (match res with + | MemValue (true) => returnm (true : bool) + | MemValue (false) => + (internal_error "store got false from mem_write_value") : M (bool) + | MemException (e) => (handle_mem_exception addr e) >> returnm (false : bool) + end) + : M (bool) + end) + : M (bool) + end) + : M (bool)) + : M (bool). + +Definition execute_STOP_FETCHING '(tt : unit) : bool := true. + +Definition execute_SRET '(tt : unit) +: M (bool) := + + read_reg cur_privilege_ref >>= fun w__0 : Privilege => + (match w__0 with + | User => (handle_illegal tt) : M (unit) + | Supervisor => + read_reg mstatus_ref >>= fun w__1 : Mstatus => + (if ((eq_vec (_get_Mstatus_TSR w__1) ((bool_to_bits true) : mword 1))) then + (handle_illegal tt) + : M (unit) + else + read_reg cur_privilege_ref >>= fun w__2 : Privilege => + ((read_reg PC_ref) : M (mword 64)) >>= fun w__3 : xlenbits => + (handle_exception w__2 (CTL_SRET (tt)) w__3) >>= fun w__4 : mword 64 => + write_reg nextPC_ref w__4 + : M (unit)) + : M (unit) + | Machine => + read_reg cur_privilege_ref >>= fun w__5 : Privilege => + ((read_reg PC_ref) : M (mword 64)) >>= fun w__6 : xlenbits => + (handle_exception w__5 (CTL_SRET (tt)) w__6) >>= fun w__7 : mword 64 => + write_reg nextPC_ref w__7 + : M (unit) + end) >> + returnm (false + : bool). + +Definition execute_SHIFTW (shamt : mword 5) (rs1 : mword 5) (rd : mword 5) (op : sop) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun w__0 : mword 64 => + let rs1_val := subrange_vec_dec w__0 31 0 in + let result : bits 32 := + match op with + | RISCV_SLLI => shift_bits_left rs1_val shamt + | RISCV_SRLI => shift_bits_right rs1_val shamt + | RISCV_SRAI => shift_right_arith32 rs1_val shamt + end in + (wX (projT1 (regbits_to_regno rd)) (EXTS 64 result)) >> returnm (true : bool). + +Definition execute_SHIFTIWOP (shamt : mword 5) (rs1 : mword 5) (rd : mword 5) (op : sopw) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun rs1_val => + let result : xlenbits := + match op with + | RISCV_SLLIW => EXTS 64 (shift_bits_left (subrange_vec_dec rs1_val 31 0) shamt) + | RISCV_SRLIW => EXTS 64 (shift_bits_right (subrange_vec_dec rs1_val 31 0) shamt) + | RISCV_SRAIW => EXTS 64 (shift_right_arith32 (subrange_vec_dec rs1_val 31 0) shamt) + end in + (wX (projT1 (regbits_to_regno rd)) result) >> returnm (true : bool). + +Definition execute_SHIFTIOP (shamt : mword 6) (rs1 : mword 5) (rd : mword 5) (op : sop) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun rs1_val => + let result : xlenbits := + match op with + | RISCV_SLLI => shift_bits_left rs1_val shamt + | RISCV_SRLI => shift_bits_right rs1_val shamt + | RISCV_SRAI => shift_right_arith64 rs1_val shamt + end in + (wX (projT1 (regbits_to_regno rd)) result) >> returnm (true : bool). + +Definition execute_SFENCE_VMA (rs1 : mword 5) (rs2 : mword 5) +: M (bool) := + + read_reg cur_privilege_ref >>= fun w__0 : Privilege => + (if ((eq_vec (privLevel_to_bits w__0) ((privLevel_to_bits User) : mword 2))) then + (handle_illegal tt) >> returnm (false : bool) + else + read_reg mstatus_ref >>= fun w__1 : Mstatus => + read_reg mstatus_ref >>= fun w__2 : Mstatus => + let p__15 := (architecture (_get_Mstatus_SXL w__1), _get_Mstatus_TVM w__2) in + (match p__15 with + | (Some (RV64), v_0) => + (if ((eq_vec v_0 ((bool_to_bits true) : mword 1))) then + (handle_illegal tt) >> returnm (false : bool) + else if ((eq_vec v_0 ((bool_to_bits false) : mword 1))) then + (if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then + returnm (None + : option (mword 39)) + else + (rX (projT1 (regbits_to_regno rs1))) >>= fun w__3 : mword 64 => + returnm ((Some + (subrange_vec_dec w__3 38 0)) + : option (mword 39))) >>= fun addr : option vaddr39 => + (if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs2)) 0)) then + returnm (None + : option (mword 16)) + else + (rX (projT1 (regbits_to_regno rs2))) >>= fun w__4 : mword 64 => + returnm ((Some + (subrange_vec_dec w__4 15 0)) + : option (mword 16))) >>= fun asid : option asid64 => + (flushTLB asid addr) >> returnm (true : bool) + else + (match (Some + (RV64), v_0) with + | (g__13, g__14) => (internal_error "unimplemented sfence architecture") : M (bool) + end) + : M (bool)) + : M (bool) + | (g__13, g__14) => (internal_error "unimplemented sfence architecture") : M (bool) + end) + : M (bool)) + : M (bool). + +Definition execute_RTYPEW (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (op : ropw) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun w__0 : mword 64 => + let rs1_val := subrange_vec_dec w__0 31 0 in + (rX (projT1 (regbits_to_regno rs2))) >>= fun w__1 : mword 64 => + let rs2_val := subrange_vec_dec w__1 31 0 in + let result : bits 32 := + match op with + | RISCV_ADDW => add_vec rs1_val rs2_val + | RISCV_SUBW => sub_vec rs1_val rs2_val + | RISCV_SLLW => shift_bits_left rs1_val (subrange_vec_dec rs2_val 4 0) + | RISCV_SRLW => shift_bits_right rs1_val (subrange_vec_dec rs2_val 4 0) + | RISCV_SRAW => shift_right_arith32 rs1_val (subrange_vec_dec rs2_val 4 0) + end in + (wX (projT1 (regbits_to_regno rd)) (EXTS 64 result)) >> returnm (true : bool). + +Definition execute_RTYPE (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (op : rop) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun rs1_val => + (rX (projT1 (regbits_to_regno rs2))) >>= fun rs2_val => + let result : xlenbits := + match op with + | RISCV_ADD => add_vec rs1_val rs2_val + | RISCV_SUB => sub_vec rs1_val rs2_val + | RISCV_SLL => shift_bits_left rs1_val (subrange_vec_dec rs2_val 5 0) + | RISCV_SLT => EXTZ 64 (bool_to_bits (zopz0zI_s rs1_val rs2_val)) + | RISCV_SLTU => EXTZ 64 (bool_to_bits (zopz0zI_u rs1_val rs2_val)) + | RISCV_XOR => xor_vec rs1_val rs2_val + | RISCV_SRL => shift_bits_right rs1_val (subrange_vec_dec rs2_val 5 0) + | RISCV_SRA => shift_right_arith64 rs1_val (subrange_vec_dec rs2_val 5 0) + | RISCV_OR => or_vec rs1_val rs2_val + | RISCV_AND => and_vec rs1_val rs2_val + end in + (wX (projT1 (regbits_to_regno rd)) result) >> returnm (true : bool). + +Definition execute_RISCV_JALR (imm : mword 12) (rs1 : mword 5) (rd : mword 5) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun w__0 : mword 64 => + let newPC : xlenbits := + concat_vec (subrange_vec_dec (add_vec w__0 (EXTS 64 imm)) 63 1) (vec_of_bits [B0] : mword 1) in + (and_boolM ((bit_to_bool (access_vec_dec newPC 1)) : M (bool)) + ((haveRVC tt) >>= fun w__2 : bool => returnm ((negb w__2) : bool))) >>= fun w__3 : bool => + (if (w__3) then (handle_mem_exception newPC E_Fetch_Addr_Align) >> returnm (false : bool) + else + ((read_reg nextPC_ref) : M (mword 64)) >>= fun w__4 : xlenbits => + (wX (projT1 (regbits_to_regno rd)) w__4) >> + write_reg nextPC_ref newPC >> returnm (true : bool)) + : M (bool). + +Definition execute_RISCV_JAL (imm : mword 21) (rd : mword 5) +: M (bool) := + + ((read_reg PC_ref) : M (mword 64)) >>= fun pc : xlenbits => + let newPC : xlenbits := add_vec pc (EXTS 64 imm) in + (and_boolM ((bit_to_bool (access_vec_dec newPC 1)) : M (bool)) + ((haveRVC tt) >>= fun w__1 : bool => returnm ((negb w__1) : bool))) >>= fun w__2 : bool => + (if (w__2) then (handle_mem_exception newPC E_Fetch_Addr_Align) >> returnm (false : bool) + else + ((read_reg nextPC_ref) : M (mword 64)) >>= fun w__3 : xlenbits => + (wX (projT1 (regbits_to_regno rd)) w__3) >> + write_reg nextPC_ref newPC >> returnm (true : bool)) + : M (bool). + +Definition execute_REMW (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (s : bool) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun w__0 : mword 64 => + let rs1_val := subrange_vec_dec w__0 31 0 in + (rX (projT1 (regbits_to_regno rs2))) >>= fun w__1 : mword 64 => + let rs2_val := subrange_vec_dec w__1 31 0 in + let rs1_int : Z := if (s) then projT1 (sint rs1_val) else projT1 (uint rs1_val) in + let rs2_int : Z := if (s) then projT1 (sint rs2_val) else projT1 (uint rs2_val) in + let r : Z := + if sumbool_of_bool ((Z.eqb rs2_int 0)) then rs1_int + else rem_round_zero rs1_int rs2_int in + (wX (projT1 (regbits_to_regno rd)) (EXTS 64 (to_bits 32 r))) >> returnm (true : bool). + +Definition execute_REM (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (s : bool) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun rs1_val => + (rX (projT1 (regbits_to_regno rs2))) >>= fun rs2_val => + let rs1_int : Z := if (s) then projT1 (sint rs1_val) else projT1 (uint rs1_val) in + let rs2_int : Z := if (s) then projT1 (sint rs2_val) else projT1 (uint rs2_val) in + let r : Z := + if sumbool_of_bool ((Z.eqb rs2_int 0)) then rs1_int + else rem_round_zero rs1_int rs2_int in + (wX (projT1 (regbits_to_regno rd)) (to_bits xlen r)) >> returnm (true : bool). + +Definition execute_MULW (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun w__0 : mword 64 => + let rs1_val := subrange_vec_dec w__0 31 0 in + (rX (projT1 (regbits_to_regno rs2))) >>= fun w__1 : mword 64 => + let rs2_val := subrange_vec_dec w__1 31 0 in + let rs1_int : Z := projT1 (sint rs1_val) in + let rs2_int : Z := projT1 (sint rs2_val) in + let result32 := subrange_vec_dec (to_bits 64 (Z.mul rs1_int rs2_int)) 31 0 in + let result : xlenbits := EXTS 64 result32 in + (wX (projT1 (regbits_to_regno rd)) result) >> returnm (true : bool). + +Definition execute_MUL +(rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (high : bool) (signed1 : bool) (signed2 : bool) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun rs1_val => + (rX (projT1 (regbits_to_regno rs2))) >>= fun rs2_val => + let rs1_int : Z := if (signed1) then projT1 (sint rs1_val) else projT1 (uint rs1_val) in + let rs2_int : Z := if (signed2) then projT1 (sint rs2_val) else projT1 (uint rs2_val) in + let result128 := to_bits 128 (Z.mul rs1_int rs2_int) in + let result := + if (high) then subrange_vec_dec result128 127 64 + else subrange_vec_dec result128 63 0 in + (wX (projT1 (regbits_to_regno rd)) result) >> returnm (true : bool). + +Definition execute_MRET '(tt : unit) +: M (bool) := + + read_reg cur_privilege_ref >>= fun w__0 : Privilege => + (if ((eq_vec (privLevel_to_bits w__0) ((privLevel_to_bits Machine) : mword 2))) then + read_reg cur_privilege_ref >>= fun w__1 : Privilege => + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : xlenbits => + (handle_exception w__1 (CTL_MRET (tt)) w__2) >>= fun w__3 : mword 64 => + write_reg nextPC_ref w__3 + : M (unit) + else (handle_illegal tt) : M (unit)) >> + returnm (false + : bool). + +Definition execute_LOADRES +(aq : bool) (rl : bool) (rs1 : mword 5) (width : word_width) (rd : mword 5) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun vaddr : xlenbits => + (match width with + | BYTE => returnm (true : bool) + | HALF => + (cast_unit_vec (access_vec_dec vaddr 0)) >>= fun w__0 : mword 1 => + returnm ((eq_vec w__0 (vec_of_bits [B0] : mword 1)) + : bool) + | WORD => + returnm ((eq_vec (subrange_vec_dec vaddr 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))) + : bool) + | DOUBLE => + returnm ((eq_vec (subrange_vec_dec vaddr 2 0) (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1))) + : bool) + end) >>= fun aligned : bool => + (if ((negb aligned)) then + (handle_mem_exception vaddr E_Load_Addr_Align) >> returnm (false : bool) + else + (translateAddr vaddr Read Data) >>= fun w__1 : TR_Result => + (match w__1 with + | TR_Failure (e) => (handle_mem_exception vaddr e) >> returnm (false : bool) + | TR_Address (addr) => + (match width with + | WORD => + (mem_read addr 4 aq rl true) >>= fun w__2 : MemoryOpResult (mword (8 * 4)) => + (process_loadres rd vaddr w__2 false) + : M (bool) + | DOUBLE => + (mem_read addr 8 aq rl true) >>= fun w__4 : MemoryOpResult (mword (8 * 8)) => + (process_loadres rd vaddr w__4 false) + : M (bool) + | _ => (internal_error "LOADRES expected WORD or DOUBLE") : M (bool) + end) + : M (bool) + end) + : M (bool)) + : M (bool). + +Definition execute_LOAD +(imm : mword 12) (rs1 : mword 5) (rd : mword 5) (is_unsigned : bool) (width : word_width) +(aq : bool) (rl : bool) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun w__0 : mword 64 => + let vaddr : xlenbits := add_vec w__0 (EXTS 64 imm) in + (check_misaligned vaddr width) >>= fun w__1 : bool => + (if (w__1) then (handle_mem_exception vaddr E_Load_Addr_Align) >> returnm (false : bool) + else + (translateAddr vaddr Read Data) >>= fun w__2 : TR_Result => + (match w__2 with + | TR_Failure (e) => (handle_mem_exception vaddr e) >> returnm (false : bool) + | TR_Address (addr) => + (match width with + | BYTE => + (mem_read addr 1 aq rl false) >>= fun w__3 : MemoryOpResult (mword (8 * 1)) => + (process_load rd vaddr w__3 is_unsigned) + : M (bool) + | HALF => + (mem_read addr 2 aq rl false) >>= fun w__5 : MemoryOpResult (mword (8 * 2)) => + (process_load rd vaddr w__5 is_unsigned) + : M (bool) + | WORD => + (mem_read addr 4 aq rl false) >>= fun w__7 : MemoryOpResult (mword (8 * 4)) => + (process_load rd vaddr w__7 is_unsigned) + : M (bool) + | DOUBLE => + (mem_read addr 8 aq rl false) >>= fun w__9 : MemoryOpResult (mword (8 * 8)) => + (process_load rd vaddr w__9 is_unsigned) + : M (bool) + end) + : M (bool) + end) + : M (bool)) + : M (bool). + +Definition execute_ITYPE (imm : mword 12) (rs1 : mword 5) (rd : mword 5) (op : iop) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun rs1_val => + let immext : xlenbits := EXTS 64 imm in + let result : xlenbits := + match op with + | RISCV_ADDI => add_vec rs1_val immext + | RISCV_SLTI => EXTZ 64 (bool_to_bits (zopz0zI_s rs1_val immext)) + | RISCV_SLTIU => EXTZ 64 (bool_to_bits (zopz0zI_u rs1_val immext)) + | RISCV_XORI => xor_vec rs1_val immext + | RISCV_ORI => or_vec rs1_val immext + | RISCV_ANDI => and_vec rs1_val immext + end in + (wX (projT1 (regbits_to_regno rd)) result) >> returnm (true : bool). + +Definition execute_ILLEGAL (s : mword 32) +: M (bool) := + + (handle_illegal tt) >> returnm (false : bool). + +Definition execute_FENCE_TSO (pred : mword 4) (succ : mword 4) +: M (bool) := + + (match (pred, succ) with + | (v__836, v__837) => + (if ((andb (eq_vec (subrange_vec_dec v__836 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__837 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))))) + then + (MEM_fence_tso tt) + : M (unit) + else + returnm ((if ((andb + (eq_vec (subrange_vec_dec v__836 1 0) + (vec_of_bits [B0;B0] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__837 1 0) + (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) then + tt + else + let '_ := (print_endline "FIXME: unsupported fence") : unit in + tt) + : unit)) + : M (unit) + end) >> + returnm (true + : bool). + +Definition execute_FENCEI '(tt : unit) : bool := true. + +Definition execute_FENCE (pred : mword 4) (succ : mword 4) +: M (bool) := + + (match (pred, succ) with + | (v__796, v__797) => + (if ((andb (eq_vec (subrange_vec_dec v__796 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__797 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))))) + then + (MEM_fence_rw_rw tt) + : M (unit) + else if ((andb + (eq_vec (subrange_vec_dec v__796 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__797 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))))) + then + (MEM_fence_r_rw tt) + : M (unit) + else if ((andb + (eq_vec (subrange_vec_dec v__796 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__797 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) + then + (MEM_fence_r_r tt) + : M (unit) + else if ((andb + (eq_vec (subrange_vec_dec v__796 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__797 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) + then + (MEM_fence_rw_w tt) + : M (unit) + else if ((andb + (eq_vec (subrange_vec_dec v__796 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__797 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) + then + (MEM_fence_w_w tt) + : M (unit) + else if ((andb + (eq_vec (subrange_vec_dec v__796 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__797 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))))) + then + (MEM_fence_w_rw tt) + : M (unit) + else if ((andb + (eq_vec (subrange_vec_dec v__796 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__797 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) + then + (MEM_fence_rw_r tt) + : M (unit) + else if ((andb + (eq_vec (subrange_vec_dec v__796 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__797 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) + then + (MEM_fence_r_w tt) + : M (unit) + else if ((andb + (eq_vec (subrange_vec_dec v__796 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__797 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) + then + (MEM_fence_w_r tt) + : M (unit) + else + returnm ((if ((andb + (eq_vec (subrange_vec_dec v__796 1 0) + (vec_of_bits [B0;B0] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__797 1 0) + (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) then + tt + else + let '_ := (print_endline "FIXME: unsupported fence") : unit in + tt) + : unit)) + : M (unit) + end) >> + returnm (true + : bool). + +Definition execute_ECALL '(tt : unit) +: M (bool) := + + read_reg cur_privilege_ref >>= fun w__0 : Privilege => + let t : sync_exception := + {| sync_exception_trap := + (match w__0 with + | User => E_U_EnvCall + | Supervisor => E_S_EnvCall + | Machine => E_M_EnvCall + end); + sync_exception_excinfo := (None : option xlenbits) |} in + read_reg cur_privilege_ref >>= fun w__1 : Privilege => + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : xlenbits => + (handle_exception w__1 (CTL_TRAP (t)) w__2) >>= fun w__3 : mword 64 => + write_reg nextPC_ref w__3 >> returnm (false : bool). + +Definition execute_EBREAK '(tt : unit) +: M (bool) := + + ((read_reg PC_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + (handle_mem_exception w__0 E_Breakpoint) >> returnm (false : bool). + +Definition execute_DIVW (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (s : bool) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun w__0 : mword 64 => + let rs1_val := subrange_vec_dec w__0 31 0 in + (rX (projT1 (regbits_to_regno rs2))) >>= fun w__1 : mword 64 => + let rs2_val := subrange_vec_dec w__1 31 0 in + let rs1_int : Z := if (s) then projT1 (sint rs1_val) else projT1 (uint rs1_val) in + let rs2_int : Z := if (s) then projT1 (sint rs2_val) else projT1 (uint rs2_val) in + let q : Z := + if sumbool_of_bool ((Z.eqb rs2_int 0)) then (-1) + else quot_round_zero rs1_int rs2_int in + let q' : Z := + if sumbool_of_bool ((andb s (Z.gtb q (Z.sub (projT1 (pow2 31)) 1)))) then Z.sub 0 (pow 2 31) + else q in + (wX (projT1 (regbits_to_regno rd)) (EXTS 64 (to_bits 32 q'))) >> returnm (true : bool). + +Definition execute_DIV (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (s : bool) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun rs1_val => + (rX (projT1 (regbits_to_regno rs2))) >>= fun rs2_val => + let rs1_int : Z := if (s) then projT1 (sint rs1_val) else projT1 (uint rs1_val) in + let rs2_int : Z := if (s) then projT1 (sint rs2_val) else projT1 (uint rs2_val) in + let q : Z := + if sumbool_of_bool ((Z.eqb rs2_int 0)) then (-1) + else quot_round_zero rs1_int rs2_int in + let q' : Z := if sumbool_of_bool ((andb s (Z.gtb q xlen_max_signed))) then xlen_min_signed else q in + (wX (projT1 (regbits_to_regno rd)) (to_bits xlen q')) >> returnm (true : bool). + +Definition execute_C_NOP '(tt : unit) : bool := true. + +Definition execute_C_ILLEGAL (s : mword 16) +: M (bool) := + + (handle_illegal tt) >> returnm (false : bool). + +Definition execute_C_ADDIW (imm : mword 6) (rsd : mword 5) +: M (bool) := + + let imm : bits 32 := EXTS 32 imm in + (rX (projT1 (regbits_to_regno rsd))) >>= fun rs_val => + let res : bits 32 := add_vec (subrange_vec_dec rs_val 31 0) imm in + (wX (projT1 (regbits_to_regno rsd)) (EXTS 64 res)) >> returnm (true : bool). + +Definition execute_CSR (csr : mword 12) (rs1 : mword 5) (rd : mword 5) (is_imm : bool) (op : csrop) +: M (bool) := + + (if (is_imm) then returnm ((EXTZ 64 rs1) : mword 64) + else (rX (projT1 (regbits_to_regno rs1))) : M (mword 64)) >>= fun rs1_val : xlenbits => + let isWrite : bool := + match op with + | CSRRW => true + | _ => if (is_imm) then neq_int (projT1 (uint rs1_val)) 0 else neq_int (projT1 (uint rs1)) 0 + end in + read_reg cur_privilege_ref >>= fun w__1 : Privilege => + (check_CSR csr w__1 isWrite) >>= fun w__2 : bool => + (if ((negb w__2)) then (handle_illegal tt) >> returnm (false : bool) + else + (readCSR csr) >>= fun csr_val => + (if (isWrite) then + let new_val : xlenbits := + match op with + | CSRRW => rs1_val + | CSRRS => or_vec csr_val rs1_val + | CSRRC => and_vec csr_val (not_vec rs1_val) + end in + (writeCSR csr new_val) + : M (unit) + else returnm (tt : unit)) >> + (wX (projT1 (regbits_to_regno rd)) csr_val) >> returnm (true : bool)) + : M (bool). + +Definition execute_BTYPE (imm : mword 13) (rs2 : mword 5) (rs1 : mword 5) (op : bop) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun rs1_val => + (rX (projT1 (regbits_to_regno rs2))) >>= fun rs2_val => + let taken : bool := + match op with + | RISCV_BEQ => eq_vec rs1_val rs2_val + | RISCV_BNE => neq_vec rs1_val rs2_val + | RISCV_BLT => zopz0zI_s rs1_val rs2_val + | RISCV_BGE => zopz0zKzJ_s rs1_val rs2_val + | RISCV_BLTU => zopz0zI_u rs1_val rs2_val + | RISCV_BGEU => zopz0zKzJ_u rs1_val rs2_val + end in + ((read_reg PC_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + let newPC := add_vec w__0 (EXTS 64 imm) in + (if (taken) then + (and_boolM ((bit_to_bool (access_vec_dec newPC 1)) : M (bool)) + ((haveRVC tt) >>= fun w__2 : bool => returnm ((negb w__2) : bool))) >>= fun w__3 : bool => + (if (w__3) then (handle_mem_exception newPC E_Fetch_Addr_Align) >> returnm (false : bool) + else write_reg nextPC_ref newPC >> returnm (true : bool)) + : M (bool) + else returnm (true : bool)) + : M (bool). + +Definition execute_AMO +(op : amoop) (aq : bool) (rl : bool) (rs2 : mword 5) (rs1 : mword 5) (width : word_width) +(rd : mword 5) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun vaddr : xlenbits => + (translateAddr vaddr ReadWrite Data) >>= fun w__0 : TR_Result => + (match w__0 with + | TR_Failure (e) => (handle_mem_exception vaddr e) >> returnm (false : bool) + | TR_Address (addr) => + (match width with + | WORD => (mem_write_ea addr 4 (andb aq rl) rl true) : M (MemoryOpResult unit) + | DOUBLE => (mem_write_ea addr 8 (andb aq rl) rl true) : M (MemoryOpResult unit) + | _ => (internal_error "AMO expected WORD or DOUBLE") : M (MemoryOpResult unit) + end) >>= fun eares : MemoryOpResult unit => + (match eares with + | MemException (e) => (handle_mem_exception addr e) >> returnm (false : bool) + | MemValue (_) => + (match width with + | WORD => + (mem_read addr 4 aq (andb aq rl) true) >>= fun w__4 : MemoryOpResult (mword (8 * 4)) => + returnm ((extend_value false w__4) + : MemoryOpResult (mword 64)) + | DOUBLE => + (mem_read addr 8 aq (andb aq rl) true) >>= fun w__5 : MemoryOpResult (mword (8 * 8)) => + returnm ((extend_value false w__5) + : MemoryOpResult (mword 64)) + | _ => (internal_error "AMO expected WORD or DOUBLE") : M (MemoryOpResult (mword 64)) + end) >>= fun rval : MemoryOpResult xlenbits => + (match rval with + | MemException (e) => (handle_mem_exception addr e) >> returnm (false : bool) + | MemValue (loaded) => + (rX (projT1 (regbits_to_regno rs2))) >>= fun rs2_val : xlenbits => + let result : xlenbits := + match op with + | AMOSWAP => rs2_val + | AMOADD => add_vec rs2_val loaded + | AMOXOR => xor_vec rs2_val loaded + | AMOAND => and_vec rs2_val loaded + | AMOOR => or_vec rs2_val loaded + | AMOMIN => vector64 (Z.min (projT1 (sint rs2_val)) (projT1 (sint loaded))) + | AMOMAX => vector64 (Z.max (projT1 (sint rs2_val)) (projT1 (sint loaded))) + | AMOMINU => + vector64 (projT1 (min_nat (projT1 (uint rs2_val)) (projT1 (uint loaded)))) + | AMOMAXU => + vector64 (projT1 (max_nat (projT1 (uint rs2_val)) (projT1 (uint loaded)))) + end in + (match width with + | WORD => + (mem_write_value addr 4 (subrange_vec_dec result 31 0) (andb aq rl) rl true) + : M (MemoryOpResult bool) + | DOUBLE => + (mem_write_value addr 8 result (andb aq rl) rl true) : M (MemoryOpResult bool) + | _ => (internal_error "AMO expected WORD or DOUBLE") : M (MemoryOpResult bool) + end) >>= fun wval : MemoryOpResult bool => + (match wval with + | MemValue (true) => + (wX (projT1 (regbits_to_regno rd)) loaded) >> returnm (true : bool) + | MemValue (false) => + (internal_error "AMO got false from mem_write_value") : M (bool) + | MemException (e) => (handle_mem_exception addr e) >> returnm (false : bool) + end) + : M (bool) + end) + : M (bool) + end) + : M (bool) + end) + : M (bool). + +Definition execute_ADDIW (imm : mword 12) (rs1 : mword 5) (rd : mword 5) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun w__0 : mword 64 => + let result : xlenbits := add_vec (EXTS 64 imm) w__0 in + (wX (projT1 (regbits_to_regno rd)) (EXTS 64 (subrange_vec_dec result 31 0))) >> + returnm (true + : bool). + +Definition compressed_measure (instr : ast) +: Z := + + match instr with + | C_ADDI4SPN (rdc,nzimm) => 1 + | C_LW (uimm,rsc,rdc) => 1 + | C_LD (uimm,rsc,rdc) => 1 + | C_SW (uimm,rsc1,rsc2) => 1 + | C_SD (uimm,rsc1,rsc2) => 1 + | C_ADDI (nzi,rsd) => 1 + | C_JAL (imm) => 1 + | C_LI (imm,rd) => 1 + | C_ADDI16SP (imm) => 1 + | C_LUI (imm,rd) => 1 + | C_SRLI (shamt,rsd) => 1 + | C_SRAI (shamt,rsd) => 1 + | C_ANDI (imm,rsd) => 1 + | C_SUB (rsd,rs2) => 1 + | C_XOR (rsd,rs2) => 1 + | C_OR (rsd,rs2) => 1 + | C_AND (rsd,rs2) => 1 + | C_SUBW (rsd,rs2) => 1 + | C_ADDW (rsd,rs2) => 1 + | C_J (imm) => 1 + | C_BEQZ (imm,rs) => 1 + | C_BNEZ (imm,rs) => 1 + | C_SLLI (shamt,rsd) => 1 + | C_LWSP (uimm,rd) => 1 + | C_LDSP (uimm,rd) => 1 + | C_SWSP (uimm,rs2) => 1 + | C_SDSP (uimm,rs2) => 1 + | C_JR (rs1) => 1 + | C_JALR (rs1) => 1 + | C_MV (rd,rs2) => 1 + | C_EBREAK (tt') => 1 + | C_ADD (rsd,rs2) => 1 + | _ => 0 + end. + +Fixpoint _rec_execute (merge_var : ast) (_reclimit : Z) (_acc : Acc (Zwf 0) _reclimit) +{struct _acc} : M (bool) := + + assert_exp' (Z.geb _reclimit 0) "recursion limit reached" >>= fun _ => + (match merge_var with + | C_ADDI4SPN (rdc,nzimm) => + let imm : bits 12 := + concat_vec (vec_of_bits [B0;B0] : mword 2) + (concat_vec nzimm (vec_of_bits [B0;B0] : mword 2)) in + let rd := creg2reg_bits rdc in + (_rec_execute (ITYPE ((imm, sp, rd, RISCV_ADDI))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_LW (uimm,rsc,rdc) => + let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in + let rd := creg2reg_bits rdc in + let rs := creg2reg_bits rsc in + (_rec_execute (LOAD ((imm, rs, rd, false, WORD, false, false))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_LD (uimm,rsc,rdc) => + let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in + let rd := creg2reg_bits rdc in + let rs := creg2reg_bits rsc in + (_rec_execute (LOAD ((imm, rs, rd, false, DOUBLE, false, false))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_SW (uimm,rsc1,rsc2) => + let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in + let rs1 := creg2reg_bits rsc1 in + let rs2 := creg2reg_bits rsc2 in + (_rec_execute (STORE ((imm, rs2, rs1, WORD, false, false))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_SD (uimm,rsc1,rsc2) => + let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in + let rs1 := creg2reg_bits rsc1 in + let rs2 := creg2reg_bits rsc2 in + (_rec_execute (STORE ((imm, rs2, rs1, DOUBLE, false, false))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_ADDI (nzi,rsd) => + let imm : bits 12 := EXTS 12 nzi in + (_rec_execute (ITYPE ((imm, rsd, rsd, RISCV_ADDI))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_JAL (imm) => + (_rec_execute (RISCV_JAL ((EXTS 21 (concat_vec imm (vec_of_bits [B0] : mword 1)), ra))) + (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_LI (imm,rd) => + let imm : bits 12 := EXTS 12 imm in + (_rec_execute (ITYPE ((imm, zreg, rd, RISCV_ADDI))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_ADDI16SP (imm) => + let imm : bits 12 := EXTS 12 (concat_vec imm (vec_of_bits [B0;B0;B0;B0] : mword 4)) in + (_rec_execute (ITYPE ((imm, sp, sp, RISCV_ADDI))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_LUI (imm,rd) => + let res : bits 20 := EXTS 20 imm in + (_rec_execute (UTYPE ((res, rd, RISCV_LUI))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_SRLI (shamt,rsd) => + let rsd := creg2reg_bits rsd in + (_rec_execute (SHIFTIOP ((shamt, rsd, rsd, RISCV_SRLI))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_SRAI (shamt,rsd) => + let rsd := creg2reg_bits rsd in + (_rec_execute (SHIFTIOP ((shamt, rsd, rsd, RISCV_SRAI))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_ANDI (imm,rsd) => + let rsd := creg2reg_bits rsd in + (_rec_execute (ITYPE ((EXTS 12 imm, rsd, rsd, RISCV_ANDI))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_SUB (rsd,rs2) => + let rsd := creg2reg_bits rsd in + let rs2 := creg2reg_bits rs2 in + (_rec_execute (RTYPE ((rs2, rsd, rsd, RISCV_SUB))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_XOR (rsd,rs2) => + let rsd := creg2reg_bits rsd in + let rs2 := creg2reg_bits rs2 in + (_rec_execute (RTYPE ((rs2, rsd, rsd, RISCV_XOR))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_OR (rsd,rs2) => + let rsd := creg2reg_bits rsd in + let rs2 := creg2reg_bits rs2 in + (_rec_execute (RTYPE ((rs2, rsd, rsd, RISCV_OR))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_AND (rsd,rs2) => + let rsd := creg2reg_bits rsd in + let rs2 := creg2reg_bits rs2 in + (_rec_execute (RTYPE ((rs2, rsd, rsd, RISCV_AND))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_SUBW (rsd,rs2) => + let rsd := creg2reg_bits rsd in + let rs2 := creg2reg_bits rs2 in + (_rec_execute (RTYPEW ((rs2, rsd, rsd, RISCV_SUBW))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_ADDW (rsd,rs2) => + let rsd := creg2reg_bits rsd in + let rs2 := creg2reg_bits rs2 in + (_rec_execute (RTYPEW ((rs2, rsd, rsd, RISCV_ADDW))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_J (imm) => + (_rec_execute (RISCV_JAL ((EXTS 21 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg))) + (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_BEQZ (imm,rs) => + (_rec_execute + (BTYPE + ((EXTS 13 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg, creg2reg_bits rs, RISCV_BEQ))) + (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_BNEZ (imm,rs) => + (_rec_execute + (BTYPE + ((EXTS 13 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg, creg2reg_bits rs, RISCV_BNE))) + (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_SLLI (shamt,rsd) => + (_rec_execute (SHIFTIOP ((shamt, rsd, rsd, RISCV_SLLI))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_LWSP (uimm,rd) => + let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in + (_rec_execute (LOAD ((imm, sp, rd, false, WORD, false, false))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_LDSP (uimm,rd) => + let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in + (_rec_execute (LOAD ((imm, sp, rd, false, DOUBLE, false, false))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_SWSP (uimm,rs2) => + let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in + (_rec_execute (STORE ((imm, rs2, sp, WORD, false, false))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_SDSP (uimm,rs2) => + let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in + (_rec_execute (STORE ((imm, rs2, sp, DOUBLE, false, false))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_JR (rs1) => + (_rec_execute (RISCV_JALR ((EXTZ 12 (vec_of_bits [B0] : mword 1), rs1, zreg))) + (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_JALR (rs1) => + (_rec_execute (RISCV_JALR ((EXTZ 12 (vec_of_bits [B0] : mword 1), rs1, ra))) + (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_MV (rd,rs2) => + (_rec_execute (RTYPE ((rs2, zreg, rd, RISCV_ADD))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_EBREAK (tt) => + (_rec_execute (EBREAK (tt)) (Z.sub _reclimit 1) (_limit_reduces _acc)) : M (bool) + | C_ADD (rsd,rs2) => + (_rec_execute (RTYPE ((rs2, rsd, rsd, RISCV_ADD))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | UTYPE (imm,rd,op) => (execute_UTYPE imm rd op) : M (bool) + | RISCV_JAL (imm,rd) => (execute_RISCV_JAL imm rd) : M (bool) + | BTYPE (imm,rs2,rs1,op) => (execute_BTYPE imm rs2 rs1 op) : M (bool) + | ITYPE (imm,rs1,rd,op) => (execute_ITYPE imm rs1 rd op) : M (bool) + | SHIFTIOP (shamt,rs1,rd,op) => (execute_SHIFTIOP shamt rs1 rd op) : M (bool) + | RTYPE (rs2,rs1,rd,op) => (execute_RTYPE rs2 rs1 rd op) : M (bool) + | LOAD (imm,rs1,rd,is_unsigned,width,aq,rl) => + (execute_LOAD imm rs1 rd is_unsigned width aq rl) : M (bool) + | STORE (imm,rs2,rs1,width,aq,rl) => (execute_STORE imm rs2 rs1 width aq rl) : M (bool) + | ADDIW (imm,rs1,rd) => (execute_ADDIW imm rs1 rd) : M (bool) + | SHIFTW (shamt,rs1,rd,op) => (execute_SHIFTW shamt rs1 rd op) : M (bool) + | RTYPEW (rs2,rs1,rd,op) => (execute_RTYPEW rs2 rs1 rd op) : M (bool) + | SHIFTIWOP (shamt,rs1,rd,op) => (execute_SHIFTIWOP shamt rs1 rd op) : M (bool) + | MUL (rs2,rs1,rd,high,signed1,signed2) => + (execute_MUL rs2 rs1 rd high signed1 signed2) : M (bool) + | DIV (rs2,rs1,rd,s) => (execute_DIV rs2 rs1 rd s) : M (bool) + | REM (rs2,rs1,rd,s) => (execute_REM rs2 rs1 rd s) : M (bool) + | MULW (rs2,rs1,rd) => (execute_MULW rs2 rs1 rd) : M (bool) + | DIVW (rs2,rs1,rd,s) => (execute_DIVW rs2 rs1 rd s) : M (bool) + | REMW (rs2,rs1,rd,s) => (execute_REMW rs2 rs1 rd s) : M (bool) + | FENCE (pred,succ) => (execute_FENCE pred succ) : M (bool) + | FENCE_TSO (pred,succ) => (execute_FENCE_TSO pred succ) : M (bool) + | FENCEI (arg0) => returnm ((execute_FENCEI arg0) : bool) + | ECALL (arg0) => (execute_ECALL arg0) : M (bool) + | MRET (arg0) => (execute_MRET arg0) : M (bool) + | SRET (arg0) => (execute_SRET arg0) : M (bool) + | EBREAK (arg0) => (execute_EBREAK arg0) : M (bool) + | WFI (arg0) => (execute_WFI arg0) : M (bool) + | SFENCE_VMA (rs1,rs2) => (execute_SFENCE_VMA rs1 rs2) : M (bool) + | LOADRES (aq,rl,rs1,width,rd) => (execute_LOADRES aq rl rs1 width rd) : M (bool) + | STORECON (aq,rl,rs2,rs1,width,rd) => (execute_STORECON aq rl rs2 rs1 width rd) : M (bool) + | AMO (op,aq,rl,rs2,rs1,width,rd) => (execute_AMO op aq rl rs2 rs1 width rd) : M (bool) + | CSR (csr,rs1,rd,is_imm,op) => (execute_CSR csr rs1 rd is_imm op) : M (bool) + | C_NOP (arg0) => returnm ((execute_C_NOP arg0) : bool) + | C_ADDIW (imm,rsd) => (execute_C_ADDIW imm rsd) : M (bool) + | STOP_FETCHING (arg0) => returnm ((execute_STOP_FETCHING arg0) : bool) + | THREAD_START (arg0) => returnm ((execute_THREAD_START arg0) : bool) + | ILLEGAL (s) => (execute_ILLEGAL s) : M (bool) + | C_ILLEGAL (s) => (execute_C_ILLEGAL s) : M (bool) + | RISCV_JALR (imm,rs1,rd) => (execute_RISCV_JALR imm rs1 rd) : M (bool) + end) + : M (bool). + +Definition execute (i : ast) +: M (bool) := + + (_rec_execute i ((compressed_measure i) : Z) (Zwf_guarded _)) + : M (bool). + +Definition print_insn (insn : ast) : M (string) := (assembly_forwards insn) : M (string). + +Definition decode (bv : mword 32) : option ast := Some (encdec_backwards bv). + +Definition decodeCompressed (bv : mword 16) : option ast := Some (encdec_compressed_backwards bv). + +Definition read_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 11)} +: read_kind := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Read_plain + else if sumbool_of_bool ((Z.eqb p0_ 1)) then Read_reserve + else if sumbool_of_bool ((Z.eqb p0_ 2)) then Read_acquire + else if sumbool_of_bool ((Z.eqb p0_ 3)) then Read_exclusive + else if sumbool_of_bool ((Z.eqb p0_ 4)) then Read_exclusive_acquire + else if sumbool_of_bool ((Z.eqb p0_ 5)) then Read_stream + else if sumbool_of_bool ((Z.eqb p0_ 6)) then Read_RISCV_acquire + else if sumbool_of_bool ((Z.eqb p0_ 7)) then Read_RISCV_strong_acquire + else if sumbool_of_bool ((Z.eqb p0_ 8)) then Read_RISCV_reserved + else if sumbool_of_bool ((Z.eqb p0_ 9)) then Read_RISCV_reserved_acquire + else if sumbool_of_bool ((Z.eqb p0_ 10)) then Read_RISCV_reserved_strong_acquire + else Read_X86_locked. + +Definition num_of_read_kind (arg_ : read_kind) +: {e : Z & ArithFact (0 <= e /\ e <= 11)} := + + build_ex(match arg_ with + | Read_plain => 0 + | Read_reserve => 1 + | Read_acquire => 2 + | Read_exclusive => 3 + | Read_exclusive_acquire => 4 + | Read_stream => 5 + | Read_RISCV_acquire => 6 + | Read_RISCV_strong_acquire => 7 + | Read_RISCV_reserved => 8 + | Read_RISCV_reserved_acquire => 9 + | Read_RISCV_reserved_strong_acquire => 10 + | Read_X86_locked => 11 + end). + +Definition write_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 10)} +: write_kind := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Write_plain + else if sumbool_of_bool ((Z.eqb p0_ 1)) then Write_conditional + else if sumbool_of_bool ((Z.eqb p0_ 2)) then Write_release + else if sumbool_of_bool ((Z.eqb p0_ 3)) then Write_exclusive + else if sumbool_of_bool ((Z.eqb p0_ 4)) then Write_exclusive_release + else if sumbool_of_bool ((Z.eqb p0_ 5)) then Write_RISCV_release + else if sumbool_of_bool ((Z.eqb p0_ 6)) then Write_RISCV_strong_release + else if sumbool_of_bool ((Z.eqb p0_ 7)) then Write_RISCV_conditional + else if sumbool_of_bool ((Z.eqb p0_ 8)) then Write_RISCV_conditional_release + else if sumbool_of_bool ((Z.eqb p0_ 9)) then Write_RISCV_conditional_strong_release + else Write_X86_locked. + +Definition num_of_write_kind (arg_ : write_kind) +: {e : Z & ArithFact (0 <= e /\ e <= 10)} := + + build_ex(match arg_ with + | Write_plain => 0 + | Write_conditional => 1 + | Write_release => 2 + | Write_exclusive => 3 + | Write_exclusive_release => 4 + | Write_RISCV_release => 5 + | Write_RISCV_strong_release => 6 + | Write_RISCV_conditional => 7 + | Write_RISCV_conditional_release => 8 + | Write_RISCV_conditional_strong_release => 9 + | Write_X86_locked => 10 + end). + +Definition barrier_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 23)} +: barrier_kind := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Barrier_Sync + else if sumbool_of_bool ((Z.eqb p0_ 1)) then Barrier_LwSync + else if sumbool_of_bool ((Z.eqb p0_ 2)) then Barrier_Eieio + else if sumbool_of_bool ((Z.eqb p0_ 3)) then Barrier_Isync + else if sumbool_of_bool ((Z.eqb p0_ 4)) then Barrier_DMB + else if sumbool_of_bool ((Z.eqb p0_ 5)) then Barrier_DMB_ST + else if sumbool_of_bool ((Z.eqb p0_ 6)) then Barrier_DMB_LD + else if sumbool_of_bool ((Z.eqb p0_ 7)) then Barrier_DSB + else if sumbool_of_bool ((Z.eqb p0_ 8)) then Barrier_DSB_ST + else if sumbool_of_bool ((Z.eqb p0_ 9)) then Barrier_DSB_LD + else if sumbool_of_bool ((Z.eqb p0_ 10)) then Barrier_ISB + else if sumbool_of_bool ((Z.eqb p0_ 11)) then Barrier_MIPS_SYNC + else if sumbool_of_bool ((Z.eqb p0_ 12)) then Barrier_RISCV_rw_rw + else if sumbool_of_bool ((Z.eqb p0_ 13)) then Barrier_RISCV_r_rw + else if sumbool_of_bool ((Z.eqb p0_ 14)) then Barrier_RISCV_r_r + else if sumbool_of_bool ((Z.eqb p0_ 15)) then Barrier_RISCV_rw_w + else if sumbool_of_bool ((Z.eqb p0_ 16)) then Barrier_RISCV_w_w + else if sumbool_of_bool ((Z.eqb p0_ 17)) then Barrier_RISCV_w_rw + else if sumbool_of_bool ((Z.eqb p0_ 18)) then Barrier_RISCV_rw_r + else if sumbool_of_bool ((Z.eqb p0_ 19)) then Barrier_RISCV_r_w + else if sumbool_of_bool ((Z.eqb p0_ 20)) then Barrier_RISCV_w_r + else if sumbool_of_bool ((Z.eqb p0_ 21)) then Barrier_RISCV_tso + else if sumbool_of_bool ((Z.eqb p0_ 22)) then Barrier_RISCV_i + else Barrier_x86_MFENCE. + +Definition num_of_barrier_kind (arg_ : barrier_kind) +: {e : Z & ArithFact (0 <= e /\ e <= 23)} := + + build_ex(match arg_ with + | Barrier_Sync => 0 + | Barrier_LwSync => 1 + | Barrier_Eieio => 2 + | Barrier_Isync => 3 + | Barrier_DMB => 4 + | Barrier_DMB_ST => 5 + | Barrier_DMB_LD => 6 + | Barrier_DSB => 7 + | Barrier_DSB_ST => 8 + | Barrier_DSB_LD => 9 + | Barrier_ISB => 10 + | Barrier_MIPS_SYNC => 11 + | Barrier_RISCV_rw_rw => 12 + | Barrier_RISCV_r_rw => 13 + | Barrier_RISCV_r_r => 14 + | Barrier_RISCV_rw_w => 15 + | Barrier_RISCV_w_w => 16 + | Barrier_RISCV_w_rw => 17 + | Barrier_RISCV_rw_r => 18 + | Barrier_RISCV_r_w => 19 + | Barrier_RISCV_w_r => 20 + | Barrier_RISCV_tso => 21 + | Barrier_RISCV_i => 22 + | Barrier_x86_MFENCE => 23 + end). + +Definition trans_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: trans_kind := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Transaction_start + else if sumbool_of_bool ((Z.eqb p0_ 1)) then Transaction_commit + else Transaction_abort. + +Definition num_of_trans_kind (arg_ : trans_kind) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with + | Transaction_start => 0 + | Transaction_commit => 1 + | Transaction_abort => 2 + end). + +Definition GPRstr : vec string 32 := +vec_of_list_len ["x31";"x30";"x29";"x28";"x27";"x26";"x25";"x24";"x23";"x22";"x21";"x20";"x19";"x18";"x17";"x16";"x15";"x14";"x13";"x12";"x11"; + "x10";"x9";"x8";"x7";"x6";"x5";"x4";"x3";"x2";"x1";"x0"]. +Hint Unfold GPRstr : sail. +Definition CIA_fp := RFull ("CIA"). +Hint Unfold CIA_fp : sail. +Definition NIA_fp := RFull ("NIA"). +Hint Unfold NIA_fp : sail. +Definition initial_analysis (instr : ast) +: M ((list regfp * list regfp * list regfp * list niafp * diafp * instruction_kind)) := + + let iR := [] : regfps in + let oR := [] : regfps in + let aR := [] : regfps in + let ik := (IK_simple (tt)) : instruction_kind in + let Nias := [NIAFP_successor (tt)] : niafps in + let Dia := (DIAFP_none (tt)) : diafp in + (match instr with + | EBREAK (tt) => returnm (Nias, aR, iR, ik, oR) + | UTYPE (imm,rd,op) => + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + returnm (Nias, aR, iR, ik, oR) + | RISCV_JAL (imm,rd) => + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + let offset : bits 64 := EXTS 64 imm in + ((read_reg PC_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + let Nias : niafps := [NIAFP_concrete_address (add_vec w__0 offset)] in + let ik : instruction_kind := IK_branch (tt) in + returnm (Nias, aR, iR, ik, oR) + | RISCV_JALR (imm,rs,rd) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs)))) :: iR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + let offset : bits 64 := EXTS 64 imm in + let Nias : niafps := [NIAFP_indirect_address (tt)] in + let ik : instruction_kind := IK_branch (tt) in + returnm (Nias, aR, iR, ik, oR) + | BTYPE (imm,rs2,rs1,op) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs2)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs2)))) :: iR in + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: iR in + let ik := (IK_branch (tt)) : instruction_kind in + let offset : bits 64 := EXTS 64 imm in + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : xlenbits => + let Nias : niafps := [NIAFP_concrete_address (add_vec w__1 offset);NIAFP_successor (tt)] in + returnm (Nias, aR, iR, ik, oR) + | ITYPE (imm,rs,rd,op) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs)))) :: iR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + returnm (Nias, aR, iR, ik, oR) + | SHIFTIOP (imm,rs,rd,op) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs)))) :: iR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + returnm (Nias, aR, iR, ik, oR) + | RTYPE (rs2,rs1,rd,op) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs2)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs2)))) :: iR in + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: iR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + returnm (Nias, aR, iR, ik, oR) + | CSR (csr,rs1,rd,is_imm,op) => + let isWrite : bool := + match op with + | CSRRW => true + | _ => if (is_imm) then neq_int (projT1 (uint rs1)) 0 else neq_int (projT1 (uint rs1)) 0 + end in + let iR : regfps := (RFull (csr_name csr)) :: iR in + let iR : regfps := + if ((negb is_imm)) then + (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: iR + else iR in + let oR : regfps := if (isWrite) then (RFull (csr_name csr)) :: oR else oR in + let oR : regfps := (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + returnm (Nias, aR, iR, ik, oR) + | LOAD (imm,rs,rd,unsign,width,aq,rl) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs)))) :: iR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + let aR := iR : regfps in + (match (aq, rl) with + | (false, false) => returnm ((IK_mem_read (Read_plain)) : instruction_kind ) + | (true, false) => returnm ((IK_mem_read (Read_RISCV_acquire)) : instruction_kind ) + | (true, true) => returnm ((IK_mem_read (Read_RISCV_strong_acquire)) : instruction_kind ) + | _ => + (internal_error "LOAD type not implemented in initial_analysis") : M (instruction_kind) + end) >>= fun w__3 : instruction_kind => + let ik : instruction_kind := w__3 in + returnm (Nias, aR, iR, ik, oR) + | STORE (imm,rs2,rs1,width,aq,rl) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs2)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs2)))) :: iR in + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: iR in + let aR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then aR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: aR in + (match (aq, rl) with + | (false, false) => returnm ((IK_mem_write (Write_plain)) : instruction_kind ) + | (false, true) => returnm ((IK_mem_write (Write_RISCV_release)) : instruction_kind ) + | (true, true) => returnm ((IK_mem_write (Write_RISCV_strong_release)) : instruction_kind ) + | _ => + (internal_error "STORE type not implemented in initial_analysis") : M (instruction_kind) + end) >>= fun w__5 : instruction_kind => + let ik : instruction_kind := w__5 in + returnm (Nias, aR, iR, ik, oR) + | ADDIW (imm,rs,rd) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs)))) :: iR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + returnm (Nias, aR, iR, ik, oR) + | SHIFTW (imm,rs,rd,op) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs)))) :: iR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + returnm (Nias, aR, iR, ik, oR) + | RTYPEW (rs2,rs1,rd,op) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs2)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs2)))) :: iR in + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: iR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + returnm (Nias, aR, iR, ik, oR) + | FENCE (pred,succ) => + (match (pred, succ) with + | (v__844, v__845) => + (if ((andb + (eq_vec (subrange_vec_dec v__844 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__845 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))))) + then + returnm ((IK_barrier + (Barrier_RISCV_rw_rw)) + : instruction_kind ) + else if ((andb + (eq_vec (subrange_vec_dec v__844 1 0) + (vec_of_bits [B1;B0] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__845 1 0) + (vec_of_bits [B1;B1] : mword (1 - 0 + 1))))) then + returnm ((IK_barrier + (Barrier_RISCV_r_rw)) + : instruction_kind ) + else if ((andb + (eq_vec (subrange_vec_dec v__844 1 0) + (vec_of_bits [B1;B0] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__845 1 0) + (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) then + returnm ((IK_barrier + (Barrier_RISCV_r_r)) + : instruction_kind ) + else if ((andb + (eq_vec (subrange_vec_dec v__844 1 0) + (vec_of_bits [B1;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__845 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) then + returnm ((IK_barrier + (Barrier_RISCV_rw_w)) + : instruction_kind ) + else if ((andb + (eq_vec (subrange_vec_dec v__844 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__845 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) then + returnm ((IK_barrier + (Barrier_RISCV_w_w)) + : instruction_kind ) + else if ((andb + (eq_vec (subrange_vec_dec v__844 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__845 1 0) + (vec_of_bits [B1;B1] : mword (1 - 0 + 1))))) then + returnm ((IK_barrier + (Barrier_RISCV_w_rw)) + : instruction_kind ) + else if ((andb + (eq_vec (subrange_vec_dec v__844 1 0) + (vec_of_bits [B1;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__845 1 0) + (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) then + returnm ((IK_barrier + (Barrier_RISCV_rw_r)) + : instruction_kind ) + else if ((andb + (eq_vec (subrange_vec_dec v__844 1 0) + (vec_of_bits [B1;B0] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__845 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) then + returnm ((IK_barrier + (Barrier_RISCV_r_w)) + : instruction_kind ) + else if ((andb + (eq_vec (subrange_vec_dec v__844 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__845 1 0) + (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) then + returnm ((IK_barrier + (Barrier_RISCV_w_r)) + : instruction_kind ) + else if ((andb + (eq_vec (subrange_vec_dec v__844 1 0) + (vec_of_bits [B0;B0] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__845 1 0) + (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) then + returnm ((IK_simple + (tt)) + : instruction_kind ) + else + (internal_error "barrier type not implemented in initial_analysis") + : M (instruction_kind)) + : M (instruction_kind) + end) >>= fun w__17 : instruction_kind => + let ik : instruction_kind := w__17 in + returnm (Nias, aR, iR, ik, oR) + | FENCE_TSO (pred,succ) => + (match (pred, succ) with + | (v__884, v__885) => + (if ((andb + (eq_vec (subrange_vec_dec v__884 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__885 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))))) + then + returnm ((IK_barrier + (Barrier_RISCV_tso)) + : instruction_kind ) + else + (internal_error "barrier type not implemented in initial_analysis") + : M (instruction_kind)) + : M (instruction_kind) + end) >>= fun w__20 : instruction_kind => + let ik : instruction_kind := w__20 in + returnm (Nias, aR, iR, ik, oR) + | FENCEI (tt) => + let ik : instruction_kind := IK_simple (tt) in + returnm (Nias, aR, iR, ik, oR) + | LOADRES (aq,rl,rs1,width,rd) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: iR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + let aR := iR : regfps in + (match (aq, rl) with + | (false, false) => returnm ((IK_mem_read (Read_RISCV_reserved)) : instruction_kind ) + | (true, false) => + returnm ((IK_mem_read (Read_RISCV_reserved_acquire)) : instruction_kind ) + | (true, true) => + returnm ((IK_mem_read (Read_RISCV_reserved_strong_acquire)) : instruction_kind ) + | (false, true) => + (internal_error "LOADRES type not implemented in initial_analysis") + : M (instruction_kind) + end) >>= fun w__22 : instruction_kind => + let ik : instruction_kind := w__22 in + returnm (Nias, aR, iR, ik, oR) + | STORECON (aq,rl,rs2,rs1,width,rd) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs2)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs2)))) :: iR in + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: iR in + let aR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then aR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: aR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + (match (aq, rl) with + | (false, false) => returnm ((IK_mem_write (Write_RISCV_conditional)) : instruction_kind ) + | (false, true) => + returnm ((IK_mem_write (Write_RISCV_conditional_release)) : instruction_kind ) + | (true, true) => + returnm ((IK_mem_write (Write_RISCV_conditional_strong_release)) : instruction_kind ) + | (true, false) => + (internal_error "STORECON type not implemented in initial_analysis") + : M (instruction_kind) + end) >>= fun w__24 : instruction_kind => + let ik : instruction_kind := w__24 in + returnm (Nias, aR, iR, ik, oR) + | AMO (op,aq,rl,rs2,rs1,width,rd) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs2)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs2)))) :: iR in + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: iR in + let aR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then aR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: aR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + let ik : instruction_kind := + match (aq, rl) with + | (false, false) => IK_mem_rmw ((Read_RISCV_reserved, Write_RISCV_conditional)) + | (false, true) => IK_mem_rmw ((Read_RISCV_reserved, Write_RISCV_conditional_release)) + | (true, false) => IK_mem_rmw ((Read_RISCV_reserved_acquire, Write_RISCV_conditional)) + | (true, true) => + IK_mem_rmw ((Read_RISCV_reserved_acquire, Write_RISCV_conditional_release)) + end in + returnm (Nias, aR, iR, ik, oR) + | _ => returnm (Nias, aR, iR, ik, oR) + end) >>= fun '(Nias, aR, iR, ik, oR) => + returnm (iR, oR, aR, Nias, Dia, ik). + +Definition initial_regstate : regstate := +{| tlb39 := None; + htif_exit_code := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + htif_done := false; + htif_tohost := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + mtimecmp := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + tselect := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + stval := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + scause := + ({| Mcause_Mcause_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + sepc := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + sscratch := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + stvec := + ({| Mtvec_Mtvec_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + satp := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + sideleg := + ({| Sinterrupts_Sinterrupts_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + sedeleg := + ({| Sedeleg_Sedeleg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + pmpcfg0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + pmpaddr0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + mhartid := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + marchid := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + mimpid := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + mvendorid := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + minstret_written := false; + minstret := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + mtime := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + mcycle := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + scounteren := + ({| Counteren_Counteren_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) |}); + mcounteren := + ({| Counteren_Counteren_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) |}); + mscratch := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + mtval := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + mepc := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + mcause := + ({| Mcause_Mcause_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + mtvec := + ({| Mtvec_Mtvec_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + medeleg := + ({| Medeleg_Medeleg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + mideleg := + ({| Minterrupts_Minterrupts_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + mie := + ({| Minterrupts_Minterrupts_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + mip := + ({| Minterrupts_Minterrupts_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + mstatus := + ({| Mstatus_Mstatus_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + misa := + ({| Misa_Misa_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + cur_inst := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + cur_privilege := User; + x31 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x30 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x29 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x28 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x27 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x26 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x25 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x24 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x23 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x22 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x21 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x20 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x19 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x18 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x17 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x16 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x15 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x14 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x13 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x12 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x11 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x10 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x9 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x8 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x7 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x6 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x5 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x4 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x3 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x2 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Xs := + (vec_of_list_len [(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64)]); + instbits := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + nextPC := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + PC := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}. +Hint Unfold initial_regstate : sail. + +End Content. diff --git a/snapshots/coq/riscv/riscv_extras.v b/snapshots/coq/riscv/riscv_extras.v new file mode 100644 index 00000000..ff235a98 --- /dev/null +++ b/snapshots/coq/riscv/riscv_extras.v @@ -0,0 +1,145 @@ +Require Import Sail2_instr_kinds. +Require Import Sail2_values. +Require Import Sail2_operators_mwords. +Require Import Sail2_prompt_monad. +Require Import Sail2_prompt. +Require Import String. +Require Import List. +Import List.ListNotations. + +Axiom real : Type. + +Definition MEM_fence_rw_rw {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_rw_rw. +Definition MEM_fence_r_rw {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_r_rw. +Definition MEM_fence_r_r {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_r_r. +Definition MEM_fence_rw_w {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_rw_w. +Definition MEM_fence_w_w {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_w_w. +Definition MEM_fence_w_rw {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_w_rw. +Definition MEM_fence_rw_r {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_rw_r. +Definition MEM_fence_r_w {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_r_w. +Definition MEM_fence_w_r {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_w_r. +Definition MEM_fence_tso {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_tso. +Definition MEM_fence_i {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_i. +(* +val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e +val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e +val MEMea_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e +val MEMea_conditional : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e +val MEMea_conditional_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e +val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e +*) +Definition MEMea {rv a e} (addr : mword a) size : monad rv unit e := write_mem_ea Write_plain addr size. +Definition MEMea_release {rv a e} (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_release addr size. +Definition MEMea_strong_release {rv a e} (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_strong_release addr size. +Definition MEMea_conditional {rv a e} (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_conditional addr size. +Definition MEMea_conditional_release {rv a e} (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_conditional_release addr size. +Definition MEMea_conditional_strong_release {rv a e} (addr : mword a) size : monad rv unit e + := write_mem_ea Write_RISCV_conditional_strong_release addr size. + + +(* Some wrappers copied from aarch64_extras *) +(* TODO: Harmonise into a common library *) +(* +Definition get_slice_int_bl len n lo := + (* TODO: Is this the intended behaviour? *) + let hi := lo + len - 1 in + let bs := bools_of_int (hi + 1) n in + subrange_list false bs hi lo + +val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a +Definition get_slice_int len n lo := of_bools (get_slice_int_bl len n lo) +*) +Definition write_ram {rv e} m size (hexRAM : mword m) (addr : mword m) (data : mword (8 * size)) : monad rv bool e := + write_mem_val data. + +Definition read_ram {rv e} m size `{ArithFact (size >= 0)} (_ : mword m) (addr : mword m) : monad rv (mword (8 * size)) e := + read_mem Read_plain addr size. +(* +Definition string_of_bits bs := string_of_bv (bits_of bs). +Definition string_of_int := show + +Definition _sign_extend bits len := maybe_failwith (of_bits (exts_bv len bits)) +Definition _zero_extend bits len := maybe_failwith (of_bits (extz_bv len bits)) +*) +Definition shift_bits_left {a b} (v : mword a) (n : mword b) : mword a := + shiftl v (int_of_mword false n). + +Definition shift_bits_right {a b} (v : mword a) (n : mword b) : mword a := + shiftr v (int_of_mword false n). + +Definition shift_bits_right_arith {a b} (v : mword a) (n : mword b) : mword a := + arith_shiftr v (int_of_mword false n). + +(* Use constants for undefined values for now *) +Definition internal_pick {rv a e} (vs : list a) : monad rv a e := +match vs with +| (h::_) => returnm h +| _ => Fail "empty list in internal_pick" +end. +Definition undefined_string {rv e} (_:unit) : monad rv string e := returnm ""%string. +Definition undefined_unit {rv e} (_:unit) : monad rv unit e := returnm tt. +Definition undefined_int {rv e} (_:unit) : monad rv Z e := returnm (0:ii). +(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*) +Definition undefined_vector {rv a e} len (u : a) `{ArithFact (len >= 0)} : monad rv (vec a len) e := returnm (vec_init u len). +(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) +Definition undefined_bitvector {rv e} len `{ArithFact (len >= 0)} : monad rv (mword len) e := returnm (mword_of_int 0). +(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) +Definition undefined_bits {rv e} := @undefined_bitvector rv e. +Definition undefined_bit {rv e} (_:unit) : monad rv bitU e := returnm BU. +(*Definition undefined_real {rv e} (_:unit) : monad rv real e := returnm (realFromFrac 0 1).*) +Definition undefined_range {rv e} i j `{ArithFact (i <= j)} : monad rv {z : Z & ArithFact (i <= z /\ z <= j)} e := returnm (build_ex i). +Definition undefined_atom {rv e} i : monad rv Z e := returnm i. +Definition undefined_nat {rv e} (_:unit) : monad rv Z e := returnm (0:ii). + +Definition skip {rv e} (_:unit) : monad rv unit e := returnm tt. + +(*val elf_entry : unit -> integer*) +Definition elf_entry (_:unit) : Z := 0. +(*declare ocaml target_rep function elf_entry := `Elf_loader.elf_entry`*) + +Definition print_bits {n} msg (bs : mword n) := prerr_endline (msg ++ (string_of_bits bs)). + +(*val get_time_ns : unit -> integer*) +Definition get_time_ns (_:unit) : Z := 0. +(*declare ocaml target_rep function get_time_ns := `(fun () -> Big_int.of_int (int_of_float (1e9 *. Unix.gettimeofday ())))`*) + +Definition eq_bit (x : bitU) (y : bitU) : bool := + match x, y with + | B0, B0 => true + | B1, B1 => true + | BU, BU => true + | _,_ => false + end. + +Require Import Zeuclid. +Definition euclid_modulo (m n : Z) `{ArithFact (n > 0)} : {z : Z & ArithFact (0 <= z <= n-1)}. +apply existT with (x := ZEuclid.modulo m n). +constructor. +destruct H. +assert (Z.abs n = n). { rewrite Z.abs_eq; auto with zarith. } +rewrite <- H at 3. +lapply (ZEuclid.mod_always_pos m n); omega. +Qed. + +(* Override the more general version *) + +Definition mults_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mults_vec l r. +Definition mult_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mult_vec l r. + + +Definition print_endline (_:string) : unit := tt. +Definition prerr_endline (_:string) : unit := tt. +Definition prerr_string (_:string) : unit := tt. +Definition putchar {T} (_:T) : unit := tt. +Require DecimalString. +Definition string_of_int z := DecimalString.NilZero.string_of_int (Z.to_int z). + +(* The constraint solver can do this itself, but a Coq bug puts + anonymous_subproof into the term instead of an actual subproof. *) +Lemma n_leading_spaces_fact {w__0} : + w__0 >= 0 -> exists ex17629_ : Z, 1 + w__0 = 1 + ex17629_ /\ 0 <= ex17629_. +intro. +exists w__0. +omega. +Qed. +Hint Resolve n_leading_spaces_fact : sail. diff --git a/snapshots/coq/riscv/riscv_types.v b/snapshots/coq/riscv/riscv_types.v new file mode 100644 index 00000000..963f498d --- /dev/null +++ b/snapshots/coq/riscv/riscv_types.v @@ -0,0 +1,1428 @@ +(*Generated by Sail from riscv.*) +Require Import Sail2_instr_kinds. +Require Import Sail2_values. +Require Import Sail2_string. +Require Import Sail2_real. +Require Import Sail2_operators_mwords. +Require Import Sail2_prompt_monad. +Require Import Sail2_prompt. +Require Import Sail2_state. +Definition bits (n : Z) : Type := mword n. + + + +Definition xlenbits : Type := bits 64. + +Definition half : Type := bits 16. + +Definition word : Type := bits 32. + +Definition regbits : Type := bits 5. + +Definition cregbits : Type := bits 3. + +Definition csreg : Type := bits 12. + +Definition regno (n : Z)`{ArithFact (0 <= n /\ (n + 1) <= 32)} : Type := Z. + +Definition opcode : Type := bits 7. + +Definition imm12 : Type := bits 12. + +Definition imm20 : Type := bits 20. + +Definition amo : Type := bits 1. + +Inductive Architecture := RV32 | RV64 | RV128. +Scheme Equality for Architecture. +Instance Decidable_eq_Architecture : +forall (x y : Architecture), Decidable (x = y) := +Decidable_eq_from_dec Architecture_eq_dec. + + +Definition arch_xlen : Type := bits 2. + +Definition priv_level : Type := bits 2. + +Inductive Privilege := User | Supervisor | Machine. +Scheme Equality for Privilege. +Instance Decidable_eq_Privilege : +forall (x y : Privilege), Decidable (x = y) := +Decidable_eq_from_dec Privilege_eq_dec. + + +Inductive AccessType := Read | Write | ReadWrite | Execute. +Scheme Equality for AccessType. +Instance Decidable_eq_AccessType : +forall (x y : AccessType), Decidable (x = y) := +Decidable_eq_from_dec AccessType_eq_dec. + + +Inductive ReadType := Instruction | Data. +Scheme Equality for ReadType. +Instance Decidable_eq_ReadType : +forall (x y : ReadType), Decidable (x = y) := +Decidable_eq_from_dec ReadType_eq_dec. + + +Inductive word_width := BYTE | HALF | WORD | DOUBLE. +Scheme Equality for word_width. +Instance Decidable_eq_word_width : +forall (x y : word_width), Decidable (x = y) := +Decidable_eq_from_dec word_width_eq_dec. + + +Definition exc_code : Type := bits 4. + +Inductive InterruptType := + I_U_Software + | I_S_Software + | I_M_Software + | I_U_Timer + | I_S_Timer + | I_M_Timer + | I_U_External + | I_S_External + | I_M_External. +Scheme Equality for InterruptType. +Instance Decidable_eq_InterruptType : +forall (x y : InterruptType), Decidable (x = y) := +Decidable_eq_from_dec InterruptType_eq_dec. + + +Inductive ExceptionType := + E_Fetch_Addr_Align + | E_Fetch_Access_Fault + | E_Illegal_Instr + | E_Breakpoint + | E_Load_Addr_Align + | E_Load_Access_Fault + | E_SAMO_Addr_Align + | E_SAMO_Access_Fault + | E_U_EnvCall + | E_S_EnvCall + | E_Reserved_10 + | E_M_EnvCall + | E_Fetch_Page_Fault + | E_Load_Page_Fault + | E_Reserved_14 + | E_SAMO_Page_Fault. +Scheme Equality for ExceptionType. +Instance Decidable_eq_ExceptionType : +forall (x y : ExceptionType), Decidable (x = y) := +Decidable_eq_from_dec ExceptionType_eq_dec. + + +Inductive exception := + Error_not_implemented : string -> exception | Error_internal_error : unit -> exception. +Arguments exception : clear implicits. + + + +Definition tv_mode : Type := bits 2. + +Inductive TrapVectorMode := TV_Direct | TV_Vector | TV_Reserved. +Scheme Equality for TrapVectorMode. +Instance Decidable_eq_TrapVectorMode : +forall (x y : TrapVectorMode), Decidable (x = y) := +Decidable_eq_from_dec TrapVectorMode_eq_dec. + + +Definition ext_status : Type := bits 2. + +Inductive ExtStatus := Off | Initial | Clean | Dirty. +Scheme Equality for ExtStatus. +Instance Decidable_eq_ExtStatus : +forall (x y : ExtStatus), Decidable (x = y) := +Decidable_eq_from_dec ExtStatus_eq_dec. + + +Definition satp_mode : Type := bits 4. + +Inductive SATPMode := Sbare | Sv32 | Sv39. +Scheme Equality for SATPMode. +Instance Decidable_eq_SATPMode : +forall (x y : SATPMode), Decidable (x = y) := +Decidable_eq_from_dec SATPMode_eq_dec. + + +Definition csrRW : Type := bits 2. + +Inductive uop := RISCV_LUI | RISCV_AUIPC. +Scheme Equality for uop. +Instance Decidable_eq_uop : +forall (x y : uop), Decidable (x = y) := +Decidable_eq_from_dec uop_eq_dec. + + +Inductive bop := RISCV_BEQ | RISCV_BNE | RISCV_BLT | RISCV_BGE | RISCV_BLTU | RISCV_BGEU. +Scheme Equality for bop. +Instance Decidable_eq_bop : +forall (x y : bop), Decidable (x = y) := +Decidable_eq_from_dec bop_eq_dec. + + +Inductive iop := RISCV_ADDI | RISCV_SLTI | RISCV_SLTIU | RISCV_XORI | RISCV_ORI | RISCV_ANDI. +Scheme Equality for iop. +Instance Decidable_eq_iop : +forall (x y : iop), Decidable (x = y) := +Decidable_eq_from_dec iop_eq_dec. + + +Inductive sop := RISCV_SLLI | RISCV_SRLI | RISCV_SRAI. +Scheme Equality for sop. +Instance Decidable_eq_sop : +forall (x y : sop), Decidable (x = y) := +Decidable_eq_from_dec sop_eq_dec. + + +Inductive rop := + RISCV_ADD + | RISCV_SUB + | RISCV_SLL + | RISCV_SLT + | RISCV_SLTU + | RISCV_XOR + | RISCV_SRL + | RISCV_SRA + | RISCV_OR + | RISCV_AND. +Scheme Equality for rop. +Instance Decidable_eq_rop : +forall (x y : rop), Decidable (x = y) := +Decidable_eq_from_dec rop_eq_dec. + + +Inductive ropw := RISCV_ADDW | RISCV_SUBW | RISCV_SLLW | RISCV_SRLW | RISCV_SRAW. +Scheme Equality for ropw. +Instance Decidable_eq_ropw : +forall (x y : ropw), Decidable (x = y) := +Decidable_eq_from_dec ropw_eq_dec. + + +Inductive sopw := RISCV_SLLIW | RISCV_SRLIW | RISCV_SRAIW. +Scheme Equality for sopw. +Instance Decidable_eq_sopw : +forall (x y : sopw), Decidable (x = y) := +Decidable_eq_from_dec sopw_eq_dec. + + +Inductive amoop := AMOSWAP | AMOADD | AMOXOR | AMOAND | AMOOR | AMOMIN | AMOMAX | AMOMINU | AMOMAXU. +Scheme Equality for amoop. +Instance Decidable_eq_amoop : +forall (x y : amoop), Decidable (x = y) := +Decidable_eq_from_dec amoop_eq_dec. + + +Inductive csrop := CSRRW | CSRRS | CSRRC. +Scheme Equality for csrop. +Instance Decidable_eq_csrop : +forall (x y : csrop), Decidable (x = y) := +Decidable_eq_from_dec csrop_eq_dec. + + +Record Misa := { Misa_Misa_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'Misa_Misa_chunk_0' := e ]}" := ({| Misa_Misa_chunk_0 := e |}). + +Record SV39_PTE := { SV39_PTE_SV39_PTE_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'SV39_PTE_SV39_PTE_chunk_0' := e ]}" := ({| SV39_PTE_SV39_PTE_chunk_0 := e |}). + +Record PTE_Bits := { PTE_Bits_PTE_Bits_chunk_0 : mword 8; }. +Notation "{[ r 'with' 'PTE_Bits_PTE_Bits_chunk_0' := e ]}" := ({| PTE_Bits_PTE_Bits_chunk_0 := e |}). + +Record Mstatus := { Mstatus_Mstatus_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'Mstatus_Mstatus_chunk_0' := e ]}" := ({| Mstatus_Mstatus_chunk_0 := e |}). + +Record Sstatus := { Sstatus_Sstatus_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'Sstatus_Sstatus_chunk_0' := e ]}" := ({| Sstatus_Sstatus_chunk_0 := e |}). + +Record Minterrupts := { Minterrupts_Minterrupts_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'Minterrupts_Minterrupts_chunk_0' := e ]}" := ({| Minterrupts_Minterrupts_chunk_0 := e |}). + +Record Sinterrupts := { Sinterrupts_Sinterrupts_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'Sinterrupts_Sinterrupts_chunk_0' := e ]}" := ({| Sinterrupts_Sinterrupts_chunk_0 := e |}). + +Record Medeleg := { Medeleg_Medeleg_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'Medeleg_Medeleg_chunk_0' := e ]}" := ({| Medeleg_Medeleg_chunk_0 := e |}). + +Record Sedeleg := { Sedeleg_Sedeleg_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'Sedeleg_Sedeleg_chunk_0' := e ]}" := ({| Sedeleg_Sedeleg_chunk_0 := e |}). + +Record Mtvec := { Mtvec_Mtvec_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'Mtvec_Mtvec_chunk_0' := e ]}" := ({| Mtvec_Mtvec_chunk_0 := e |}). + +Record Satp64 := { Satp64_Satp64_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'Satp64_Satp64_chunk_0' := e ]}" := ({| Satp64_Satp64_chunk_0 := e |}). + +Record Mcause := { Mcause_Mcause_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'Mcause_Mcause_chunk_0' := e ]}" := ({| Mcause_Mcause_chunk_0 := e |}). + +Record Counteren := { Counteren_Counteren_chunk_0 : mword 32; }. +Notation "{[ r 'with' 'Counteren_Counteren_chunk_0' := e ]}" := ({| Counteren_Counteren_chunk_0 := e |}). + +Record sync_exception := + { sync_exception_trap : ExceptionType; sync_exception_excinfo : option xlenbits; }. +Notation "{[ r 'with' 'sync_exception_trap' := e ]}" := ({| sync_exception_trap := e; sync_exception_excinfo := sync_exception_excinfo r |}). +Notation "{[ r 'with' 'sync_exception_excinfo' := e ]}" := ({| sync_exception_excinfo := e; sync_exception_trap := sync_exception_trap r |}). + +Inductive ctl_result := + CTL_TRAP : sync_exception -> ctl_result + | CTL_SRET : unit -> ctl_result + | CTL_MRET : unit -> ctl_result. +Arguments ctl_result : clear implicits. + + + +Inductive MemoryOpResult {a : Type} := + MemValue : a -> MemoryOpResult | MemException : ExceptionType -> MemoryOpResult. +Arguments MemoryOpResult : clear implicits. + + + +Record htif_cmd := { htif_cmd_htif_cmd_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'htif_cmd_htif_cmd_chunk_0' := e ]}" := ({| htif_cmd_htif_cmd_chunk_0 := e |}). + +Definition pteAttribs : Type := bits 8. + +Inductive PTW_Error := + PTW_Access | PTW_Invalid_PTE | PTW_No_Permission | PTW_Misaligned | PTW_PTE_Update. +Scheme Equality for PTW_Error. +Instance Decidable_eq_PTW_Error : +forall (x y : PTW_Error), Decidable (x = y) := +Decidable_eq_from_dec PTW_Error_eq_dec. + + +Definition vaddr39 : Type := bits 39. + +Definition paddr39 : Type := bits 56. + +Definition pte39 : Type := xlenbits. + +Record SV39_Vaddr := { SV39_Vaddr_SV39_Vaddr_chunk_0 : mword 39; }. +Notation "{[ r 'with' 'SV39_Vaddr_SV39_Vaddr_chunk_0' := e ]}" := ({| SV39_Vaddr_SV39_Vaddr_chunk_0 := e |}). + +Record SV39_Paddr := { SV39_Paddr_SV39_Paddr_chunk_0 : mword 56; }. +Notation "{[ r 'with' 'SV39_Paddr_SV39_Paddr_chunk_0' := e ]}" := ({| SV39_Paddr_SV39_Paddr_chunk_0 := e |}). + +Definition asid64 : Type := bits 16. + +Inductive PTW_Result := + PTW_Success : (paddr39 * SV39_PTE * paddr39 * {n : Z & ArithFact (n >= 0)} * bool) -> PTW_Result + | PTW_Failure : PTW_Error -> PTW_Result. +Arguments PTW_Result : clear implicits. + + + +Record TLB39_Entry := + { TLB39_Entry_asid : asid64; + TLB39_Entry_global : bool; + TLB39_Entry_vAddr : vaddr39; + TLB39_Entry_pAddr : paddr39; + TLB39_Entry_vMatchMask : vaddr39; + TLB39_Entry_vAddrMask : vaddr39; + TLB39_Entry_pte : SV39_PTE; + TLB39_Entry_pteAddr : paddr39; + TLB39_Entry_age : xlenbits; }. +Notation "{[ r 'with' 'TLB39_Entry_asid' := e ]}" := ({| TLB39_Entry_asid := e; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). +Notation "{[ r 'with' 'TLB39_Entry_global' := e ]}" := ({| TLB39_Entry_global := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). +Notation "{[ r 'with' 'TLB39_Entry_vAddr' := e ]}" := ({| TLB39_Entry_vAddr := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). +Notation "{[ r 'with' 'TLB39_Entry_pAddr' := e ]}" := ({| TLB39_Entry_pAddr := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). +Notation "{[ r 'with' 'TLB39_Entry_vMatchMask' := e ]}" := ({| TLB39_Entry_vMatchMask := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). +Notation "{[ r 'with' 'TLB39_Entry_vAddrMask' := e ]}" := ({| TLB39_Entry_vAddrMask := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). +Notation "{[ r 'with' 'TLB39_Entry_pte' := e ]}" := ({| TLB39_Entry_pte := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). +Notation "{[ r 'with' 'TLB39_Entry_pteAddr' := e ]}" := ({| TLB39_Entry_pteAddr := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_age := TLB39_Entry_age r |}). +Notation "{[ r 'with' 'TLB39_Entry_age' := e ]}" := ({| TLB39_Entry_age := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r |}). + +Inductive TR39_Result := + TR39_Address : paddr39 -> TR39_Result | TR39_Failure : PTW_Error -> TR39_Result. +Arguments TR39_Result : clear implicits. + + + +Inductive TR_Result := TR_Address : xlenbits -> TR_Result | TR_Failure : ExceptionType -> TR_Result. +Arguments TR_Result : clear implicits. + + + +Inductive ast := + UTYPE : (bits 20 * regbits * uop) -> ast + | RISCV_JAL : (bits 21 * regbits) -> ast + | RISCV_JALR : (bits 12 * regbits * regbits) -> ast + | BTYPE : (bits 13 * regbits * regbits * bop) -> ast + | ITYPE : (bits 12 * regbits * regbits * iop) -> ast + | SHIFTIOP : (bits 6 * regbits * regbits * sop) -> ast + | RTYPE : (regbits * regbits * regbits * rop) -> ast + | LOAD : (bits 12 * regbits * regbits * bool * word_width * bool * bool) -> ast + | STORE : (bits 12 * regbits * regbits * word_width * bool * bool) -> ast + | ADDIW : (bits 12 * regbits * regbits) -> ast + | SHIFTW : (bits 5 * regbits * regbits * sop) -> ast + | RTYPEW : (regbits * regbits * regbits * ropw) -> ast + | SHIFTIWOP : (bits 5 * regbits * regbits * sopw) -> ast + | MUL : (regbits * regbits * regbits * bool * bool * bool) -> ast + | DIV : (regbits * regbits * regbits * bool) -> ast + | REM : (regbits * regbits * regbits * bool) -> ast + | MULW : (regbits * regbits * regbits) -> ast + | DIVW : (regbits * regbits * regbits * bool) -> ast + | REMW : (regbits * regbits * regbits * bool) -> ast + | FENCE : (bits 4 * bits 4) -> ast + | FENCE_TSO : (bits 4 * bits 4) -> ast + | FENCEI : unit -> ast + | ECALL : unit -> ast + | MRET : unit -> ast + | SRET : unit -> ast + | EBREAK : unit -> ast + | WFI : unit -> ast + | SFENCE_VMA : (regbits * regbits) -> ast + | LOADRES : (bool * bool * regbits * word_width * regbits) -> ast + | STORECON : (bool * bool * regbits * regbits * word_width * regbits) -> ast + | AMO : (amoop * bool * bool * regbits * regbits * word_width * regbits) -> ast + | CSR : (bits 12 * regbits * regbits * bool * csrop) -> ast + | C_NOP : unit -> ast + | C_ADDI4SPN : (cregbits * bits 8) -> ast + | C_LW : (bits 5 * cregbits * cregbits) -> ast + | C_LD : (bits 5 * cregbits * cregbits) -> ast + | C_SW : (bits 5 * cregbits * cregbits) -> ast + | C_SD : (bits 5 * cregbits * cregbits) -> ast + | C_ADDI : (bits 6 * regbits) -> ast + | C_JAL : bits 11 -> ast + | C_ADDIW : (bits 6 * regbits) -> ast + | C_LI : (bits 6 * regbits) -> ast + | C_ADDI16SP : bits 6 -> ast + | C_LUI : (bits 6 * regbits) -> ast + | C_SRLI : (bits 6 * cregbits) -> ast + | C_SRAI : (bits 6 * cregbits) -> ast + | C_ANDI : (bits 6 * cregbits) -> ast + | C_SUB : (cregbits * cregbits) -> ast + | C_XOR : (cregbits * cregbits) -> ast + | C_OR : (cregbits * cregbits) -> ast + | C_AND : (cregbits * cregbits) -> ast + | C_SUBW : (cregbits * cregbits) -> ast + | C_ADDW : (cregbits * cregbits) -> ast + | C_J : bits 11 -> ast + | C_BEQZ : (bits 8 * cregbits) -> ast + | C_BNEZ : (bits 8 * cregbits) -> ast + | C_SLLI : (bits 6 * regbits) -> ast + | C_LWSP : (bits 6 * regbits) -> ast + | C_LDSP : (bits 6 * regbits) -> ast + | C_SWSP : (bits 6 * regbits) -> ast + | C_SDSP : (bits 6 * regbits) -> ast + | C_JR : regbits -> ast + | C_JALR : regbits -> ast + | C_MV : (regbits * regbits) -> ast + | C_EBREAK : unit -> ast + | C_ADD : (regbits * regbits) -> ast + | STOP_FETCHING : unit -> ast + | THREAD_START : unit -> ast + | ILLEGAL : word -> ast + | C_ILLEGAL : half -> ast. +Arguments ast : clear implicits. + + + +Inductive regfp := + RFull : string -> regfp + | RSlice : (string * {n : Z & ArithFact (n >= 0)} * {n : Z & ArithFact (n >= 0)}) -> regfp + | RSliceBit : (string * {n : Z & ArithFact (n >= 0)}) -> regfp + | RField : (string * string) -> regfp. +Arguments regfp : clear implicits. + + + +Definition regfps : Type := list regfp. + +Inductive niafp := + NIAFP_successor : unit -> niafp + | NIAFP_concrete_address : bits 64 -> niafp + | NIAFP_indirect_address : unit -> niafp. +Arguments niafp : clear implicits. + + + +Definition niafps : Type := list niafp. + +Inductive diafp := + DIAFP_none : unit -> diafp | DIAFP_concrete : bits 64 -> diafp | DIAFP_reg : regfp -> diafp. +Arguments diafp : clear implicits. + + + + + + + + + + + + + +Inductive register_value := + Regval_vector : (Z * bool * list register_value) -> register_value + | Regval_list : list register_value -> register_value + | Regval_option : option register_value -> register_value + | Regval_Counteren : Counteren -> register_value + | Regval_Mcause : Mcause -> register_value + | Regval_Medeleg : Medeleg -> register_value + | Regval_Minterrupts : Minterrupts -> register_value + | Regval_Misa : Misa -> register_value + | Regval_Mstatus : Mstatus -> register_value + | Regval_Mtvec : Mtvec -> register_value + | Regval_Privilege : Privilege -> register_value + | Regval_Sedeleg : Sedeleg -> register_value + | Regval_Sinterrupts : Sinterrupts -> register_value + | Regval_TLB39_Entry : TLB39_Entry -> register_value + | Regval_bool : bool -> register_value + | Regval_vector_64_dec_bit : mword 64 -> register_value. +Arguments register_value : clear implicits. + + + +Record regstate := + { tlb39 : option TLB39_Entry; + htif_exit_code : mword 64; + htif_done : bool; + htif_tohost : mword 64; + mtimecmp : mword 64; + tselect : mword 64; + stval : mword 64; + scause : Mcause; + sepc : mword 64; + sscratch : mword 64; + stvec : Mtvec; + satp : mword 64; + sideleg : Sinterrupts; + sedeleg : Sedeleg; + pmpcfg0 : mword 64; + pmpaddr0 : mword 64; + mhartid : mword 64; + marchid : mword 64; + mimpid : mword 64; + mvendorid : mword 64; + minstret_written : bool; + minstret : mword 64; + mtime : mword 64; + mcycle : mword 64; + scounteren : Counteren; + mcounteren : Counteren; + mscratch : mword 64; + mtval : mword 64; + mepc : mword 64; + mcause : Mcause; + mtvec : Mtvec; + medeleg : Medeleg; + mideleg : Minterrupts; + mie : Minterrupts; + mip : Minterrupts; + mstatus : Mstatus; + misa : Misa; + cur_inst : mword 64; + cur_privilege : Privilege; + x31 : mword 64; + x30 : mword 64; + x29 : mword 64; + x28 : mword 64; + x27 : mword 64; + x26 : mword 64; + x25 : mword 64; + x24 : mword 64; + x23 : mword 64; + x22 : mword 64; + x21 : mword 64; + x20 : mword 64; + x19 : mword 64; + x18 : mword 64; + x17 : mword 64; + x16 : mword 64; + x15 : mword 64; + x14 : mword 64; + x13 : mword 64; + x12 : mword 64; + x11 : mword 64; + x10 : mword 64; + x9 : mword 64; + x8 : mword 64; + x7 : mword 64; + x6 : mword 64; + x5 : mword 64; + x4 : mword 64; + x3 : mword 64; + x2 : mword 64; + x1 : mword 64; + Xs : vec (mword 64) 32; + instbits : mword 64; + nextPC : mword 64; + PC : mword 64; }. +Notation "{[ r 'with' 'tlb39' := e ]}" := ({| tlb39 := e; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'htif_exit_code' := e ]}" := ({| htif_exit_code := e; tlb39 := tlb39 r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'htif_done' := e ]}" := ({| htif_done := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'htif_tohost' := e ]}" := ({| htif_tohost := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mtimecmp' := e ]}" := ({| mtimecmp := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'tselect' := e ]}" := ({| tselect := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'stval' := e ]}" := ({| stval := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'scause' := e ]}" := ({| scause := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'sepc' := e ]}" := ({| sepc := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'sscratch' := e ]}" := ({| sscratch := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'stvec' := e ]}" := ({| stvec := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'satp' := e ]}" := ({| satp := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'sideleg' := e ]}" := ({| sideleg := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'sedeleg' := e ]}" := ({| sedeleg := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'pmpcfg0' := e ]}" := ({| pmpcfg0 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'pmpaddr0' := e ]}" := ({| pmpaddr0 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mhartid' := e ]}" := ({| mhartid := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'marchid' := e ]}" := ({| marchid := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mimpid' := e ]}" := ({| mimpid := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mvendorid' := e ]}" := ({| mvendorid := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'minstret_written' := e ]}" := ({| minstret_written := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'minstret' := e ]}" := ({| minstret := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mtime' := e ]}" := ({| mtime := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mcycle' := e ]}" := ({| mcycle := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'scounteren' := e ]}" := ({| scounteren := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mcounteren' := e ]}" := ({| mcounteren := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mscratch' := e ]}" := ({| mscratch := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mtval' := e ]}" := ({| mtval := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mepc' := e ]}" := ({| mepc := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mcause' := e ]}" := ({| mcause := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mtvec' := e ]}" := ({| mtvec := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'medeleg' := e ]}" := ({| medeleg := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mideleg' := e ]}" := ({| mideleg := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mie' := e ]}" := ({| mie := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mip' := e ]}" := ({| mip := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mstatus' := e ]}" := ({| mstatus := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'misa' := e ]}" := ({| misa := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'cur_inst' := e ]}" := ({| cur_inst := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'cur_privilege' := e ]}" := ({| cur_privilege := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x31' := e ]}" := ({| x31 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x30' := e ]}" := ({| x30 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x29' := e ]}" := ({| x29 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x28' := e ]}" := ({| x28 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x27' := e ]}" := ({| x27 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x26' := e ]}" := ({| x26 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x25' := e ]}" := ({| x25 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x24' := e ]}" := ({| x24 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x23' := e ]}" := ({| x23 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x22' := e ]}" := ({| x22 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x21' := e ]}" := ({| x21 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x20' := e ]}" := ({| x20 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x19' := e ]}" := ({| x19 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x18' := e ]}" := ({| x18 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x17' := e ]}" := ({| x17 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x16' := e ]}" := ({| x16 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x15' := e ]}" := ({| x15 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x14' := e ]}" := ({| x14 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x13' := e ]}" := ({| x13 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x12' := e ]}" := ({| x12 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x11' := e ]}" := ({| x11 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x10' := e ]}" := ({| x10 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x9' := e ]}" := ({| x9 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x8' := e ]}" := ({| x8 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x7' := e ]}" := ({| x7 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x6' := e ]}" := ({| x6 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x5' := e ]}" := ({| x5 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x4' := e ]}" := ({| x4 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x3' := e ]}" := ({| x3 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x2' := e ]}" := ({| x2 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x1' := e ]}" := ({| x1 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'Xs' := e ]}" := ({| Xs := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'instbits' := e ]}" := ({| instbits := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'nextPC' := e ]}" := ({| nextPC := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; PC := PC r |}). +Notation "{[ r 'with' 'PC' := e ]}" := ({| PC := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r |}). + + + +Definition Counteren_of_regval (merge_var : register_value) +: option Counteren := + + match merge_var with | Regval_Counteren (v) => Some (v) | g__12 => None end. + +Definition regval_of_Counteren (v : Counteren) : register_value := Regval_Counteren (v). + +Definition Mcause_of_regval (merge_var : register_value) +: option Mcause := + + match merge_var with | Regval_Mcause (v) => Some (v) | g__11 => None end. + +Definition regval_of_Mcause (v : Mcause) : register_value := Regval_Mcause (v). + +Definition Medeleg_of_regval (merge_var : register_value) +: option Medeleg := + + match merge_var with | Regval_Medeleg (v) => Some (v) | g__10 => None end. + +Definition regval_of_Medeleg (v : Medeleg) : register_value := Regval_Medeleg (v). + +Definition Minterrupts_of_regval (merge_var : register_value) +: option Minterrupts := + + match merge_var with | Regval_Minterrupts (v) => Some (v) | g__9 => None end. + +Definition regval_of_Minterrupts (v : Minterrupts) : register_value := Regval_Minterrupts (v). + +Definition Misa_of_regval (merge_var : register_value) +: option Misa := + + match merge_var with | Regval_Misa (v) => Some (v) | g__8 => None end. + +Definition regval_of_Misa (v : Misa) : register_value := Regval_Misa (v). + +Definition Mstatus_of_regval (merge_var : register_value) +: option Mstatus := + + match merge_var with | Regval_Mstatus (v) => Some (v) | g__7 => None end. + +Definition regval_of_Mstatus (v : Mstatus) : register_value := Regval_Mstatus (v). + +Definition Mtvec_of_regval (merge_var : register_value) +: option Mtvec := + + match merge_var with | Regval_Mtvec (v) => Some (v) | g__6 => None end. + +Definition regval_of_Mtvec (v : Mtvec) : register_value := Regval_Mtvec (v). + +Definition Privilege_of_regval (merge_var : register_value) +: option Privilege := + + match merge_var with | Regval_Privilege (v) => Some (v) | g__5 => None end. + +Definition regval_of_Privilege (v : Privilege) : register_value := Regval_Privilege (v). + +Definition Sedeleg_of_regval (merge_var : register_value) +: option Sedeleg := + + match merge_var with | Regval_Sedeleg (v) => Some (v) | g__4 => None end. + +Definition regval_of_Sedeleg (v : Sedeleg) : register_value := Regval_Sedeleg (v). + +Definition Sinterrupts_of_regval (merge_var : register_value) +: option Sinterrupts := + + match merge_var with | Regval_Sinterrupts (v) => Some (v) | g__3 => None end. + +Definition regval_of_Sinterrupts (v : Sinterrupts) : register_value := Regval_Sinterrupts (v). + +Definition TLB39_Entry_of_regval (merge_var : register_value) +: option TLB39_Entry := + + match merge_var with | Regval_TLB39_Entry (v) => Some (v) | g__2 => None end. + +Definition regval_of_TLB39_Entry (v : TLB39_Entry) : register_value := Regval_TLB39_Entry (v). + +Definition bool_of_regval (merge_var : register_value) +: option bool := + + match merge_var with | Regval_bool (v) => Some (v) | g__1 => None end. + +Definition regval_of_bool (v : bool) : register_value := Regval_bool (v). + +Definition vector_64_dec_bit_of_regval (merge_var : register_value) +: option (mword 64) := + + match merge_var with | Regval_vector_64_dec_bit (v) => Some (v) | g__0 => None end. + +Definition regval_of_vector_64_dec_bit (v : mword 64) +: register_value := + + Regval_vector_64_dec_bit + (v). + + + +Definition vector_of_regval {a} n (of_regval : register_value -> option a) (rv : register_value) : option (vec a n) := match rv with + | Regval_vector (n', _, v) => if n =? n' then map_bind (vec_of_list n) (just_list (List.map of_regval v)) else None + | _ => None +end. + +Definition regval_of_vector {a} (regval_of : a -> register_value) (size : Z) (is_inc : bool) (xs : vec a size) : register_value := Regval_vector (size, is_inc, List.map regval_of (list_of_vec xs)). + +Definition list_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (list a) := match rv with + | Regval_list v => just_list (List.map of_regval v) + | _ => None +end. + +Definition regval_of_list {a} (regval_of : a -> register_value) (xs : list a) : register_value := Regval_list (List.map regval_of xs). + +Definition option_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (option a) := match rv with + | Regval_option v => option_map of_regval v + | _ => None +end. + +Definition regval_of_option {a} (regval_of : a -> register_value) (v : option a) := Regval_option (option_map regval_of v). + + +Definition tlb39_ref := {| + name := "tlb39"; + read_from := (fun s => s.(tlb39)); + write_to := (fun v s => ({[ s with tlb39 := v ]})); + of_regval := (fun v => option_of_regval (fun v => TLB39_Entry_of_regval v) v); + regval_of := (fun v => regval_of_option (fun v => regval_of_TLB39_Entry v) v) |}. + +Definition htif_exit_code_ref := {| + name := "htif_exit_code"; + read_from := (fun s => s.(htif_exit_code)); + write_to := (fun v s => ({[ s with htif_exit_code := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition htif_done_ref := {| + name := "htif_done"; + read_from := (fun s => s.(htif_done)); + write_to := (fun v s => ({[ s with htif_done := v ]})); + of_regval := (fun v => bool_of_regval v); + regval_of := (fun v => regval_of_bool v) |}. + +Definition htif_tohost_ref := {| + name := "htif_tohost"; + read_from := (fun s => s.(htif_tohost)); + write_to := (fun v s => ({[ s with htif_tohost := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition mtimecmp_ref := {| + name := "mtimecmp"; + read_from := (fun s => s.(mtimecmp)); + write_to := (fun v s => ({[ s with mtimecmp := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition tselect_ref := {| + name := "tselect"; + read_from := (fun s => s.(tselect)); + write_to := (fun v s => ({[ s with tselect := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition stval_ref := {| + name := "stval"; + read_from := (fun s => s.(stval)); + write_to := (fun v s => ({[ s with stval := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition scause_ref := {| + name := "scause"; + read_from := (fun s => s.(scause)); + write_to := (fun v s => ({[ s with scause := v ]})); + of_regval := (fun v => Mcause_of_regval v); + regval_of := (fun v => regval_of_Mcause v) |}. + +Definition sepc_ref := {| + name := "sepc"; + read_from := (fun s => s.(sepc)); + write_to := (fun v s => ({[ s with sepc := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition sscratch_ref := {| + name := "sscratch"; + read_from := (fun s => s.(sscratch)); + write_to := (fun v s => ({[ s with sscratch := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition stvec_ref := {| + name := "stvec"; + read_from := (fun s => s.(stvec)); + write_to := (fun v s => ({[ s with stvec := v ]})); + of_regval := (fun v => Mtvec_of_regval v); + regval_of := (fun v => regval_of_Mtvec v) |}. + +Definition satp_ref := {| + name := "satp"; + read_from := (fun s => s.(satp)); + write_to := (fun v s => ({[ s with satp := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition sideleg_ref := {| + name := "sideleg"; + read_from := (fun s => s.(sideleg)); + write_to := (fun v s => ({[ s with sideleg := v ]})); + of_regval := (fun v => Sinterrupts_of_regval v); + regval_of := (fun v => regval_of_Sinterrupts v) |}. + +Definition sedeleg_ref := {| + name := "sedeleg"; + read_from := (fun s => s.(sedeleg)); + write_to := (fun v s => ({[ s with sedeleg := v ]})); + of_regval := (fun v => Sedeleg_of_regval v); + regval_of := (fun v => regval_of_Sedeleg v) |}. + +Definition pmpcfg0_ref := {| + name := "pmpcfg0"; + read_from := (fun s => s.(pmpcfg0)); + write_to := (fun v s => ({[ s with pmpcfg0 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition pmpaddr0_ref := {| + name := "pmpaddr0"; + read_from := (fun s => s.(pmpaddr0)); + write_to := (fun v s => ({[ s with pmpaddr0 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition mhartid_ref := {| + name := "mhartid"; + read_from := (fun s => s.(mhartid)); + write_to := (fun v s => ({[ s with mhartid := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition marchid_ref := {| + name := "marchid"; + read_from := (fun s => s.(marchid)); + write_to := (fun v s => ({[ s with marchid := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition mimpid_ref := {| + name := "mimpid"; + read_from := (fun s => s.(mimpid)); + write_to := (fun v s => ({[ s with mimpid := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition mvendorid_ref := {| + name := "mvendorid"; + read_from := (fun s => s.(mvendorid)); + write_to := (fun v s => ({[ s with mvendorid := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition minstret_written_ref := {| + name := "minstret_written"; + read_from := (fun s => s.(minstret_written)); + write_to := (fun v s => ({[ s with minstret_written := v ]})); + of_regval := (fun v => bool_of_regval v); + regval_of := (fun v => regval_of_bool v) |}. + +Definition minstret_ref := {| + name := "minstret"; + read_from := (fun s => s.(minstret)); + write_to := (fun v s => ({[ s with minstret := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition mtime_ref := {| + name := "mtime"; + read_from := (fun s => s.(mtime)); + write_to := (fun v s => ({[ s with mtime := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition mcycle_ref := {| + name := "mcycle"; + read_from := (fun s => s.(mcycle)); + write_to := (fun v s => ({[ s with mcycle := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition scounteren_ref := {| + name := "scounteren"; + read_from := (fun s => s.(scounteren)); + write_to := (fun v s => ({[ s with scounteren := v ]})); + of_regval := (fun v => Counteren_of_regval v); + regval_of := (fun v => regval_of_Counteren v) |}. + +Definition mcounteren_ref := {| + name := "mcounteren"; + read_from := (fun s => s.(mcounteren)); + write_to := (fun v s => ({[ s with mcounteren := v ]})); + of_regval := (fun v => Counteren_of_regval v); + regval_of := (fun v => regval_of_Counteren v) |}. + +Definition mscratch_ref := {| + name := "mscratch"; + read_from := (fun s => s.(mscratch)); + write_to := (fun v s => ({[ s with mscratch := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition mtval_ref := {| + name := "mtval"; + read_from := (fun s => s.(mtval)); + write_to := (fun v s => ({[ s with mtval := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition mepc_ref := {| + name := "mepc"; + read_from := (fun s => s.(mepc)); + write_to := (fun v s => ({[ s with mepc := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition mcause_ref := {| + name := "mcause"; + read_from := (fun s => s.(mcause)); + write_to := (fun v s => ({[ s with mcause := v ]})); + of_regval := (fun v => Mcause_of_regval v); + regval_of := (fun v => regval_of_Mcause v) |}. + +Definition mtvec_ref := {| + name := "mtvec"; + read_from := (fun s => s.(mtvec)); + write_to := (fun v s => ({[ s with mtvec := v ]})); + of_regval := (fun v => Mtvec_of_regval v); + regval_of := (fun v => regval_of_Mtvec v) |}. + +Definition medeleg_ref := {| + name := "medeleg"; + read_from := (fun s => s.(medeleg)); + write_to := (fun v s => ({[ s with medeleg := v ]})); + of_regval := (fun v => Medeleg_of_regval v); + regval_of := (fun v => regval_of_Medeleg v) |}. + +Definition mideleg_ref := {| + name := "mideleg"; + read_from := (fun s => s.(mideleg)); + write_to := (fun v s => ({[ s with mideleg := v ]})); + of_regval := (fun v => Minterrupts_of_regval v); + regval_of := (fun v => regval_of_Minterrupts v) |}. + +Definition mie_ref := {| + name := "mie"; + read_from := (fun s => s.(mie)); + write_to := (fun v s => ({[ s with mie := v ]})); + of_regval := (fun v => Minterrupts_of_regval v); + regval_of := (fun v => regval_of_Minterrupts v) |}. + +Definition mip_ref := {| + name := "mip"; + read_from := (fun s => s.(mip)); + write_to := (fun v s => ({[ s with mip := v ]})); + of_regval := (fun v => Minterrupts_of_regval v); + regval_of := (fun v => regval_of_Minterrupts v) |}. + +Definition mstatus_ref := {| + name := "mstatus"; + read_from := (fun s => s.(mstatus)); + write_to := (fun v s => ({[ s with mstatus := v ]})); + of_regval := (fun v => Mstatus_of_regval v); + regval_of := (fun v => regval_of_Mstatus v) |}. + +Definition misa_ref := {| + name := "misa"; + read_from := (fun s => s.(misa)); + write_to := (fun v s => ({[ s with misa := v ]})); + of_regval := (fun v => Misa_of_regval v); + regval_of := (fun v => regval_of_Misa v) |}. + +Definition cur_inst_ref := {| + name := "cur_inst"; + read_from := (fun s => s.(cur_inst)); + write_to := (fun v s => ({[ s with cur_inst := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition cur_privilege_ref := {| + name := "cur_privilege"; + read_from := (fun s => s.(cur_privilege)); + write_to := (fun v s => ({[ s with cur_privilege := v ]})); + of_regval := (fun v => Privilege_of_regval v); + regval_of := (fun v => regval_of_Privilege v) |}. + +Definition x31_ref := {| + name := "x31"; + read_from := (fun s => s.(x31)); + write_to := (fun v s => ({[ s with x31 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x30_ref := {| + name := "x30"; + read_from := (fun s => s.(x30)); + write_to := (fun v s => ({[ s with x30 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x29_ref := {| + name := "x29"; + read_from := (fun s => s.(x29)); + write_to := (fun v s => ({[ s with x29 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x28_ref := {| + name := "x28"; + read_from := (fun s => s.(x28)); + write_to := (fun v s => ({[ s with x28 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x27_ref := {| + name := "x27"; + read_from := (fun s => s.(x27)); + write_to := (fun v s => ({[ s with x27 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x26_ref := {| + name := "x26"; + read_from := (fun s => s.(x26)); + write_to := (fun v s => ({[ s with x26 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x25_ref := {| + name := "x25"; + read_from := (fun s => s.(x25)); + write_to := (fun v s => ({[ s with x25 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x24_ref := {| + name := "x24"; + read_from := (fun s => s.(x24)); + write_to := (fun v s => ({[ s with x24 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x23_ref := {| + name := "x23"; + read_from := (fun s => s.(x23)); + write_to := (fun v s => ({[ s with x23 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x22_ref := {| + name := "x22"; + read_from := (fun s => s.(x22)); + write_to := (fun v s => ({[ s with x22 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x21_ref := {| + name := "x21"; + read_from := (fun s => s.(x21)); + write_to := (fun v s => ({[ s with x21 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x20_ref := {| + name := "x20"; + read_from := (fun s => s.(x20)); + write_to := (fun v s => ({[ s with x20 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x19_ref := {| + name := "x19"; + read_from := (fun s => s.(x19)); + write_to := (fun v s => ({[ s with x19 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x18_ref := {| + name := "x18"; + read_from := (fun s => s.(x18)); + write_to := (fun v s => ({[ s with x18 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x17_ref := {| + name := "x17"; + read_from := (fun s => s.(x17)); + write_to := (fun v s => ({[ s with x17 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x16_ref := {| + name := "x16"; + read_from := (fun s => s.(x16)); + write_to := (fun v s => ({[ s with x16 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x15_ref := {| + name := "x15"; + read_from := (fun s => s.(x15)); + write_to := (fun v s => ({[ s with x15 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x14_ref := {| + name := "x14"; + read_from := (fun s => s.(x14)); + write_to := (fun v s => ({[ s with x14 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x13_ref := {| + name := "x13"; + read_from := (fun s => s.(x13)); + write_to := (fun v s => ({[ s with x13 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x12_ref := {| + name := "x12"; + read_from := (fun s => s.(x12)); + write_to := (fun v s => ({[ s with x12 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x11_ref := {| + name := "x11"; + read_from := (fun s => s.(x11)); + write_to := (fun v s => ({[ s with x11 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x10_ref := {| + name := "x10"; + read_from := (fun s => s.(x10)); + write_to := (fun v s => ({[ s with x10 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x9_ref := {| + name := "x9"; + read_from := (fun s => s.(x9)); + write_to := (fun v s => ({[ s with x9 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x8_ref := {| + name := "x8"; + read_from := (fun s => s.(x8)); + write_to := (fun v s => ({[ s with x8 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x7_ref := {| + name := "x7"; + read_from := (fun s => s.(x7)); + write_to := (fun v s => ({[ s with x7 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x6_ref := {| + name := "x6"; + read_from := (fun s => s.(x6)); + write_to := (fun v s => ({[ s with x6 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x5_ref := {| + name := "x5"; + read_from := (fun s => s.(x5)); + write_to := (fun v s => ({[ s with x5 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x4_ref := {| + name := "x4"; + read_from := (fun s => s.(x4)); + write_to := (fun v s => ({[ s with x4 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x3_ref := {| + name := "x3"; + read_from := (fun s => s.(x3)); + write_to := (fun v s => ({[ s with x3 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x2_ref := {| + name := "x2"; + read_from := (fun s => s.(x2)); + write_to := (fun v s => ({[ s with x2 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x1_ref := {| + name := "x1"; + read_from := (fun s => s.(x1)); + write_to := (fun v s => ({[ s with x1 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition Xs_ref := {| + name := "Xs"; + read_from := (fun s => s.(Xs)); + write_to := (fun v s => ({[ s with Xs := v ]})); + of_regval := (fun v => vector_of_regval 32 (fun v => vector_64_dec_bit_of_regval v) v); + regval_of := (fun v => regval_of_vector (fun v => regval_of_vector_64_dec_bit v) 32 false v) |}. + +Definition instbits_ref := {| + name := "instbits"; + read_from := (fun s => s.(instbits)); + write_to := (fun v s => ({[ s with instbits := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition nextPC_ref := {| + name := "nextPC"; + read_from := (fun s => s.(nextPC)); + write_to := (fun v s => ({[ s with nextPC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition PC_ref := {| + name := "PC"; + read_from := (fun s => s.(PC)); + write_to := (fun v s => ({[ s with PC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Local Open Scope string. +Definition get_regval (reg_name : string) (s : regstate) : option register_value := + if string_dec reg_name "tlb39" then Some (tlb39_ref.(regval_of) (tlb39_ref.(read_from) s)) else + if string_dec reg_name "htif_exit_code" then Some (htif_exit_code_ref.(regval_of) (htif_exit_code_ref.(read_from) s)) else + if string_dec reg_name "htif_done" then Some (htif_done_ref.(regval_of) (htif_done_ref.(read_from) s)) else + if string_dec reg_name "htif_tohost" then Some (htif_tohost_ref.(regval_of) (htif_tohost_ref.(read_from) s)) else + if string_dec reg_name "mtimecmp" then Some (mtimecmp_ref.(regval_of) (mtimecmp_ref.(read_from) s)) else + if string_dec reg_name "tselect" then Some (tselect_ref.(regval_of) (tselect_ref.(read_from) s)) else + if string_dec reg_name "stval" then Some (stval_ref.(regval_of) (stval_ref.(read_from) s)) else + if string_dec reg_name "scause" then Some (scause_ref.(regval_of) (scause_ref.(read_from) s)) else + if string_dec reg_name "sepc" then Some (sepc_ref.(regval_of) (sepc_ref.(read_from) s)) else + if string_dec reg_name "sscratch" then Some (sscratch_ref.(regval_of) (sscratch_ref.(read_from) s)) else + if string_dec reg_name "stvec" then Some (stvec_ref.(regval_of) (stvec_ref.(read_from) s)) else + if string_dec reg_name "satp" then Some (satp_ref.(regval_of) (satp_ref.(read_from) s)) else + if string_dec reg_name "sideleg" then Some (sideleg_ref.(regval_of) (sideleg_ref.(read_from) s)) else + if string_dec reg_name "sedeleg" then Some (sedeleg_ref.(regval_of) (sedeleg_ref.(read_from) s)) else + if string_dec reg_name "pmpcfg0" then Some (pmpcfg0_ref.(regval_of) (pmpcfg0_ref.(read_from) s)) else + if string_dec reg_name "pmpaddr0" then Some (pmpaddr0_ref.(regval_of) (pmpaddr0_ref.(read_from) s)) else + if string_dec reg_name "mhartid" then Some (mhartid_ref.(regval_of) (mhartid_ref.(read_from) s)) else + if string_dec reg_name "marchid" then Some (marchid_ref.(regval_of) (marchid_ref.(read_from) s)) else + if string_dec reg_name "mimpid" then Some (mimpid_ref.(regval_of) (mimpid_ref.(read_from) s)) else + if string_dec reg_name "mvendorid" then Some (mvendorid_ref.(regval_of) (mvendorid_ref.(read_from) s)) else + if string_dec reg_name "minstret_written" then Some (minstret_written_ref.(regval_of) (minstret_written_ref.(read_from) s)) else + if string_dec reg_name "minstret" then Some (minstret_ref.(regval_of) (minstret_ref.(read_from) s)) else + if string_dec reg_name "mtime" then Some (mtime_ref.(regval_of) (mtime_ref.(read_from) s)) else + if string_dec reg_name "mcycle" then Some (mcycle_ref.(regval_of) (mcycle_ref.(read_from) s)) else + if string_dec reg_name "scounteren" then Some (scounteren_ref.(regval_of) (scounteren_ref.(read_from) s)) else + if string_dec reg_name "mcounteren" then Some (mcounteren_ref.(regval_of) (mcounteren_ref.(read_from) s)) else + if string_dec reg_name "mscratch" then Some (mscratch_ref.(regval_of) (mscratch_ref.(read_from) s)) else + if string_dec reg_name "mtval" then Some (mtval_ref.(regval_of) (mtval_ref.(read_from) s)) else + if string_dec reg_name "mepc" then Some (mepc_ref.(regval_of) (mepc_ref.(read_from) s)) else + if string_dec reg_name "mcause" then Some (mcause_ref.(regval_of) (mcause_ref.(read_from) s)) else + if string_dec reg_name "mtvec" then Some (mtvec_ref.(regval_of) (mtvec_ref.(read_from) s)) else + if string_dec reg_name "medeleg" then Some (medeleg_ref.(regval_of) (medeleg_ref.(read_from) s)) else + if string_dec reg_name "mideleg" then Some (mideleg_ref.(regval_of) (mideleg_ref.(read_from) s)) else + if string_dec reg_name "mie" then Some (mie_ref.(regval_of) (mie_ref.(read_from) s)) else + if string_dec reg_name "mip" then Some (mip_ref.(regval_of) (mip_ref.(read_from) s)) else + if string_dec reg_name "mstatus" then Some (mstatus_ref.(regval_of) (mstatus_ref.(read_from) s)) else + if string_dec reg_name "misa" then Some (misa_ref.(regval_of) (misa_ref.(read_from) s)) else + if string_dec reg_name "cur_inst" then Some (cur_inst_ref.(regval_of) (cur_inst_ref.(read_from) s)) else + if string_dec reg_name "cur_privilege" then Some (cur_privilege_ref.(regval_of) (cur_privilege_ref.(read_from) s)) else + if string_dec reg_name "x31" then Some (x31_ref.(regval_of) (x31_ref.(read_from) s)) else + if string_dec reg_name "x30" then Some (x30_ref.(regval_of) (x30_ref.(read_from) s)) else + if string_dec reg_name "x29" then Some (x29_ref.(regval_of) (x29_ref.(read_from) s)) else + if string_dec reg_name "x28" then Some (x28_ref.(regval_of) (x28_ref.(read_from) s)) else + if string_dec reg_name "x27" then Some (x27_ref.(regval_of) (x27_ref.(read_from) s)) else + if string_dec reg_name "x26" then Some (x26_ref.(regval_of) (x26_ref.(read_from) s)) else + if string_dec reg_name "x25" then Some (x25_ref.(regval_of) (x25_ref.(read_from) s)) else + if string_dec reg_name "x24" then Some (x24_ref.(regval_of) (x24_ref.(read_from) s)) else + if string_dec reg_name "x23" then Some (x23_ref.(regval_of) (x23_ref.(read_from) s)) else + if string_dec reg_name "x22" then Some (x22_ref.(regval_of) (x22_ref.(read_from) s)) else + if string_dec reg_name "x21" then Some (x21_ref.(regval_of) (x21_ref.(read_from) s)) else + if string_dec reg_name "x20" then Some (x20_ref.(regval_of) (x20_ref.(read_from) s)) else + if string_dec reg_name "x19" then Some (x19_ref.(regval_of) (x19_ref.(read_from) s)) else + if string_dec reg_name "x18" then Some (x18_ref.(regval_of) (x18_ref.(read_from) s)) else + if string_dec reg_name "x17" then Some (x17_ref.(regval_of) (x17_ref.(read_from) s)) else + if string_dec reg_name "x16" then Some (x16_ref.(regval_of) (x16_ref.(read_from) s)) else + if string_dec reg_name "x15" then Some (x15_ref.(regval_of) (x15_ref.(read_from) s)) else + if string_dec reg_name "x14" then Some (x14_ref.(regval_of) (x14_ref.(read_from) s)) else + if string_dec reg_name "x13" then Some (x13_ref.(regval_of) (x13_ref.(read_from) s)) else + if string_dec reg_name "x12" then Some (x12_ref.(regval_of) (x12_ref.(read_from) s)) else + if string_dec reg_name "x11" then Some (x11_ref.(regval_of) (x11_ref.(read_from) s)) else + if string_dec reg_name "x10" then Some (x10_ref.(regval_of) (x10_ref.(read_from) s)) else + if string_dec reg_name "x9" then Some (x9_ref.(regval_of) (x9_ref.(read_from) s)) else + if string_dec reg_name "x8" then Some (x8_ref.(regval_of) (x8_ref.(read_from) s)) else + if string_dec reg_name "x7" then Some (x7_ref.(regval_of) (x7_ref.(read_from) s)) else + if string_dec reg_name "x6" then Some (x6_ref.(regval_of) (x6_ref.(read_from) s)) else + if string_dec reg_name "x5" then Some (x5_ref.(regval_of) (x5_ref.(read_from) s)) else + if string_dec reg_name "x4" then Some (x4_ref.(regval_of) (x4_ref.(read_from) s)) else + if string_dec reg_name "x3" then Some (x3_ref.(regval_of) (x3_ref.(read_from) s)) else + if string_dec reg_name "x2" then Some (x2_ref.(regval_of) (x2_ref.(read_from) s)) else + if string_dec reg_name "x1" then Some (x1_ref.(regval_of) (x1_ref.(read_from) s)) else + if string_dec reg_name "Xs" then Some (Xs_ref.(regval_of) (Xs_ref.(read_from) s)) else + if string_dec reg_name "instbits" then Some (instbits_ref.(regval_of) (instbits_ref.(read_from) s)) else + if string_dec reg_name "nextPC" then Some (nextPC_ref.(regval_of) (nextPC_ref.(read_from) s)) else + if string_dec reg_name "PC" then Some (PC_ref.(regval_of) (PC_ref.(read_from) s)) else + None. + +Definition set_regval (reg_name : string) (v : register_value) (s : regstate) : option regstate := + if string_dec reg_name "tlb39" then option_map (fun v => tlb39_ref.(write_to) v s) (tlb39_ref.(of_regval) v) else + if string_dec reg_name "htif_exit_code" then option_map (fun v => htif_exit_code_ref.(write_to) v s) (htif_exit_code_ref.(of_regval) v) else + if string_dec reg_name "htif_done" then option_map (fun v => htif_done_ref.(write_to) v s) (htif_done_ref.(of_regval) v) else + if string_dec reg_name "htif_tohost" then option_map (fun v => htif_tohost_ref.(write_to) v s) (htif_tohost_ref.(of_regval) v) else + if string_dec reg_name "mtimecmp" then option_map (fun v => mtimecmp_ref.(write_to) v s) (mtimecmp_ref.(of_regval) v) else + if string_dec reg_name "tselect" then option_map (fun v => tselect_ref.(write_to) v s) (tselect_ref.(of_regval) v) else + if string_dec reg_name "stval" then option_map (fun v => stval_ref.(write_to) v s) (stval_ref.(of_regval) v) else + if string_dec reg_name "scause" then option_map (fun v => scause_ref.(write_to) v s) (scause_ref.(of_regval) v) else + if string_dec reg_name "sepc" then option_map (fun v => sepc_ref.(write_to) v s) (sepc_ref.(of_regval) v) else + if string_dec reg_name "sscratch" then option_map (fun v => sscratch_ref.(write_to) v s) (sscratch_ref.(of_regval) v) else + if string_dec reg_name "stvec" then option_map (fun v => stvec_ref.(write_to) v s) (stvec_ref.(of_regval) v) else + if string_dec reg_name "satp" then option_map (fun v => satp_ref.(write_to) v s) (satp_ref.(of_regval) v) else + if string_dec reg_name "sideleg" then option_map (fun v => sideleg_ref.(write_to) v s) (sideleg_ref.(of_regval) v) else + if string_dec reg_name "sedeleg" then option_map (fun v => sedeleg_ref.(write_to) v s) (sedeleg_ref.(of_regval) v) else + if string_dec reg_name "pmpcfg0" then option_map (fun v => pmpcfg0_ref.(write_to) v s) (pmpcfg0_ref.(of_regval) v) else + if string_dec reg_name "pmpaddr0" then option_map (fun v => pmpaddr0_ref.(write_to) v s) (pmpaddr0_ref.(of_regval) v) else + if string_dec reg_name "mhartid" then option_map (fun v => mhartid_ref.(write_to) v s) (mhartid_ref.(of_regval) v) else + if string_dec reg_name "marchid" then option_map (fun v => marchid_ref.(write_to) v s) (marchid_ref.(of_regval) v) else + if string_dec reg_name "mimpid" then option_map (fun v => mimpid_ref.(write_to) v s) (mimpid_ref.(of_regval) v) else + if string_dec reg_name "mvendorid" then option_map (fun v => mvendorid_ref.(write_to) v s) (mvendorid_ref.(of_regval) v) else + if string_dec reg_name "minstret_written" then option_map (fun v => minstret_written_ref.(write_to) v s) (minstret_written_ref.(of_regval) v) else + if string_dec reg_name "minstret" then option_map (fun v => minstret_ref.(write_to) v s) (minstret_ref.(of_regval) v) else + if string_dec reg_name "mtime" then option_map (fun v => mtime_ref.(write_to) v s) (mtime_ref.(of_regval) v) else + if string_dec reg_name "mcycle" then option_map (fun v => mcycle_ref.(write_to) v s) (mcycle_ref.(of_regval) v) else + if string_dec reg_name "scounteren" then option_map (fun v => scounteren_ref.(write_to) v s) (scounteren_ref.(of_regval) v) else + if string_dec reg_name "mcounteren" then option_map (fun v => mcounteren_ref.(write_to) v s) (mcounteren_ref.(of_regval) v) else + if string_dec reg_name "mscratch" then option_map (fun v => mscratch_ref.(write_to) v s) (mscratch_ref.(of_regval) v) else + if string_dec reg_name "mtval" then option_map (fun v => mtval_ref.(write_to) v s) (mtval_ref.(of_regval) v) else + if string_dec reg_name "mepc" then option_map (fun v => mepc_ref.(write_to) v s) (mepc_ref.(of_regval) v) else + if string_dec reg_name "mcause" then option_map (fun v => mcause_ref.(write_to) v s) (mcause_ref.(of_regval) v) else + if string_dec reg_name "mtvec" then option_map (fun v => mtvec_ref.(write_to) v s) (mtvec_ref.(of_regval) v) else + if string_dec reg_name "medeleg" then option_map (fun v => medeleg_ref.(write_to) v s) (medeleg_ref.(of_regval) v) else + if string_dec reg_name "mideleg" then option_map (fun v => mideleg_ref.(write_to) v s) (mideleg_ref.(of_regval) v) else + if string_dec reg_name "mie" then option_map (fun v => mie_ref.(write_to) v s) (mie_ref.(of_regval) v) else + if string_dec reg_name "mip" then option_map (fun v => mip_ref.(write_to) v s) (mip_ref.(of_regval) v) else + if string_dec reg_name "mstatus" then option_map (fun v => mstatus_ref.(write_to) v s) (mstatus_ref.(of_regval) v) else + if string_dec reg_name "misa" then option_map (fun v => misa_ref.(write_to) v s) (misa_ref.(of_regval) v) else + if string_dec reg_name "cur_inst" then option_map (fun v => cur_inst_ref.(write_to) v s) (cur_inst_ref.(of_regval) v) else + if string_dec reg_name "cur_privilege" then option_map (fun v => cur_privilege_ref.(write_to) v s) (cur_privilege_ref.(of_regval) v) else + if string_dec reg_name "x31" then option_map (fun v => x31_ref.(write_to) v s) (x31_ref.(of_regval) v) else + if string_dec reg_name "x30" then option_map (fun v => x30_ref.(write_to) v s) (x30_ref.(of_regval) v) else + if string_dec reg_name "x29" then option_map (fun v => x29_ref.(write_to) v s) (x29_ref.(of_regval) v) else + if string_dec reg_name "x28" then option_map (fun v => x28_ref.(write_to) v s) (x28_ref.(of_regval) v) else + if string_dec reg_name "x27" then option_map (fun v => x27_ref.(write_to) v s) (x27_ref.(of_regval) v) else + if string_dec reg_name "x26" then option_map (fun v => x26_ref.(write_to) v s) (x26_ref.(of_regval) v) else + if string_dec reg_name "x25" then option_map (fun v => x25_ref.(write_to) v s) (x25_ref.(of_regval) v) else + if string_dec reg_name "x24" then option_map (fun v => x24_ref.(write_to) v s) (x24_ref.(of_regval) v) else + if string_dec reg_name "x23" then option_map (fun v => x23_ref.(write_to) v s) (x23_ref.(of_regval) v) else + if string_dec reg_name "x22" then option_map (fun v => x22_ref.(write_to) v s) (x22_ref.(of_regval) v) else + if string_dec reg_name "x21" then option_map (fun v => x21_ref.(write_to) v s) (x21_ref.(of_regval) v) else + if string_dec reg_name "x20" then option_map (fun v => x20_ref.(write_to) v s) (x20_ref.(of_regval) v) else + if string_dec reg_name "x19" then option_map (fun v => x19_ref.(write_to) v s) (x19_ref.(of_regval) v) else + if string_dec reg_name "x18" then option_map (fun v => x18_ref.(write_to) v s) (x18_ref.(of_regval) v) else + if string_dec reg_name "x17" then option_map (fun v => x17_ref.(write_to) v s) (x17_ref.(of_regval) v) else + if string_dec reg_name "x16" then option_map (fun v => x16_ref.(write_to) v s) (x16_ref.(of_regval) v) else + if string_dec reg_name "x15" then option_map (fun v => x15_ref.(write_to) v s) (x15_ref.(of_regval) v) else + if string_dec reg_name "x14" then option_map (fun v => x14_ref.(write_to) v s) (x14_ref.(of_regval) v) else + if string_dec reg_name "x13" then option_map (fun v => x13_ref.(write_to) v s) (x13_ref.(of_regval) v) else + if string_dec reg_name "x12" then option_map (fun v => x12_ref.(write_to) v s) (x12_ref.(of_regval) v) else + if string_dec reg_name "x11" then option_map (fun v => x11_ref.(write_to) v s) (x11_ref.(of_regval) v) else + if string_dec reg_name "x10" then option_map (fun v => x10_ref.(write_to) v s) (x10_ref.(of_regval) v) else + if string_dec reg_name "x9" then option_map (fun v => x9_ref.(write_to) v s) (x9_ref.(of_regval) v) else + if string_dec reg_name "x8" then option_map (fun v => x8_ref.(write_to) v s) (x8_ref.(of_regval) v) else + if string_dec reg_name "x7" then option_map (fun v => x7_ref.(write_to) v s) (x7_ref.(of_regval) v) else + if string_dec reg_name "x6" then option_map (fun v => x6_ref.(write_to) v s) (x6_ref.(of_regval) v) else + if string_dec reg_name "x5" then option_map (fun v => x5_ref.(write_to) v s) (x5_ref.(of_regval) v) else + if string_dec reg_name "x4" then option_map (fun v => x4_ref.(write_to) v s) (x4_ref.(of_regval) v) else + if string_dec reg_name "x3" then option_map (fun v => x3_ref.(write_to) v s) (x3_ref.(of_regval) v) else + if string_dec reg_name "x2" then option_map (fun v => x2_ref.(write_to) v s) (x2_ref.(of_regval) v) else + if string_dec reg_name "x1" then option_map (fun v => x1_ref.(write_to) v s) (x1_ref.(of_regval) v) else + if string_dec reg_name "Xs" then option_map (fun v => Xs_ref.(write_to) v s) (Xs_ref.(of_regval) v) else + if string_dec reg_name "instbits" then option_map (fun v => instbits_ref.(write_to) v s) (instbits_ref.(of_regval) v) else + if string_dec reg_name "nextPC" then option_map (fun v => nextPC_ref.(write_to) v s) (nextPC_ref.(of_regval) v) else + if string_dec reg_name "PC" then option_map (fun v => PC_ref.(write_to) v s) (PC_ref.(of_regval) v) else + None. + +Definition register_accessors := (get_regval, set_regval). + + +Definition MR a r := monadR register_value a r exception. +Definition M a := monad register_value a exception. -- cgit v1.2.3 From af5e6e4d11d9df0bd2058ef3cc5b69d877c001ef Mon Sep 17 00:00:00 2001 From: Peter Sewell Date: Sun, 13 Jan 2019 09:19:35 +0000 Subject: update README with current model repos --- README.md | 49 ++++++++++++++++++++++++++++++++----------------- 1 file changed, 32 insertions(+), 17 deletions(-) diff --git a/README.md b/README.md index f1d9aeed..8917de6a 100644 --- a/README.md +++ b/README.md @@ -4,13 +4,14 @@ The Sail ISA specification language Overview ======== -Sail is a language for describing the instruction semantics of -processors. Sail aims to provide a engineer-friendly, -vendor-pseudocode-like language for describing instruction -semantics. It is an imperative language containing some advanced -features like dependent typing for numeric types and bitvector -lengths, which are automatically checked using Z3. It has been used -for several papers, available from http://www.cl.cam.ac.uk/~pes20/sail/ +Sail is a language for describing the instruction-set architecture +(ISA) semantics of processors. Sail aims to provide a +engineer-friendly, vendor-pseudocode-like language for describing +instruction semantics. It is essentially a first-order imperative +language, but with lightweight dependent typing for numeric types and +bitvector lengths, which are automatically checked using Z3. It has +been used for several papers, available from +. This repository contains the implementation of Sail, together with some Sail specifications and related tools. @@ -19,10 +20,7 @@ some Sail specifications and related tools. * The Sail source code (in [src/](src/)) -* A Sail specification of ARMv8.3-A generated from ARM's publically - released ASL specification (in [aarch64/](aarch64/)) - -* Generated Isabelle snapshots of the above ISAs in [snapshots/isabelle](snapshots/isabelle) +* Generated Isabelle snapshots of some ISA models, in [snapshots/isabelle](snapshots/isabelle) * Documentation for generating Isabelle and working with the ISA specs in Isabelle in [snapshots/isabelle/Manual.pdf](snapshots/isabelle/Manual.pdf) @@ -31,13 +29,28 @@ some Sail specifications and related tools. * A test suite for Sail (in [test/](test/)) -We also have versions of IBM POWER, a fragment of x86, and a -hand-written fragment of ARMv8-A, but these are currently not up-to-date -with the latest version of Sail, which is the (default) sail2 branch -on Github. +Sail ISA Models +=============== + +Sail is currently being used for ARM, RISC-V, MIPS, CHERI-MIPS, IBM Power, and x86 models, variously ranging from full definitions to core user-mode fragments, and either here or in separate repositories: + +* [Sail ARMv8.5-A ISA model, automatically generated from the ARM-internal ASL reference, as used in the ARM ARM](https://github.com/rems-project/sail-arm). + +* [Sail ARMv8.3-A ISA model](https://github.com/rems-project/sail/tree/sail2/arm). This is the "public" model described in our [POPL 2019 paper](http://www.cl.cam.ac.uk/users/pes20/sail/sail-popl2019.pdf), now largely superseded by the above. + +* [Sail ARMv8-A ISA model, handwritten](https://github.com/rems-project/sail/tree/sail2/arm). This is a handwritten user-mode fragment. -The mips and cheri-mips specifications that used to be here have moved to -https://github.com/CTSRD-CHERI/sail-cheri-mips . +* [Sail RISC-V ISA model, handwritten](https://github.com/rems-project/sail-riscv). + +* [Sail MIPS and CHERI-MIPS ISA models, handwritten](https://github.com/CTSRD-CHERI/sail-cheri-mips). + +* [Sail IBM POWER ISA model, automatically generated from IBM XML documentation](https://github.com/rems-project/sail/tree/sail2/power). This is a user-mode fragment. + +* [Sail x86 ISA model, handwritten](https://github.com/rems-project/sail/tree/sail2/x86). This is a handwritten user-mode fragment. + +The hand-written ARMv8-A, IBM POWER, and x86 models are currently not in sync +with the latest version of Sail, which is the (default) sail2 branch +on Github. These and the RISC-V model are integrated with our [RMEM](http://www.cl.cam.ac.uk/users/pes20/rmem) tool for concurrency semantics. OPAM Installation ================= @@ -81,3 +94,5 @@ the headers of those files. The POWER model in power/ is distributed under the 2-clause BSD licence in the headers of those files. + +The models in separate repositories are licensed as described in each. \ No newline at end of file -- cgit v1.2.3 From a3da2efb3ef08e132e16db0c510b1b8fe4ee600c Mon Sep 17 00:00:00 2001 From: Peter Sewell Date: Sun, 13 Jan 2019 09:45:59 +0000 Subject: update README --- README.md | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/README.md b/README.md index 8917de6a..f3c877a4 100644 --- a/README.md +++ b/README.md @@ -12,6 +12,20 @@ language, but with lightweight dependent typing for numeric types and bitvector lengths, which are automatically checked using Z3. It has been used for several papers, available from . +

+ +Given a Sail definition, the tool will type-check it and generate +executable emulators, in C and OCaml, theorem-prover definitions for +Isabelle, HOL4, and Coq, and definitions to integrate with our +RMEM tool for +concurrency semantics. This is all work in progress, and some +theorem-prover definitions do not yet work for the more complex +models; see the most recent papers and the ARMv8.5-A model for +descriptions of the current state. +

+ + +

This repository contains the implementation of Sail, together with some Sail specifications and related tools. -- cgit v1.2.3