From 2bf408e37eabfa0dfb7cee5165a4208de5846b9e Mon Sep 17 00:00:00 2001
From: Prashanth Mundkur
Date: Wed, 18 Apr 2018 15:01:43 -0700
Subject: Fix mideleg semantics after spec clarification from Andrew Waterman.

---
 riscv/riscv_sys.sail | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail
index dfed02c4..37c487cf 100644
--- a/riscv/riscv_sys.sail
+++ b/riscv/riscv_sys.sail
@@ -152,7 +152,13 @@ function legalize_mie(o : Minterrupts, v : xlenbits) -> Minterrupts = {
 }
 
 function legalize_mideleg(o : Minterrupts, v : xlenbits) -> Minterrupts = {
-  Mk_Minterrupts(v)
+  /* M-mode interrupt delegation bits "should" be hardwired to 0. */
+  /* FIXME: needs verification against eventual spec language. */
+  let m = Mk_Minterrupts(v);
+  let m = update_MEI(m, false);
+  let m = update_MTI(m, false);
+  let m = update_MSI(m, false);
+  m
 }
 
 /* exception registers */
@@ -325,9 +331,9 @@ bitfield Sinterrupts : bits(64) = {
 function lower_mip(m : Minterrupts, d : Minterrupts) -> Sinterrupts = {
   let s : Sinterrupts = Mk_Sinterrupts(EXTZ(0b0));
   /* M-mode interrupts delegated to S-mode should appear as S-mode interrupts */
-  let s = update_SEI(s, (m.SEI() & d.SEI()) | (m.MEI() & d.MEI()));
-  let s = update_STI(s, (m.STI() & d.STI()) | (m.MTI() & d.MTI()));
-  let s = update_SSI(s, (m.SSI() & d.SSI()) | (m.MSI() & d.MSI()));
+  let s = update_SEI(s, m.SEI() & d.SEI());
+  let s = update_STI(s, m.STI() & d.STI());
+  let s = update_SSI(s, m.SSI() & d.SSI());
 
   let s = update_UEI(s, m.UEI() & d.UEI());
   let s = update_UTI(s, m.UTI() & d.UTI());
-- 
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