From 252460bc33fc26d8ef8aa905592fd4029d97d419 Mon Sep 17 00:00:00 2001
From: Robert Norton
Date: Wed, 4 Apr 2018 17:06:03 +0100
Subject: Fix another infinite loop in cast bit_to_bool. Following introduction
 of eq_bool this was preferred over eq_bit when compiling the match on bit in
 bit_to_bool... Fix is to overload == before including flow.sail but feels a
 bit inelegant.

---
 cheri/Makefile    | 5 ++++-
 mips/Makefile     | 2 +-
 mips/prelude.sail | 6 +++++-
 3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/cheri/Makefile b/cheri/Makefile
index 69f12fda..663c8763 100644
--- a/cheri/Makefile
+++ b/cheri/Makefile
@@ -5,7 +5,7 @@ SAIL_LIB_DIR:=$(SAIL_DIR)/lib
 MIPS_SAIL_DIR:=$(SAIL_DIR)/mips
 CHERI_SAIL_DIR:=$(SAIL_DIR)/cheri
 SAIL:=$(SAIL_DIR)/sail
-SAIL_LIB_HEADERS:=$(SAIL_LIB_DIR)/flow.sail
+SAIL_LIB_HEADERS:=
 
 MIPS_PRE:=$(MIPS_SAIL_DIR)/prelude.sail $(MIPS_SAIL_DIR)/mips_prelude.sail
 MIPS_TLB:=$(MIPS_SAIL_DIR)/mips_tlb.sail
@@ -28,6 +28,9 @@ cheri: $(CHERI_SAILS) $(CHERI_MAIN)
 cheri.c: $(CHERI_SAILS) $(CHERI_MAIN)
 	$(SAIL) -memo_z3 -c $^ 1> $@
 
+latex: $(CHERI_SAILS)
+	$(SAIL) -latex $^
+
 cheri128: $(CHERI128_SAILS) $(CHERI_MAIN)
 	$(SAIL) -ocaml -o $@ $^
 
diff --git a/mips/Makefile b/mips/Makefile
index e0bc27b6..00703f62 100644
--- a/mips/Makefile
+++ b/mips/Makefile
@@ -6,7 +6,7 @@ MIPS_SAIL_DIR:=$(SAIL_DIR)/mips
 
 SAIL:=$(SAIL_DIR)/sail
 
-MIPS_PRE:=$(SAIL_LIB_DIR)/flow.sail $(MIPS_SAIL_DIR)/prelude.sail $(MIPS_SAIL_DIR)/mips_prelude.sail
+MIPS_PRE:=$(MIPS_SAIL_DIR)/prelude.sail $(MIPS_SAIL_DIR)/mips_prelude.sail
 MIPS_TLB:=$(MIPS_SAIL_DIR)/mips_tlb.sail
 MIPS_TLB_STUB:=$(MIPS_SAIL_DIR)/mips_tlb_stub.sail
 MIPS_SAILS:=$(MIPS_SAIL_DIR)/mips_wrappers.sail $(MIPS_SAIL_DIR)/mips_ast_decl.sail $(MIPS_SAIL_DIR)/mips_insts.sail $(MIPS_SAIL_DIR)/mips_ri.sail $(MIPS_SAIL_DIR)/mips_epilogue.sail
diff --git a/mips/prelude.sail b/mips/prelude.sail
index 9607e508..74ae95b2 100644
--- a/mips/prelude.sail
+++ b/mips/prelude.sail
@@ -23,7 +23,11 @@ val "reg_deref" : forall ('a : Type). register('a) -> 'a effect {rreg}
 /* sneaky deref with no effect necessary for bitfield writes */
 val _reg_deref = "reg_deref" : forall ('a : Type). register('a) -> 'a
 
-overload operator == = {eq_atom, eq_int, eq_bit, eq_vec, eq_string, eq_real, eq_anything}
+overload operator == = {eq_bit}
+
+$include <flow.sail>
+
+overload operator == = {eq_vec, eq_string, eq_real, eq_anything}
 
 val vector_subrange = {ocaml: "subrange", lem: "subrange_vec_dec"} : forall ('n : Int) ('m : Int) ('o : Int), 'o <= 'm <= 'n.
   (bits('n), atom('m), atom('o)) -> bits('m - ('o - 1))
-- 
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