From 016cb11c78f84d02b40988958098b464dffc0f26 Mon Sep 17 00:00:00 2001
From: Shaked Flur
Date: Sat, 2 Sep 2017 08:09:44 +0100
Subject: check the status of SC before doing the memory write

---
 risc-v/riscv.sail | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/risc-v/riscv.sail b/risc-v/riscv.sail
index 5b749656..cd0e5bf9 100644
--- a/risc-v/riscv.sail
+++ b/risc-v/riscv.sail
@@ -380,15 +380,17 @@ function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = {
   (*(bit)*) status := if speculate_conditional_success() then 0 else 1;
   wGPR(rd) := (bit[64]) (EXTZ([status]));
 
-  (bit[64]) addr := rGPR(rs1);
-  switch width {
-    case WORD   -> mem_write_ea(addr, 4, rl, true)
-    case DOUBLE -> mem_write_ea(addr, 8, rl, true)
-  };
-  rs2_val := rGPR(rs2);
-  switch width {
-    case WORD   -> mem_write_value(addr, 4, rs2_val[31..0], rl, true)
-    case DOUBLE -> mem_write_value(addr, 8, rs2_val,        rl, true)
+  if status == 1 then () else {
+    (bit[64]) addr := rGPR(rs1);
+    switch width {
+      case WORD   -> mem_write_ea(addr, 4, rl, true)
+      case DOUBLE -> mem_write_ea(addr, 8, rl, true)
+    };
+    rs2_val := rGPR(rs2);
+    switch width {
+      case WORD   -> mem_write_value(addr, 4, rs2_val[31..0], rl, true)
+      case DOUBLE -> mem_write_value(addr, 8, rs2_val,        rl, true)
+    };
   };
 }
 
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