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AgeCommit message (Expand)Author
2018-05-11further riscv mappingJon French
2018-05-11Work around Lem generation problem in RISC-VThomas Bauereiss
2018-05-11Merge branch 'sail2' into cheri-monoThomas Bauereiss
2018-05-11Remove buggy bit list comparison functions from Lem libraryThomas Bauereiss
2018-05-10more mappingJon French
2018-05-10RISC-V in HOL4Brian Campbell
2018-05-10load-type riscv assemblyJon French
2018-05-10rtype mapping clausesJon French
2018-05-10move common mappings to riscv_types.sailJon French
2018-05-10hacky monomorphic bits-string-parser for nowJon French
2018-05-10Merge branch 'sail2' into mappingsJon French
2018-05-10riscv/Makefile: add SAIL variable for easier debuggingJon French
2018-05-10refining spaces mappingsJon French
2018-05-10add space handling mappings to riscv prelude and sail_lib.mlJon French
2018-05-09Remove unused definitions.Prashanth Mundkur
2018-05-09remove redundant cloc targets.Robert Norton
2018-05-09Add targets for counting lines in mips, cheri and riscv. Can use either slocc...Robert Norton
2018-05-09start of riscv assembly mappingsJon French
2018-05-09add SAIL_FLAGS env var to riscv makefileJon French
2018-05-07Add a register indicating no trigger/breakpoint support, which allows the bre...Prashanth Mundkur
2018-05-07Fix another mask computation bug.Prashanth Mundkur
2018-05-07Adjust default pte update setting to match spike's default.Prashanth Mundkur
2018-05-07Log trap value on traps.Prashanth Mundkur
2018-05-07Fix a missed csr read.Prashanth Mundkur
2018-05-04Tweak the execution log.Prashanth Mundkur
2018-05-04Fix two bugs in the page-table walker, and add some comments.Prashanth Mundkur
2018-05-04Fix printing of ld.Prashanth Mundkur
2018-05-03Fix a typo in sret decode and privilege checks in xret.Prashanth Mundkur
2018-05-03Add implementation of sfence with a fixme note.Prashanth Mundkur
2018-05-03Fix a bug in privilege transition, add better transition logging.Prashanth Mundkur
2018-05-03Implement wfi, and cleanup handling illegal operations.Prashanth Mundkur
2018-05-03Fix interrupt dispatch, improve execution logs, cleanup unused bits.Prashanth Mundkur
2018-05-03Simplify the top-level execute loop using the step function.Prashanth Mundkur
2018-05-03Fix up interrupt and exception dispatch.Prashanth Mundkur
2018-05-03Implement fetch to properly handle RVC and address translation, and add a ste...Prashanth Mundkur
2018-05-03Fix duopod with latest riscv preludeAlasdair Armstrong
2018-05-03Hook in address translation for stores and atomics.Prashanth Mundkur
2018-05-03Log csr writes in the execution log.Prashanth Mundkur
2018-05-02Hook in address translation for loads.Prashanth Mundkur
2018-05-02Finish up Sv39 address translation.Prashanth Mundkur
2018-05-02Tick cycle counter in execute loop.Prashanth Mundkur
2018-05-02Fix printing of csr immediates.Prashanth Mundkur
2018-05-02Fix typo in riscv model.Prashanth Mundkur
2018-04-26Add riscv SV39 page-table walk.Prashanth Mundkur
2018-04-26Ensure riscv interrupt delegation does not reduce current privilege.Prashanth Mundkur
2018-04-26Fix bug introduced in alignment check.Prashanth Mundkur
2018-04-26Initial support for faults of writes to physical addresses.Prashanth Mundkur
2018-04-26Initial support for faults of reads to physical addresses.Prashanth Mundkur
2018-04-23Make riscv build depend on Makefile updates.Prashanth Mundkur
2018-04-23Add riscv PTE definitions and access control checks.Prashanth Mundkur
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