sail - Formal specification language for ISAs

Age	Commit message (Collapse)	Author
2018-07-11	Update the exception code for riscv LR after clarification on isa-dev.	Prashanth Mundkur

2018-07-11	RISC-V model fixes for RMEM	Jon French

2018-07-11	Fix riscv_duopod build.	Robert Norton

2018-07-10	Add an option to specify the dtc to use for the riscv platform.	Prashanth Mundkur

2018-07-10	Turn off some riscv debug tracing.	Prashanth Mundkur

2018-07-10	Start adding c-backend bits for riscv.	Prashanth Mundkur

2018-07-10	Support riscv atomic accesses to mmio regions, used by linux to access ↵	Prashanth Mundkur
	device registers.
2018-07-10	Make HOL build properly again for all of the models	Brian Campbell

2018-07-10	RISCV load-acquire in Lem (-> rmem)	Jon French

2018-07-10	correct pretty-printing using mappings	Jon French

2018-07-10	disable printing when compiling to Lem to keep rmem happy	Jon French

2018-07-09	Log some timing info at the end of riscv execution.	Prashanth Mundkur

2018-07-09	add riscv_analysis.sail to SAIL_SRCS	Jon French

2018-07-09	add LOADRES, STORECON, AMO to analysis	Jon French

2018-07-09	Support writes to misa.C in riscv.	Prashanth Mundkur

2018-07-08	Make the riscv fetch-execute loop return instead of exiting when done.	Prashanth Mundkur

2018-07-08	Move the riscv analysis function into its own file for coverage purposes.	Prashanth Mundkur

2018-07-08	Add a riscv coverage target using bisect-ppx.	Prashanth Mundkur

2018-07-07	Add reservation traces to riscv tracecmp tool.	Prashanth Mundkur

2018-07-07	Cancel riscv reservation before i/o scheduling, tweak reservation tracing.	Prashanth Mundkur

2018-07-07	An initial fix to riscv lr/sc, needs a review.	Prashanth Mundkur
	This uses a stronger model than the version in Sail-1 in order to perform address alignment checks. The reservation is kept on virtual addresses, and maintained in the platform model, but now the lr/sc definitions need calls to externs to update this state. An alternative was to reserve physical addresses, but that appeared to be more complicated without a lot more changes. Ideally, the model should be parameterizable over both options.
2018-07-07	Add some tracing to riscv address translation.	Prashanth Mundkur

2018-07-05	Fix printing of aq/rl flags in risc-v lr/sc.	Prashanth Mundkur

2018-07-05	support acquire/release loads/stores in RISCV initial_analysis	Jon French

2018-07-05	print to stdout not stderr to stop upsetting rmem regression tests	Jon French

2018-07-05	restore missing RISC-V fence types in sail2; ignore io bits in fences more ↵	Jon French
	cleanly
2018-07-03	Add htif tohost to the riscv tracecmp tool.	Prashanth Mundkur

2018-07-03	Allow the riscv htif_tohost mmio port to be readable, and ack writes to that ↵	Prashanth Mundkur
	port.
2018-06-28	further changes to support rmem	Jon French

2018-06-26	Fix duplicate riscv mem-ea, spotted by Jon French.	Prashanth Mundkur

2018-06-25	Add a riscv platform parameter to control trapping to M-mode on misaligned ↵	Prashanth Mundkur
	access, and a cli option to control it.
2018-06-25	Increment the riscv trace step counter only when instructions are executed.	Prashanth Mundkur

2018-06-25	Hook in the missed misa legalizer.	Prashanth Mundkur

2018-06-25	Fix riscv interrupt pending check to handle implicit enabling at lower ↵	Prashanth Mundkur
	privileges. Also fix timer threshold comparison to be <= instead of <.
2018-06-25	Make sstatus.UXL legalization match spike for now. Leave a fixme to make ↵	Prashanth Mundkur
	this a platform setting.
2018-06-25	Fix a missed fixme for the sstatus view of mstatus.	Prashanth Mundkur

2018-06-25	Fix tracecmp for spike's recursive calls for sie/sip/sstatus csr writes.	Prashanth Mundkur

2018-06-25	Support bitlist representation in Sail2_string	Thomas Bauereiss

2018-06-23	Add clock tick checks to the riscv tracecmp tool.	Prashanth Mundkur

2018-06-23	Fix a missing check for interrupt dispatch when riscv clint registers are ↵	Prashanth Mundkur
	written.
2018-06-22	Make riscv pte dirty-bit update handling configurable via a platform cli option.	Prashanth Mundkur
	Fix a redundant clock tick.
2018-06-22	Some more riscv trace log tweaking for spike compatibility.	Prashanth Mundkur

2018-06-22	Add cli options to riscv simulator to dump platform device-tree info.	Prashanth Mundkur

2018-06-22	Add a simple trace log comparison tool for riscv vs. a patched spike.	Prashanth Mundkur

2018-06-22	More trace log tweaks.	Prashanth Mundkur

2018-06-21	Merge branch 'sail2' of github.com:rems-project/sail into sail2	Alasdair Armstrong

2018-06-21	add PMP registers to CSR, fix build	Jon French

2018-06-21	Merge branch 'tracing' into sail2	Alasdair Armstrong

2018-06-21	changes to riscv model to support rmem	Jon French

2018-06-19	Add more detail to riscv execution trace log.	Prashanth Mundkur