sail - Formal specification language for ISAs

Age	Commit message (Expand)	Author
2018-11-30	RISC-V: update the riscv/readme to point to the new repository.	Prashanth Mundkur
2018-11-29	RISC-V: more tidying up of the Spike interface.	Prashanth Mundkur
2018-11-29	RISC-V: implement WFI in the platform model.	Prashanth Mundkur
2018-11-29	RISC-V: factor the execution trace.	Prashanth Mundkur
2018-11-29	RISC-V: no ldu for rv64i	Brian Campbell
2018-11-29	RISC-V: properly set mstatus.FS in absence of floating-point support.	Prashanth Mundkur
2018-11-29	RISC-V: minor cleanup of the spike interface.	Prashanth Mundkur
2018-11-29	RISC-V: add some missing constraints on compressed instruction encodings	Brian Campbell
2018-11-29	RISC-V: add checks for misaligned targets to jumps and branches	Brian Campbell
2018-11-29	Merge branch 'rvfi-dii' into sail2	Brian Campbell
2018-11-27	Fix memory leak in string_of_bits	Alasdair Armstrong
2018-11-21	RISC-V: allow platform ram size to be configurable.	Prashanth Mundkur
2018-11-20	Minor coq updates	Brian Campbell
2018-11-14	Add option to turn off RISC-V compressed instruction support	Brian Campbell
2018-11-14	Fix memory map in RVFI-DII mode	Brian Campbell
2018-11-12	rvfi_dii: take port number with option	Brian Campbell
2018-11-12	Add RVFI DII version of the RISC-V simulator for TestRIG	Brian Campbell
2018-11-09	RISC-V: add missed c.ebreak instruction	Prashanth Mundkur
2018-11-08	RISC-V: fix a typo-induced bug in updating the PTE.	Prashanth Mundkur
2018-11-07	RISC-V: fix assembly mappings for lr/sc.	Prashanth Mundkur
2018-11-07	Move inline forall in function definitions	Alasdair Armstrong
2018-11-07	RISC-V: add some consistency checks when run with spike.	Prashanth Mundkur
2018-10-23	RISC-V: use stderr for terminal output in OCaml backend.	Prashanth Mundkur
2018-10-23	RISC-V: separate jalr execute clause for seq model and rmem.	Prashanth Mundkur
2018-10-23	RISC-V: Initial splitting of instructions across multiple files.	Prashanth Mundkur
2018-10-23	RISC-V: Allow the C platform to get the DTB from a file, so that OS boot is p...	Prashanth Mundkur
2018-10-23	RISC-V: add cli option to dump the platform device-tree.	Prashanth Mundkur
2018-10-23	RISC-V: Add a platform knob to control mtval contents on illegal instruction ...	Prashanth Mundkur
2018-10-23	RISC-V: various fixes	Prashanth Mundkur
2018-10-23	RISC-V: fix: sstatus.SD depends on .XS and .FS.	Prashanth Mundkur
2018-10-23	RISC-V: adjust main loop for the non-spike case.	Prashanth Mundkur
2018-10-23	RISC-V: implement terminal output for C platform.	Prashanth Mundkur
2018-10-23	RISC-V: tick the clock in the C platform.	Prashanth Mundkur
2018-10-23	RISC-V: Add device tree blob into rom, currently only when linked against spike.	Prashanth Mundkur
2018-10-23	RISC-V: add default reset vector.	Prashanth Mundkur
2018-10-23	RISC-V: fix up platform bits for lr/sc.	Prashanth Mundkur
2018-10-23	RISC-V: set htif tohost port address using ELF symbol.	Prashanth Mundkur
2018-10-23	Fix typo in plat_ram_size	Alasdair Armstrong
2018-10-23	RISC-V: Add some debug logs for within_phys_mem.	Prashanth Mundkur
2018-10-23	RISC-V: Allow Spike linkage to be conditionally enabled.	Prashanth Mundkur
2018-10-23	RISC-V: flush logs at each step.	Prashanth Mundkur
2018-10-23	RISC-V: Flesh out more of the tandem checks in the C platform simulator.	Prashanth Mundkur
2018-10-23	RISC-V: An initial C Sail model linked against Spike for testing.	Prashanth Mundkur
2018-10-23	RISC-V: Refactor c platform bits.	Prashanth Mundkur
2018-10-22	Coq: use function type more carefully in untupling	Brian Campbell
2018-10-22	Update Coq patch for RISC-V, add string_take to Coq library	Brian Campbell
2018-10-16	Re-implement space-related mapping functions in Sail rather than backends	Jon French
2018-10-13	Adapt checked_mem_read to have acquire/release/reserve arguments so	Christopher Pulte
2018-10-05	RISC-V: encode/decode and assembly mappings for compressed instructions	Jon French
2018-10-01	Update Coq RISC-V patch now that the assembler is in good shape	Brian Campbell