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AgeCommit message (Expand)Author
2018-06-28further changes to support rmemJon French
2018-06-26Fix duplicate riscv mem-ea, spotted by Jon French.Prashanth Mundkur
2018-06-25Add a riscv platform parameter to control trapping to M-mode on misaligned ac...Prashanth Mundkur
2018-06-25Increment the riscv trace step counter only when instructions are executed.Prashanth Mundkur
2018-06-25Hook in the missed misa legalizer.Prashanth Mundkur
2018-06-25Fix riscv interrupt pending check to handle implicit enabling at lower privil...Prashanth Mundkur
2018-06-25Make sstatus.UXL legalization match spike for now. Leave a fixme to make this...Prashanth Mundkur
2018-06-25Fix a missed fixme for the sstatus view of mstatus.Prashanth Mundkur
2018-06-25Fix tracecmp for spike's recursive calls for sie/sip/sstatus csr writes.Prashanth Mundkur
2018-06-25Support bitlist representation in Sail2_stringThomas Bauereiss
2018-06-23Add clock tick checks to the riscv tracecmp tool.Prashanth Mundkur
2018-06-23Fix a missing check for interrupt dispatch when riscv clint registers are wri...Prashanth Mundkur
2018-06-22Make riscv pte dirty-bit update handling configurable via a platform cli option.Prashanth Mundkur
2018-06-22Some more riscv trace log tweaking for spike compatibility.Prashanth Mundkur
2018-06-22Add cli options to riscv simulator to dump platform device-tree info.Prashanth Mundkur
2018-06-22Add a simple trace log comparison tool for riscv vs. a patched spike.Prashanth Mundkur
2018-06-22More trace log tweaks.Prashanth Mundkur
2018-06-21Merge branch 'sail2' of github.com:rems-project/sail into sail2Alasdair Armstrong
2018-06-21add PMP registers to CSR, fix buildJon French
2018-06-21Merge branch 'tracing' into sail2Alasdair Armstrong
2018-06-21changes to riscv model to support rmemJon French
2018-06-19Add more detail to riscv execution trace log.Prashanth Mundkur
2018-06-15Fix riscv system register initialization.Prashanth Mundkur
2018-06-14rename all lem support files to sail2_foo to avoid conflict with sail1 in rmemJon French
2018-06-13Tracing instrumentation for C backendAlasdair Armstrong
2018-06-11Use riscv platform insns_per_tick to tick the clock.Prashanth Mundkur
2018-06-11Put the riscv model's output on stderr, leaving stdout for the platform termi...Prashanth Mundkur
2018-06-11Update retire semantics for riscv WFI.Prashanth Mundkur
2018-06-11Merge branch 'sail2' into mappingsJon French
2018-06-11change double-caret for string-append-pattern to single caret, since that wou...Jon French
2018-06-11drop now-unnecessary type annotation clutter from riscv decode mappingsJon French
2018-06-09Increment minstret on instruction retires, and handle the case when the minst...Prashanth Mundkur
2018-06-09Some fixes to counteren handling.Prashanth Mundkur
2018-06-08Fix mmio address matching for clint device.Prashanth Mundkur
2018-06-08Add counteren registers.Prashanth Mundkur
2018-06-08Slightly condense execution trace log.Prashanth Mundkur
2018-06-08Update initialization of misa.Prashanth Mundkur
2018-06-08Make the simulation loop use the platform interface to detect exits via htif.Prashanth Mundkur
2018-06-08Add mem and mmio access tracing.Prashanth Mundkur
2018-06-08type checking mappings: allow inferring based on the other side's id inferencesJon French
2018-06-07Slight refactor to keep platform handling localized to the _platform file.Prashanth Mundkur
2018-06-07Fix width guards on htif accesses.Prashanth Mundkur
2018-06-07Update physical memory and address translation for MMIO.Prashanth Mundkur
2018-06-07More definitions for the physical memory map.Prashanth Mundkur
2018-06-07Remove unused file.Prashanth Mundkur
2018-06-07Add terminal output to riscv platform, with incomplete handling of input.Prashanth Mundkur
2018-06-07Fix Lem build of RISC-VThomas Bauereiss
2018-06-04Add the htif exit command, a top-level function to initialize the riscv platf...Prashanth Mundkur
2018-06-04Uncomment the clint implementation in riscv_platform.Prashanth Mundkur
2018-05-31Fixes to get ARM u-boot working in Sail.Alasdair Armstrong
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