| Age | Commit message (Expand) | Author |
|---|
| 2018-05-03 | Fix a typo in sret decode and privilege checks in xret. | Prashanth Mundkur |
| 2018-05-03 | Add implementation of sfence with a fixme note. | Prashanth Mundkur |
| 2018-05-03 | Fix a bug in privilege transition, add better transition logging. | Prashanth Mundkur |
| 2018-05-03 | Implement wfi, and cleanup handling illegal operations. | Prashanth Mundkur |
| 2018-05-03 | Fix interrupt dispatch, improve execution logs, cleanup unused bits. | Prashanth Mundkur |
| 2018-05-03 | Simplify the top-level execute loop using the step function. | Prashanth Mundkur |
| 2018-05-03 | Fix up interrupt and exception dispatch. | Prashanth Mundkur |
| 2018-05-03 | Implement fetch to properly handle RVC and address translation, and add a ste... | Prashanth Mundkur |
| 2018-05-03 | Fix duopod with latest riscv prelude | Alasdair Armstrong |
| 2018-05-03 | Hook in address translation for stores and atomics. | Prashanth Mundkur |
| 2018-05-03 | Log csr writes in the execution log. | Prashanth Mundkur |
| 2018-05-02 | Hook in address translation for loads. | Prashanth Mundkur |
| 2018-05-02 | Finish up Sv39 address translation. | Prashanth Mundkur |
| 2018-05-02 | Tick cycle counter in execute loop. | Prashanth Mundkur |
| 2018-05-02 | Fix printing of csr immediates. | Prashanth Mundkur |
| 2018-05-02 | Fix typo in riscv model. | Prashanth Mundkur |
| 2018-04-26 | Add riscv SV39 page-table walk. | Prashanth Mundkur |
| 2018-04-26 | Ensure riscv interrupt delegation does not reduce current privilege. | Prashanth Mundkur |
| 2018-04-26 | Fix bug introduced in alignment check. | Prashanth Mundkur |
| 2018-04-26 | Initial support for faults of writes to physical addresses. | Prashanth Mundkur |
| 2018-04-26 | Initial support for faults of reads to physical addresses. | Prashanth Mundkur |
| 2018-04-23 | Make riscv build depend on Makefile updates. | Prashanth Mundkur |
| 2018-04-23 | Add riscv PTE definitions and access control checks. | Prashanth Mundkur |
| 2018-04-20 | Fix a typo. | Prashanth Mundkur |
| 2018-04-20 | Add a riscv instruction printer for the execution log. | Prashanth Mundkur |
| 2018-04-20 | Some cleanup and comments. | Prashanth Mundkur |
| 2018-04-20 | Have sign_extend in common Sail Lem library, use it and zero_extend in | Brian Campbell |
| 2018-04-18 | Remove obsolete comment. | Prashanth Mundkur |
| 2018-04-18 | Add interrupt prioritization and delegation. | Prashanth Mundkur |
| 2018-04-18 | Fix mideleg semantics after spec clarification from Andrew Waterman. | Prashanth Mundkur |
| 2018-04-18 | Use the generated num_of_E function for enum E instead of defining one by hand. | Prashanth Mundkur |
| 2018-04-18 | Move a few printing functions to sail_values.lem | Thomas Bauereiss |
| 2018-04-17 | Implement sret. | Prashanth Mundkur |
| 2018-04-17 | Hook in the delegated trap handler and remove the old one. | Prashanth Mundkur |
| 2018-04-17 | Add platform initialization for the new bits of machine state. | Prashanth Mundkur |
| 2018-04-17 | Separate out the trap handler, and make it use the delegatee privilege. | Prashanth Mundkur |
| 2018-04-17 | Define exception handler delegation. | Prashanth Mundkur |
| 2018-04-16 | Implement the s-mode views of mie/mip, and their legalizers. | Prashanth Mundkur |
| 2018-04-16 | Add the satp legalizer. | Prashanth Mundkur |
| 2018-04-13 | Add <=_u to riscv prelude. | Prashanth Mundkur |
| 2018-04-13 | Add some checks of current state, and use for the xepc write legalizer. | Prashanth Mundkur |
| 2018-04-13 | Some initial legalizers for writes to S-mode CSRs. | Prashanth Mundkur |
| 2018-04-13 | Define legalizers for writes to M-mode CSRs, and hook these writes to use them. | Prashanth Mundkur |
| 2018-04-13 | Move riscv memory definitions into a separate file. | Prashanth Mundkur |
| 2018-04-13 | Fix access checks to riscv CSRs. | Prashanth Mundkur |
| 2018-04-11 | Initial bits of supervisor state. | Prashanth Mundkur |
| 2018-04-11 | Add some misc informational m-mode registers that are used in a test. | Prashanth Mundkur |
| 2018-04-11 | More structured riscv trap vector handling. | Prashanth Mundkur |
| 2018-04-09 | Update riscv to use the new system definitions, remove duplicates. | Prashanth Mundkur |
| 2018-04-09 | Add some riscv arch definitions: privilege levels, exceptions, interrupts, ex... | Prashanth Mundkur |
