| Age | Commit message (Expand) | Author |
|---|
| 2018-07-09 | Log some timing info at the end of riscv execution. | Prashanth Mundkur |
| 2018-07-09 | add riscv_analysis.sail to SAIL_SRCS | Jon French |
| 2018-07-09 | add LOADRES, STORECON, AMO to analysis | Jon French |
| 2018-07-09 | Support writes to misa.C in riscv. | Prashanth Mundkur |
| 2018-07-08 | Make the riscv fetch-execute loop return instead of exiting when done. | Prashanth Mundkur |
| 2018-07-08 | Move the riscv analysis function into its own file for coverage purposes. | Prashanth Mundkur |
| 2018-07-08 | Add a riscv coverage target using bisect-ppx. | Prashanth Mundkur |
| 2018-07-07 | Add reservation traces to riscv tracecmp tool. | Prashanth Mundkur |
| 2018-07-07 | Cancel riscv reservation before i/o scheduling, tweak reservation tracing. | Prashanth Mundkur |
| 2018-07-07 | An initial fix to riscv lr/sc, needs a review. | Prashanth Mundkur |
| 2018-07-07 | Add some tracing to riscv address translation. | Prashanth Mundkur |
| 2018-07-05 | Fix printing of aq/rl flags in risc-v lr/sc. | Prashanth Mundkur |
| 2018-07-05 | support acquire/release loads/stores in RISCV initial_analysis | Jon French |
| 2018-07-05 | print to stdout not stderr to stop upsetting rmem regression tests | Jon French |
| 2018-07-05 | restore missing RISC-V fence types in sail2; ignore io bits in fences more cl... | Jon French |
| 2018-07-03 | Add htif tohost to the riscv tracecmp tool. | Prashanth Mundkur |
| 2018-07-03 | Allow the riscv htif_tohost mmio port to be readable, and ack writes to that ... | Prashanth Mundkur |
| 2018-06-28 | further changes to support rmem | Jon French |
| 2018-06-26 | Fix duplicate riscv mem-ea, spotted by Jon French. | Prashanth Mundkur |
| 2018-06-25 | Add a riscv platform parameter to control trapping to M-mode on misaligned ac... | Prashanth Mundkur |
| 2018-06-25 | Increment the riscv trace step counter only when instructions are executed. | Prashanth Mundkur |
| 2018-06-25 | Hook in the missed misa legalizer. | Prashanth Mundkur |
| 2018-06-25 | Fix riscv interrupt pending check to handle implicit enabling at lower privil... | Prashanth Mundkur |
| 2018-06-25 | Make sstatus.UXL legalization match spike for now. Leave a fixme to make this... | Prashanth Mundkur |
| 2018-06-25 | Fix a missed fixme for the sstatus view of mstatus. | Prashanth Mundkur |
| 2018-06-25 | Fix tracecmp for spike's recursive calls for sie/sip/sstatus csr writes. | Prashanth Mundkur |
| 2018-06-25 | Support bitlist representation in Sail2_string | Thomas Bauereiss |
| 2018-06-23 | Add clock tick checks to the riscv tracecmp tool. | Prashanth Mundkur |
| 2018-06-23 | Fix a missing check for interrupt dispatch when riscv clint registers are wri... | Prashanth Mundkur |
| 2018-06-22 | Make riscv pte dirty-bit update handling configurable via a platform cli option. | Prashanth Mundkur |
| 2018-06-22 | Some more riscv trace log tweaking for spike compatibility. | Prashanth Mundkur |
| 2018-06-22 | Add cli options to riscv simulator to dump platform device-tree info. | Prashanth Mundkur |
| 2018-06-22 | Add a simple trace log comparison tool for riscv vs. a patched spike. | Prashanth Mundkur |
| 2018-06-22 | More trace log tweaks. | Prashanth Mundkur |
| 2018-06-21 | Merge branch 'sail2' of github.com:rems-project/sail into sail2 | Alasdair Armstrong |
| 2018-06-21 | add PMP registers to CSR, fix build | Jon French |
| 2018-06-21 | Merge branch 'tracing' into sail2 | Alasdair Armstrong |
| 2018-06-21 | changes to riscv model to support rmem | Jon French |
| 2018-06-19 | Add more detail to riscv execution trace log. | Prashanth Mundkur |
| 2018-06-15 | Fix riscv system register initialization. | Prashanth Mundkur |
| 2018-06-14 | rename all lem support files to sail2_foo to avoid conflict with sail1 in rmem | Jon French |
| 2018-06-13 | Tracing instrumentation for C backend | Alasdair Armstrong |
| 2018-06-11 | Use riscv platform insns_per_tick to tick the clock. | Prashanth Mundkur |
| 2018-06-11 | Put the riscv model's output on stderr, leaving stdout for the platform termi... | Prashanth Mundkur |
| 2018-06-11 | Update retire semantics for riscv WFI. | Prashanth Mundkur |
| 2018-06-11 | Merge branch 'sail2' into mappings | Jon French |
| 2018-06-11 | change double-caret for string-append-pattern to single caret, since that wou... | Jon French |
| 2018-06-11 | drop now-unnecessary type annotation clutter from riscv decode mappings | Jon French |
| 2018-06-09 | Increment minstret on instruction retires, and handle the case when the minst... | Prashanth Mundkur |
| 2018-06-09 | Some fixes to counteren handling. | Prashanth Mundkur |
