sail - Formal specification language for ISAs

Age	Commit message (Expand)	Author
2018-04-13	Move riscv memory definitions into a separate file.	Prashanth Mundkur
2018-04-13	Fix access checks to riscv CSRs.	Prashanth Mundkur
2018-04-11	Initial bits of supervisor state.	Prashanth Mundkur
2018-04-11	Add some misc informational m-mode registers that are used in a test.	Prashanth Mundkur
2018-04-11	More structured riscv trap vector handling.	Prashanth Mundkur
2018-04-09	Update riscv to use the new system definitions, remove duplicates.	Prashanth Mundkur
2018-04-09	Add some riscv arch definitions: privilege levels, exceptions, interrupts, ex...	Prashanth Mundkur
2018-04-09	Slightly re-org defs to move related things closer together.	Prashanth Mundkur
2018-04-09	Better separate riscv-independent and riscv-specific parts between prelude an...	Prashanth Mundkur
2018-03-21	Patch AST datatypes in generated Isabelle theories	Thomas Bauereiss
2018-03-19	Fixes to C backend for RISCV-compilation	Alasdair Armstrong
2018-03-14	WIP Latex formatting	Alasdair Armstrong
2018-03-14	Fix toplevel pattern compilation	Alasdair Armstrong
2018-03-14	Make partiality more explicit in library functions of Lem shallow embedding	Thomas Bauereiss
2018-03-09	Specialise constructors for polymorphic unions	Alasdair Armstrong
2018-03-07	Make union types consistent in the AST	Alasdair Armstrong
2018-02-15	Rebase state monad onto prompt monad	Thomas Bauereiss
2018-02-15	Re-engineer prompt monad of Lem shallow embedding	Thomas Bauereiss
2018-02-07	Add some printing functions to Lem shallow embedding	Thomas Bauereiss
2018-02-06	Fixed some bugs in the RVC spec; the rvc test now passes.	Prashanth Mundkur
2018-02-06	Add a system initialization function. For now, it merely initializes support...	Prashanth Mundkur
2018-02-06	some prettyfying of riscv: replace regbits/bits(64) with xlenbits and use ove...	Robert Norton
2018-02-06	Add remaining RVC instructions.	Prashanth Mundkur
2018-02-06	Make small change to improve readability of riscv duopod	Alasdair Armstrong
2018-02-05	riscv: slightly prettier register trace output	Robert Norton
2018-02-05	squash a warning.	Robert Norton
2018-02-02	Added remaining compressed instructions in Quadrant 0 and 1, Quadrant 2 remains.	Prashanth Mundkur
2018-02-02	Add M extension to RISCV. Slightly inelegant implementation for now but passi...	Robert Norton
2018-02-02	Add some more compressed instruction specs, and slightly clean up previous ones.	Prashanth Mundkur
2018-02-01	Use the recursive execute for c.addi4spn.	Prashanth Mundkur
2018-02-01	badaddr is a misleading name, since it could contain what the PC points to fo...	Prashanth Mundkur
2018-02-01	riscv: avoid name clash with global function 'unsigned'.	Robert Norton
2018-02-01	Clean up riscv_duopod sail and add make targets for ocaml and Isabelle.	Robert Norton
2018-02-01	Add c.addi4spn.	Prashanth Mundkur
2018-02-01	Fix encoding for compressed ILLEGAL.	Prashanth Mundkur
2018-02-01	Initial top-level support for compression instructions.	Prashanth Mundkur
2018-01-31	Add wrappers around Lem operators using bitvector type class	Thomas Bauereiss
2018-01-31	Split base definitions of Lem monads and further built-ins (e.g. loop combina...	Thomas Bauereiss
2018-01-31	add very stripped down 2-instruction RISCV example with add and load.	Robert Norton
2018-01-30	Fix failing Lem tests	Alasdair Armstrong
2018-01-30	riscv prelude: add a to_bits function for converting ints to bits of given le...	Robert Norton
2018-01-29	Fix Lem generation for RISC-V	Thomas Bauereiss
2018-01-29	Add a fixme for unhandled fences but allow them to execute.	Prashanth Mundkur
2018-01-29	Initial handling of CSR reads/writes.	Prashanth Mundkur
2018-01-29	Add satp to CSR dummy implemented predicate. Also direct the illegal instruc...	Prashanth Mundkur
2018-01-29	riscv: fix warnings about incomplete patterns. Add a check target in Makefile...	Robert Norton
2018-01-29	Add some initial exception handling to the riscv execution loop.	Prashanth Mundkur
2018-01-29	Merge branch 'sail2' of https://bitbucket.org/Peter_Sewell/sail into sail2	Robert Norton
2018-01-29	riscv: remove break from main loop and place val spec in prelude.	Robert Norton
2018-01-29	riscv: add tracing of register writes.	Robert Norton