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AgeCommit message (Expand)Author
2018-08-31riscv prelude: yet more manual monomorphisations for hex_bitsJon French
2018-08-30Annotate the RISC-V prelude for C builtins.Prashanth Mundkur
2018-08-30Add a C header containing declarations needed by RISC-V.Prashanth Mundkur
2018-08-29C: Fix some issues with tuples as arguments to polymorphic constructorsAlasdair Armstrong
2018-08-29Updated snapshots for Isabelle 2018Thomas Bauereiss
2018-08-28Adapt theory imports for Isabelle 2018Thomas Bauereiss
2018-08-28fix bug in RISCV assembly mapping, incorrect order of FENCE pred/succ bitsJon French
2018-08-16Add the type an expression was checked against to tannots, and use for CoqBrian Campbell
2018-08-15Temporary fix for RISC-V Lem generationBrian Campbell
2018-08-15Get RISC-V on Coq into reasonable state to showBrian Campbell
2018-08-13More RISC-V built-in type constraintsBrian Campbell
2018-08-13Coq: more strings for RISC-VBrian Campbell
2018-08-13Add constraints to RISC-V duopod, makefile rulesBrian Campbell
2018-08-13RISC-V: mult_range is ill-typed, use mult_atom insteadBrian Campbell
2018-08-13Basic Coq support for RISC-VBrian Campbell
2018-07-27Add some missing rv64i instructions, discovered when annotating the riscv isa...Prashanth Mundkur
2018-07-27Add a riscv latex target.Prashanth Mundkur
2018-07-20Add assorted comments, consistency fixes and cleanup.Prashanth Mundkur
2018-07-12Fixed a nested comment issueShaked Flur
2018-07-11Add fixme note about riscv jalr.Prashanth Mundkur
2018-07-11Update the exception code for riscv LR after clarification on isa-dev.Prashanth Mundkur
2018-07-11RISC-V model fixes for RMEMJon French
2018-07-11Fix riscv_duopod build.Robert Norton
2018-07-10Add an option to specify the dtc to use for the riscv platform.Prashanth Mundkur
2018-07-10Turn off some riscv debug tracing.Prashanth Mundkur
2018-07-10Start adding c-backend bits for riscv.Prashanth Mundkur
2018-07-10Support riscv atomic accesses to mmio regions, used by linux to access device...Prashanth Mundkur
2018-07-10Make HOL build properly again for all of the modelsBrian Campbell
2018-07-10RISCV load-acquire in Lem (-> rmem)Jon French
2018-07-10correct pretty-printing using mappingsJon French
2018-07-10disable printing when compiling to Lem to keep rmem happyJon French
2018-07-09Log some timing info at the end of riscv execution.Prashanth Mundkur
2018-07-09add riscv_analysis.sail to SAIL_SRCSJon French
2018-07-09add LOADRES, STORECON, AMO to analysisJon French
2018-07-09Support writes to misa.C in riscv.Prashanth Mundkur
2018-07-08Make the riscv fetch-execute loop return instead of exiting when done.Prashanth Mundkur
2018-07-08Move the riscv analysis function into its own file for coverage purposes.Prashanth Mundkur
2018-07-08Add a riscv coverage target using bisect-ppx.Prashanth Mundkur
2018-07-07Add reservation traces to riscv tracecmp tool.Prashanth Mundkur
2018-07-07Cancel riscv reservation before i/o scheduling, tweak reservation tracing.Prashanth Mundkur
2018-07-07An initial fix to riscv lr/sc, needs a review.Prashanth Mundkur
2018-07-07Add some tracing to riscv address translation.Prashanth Mundkur
2018-07-05Fix printing of aq/rl flags in risc-v lr/sc.Prashanth Mundkur
2018-07-05support acquire/release loads/stores in RISCV initial_analysisJon French
2018-07-05print to stdout not stderr to stop upsetting rmem regression testsJon French
2018-07-05restore missing RISC-V fence types in sail2; ignore io bits in fences more cl...Jon French
2018-07-03Add htif tohost to the riscv tracecmp tool.Prashanth Mundkur
2018-07-03Allow the riscv htif_tohost mmio port to be readable, and ack writes to that ...Prashanth Mundkur
2018-06-28further changes to support rmemJon French
2018-06-26Fix duplicate riscv mem-ea, spotted by Jon French.Prashanth Mundkur