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AgeCommit message (Expand)Author
2018-06-21Merge branch 'sail2' of github.com:rems-project/sail into sail2Alasdair Armstrong
2018-06-21add PMP registers to CSR, fix buildJon French
2018-06-21Merge branch 'tracing' into sail2Alasdair Armstrong
2018-06-21changes to riscv model to support rmemJon French
2018-06-19Add more detail to riscv execution trace log.Prashanth Mundkur
2018-06-15Fix riscv system register initialization.Prashanth Mundkur
2018-06-14rename all lem support files to sail2_foo to avoid conflict with sail1 in rmemJon French
2018-06-13Tracing instrumentation for C backendAlasdair Armstrong
2018-06-11Use riscv platform insns_per_tick to tick the clock.Prashanth Mundkur
2018-06-11Put the riscv model's output on stderr, leaving stdout for the platform termi...Prashanth Mundkur
2018-06-11Update retire semantics for riscv WFI.Prashanth Mundkur
2018-06-11Merge branch 'sail2' into mappingsJon French
2018-06-11change double-caret for string-append-pattern to single caret, since that wou...Jon French
2018-06-11drop now-unnecessary type annotation clutter from riscv decode mappingsJon French
2018-06-09Increment minstret on instruction retires, and handle the case when the minst...Prashanth Mundkur
2018-06-09Some fixes to counteren handling.Prashanth Mundkur
2018-06-08Fix mmio address matching for clint device.Prashanth Mundkur
2018-06-08Add counteren registers.Prashanth Mundkur
2018-06-08Slightly condense execution trace log.Prashanth Mundkur
2018-06-08Update initialization of misa.Prashanth Mundkur
2018-06-08Make the simulation loop use the platform interface to detect exits via htif.Prashanth Mundkur
2018-06-08Add mem and mmio access tracing.Prashanth Mundkur
2018-06-08type checking mappings: allow inferring based on the other side's id inferencesJon French
2018-06-07Slight refactor to keep platform handling localized to the _platform file.Prashanth Mundkur
2018-06-07Fix width guards on htif accesses.Prashanth Mundkur
2018-06-07Update physical memory and address translation for MMIO.Prashanth Mundkur
2018-06-07More definitions for the physical memory map.Prashanth Mundkur
2018-06-07Remove unused file.Prashanth Mundkur
2018-06-07Add terminal output to riscv platform, with incomplete handling of input.Prashanth Mundkur
2018-06-07Fix Lem build of RISC-VThomas Bauereiss
2018-06-04Add the htif exit command, a top-level function to initialize the riscv platf...Prashanth Mundkur
2018-06-04Uncomment the clint implementation in riscv_platform.Prashanth Mundkur
2018-05-31Fixes to get ARM u-boot working in Sail.Alasdair Armstrong
2018-05-23Fix incorrect channel in dtc i/o.Prashanth Mundkur
2018-05-23riscv decode now uses mapping-decode and passes testsJon French
2018-05-23restore original riscv mainJon French
2018-05-23Fix riscv build for older versions of ocamlbuild (e.g. 4.02.3) by copying pla...Robert Norton
2018-05-22Re-enable the RISC-V lem build, and switch the test-suite to use the platform...Prashanth Mundkur
2018-05-22Fix for E_cons not being compiled correctly into OCamlAlasdair Armstrong
2018-05-22Fix Lem build for RISC-VThomas Bauereiss
2018-05-21Add the missed _tags file, and fix a typo.Prashanth Mundkur
2018-05-21Start platform execution at the reset-vector in the rom.Prashanth Mundkur
2018-05-21Add in the platform files and update the ocaml build. Disable the isabelle b...Prashanth Mundkur
2018-05-21Move the top-level loop from main to riscv_step, but remove elf bits.Prashanth Mundkur
2018-05-21Move mem-op-result to _sys to be usable from _platform.Prashanth Mundkur
2018-05-21further RISCV mapping: all extant non-compressed instructions doneJon French
2018-05-18more riscv mappingJon French
2018-05-18more riscv mappings; riscv now builds successfully to lem which builds to isa...Jon French
2018-05-17Merge branch 'cheri-mono' into sail2Brian Campbell
2018-05-17Tidy up HOL4 riscv a littleBrian Campbell
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