| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-12-20 | RISVC model is now at https://github.com/rems-project/sail-riscv . Remove it ↵ | Robert Norton | |
| and tests. | |||
| 2018-11-29 | RISC-V: factor the execution trace. | Prashanth Mundkur | |
| This is now split into instructions, regs, memory and platform, each controlled individually. Currently all are enabled and not connected to any command-line options, so a recompile is needed for trace tuning. | |||
| 2018-11-29 | RISC-V: properly set mstatus.FS in absence of floating-point support. | Prashanth Mundkur | |
| 2018-11-12 | Add RVFI DII version of the RISC-V simulator for TestRIG | Brian Campbell | |
| The new riscv_rvfi target should still be usable as a normal simulator, but also has extra registers in the model for the RVFI DII protocol and code to update them, and the driver has a -r option to enable RVFI mode. | |||
| 2018-10-23 | RISC-V: Add a platform knob to control mtval contents on illegal instruction ↵ | Prashanth Mundkur | |
| faults. | |||
| 2018-10-23 | RISC-V: fix: sstatus.SD depends on .XS and .FS. | Prashanth Mundkur | |
| 2018-09-04 | C: Tweaks to RISC-V to get compiling to C | Alasdair Armstrong | |
| Revert a change to string_of_bits because it broke all the RISC-V tests in OCaml. string_of_int (int_of_string x) is not valid because x may not fit within an integer. | |||
| 2018-08-31 | Some C stubs for platform bits for RISC-V. | Prashanth Mundkur | |
| 2018-07-20 | Add assorted comments, consistency fixes and cleanup. | Prashanth Mundkur | |
| 2018-07-10 | correct pretty-printing using mappings | Jon French | |
| 2018-07-09 | Support writes to misa.C in riscv. | Prashanth Mundkur | |
| 2018-07-07 | Cancel riscv reservation before i/o scheduling, tweak reservation tracing. | Prashanth Mundkur | |
| 2018-07-07 | An initial fix to riscv lr/sc, needs a review. | Prashanth Mundkur | |
| This uses a stronger model than the version in Sail-1 in order to perform address alignment checks. The reservation is kept on virtual addresses, and maintained in the platform model, but now the lr/sc definitions need calls to externs to update this state. An alternative was to reserve physical addresses, but that appeared to be more complicated without a lot more changes. Ideally, the model should be parameterizable over both options. | |||
| 2018-06-25 | Fix riscv interrupt pending check to handle implicit enabling at lower ↵ | Prashanth Mundkur | |
| privileges. Also fix timer threshold comparison to be <= instead of <. | |||
| 2018-06-25 | Make sstatus.UXL legalization match spike for now. Leave a fixme to make ↵ | Prashanth Mundkur | |
| this a platform setting. | |||
| 2018-06-22 | Some more riscv trace log tweaking for spike compatibility. | Prashanth Mundkur | |
| 2018-06-22 | More trace log tweaks. | Prashanth Mundkur | |
| 2018-06-21 | add PMP registers to CSR, fix build | Jon French | |
| 2018-06-19 | Add more detail to riscv execution trace log. | Prashanth Mundkur | |
| 2018-06-15 | Fix riscv system register initialization. | Prashanth Mundkur | |
| 2018-06-11 | Use riscv platform insns_per_tick to tick the clock. | Prashanth Mundkur | |
| 2018-06-11 | Merge branch 'sail2' into mappings | Jon French | |
| (involved some manual tinkering with gitignore, type_check, riscv) | |||
| 2018-06-09 | Increment minstret on instruction retires, and handle the case when the ↵ | Prashanth Mundkur | |
| minstret CSR is explicitly written to. | |||
| 2018-06-09 | Some fixes to counteren handling. | Prashanth Mundkur | |
| 2018-06-08 | Add counteren registers. | Prashanth Mundkur | |
| 2018-06-08 | Update initialization of misa. | Prashanth Mundkur | |
| 2018-05-21 | Move mem-op-result to _sys to be usable from _platform. | Prashanth Mundkur | |
| 2018-05-21 | further RISCV mapping: all extant non-compressed instructions done | Jon French | |
| 2018-05-07 | Add a register indicating no trigger/breakpoint support, which allows the ↵ | Prashanth Mundkur | |
| breakpoint test to pass. | |||
| 2018-05-07 | Log trap value on traps. | Prashanth Mundkur | |
| 2018-05-03 | Fix a bug in privilege transition, add better transition logging. | Prashanth Mundkur | |
| 2018-05-03 | Implement wfi, and cleanup handling illegal operations. | Prashanth Mundkur | |
| 2018-05-03 | Fix interrupt dispatch, improve execution logs, cleanup unused bits. | Prashanth Mundkur | |
| 2018-05-03 | Fix up interrupt and exception dispatch. | Prashanth Mundkur | |
| 2018-05-03 | Implement fetch to properly handle RVC and address translation, and add a ↵ | Prashanth Mundkur | |
| step function for execution. | |||
| 2018-05-02 | Finish up Sv39 address translation. | Prashanth Mundkur | |
| 2018-05-02 | Tick cycle counter in execute loop. | Prashanth Mundkur | |
| 2018-04-26 | Ensure riscv interrupt delegation does not reduce current privilege. | Prashanth Mundkur | |
| 2018-04-26 | Initial support for faults of writes to physical addresses. | Prashanth Mundkur | |
| 2018-04-26 | Initial support for faults of reads to physical addresses. | Prashanth Mundkur | |
| 2018-04-20 | Add a riscv instruction printer for the execution log. | Prashanth Mundkur | |
| 2018-04-20 | Some cleanup and comments. | Prashanth Mundkur | |
| 2018-04-18 | Remove obsolete comment. | Prashanth Mundkur | |
| 2018-04-18 | Add interrupt prioritization and delegation. | Prashanth Mundkur | |
| 2018-04-18 | Fix mideleg semantics after spec clarification from Andrew Waterman. | Prashanth Mundkur | |
| 2018-04-18 | Use the generated num_of_E function for enum E instead of defining one by hand. | Prashanth Mundkur | |
| 2018-04-17 | Implement sret. | Prashanth Mundkur | |
| 2018-04-17 | Hook in the delegated trap handler and remove the old one. | Prashanth Mundkur | |
| 2018-04-17 | Add platform initialization for the new bits of machine state. | Prashanth Mundkur | |
| 2018-04-17 | Separate out the trap handler, and make it use the delegatee privilege. | Prashanth Mundkur | |
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index : sail | |
| Formal specification language for ISAs |
| summaryrefslogtreecommitdiff |