sail - Formal specification language for ISAs

Age	Commit message (Expand)	Author
2018-04-17	Define exception handler delegation.	Prashanth Mundkur
2018-04-16	Implement the s-mode views of mie/mip, and their legalizers.	Prashanth Mundkur
2018-04-16	Add the satp legalizer.	Prashanth Mundkur
2018-04-13	Add some checks of current state, and use for the xepc write legalizer.	Prashanth Mundkur
2018-04-13	Some initial legalizers for writes to S-mode CSRs.	Prashanth Mundkur
2018-04-13	Define legalizers for writes to M-mode CSRs, and hook these writes to use them.	Prashanth Mundkur
2018-04-13	Fix access checks to riscv CSRs.	Prashanth Mundkur
2018-04-11	Initial bits of supervisor state.	Prashanth Mundkur
2018-04-11	Add some misc informational m-mode registers that are used in a test.	Prashanth Mundkur
2018-04-11	More structured riscv trap vector handling.	Prashanth Mundkur
2018-04-09	Update riscv to use the new system definitions, remove duplicates.	Prashanth Mundkur
2018-03-07	Make union types consistent in the AST	Alasdair Armstrong
2018-02-06	Add a system initialization function. For now, it merely initializes support...	Prashanth Mundkur
2018-02-06	some prettyfying of riscv: replace regbits/bits(64) with xlenbits and use ove...	Robert Norton
2018-02-05	squash a warning.	Robert Norton
2018-02-01	badaddr is a misleading name, since it could contain what the PC points to fo...	Prashanth Mundkur
2018-02-01	Initial top-level support for compression instructions.	Prashanth Mundkur
2018-01-29	Initial handling of CSR reads/writes.	Prashanth Mundkur
2018-01-29	Added ecall/mret and exception support.	Prashanth Mundkur