| Age | Commit message (Expand) | Author |
|---|
| 2018-06-19 | Add more detail to riscv execution trace log. | Prashanth Mundkur |
| 2018-06-15 | Fix riscv system register initialization. | Prashanth Mundkur |
| 2018-06-11 | Use riscv platform insns_per_tick to tick the clock. | Prashanth Mundkur |
| 2018-06-11 | Merge branch 'sail2' into mappings | Jon French |
| 2018-06-09 | Increment minstret on instruction retires, and handle the case when the minst... | Prashanth Mundkur |
| 2018-06-09 | Some fixes to counteren handling. | Prashanth Mundkur |
| 2018-06-08 | Add counteren registers. | Prashanth Mundkur |
| 2018-06-08 | Update initialization of misa. | Prashanth Mundkur |
| 2018-05-21 | Move mem-op-result to _sys to be usable from _platform. | Prashanth Mundkur |
| 2018-05-21 | further RISCV mapping: all extant non-compressed instructions done | Jon French |
| 2018-05-07 | Add a register indicating no trigger/breakpoint support, which allows the bre... | Prashanth Mundkur |
| 2018-05-07 | Log trap value on traps. | Prashanth Mundkur |
| 2018-05-03 | Fix a bug in privilege transition, add better transition logging. | Prashanth Mundkur |
| 2018-05-03 | Implement wfi, and cleanup handling illegal operations. | Prashanth Mundkur |
| 2018-05-03 | Fix interrupt dispatch, improve execution logs, cleanup unused bits. | Prashanth Mundkur |
| 2018-05-03 | Fix up interrupt and exception dispatch. | Prashanth Mundkur |
| 2018-05-03 | Implement fetch to properly handle RVC and address translation, and add a ste... | Prashanth Mundkur |
| 2018-05-02 | Finish up Sv39 address translation. | Prashanth Mundkur |
| 2018-05-02 | Tick cycle counter in execute loop. | Prashanth Mundkur |
| 2018-04-26 | Ensure riscv interrupt delegation does not reduce current privilege. | Prashanth Mundkur |
| 2018-04-26 | Initial support for faults of writes to physical addresses. | Prashanth Mundkur |
| 2018-04-26 | Initial support for faults of reads to physical addresses. | Prashanth Mundkur |
| 2018-04-20 | Add a riscv instruction printer for the execution log. | Prashanth Mundkur |
| 2018-04-20 | Some cleanup and comments. | Prashanth Mundkur |
| 2018-04-18 | Remove obsolete comment. | Prashanth Mundkur |
| 2018-04-18 | Add interrupt prioritization and delegation. | Prashanth Mundkur |
| 2018-04-18 | Fix mideleg semantics after spec clarification from Andrew Waterman. | Prashanth Mundkur |
| 2018-04-18 | Use the generated num_of_E function for enum E instead of defining one by hand. | Prashanth Mundkur |
| 2018-04-17 | Implement sret. | Prashanth Mundkur |
| 2018-04-17 | Hook in the delegated trap handler and remove the old one. | Prashanth Mundkur |
| 2018-04-17 | Add platform initialization for the new bits of machine state. | Prashanth Mundkur |
| 2018-04-17 | Separate out the trap handler, and make it use the delegatee privilege. | Prashanth Mundkur |
| 2018-04-17 | Define exception handler delegation. | Prashanth Mundkur |
| 2018-04-16 | Implement the s-mode views of mie/mip, and their legalizers. | Prashanth Mundkur |
| 2018-04-16 | Add the satp legalizer. | Prashanth Mundkur |
| 2018-04-13 | Add some checks of current state, and use for the xepc write legalizer. | Prashanth Mundkur |
| 2018-04-13 | Some initial legalizers for writes to S-mode CSRs. | Prashanth Mundkur |
| 2018-04-13 | Define legalizers for writes to M-mode CSRs, and hook these writes to use them. | Prashanth Mundkur |
| 2018-04-13 | Fix access checks to riscv CSRs. | Prashanth Mundkur |
| 2018-04-11 | Initial bits of supervisor state. | Prashanth Mundkur |
| 2018-04-11 | Add some misc informational m-mode registers that are used in a test. | Prashanth Mundkur |
| 2018-04-11 | More structured riscv trap vector handling. | Prashanth Mundkur |
| 2018-04-09 | Update riscv to use the new system definitions, remove duplicates. | Prashanth Mundkur |
| 2018-03-07 | Make union types consistent in the AST | Alasdair Armstrong |
| 2018-02-06 | Add a system initialization function. For now, it merely initializes support... | Prashanth Mundkur |
| 2018-02-06 | some prettyfying of riscv: replace regbits/bits(64) with xlenbits and use ove... | Robert Norton |
| 2018-02-05 | squash a warning. | Robert Norton |
| 2018-02-01 | badaddr is a misleading name, since it could contain what the PC points to fo... | Prashanth Mundkur |
| 2018-02-01 | Initial top-level support for compression instructions. | Prashanth Mundkur |
| 2018-01-29 | Initial handling of CSR reads/writes. | Prashanth Mundkur |
